LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/ARM - ARMGenGlobalISel.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 142 195 72.8 %
Date: 2017-09-14 15:23:50 Functions: 4 37 10.8 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Global Instruction Selector for the ARM target                             *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : #ifdef GET_GLOBALISEL_PREDICATE_BITSET
      10             : const unsigned MAX_SUBTARGET_PREDICATES = 61;
      11             : using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
      12             : #endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
      13             : 
      14             : #ifdef GET_GLOBALISEL_TEMPORARIES_DECL
      15             :   mutable MatcherState State;
      16             :   typedef ComplexRendererFn(ARMInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
      17             : const MatcherInfoTy<PredicateBitset, ComplexMatcherMemFn> MatcherInfo;
      18             : #endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
      19             : 
      20             : #ifdef GET_GLOBALISEL_TEMPORARIES_INIT
      21             : , State(0),
      22             : MatcherInfo({TypeObjects, FeatureBitsets, ImmPredicateFns, {
      23             :   nullptr, // GICP_Invalid
      24       26922 : }})
      25             : #endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
      26             : 
      27             : #ifdef GET_GLOBALISEL_IMPL
      28             : // Bits for subtarget features that participate in instruction matching.
      29             : enum SubtargetFeatureBits : uint8_t {
      30             :   Feature_NoHonorSignDependentRoundingBit = 54,
      31             :   Feature_HasV4TBit = 6,
      32             :   Feature_NoV4TBit = 7,
      33             :   Feature_HasV5TBit = 8,
      34             :   Feature_HasV5TEBit = 12,
      35             :   Feature_HasV6Bit = 1,
      36             :   Feature_NoV6Bit = 10,
      37             :   Feature_HasV6MBit = 28,
      38             :   Feature_HasV8MBaselineBit = 32,
      39             :   Feature_HasV6T2Bit = 9,
      40             :   Feature_HasV6KBit = 19,
      41             :   Feature_HasV7Bit = 2,
      42             :   Feature_HasV8Bit = 14,
      43             :   Feature_PreV8Bit = 20,
      44             :   Feature_HasV8_1aBit = 56,
      45             :   Feature_NoVFPBit = 23,
      46             :   Feature_HasVFP2Bit = 22,
      47             :   Feature_HasVFP3Bit = 44,
      48             :   Feature_HasVFP4Bit = 42,
      49             :   Feature_HasDPVFPBit = 36,
      50             :   Feature_HasFPARMv8Bit = 38,
      51             :   Feature_HasNEONBit = 45,
      52             :   Feature_HasCryptoBit = 47,
      53             :   Feature_HasCRCBit = 15,
      54             :   Feature_HasFP16Bit = 51,
      55             :   Feature_HasFullFP16Bit = 46,
      56             :   Feature_HasDivideInThumbBit = 34,
      57             :   Feature_HasDivideInARMBit = 13,
      58             :   Feature_HasDSPBit = 33,
      59             :   Feature_HasDBBit = 16,
      60             :   Feature_HasV7ClrexBit = 18,
      61             :   Feature_HasAcquireReleaseBit = 17,
      62             :   Feature_HasMPBit = 3,
      63             :   Feature_HasZCZBit = 48,
      64             :   Feature_UseNEONForFPBit = 59,
      65             :   Feature_DontUseNEONForFPBit = 37,
      66             :   Feature_IsThumbBit = 26,
      67             :   Feature_IsThumb1OnlyBit = 27,
      68             :   Feature_IsThumb2Bit = 31,
      69             :   Feature_IsNotMClassBit = 35,
      70             :   Feature_IsARMBit = 0,
      71             :   Feature_IsWindowsBit = 29,
      72             :   Feature_IsNotWindowsBit = 30,
      73             :   Feature_IsReadTPHardBit = 52,
      74             :   Feature_IsReadTPSoftBit = 21,
      75             :   Feature_UseNaClTrapBit = 4,
      76             :   Feature_DontUseNaClTrapBit = 5,
      77             :   Feature_UseMovtBit = 25,
      78             :   Feature_DontUseMovtBit = 24,
      79             :   Feature_UseFPVMLxBit = 40,
      80             :   Feature_UseMulOpsBit = 11,
      81             :   Feature_UseFusedMACBit = 43,
      82             :   Feature_DontUseFusedMACBit = 41,
      83             :   Feature_HasFastVGETLNi32Bit = 49,
      84             :   Feature_HasSlowVGETLNi32Bit = 57,
      85             :   Feature_HasFastVDUP32Bit = 50,
      86             :   Feature_HasSlowVDUP32Bit = 58,
      87             :   Feature_UseVMOVSRBit = 39,
      88             :   Feature_DontUseVMOVSRBit = 60,
      89             :   Feature_IsLEBit = 53,
      90             :   Feature_IsBEBit = 55,
      91             : };
      92             : 
      93        4487 : PredicateBitset ARMInstructionSelector::
      94             : computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const {
      95        4487 :   PredicateBitset Features;
      96        4487 :   if (!TM.Options.HonorSignDependentRoundingFPMath())
      97        8834 :     Features[Feature_NoHonorSignDependentRoundingBit] = 1;
      98        4487 :   if (Subtarget->hasV4TOps())
      99        7046 :     Features[Feature_HasV4TBit] = 1;
     100        4487 :   if (!Subtarget->hasV4TOps())
     101        1928 :     Features[Feature_NoV4TBit] = 1;
     102        4487 :   if (Subtarget->hasV5TOps())
     103        6604 :     Features[Feature_HasV5TBit] = 1;
     104        4487 :   if (Subtarget->hasV5TEOps())
     105        6530 :     Features[Feature_HasV5TEBit] = 1;
     106        4487 :   if (Subtarget->hasV6Ops())
     107        6468 :     Features[Feature_HasV6Bit] = 1;
     108        4487 :   if (!Subtarget->hasV6Ops())
     109        2506 :     Features[Feature_NoV6Bit] = 1;
     110        4487 :   if (Subtarget->hasV6MOps())
     111        5964 :     Features[Feature_HasV6MBit] = 1;
     112        4487 :   if (Subtarget->hasV8MBaselineOps())
     113        5644 :     Features[Feature_HasV8MBaselineBit] = 1;
     114        4487 :   if (Subtarget->hasV6T2Ops())
     115        5556 :     Features[Feature_HasV6T2Bit] = 1;
     116        4487 :   if (Subtarget->hasV6KOps())
     117        5604 :     Features[Feature_HasV6KBit] = 1;
     118        4487 :   if (Subtarget->hasV7Ops())
     119        5126 :     Features[Feature_HasV7Bit] = 1;
     120        4487 :   if (Subtarget->hasV8Ops())
     121         498 :     Features[Feature_HasV8Bit] = 1;
     122        4487 :   if (!Subtarget->hasV8Ops())
     123        8476 :     Features[Feature_PreV8Bit] = 1;
     124        4487 :   if (Subtarget->hasV8_1aOps())
     125          28 :     Features[Feature_HasV8_1aBit] = 1;
     126        4487 :   if (!Subtarget->hasVFP2())
     127        3568 :     Features[Feature_NoVFPBit] = 1;
     128        4487 :   if (Subtarget->hasVFP2())
     129        5406 :     Features[Feature_HasVFP2Bit] = 1;
     130        4487 :   if (Subtarget->hasVFP3())
     131        5102 :     Features[Feature_HasVFP3Bit] = 1;
     132        4487 :   if (Subtarget->hasVFP4())
     133        1294 :     Features[Feature_HasVFP4Bit] = 1;
     134        4487 :   if (!Subtarget->isFPOnlySP())
     135        8802 :     Features[Feature_HasDPVFPBit] = 1;
     136        4487 :   if (Subtarget->hasFPARMv8())
     137         598 :     Features[Feature_HasFPARMv8Bit] = 1;
     138        4487 :   if (Subtarget->hasNEON())
     139        4720 :     Features[Feature_HasNEONBit] = 1;
     140        4487 :   if (Subtarget->hasCrypto())
     141         468 :     Features[Feature_HasCryptoBit] = 1;
     142        4487 :   if (Subtarget->hasCRC())
     143         498 :     Features[Feature_HasCRCBit] = 1;
     144        4487 :   if (Subtarget->hasFP16())
     145        1624 :     Features[Feature_HasFP16Bit] = 1;
     146        4487 :   if (Subtarget->hasFullFP16())
     147           0 :     Features[Feature_HasFullFP16Bit] = 1;
     148        4487 :   if (Subtarget->hasDivideInThumbMode())
     149        1806 :     Features[Feature_HasDivideInThumbBit] = 1;
     150        4487 :   if (Subtarget->hasDivideInARMMode())
     151        1158 :     Features[Feature_HasDivideInARMBit] = 1;
     152        4487 :   if (Subtarget->hasDSP())
     153        5172 :     Features[Feature_HasDSPBit] = 1;
     154        4487 :   if (Subtarget->hasDataBarrier())
     155        5434 :     Features[Feature_HasDBBit] = 1;
     156        4487 :   if (Subtarget->hasV7Clrex())
     157        5204 :     Features[Feature_HasV7ClrexBit] = 1;
     158        4487 :   if (Subtarget->hasAcquireRelease())
     159         682 :     Features[Feature_HasAcquireReleaseBit] = 1;
     160        4487 :   if (Subtarget->hasMPExtension())
     161        1342 :     Features[Feature_HasMPBit] = 1;
     162        4487 :   if (Subtarget->hasZeroCycleZeroing())
     163           6 :     Features[Feature_HasZCZBit] = 1;
     164         259 :   if (Subtarget->useNEONForSinglePrecisionFP())
     165         518 :     Features[Feature_UseNEONForFPBit] = 1;
     166        4228 :   if (!Subtarget->useNEONForSinglePrecisionFP())
     167        8456 :     Features[Feature_DontUseNEONForFPBit] = 1;
     168        4487 :   if (Subtarget->isThumb())
     169        3506 :     Features[Feature_IsThumbBit] = 1;
     170        4487 :   if (Subtarget->isThumb1Only())
     171         846 :     Features[Feature_IsThumb1OnlyBit] = 1;
     172        4487 :   if (Subtarget->isThumb2())
     173        2660 :     Features[Feature_IsThumb2Bit] = 1;
     174        4487 :   if (!Subtarget->isMClass())
     175        8006 :     Features[Feature_IsNotMClassBit] = 1;
     176        4487 :   if (!Subtarget->isThumb())
     177        5468 :     Features[Feature_IsARMBit] = 1;
     178        4487 :   if (Subtarget->isTargetWindows())
     179         144 :     Features[Feature_IsWindowsBit] = 1;
     180        4487 :   if (!Subtarget->isTargetWindows())
     181        8830 :     Features[Feature_IsNotWindowsBit] = 1;
     182        4487 :   if (Subtarget->isReadTPHard())
     183           4 :     Features[Feature_IsReadTPHardBit] = 1;
     184        4487 :   if (!Subtarget->isReadTPHard())
     185        8970 :     Features[Feature_IsReadTPSoftBit] = 1;
     186        4487 :   if (Subtarget->useNaClTrap())
     187          28 :     Features[Feature_UseNaClTrapBit] = 1;
     188        4487 :   if (!Subtarget->useNaClTrap())
     189        8946 :     Features[Feature_DontUseNaClTrapBit] = 1;
     190        4487 :   if (Subtarget->useFPVMLx())
     191        7762 :     Features[Feature_UseFPVMLxBit] = 1;
     192        4487 :   if (Subtarget->useMulOps())
     193        8962 :     Features[Feature_UseMulOpsBit] = 1;
     194        4529 :   if ((TM.Options.AllowFPOpFusion == FPOpFusion::Fast &&  Subtarget->hasVFP4()) && !Subtarget->isTargetDarwin())
     195          84 :     Features[Feature_UseFusedMACBit] = 1;
     196        4487 :   if (!(TM.Options.AllowFPOpFusion == FPOpFusion::Fast && Subtarget->hasVFP4()) || Subtarget->isTargetDarwin())
     197        8890 :     Features[Feature_DontUseFusedMACBit] = 1;
     198        4487 :   if (!Subtarget->hasSlowVGETLNi32())
     199        8780 :     Features[Feature_HasFastVGETLNi32Bit] = 1;
     200        4487 :   if (Subtarget->hasSlowVGETLNi32())
     201         194 :     Features[Feature_HasSlowVGETLNi32Bit] = 1;
     202        4487 :   if (!Subtarget->hasSlowVDUP32())
     203        8780 :     Features[Feature_HasFastVDUP32Bit] = 1;
     204        4487 :   if (Subtarget->hasSlowVDUP32())
     205         194 :     Features[Feature_HasSlowVDUP32Bit] = 1;
     206        4487 :   if (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP())
     207        8472 :     Features[Feature_UseVMOVSRBit] = 1;
     208        4738 :   if (!Subtarget->preferVMOVSR() &&Subtarget->useNEONForSinglePrecisionFP())
     209         502 :     Features[Feature_DontUseVMOVSRBit] = 1;
     210        4487 :   return Features;
     211             : }
     212             : 
     213         646 : PredicateBitset ARMInstructionSelector::
     214             : computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget, const MachineFunction *MF) const {
     215         646 :   PredicateBitset Features;
     216         646 :   if (Subtarget->useMovt(*MF))
     217         194 :     Features[Feature_UseMovtBit] = 1;
     218         646 :   if (!Subtarget->useMovt(*MF))
     219        1098 :     Features[Feature_DontUseMovtBit] = 1;
     220         646 :   if (MF->getDataLayout().isLittleEndian())
     221        1292 :     Features[Feature_IsLEBit] = 1;
     222         646 :   if (MF->getDataLayout().isBigEndian())
     223           0 :     Features[Feature_IsBEBit] = 1;
     224         646 :   return Features;
     225             : }
     226             : 
     227             : // LLT Objects.
     228             : enum {
     229             :   GILLT_s32,
     230             :   GILLT_s64,
     231             :   GILLT_v2s32,
     232             :   GILLT_v2s64,
     233             :   GILLT_v4s16,
     234             :   GILLT_v4s32,
     235             :   GILLT_v8s8,
     236             :   GILLT_v8s16,
     237             :   GILLT_v16s8,
     238             : };
     239             : const static LLT TypeObjects[] = {
     240             :   LLT::scalar(32),
     241             :   LLT::scalar(64),
     242             :   LLT::vector(2, 32),
     243             :   LLT::vector(2, 64),
     244             :   LLT::vector(4, 16),
     245             :   LLT::vector(4, 32),
     246             :   LLT::vector(8, 8),
     247             :   LLT::vector(8, 16),
     248             :   LLT::vector(16, 8),
     249      723060 : };
     250             : 
     251             : // Feature bitsets.
     252             : enum {
     253             :   GIFBS_Invalid,
     254             :   GIFBS_HasNEON,
     255             :   GIFBS_HasVFP2,
     256             :   GIFBS_HasVFP4,
     257             :   GIFBS_IsARM,
     258             :   GIFBS_IsBE,
     259             :   GIFBS_IsLE,
     260             :   GIFBS_IsThumb2,
     261             :   GIFBS_NoHonorSignDependentRounding,
     262             :   GIFBS_HasDSP_IsThumb2,
     263             :   GIFBS_HasNEON_HasFP16,
     264             :   GIFBS_HasNEON_HasFullFP16,
     265             :   GIFBS_HasNEON_HasV8_1a,
     266             :   GIFBS_HasV8_HasCrypto,
     267             :   GIFBS_HasV8_HasNEON,
     268             :   GIFBS_HasVFP2_DontUseNEONForFP,
     269             :   GIFBS_HasVFP2_HasDPVFP,
     270             :   GIFBS_HasVFP2_UseVMOVSR,
     271             :   GIFBS_HasVFP4_HasDPVFP,
     272             :   GIFBS_IsARM_HasDivideInARM,
     273             :   GIFBS_IsARM_HasV5TE,
     274             :   GIFBS_IsARM_HasV6,
     275             :   GIFBS_IsARM_HasV6T2,
     276             :   GIFBS_IsARM_NoV6,
     277             :   GIFBS_IsThumb_HasV8MBaseline,
     278             :   GIFBS_IsThumb_IsThumb1Only,
     279             :   GIFBS_IsThumb_UseMovt,
     280             :   GIFBS_IsThumb2_HasDSP,
     281             :   GIFBS_IsThumb2_UseMulOps,
     282             :   GIFBS_NoHonorSignDependentRounding_HasDPVFP,
     283             :   GIFBS_HasDivideInThumb_IsThumb_HasV8MBaseline,
     284             :   GIFBS_HasNEON_HasFullFP16_UseFusedMAC,
     285             :   GIFBS_HasV8_HasNEON_HasFullFP16,
     286             :   GIFBS_IsARM_HasV5TE_UseMulOps,
     287             :   GIFBS_IsARM_HasV6_UseMulOps,
     288             :   GIFBS_IsARM_HasV6T2_UseMulOps,
     289             :   GIFBS_IsARM_HasV8_HasCRC,
     290             :   GIFBS_IsARM_NoV6_UseMulOps,
     291             :   GIFBS_IsThumb_IsThumb1Only_HasV6,
     292             :   GIFBS_IsThumb2_HasDSP_UseMulOps,
     293             :   GIFBS_IsThumb2_HasV8_HasCRC,
     294             :   GIFBS_IsThumb2_UseMulOps_HasDSP,
     295             :   GIFBS_HasNEON_HasFullFP16_UseFPVMLx_DontUseFusedMAC,
     296             : };
     297             : const static PredicateBitset FeatureBitsets[] {
     298             :   {}, // GIFBS_Invalid
     299             :   {Feature_HasNEONBit, },
     300             :   {Feature_HasVFP2Bit, },
     301             :   {Feature_HasVFP4Bit, },
     302             :   {Feature_IsARMBit, },
     303             :   {Feature_IsBEBit, },
     304             :   {Feature_IsLEBit, },
     305             :   {Feature_IsThumb2Bit, },
     306             :   {Feature_NoHonorSignDependentRoundingBit, },
     307             :   {Feature_HasDSPBit, Feature_IsThumb2Bit, },
     308             :   {Feature_HasNEONBit, Feature_HasFP16Bit, },
     309             :   {Feature_HasNEONBit, Feature_HasFullFP16Bit, },
     310             :   {Feature_HasNEONBit, Feature_HasV8_1aBit, },
     311             :   {Feature_HasV8Bit, Feature_HasCryptoBit, },
     312             :   {Feature_HasV8Bit, Feature_HasNEONBit, },
     313             :   {Feature_HasVFP2Bit, Feature_DontUseNEONForFPBit, },
     314             :   {Feature_HasVFP2Bit, Feature_HasDPVFPBit, },
     315             :   {Feature_HasVFP2Bit, Feature_UseVMOVSRBit, },
     316             :   {Feature_HasVFP4Bit, Feature_HasDPVFPBit, },
     317             :   {Feature_IsARMBit, Feature_HasDivideInARMBit, },
     318             :   {Feature_IsARMBit, Feature_HasV5TEBit, },
     319             :   {Feature_IsARMBit, Feature_HasV6Bit, },
     320             :   {Feature_IsARMBit, Feature_HasV6T2Bit, },
     321             :   {Feature_IsARMBit, Feature_NoV6Bit, },
     322             :   {Feature_IsThumbBit, Feature_HasV8MBaselineBit, },
     323             :   {Feature_IsThumbBit, Feature_IsThumb1OnlyBit, },
     324             :   {Feature_IsThumbBit, Feature_UseMovtBit, },
     325             :   {Feature_IsThumb2Bit, Feature_HasDSPBit, },
     326             :   {Feature_IsThumb2Bit, Feature_UseMulOpsBit, },
     327             :   {Feature_NoHonorSignDependentRoundingBit, Feature_HasDPVFPBit, },
     328             :   {Feature_HasDivideInThumbBit, Feature_IsThumbBit, Feature_HasV8MBaselineBit, },
     329             :   {Feature_HasNEONBit, Feature_HasFullFP16Bit, Feature_UseFusedMACBit, },
     330             :   {Feature_HasV8Bit, Feature_HasNEONBit, Feature_HasFullFP16Bit, },
     331             :   {Feature_IsARMBit, Feature_HasV5TEBit, Feature_UseMulOpsBit, },
     332             :   {Feature_IsARMBit, Feature_HasV6Bit, Feature_UseMulOpsBit, },
     333             :   {Feature_IsARMBit, Feature_HasV6T2Bit, Feature_UseMulOpsBit, },
     334             :   {Feature_IsARMBit, Feature_HasV8Bit, Feature_HasCRCBit, },
     335             :   {Feature_IsARMBit, Feature_NoV6Bit, Feature_UseMulOpsBit, },
     336             :   {Feature_IsThumbBit, Feature_IsThumb1OnlyBit, Feature_HasV6Bit, },
     337             :   {Feature_IsThumb2Bit, Feature_HasDSPBit, Feature_UseMulOpsBit, },
     338             :   {Feature_IsThumb2Bit, Feature_HasV8Bit, Feature_HasCRCBit, },
     339             :   {Feature_IsThumb2Bit, Feature_UseMulOpsBit, Feature_HasDSPBit, },
     340             :   {Feature_HasNEONBit, Feature_HasFullFP16Bit, Feature_UseFPVMLxBit, Feature_DontUseFusedMACBit, },
     341       72306 : };
     342             : 
     343             : // ComplexPattern predicates.
     344             : enum {
     345             :   GICP_Invalid,
     346             : };
     347             : // See constructor for table contents
     348             : 
     349             : // PatFrag predicates.
     350             : enum {
     351             :   GIPFP_Predicate_VectorIndex16 = GIPFP_Invalid + 1,
     352             :   GIPFP_Predicate_VectorIndex32,
     353             :   GIPFP_Predicate_VectorIndex8,
     354             :   GIPFP_Predicate_imm0_15,
     355             :   GIPFP_Predicate_imm0_239,
     356             :   GIPFP_Predicate_imm0_255,
     357             :   GIPFP_Predicate_imm0_31,
     358             :   GIPFP_Predicate_imm0_32,
     359             :   GIPFP_Predicate_imm0_4095,
     360             :   GIPFP_Predicate_imm0_63,
     361             :   GIPFP_Predicate_imm0_65535,
     362             :   GIPFP_Predicate_imm0_65535_neg,
     363             :   GIPFP_Predicate_imm0_7,
     364             :   GIPFP_Predicate_imm16,
     365             :   GIPFP_Predicate_imm16_31,
     366             :   GIPFP_Predicate_imm1_15,
     367             :   GIPFP_Predicate_imm1_16,
     368             :   GIPFP_Predicate_imm1_31,
     369             :   GIPFP_Predicate_imm1_7,
     370             :   GIPFP_Predicate_imm24b,
     371             :   GIPFP_Predicate_imm256_510,
     372             :   GIPFP_Predicate_imm32,
     373             :   GIPFP_Predicate_imm8,
     374             :   GIPFP_Predicate_imm8_255,
     375             :   GIPFP_Predicate_imm8_or_16,
     376             :   GIPFP_Predicate_mod_imm,
     377             :   GIPFP_Predicate_pkh_asr_amt,
     378             :   GIPFP_Predicate_pkh_lsl_amt,
     379             :   GIPFP_Predicate_shr_imm16,
     380             :   GIPFP_Predicate_shr_imm32,
     381             :   GIPFP_Predicate_shr_imm64,
     382             :   GIPFP_Predicate_shr_imm8,
     383             :   GIPFP_Predicate_t2_so_imm,
     384             :   GIPFP_Predicate_t2_so_imm_neg,
     385             : };
     386           0 :   static bool Predicate_VectorIndex16(int64_t Imm) {
     387           0 :   return ((uint64_t)Imm) < 4;
     388             :   }
     389           0 :   static bool Predicate_VectorIndex32(int64_t Imm) {
     390           0 :   return ((uint64_t)Imm) < 2;
     391             :   }
     392           0 :   static bool Predicate_VectorIndex8(int64_t Imm) {
     393           0 :   return ((uint64_t)Imm) < 8;
     394             :   }
     395           0 :   static bool Predicate_imm0_15(int64_t Imm) {
     396           0 :   return Imm >= 0 && Imm < 16;
     397             :   }
     398           0 :   static bool Predicate_imm0_239(int64_t Imm) { return Imm >= 0 && Imm < 240;   }
     399           0 :   static bool Predicate_imm0_255(int64_t Imm) { return Imm >= 0 && Imm < 256;   }
     400           0 :   static bool Predicate_imm0_31(int64_t Imm) {
     401           0 :   return Imm >= 0 && Imm < 32;
     402             :   }
     403           0 :   static bool Predicate_imm0_32(int64_t Imm) {
     404           0 :   return Imm >= 0 && Imm < 33;
     405             :   }
     406           0 :   static bool Predicate_imm0_4095(int64_t Imm) {
     407           0 :   return Imm >= 0 && Imm < 4096;
     408             :   }
     409           0 :   static bool Predicate_imm0_63(int64_t Imm) {
     410           0 :   return Imm >= 0 && Imm < 64;
     411             :   }
     412           0 :   static bool Predicate_imm0_65535(int64_t Imm) {
     413           0 :   return Imm >= 0 && Imm < 65536;
     414             :   }
     415           0 :   static bool Predicate_imm0_65535_neg(int64_t Imm) {
     416           0 :   return -Imm >= 0 && -Imm < 65536;
     417             :   }
     418           0 :   static bool Predicate_imm0_7(int64_t Imm) {
     419           0 :   return Imm >= 0 && Imm < 8;
     420             :   }
     421           0 :   static bool Predicate_imm16(int64_t Imm) { return Imm == 16;   }
     422           0 :   static bool Predicate_imm16_31(int64_t Imm) {
     423           0 :   return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
     424             :   }
     425           0 :   static bool Predicate_imm1_15(int64_t Imm) { return Imm > 0 && Imm < 16;   }
     426           0 :   static bool Predicate_imm1_16(int64_t Imm) {
     427           0 :     return Imm > 0 && Imm <= 16;
     428             :     }
     429           0 :   static bool Predicate_imm1_31(int64_t Imm) { return Imm > 0 && Imm < 32;   }
     430           0 :   static bool Predicate_imm1_7(int64_t Imm) { return Imm > 0 && Imm < 8;   }
     431           0 :   static bool Predicate_imm24b(int64_t Imm) {
     432           0 :   return Imm >= 0 && Imm <= 0xffffff;
     433             :   }
     434           0 :   static bool Predicate_imm256_510(int64_t Imm) {
     435           0 :   return Imm >= 256 && Imm < 511;
     436             :   }
     437           0 :   static bool Predicate_imm32(int64_t Imm) { return Imm == 32;   }
     438           0 :   static bool Predicate_imm8(int64_t Imm) { return Imm == 8;   }
     439           0 :   static bool Predicate_imm8_255(int64_t Imm) {
     440           0 :   return Imm >= 8 && Imm < 256;
     441             :   }
     442           0 :   static bool Predicate_imm8_or_16(int64_t Imm) { return Imm == 8 || Imm == 16;  }
     443           7 :   static bool Predicate_mod_imm(int64_t Imm) {
     444           7 :     return ARM_AM::getSOImmVal(Imm) != -1;
     445             :     }
     446           0 :   static bool Predicate_pkh_asr_amt(int64_t Imm) { return Imm > 0 && Imm <= 32;   }
     447           0 :   static bool Predicate_pkh_lsl_amt(int64_t Imm) { return Imm >= 0 && Imm < 32;   }
     448           0 :   static bool Predicate_shr_imm16(int64_t Imm) { return Imm > 0 && Imm <= 16;   }
     449           0 :   static bool Predicate_shr_imm32(int64_t Imm) { return Imm > 0 && Imm <= 32;   }
     450           0 :   static bool Predicate_shr_imm64(int64_t Imm) { return Imm > 0 && Imm <= 64;   }
     451           0 :   static bool Predicate_shr_imm8(int64_t Imm) { return Imm > 0 && Imm <= 8;   }
     452           0 :   static bool Predicate_t2_so_imm(int64_t Imm) {
     453           0 :     return ARM_AM::getT2SOImmVal(Imm) != -1;
     454             :     }
     455           0 :   static bool Predicate_t2_so_imm_neg(int64_t Imm) {
     456           0 :   return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;
     457             :   }
     458             : static InstructionSelector::ImmediatePredicateFn ImmPredicateFns[] = {
     459             :   nullptr,
     460             :   Predicate_VectorIndex16,
     461             :   Predicate_VectorIndex32,
     462             :   Predicate_VectorIndex8,
     463             :   Predicate_imm0_15,
     464             :   Predicate_imm0_239,
     465             :   Predicate_imm0_255,
     466             :   Predicate_imm0_31,
     467             :   Predicate_imm0_32,
     468             :   Predicate_imm0_4095,
     469             :   Predicate_imm0_63,
     470             :   Predicate_imm0_65535,
     471             :   Predicate_imm0_65535_neg,
     472             :   Predicate_imm0_7,
     473             :   Predicate_imm16,
     474             :   Predicate_imm16_31,
     475             :   Predicate_imm1_15,
     476             :   Predicate_imm1_16,
     477             :   Predicate_imm1_31,
     478             :   Predicate_imm1_7,
     479             :   Predicate_imm24b,
     480             :   Predicate_imm256_510,
     481             :   Predicate_imm32,
     482             :   Predicate_imm8,
     483             :   Predicate_imm8_255,
     484             :   Predicate_imm8_or_16,
     485             :   Predicate_mod_imm,
     486             :   Predicate_pkh_asr_amt,
     487             :   Predicate_pkh_lsl_amt,
     488             :   Predicate_shr_imm16,
     489             :   Predicate_shr_imm32,
     490             :   Predicate_shr_imm64,
     491             :   Predicate_shr_imm8,
     492             :   Predicate_t2_so_imm,
     493             :   Predicate_t2_so_imm_neg,
     494             : };
     495         646 : bool ARMInstructionSelector::selectImpl(MachineInstr &I) const {
     496         646 :   MachineFunction &MF = *I.getParent()->getParent();
     497         646 :   MachineRegisterInfo &MRI = MF.getRegInfo();
     498             :   // FIXME: This should be computed on a per-function basis rather than per-insn.
     499         646 :   AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);
     500         646 :   const PredicateBitset AvailableFeatures = getAvailableFeatures();
     501        1292 :   NewMIVector OutMIs;
     502        1292 :   State.MIs.clear();
     503         646 :   State.MIs.push_back(&I);
     504             : 
     505             :   constexpr static int64_t MatchTable0[] = {
     506             :     GIM_Try, /*On fail goto*//*Label 0*/ 76,
     507             :       GIM_CheckFeatures, GIFBS_IsARM_HasV6,
     508             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
     509             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
     510             :       // MIs[0] Rd
     511             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
     512             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
     513             :       // MIs[0] Operand 1
     514             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usada8,
     515             :       // MIs[0] Rn
     516             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
     517             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
     518             :       // MIs[0] Rm
     519             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
     520             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
     521             :       // MIs[0] Ra
     522             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
     523             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
     524             :       // (intrinsic_wo_chain:i32 794:iPTR, GPR:i32:$Rn, GPR:i32:$Rm, GPR:i32:$Ra)  =>  (USADA8:i32 GPR:i32:$Rn, GPR:i32:$Rm, GPR:i32:$Ra)
     525             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USADA8,
     526             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
     527             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     528             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
     529             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
     530             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
     531             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
     532             :       GIR_EraseFromParent, /*InsnID*/0,
     533             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     534             :       GIR_Done,
     535             :     // Label 0: @76
     536             :     GIM_Try, /*On fail goto*//*Label 1*/ 152,
     537             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
     538             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
     539             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
     540             :       // MIs[0] Rd
     541             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
     542             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
     543             :       // MIs[0] Operand 1
     544             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usada8,
     545             :       // MIs[0] Rn
     546             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
     547             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
     548             :       // MIs[0] Rm
     549             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
     550             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
     551             :       // MIs[0] Ra
     552             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
     553             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
     554             :       // (intrinsic_wo_chain:i32 794:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm, rGPR:i32:$Ra)  =>  (t2USADA8:i32 rGPR:i32:$Rn, rGPR:i32:$Rm, rGPR:i32:$Ra)
     555             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USADA8,
     556             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
     557             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     558             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
     559             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
     560             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
     561             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
     562             :       GIR_EraseFromParent, /*InsnID*/0,
     563             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     564             :       GIR_Done,
     565             :     // Label 1: @152
     566             :     GIM_Try, /*On fail goto*//*Label 2*/ 228,
     567             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
     568             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
     569             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
     570             :       // MIs[0] Rd
     571             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
     572             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
     573             :       // MIs[0] Operand 1
     574             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlad,
     575             :       // MIs[0] Rn
     576             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
     577             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
     578             :       // MIs[0] Rm
     579             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
     580             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
     581             :       // MIs[0] Ra
     582             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
     583             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
     584             :       // (intrinsic_wo_chain:i32 739:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm, rGPR:i32:$Ra)  =>  (t2SMLAD:i32 rGPR:i32:$Rn, rGPR:i32:$Rm, rGPR:i32:$Ra)
     585             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLAD,
     586             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
     587             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     588             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
     589             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
     590             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
     591             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
     592             :       GIR_EraseFromParent, /*InsnID*/0,
     593             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     594             :       GIR_Done,
     595             :     // Label 2: @228
     596             :     GIM_Try, /*On fail goto*//*Label 3*/ 304,
     597             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
     598             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
     599             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
     600             :       // MIs[0] Rd
     601             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
     602             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
     603             :       // MIs[0] Operand 1
     604             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smladx,
     605             :       // MIs[0] Rn
     606             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
     607             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
     608             :       // MIs[0] Rm
     609             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
     610             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
     611             :       // MIs[0] Ra
     612             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
     613             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
     614             :       // (intrinsic_wo_chain:i32 740:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm, rGPR:i32:$Ra)  =>  (t2SMLADX:i32 rGPR:i32:$Rn, rGPR:i32:$Rm, rGPR:i32:$Ra)
     615             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLADX,
     616             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
     617             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     618             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
     619             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
     620             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
     621             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
     622             :       GIR_EraseFromParent, /*InsnID*/0,
     623             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     624             :       GIR_Done,
     625             :     // Label 3: @304
     626             :     GIM_Try, /*On fail goto*//*Label 4*/ 380,
     627             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
     628             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
     629             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
     630             :       // MIs[0] Rd
     631             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
     632             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
     633             :       // MIs[0] Operand 1
     634             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlsd,
     635             :       // MIs[0] Rn
     636             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
     637             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
     638             :       // MIs[0] Rm
     639             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
     640             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
     641             :       // MIs[0] Ra
     642             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
     643             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
     644             :       // (intrinsic_wo_chain:i32 747:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm, rGPR:i32:$Ra)  =>  (t2SMLSD:i32 rGPR:i32:$Rn, rGPR:i32:$Rm, rGPR:i32:$Ra)
     645             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLSD,
     646             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
     647             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     648             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
     649             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
     650             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
     651             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
     652             :       GIR_EraseFromParent, /*InsnID*/0,
     653             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     654             :       GIR_Done,
     655             :     // Label 4: @380
     656             :     GIM_Try, /*On fail goto*//*Label 5*/ 456,
     657             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
     658             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
     659             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
     660             :       // MIs[0] Rd
     661             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
     662             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
     663             :       // MIs[0] Operand 1
     664             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlsdx,
     665             :       // MIs[0] Rn
     666             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
     667             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
     668             :       // MIs[0] Rm
     669             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
     670             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
     671             :       // MIs[0] Ra
     672             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
     673             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
     674             :       // (intrinsic_wo_chain:i32 748:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm, rGPR:i32:$Ra)  =>  (t2SMLSDX:i32 rGPR:i32:$Rn, rGPR:i32:$Rm, rGPR:i32:$Ra)
     675             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLSDX,
     676             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
     677             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     678             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
     679             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
     680             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
     681             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
     682             :       GIR_EraseFromParent, /*InsnID*/0,
     683             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     684             :       GIR_Done,
     685             :     // Label 5: @456
     686             :     GIM_Try, /*On fail goto*//*Label 6*/ 532,
     687             :       GIM_CheckFeatures, GIFBS_HasNEON,
     688             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
     689             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
     690             :       // MIs[0] Vd
     691             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
     692             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
     693             :       // MIs[0] Operand 1
     694             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vtbx1,
     695             :       // MIs[0] orig
     696             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
     697             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
     698             :       // MIs[0] Vn
     699             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
     700             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
     701             :       // MIs[0] Vm
     702             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
     703             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
     704             :       // (intrinsic_wo_chain:v8i8 714:iPTR, DPR:v8i8:$orig, VecListOneD:v8i8:$Vn, DPR:v8i8:$Vm)  =>  (VTBX1:v8i8 DPR:v8i8:$orig, VecListOneD:v8i8:$Vn, DPR:v8i8:$Vm)
     705             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBX1,
     706             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
     707             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // orig
     708             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
     709             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
     710             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
     711             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
     712             :       GIR_EraseFromParent, /*InsnID*/0,
     713             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     714             :       GIR_Done,
     715             :     // Label 6: @532
     716             :     GIM_Try, /*On fail goto*//*Label 7*/ 602,
     717             :       GIM_CheckFeatures, GIFBS_HasV8_HasCrypto,
     718             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
     719             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
     720             :       // MIs[0] Vd
     721             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
     722             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
     723             :       // MIs[0] Operand 1
     724             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha1su0,
     725             :       // MIs[0] src
     726             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
     727             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
     728             :       // MIs[0] Vn
     729             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
     730             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
     731             :       // MIs[0] Vm
     732             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
     733             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
     734             :       // (intrinsic_wo_chain:v4i32 603:iPTR, QPR:v4i32:$src, QPR:v4i32:$Vn, QPR:v4i32:$Vm)  =>  (SHA1SU0:v4i32 QPR:v4i32:$src, QPR:v4i32:$Vn, QPR:v4i32:$Vm)
     735             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA1SU0,
     736             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
     737             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
     738             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
     739             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
     740             :       GIR_EraseFromParent, /*InsnID*/0,
     741             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     742             :       GIR_Done,
     743             :     // Label 7: @602
     744             :     GIM_Try, /*On fail goto*//*Label 8*/ 672,
     745             :       GIM_CheckFeatures, GIFBS_HasV8_HasCrypto,
     746             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
     747             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
     748             :       // MIs[0] Vd
     749             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
     750             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
     751             :       // MIs[0] Operand 1
     752             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha256h,
     753             :       // MIs[0] src
     754             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
     755             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
     756             :       // MIs[0] Vn
     757             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
     758             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
     759             :       // MIs[0] Vm
     760             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
     761             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
     762             :       // (intrinsic_wo_chain:v4i32 605:iPTR, QPR:v4i32:$src, QPR:v4i32:$Vn, QPR:v4i32:$Vm)  =>  (SHA256H:v4i32 QPR:v4i32:$src, QPR:v4i32:$Vn, QPR:v4i32:$Vm)
     763             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA256H,
     764             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
     765             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
     766             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
     767             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
     768             :       GIR_EraseFromParent, /*InsnID*/0,
     769             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     770             :       GIR_Done,
     771             :     // Label 8: @672
     772             :     GIM_Try, /*On fail goto*//*Label 9*/ 742,
     773             :       GIM_CheckFeatures, GIFBS_HasV8_HasCrypto,
     774             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
     775             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
     776             :       // MIs[0] Vd
     777             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
     778             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
     779             :       // MIs[0] Operand 1
     780             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha256h2,
     781             :       // MIs[0] src
     782             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
     783             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
     784             :       // MIs[0] Vn
     785             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
     786             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
     787             :       // MIs[0] Vm
     788             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
     789             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
     790             :       // (intrinsic_wo_chain:v4i32 606:iPTR, QPR:v4i32:$src, QPR:v4i32:$Vn, QPR:v4i32:$Vm)  =>  (SHA256H2:v4i32 QPR:v4i32:$src, QPR:v4i32:$Vn, QPR:v4i32:$Vm)
     791             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA256H2,
     792             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
     793             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
     794             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
     795             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
     796             :       GIR_EraseFromParent, /*InsnID*/0,
     797             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     798             :       GIR_Done,
     799             :     // Label 9: @742
     800             :     GIM_Try, /*On fail goto*//*Label 10*/ 812,
     801             :       GIM_CheckFeatures, GIFBS_HasV8_HasCrypto,
     802             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
     803             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
     804             :       // MIs[0] Vd
     805             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
     806             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
     807             :       // MIs[0] Operand 1
     808             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha256su1,
     809             :       // MIs[0] src
     810             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
     811             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
     812             :       // MIs[0] Vn
     813             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
     814             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
     815             :       // MIs[0] Vm
     816             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
     817             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
     818             :       // (intrinsic_wo_chain:v4i32 608:iPTR, QPR:v4i32:$src, QPR:v4i32:$Vn, QPR:v4i32:$Vm)  =>  (SHA256SU1:v4i32 QPR:v4i32:$src, QPR:v4i32:$Vn, QPR:v4i32:$Vm)
     819             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA256SU1,
     820             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
     821             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
     822             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
     823             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
     824             :       GIR_EraseFromParent, /*InsnID*/0,
     825             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     826             :       GIR_Done,
     827             :     // Label 10: @812
     828             :     GIM_Try, /*On fail goto*//*Label 11*/ 888,
     829             :       GIM_CheckFeatures, GIFBS_IsARM_HasV6,
     830             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
     831             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
     832             :       // MIs[0] Rd
     833             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
     834             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
     835             :       // MIs[0] Operand 1
     836             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlad,
     837             :       // MIs[0] Rn
     838             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
     839             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
     840             :       // MIs[0] Rm
     841             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
     842             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
     843             :       // MIs[0] Ra
     844             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
     845             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
     846             :       // (intrinsic_wo_chain:i32 739:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm, GPR:i32:$Ra)  =>  (SMLAD:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm, GPRnopc:i32:$Ra)
     847             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLAD,
     848             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
     849             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     850             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
     851             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
     852             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
     853             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
     854             :       GIR_EraseFromParent, /*InsnID*/0,
     855             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     856             :       GIR_Done,
     857             :     // Label 11: @888
     858             :     GIM_Try, /*On fail goto*//*Label 12*/ 964,
     859             :       GIM_CheckFeatures, GIFBS_IsARM_HasV6,
     860             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
     861             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
     862             :       // MIs[0] Rd
     863             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
     864             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
     865             :       // MIs[0] Operand 1
     866             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smladx,
     867             :       // MIs[0] Rn
     868             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
     869             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
     870             :       // MIs[0] Rm
     871             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
     872             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
     873             :       // MIs[0] Ra
     874             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
     875             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
     876             :       // (intrinsic_wo_chain:i32 740:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm, GPR:i32:$Ra)  =>  (SMLADX:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm, GPRnopc:i32:$Ra)
     877             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLADX,
     878             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
     879             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     880             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
     881             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
     882             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
     883             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
     884             :       GIR_EraseFromParent, /*InsnID*/0,
     885             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     886             :       GIR_Done,
     887             :     // Label 12: @964
     888             :     GIM_Try, /*On fail goto*//*Label 13*/ 1040,
     889             :       GIM_CheckFeatures, GIFBS_IsARM_HasV6,
     890             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
     891             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
     892             :       // MIs[0] Rd
     893             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
     894             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
     895             :       // MIs[0] Operand 1
     896             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlsd,
     897             :       // MIs[0] Rn
     898             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
     899             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
     900             :       // MIs[0] Rm
     901             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
     902             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
     903             :       // MIs[0] Ra
     904             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
     905             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
     906             :       // (intrinsic_wo_chain:i32 747:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm, GPR:i32:$Ra)  =>  (SMLSD:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm, GPRnopc:i32:$Ra)
     907             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLSD,
     908             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
     909             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     910             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
     911             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
     912             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
     913             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
     914             :       GIR_EraseFromParent, /*InsnID*/0,
     915             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     916             :       GIR_Done,
     917             :     // Label 13: @1040
     918             :     GIM_Try, /*On fail goto*//*Label 14*/ 1116,
     919             :       GIM_CheckFeatures, GIFBS_IsARM_HasV6,
     920             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
     921             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
     922             :       // MIs[0] Rd
     923             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
     924             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
     925             :       // MIs[0] Operand 1
     926             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlsdx,
     927             :       // MIs[0] Rn
     928             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
     929             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
     930             :       // MIs[0] Rm
     931             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
     932             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
     933             :       // MIs[0] Ra
     934             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
     935             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
     936             :       // (intrinsic_wo_chain:i32 748:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm, GPR:i32:$Ra)  =>  (SMLSDX:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm, GPRnopc:i32:$Ra)
     937             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLSDX,
     938             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
     939             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     940             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
     941             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
     942             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
     943             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
     944             :       GIR_EraseFromParent, /*InsnID*/0,
     945             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     946             :       GIR_Done,
     947             :     // Label 14: @1116
     948             :     GIM_Try, /*On fail goto*//*Label 15*/ 1192,
     949             :       GIM_CheckFeatures, GIFBS_IsARM_HasV5TE,
     950             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
     951             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
     952             :       // MIs[0] Rd
     953             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
     954             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
     955             :       // MIs[0] Operand 1
     956             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlabb,
     957             :       // MIs[0] a
     958             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
     959             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
     960             :       // MIs[0] b
     961             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
     962             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
     963             :       // MIs[0] acc
     964             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
     965             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
     966             :       // (intrinsic_wo_chain:i32 737:iPTR, GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)  =>  (SMLABB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
     967             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLABB,
     968             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
     969             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
     970             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
     971             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
     972             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
     973             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
     974             :       GIR_EraseFromParent, /*InsnID*/0,
     975             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     976             :       GIR_Done,
     977             :     // Label 15: @1192
     978             :     GIM_Try, /*On fail goto*//*Label 16*/ 1268,
     979             :       GIM_CheckFeatures, GIFBS_IsARM_HasV5TE,
     980             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
     981             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
     982             :       // MIs[0] Rd
     983             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
     984             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
     985             :       // MIs[0] Operand 1
     986             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlabt,
     987             :       // MIs[0] a
     988             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
     989             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
     990             :       // MIs[0] b
     991             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
     992             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
     993             :       // MIs[0] acc
     994             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
     995             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
     996             :       // (intrinsic_wo_chain:i32 738:iPTR, GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)  =>  (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
     997             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLABT,
     998             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
     999             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
    1000             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
    1001             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
    1002             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1003             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1004             :       GIR_EraseFromParent, /*InsnID*/0,
    1005             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1006             :       GIR_Done,
    1007             :     // Label 16: @1268
    1008             :     GIM_Try, /*On fail goto*//*Label 17*/ 1344,
    1009             :       GIM_CheckFeatures, GIFBS_IsARM_HasV5TE,
    1010             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    1011             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    1012             :       // MIs[0] Rd
    1013             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    1014             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    1015             :       // MIs[0] Operand 1
    1016             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlatb,
    1017             :       // MIs[0] a
    1018             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    1019             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
    1020             :       // MIs[0] b
    1021             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    1022             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
    1023             :       // MIs[0] acc
    1024             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    1025             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
    1026             :       // (intrinsic_wo_chain:i32 743:iPTR, GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)  =>  (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
    1027             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATB,
    1028             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    1029             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
    1030             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
    1031             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
    1032             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1033             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1034             :       GIR_EraseFromParent, /*InsnID*/0,
    1035             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1036             :       GIR_Done,
    1037             :     // Label 17: @1344
    1038             :     GIM_Try, /*On fail goto*//*Label 18*/ 1420,
    1039             :       GIM_CheckFeatures, GIFBS_IsARM_HasV5TE,
    1040             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    1041             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    1042             :       // MIs[0] Rd
    1043             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    1044             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    1045             :       // MIs[0] Operand 1
    1046             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlatt,
    1047             :       // MIs[0] a
    1048             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    1049             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
    1050             :       // MIs[0] b
    1051             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    1052             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
    1053             :       // MIs[0] acc
    1054             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    1055             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
    1056             :       // (intrinsic_wo_chain:i32 744:iPTR, GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)  =>  (SMLATT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
    1057             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATT,
    1058             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    1059             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
    1060             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
    1061             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
    1062             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1063             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1064             :       GIR_EraseFromParent, /*InsnID*/0,
    1065             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1066             :       GIR_Done,
    1067             :     // Label 18: @1420
    1068             :     GIM_Try, /*On fail goto*//*Label 19*/ 1496,
    1069             :       GIM_CheckFeatures, GIFBS_IsARM_HasV5TE,
    1070             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    1071             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    1072             :       // MIs[0] Rd
    1073             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    1074             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    1075             :       // MIs[0] Operand 1
    1076             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlawb,
    1077             :       // MIs[0] a
    1078             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    1079             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
    1080             :       // MIs[0] b
    1081             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    1082             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
    1083             :       // MIs[0] acc
    1084             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    1085             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
    1086             :       // (intrinsic_wo_chain:i32 745:iPTR, GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)  =>  (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
    1087             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLAWB,
    1088             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    1089             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
    1090             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
    1091             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
    1092             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1093             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1094             :       GIR_EraseFromParent, /*InsnID*/0,
    1095             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1096             :       GIR_Done,
    1097             :     // Label 19: @1496
    1098             :     GIM_Try, /*On fail goto*//*Label 20*/ 1572,
    1099             :       GIM_CheckFeatures, GIFBS_IsARM_HasV5TE,
    1100             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    1101             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    1102             :       // MIs[0] Rd
    1103             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    1104             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    1105             :       // MIs[0] Operand 1
    1106             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlawt,
    1107             :       // MIs[0] a
    1108             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    1109             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
    1110             :       // MIs[0] b
    1111             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    1112             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
    1113             :       // MIs[0] acc
    1114             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    1115             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
    1116             :       // (intrinsic_wo_chain:i32 746:iPTR, GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)  =>  (SMLAWT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
    1117             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLAWT,
    1118             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    1119             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
    1120             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
    1121             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
    1122             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1123             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1124             :       GIR_EraseFromParent, /*InsnID*/0,
    1125             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1126             :       GIR_Done,
    1127             :     // Label 20: @1572
    1128             :     GIM_Try, /*On fail goto*//*Label 21*/ 1648,
    1129             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    1130             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    1131             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    1132             :       // MIs[0] Rd
    1133             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    1134             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    1135             :       // MIs[0] Operand 1
    1136             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlabb,
    1137             :       // MIs[0] a
    1138             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    1139             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
    1140             :       // MIs[0] b
    1141             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    1142             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
    1143             :       // MIs[0] acc
    1144             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    1145             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
    1146             :       // (intrinsic_wo_chain:i32 737:iPTR, GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)  =>  (t2SMLABB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
    1147             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLABB,
    1148             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    1149             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
    1150             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
    1151             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
    1152             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1153             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1154             :       GIR_EraseFromParent, /*InsnID*/0,
    1155             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1156             :       GIR_Done,
    1157             :     // Label 21: @1648
    1158             :     GIM_Try, /*On fail goto*//*Label 22*/ 1724,
    1159             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    1160             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    1161             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    1162             :       // MIs[0] Rd
    1163             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    1164             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    1165             :       // MIs[0] Operand 1
    1166             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlabt,
    1167             :       // MIs[0] a
    1168             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    1169             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
    1170             :       // MIs[0] b
    1171             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    1172             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
    1173             :       // MIs[0] acc
    1174             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    1175             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
    1176             :       // (intrinsic_wo_chain:i32 738:iPTR, GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)  =>  (t2SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
    1177             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLABT,
    1178             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    1179             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
    1180             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
    1181             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
    1182             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1183             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1184             :       GIR_EraseFromParent, /*InsnID*/0,
    1185             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1186             :       GIR_Done,
    1187             :     // Label 22: @1724
    1188             :     GIM_Try, /*On fail goto*//*Label 23*/ 1800,
    1189             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    1190             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    1191             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    1192             :       // MIs[0] Rd
    1193             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    1194             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    1195             :       // MIs[0] Operand 1
    1196             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlatb,
    1197             :       // MIs[0] a
    1198             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    1199             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
    1200             :       // MIs[0] b
    1201             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    1202             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
    1203             :       // MIs[0] acc
    1204             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    1205             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
    1206             :       // (intrinsic_wo_chain:i32 743:iPTR, GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)  =>  (t2SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
    1207             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATB,
    1208             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    1209             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
    1210             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
    1211             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
    1212             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1213             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1214             :       GIR_EraseFromParent, /*InsnID*/0,
    1215             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1216             :       GIR_Done,
    1217             :     // Label 23: @1800
    1218             :     GIM_Try, /*On fail goto*//*Label 24*/ 1876,
    1219             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    1220             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    1221             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    1222             :       // MIs[0] Rd
    1223             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    1224             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    1225             :       // MIs[0] Operand 1
    1226             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlatt,
    1227             :       // MIs[0] a
    1228             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    1229             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
    1230             :       // MIs[0] b
    1231             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    1232             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
    1233             :       // MIs[0] acc
    1234             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    1235             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
    1236             :       // (intrinsic_wo_chain:i32 744:iPTR, GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)  =>  (t2SMLATT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
    1237             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATT,
    1238             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    1239             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
    1240             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
    1241             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
    1242             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1243             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1244             :       GIR_EraseFromParent, /*InsnID*/0,
    1245             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1246             :       GIR_Done,
    1247             :     // Label 24: @1876
    1248             :     GIM_Try, /*On fail goto*//*Label 25*/ 1952,
    1249             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    1250             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    1251             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    1252             :       // MIs[0] Rd
    1253             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    1254             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    1255             :       // MIs[0] Operand 1
    1256             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlawb,
    1257             :       // MIs[0] a
    1258             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    1259             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
    1260             :       // MIs[0] b
    1261             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    1262             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
    1263             :       // MIs[0] acc
    1264             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    1265             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
    1266             :       // (intrinsic_wo_chain:i32 745:iPTR, GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)  =>  (t2SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
    1267             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLAWB,
    1268             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    1269             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
    1270             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
    1271             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
    1272             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1273             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1274             :       GIR_EraseFromParent, /*InsnID*/0,
    1275             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1276             :       GIR_Done,
    1277             :     // Label 25: @1952
    1278             :     GIM_Try, /*On fail goto*//*Label 26*/ 2028,
    1279             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    1280             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    1281             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    1282             :       // MIs[0] Rd
    1283             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    1284             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    1285             :       // MIs[0] Operand 1
    1286             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlawt,
    1287             :       // MIs[0] a
    1288             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    1289             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
    1290             :       // MIs[0] b
    1291             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    1292             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
    1293             :       // MIs[0] acc
    1294             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    1295             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
    1296             :       // (intrinsic_wo_chain:i32 746:iPTR, GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)  =>  (t2SMLAWT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
    1297             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLAWT,
    1298             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    1299             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
    1300             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
    1301             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
    1302             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1303             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1304             :       GIR_EraseFromParent, /*InsnID*/0,
    1305             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1306             :       GIR_Done,
    1307             :     // Label 26: @2028
    1308             :     GIM_Try, /*On fail goto*//*Label 27*/ 2104,
    1309             :       GIM_CheckFeatures, GIFBS_HasNEON,
    1310             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    1311             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    1312             :       // MIs[0] Vd
    1313             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    1314             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    1315             :       // MIs[0] Operand 1
    1316             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
    1317             :       // MIs[0] src1
    1318             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    1319             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    1320             :       // MIs[0] Vn
    1321             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
    1322             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    1323             :       // MIs[0] Vm
    1324             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
    1325             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
    1326             :       // (intrinsic_wo_chain:v8i8 614:iPTR, DPR:v8i8:$src1, DPR:v8i8:$Vn, DPR:v8i8:$Vm)  =>  (VBSLd:v8i8 DPR:v8i8:$src1, DPR:v8i8:$Vn, DPR:v8i8:$Vm)
    1327             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLd,
    1328             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    1329             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    1330             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    1331             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
    1332             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1333             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1334             :       GIR_EraseFromParent, /*InsnID*/0,
    1335             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1336             :       GIR_Done,
    1337             :     // Label 27: @2104
    1338             :     GIM_Try, /*On fail goto*//*Label 28*/ 2180,
    1339             :       GIM_CheckFeatures, GIFBS_HasNEON,
    1340             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    1341             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    1342             :       // MIs[0] Vd
    1343             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    1344             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    1345             :       // MIs[0] Operand 1
    1346             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
    1347             :       // MIs[0] src1
    1348             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    1349             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    1350             :       // MIs[0] Vn
    1351             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    1352             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    1353             :       // MIs[0] Vm
    1354             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16,
    1355             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
    1356             :       // (intrinsic_wo_chain:v4i16 614:iPTR, DPR:v4i16:$src1, DPR:v4i16:$Vn, DPR:v4i16:$Vm)  =>  (VBSLd:v4i16 DPR:v4i16:$src1, DPR:v4i16:$Vn, DPR:v4i16:$Vm)
    1357             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLd,
    1358             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    1359             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    1360             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    1361             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
    1362             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1363             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1364             :       GIR_EraseFromParent, /*InsnID*/0,
    1365             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1366             :       GIR_Done,
    1367             :     // Label 28: @2180
    1368             :     GIM_Try, /*On fail goto*//*Label 29*/ 2256,
    1369             :       GIM_CheckFeatures, GIFBS_HasNEON,
    1370             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    1371             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    1372             :       // MIs[0] Vd
    1373             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    1374             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    1375             :       // MIs[0] Operand 1
    1376             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
    1377             :       // MIs[0] src1
    1378             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    1379             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    1380             :       // MIs[0] Vn
    1381             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    1382             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    1383             :       // MIs[0] Vm
    1384             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s32,
    1385             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
    1386             :       // (intrinsic_wo_chain:v2i32 614:iPTR, DPR:v2i32:$src1, DPR:v2i32:$Vn, DPR:v2i32:$Vm)  =>  (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$Vn, DPR:v2i32:$Vm)
    1387             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLd,
    1388             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    1389             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    1390             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    1391             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
    1392             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1393             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1394             :       GIR_EraseFromParent, /*InsnID*/0,
    1395             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1396             :       GIR_Done,
    1397             :     // Label 29: @2256
    1398             :     GIM_Try, /*On fail goto*//*Label 30*/ 2332,
    1399             :       GIM_CheckFeatures, GIFBS_HasNEON,
    1400             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    1401             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    1402             :       // MIs[0] Vd
    1403             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    1404             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    1405             :       // MIs[0] Operand 1
    1406             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
    1407             :       // MIs[0] src1
    1408             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    1409             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    1410             :       // MIs[0] Vn
    1411             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    1412             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    1413             :       // MIs[0] Vm
    1414             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s32,
    1415             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
    1416             :       // (intrinsic_wo_chain:v2f32 614:iPTR, DPR:v2f32:$src1, DPR:v2f32:$Vn, DPR:v2f32:$Vm)  =>  (VBSLd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$Vn, DPR:v2f32:$Vm)
    1417             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLd,
    1418             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    1419             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    1420             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    1421             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
    1422             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1423             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1424             :       GIR_EraseFromParent, /*InsnID*/0,
    1425             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1426             :       GIR_Done,
    1427             :     // Label 30: @2332
    1428             :     GIM_Try, /*On fail goto*//*Label 31*/ 2408,
    1429             :       GIM_CheckFeatures, GIFBS_HasNEON,
    1430             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    1431             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    1432             :       // MIs[0] Vd
    1433             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1434             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    1435             :       // MIs[0] Operand 1
    1436             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
    1437             :       // MIs[0] src1
    1438             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    1439             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    1440             :       // MIs[0] Vn
    1441             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    1442             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    1443             :       // MIs[0] Vm
    1444             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
    1445             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
    1446             :       // (intrinsic_wo_chain:v1i64 614:iPTR, DPR:v1i64:$src1, DPR:v1i64:$Vn, DPR:v1i64:$Vm)  =>  (VBSLd:v1i64 DPR:v1i64:$src1, DPR:v1i64:$Vn, DPR:v1i64:$Vm)
    1447             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLd,
    1448             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    1449             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    1450             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    1451             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
    1452             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1453             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1454             :       GIR_EraseFromParent, /*InsnID*/0,
    1455             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1456             :       GIR_Done,
    1457             :     // Label 31: @2408
    1458             :     GIM_Try, /*On fail goto*//*Label 32*/ 2484,
    1459             :       GIM_CheckFeatures, GIFBS_HasNEON,
    1460             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    1461             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    1462             :       // MIs[0] Vd
    1463             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    1464             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    1465             :       // MIs[0] Operand 1
    1466             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
    1467             :       // MIs[0] src1
    1468             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    1469             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    1470             :       // MIs[0] Vn
    1471             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
    1472             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    1473             :       // MIs[0] Vm
    1474             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
    1475             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
    1476             :       // (intrinsic_wo_chain:v16i8 614:iPTR, QPR:v16i8:$src1, QPR:v16i8:$Vn, QPR:v16i8:$Vm)  =>  (VBSLq:v16i8 QPR:v16i8:$src1, QPR:v16i8:$Vn, QPR:v16i8:$Vm)
    1477             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLq,
    1478             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    1479             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    1480             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    1481             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
    1482             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1483             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1484             :       GIR_EraseFromParent, /*InsnID*/0,
    1485             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1486             :       GIR_Done,
    1487             :     // Label 32: @2484
    1488             :     GIM_Try, /*On fail goto*//*Label 33*/ 2560,
    1489             :       GIM_CheckFeatures, GIFBS_HasNEON,
    1490             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    1491             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    1492             :       // MIs[0] Vd
    1493             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    1494             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    1495             :       // MIs[0] Operand 1
    1496             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
    1497             :       // MIs[0] src1
    1498             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    1499             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    1500             :       // MIs[0] Vn
    1501             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    1502             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    1503             :       // MIs[0] Vm
    1504             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
    1505             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
    1506             :       // (intrinsic_wo_chain:v8i16 614:iPTR, QPR:v8i16:$src1, QPR:v8i16:$Vn, QPR:v8i16:$Vm)  =>  (VBSLq:v8i16 QPR:v8i16:$src1, QPR:v8i16:$Vn, QPR:v8i16:$Vm)
    1507             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLq,
    1508             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    1509             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    1510             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    1511             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
    1512             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1513             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1514             :       GIR_EraseFromParent, /*InsnID*/0,
    1515             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1516             :       GIR_Done,
    1517             :     // Label 33: @2560
    1518             :     GIM_Try, /*On fail goto*//*Label 34*/ 2636,
    1519             :       GIM_CheckFeatures, GIFBS_HasNEON,
    1520             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    1521             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    1522             :       // MIs[0] Vd
    1523             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    1524             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    1525             :       // MIs[0] Operand 1
    1526             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
    1527             :       // MIs[0] src1
    1528             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    1529             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    1530             :       // MIs[0] Vn
    1531             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    1532             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    1533             :       // MIs[0] Vm
    1534             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
    1535             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
    1536             :       // (intrinsic_wo_chain:v4i32 614:iPTR, QPR:v4i32:$src1, QPR:v4i32:$Vn, QPR:v4i32:$Vm)  =>  (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$Vn, QPR:v4i32:$Vm)
    1537             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLq,
    1538             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    1539             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    1540             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    1541             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
    1542             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1543             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1544             :       GIR_EraseFromParent, /*InsnID*/0,
    1545             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1546             :       GIR_Done,
    1547             :     // Label 34: @2636
    1548             :     GIM_Try, /*On fail goto*//*Label 35*/ 2712,
    1549             :       GIM_CheckFeatures, GIFBS_HasNEON,
    1550             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    1551             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    1552             :       // MIs[0] Vd
    1553             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    1554             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    1555             :       // MIs[0] Operand 1
    1556             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
    1557             :       // MIs[0] src1
    1558             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    1559             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    1560             :       // MIs[0] Vn
    1561             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    1562             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    1563             :       // MIs[0] Vm
    1564             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
    1565             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
    1566             :       // (intrinsic_wo_chain:v4f32 614:iPTR, QPR:v4f32:$src1, QPR:v4f32:$Vn, QPR:v4f32:$Vm)  =>  (VBSLq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$Vn, QPR:v4f32:$Vm)
    1567             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLq,
    1568             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    1569             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    1570             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    1571             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
    1572             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1573             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1574             :       GIR_EraseFromParent, /*InsnID*/0,
    1575             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1576             :       GIR_Done,
    1577             :     // Label 35: @2712
    1578             :     GIM_Try, /*On fail goto*//*Label 36*/ 2788,
    1579             :       GIM_CheckFeatures, GIFBS_HasNEON,
    1580             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    1581             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    1582             :       // MIs[0] Vd
    1583             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    1584             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    1585             :       // MIs[0] Operand 1
    1586             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
    1587             :       // MIs[0] src1
    1588             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    1589             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    1590             :       // MIs[0] Vn
    1591             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
    1592             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    1593             :       // MIs[0] Vm
    1594             :       GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64,
    1595             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
    1596             :       // (intrinsic_wo_chain:v2i64 614:iPTR, QPR:v2i64:$src1, QPR:v2i64:$Vn, QPR:v2i64:$Vm)  =>  (VBSLq:v2i64 QPR:v2i64:$src1, QPR:v2i64:$Vn, QPR:v2i64:$Vm)
    1597             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLq,
    1598             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    1599             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    1600             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    1601             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
    1602             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1603             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1604             :       GIR_EraseFromParent, /*InsnID*/0,
    1605             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1606             :       GIR_Done,
    1607             :     // Label 36: @2788
    1608             :     GIM_Try, /*On fail goto*//*Label 37*/ 2900,
    1609             :       GIM_CheckFeatures, GIFBS_HasVFP4_HasDPVFP,
    1610             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    1611             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    1612             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    1613             :       GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
    1614             :       GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    1615             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FMA,
    1616             :       // MIs[0] Dd
    1617             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1618             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    1619             :       // MIs[0] Operand 1
    1620             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1621             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
    1622             :       // MIs[1] Operand 0
    1623             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    1624             :       // MIs[1] Dn
    1625             :       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    1626             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
    1627             :       // MIs[0] Dm
    1628             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    1629             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    1630             :       // MIs[0] Operand 3
    1631             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    1632             :       GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
    1633             :       // MIs[2] Operand 0
    1634             :       GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s64,
    1635             :       // MIs[2] Ddin
    1636             :       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
    1637             :       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
    1638             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    1639             :       GIM_CheckIsSafeToFold, /*InsnID*/2,
    1640             :       // (fma:f64 (fneg:f64 DPR:f64:$Dn), DPR:f64:$Dm, (fneg:f64 DPR:f64:$Ddin))  =>  (VFNMAD:f64 DPR:f64:$Ddin, DPR:f64:$Dn, DPR:f64:$Dm)
    1641             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAD,
    1642             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
    1643             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin
    1644             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
    1645             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
    1646             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1647             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1648             :       GIR_EraseFromParent, /*InsnID*/0,
    1649             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1650             :       GIR_Done,
    1651             :     // Label 37: @2900
    1652             :     GIM_Try, /*On fail goto*//*Label 38*/ 3012,
    1653             :       GIM_CheckFeatures, GIFBS_HasVFP4,
    1654             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    1655             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    1656             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    1657             :       GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
    1658             :       GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
    1659             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FMA,
    1660             :       // MIs[0] Sd
    1661             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    1662             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
    1663             :       // MIs[0] Operand 1
    1664             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    1665             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
    1666             :       // MIs[1] Operand 0
    1667             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    1668             :       // MIs[1] Sn
    1669             :       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
    1670             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
    1671             :       // MIs[0] Sm
    1672             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    1673             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
    1674             :       // MIs[0] Operand 3
    1675             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    1676             :       GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
    1677             :       // MIs[2] Operand 0
    1678             :       GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s32,
    1679             :       // MIs[2] Sdin
    1680             :       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    1681             :       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::SPRRegClassID,
    1682             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    1683             :       GIM_CheckIsSafeToFold, /*InsnID*/2,
    1684             :       // (fma:f32 (fneg:f32 SPR:f32:$Sn), SPR:f32:$Sm, (fneg:f32 SPR:f32:$Sdin))  =>  (VFNMAS:f32 SPR:f32:$Sdin, SPR:f32:$Sn, SPR:f32:$Sm)
    1685             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAS,
    1686             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
    1687             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
    1688             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
    1689             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
    1690             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1691             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1692             :       GIR_EraseFromParent, /*InsnID*/0,
    1693             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1694             :       GIR_Done,
    1695             :     // Label 38: @3012
    1696             :     GIM_Try, /*On fail goto*//*Label 39*/ 3104,
    1697             :       GIM_CheckFeatures, GIFBS_HasVFP4_HasDPVFP,
    1698             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    1699             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    1700             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    1701             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FMA,
    1702             :       // MIs[0] Dd
    1703             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1704             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    1705             :       // MIs[0] Operand 1
    1706             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1707             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
    1708             :       // MIs[1] Operand 0
    1709             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    1710             :       // MIs[1] Dn
    1711             :       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    1712             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
    1713             :       // MIs[0] Dm
    1714             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    1715             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    1716             :       // MIs[0] Ddin
    1717             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    1718             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    1719             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    1720             :       // (fma:f64 (fneg:f64 DPR:f64:$Dn), DPR:f64:$Dm, DPR:f64:$Ddin)  =>  (VFMSD:f64 DPR:f64:$Ddin, DPR:f64:$Dn, DPR:f64:$Dm)
    1721             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSD,
    1722             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
    1723             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ddin
    1724             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
    1725             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
    1726             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1727             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1728             :       GIR_EraseFromParent, /*InsnID*/0,
    1729             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1730             :       GIR_Done,
    1731             :     // Label 39: @3104
    1732             :     GIM_Try, /*On fail goto*//*Label 40*/ 3196,
    1733             :       GIM_CheckFeatures, GIFBS_HasVFP4,
    1734             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    1735             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    1736             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    1737             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FMA,
    1738             :       // MIs[0] Sd
    1739             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    1740             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
    1741             :       // MIs[0] Operand 1
    1742             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    1743             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
    1744             :       // MIs[1] Operand 0
    1745             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    1746             :       // MIs[1] Sn
    1747             :       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
    1748             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
    1749             :       // MIs[0] Sm
    1750             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    1751             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
    1752             :       // MIs[0] Sdin
    1753             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    1754             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::SPRRegClassID,
    1755             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    1756             :       // (fma:f32 (fneg:f32 SPR:f32:$Sn), SPR:f32:$Sm, SPR:f32:$Sdin)  =>  (VFMSS:f32 SPR:f32:$Sdin, SPR:f32:$Sn, SPR:f32:$Sm)
    1757             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSS,
    1758             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
    1759             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin
    1760             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
    1761             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
    1762             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1763             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1764             :       GIR_EraseFromParent, /*InsnID*/0,
    1765             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1766             :       GIR_Done,
    1767             :     // Label 40: @3196
    1768             :     GIM_Try, /*On fail goto*//*Label 41*/ 3288,
    1769             :       GIM_CheckFeatures, GIFBS_HasVFP4,
    1770             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    1771             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    1772             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    1773             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FMA,
    1774             :       // MIs[0] Vd
    1775             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    1776             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    1777             :       // MIs[0] Operand 1
    1778             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
    1779             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
    1780             :       // MIs[1] Operand 0
    1781             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s32,
    1782             :       // MIs[1] Vn
    1783             :       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
    1784             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
    1785             :       // MIs[0] Vm
    1786             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    1787             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    1788             :       // MIs[0] src1
    1789             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    1790             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    1791             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    1792             :       // (fma:v2f32 (fneg:v2f32 DPR:v2f32:$Vn), DPR:v2f32:$Vm, DPR:v2f32:$src1)  =>  (VFMSfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$Vn, DPR:v2f32:$Vm)
    1793             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSfd,
    1794             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    1795             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
    1796             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
    1797             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    1798             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1799             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1800             :       GIR_EraseFromParent, /*InsnID*/0,
    1801             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1802             :       GIR_Done,
    1803             :     // Label 41: @3288
    1804             :     GIM_Try, /*On fail goto*//*Label 42*/ 3380,
    1805             :       GIM_CheckFeatures, GIFBS_HasVFP4,
    1806             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    1807             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
    1808             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    1809             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FMA,
    1810             :       // MIs[0] Vd
    1811             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    1812             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    1813             :       // MIs[0] Operand 1
    1814             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
    1815             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
    1816             :       // MIs[1] Operand 0
    1817             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    1818             :       // MIs[1] Vn
    1819             :       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
    1820             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
    1821             :       // MIs[0] Vm
    1822             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    1823             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    1824             :       // MIs[0] src1
    1825             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    1826             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    1827             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    1828             :       // (fma:v4f32 (fneg:v4f32 QPR:v4f32:$Vn), QPR:v4f32:$Vm, QPR:v4f32:$src1)  =>  (VFMSfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$Vn, QPR:v4f32:$Vm)
    1829             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSfq,
    1830             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    1831             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
    1832             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
    1833             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    1834             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1835             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1836             :       GIR_EraseFromParent, /*InsnID*/0,
    1837             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1838             :       GIR_Done,
    1839             :     // Label 42: @3380
    1840             :     GIM_Try, /*On fail goto*//*Label 43*/ 3472,
    1841             :       GIM_CheckFeatures, GIFBS_HasVFP4_HasDPVFP,
    1842             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    1843             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    1844             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    1845             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FMA,
    1846             :       // MIs[0] Dd
    1847             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1848             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    1849             :       // MIs[0] Dn
    1850             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1851             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
    1852             :       // MIs[0] Operand 2
    1853             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    1854             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
    1855             :       // MIs[1] Operand 0
    1856             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    1857             :       // MIs[1] Dm
    1858             :       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    1859             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
    1860             :       // MIs[0] Ddin
    1861             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    1862             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    1863             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    1864             :       // (fma:f64 DPR:f64:$Dn, (fneg:f64 DPR:f64:$Dm), DPR:f64:$Ddin)  =>  (VFMSD:f64 DPR:f64:$Ddin, DPR:f64:$Dn, DPR:f64:$Dm)
    1865             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSD,
    1866             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
    1867             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ddin
    1868             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
    1869             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dm
    1870             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1871             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1872             :       GIR_EraseFromParent, /*InsnID*/0,
    1873             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1874             :       GIR_Done,
    1875             :     // Label 43: @3472
    1876             :     GIM_Try, /*On fail goto*//*Label 44*/ 3564,
    1877             :       GIM_CheckFeatures, GIFBS_HasVFP4,
    1878             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    1879             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    1880             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    1881             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FMA,
    1882             :       // MIs[0] Sd
    1883             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    1884             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
    1885             :       // MIs[0] Sn
    1886             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    1887             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
    1888             :       // MIs[0] Operand 2
    1889             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    1890             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
    1891             :       // MIs[1] Operand 0
    1892             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    1893             :       // MIs[1] Sm
    1894             :       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
    1895             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
    1896             :       // MIs[0] Sdin
    1897             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    1898             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::SPRRegClassID,
    1899             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    1900             :       // (fma:f32 SPR:f32:$Sn, (fneg:f32 SPR:f32:$Sm), SPR:f32:$Sdin)  =>  (VFMSS:f32 SPR:f32:$Sdin, SPR:f32:$Sn, SPR:f32:$Sm)
    1901             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSS,
    1902             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
    1903             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin
    1904             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
    1905             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm
    1906             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1907             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1908             :       GIR_EraseFromParent, /*InsnID*/0,
    1909             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1910             :       GIR_Done,
    1911             :     // Label 44: @3564
    1912             :     GIM_Try, /*On fail goto*//*Label 45*/ 3656,
    1913             :       GIM_CheckFeatures, GIFBS_HasVFP4_HasDPVFP,
    1914             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    1915             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    1916             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    1917             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FMA,
    1918             :       // MIs[0] Dd
    1919             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1920             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    1921             :       // MIs[0] Dn
    1922             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1923             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
    1924             :       // MIs[0] Dm
    1925             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    1926             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    1927             :       // MIs[0] Operand 3
    1928             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    1929             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
    1930             :       // MIs[1] Operand 0
    1931             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s64,
    1932             :       // MIs[1] Ddin
    1933             :       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
    1934             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
    1935             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    1936             :       // (fma:f64 DPR:f64:$Dn, DPR:f64:$Dm, (fneg:f64 DPR:f64:$Ddin))  =>  (VFNMSD:f64 DPR:f64:$Ddin, DPR:f64:$Dn, DPR:f64:$Dm)
    1937             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSD,
    1938             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
    1939             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ddin
    1940             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
    1941             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
    1942             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1943             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1944             :       GIR_EraseFromParent, /*InsnID*/0,
    1945             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1946             :       GIR_Done,
    1947             :     // Label 45: @3656
    1948             :     GIM_Try, /*On fail goto*//*Label 46*/ 3748,
    1949             :       GIM_CheckFeatures, GIFBS_HasVFP4,
    1950             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    1951             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    1952             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    1953             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FMA,
    1954             :       // MIs[0] Sd
    1955             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    1956             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
    1957             :       // MIs[0] Sn
    1958             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    1959             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
    1960             :       // MIs[0] Sm
    1961             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    1962             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
    1963             :       // MIs[0] Operand 3
    1964             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    1965             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
    1966             :       // MIs[1] Operand 0
    1967             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    1968             :       // MIs[1] Sdin
    1969             :       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
    1970             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
    1971             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    1972             :       // (fma:f32 SPR:f32:$Sn, SPR:f32:$Sm, (fneg:f32 SPR:f32:$Sdin))  =>  (VFNMSS:f32 SPR:f32:$Sdin, SPR:f32:$Sn, SPR:f32:$Sm)
    1973             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSS,
    1974             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
    1975             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin
    1976             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
    1977             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
    1978             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    1979             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    1980             :       GIR_EraseFromParent, /*InsnID*/0,
    1981             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1982             :       GIR_Done,
    1983             :     // Label 46: @3748
    1984             :     GIM_Try, /*On fail goto*//*Label 47*/ 3820,
    1985             :       GIM_CheckFeatures, GIFBS_HasVFP4_HasDPVFP,
    1986             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    1987             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FMA,
    1988             :       // MIs[0] Dd
    1989             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    1990             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    1991             :       // MIs[0] Dn
    1992             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1993             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
    1994             :       // MIs[0] Dm
    1995             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    1996             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    1997             :       // MIs[0] Ddin
    1998             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    1999             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    2000             :       // (fma:f64 DPR:f64:$Dn, DPR:f64:$Dm, DPR:f64:$Ddin)  =>  (VFMAD:f64 DPR:f64:$Ddin, DPR:f64:$Dn, DPR:f64:$Dm)
    2001             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAD,
    2002             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
    2003             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ddin
    2004             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
    2005             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
    2006             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    2007             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    2008             :       GIR_EraseFromParent, /*InsnID*/0,
    2009             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2010             :       GIR_Done,
    2011             :     // Label 47: @3820
    2012             :     GIM_Try, /*On fail goto*//*Label 48*/ 3892,
    2013             :       GIM_CheckFeatures, GIFBS_HasVFP4,
    2014             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2015             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FMA,
    2016             :       // MIs[0] Sd
    2017             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2018             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
    2019             :       // MIs[0] Sn
    2020             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    2021             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
    2022             :       // MIs[0] Sm
    2023             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2024             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
    2025             :       // MIs[0] Sdin
    2026             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2027             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::SPRRegClassID,
    2028             :       // (fma:f32 SPR:f32:$Sn, SPR:f32:$Sm, SPR:f32:$Sdin)  =>  (VFMAS:f32 SPR:f32:$Sdin, SPR:f32:$Sn, SPR:f32:$Sm)
    2029             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAS,
    2030             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
    2031             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin
    2032             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
    2033             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
    2034             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    2035             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    2036             :       GIR_EraseFromParent, /*InsnID*/0,
    2037             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2038             :       GIR_Done,
    2039             :     // Label 48: @3892
    2040             :     GIM_Try, /*On fail goto*//*Label 49*/ 3964,
    2041             :       GIM_CheckFeatures, GIFBS_HasVFP4,
    2042             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2043             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FMA,
    2044             :       // MIs[0] Vd
    2045             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    2046             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    2047             :       // MIs[0] Vn
    2048             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
    2049             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
    2050             :       // MIs[0] Vm
    2051             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    2052             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    2053             :       // MIs[0] src1
    2054             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    2055             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    2056             :       // (fma:v2f32 DPR:v2f32:$Vn, DPR:v2f32:$Vm, DPR:v2f32:$src1)  =>  (VFMAfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$Vn, DPR:v2f32:$Vm)
    2057             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAfd,
    2058             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    2059             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
    2060             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
    2061             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    2062             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    2063             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    2064             :       GIR_EraseFromParent, /*InsnID*/0,
    2065             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2066             :       GIR_Done,
    2067             :     // Label 49: @3964
    2068             :     GIM_Try, /*On fail goto*//*Label 50*/ 4036,
    2069             :       GIM_CheckFeatures, GIFBS_HasVFP4,
    2070             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2071             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FMA,
    2072             :       // MIs[0] Vd
    2073             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    2074             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    2075             :       // MIs[0] Vn
    2076             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
    2077             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
    2078             :       // MIs[0] Vm
    2079             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    2080             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    2081             :       // MIs[0] src1
    2082             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    2083             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    2084             :       // (fma:v4f32 QPR:v4f32:$Vn, QPR:v4f32:$Vm, QPR:v4f32:$src1)  =>  (VFMAfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$Vn, QPR:v4f32:$Vm)
    2085             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAfq,
    2086             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    2087             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
    2088             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
    2089             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    2090             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    2091             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    2092             :       GIR_EraseFromParent, /*InsnID*/0,
    2093             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2094             :       GIR_Done,
    2095             :     // Label 50: @4036
    2096             :     GIM_Try, /*On fail goto*//*Label 51*/ 4132,
    2097             :       GIM_CheckFeatures, GIFBS_IsARM,
    2098             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2099             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    2100             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2101             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    2102             :       // MIs[0] Rd
    2103             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2104             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    2105             :       // MIs[0] Operand 1
    2106             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd,
    2107             :       // MIs[0] Operand 2
    2108             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2109             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2110             :       // MIs[1] Operand 0
    2111             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    2112             :       // MIs[1] Operand 1
    2113             :       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd,
    2114             :       // MIs[1] Rm
    2115             :       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
    2116             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    2117             :       // MIs[1] Rm
    2118             :       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
    2119             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    2120             :       // MIs[0] Rn
    2121             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2122             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    2123             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    2124             :       // (intrinsic_wo_chain:i32 718:iPTR, (intrinsic_wo_chain:i32 718:iPTR, GPRnopc:i32:$Rm, GPRnopc:i32:$Rm), GPRnopc:i32:$Rn)  =>  (QDADD:i32 GPRnopc:i32:$Rm, GPRnopc:i32:$Rn)
    2125             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QDADD,
    2126             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    2127             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
    2128             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    2129             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    2130             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    2131             :       GIR_EraseFromParent, /*InsnID*/0,
    2132             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2133             :       GIR_Done,
    2134             :     // Label 51: @4132
    2135             :     GIM_Try, /*On fail goto*//*Label 52*/ 4228,
    2136             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    2137             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2138             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    2139             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2140             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    2141             :       // MIs[0] Rd
    2142             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2143             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    2144             :       // MIs[0] Operand 1
    2145             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd,
    2146             :       // MIs[0] Operand 2
    2147             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2148             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2149             :       // MIs[1] Operand 0
    2150             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    2151             :       // MIs[1] Operand 1
    2152             :       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd,
    2153             :       // MIs[1] Rm
    2154             :       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
    2155             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    2156             :       // MIs[1] Rm
    2157             :       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
    2158             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    2159             :       // MIs[0] Rn
    2160             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2161             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    2162             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    2163             :       // (intrinsic_wo_chain:i32 718:iPTR, (intrinsic_wo_chain:i32 718:iPTR, rGPR:i32:$Rm, rGPR:i32:$Rm), rGPR:i32:$Rn)  =>  (t2QDADD:i32 rGPR:i32:$Rm, rGPR:i32:$Rn)
    2164             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QDADD,
    2165             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    2166             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
    2167             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    2168             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    2169             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    2170             :       GIR_EraseFromParent, /*InsnID*/0,
    2171             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2172             :       GIR_Done,
    2173             :     // Label 52: @4228
    2174             :     GIM_Try, /*On fail goto*//*Label 53*/ 4328,
    2175             :       GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
    2176             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2177             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    2178             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2179             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    2180             :       // MIs[0] Vd
    2181             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    2182             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    2183             :       // MIs[0] Operand 1
    2184             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
    2185             :       // MIs[0] Operand 2
    2186             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    2187             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2188             :       // MIs[1] Operand 0
    2189             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s16,
    2190             :       // MIs[1] Operand 1
    2191             :       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
    2192             :       // MIs[1] Vn
    2193             :       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
    2194             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    2195             :       // MIs[1] Vm
    2196             :       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
    2197             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    2198             :       // MIs[0] src1
    2199             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    2200             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    2201             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    2202             :       // (intrinsic_wo_chain:v4i16 661:iPTR, (intrinsic_wo_chain:v4i16 669:iPTR, DPR:v4i16:$Vn, DPR:v4i16:$Vm), DPR:v4i16:$src1)  =>  (VQRDMLAHv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$Vn, DPR:v4i16:$Vm)
    2203             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv4i16,
    2204             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    2205             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
    2206             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
    2207             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
    2208             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    2209             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    2210             :       GIR_EraseFromParent, /*InsnID*/0,
    2211             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2212             :       GIR_Done,
    2213             :     // Label 53: @4328
    2214             :     GIM_Try, /*On fail goto*//*Label 54*/ 4428,
    2215             :       GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
    2216             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2217             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    2218             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2219             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    2220             :       // MIs[0] Vd
    2221             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    2222             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    2223             :       // MIs[0] Operand 1
    2224             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
    2225             :       // MIs[0] Operand 2
    2226             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    2227             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2228             :       // MIs[1] Operand 0
    2229             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s32,
    2230             :       // MIs[1] Operand 1
    2231             :       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
    2232             :       // MIs[1] Vn
    2233             :       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
    2234             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    2235             :       // MIs[1] Vm
    2236             :       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
    2237             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    2238             :       // MIs[0] src1
    2239             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    2240             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    2241             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    2242             :       // (intrinsic_wo_chain:v2i32 661:iPTR, (intrinsic_wo_chain:v2i32 669:iPTR, DPR:v2i32:$Vn, DPR:v2i32:$Vm), DPR:v2i32:$src1)  =>  (VQRDMLAHv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$Vn, DPR:v2i32:$Vm)
    2243             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv2i32,
    2244             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    2245             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
    2246             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
    2247             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
    2248             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    2249             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    2250             :       GIR_EraseFromParent, /*InsnID*/0,
    2251             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2252             :       GIR_Done,
    2253             :     // Label 54: @4428
    2254             :     GIM_Try, /*On fail goto*//*Label 55*/ 4528,
    2255             :       GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
    2256             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2257             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    2258             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2259             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    2260             :       // MIs[0] Vd
    2261             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    2262             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    2263             :       // MIs[0] Operand 1
    2264             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
    2265             :       // MIs[0] Operand 2
    2266             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    2267             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2268             :       // MIs[1] Operand 0
    2269             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s16,
    2270             :       // MIs[1] Operand 1
    2271             :       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
    2272             :       // MIs[1] Vn
    2273             :       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
    2274             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    2275             :       // MIs[1] Vm
    2276             :       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
    2277             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    2278             :       // MIs[0] src1
    2279             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    2280             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    2281             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    2282             :       // (intrinsic_wo_chain:v8i16 661:iPTR, (intrinsic_wo_chain:v8i16 669:iPTR, QPR:v8i16:$Vn, QPR:v8i16:$Vm), QPR:v8i16:$src1)  =>  (VQRDMLAHv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$Vn, QPR:v8i16:$Vm)
    2283             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv8i16,
    2284             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    2285             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
    2286             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
    2287             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
    2288             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    2289             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    2290             :       GIR_EraseFromParent, /*InsnID*/0,
    2291             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2292             :       GIR_Done,
    2293             :     // Label 55: @4528
    2294             :     GIM_Try, /*On fail goto*//*Label 56*/ 4628,
    2295             :       GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
    2296             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2297             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    2298             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2299             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    2300             :       // MIs[0] Vd
    2301             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    2302             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    2303             :       // MIs[0] Operand 1
    2304             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
    2305             :       // MIs[0] Operand 2
    2306             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    2307             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2308             :       // MIs[1] Operand 0
    2309             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    2310             :       // MIs[1] Operand 1
    2311             :       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
    2312             :       // MIs[1] Vn
    2313             :       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
    2314             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    2315             :       // MIs[1] Vm
    2316             :       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
    2317             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    2318             :       // MIs[0] src1
    2319             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    2320             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    2321             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    2322             :       // (intrinsic_wo_chain:v4i32 661:iPTR, (intrinsic_wo_chain:v4i32 669:iPTR, QPR:v4i32:$Vn, QPR:v4i32:$Vm), QPR:v4i32:$src1)  =>  (VQRDMLAHv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$Vn, QPR:v4i32:$Vm)
    2323             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv4i32,
    2324             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    2325             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
    2326             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
    2327             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
    2328             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    2329             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    2330             :       GIR_EraseFromParent, /*InsnID*/0,
    2331             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2332             :       GIR_Done,
    2333             :     // Label 56: @4628
    2334             :     GIM_Try, /*On fail goto*//*Label 57*/ 4726,
    2335             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2336             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    2337             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2338             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    2339             :       // MIs[0] Vd
    2340             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    2341             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    2342             :       // MIs[0] Operand 1
    2343             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
    2344             :       // MIs[0] Operand 2
    2345             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    2346             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2347             :       // MIs[1] Operand 0
    2348             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    2349             :       // MIs[1] Operand 1
    2350             :       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqdmull,
    2351             :       // MIs[1] Vn
    2352             :       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
    2353             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    2354             :       // MIs[1] Vm
    2355             :       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
    2356             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    2357             :       // MIs[0] src1
    2358             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    2359             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    2360             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    2361             :       // (intrinsic_wo_chain:v4i32 661:iPTR, (intrinsic_wo_chain:v4i32 664:iPTR, DPR:v4i16:$Vn, DPR:v4i16:$Vm), QPR:v4i32:$src1)  =>  (VQDMLALv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$Vn, DPR:v4i16:$Vm)
    2362             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMLALv4i32,
    2363             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    2364             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
    2365             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
    2366             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
    2367             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    2368             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    2369             :       GIR_EraseFromParent, /*InsnID*/0,
    2370             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2371             :       GIR_Done,
    2372             :     // Label 57: @4726
    2373             :     GIM_Try, /*On fail goto*//*Label 58*/ 4824,
    2374             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2375             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
    2376             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2377             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    2378             :       // MIs[0] Vd
    2379             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    2380             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    2381             :       // MIs[0] Operand 1
    2382             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
    2383             :       // MIs[0] Operand 2
    2384             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    2385             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2386             :       // MIs[1] Operand 0
    2387             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s64,
    2388             :       // MIs[1] Operand 1
    2389             :       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqdmull,
    2390             :       // MIs[1] Vn
    2391             :       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
    2392             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    2393             :       // MIs[1] Vm
    2394             :       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
    2395             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    2396             :       // MIs[0] src1
    2397             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
    2398             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    2399             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    2400             :       // (intrinsic_wo_chain:v2i64 661:iPTR, (intrinsic_wo_chain:v2i64 664:iPTR, DPR:v2i32:$Vn, DPR:v2i32:$Vm), QPR:v2i64:$src1)  =>  (VQDMLALv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$Vn, DPR:v2i32:$Vm)
    2401             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMLALv2i64,
    2402             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    2403             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
    2404             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
    2405             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
    2406             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    2407             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    2408             :       GIR_EraseFromParent, /*InsnID*/0,
    2409             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2410             :       GIR_Done,
    2411             :     // Label 58: @4824
    2412             :     GIM_Try, /*On fail goto*//*Label 59*/ 4920,
    2413             :       GIM_CheckFeatures, GIFBS_IsARM,
    2414             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2415             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2416             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2417             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    2418             :       // MIs[0] Rd
    2419             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2420             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    2421             :       // MIs[0] Operand 1
    2422             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub,
    2423             :       // MIs[0] Rm
    2424             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2425             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    2426             :       // MIs[0] Operand 3
    2427             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2428             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2429             :       // MIs[1] Operand 0
    2430             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    2431             :       // MIs[1] Operand 1
    2432             :       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd,
    2433             :       // MIs[1] Rn
    2434             :       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
    2435             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    2436             :       // MIs[1] Rn
    2437             :       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
    2438             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    2439             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    2440             :       // (intrinsic_wo_chain:i32 723:iPTR, GPRnopc:i32:$Rm, (intrinsic_wo_chain:i32 718:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rn))  =>  (QDSUB:i32 GPRnopc:i32:$Rm, GPRnopc:i32:$Rn)
    2441             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QDSUB,
    2442             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    2443             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
    2444             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    2445             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    2446             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    2447             :       GIR_EraseFromParent, /*InsnID*/0,
    2448             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2449             :       GIR_Done,
    2450             :     // Label 59: @4920
    2451             :     GIM_Try, /*On fail goto*//*Label 60*/ 5016,
    2452             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    2453             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2454             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2455             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2456             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    2457             :       // MIs[0] Rd
    2458             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2459             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    2460             :       // MIs[0] Operand 1
    2461             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub,
    2462             :       // MIs[0] Rm
    2463             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2464             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    2465             :       // MIs[0] Operand 3
    2466             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2467             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2468             :       // MIs[1] Operand 0
    2469             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    2470             :       // MIs[1] Operand 1
    2471             :       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd,
    2472             :       // MIs[1] Rn
    2473             :       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
    2474             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    2475             :       // MIs[1] Rn
    2476             :       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
    2477             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    2478             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    2479             :       // (intrinsic_wo_chain:i32 723:iPTR, rGPR:i32:$Rm, (intrinsic_wo_chain:i32 718:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rn))  =>  (t2QDSUB:i32 rGPR:i32:$Rm, rGPR:i32:$Rn)
    2480             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QDSUB,
    2481             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    2482             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
    2483             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
    2484             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    2485             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    2486             :       GIR_EraseFromParent, /*InsnID*/0,
    2487             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2488             :       GIR_Done,
    2489             :     // Label 60: @5016
    2490             :     GIM_Try, /*On fail goto*//*Label 61*/ 5116,
    2491             :       GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
    2492             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2493             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2494             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2495             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    2496             :       // MIs[0] Vd
    2497             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    2498             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    2499             :       // MIs[0] Operand 1
    2500             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
    2501             :       // MIs[0] src1
    2502             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    2503             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    2504             :       // MIs[0] Operand 3
    2505             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    2506             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2507             :       // MIs[1] Operand 0
    2508             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s16,
    2509             :       // MIs[1] Operand 1
    2510             :       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
    2511             :       // MIs[1] Vn
    2512             :       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
    2513             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    2514             :       // MIs[1] Vm
    2515             :       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
    2516             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    2517             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    2518             :       // (intrinsic_wo_chain:v4i16 661:iPTR, DPR:v4i16:$src1, (intrinsic_wo_chain:v4i16 669:iPTR, DPR:v4i16:$Vn, DPR:v4i16:$Vm))  =>  (VQRDMLAHv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$Vn, DPR:v4i16:$Vm)
    2519             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv4i16,
    2520             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    2521             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    2522             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
    2523             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
    2524             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    2525             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    2526             :       GIR_EraseFromParent, /*InsnID*/0,
    2527             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2528             :       GIR_Done,
    2529             :     // Label 61: @5116
    2530             :     GIM_Try, /*On fail goto*//*Label 62*/ 5216,
    2531             :       GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
    2532             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2533             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2534             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2535             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    2536             :       // MIs[0] Vd
    2537             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    2538             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    2539             :       // MIs[0] Operand 1
    2540             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
    2541             :       // MIs[0] src1
    2542             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    2543             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    2544             :       // MIs[0] Operand 3
    2545             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    2546             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2547             :       // MIs[1] Operand 0
    2548             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s32,
    2549             :       // MIs[1] Operand 1
    2550             :       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
    2551             :       // MIs[1] Vn
    2552             :       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
    2553             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    2554             :       // MIs[1] Vm
    2555             :       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
    2556             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    2557             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    2558             :       // (intrinsic_wo_chain:v2i32 661:iPTR, DPR:v2i32:$src1, (intrinsic_wo_chain:v2i32 669:iPTR, DPR:v2i32:$Vn, DPR:v2i32:$Vm))  =>  (VQRDMLAHv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$Vn, DPR:v2i32:$Vm)
    2559             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv2i32,
    2560             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    2561             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    2562             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
    2563             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
    2564             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    2565             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    2566             :       GIR_EraseFromParent, /*InsnID*/0,
    2567             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2568             :       GIR_Done,
    2569             :     // Label 62: @5216
    2570             :     GIM_Try, /*On fail goto*//*Label 63*/ 5316,
    2571             :       GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
    2572             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2573             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2574             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2575             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    2576             :       // MIs[0] Vd
    2577             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    2578             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    2579             :       // MIs[0] Operand 1
    2580             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
    2581             :       // MIs[0] src1
    2582             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    2583             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    2584             :       // MIs[0] Operand 3
    2585             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    2586             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2587             :       // MIs[1] Operand 0
    2588             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s16,
    2589             :       // MIs[1] Operand 1
    2590             :       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
    2591             :       // MIs[1] Vn
    2592             :       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
    2593             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    2594             :       // MIs[1] Vm
    2595             :       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
    2596             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    2597             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    2598             :       // (intrinsic_wo_chain:v8i16 661:iPTR, QPR:v8i16:$src1, (intrinsic_wo_chain:v8i16 669:iPTR, QPR:v8i16:$Vn, QPR:v8i16:$Vm))  =>  (VQRDMLAHv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$Vn, QPR:v8i16:$Vm)
    2599             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv8i16,
    2600             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    2601             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    2602             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
    2603             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
    2604             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    2605             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    2606             :       GIR_EraseFromParent, /*InsnID*/0,
    2607             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2608             :       GIR_Done,
    2609             :     // Label 63: @5316
    2610             :     GIM_Try, /*On fail goto*//*Label 64*/ 5416,
    2611             :       GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
    2612             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2613             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2614             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2615             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    2616             :       // MIs[0] Vd
    2617             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    2618             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    2619             :       // MIs[0] Operand 1
    2620             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
    2621             :       // MIs[0] src1
    2622             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    2623             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    2624             :       // MIs[0] Operand 3
    2625             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    2626             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2627             :       // MIs[1] Operand 0
    2628             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    2629             :       // MIs[1] Operand 1
    2630             :       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
    2631             :       // MIs[1] Vn
    2632             :       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
    2633             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    2634             :       // MIs[1] Vm
    2635             :       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
    2636             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    2637             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    2638             :       // (intrinsic_wo_chain:v4i32 661:iPTR, QPR:v4i32:$src1, (intrinsic_wo_chain:v4i32 669:iPTR, QPR:v4i32:$Vn, QPR:v4i32:$Vm))  =>  (VQRDMLAHv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$Vn, QPR:v4i32:$Vm)
    2639             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv4i32,
    2640             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    2641             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    2642             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
    2643             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
    2644             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    2645             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    2646             :       GIR_EraseFromParent, /*InsnID*/0,
    2647             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2648             :       GIR_Done,
    2649             :     // Label 64: @5416
    2650             :     GIM_Try, /*On fail goto*//*Label 65*/ 5516,
    2651             :       GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
    2652             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2653             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2654             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2655             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    2656             :       // MIs[0] Vd
    2657             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    2658             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    2659             :       // MIs[0] Operand 1
    2660             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubs,
    2661             :       // MIs[0] src1
    2662             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    2663             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    2664             :       // MIs[0] Operand 3
    2665             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    2666             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2667             :       // MIs[1] Operand 0
    2668             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s16,
    2669             :       // MIs[1] Operand 1
    2670             :       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
    2671             :       // MIs[1] Vn
    2672             :       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
    2673             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    2674             :       // MIs[1] Vm
    2675             :       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
    2676             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    2677             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    2678             :       // (intrinsic_wo_chain:v4i16 681:iPTR, DPR:v4i16:$src1, (intrinsic_wo_chain:v4i16 669:iPTR, DPR:v4i16:$Vn, DPR:v4i16:$Vm))  =>  (VQRDMLSHv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$Vn, DPR:v4i16:$Vm)
    2679             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLSHv4i16,
    2680             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    2681             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    2682             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
    2683             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
    2684             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    2685             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    2686             :       GIR_EraseFromParent, /*InsnID*/0,
    2687             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2688             :       GIR_Done,
    2689             :     // Label 65: @5516
    2690             :     GIM_Try, /*On fail goto*//*Label 66*/ 5616,
    2691             :       GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
    2692             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2693             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2694             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2695             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    2696             :       // MIs[0] Vd
    2697             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    2698             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    2699             :       // MIs[0] Operand 1
    2700             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubs,
    2701             :       // MIs[0] src1
    2702             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    2703             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    2704             :       // MIs[0] Operand 3
    2705             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    2706             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2707             :       // MIs[1] Operand 0
    2708             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s32,
    2709             :       // MIs[1] Operand 1
    2710             :       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
    2711             :       // MIs[1] Vn
    2712             :       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
    2713             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    2714             :       // MIs[1] Vm
    2715             :       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
    2716             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    2717             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    2718             :       // (intrinsic_wo_chain:v2i32 681:iPTR, DPR:v2i32:$src1, (intrinsic_wo_chain:v2i32 669:iPTR, DPR:v2i32:$Vn, DPR:v2i32:$Vm))  =>  (VQRDMLSHv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$Vn, DPR:v2i32:$Vm)
    2719             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLSHv2i32,
    2720             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    2721             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    2722             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
    2723             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
    2724             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    2725             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    2726             :       GIR_EraseFromParent, /*InsnID*/0,
    2727             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2728             :       GIR_Done,
    2729             :     // Label 66: @5616
    2730             :     GIM_Try, /*On fail goto*//*Label 67*/ 5716,
    2731             :       GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
    2732             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2733             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2734             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2735             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    2736             :       // MIs[0] Vd
    2737             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    2738             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    2739             :       // MIs[0] Operand 1
    2740             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubs,
    2741             :       // MIs[0] src1
    2742             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    2743             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    2744             :       // MIs[0] Operand 3
    2745             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    2746             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2747             :       // MIs[1] Operand 0
    2748             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v8s16,
    2749             :       // MIs[1] Operand 1
    2750             :       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
    2751             :       // MIs[1] Vn
    2752             :       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
    2753             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    2754             :       // MIs[1] Vm
    2755             :       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
    2756             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    2757             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    2758             :       // (intrinsic_wo_chain:v8i16 681:iPTR, QPR:v8i16:$src1, (intrinsic_wo_chain:v8i16 669:iPTR, QPR:v8i16:$Vn, QPR:v8i16:$Vm))  =>  (VQRDMLSHv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$Vn, QPR:v8i16:$Vm)
    2759             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLSHv8i16,
    2760             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    2761             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    2762             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
    2763             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
    2764             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    2765             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    2766             :       GIR_EraseFromParent, /*InsnID*/0,
    2767             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2768             :       GIR_Done,
    2769             :     // Label 67: @5716
    2770             :     GIM_Try, /*On fail goto*//*Label 68*/ 5816,
    2771             :       GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
    2772             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2773             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2774             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2775             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    2776             :       // MIs[0] Vd
    2777             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    2778             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    2779             :       // MIs[0] Operand 1
    2780             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubs,
    2781             :       // MIs[0] src1
    2782             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    2783             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    2784             :       // MIs[0] Operand 3
    2785             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    2786             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2787             :       // MIs[1] Operand 0
    2788             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    2789             :       // MIs[1] Operand 1
    2790             :       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
    2791             :       // MIs[1] Vn
    2792             :       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
    2793             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    2794             :       // MIs[1] Vm
    2795             :       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
    2796             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    2797             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    2798             :       // (intrinsic_wo_chain:v4i32 681:iPTR, QPR:v4i32:$src1, (intrinsic_wo_chain:v4i32 669:iPTR, QPR:v4i32:$Vn, QPR:v4i32:$Vm))  =>  (VQRDMLSHv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$Vn, QPR:v4i32:$Vm)
    2799             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLSHv4i32,
    2800             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    2801             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    2802             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
    2803             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
    2804             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    2805             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    2806             :       GIR_EraseFromParent, /*InsnID*/0,
    2807             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2808             :       GIR_Done,
    2809             :     // Label 68: @5816
    2810             :     GIM_Try, /*On fail goto*//*Label 69*/ 5914,
    2811             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2812             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2813             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2814             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    2815             :       // MIs[0] Vd
    2816             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    2817             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    2818             :       // MIs[0] Operand 1
    2819             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
    2820             :       // MIs[0] src1
    2821             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    2822             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    2823             :       // MIs[0] Operand 3
    2824             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    2825             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2826             :       // MIs[1] Operand 0
    2827             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    2828             :       // MIs[1] Operand 1
    2829             :       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqdmull,
    2830             :       // MIs[1] Vn
    2831             :       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
    2832             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    2833             :       // MIs[1] Vm
    2834             :       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
    2835             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    2836             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    2837             :       // (intrinsic_wo_chain:v4i32 661:iPTR, QPR:v4i32:$src1, (intrinsic_wo_chain:v4i32 664:iPTR, DPR:v4i16:$Vn, DPR:v4i16:$Vm))  =>  (VQDMLALv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$Vn, DPR:v4i16:$Vm)
    2838             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMLALv4i32,
    2839             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    2840             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    2841             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
    2842             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
    2843             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    2844             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    2845             :       GIR_EraseFromParent, /*InsnID*/0,
    2846             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2847             :       GIR_Done,
    2848             :     // Label 69: @5914
    2849             :     GIM_Try, /*On fail goto*//*Label 70*/ 6012,
    2850             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2851             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2852             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2853             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    2854             :       // MIs[0] Vd
    2855             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    2856             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    2857             :       // MIs[0] Operand 1
    2858             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
    2859             :       // MIs[0] src1
    2860             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    2861             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    2862             :       // MIs[0] Operand 3
    2863             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
    2864             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2865             :       // MIs[1] Operand 0
    2866             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s64,
    2867             :       // MIs[1] Operand 1
    2868             :       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqdmull,
    2869             :       // MIs[1] Vn
    2870             :       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
    2871             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    2872             :       // MIs[1] Vm
    2873             :       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
    2874             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    2875             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    2876             :       // (intrinsic_wo_chain:v2i64 661:iPTR, QPR:v2i64:$src1, (intrinsic_wo_chain:v2i64 664:iPTR, DPR:v2i32:$Vn, DPR:v2i32:$Vm))  =>  (VQDMLALv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$Vn, DPR:v2i32:$Vm)
    2877             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMLALv2i64,
    2878             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    2879             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    2880             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
    2881             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
    2882             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    2883             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    2884             :       GIR_EraseFromParent, /*InsnID*/0,
    2885             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2886             :       GIR_Done,
    2887             :     // Label 70: @6012
    2888             :     GIM_Try, /*On fail goto*//*Label 71*/ 6110,
    2889             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2890             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2891             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2892             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    2893             :       // MIs[0] Vd
    2894             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    2895             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    2896             :       // MIs[0] Operand 1
    2897             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubs,
    2898             :       // MIs[0] src1
    2899             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    2900             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    2901             :       // MIs[0] Operand 3
    2902             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    2903             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2904             :       // MIs[1] Operand 0
    2905             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s32,
    2906             :       // MIs[1] Operand 1
    2907             :       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqdmull,
    2908             :       // MIs[1] Vn
    2909             :       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
    2910             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    2911             :       // MIs[1] Vm
    2912             :       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
    2913             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    2914             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    2915             :       // (intrinsic_wo_chain:v4i32 681:iPTR, QPR:v4i32:$src1, (intrinsic_wo_chain:v4i32 664:iPTR, DPR:v4i16:$Vn, DPR:v4i16:$Vm))  =>  (VQDMLSLv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$Vn, DPR:v4i16:$Vm)
    2916             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMLSLv4i32,
    2917             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    2918             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    2919             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
    2920             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
    2921             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    2922             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    2923             :       GIR_EraseFromParent, /*InsnID*/0,
    2924             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2925             :       GIR_Done,
    2926             :     // Label 71: @6110
    2927             :     GIM_Try, /*On fail goto*//*Label 72*/ 6208,
    2928             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2929             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2930             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2931             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    2932             :       // MIs[0] Vd
    2933             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    2934             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    2935             :       // MIs[0] Operand 1
    2936             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubs,
    2937             :       // MIs[0] src1
    2938             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    2939             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    2940             :       // MIs[0] Operand 3
    2941             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
    2942             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2943             :       // MIs[1] Operand 0
    2944             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v2s64,
    2945             :       // MIs[1] Operand 1
    2946             :       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqdmull,
    2947             :       // MIs[1] Vn
    2948             :       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
    2949             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    2950             :       // MIs[1] Vm
    2951             :       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
    2952             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    2953             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    2954             :       // (intrinsic_wo_chain:v2i64 681:iPTR, QPR:v2i64:$src1, (intrinsic_wo_chain:v2i64 664:iPTR, DPR:v2i32:$Vn, DPR:v2i32:$Vm))  =>  (VQDMLSLv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$Vn, DPR:v2i32:$Vm)
    2955             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMLSLv2i64,
    2956             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    2957             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    2958             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
    2959             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
    2960             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    2961             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    2962             :       GIR_EraseFromParent, /*InsnID*/0,
    2963             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2964             :       GIR_Done,
    2965             :     // Label 72: @6208
    2966             :     GIM_Try, /*On fail goto*//*Label 73*/ 6304,
    2967             :       GIM_CheckFeatures, GIFBS_IsARM,
    2968             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2969             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    2970             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    2971             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    2972             :       // MIs[0] Rd
    2973             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2974             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    2975             :       // MIs[0] Operand 1
    2976             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd,
    2977             :       // MIs[0] Rn
    2978             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2979             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    2980             :       // MIs[0] Operand 3
    2981             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2982             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    2983             :       // MIs[1] Operand 0
    2984             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    2985             :       // MIs[1] Operand 1
    2986             :       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd,
    2987             :       // MIs[1] Rm
    2988             :       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
    2989             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    2990             :       // MIs[1] Rm
    2991             :       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
    2992             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    2993             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    2994             :       // (intrinsic_wo_chain:i32 718:iPTR, GPRnopc:i32:$Rn, (intrinsic_wo_chain:i32 718:iPTR, GPRnopc:i32:$Rm, GPRnopc:i32:$Rm))  =>  (QDADD:i32 GPRnopc:i32:$Rm, GPRnopc:i32:$Rn)
    2995             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QDADD,
    2996             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    2997             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
    2998             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    2999             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3000             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3001             :       GIR_EraseFromParent, /*InsnID*/0,
    3002             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3003             :       GIR_Done,
    3004             :     // Label 73: @6304
    3005             :     GIM_Try, /*On fail goto*//*Label 74*/ 6400,
    3006             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    3007             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3008             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3009             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
    3010             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3011             :       // MIs[0] Rd
    3012             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3013             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    3014             :       // MIs[0] Operand 1
    3015             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd,
    3016             :       // MIs[0] Rn
    3017             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3018             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    3019             :       // MIs[0] Operand 3
    3020             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3021             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
    3022             :       // MIs[1] Operand 0
    3023             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    3024             :       // MIs[1] Operand 1
    3025             :       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd,
    3026             :       // MIs[1] Rm
    3027             :       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
    3028             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    3029             :       // MIs[1] Rm
    3030             :       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
    3031             :       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    3032             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    3033             :       // (intrinsic_wo_chain:i32 718:iPTR, rGPR:i32:$Rn, (intrinsic_wo_chain:i32 718:iPTR, rGPR:i32:$Rm, rGPR:i32:$Rm))  =>  (t2QDADD:i32 rGPR:i32:$Rm, rGPR:i32:$Rn)
    3034             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QDADD,
    3035             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3036             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
    3037             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    3038             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3039             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3040             :       GIR_EraseFromParent, /*InsnID*/0,
    3041             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3042             :       GIR_Done,
    3043             :     // Label 74: @6400
    3044             :     GIM_Try, /*On fail goto*//*Label 75*/ 6475,
    3045             :       GIM_CheckFeatures, GIFBS_HasNEON,
    3046             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3047             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3048             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3049             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3050             :       // MIs[0] Vd
    3051             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    3052             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    3053             :       // MIs[0] Operand 1
    3054             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxs,
    3055             :       // MIs[0] Vm
    3056             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    3057             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    3058             :       // MIs[0] SIMM
    3059             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3060             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    3061             :       // MIs[1] Operand 0
    3062             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    3063             :       // MIs[1] Operand 1
    3064             :       // No operand predicates
    3065             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    3066             :       // (intrinsic_wo_chain:v2i32 618:iPTR, DPR:v2f32:$Vm, (imm:i32):$SIMM)  =>  (VCVTf2xsd:v2i32 DPR:v2f32:$Vm, (imm:i32):$SIMM)
    3067             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2xsd,
    3068             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    3069             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    3070             :       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
    3071             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3072             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3073             :       GIR_EraseFromParent, /*InsnID*/0,
    3074             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3075             :       GIR_Done,
    3076             :     // Label 75: @6475
    3077             :     GIM_Try, /*On fail goto*//*Label 76*/ 6550,
    3078             :       GIM_CheckFeatures, GIFBS_HasNEON,
    3079             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3080             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3081             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3082             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3083             :       // MIs[0] Vd
    3084             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    3085             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    3086             :       // MIs[0] Operand 1
    3087             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxu,
    3088             :       // MIs[0] Vm
    3089             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    3090             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    3091             :       // MIs[0] SIMM
    3092             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3093             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    3094             :       // MIs[1] Operand 0
    3095             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    3096             :       // MIs[1] Operand 1
    3097             :       // No operand predicates
    3098             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    3099             :       // (intrinsic_wo_chain:v2i32 619:iPTR, DPR:v2f32:$Vm, (imm:i32):$SIMM)  =>  (VCVTf2xud:v2i32 DPR:v2f32:$Vm, (imm:i32):$SIMM)
    3100             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2xud,
    3101             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    3102             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    3103             :       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
    3104             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3105             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3106             :       GIR_EraseFromParent, /*InsnID*/0,
    3107             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3108             :       GIR_Done,
    3109             :     // Label 76: @6550
    3110             :     GIM_Try, /*On fail goto*//*Label 77*/ 6625,
    3111             :       GIM_CheckFeatures, GIFBS_HasNEON,
    3112             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3113             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3114             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3115             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3116             :       // MIs[0] Vd
    3117             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    3118             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    3119             :       // MIs[0] Operand 1
    3120             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxs2fp,
    3121             :       // MIs[0] Vm
    3122             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    3123             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    3124             :       // MIs[0] SIMM
    3125             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3126             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    3127             :       // MIs[1] Operand 0
    3128             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    3129             :       // MIs[1] Operand 1
    3130             :       // No operand predicates
    3131             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    3132             :       // (intrinsic_wo_chain:v2f32 621:iPTR, DPR:v2i32:$Vm, (imm:i32):$SIMM)  =>  (VCVTxs2fd:v2f32 DPR:v2i32:$Vm, (imm:i32):$SIMM)
    3133             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxs2fd,
    3134             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    3135             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    3136             :       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
    3137             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3138             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3139             :       GIR_EraseFromParent, /*InsnID*/0,
    3140             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3141             :       GIR_Done,
    3142             :     // Label 77: @6625
    3143             :     GIM_Try, /*On fail goto*//*Label 78*/ 6700,
    3144             :       GIM_CheckFeatures, GIFBS_HasNEON,
    3145             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3146             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3147             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3148             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3149             :       // MIs[0] Vd
    3150             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    3151             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    3152             :       // MIs[0] Operand 1
    3153             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxu2fp,
    3154             :       // MIs[0] Vm
    3155             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    3156             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    3157             :       // MIs[0] SIMM
    3158             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3159             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    3160             :       // MIs[1] Operand 0
    3161             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    3162             :       // MIs[1] Operand 1
    3163             :       // No operand predicates
    3164             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    3165             :       // (intrinsic_wo_chain:v2f32 622:iPTR, DPR:v2i32:$Vm, (imm:i32):$SIMM)  =>  (VCVTxu2fd:v2f32 DPR:v2i32:$Vm, (imm:i32):$SIMM)
    3166             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxu2fd,
    3167             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    3168             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    3169             :       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
    3170             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3171             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3172             :       GIR_EraseFromParent, /*InsnID*/0,
    3173             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3174             :       GIR_Done,
    3175             :     // Label 78: @6700
    3176             :     GIM_Try, /*On fail goto*//*Label 79*/ 6775,
    3177             :       GIM_CheckFeatures, GIFBS_HasNEON_HasFullFP16,
    3178             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3179             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3180             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3181             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3182             :       // MIs[0] Vd
    3183             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    3184             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    3185             :       // MIs[0] Operand 1
    3186             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxs,
    3187             :       // MIs[0] Vm
    3188             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    3189             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    3190             :       // MIs[0] SIMM
    3191             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3192             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    3193             :       // MIs[1] Operand 0
    3194             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    3195             :       // MIs[1] Operand 1
    3196             :       // No operand predicates
    3197             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    3198             :       // (intrinsic_wo_chain:v4i16 618:iPTR, DPR:v4f16:$Vm, (imm:i32):$SIMM)  =>  (VCVTh2xsd:v4i16 DPR:v4f16:$Vm, (imm:i32):$SIMM)
    3199             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2xsd,
    3200             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    3201             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    3202             :       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
    3203             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3204             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3205             :       GIR_EraseFromParent, /*InsnID*/0,
    3206             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3207             :       GIR_Done,
    3208             :     // Label 79: @6775
    3209             :     GIM_Try, /*On fail goto*//*Label 80*/ 6850,
    3210             :       GIM_CheckFeatures, GIFBS_HasNEON_HasFullFP16,
    3211             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3212             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3213             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3214             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3215             :       // MIs[0] Vd
    3216             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    3217             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    3218             :       // MIs[0] Operand 1
    3219             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxu,
    3220             :       // MIs[0] Vm
    3221             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    3222             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    3223             :       // MIs[0] SIMM
    3224             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3225             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    3226             :       // MIs[1] Operand 0
    3227             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    3228             :       // MIs[1] Operand 1
    3229             :       // No operand predicates
    3230             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    3231             :       // (intrinsic_wo_chain:v4i16 619:iPTR, DPR:v4f16:$Vm, (imm:i32):$SIMM)  =>  (VCVTh2xud:v4i16 DPR:v4f16:$Vm, (imm:i32):$SIMM)
    3232             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2xud,
    3233             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    3234             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    3235             :       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
    3236             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3237             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3238             :       GIR_EraseFromParent, /*InsnID*/0,
    3239             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3240             :       GIR_Done,
    3241             :     // Label 80: @6850
    3242             :     GIM_Try, /*On fail goto*//*Label 81*/ 6925,
    3243             :       GIM_CheckFeatures, GIFBS_HasNEON_HasFullFP16,
    3244             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3245             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3246             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3247             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3248             :       // MIs[0] Vd
    3249             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    3250             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    3251             :       // MIs[0] Operand 1
    3252             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxs2fp,
    3253             :       // MIs[0] Vm
    3254             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    3255             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    3256             :       // MIs[0] SIMM
    3257             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3258             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    3259             :       // MIs[1] Operand 0
    3260             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    3261             :       // MIs[1] Operand 1
    3262             :       // No operand predicates
    3263             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    3264             :       // (intrinsic_wo_chain:v4f16 621:iPTR, DPR:v4i16:$Vm, (imm:i32):$SIMM)  =>  (VCVTxs2hd:v4f16 DPR:v4i16:$Vm, (imm:i32):$SIMM)
    3265             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxs2hd,
    3266             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    3267             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    3268             :       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
    3269             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3270             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3271             :       GIR_EraseFromParent, /*InsnID*/0,
    3272             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3273             :       GIR_Done,
    3274             :     // Label 81: @6925
    3275             :     GIM_Try, /*On fail goto*//*Label 82*/ 7000,
    3276             :       GIM_CheckFeatures, GIFBS_HasNEON_HasFullFP16,
    3277             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3278             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3279             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3280             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3281             :       // MIs[0] Vd
    3282             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    3283             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    3284             :       // MIs[0] Operand 1
    3285             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxu2fp,
    3286             :       // MIs[0] Vm
    3287             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    3288             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    3289             :       // MIs[0] SIMM
    3290             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3291             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    3292             :       // MIs[1] Operand 0
    3293             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    3294             :       // MIs[1] Operand 1
    3295             :       // No operand predicates
    3296             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    3297             :       // (intrinsic_wo_chain:v4f16 622:iPTR, DPR:v4i16:$Vm, (imm:i32):$SIMM)  =>  (VCVTxu2hd:v4f16 DPR:v4i16:$Vm, (imm:i32):$SIMM)
    3298             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxu2hd,
    3299             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    3300             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    3301             :       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
    3302             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3303             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3304             :       GIR_EraseFromParent, /*InsnID*/0,
    3305             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3306             :       GIR_Done,
    3307             :     // Label 82: @7000
    3308             :     GIM_Try, /*On fail goto*//*Label 83*/ 7075,
    3309             :       GIM_CheckFeatures, GIFBS_HasNEON,
    3310             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3311             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3312             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3313             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3314             :       // MIs[0] Vd
    3315             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    3316             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    3317             :       // MIs[0] Operand 1
    3318             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxs,
    3319             :       // MIs[0] Vm
    3320             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    3321             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    3322             :       // MIs[0] SIMM
    3323             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3324             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    3325             :       // MIs[1] Operand 0
    3326             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    3327             :       // MIs[1] Operand 1
    3328             :       // No operand predicates
    3329             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    3330             :       // (intrinsic_wo_chain:v4i32 618:iPTR, QPR:v4f32:$Vm, (imm:i32):$SIMM)  =>  (VCVTf2xsq:v4i32 QPR:v4f32:$Vm, (imm:i32):$SIMM)
    3331             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2xsq,
    3332             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    3333             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    3334             :       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
    3335             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3336             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3337             :       GIR_EraseFromParent, /*InsnID*/0,
    3338             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3339             :       GIR_Done,
    3340             :     // Label 83: @7075
    3341             :     GIM_Try, /*On fail goto*//*Label 84*/ 7150,
    3342             :       GIM_CheckFeatures, GIFBS_HasNEON,
    3343             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3344             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3345             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3346             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3347             :       // MIs[0] Vd
    3348             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    3349             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    3350             :       // MIs[0] Operand 1
    3351             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxu,
    3352             :       // MIs[0] Vm
    3353             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    3354             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    3355             :       // MIs[0] SIMM
    3356             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3357             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    3358             :       // MIs[1] Operand 0
    3359             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    3360             :       // MIs[1] Operand 1
    3361             :       // No operand predicates
    3362             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    3363             :       // (intrinsic_wo_chain:v4i32 619:iPTR, QPR:v4f32:$Vm, (imm:i32):$SIMM)  =>  (VCVTf2xuq:v4i32 QPR:v4f32:$Vm, (imm:i32):$SIMM)
    3364             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2xuq,
    3365             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    3366             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    3367             :       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
    3368             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3369             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3370             :       GIR_EraseFromParent, /*InsnID*/0,
    3371             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3372             :       GIR_Done,
    3373             :     // Label 84: @7150
    3374             :     GIM_Try, /*On fail goto*//*Label 85*/ 7225,
    3375             :       GIM_CheckFeatures, GIFBS_HasNEON,
    3376             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3377             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3378             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3379             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3380             :       // MIs[0] Vd
    3381             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    3382             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    3383             :       // MIs[0] Operand 1
    3384             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxs2fp,
    3385             :       // MIs[0] Vm
    3386             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    3387             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    3388             :       // MIs[0] SIMM
    3389             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3390             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    3391             :       // MIs[1] Operand 0
    3392             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    3393             :       // MIs[1] Operand 1
    3394             :       // No operand predicates
    3395             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    3396             :       // (intrinsic_wo_chain:v4f32 621:iPTR, QPR:v4i32:$Vm, (imm:i32):$SIMM)  =>  (VCVTxs2fq:v4f32 QPR:v4i32:$Vm, (imm:i32):$SIMM)
    3397             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxs2fq,
    3398             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    3399             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    3400             :       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
    3401             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3402             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3403             :       GIR_EraseFromParent, /*InsnID*/0,
    3404             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3405             :       GIR_Done,
    3406             :     // Label 85: @7225
    3407             :     GIM_Try, /*On fail goto*//*Label 86*/ 7300,
    3408             :       GIM_CheckFeatures, GIFBS_HasNEON,
    3409             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3410             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3411             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3412             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3413             :       // MIs[0] Vd
    3414             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    3415             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    3416             :       // MIs[0] Operand 1
    3417             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxu2fp,
    3418             :       // MIs[0] Vm
    3419             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    3420             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    3421             :       // MIs[0] SIMM
    3422             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3423             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    3424             :       // MIs[1] Operand 0
    3425             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    3426             :       // MIs[1] Operand 1
    3427             :       // No operand predicates
    3428             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    3429             :       // (intrinsic_wo_chain:v4f32 622:iPTR, QPR:v4i32:$Vm, (imm:i32):$SIMM)  =>  (VCVTxu2fq:v4f32 QPR:v4i32:$Vm, (imm:i32):$SIMM)
    3430             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxu2fq,
    3431             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    3432             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    3433             :       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
    3434             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3435             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3436             :       GIR_EraseFromParent, /*InsnID*/0,
    3437             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3438             :       GIR_Done,
    3439             :     // Label 86: @7300
    3440             :     GIM_Try, /*On fail goto*//*Label 87*/ 7375,
    3441             :       GIM_CheckFeatures, GIFBS_HasNEON_HasFullFP16,
    3442             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3443             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3444             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3445             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3446             :       // MIs[0] Vd
    3447             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    3448             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    3449             :       // MIs[0] Operand 1
    3450             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxs,
    3451             :       // MIs[0] Vm
    3452             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    3453             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    3454             :       // MIs[0] SIMM
    3455             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3456             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    3457             :       // MIs[1] Operand 0
    3458             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    3459             :       // MIs[1] Operand 1
    3460             :       // No operand predicates
    3461             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    3462             :       // (intrinsic_wo_chain:v8i16 618:iPTR, QPR:v8f16:$Vm, (imm:i32):$SIMM)  =>  (VCVTh2xsq:v8i16 QPR:v8f16:$Vm, (imm:i32):$SIMM)
    3463             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2xsq,
    3464             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    3465             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    3466             :       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
    3467             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3468             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3469             :       GIR_EraseFromParent, /*InsnID*/0,
    3470             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3471             :       GIR_Done,
    3472             :     // Label 87: @7375
    3473             :     GIM_Try, /*On fail goto*//*Label 88*/ 7450,
    3474             :       GIM_CheckFeatures, GIFBS_HasNEON_HasFullFP16,
    3475             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3476             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3477             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3478             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3479             :       // MIs[0] Vd
    3480             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    3481             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    3482             :       // MIs[0] Operand 1
    3483             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxu,
    3484             :       // MIs[0] Vm
    3485             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    3486             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    3487             :       // MIs[0] SIMM
    3488             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3489             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    3490             :       // MIs[1] Operand 0
    3491             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    3492             :       // MIs[1] Operand 1
    3493             :       // No operand predicates
    3494             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    3495             :       // (intrinsic_wo_chain:v8i16 619:iPTR, QPR:v8f16:$Vm, (imm:i32):$SIMM)  =>  (VCVTh2xuq:v8i16 QPR:v8f16:$Vm, (imm:i32):$SIMM)
    3496             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2xuq,
    3497             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    3498             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    3499             :       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
    3500             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3501             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3502             :       GIR_EraseFromParent, /*InsnID*/0,
    3503             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3504             :       GIR_Done,
    3505             :     // Label 88: @7450
    3506             :     GIM_Try, /*On fail goto*//*Label 89*/ 7525,
    3507             :       GIM_CheckFeatures, GIFBS_HasNEON_HasFullFP16,
    3508             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3509             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3510             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3511             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3512             :       // MIs[0] Vd
    3513             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    3514             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    3515             :       // MIs[0] Operand 1
    3516             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxs2fp,
    3517             :       // MIs[0] Vm
    3518             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    3519             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    3520             :       // MIs[0] SIMM
    3521             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3522             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    3523             :       // MIs[1] Operand 0
    3524             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    3525             :       // MIs[1] Operand 1
    3526             :       // No operand predicates
    3527             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    3528             :       // (intrinsic_wo_chain:v8f16 621:iPTR, QPR:v8i16:$Vm, (imm:i32):$SIMM)  =>  (VCVTxs2hq:v8f16 QPR:v8i16:$Vm, (imm:i32):$SIMM)
    3529             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxs2hq,
    3530             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    3531             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    3532             :       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
    3533             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3534             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3535             :       GIR_EraseFromParent, /*InsnID*/0,
    3536             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3537             :       GIR_Done,
    3538             :     // Label 89: @7525
    3539             :     GIM_Try, /*On fail goto*//*Label 90*/ 7600,
    3540             :       GIM_CheckFeatures, GIFBS_HasNEON_HasFullFP16,
    3541             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3542             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3543             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3544             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3545             :       // MIs[0] Vd
    3546             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    3547             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    3548             :       // MIs[0] Operand 1
    3549             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxu2fp,
    3550             :       // MIs[0] Vm
    3551             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    3552             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    3553             :       // MIs[0] SIMM
    3554             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3555             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    3556             :       // MIs[1] Operand 0
    3557             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    3558             :       // MIs[1] Operand 1
    3559             :       // No operand predicates
    3560             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    3561             :       // (intrinsic_wo_chain:v8f16 622:iPTR, QPR:v8i16:$Vm, (imm:i32):$SIMM)  =>  (VCVTxu2hq:v8f16 QPR:v8i16:$Vm, (imm:i32):$SIMM)
    3562             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxu2hq,
    3563             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    3564             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    3565             :       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
    3566             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3567             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3568             :       GIR_EraseFromParent, /*InsnID*/0,
    3569             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3570             :       GIR_Done,
    3571             :     // Label 90: @7600
    3572             :     GIM_Try, /*On fail goto*//*Label 91*/ 7678,
    3573             :       GIM_CheckFeatures, GIFBS_IsARM_HasV6,
    3574             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3575             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3576             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3577             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3578             :       // MIs[0] Rd
    3579             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3580             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    3581             :       // MIs[0] Operand 1
    3582             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usat16,
    3583             :       // MIs[0] a
    3584             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3585             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    3586             :       // MIs[0] pos
    3587             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3588             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    3589             :       GIM_CheckImmPredicate, /*MI*/1, /*Predicate*/GIPFP_Predicate_imm0_15,
    3590             :       // MIs[1] Operand 0
    3591             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    3592             :       // MIs[1] Operand 1
    3593             :       // No operand predicates
    3594             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    3595             :       // (intrinsic_wo_chain:i32 796:iPTR, GPRnopc:i32:$a, (imm:i32)<<P:Predicate_imm0_15>>:$pos)  =>  (USAT16:i32 (imm:i32)<<P:Predicate_imm0_15>>:$pos, GPRnopc:i32:$a)
    3596             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USAT16,
    3597             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3598             :       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
    3599             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
    3600             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3601             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3602             :       GIR_EraseFromParent, /*InsnID*/0,
    3603             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3604             :       GIR_Done,
    3605             :     // Label 91: @7678
    3606             :     GIM_Try, /*On fail goto*//*Label 92*/ 7756,
    3607             :       GIM_CheckFeatures, GIFBS_IsThumb2,
    3608             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3609             :       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
    3610             :       GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
    3611             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3612             :       // MIs[0] Rd
    3613             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3614             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    3615             :       // MIs[0] Operand 1
    3616             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usat16,
    3617             :       // MIs[0] a
    3618             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3619             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
    3620             :       // MIs[0] pos
    3621             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3622             :       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
    3623             :       GIM_CheckImmPredicate, /*MI*/1, /*Predicate*/GIPFP_Predicate_imm0_15,
    3624             :       // MIs[1] Operand 0
    3625             :       GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
    3626             :       // MIs[1] Operand 1
    3627             :       // No operand predicates
    3628             :       GIM_CheckIsSafeToFold, /*InsnID*/1,
    3629             :       // (intrinsic_wo_chain:i32 796:iPTR, GPR:i32:$a, (imm:i32)<<P:Predicate_imm0_15>>:$pos)  =>  (t2USAT16:i32 (imm:i32)<<P:Predicate_imm0_15>>:$pos, GPR:i32:$a)
    3630             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USAT16,
    3631             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3632             :       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
    3633             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
    3634             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3635             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3636             :       GIR_EraseFromParent, /*InsnID*/0,
    3637             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3638             :       GIR_Done,
    3639             :     // Label 92: @7756
    3640             :     GIM_Try, /*On fail goto*//*Label 93*/ 7820,
    3641             :       GIM_CheckFeatures, GIFBS_IsARM,
    3642             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3643             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3644             :       // MIs[0] Rd
    3645             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3646             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    3647             :       // MIs[0] Operand 1
    3648             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd8,
    3649             :       // MIs[0] Rn
    3650             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3651             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    3652             :       // MIs[0] Rm
    3653             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3654             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    3655             :       // (intrinsic_wo_chain:i32 720:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)  =>  (QADD8:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)
    3656             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QADD8,
    3657             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3658             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    3659             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    3660             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3661             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3662             :       GIR_EraseFromParent, /*InsnID*/0,
    3663             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3664             :       GIR_Done,
    3665             :     // Label 93: @7820
    3666             :     GIM_Try, /*On fail goto*//*Label 94*/ 7884,
    3667             :       GIM_CheckFeatures, GIFBS_IsARM,
    3668             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3669             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3670             :       // MIs[0] Rd
    3671             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3672             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    3673             :       // MIs[0] Operand 1
    3674             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd16,
    3675             :       // MIs[0] Rn
    3676             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3677             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    3678             :       // MIs[0] Rm
    3679             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3680             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    3681             :       // (intrinsic_wo_chain:i32 719:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)  =>  (QADD16:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)
    3682             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QADD16,
    3683             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3684             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    3685             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    3686             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3687             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3688             :       GIR_EraseFromParent, /*InsnID*/0,
    3689             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3690             :       GIR_Done,
    3691             :     // Label 94: @7884
    3692             :     GIM_Try, /*On fail goto*//*Label 95*/ 7948,
    3693             :       GIM_CheckFeatures, GIFBS_IsARM,
    3694             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3695             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3696             :       // MIs[0] Rd
    3697             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3698             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    3699             :       // MIs[0] Operand 1
    3700             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub16,
    3701             :       // MIs[0] Rn
    3702             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3703             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    3704             :       // MIs[0] Rm
    3705             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3706             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    3707             :       // (intrinsic_wo_chain:i32 724:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)  =>  (QSUB16:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)
    3708             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QSUB16,
    3709             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3710             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    3711             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    3712             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3713             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3714             :       GIR_EraseFromParent, /*InsnID*/0,
    3715             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3716             :       GIR_Done,
    3717             :     // Label 95: @7948
    3718             :     GIM_Try, /*On fail goto*//*Label 96*/ 8012,
    3719             :       GIM_CheckFeatures, GIFBS_IsARM,
    3720             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3721             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3722             :       // MIs[0] Rd
    3723             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3724             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    3725             :       // MIs[0] Operand 1
    3726             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub8,
    3727             :       // MIs[0] Rn
    3728             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3729             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    3730             :       // MIs[0] Rm
    3731             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3732             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    3733             :       // (intrinsic_wo_chain:i32 725:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)  =>  (QSUB8:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)
    3734             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QSUB8,
    3735             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3736             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    3737             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    3738             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3739             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3740             :       GIR_EraseFromParent, /*InsnID*/0,
    3741             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3742             :       GIR_Done,
    3743             :     // Label 96: @8012
    3744             :     GIM_Try, /*On fail goto*//*Label 97*/ 8076,
    3745             :       GIM_CheckFeatures, GIFBS_IsARM,
    3746             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3747             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3748             :       // MIs[0] Rd
    3749             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3750             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    3751             :       // MIs[0] Operand 1
    3752             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub,
    3753             :       // MIs[0] Rm
    3754             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3755             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    3756             :       // MIs[0] Rn
    3757             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3758             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    3759             :       // (intrinsic_wo_chain:i32 723:iPTR, GPRnopc:i32:$Rm, GPRnopc:i32:$Rn)  =>  (QSUB:i32 GPRnopc:i32:$Rm, GPRnopc:i32:$Rn)
    3760             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QSUB,
    3761             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3762             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
    3763             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    3764             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3765             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3766             :       GIR_EraseFromParent, /*InsnID*/0,
    3767             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3768             :       GIR_Done,
    3769             :     // Label 97: @8076
    3770             :     GIM_Try, /*On fail goto*//*Label 98*/ 8140,
    3771             :       GIM_CheckFeatures, GIFBS_IsARM,
    3772             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3773             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3774             :       // MIs[0] Rd
    3775             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3776             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    3777             :       // MIs[0] Operand 1
    3778             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd,
    3779             :       // MIs[0] Rm
    3780             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3781             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    3782             :       // MIs[0] Rn
    3783             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3784             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    3785             :       // (intrinsic_wo_chain:i32 718:iPTR, GPRnopc:i32:$Rm, GPRnopc:i32:$Rn)  =>  (QADD:i32 GPRnopc:i32:$Rm, GPRnopc:i32:$Rn)
    3786             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QADD,
    3787             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3788             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
    3789             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
    3790             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3791             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3792             :       GIR_EraseFromParent, /*InsnID*/0,
    3793             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3794             :       GIR_Done,
    3795             :     // Label 98: @8140
    3796             :     GIM_Try, /*On fail goto*//*Label 99*/ 8204,
    3797             :       GIM_CheckFeatures, GIFBS_IsARM,
    3798             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3799             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3800             :       // MIs[0] Rd
    3801             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3802             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    3803             :       // MIs[0] Operand 1
    3804             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqadd16,
    3805             :       // MIs[0] Rn
    3806             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3807             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    3808             :       // MIs[0] Rm
    3809             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3810             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    3811             :       // (intrinsic_wo_chain:i32 787:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)  =>  (UQADD16:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)
    3812             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQADD16,
    3813             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3814             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    3815             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    3816             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3817             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3818             :       GIR_EraseFromParent, /*InsnID*/0,
    3819             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3820             :       GIR_Done,
    3821             :     // Label 99: @8204
    3822             :     GIM_Try, /*On fail goto*//*Label 100*/ 8268,
    3823             :       GIM_CheckFeatures, GIFBS_IsARM,
    3824             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3825             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3826             :       // MIs[0] Rd
    3827             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3828             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    3829             :       // MIs[0] Operand 1
    3830             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqadd8,
    3831             :       // MIs[0] Rn
    3832             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3833             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    3834             :       // MIs[0] Rm
    3835             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3836             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    3837             :       // (intrinsic_wo_chain:i32 788:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)  =>  (UQADD8:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)
    3838             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQADD8,
    3839             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3840             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    3841             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    3842             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3843             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3844             :       GIR_EraseFromParent, /*InsnID*/0,
    3845             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3846             :       GIR_Done,
    3847             :     // Label 100: @8268
    3848             :     GIM_Try, /*On fail goto*//*Label 101*/ 8332,
    3849             :       GIM_CheckFeatures, GIFBS_IsARM,
    3850             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3851             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3852             :       // MIs[0] Rd
    3853             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3854             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    3855             :       // MIs[0] Operand 1
    3856             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsub16,
    3857             :       // MIs[0] Rn
    3858             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3859             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    3860             :       // MIs[0] Rm
    3861             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3862             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    3863             :       // (intrinsic_wo_chain:i32 791:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)  =>  (UQSUB16:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)
    3864             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQSUB16,
    3865             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3866             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    3867             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    3868             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3869             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3870             :       GIR_EraseFromParent, /*InsnID*/0,
    3871             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3872             :       GIR_Done,
    3873             :     // Label 101: @8332
    3874             :     GIM_Try, /*On fail goto*//*Label 102*/ 8396,
    3875             :       GIM_CheckFeatures, GIFBS_IsARM,
    3876             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3877             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3878             :       // MIs[0] Rd
    3879             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3880             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    3881             :       // MIs[0] Operand 1
    3882             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsub8,
    3883             :       // MIs[0] Rn
    3884             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3885             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    3886             :       // MIs[0] Rm
    3887             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3888             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    3889             :       // (intrinsic_wo_chain:i32 792:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)  =>  (UQSUB8:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)
    3890             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQSUB8,
    3891             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3892             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    3893             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    3894             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3895             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3896             :       GIR_EraseFromParent, /*InsnID*/0,
    3897             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3898             :       GIR_Done,
    3899             :     // Label 102: @8396
    3900             :     GIM_Try, /*On fail goto*//*Label 103*/ 8460,
    3901             :       GIM_CheckFeatures, GIFBS_IsARM,
    3902             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3903             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3904             :       // MIs[0] Rd
    3905             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3906             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    3907             :       // MIs[0] Operand 1
    3908             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qasx,
    3909             :       // MIs[0] Rn
    3910             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3911             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    3912             :       // MIs[0] Rm
    3913             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3914             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    3915             :       // (intrinsic_wo_chain:i32 721:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)  =>  (QASX:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)
    3916             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QASX,
    3917             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3918             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    3919             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    3920             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3921             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3922             :       GIR_EraseFromParent, /*InsnID*/0,
    3923             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3924             :       GIR_Done,
    3925             :     // Label 103: @8460
    3926             :     GIM_Try, /*On fail goto*//*Label 104*/ 8524,
    3927             :       GIM_CheckFeatures, GIFBS_IsARM,
    3928             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3929             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3930             :       // MIs[0] Rd
    3931             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3932             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    3933             :       // MIs[0] Operand 1
    3934             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsax,
    3935             :       // MIs[0] Rn
    3936             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3937             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    3938             :       // MIs[0] Rm
    3939             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3940             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    3941             :       // (intrinsic_wo_chain:i32 722:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)  =>  (QSAX:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)
    3942             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QSAX,
    3943             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3944             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    3945             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    3946             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3947             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3948             :       GIR_EraseFromParent, /*InsnID*/0,
    3949             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3950             :       GIR_Done,
    3951             :     // Label 104: @8524
    3952             :     GIM_Try, /*On fail goto*//*Label 105*/ 8588,
    3953             :       GIM_CheckFeatures, GIFBS_IsARM,
    3954             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3955             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3956             :       // MIs[0] Rd
    3957             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3958             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    3959             :       // MIs[0] Operand 1
    3960             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqasx,
    3961             :       // MIs[0] Rn
    3962             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3963             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    3964             :       // MIs[0] Rm
    3965             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3966             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    3967             :       // (intrinsic_wo_chain:i32 789:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)  =>  (UQASX:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)
    3968             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQASX,
    3969             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3970             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    3971             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    3972             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3973             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    3974             :       GIR_EraseFromParent, /*InsnID*/0,
    3975             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3976             :       GIR_Done,
    3977             :     // Label 105: @8588
    3978             :     GIM_Try, /*On fail goto*//*Label 106*/ 8652,
    3979             :       GIM_CheckFeatures, GIFBS_IsARM,
    3980             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    3981             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    3982             :       // MIs[0] Rd
    3983             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3984             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    3985             :       // MIs[0] Operand 1
    3986             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsax,
    3987             :       // MIs[0] Rn
    3988             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3989             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    3990             :       // MIs[0] Rm
    3991             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3992             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    3993             :       // (intrinsic_wo_chain:i32 790:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)  =>  (UQSAX:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)
    3994             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQSAX,
    3995             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    3996             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    3997             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    3998             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    3999             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4000             :       GIR_EraseFromParent, /*InsnID*/0,
    4001             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4002             :       GIR_Done,
    4003             :     // Label 106: @8652
    4004             :     GIM_Try, /*On fail goto*//*Label 107*/ 8716,
    4005             :       GIM_CheckFeatures, GIFBS_IsARM,
    4006             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4007             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4008             :       // MIs[0] Rd
    4009             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4010             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    4011             :       // MIs[0] Operand 1
    4012             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shasx,
    4013             :       // MIs[0] Rn
    4014             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4015             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    4016             :       // MIs[0] Rm
    4017             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4018             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    4019             :       // (intrinsic_wo_chain:i32 733:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)  =>  (SHASX:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)
    4020             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHASX,
    4021             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4022             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4023             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4024             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4025             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4026             :       GIR_EraseFromParent, /*InsnID*/0,
    4027             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4028             :       GIR_Done,
    4029             :     // Label 107: @8716
    4030             :     GIM_Try, /*On fail goto*//*Label 108*/ 8780,
    4031             :       GIM_CheckFeatures, GIFBS_IsARM,
    4032             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4033             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4034             :       // MIs[0] Rd
    4035             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4036             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    4037             :       // MIs[0] Operand 1
    4038             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shadd16,
    4039             :       // MIs[0] Rn
    4040             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4041             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    4042             :       // MIs[0] Rm
    4043             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4044             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    4045             :       // (intrinsic_wo_chain:i32 731:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)  =>  (SHADD16:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)
    4046             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHADD16,
    4047             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4048             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4049             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4050             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4051             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4052             :       GIR_EraseFromParent, /*InsnID*/0,
    4053             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4054             :       GIR_Done,
    4055             :     // Label 108: @8780
    4056             :     GIM_Try, /*On fail goto*//*Label 109*/ 8844,
    4057             :       GIM_CheckFeatures, GIFBS_IsARM,
    4058             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4059             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4060             :       // MIs[0] Rd
    4061             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4062             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    4063             :       // MIs[0] Operand 1
    4064             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shadd8,
    4065             :       // MIs[0] Rn
    4066             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4067             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    4068             :       // MIs[0] Rm
    4069             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4070             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    4071             :       // (intrinsic_wo_chain:i32 732:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)  =>  (SHADD8:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)
    4072             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHADD8,
    4073             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4074             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4075             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4076             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4077             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4078             :       GIR_EraseFromParent, /*InsnID*/0,
    4079             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4080             :       GIR_Done,
    4081             :     // Label 109: @8844
    4082             :     GIM_Try, /*On fail goto*//*Label 110*/ 8908,
    4083             :       GIM_CheckFeatures, GIFBS_IsARM,
    4084             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4085             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4086             :       // MIs[0] Rd
    4087             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4088             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    4089             :       // MIs[0] Operand 1
    4090             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsax,
    4091             :       // MIs[0] Rn
    4092             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4093             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    4094             :       // MIs[0] Rm
    4095             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4096             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    4097             :       // (intrinsic_wo_chain:i32 734:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)  =>  (SHSAX:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)
    4098             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHSAX,
    4099             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4100             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4101             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4102             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4103             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4104             :       GIR_EraseFromParent, /*InsnID*/0,
    4105             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4106             :       GIR_Done,
    4107             :     // Label 110: @8908
    4108             :     GIM_Try, /*On fail goto*//*Label 111*/ 8972,
    4109             :       GIM_CheckFeatures, GIFBS_IsARM,
    4110             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4111             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4112             :       // MIs[0] Rd
    4113             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4114             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    4115             :       // MIs[0] Operand 1
    4116             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsub16,
    4117             :       // MIs[0] Rn
    4118             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4119             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    4120             :       // MIs[0] Rm
    4121             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4122             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    4123             :       // (intrinsic_wo_chain:i32 735:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)  =>  (SHSUB16:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)
    4124             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHSUB16,
    4125             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4126             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4127             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4128             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4129             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4130             :       GIR_EraseFromParent, /*InsnID*/0,
    4131             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4132             :       GIR_Done,
    4133             :     // Label 111: @8972
    4134             :     GIM_Try, /*On fail goto*//*Label 112*/ 9036,
    4135             :       GIM_CheckFeatures, GIFBS_IsARM,
    4136             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4137             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4138             :       // MIs[0] Rd
    4139             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4140             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    4141             :       // MIs[0] Operand 1
    4142             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsub8,
    4143             :       // MIs[0] Rn
    4144             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4145             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    4146             :       // MIs[0] Rm
    4147             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4148             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    4149             :       // (intrinsic_wo_chain:i32 736:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)  =>  (SHSUB8:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)
    4150             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHSUB8,
    4151             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4152             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4153             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4154             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4155             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4156             :       GIR_EraseFromParent, /*InsnID*/0,
    4157             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4158             :       GIR_Done,
    4159             :     // Label 112: @9036
    4160             :     GIM_Try, /*On fail goto*//*Label 113*/ 9100,
    4161             :       GIM_CheckFeatures, GIFBS_IsARM,
    4162             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4163             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4164             :       // MIs[0] Rd
    4165             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4166             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    4167             :       // MIs[0] Operand 1
    4168             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhasx,
    4169             :       // MIs[0] Rn
    4170             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4171             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    4172             :       // MIs[0] Rm
    4173             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4174             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    4175             :       // (intrinsic_wo_chain:i32 782:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)  =>  (UHASX:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)
    4176             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHASX,
    4177             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4178             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4179             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4180             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4181             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4182             :       GIR_EraseFromParent, /*InsnID*/0,
    4183             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4184             :       GIR_Done,
    4185             :     // Label 113: @9100
    4186             :     GIM_Try, /*On fail goto*//*Label 114*/ 9164,
    4187             :       GIM_CheckFeatures, GIFBS_IsARM,
    4188             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4189             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4190             :       // MIs[0] Rd
    4191             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4192             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    4193             :       // MIs[0] Operand 1
    4194             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhadd16,
    4195             :       // MIs[0] Rn
    4196             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4197             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    4198             :       // MIs[0] Rm
    4199             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4200             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    4201             :       // (intrinsic_wo_chain:i32 780:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)  =>  (UHADD16:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)
    4202             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHADD16,
    4203             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4204             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4205             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4206             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4207             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4208             :       GIR_EraseFromParent, /*InsnID*/0,
    4209             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4210             :       GIR_Done,
    4211             :     // Label 114: @9164
    4212             :     GIM_Try, /*On fail goto*//*Label 115*/ 9228,
    4213             :       GIM_CheckFeatures, GIFBS_IsARM,
    4214             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4215             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4216             :       // MIs[0] Rd
    4217             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4218             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    4219             :       // MIs[0] Operand 1
    4220             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhadd8,
    4221             :       // MIs[0] Rn
    4222             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4223             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    4224             :       // MIs[0] Rm
    4225             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4226             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    4227             :       // (intrinsic_wo_chain:i32 781:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)  =>  (UHADD8:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)
    4228             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHADD8,
    4229             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4230             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4231             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4232             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4233             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4234             :       GIR_EraseFromParent, /*InsnID*/0,
    4235             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4236             :       GIR_Done,
    4237             :     // Label 115: @9228
    4238             :     GIM_Try, /*On fail goto*//*Label 116*/ 9292,
    4239             :       GIM_CheckFeatures, GIFBS_IsARM,
    4240             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4241             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4242             :       // MIs[0] Rd
    4243             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4244             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    4245             :       // MIs[0] Operand 1
    4246             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsax,
    4247             :       // MIs[0] Rn
    4248             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4249             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    4250             :       // MIs[0] Rm
    4251             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4252             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    4253             :       // (intrinsic_wo_chain:i32 783:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)  =>  (UHSAX:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)
    4254             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHSAX,
    4255             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4256             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4257             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4258             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4259             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4260             :       GIR_EraseFromParent, /*InsnID*/0,
    4261             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4262             :       GIR_Done,
    4263             :     // Label 116: @9292
    4264             :     GIM_Try, /*On fail goto*//*Label 117*/ 9356,
    4265             :       GIM_CheckFeatures, GIFBS_IsARM,
    4266             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4267             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4268             :       // MIs[0] Rd
    4269             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4270             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    4271             :       // MIs[0] Operand 1
    4272             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsub16,
    4273             :       // MIs[0] Rn
    4274             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4275             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    4276             :       // MIs[0] Rm
    4277             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4278             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    4279             :       // (intrinsic_wo_chain:i32 784:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)  =>  (UHSUB16:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)
    4280             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHSUB16,
    4281             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4282             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4283             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4284             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4285             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4286             :       GIR_EraseFromParent, /*InsnID*/0,
    4287             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4288             :       GIR_Done,
    4289             :     // Label 117: @9356
    4290             :     GIM_Try, /*On fail goto*//*Label 118*/ 9420,
    4291             :       GIM_CheckFeatures, GIFBS_IsARM,
    4292             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4293             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4294             :       // MIs[0] Rd
    4295             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4296             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    4297             :       // MIs[0] Operand 1
    4298             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsub8,
    4299             :       // MIs[0] Rn
    4300             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4301             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    4302             :       // MIs[0] Rm
    4303             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4304             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    4305             :       // (intrinsic_wo_chain:i32 785:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)  =>  (UHSUB8:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)
    4306             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHSUB8,
    4307             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4308             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4309             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4310             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4311             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4312             :       GIR_EraseFromParent, /*InsnID*/0,
    4313             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4314             :       GIR_Done,
    4315             :     // Label 118: @9420
    4316             :     GIM_Try, /*On fail goto*//*Label 119*/ 9484,
    4317             :       GIM_CheckFeatures, GIFBS_IsARM_HasV6,
    4318             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4319             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4320             :       // MIs[0] Rd
    4321             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4322             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
    4323             :       // MIs[0] Operand 1
    4324             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usad8,
    4325             :       // MIs[0] Rn
    4326             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4327             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
    4328             :       // MIs[0] Rm
    4329             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4330             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
    4331             :       // (intrinsic_wo_chain:i32 793:iPTR, GPR:i32:$Rn, GPR:i32:$Rm)  =>  (USAD8:i32 GPR:i32:$Rn, GPR:i32:$Rm)
    4332             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USAD8,
    4333             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4334             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4335             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4336             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4337             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4338             :       GIR_EraseFromParent, /*InsnID*/0,
    4339             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4340             :       GIR_Done,
    4341             :     // Label 119: @9484
    4342             :     GIM_Try, /*On fail goto*//*Label 120*/ 9542,
    4343             :       GIM_CheckFeatures, GIFBS_IsARM_HasV8_HasCRC,
    4344             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4345             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4346             :       // MIs[0] Rd
    4347             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4348             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    4349             :       // MIs[0] Operand 1
    4350             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32b,
    4351             :       // MIs[0] Rn
    4352             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4353             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    4354             :       // MIs[0] Rm
    4355             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4356             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    4357             :       // (intrinsic_wo_chain:i32 567:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)  =>  (CRC32B:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)
    4358             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32B,
    4359             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4360             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4361             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4362             :       GIR_EraseFromParent, /*InsnID*/0,
    4363             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4364             :       GIR_Done,
    4365             :     // Label 120: @9542
    4366             :     GIM_Try, /*On fail goto*//*Label 121*/ 9600,
    4367             :       GIM_CheckFeatures, GIFBS_IsARM_HasV8_HasCRC,
    4368             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4369             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4370             :       // MIs[0] Rd
    4371             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4372             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    4373             :       // MIs[0] Operand 1
    4374             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32cb,
    4375             :       // MIs[0] Rn
    4376             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4377             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    4378             :       // MIs[0] Rm
    4379             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4380             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    4381             :       // (intrinsic_wo_chain:i32 568:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)  =>  (CRC32CB:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)
    4382             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32CB,
    4383             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4384             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4385             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4386             :       GIR_EraseFromParent, /*InsnID*/0,
    4387             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4388             :       GIR_Done,
    4389             :     // Label 121: @9600
    4390             :     GIM_Try, /*On fail goto*//*Label 122*/ 9658,
    4391             :       GIM_CheckFeatures, GIFBS_IsARM_HasV8_HasCRC,
    4392             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4393             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4394             :       // MIs[0] Rd
    4395             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4396             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    4397             :       // MIs[0] Operand 1
    4398             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32h,
    4399             :       // MIs[0] Rn
    4400             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4401             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    4402             :       // MIs[0] Rm
    4403             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4404             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    4405             :       // (intrinsic_wo_chain:i32 571:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)  =>  (CRC32H:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)
    4406             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32H,
    4407             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4408             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4409             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4410             :       GIR_EraseFromParent, /*InsnID*/0,
    4411             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4412             :       GIR_Done,
    4413             :     // Label 122: @9658
    4414             :     GIM_Try, /*On fail goto*//*Label 123*/ 9716,
    4415             :       GIM_CheckFeatures, GIFBS_IsARM_HasV8_HasCRC,
    4416             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4417             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4418             :       // MIs[0] Rd
    4419             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4420             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    4421             :       // MIs[0] Operand 1
    4422             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32ch,
    4423             :       // MIs[0] Rn
    4424             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4425             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    4426             :       // MIs[0] Rm
    4427             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4428             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    4429             :       // (intrinsic_wo_chain:i32 569:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)  =>  (CRC32CH:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)
    4430             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32CH,
    4431             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4432             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4433             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4434             :       GIR_EraseFromParent, /*InsnID*/0,
    4435             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4436             :       GIR_Done,
    4437             :     // Label 123: @9716
    4438             :     GIM_Try, /*On fail goto*//*Label 124*/ 9774,
    4439             :       GIM_CheckFeatures, GIFBS_IsARM_HasV8_HasCRC,
    4440             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4441             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4442             :       // MIs[0] Rd
    4443             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4444             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    4445             :       // MIs[0] Operand 1
    4446             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32w,
    4447             :       // MIs[0] Rn
    4448             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4449             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    4450             :       // MIs[0] Rm
    4451             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4452             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    4453             :       // (intrinsic_wo_chain:i32 572:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)  =>  (CRC32W:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)
    4454             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32W,
    4455             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4456             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4457             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4458             :       GIR_EraseFromParent, /*InsnID*/0,
    4459             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4460             :       GIR_Done,
    4461             :     // Label 124: @9774
    4462             :     GIM_Try, /*On fail goto*//*Label 125*/ 9832,
    4463             :       GIM_CheckFeatures, GIFBS_IsARM_HasV8_HasCRC,
    4464             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4465             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4466             :       // MIs[0] Rd
    4467             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4468             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
    4469             :       // MIs[0] Operand 1
    4470             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32cw,
    4471             :       // MIs[0] Rn
    4472             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4473             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
    4474             :       // MIs[0] Rm
    4475             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4476             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
    4477             :       // (intrinsic_wo_chain:i32 570:iPTR, GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)  =>  (CRC32CW:i32 GPRnopc:i32:$Rn, GPRnopc:i32:$Rm)
    4478             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32CW,
    4479             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4480             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4481             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4482             :       GIR_EraseFromParent, /*InsnID*/0,
    4483             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4484             :       GIR_Done,
    4485             :     // Label 125: @9832
    4486             :     GIM_Try, /*On fail goto*//*Label 126*/ 9896,
    4487             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    4488             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4489             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4490             :       // MIs[0] Rd
    4491             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4492             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    4493             :       // MIs[0] Operand 1
    4494             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd16,
    4495             :       // MIs[0] Rn
    4496             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4497             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    4498             :       // MIs[0] Rm
    4499             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4500             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    4501             :       // (intrinsic_wo_chain:i32 719:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2QADD16:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    4502             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QADD16,
    4503             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4504             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4505             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4506             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4507             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4508             :       GIR_EraseFromParent, /*InsnID*/0,
    4509             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4510             :       GIR_Done,
    4511             :     // Label 126: @9896
    4512             :     GIM_Try, /*On fail goto*//*Label 127*/ 9960,
    4513             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    4514             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4515             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4516             :       // MIs[0] Rd
    4517             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4518             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    4519             :       // MIs[0] Operand 1
    4520             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd8,
    4521             :       // MIs[0] Rn
    4522             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4523             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    4524             :       // MIs[0] Rm
    4525             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4526             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    4527             :       // (intrinsic_wo_chain:i32 720:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2QADD8:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    4528             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QADD8,
    4529             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4530             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4531             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4532             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4533             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4534             :       GIR_EraseFromParent, /*InsnID*/0,
    4535             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4536             :       GIR_Done,
    4537             :     // Label 127: @9960
    4538             :     GIM_Try, /*On fail goto*//*Label 128*/ 10024,
    4539             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    4540             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4541             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4542             :       // MIs[0] Rd
    4543             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4544             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    4545             :       // MIs[0] Operand 1
    4546             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qasx,
    4547             :       // MIs[0] Rn
    4548             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4549             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    4550             :       // MIs[0] Rm
    4551             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4552             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    4553             :       // (intrinsic_wo_chain:i32 721:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2QASX:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    4554             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QASX,
    4555             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4556             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4557             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4558             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4559             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4560             :       GIR_EraseFromParent, /*InsnID*/0,
    4561             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4562             :       GIR_Done,
    4563             :     // Label 128: @10024
    4564             :     GIM_Try, /*On fail goto*//*Label 129*/ 10088,
    4565             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    4566             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4567             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4568             :       // MIs[0] Rd
    4569             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4570             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    4571             :       // MIs[0] Operand 1
    4572             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsub8,
    4573             :       // MIs[0] Rn
    4574             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4575             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    4576             :       // MIs[0] Rm
    4577             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4578             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    4579             :       // (intrinsic_wo_chain:i32 792:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2UQSUB8:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    4580             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQSUB8,
    4581             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4582             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4583             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4584             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4585             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4586             :       GIR_EraseFromParent, /*InsnID*/0,
    4587             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4588             :       GIR_Done,
    4589             :     // Label 129: @10088
    4590             :     GIM_Try, /*On fail goto*//*Label 130*/ 10152,
    4591             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    4592             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4593             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4594             :       // MIs[0] Rd
    4595             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4596             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    4597             :       // MIs[0] Operand 1
    4598             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsax,
    4599             :       // MIs[0] Rn
    4600             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4601             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    4602             :       // MIs[0] Rm
    4603             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4604             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    4605             :       // (intrinsic_wo_chain:i32 722:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2QSAX:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    4606             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QSAX,
    4607             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4608             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4609             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4610             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4611             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4612             :       GIR_EraseFromParent, /*InsnID*/0,
    4613             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4614             :       GIR_Done,
    4615             :     // Label 130: @10152
    4616             :     GIM_Try, /*On fail goto*//*Label 131*/ 10216,
    4617             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    4618             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4619             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4620             :       // MIs[0] Rd
    4621             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4622             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    4623             :       // MIs[0] Operand 1
    4624             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub16,
    4625             :       // MIs[0] Rn
    4626             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4627             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    4628             :       // MIs[0] Rm
    4629             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4630             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    4631             :       // (intrinsic_wo_chain:i32 724:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2QSUB16:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    4632             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QSUB16,
    4633             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4634             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4635             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4636             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4637             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4638             :       GIR_EraseFromParent, /*InsnID*/0,
    4639             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4640             :       GIR_Done,
    4641             :     // Label 131: @10216
    4642             :     GIM_Try, /*On fail goto*//*Label 132*/ 10280,
    4643             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    4644             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4645             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4646             :       // MIs[0] Rd
    4647             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4648             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    4649             :       // MIs[0] Operand 1
    4650             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub8,
    4651             :       // MIs[0] Rn
    4652             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4653             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    4654             :       // MIs[0] Rm
    4655             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4656             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    4657             :       // (intrinsic_wo_chain:i32 725:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2QSUB8:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    4658             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QSUB8,
    4659             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4660             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4661             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4662             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4663             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4664             :       GIR_EraseFromParent, /*InsnID*/0,
    4665             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4666             :       GIR_Done,
    4667             :     // Label 132: @10280
    4668             :     GIM_Try, /*On fail goto*//*Label 133*/ 10344,
    4669             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    4670             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4671             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4672             :       // MIs[0] Rd
    4673             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4674             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    4675             :       // MIs[0] Operand 1
    4676             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqadd16,
    4677             :       // MIs[0] Rn
    4678             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4679             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    4680             :       // MIs[0] Rm
    4681             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4682             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    4683             :       // (intrinsic_wo_chain:i32 787:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2UQADD16:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    4684             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQADD16,
    4685             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4686             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4687             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4688             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4689             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4690             :       GIR_EraseFromParent, /*InsnID*/0,
    4691             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4692             :       GIR_Done,
    4693             :     // Label 133: @10344
    4694             :     GIM_Try, /*On fail goto*//*Label 134*/ 10408,
    4695             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    4696             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4697             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4698             :       // MIs[0] Rd
    4699             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4700             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    4701             :       // MIs[0] Operand 1
    4702             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqadd8,
    4703             :       // MIs[0] Rn
    4704             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4705             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    4706             :       // MIs[0] Rm
    4707             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4708             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    4709             :       // (intrinsic_wo_chain:i32 788:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2UQADD8:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    4710             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQADD8,
    4711             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4712             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4713             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4714             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4715             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4716             :       GIR_EraseFromParent, /*InsnID*/0,
    4717             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4718             :       GIR_Done,
    4719             :     // Label 134: @10408
    4720             :     GIM_Try, /*On fail goto*//*Label 135*/ 10472,
    4721             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    4722             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4723             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4724             :       // MIs[0] Rd
    4725             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4726             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    4727             :       // MIs[0] Operand 1
    4728             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqasx,
    4729             :       // MIs[0] Rn
    4730             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4731             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    4732             :       // MIs[0] Rm
    4733             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4734             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    4735             :       // (intrinsic_wo_chain:i32 789:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2UQASX:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    4736             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQASX,
    4737             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4738             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4739             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4740             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4741             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4742             :       GIR_EraseFromParent, /*InsnID*/0,
    4743             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4744             :       GIR_Done,
    4745             :     // Label 135: @10472
    4746             :     GIM_Try, /*On fail goto*//*Label 136*/ 10536,
    4747             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    4748             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4749             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4750             :       // MIs[0] Rd
    4751             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4752             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    4753             :       // MIs[0] Operand 1
    4754             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsax,
    4755             :       // MIs[0] Rn
    4756             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4757             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    4758             :       // MIs[0] Rm
    4759             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4760             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    4761             :       // (intrinsic_wo_chain:i32 790:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2UQSAX:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    4762             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQSAX,
    4763             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4764             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4765             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4766             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4767             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4768             :       GIR_EraseFromParent, /*InsnID*/0,
    4769             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4770             :       GIR_Done,
    4771             :     // Label 136: @10536
    4772             :     GIM_Try, /*On fail goto*//*Label 137*/ 10600,
    4773             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    4774             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4775             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4776             :       // MIs[0] Rd
    4777             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4778             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    4779             :       // MIs[0] Operand 1
    4780             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsub16,
    4781             :       // MIs[0] Rn
    4782             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4783             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    4784             :       // MIs[0] Rm
    4785             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4786             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    4787             :       // (intrinsic_wo_chain:i32 791:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2UQSUB16:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    4788             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQSUB16,
    4789             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4790             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4791             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4792             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4793             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4794             :       GIR_EraseFromParent, /*InsnID*/0,
    4795             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4796             :       GIR_Done,
    4797             :     // Label 137: @10600
    4798             :     GIM_Try, /*On fail goto*//*Label 138*/ 10664,
    4799             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    4800             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4801             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4802             :       // MIs[0] Rd
    4803             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4804             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    4805             :       // MIs[0] Operand 1
    4806             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shasx,
    4807             :       // MIs[0] Rn
    4808             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4809             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    4810             :       // MIs[0] Rm
    4811             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4812             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    4813             :       // (intrinsic_wo_chain:i32 733:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2SHASX:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    4814             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHASX,
    4815             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4816             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4817             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4818             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4819             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4820             :       GIR_EraseFromParent, /*InsnID*/0,
    4821             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4822             :       GIR_Done,
    4823             :     // Label 138: @10664
    4824             :     GIM_Try, /*On fail goto*//*Label 139*/ 10728,
    4825             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    4826             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4827             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4828             :       // MIs[0] Rd
    4829             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4830             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    4831             :       // MIs[0] Operand 1
    4832             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shadd16,
    4833             :       // MIs[0] Rn
    4834             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4835             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    4836             :       // MIs[0] Rm
    4837             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4838             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    4839             :       // (intrinsic_wo_chain:i32 731:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2SHADD16:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    4840             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHADD16,
    4841             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4842             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4843             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4844             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4845             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4846             :       GIR_EraseFromParent, /*InsnID*/0,
    4847             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4848             :       GIR_Done,
    4849             :     // Label 139: @10728
    4850             :     GIM_Try, /*On fail goto*//*Label 140*/ 10792,
    4851             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    4852             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4853             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4854             :       // MIs[0] Rd
    4855             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4856             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    4857             :       // MIs[0] Operand 1
    4858             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shadd8,
    4859             :       // MIs[0] Rn
    4860             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4861             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    4862             :       // MIs[0] Rm
    4863             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4864             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    4865             :       // (intrinsic_wo_chain:i32 732:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2SHADD8:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    4866             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHADD8,
    4867             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4868             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4869             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4870             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4871             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4872             :       GIR_EraseFromParent, /*InsnID*/0,
    4873             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4874             :       GIR_Done,
    4875             :     // Label 140: @10792
    4876             :     GIM_Try, /*On fail goto*//*Label 141*/ 10856,
    4877             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    4878             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4879             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4880             :       // MIs[0] Rd
    4881             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4882             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    4883             :       // MIs[0] Operand 1
    4884             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsax,
    4885             :       // MIs[0] Rn
    4886             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4887             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    4888             :       // MIs[0] Rm
    4889             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4890             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    4891             :       // (intrinsic_wo_chain:i32 734:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2SHSAX:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    4892             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHSAX,
    4893             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4894             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4895             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4896             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4897             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4898             :       GIR_EraseFromParent, /*InsnID*/0,
    4899             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4900             :       GIR_Done,
    4901             :     // Label 141: @10856
    4902             :     GIM_Try, /*On fail goto*//*Label 142*/ 10920,
    4903             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    4904             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4905             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4906             :       // MIs[0] Rd
    4907             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4908             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    4909             :       // MIs[0] Operand 1
    4910             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsub16,
    4911             :       // MIs[0] Rn
    4912             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4913             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    4914             :       // MIs[0] Rm
    4915             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4916             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    4917             :       // (intrinsic_wo_chain:i32 735:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2SHSUB16:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    4918             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHSUB16,
    4919             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4920             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4921             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4922             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4923             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4924             :       GIR_EraseFromParent, /*InsnID*/0,
    4925             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4926             :       GIR_Done,
    4927             :     // Label 142: @10920
    4928             :     GIM_Try, /*On fail goto*//*Label 143*/ 10984,
    4929             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    4930             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4931             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4932             :       // MIs[0] Rd
    4933             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4934             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    4935             :       // MIs[0] Operand 1
    4936             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsub8,
    4937             :       // MIs[0] Rn
    4938             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4939             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    4940             :       // MIs[0] Rm
    4941             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4942             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    4943             :       // (intrinsic_wo_chain:i32 736:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2SHSUB8:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    4944             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHSUB8,
    4945             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4946             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4947             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4948             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4949             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4950             :       GIR_EraseFromParent, /*InsnID*/0,
    4951             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4952             :       GIR_Done,
    4953             :     // Label 143: @10984
    4954             :     GIM_Try, /*On fail goto*//*Label 144*/ 11048,
    4955             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    4956             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4957             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4958             :       // MIs[0] Rd
    4959             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4960             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    4961             :       // MIs[0] Operand 1
    4962             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhasx,
    4963             :       // MIs[0] Rn
    4964             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4965             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    4966             :       // MIs[0] Rm
    4967             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4968             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    4969             :       // (intrinsic_wo_chain:i32 782:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2UHASX:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    4970             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHASX,
    4971             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4972             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4973             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    4974             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    4975             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    4976             :       GIR_EraseFromParent, /*InsnID*/0,
    4977             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4978             :       GIR_Done,
    4979             :     // Label 144: @11048
    4980             :     GIM_Try, /*On fail goto*//*Label 145*/ 11112,
    4981             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    4982             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    4983             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    4984             :       // MIs[0] Rd
    4985             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4986             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    4987             :       // MIs[0] Operand 1
    4988             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhadd16,
    4989             :       // MIs[0] Rn
    4990             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    4991             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    4992             :       // MIs[0] Rm
    4993             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    4994             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    4995             :       // (intrinsic_wo_chain:i32 780:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2UHADD16:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    4996             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHADD16,
    4997             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    4998             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    4999             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    5000             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5001             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5002             :       GIR_EraseFromParent, /*InsnID*/0,
    5003             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5004             :       GIR_Done,
    5005             :     // Label 145: @11112
    5006             :     GIM_Try, /*On fail goto*//*Label 146*/ 11176,
    5007             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    5008             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5009             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5010             :       // MIs[0] Rd
    5011             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    5012             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    5013             :       // MIs[0] Operand 1
    5014             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhadd8,
    5015             :       // MIs[0] Rn
    5016             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    5017             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    5018             :       // MIs[0] Rm
    5019             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    5020             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    5021             :       // (intrinsic_wo_chain:i32 781:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2UHADD8:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    5022             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHADD8,
    5023             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    5024             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    5025             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    5026             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5027             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5028             :       GIR_EraseFromParent, /*InsnID*/0,
    5029             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5030             :       GIR_Done,
    5031             :     // Label 146: @11176
    5032             :     GIM_Try, /*On fail goto*//*Label 147*/ 11240,
    5033             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    5034             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5035             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5036             :       // MIs[0] Rd
    5037             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    5038             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    5039             :       // MIs[0] Operand 1
    5040             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsax,
    5041             :       // MIs[0] Rn
    5042             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    5043             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    5044             :       // MIs[0] Rm
    5045             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    5046             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    5047             :       // (intrinsic_wo_chain:i32 783:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2UHSAX:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    5048             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHSAX,
    5049             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    5050             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    5051             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    5052             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5053             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5054             :       GIR_EraseFromParent, /*InsnID*/0,
    5055             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5056             :       GIR_Done,
    5057             :     // Label 147: @11240
    5058             :     GIM_Try, /*On fail goto*//*Label 148*/ 11304,
    5059             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    5060             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5061             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5062             :       // MIs[0] Rd
    5063             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    5064             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    5065             :       // MIs[0] Operand 1
    5066             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsub16,
    5067             :       // MIs[0] Rn
    5068             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    5069             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    5070             :       // MIs[0] Rm
    5071             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    5072             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    5073             :       // (intrinsic_wo_chain:i32 784:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2UHSUB16:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    5074             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHSUB16,
    5075             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    5076             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    5077             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    5078             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5079             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5080             :       GIR_EraseFromParent, /*InsnID*/0,
    5081             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5082             :       GIR_Done,
    5083             :     // Label 148: @11304
    5084             :     GIM_Try, /*On fail goto*//*Label 149*/ 11368,
    5085             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    5086             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5087             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5088             :       // MIs[0] Rd
    5089             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    5090             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    5091             :       // MIs[0] Operand 1
    5092             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsub8,
    5093             :       // MIs[0] Rn
    5094             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    5095             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    5096             :       // MIs[0] Rm
    5097             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    5098             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    5099             :       // (intrinsic_wo_chain:i32 785:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2UHSUB8:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    5100             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHSUB8,
    5101             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    5102             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    5103             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    5104             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5105             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5106             :       GIR_EraseFromParent, /*InsnID*/0,
    5107             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5108             :       GIR_Done,
    5109             :     // Label 149: @11368
    5110             :     GIM_Try, /*On fail goto*//*Label 150*/ 11432,
    5111             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    5112             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5113             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5114             :       // MIs[0] Rd
    5115             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    5116             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    5117             :       // MIs[0] Operand 1
    5118             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usad8,
    5119             :       // MIs[0] Rn
    5120             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    5121             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    5122             :       // MIs[0] Rm
    5123             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    5124             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    5125             :       // (intrinsic_wo_chain:i32 793:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2USAD8:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    5126             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USAD8,
    5127             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    5128             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    5129             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    5130             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5131             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5132             :       GIR_EraseFromParent, /*InsnID*/0,
    5133             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5134             :       GIR_Done,
    5135             :     // Label 150: @11432
    5136             :     GIM_Try, /*On fail goto*//*Label 151*/ 11496,
    5137             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    5138             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5139             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5140             :       // MIs[0] Rd
    5141             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    5142             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    5143             :       // MIs[0] Operand 1
    5144             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smuad,
    5145             :       // MIs[0] Rn
    5146             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    5147             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    5148             :       // MIs[0] Rm
    5149             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    5150             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    5151             :       // (intrinsic_wo_chain:i32 751:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2SMUAD:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    5152             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMUAD,
    5153             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    5154             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    5155             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    5156             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5157             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5158             :       GIR_EraseFromParent, /*InsnID*/0,
    5159             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5160             :       GIR_Done,
    5161             :     // Label 151: @11496
    5162             :     GIM_Try, /*On fail goto*//*Label 152*/ 11560,
    5163             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    5164             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5165             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5166             :       // MIs[0] Rd
    5167             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    5168             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    5169             :       // MIs[0] Operand 1
    5170             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smuadx,
    5171             :       // MIs[0] Rn
    5172             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    5173             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    5174             :       // MIs[0] Rm
    5175             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    5176             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    5177             :       // (intrinsic_wo_chain:i32 752:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2SMUADX:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    5178             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMUADX,
    5179             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    5180             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    5181             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    5182             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5183             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5184             :       GIR_EraseFromParent, /*InsnID*/0,
    5185             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5186             :       GIR_Done,
    5187             :     // Label 152: @11560
    5188             :     GIM_Try, /*On fail goto*//*Label 153*/ 11624,
    5189             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    5190             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5191             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5192             :       // MIs[0] Rd
    5193             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    5194             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    5195             :       // MIs[0] Operand 1
    5196             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smusd,
    5197             :       // MIs[0] Rn
    5198             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    5199             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    5200             :       // MIs[0] Rm
    5201             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    5202             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    5203             :       // (intrinsic_wo_chain:i32 759:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2SMUSD:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    5204             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMUSD,
    5205             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    5206             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    5207             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    5208             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5209             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5210             :       GIR_EraseFromParent, /*InsnID*/0,
    5211             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5212             :       GIR_Done,
    5213             :     // Label 153: @11624
    5214             :     GIM_Try, /*On fail goto*//*Label 154*/ 11688,
    5215             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasDSP,
    5216             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5217             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5218             :       // MIs[0] Rd
    5219             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    5220             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    5221             :       // MIs[0] Operand 1
    5222             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smusdx,
    5223             :       // MIs[0] Rn
    5224             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    5225             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    5226             :       // MIs[0] Rm
    5227             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    5228             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    5229             :       // (intrinsic_wo_chain:i32 760:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2SMUSDX:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    5230             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMUSDX,
    5231             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    5232             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    5233             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    5234             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5235             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5236             :       GIR_EraseFromParent, /*InsnID*/0,
    5237             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5238             :       GIR_Done,
    5239             :     // Label 154: @11688
    5240             :     GIM_Try, /*On fail goto*//*Label 155*/ 11746,
    5241             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasV8_HasCRC,
    5242             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5243             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5244             :       // MIs[0] Rd
    5245             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    5246             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    5247             :       // MIs[0] Operand 1
    5248             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32b,
    5249             :       // MIs[0] Rn
    5250             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    5251             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    5252             :       // MIs[0] Rm
    5253             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    5254             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    5255             :       // (intrinsic_wo_chain:i32 567:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2CRC32B:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    5256             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32B,
    5257             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    5258             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    5259             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    5260             :       GIR_EraseFromParent, /*InsnID*/0,
    5261             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5262             :       GIR_Done,
    5263             :     // Label 155: @11746
    5264             :     GIM_Try, /*On fail goto*//*Label 156*/ 11804,
    5265             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasV8_HasCRC,
    5266             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5267             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5268             :       // MIs[0] Rd
    5269             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    5270             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    5271             :       // MIs[0] Operand 1
    5272             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32cb,
    5273             :       // MIs[0] Rn
    5274             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    5275             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    5276             :       // MIs[0] Rm
    5277             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    5278             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    5279             :       // (intrinsic_wo_chain:i32 568:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2CRC32CB:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    5280             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32CB,
    5281             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    5282             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    5283             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    5284             :       GIR_EraseFromParent, /*InsnID*/0,
    5285             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5286             :       GIR_Done,
    5287             :     // Label 156: @11804
    5288             :     GIM_Try, /*On fail goto*//*Label 157*/ 11862,
    5289             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasV8_HasCRC,
    5290             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5291             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5292             :       // MIs[0] Rd
    5293             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    5294             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    5295             :       // MIs[0] Operand 1
    5296             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32h,
    5297             :       // MIs[0] Rn
    5298             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    5299             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    5300             :       // MIs[0] Rm
    5301             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    5302             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    5303             :       // (intrinsic_wo_chain:i32 571:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2CRC32H:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    5304             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32H,
    5305             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    5306             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    5307             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    5308             :       GIR_EraseFromParent, /*InsnID*/0,
    5309             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5310             :       GIR_Done,
    5311             :     // Label 157: @11862
    5312             :     GIM_Try, /*On fail goto*//*Label 158*/ 11920,
    5313             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasV8_HasCRC,
    5314             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5315             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5316             :       // MIs[0] Rd
    5317             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    5318             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    5319             :       // MIs[0] Operand 1
    5320             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32ch,
    5321             :       // MIs[0] Rn
    5322             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    5323             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    5324             :       // MIs[0] Rm
    5325             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    5326             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    5327             :       // (intrinsic_wo_chain:i32 569:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2CRC32CH:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    5328             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32CH,
    5329             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    5330             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    5331             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    5332             :       GIR_EraseFromParent, /*InsnID*/0,
    5333             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5334             :       GIR_Done,
    5335             :     // Label 158: @11920
    5336             :     GIM_Try, /*On fail goto*//*Label 159*/ 11978,
    5337             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasV8_HasCRC,
    5338             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5339             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5340             :       // MIs[0] Rd
    5341             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    5342             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    5343             :       // MIs[0] Operand 1
    5344             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32w,
    5345             :       // MIs[0] Rn
    5346             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    5347             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    5348             :       // MIs[0] Rm
    5349             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    5350             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    5351             :       // (intrinsic_wo_chain:i32 572:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2CRC32W:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    5352             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32W,
    5353             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    5354             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    5355             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    5356             :       GIR_EraseFromParent, /*InsnID*/0,
    5357             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5358             :       GIR_Done,
    5359             :     // Label 159: @11978
    5360             :     GIM_Try, /*On fail goto*//*Label 160*/ 12036,
    5361             :       GIM_CheckFeatures, GIFBS_IsThumb2_HasV8_HasCRC,
    5362             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5363             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5364             :       // MIs[0] Rd
    5365             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    5366             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
    5367             :       // MIs[0] Operand 1
    5368             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32cw,
    5369             :       // MIs[0] Rn
    5370             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    5371             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
    5372             :       // MIs[0] Rm
    5373             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    5374             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
    5375             :       // (intrinsic_wo_chain:i32 570:iPTR, rGPR:i32:$Rn, rGPR:i32:$Rm)  =>  (t2CRC32CW:i32 rGPR:i32:$Rn, rGPR:i32:$Rm)
    5376             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32CW,
    5377             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
    5378             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
    5379             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
    5380             :       GIR_EraseFromParent, /*InsnID*/0,
    5381             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5382             :       GIR_Done,
    5383             :     // Label 160: @12036
    5384             :     GIM_Try, /*On fail goto*//*Label 161*/ 12100,
    5385             :       GIM_CheckFeatures, GIFBS_HasNEON,
    5386             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5387             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5388             :       // MIs[0] Vd
    5389             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    5390             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    5391             :       // MIs[0] Operand 1
    5392             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds,
    5393             :       // MIs[0] Vn
    5394             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    5395             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    5396             :       // MIs[0] Vm
    5397             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    5398             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    5399             :       // (intrinsic_wo_chain:v4i16 630:iPTR, DPR:v4i16:$Vn, DPR:v4i16:$Vm)  =>  (VHADDsv4i16:v4i16 DPR:v4i16:$Vn, DPR:v4i16:$Vm)
    5400             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv4i16,
    5401             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    5402             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    5403             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    5404             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5405             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5406             :       GIR_EraseFromParent, /*InsnID*/0,
    5407             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5408             :       GIR_Done,
    5409             :     // Label 161: @12100
    5410             :     GIM_Try, /*On fail goto*//*Label 162*/ 12164,
    5411             :       GIM_CheckFeatures, GIFBS_HasNEON,
    5412             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5413             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5414             :       // MIs[0] Vd
    5415             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    5416             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    5417             :       // MIs[0] Operand 1
    5418             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds,
    5419             :       // MIs[0] Vn
    5420             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    5421             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    5422             :       // MIs[0] Vm
    5423             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    5424             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    5425             :       // (intrinsic_wo_chain:v2i32 630:iPTR, DPR:v2i32:$Vn, DPR:v2i32:$Vm)  =>  (VHADDsv2i32:v2i32 DPR:v2i32:$Vn, DPR:v2i32:$Vm)
    5426             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv2i32,
    5427             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    5428             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    5429             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    5430             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5431             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5432             :       GIR_EraseFromParent, /*InsnID*/0,
    5433             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5434             :       GIR_Done,
    5435             :     // Label 162: @12164
    5436             :     GIM_Try, /*On fail goto*//*Label 163*/ 12228,
    5437             :       GIM_CheckFeatures, GIFBS_HasNEON,
    5438             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5439             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5440             :       // MIs[0] Vd
    5441             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    5442             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    5443             :       // MIs[0] Operand 1
    5444             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds,
    5445             :       // MIs[0] Vn
    5446             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    5447             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    5448             :       // MIs[0] Vm
    5449             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    5450             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    5451             :       // (intrinsic_wo_chain:v8i16 630:iPTR, QPR:v8i16:$Vn, QPR:v8i16:$Vm)  =>  (VHADDsv8i16:v8i16 QPR:v8i16:$Vn, QPR:v8i16:$Vm)
    5452             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv8i16,
    5453             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    5454             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    5455             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    5456             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5457             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5458             :       GIR_EraseFromParent, /*InsnID*/0,
    5459             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5460             :       GIR_Done,
    5461             :     // Label 163: @12228
    5462             :     GIM_Try, /*On fail goto*//*Label 164*/ 12292,
    5463             :       GIM_CheckFeatures, GIFBS_HasNEON,
    5464             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5465             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5466             :       // MIs[0] Vd
    5467             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    5468             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    5469             :       // MIs[0] Operand 1
    5470             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds,
    5471             :       // MIs[0] Vn
    5472             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    5473             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    5474             :       // MIs[0] Vm
    5475             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    5476             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    5477             :       // (intrinsic_wo_chain:v4i32 630:iPTR, QPR:v4i32:$Vn, QPR:v4i32:$Vm)  =>  (VHADDsv4i32:v4i32 QPR:v4i32:$Vn, QPR:v4i32:$Vm)
    5478             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv4i32,
    5479             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    5480             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    5481             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    5482             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5483             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5484             :       GIR_EraseFromParent, /*InsnID*/0,
    5485             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5486             :       GIR_Done,
    5487             :     // Label 164: @12292
    5488             :     GIM_Try, /*On fail goto*//*Label 165*/ 12356,
    5489             :       GIM_CheckFeatures, GIFBS_HasNEON,
    5490             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5491             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5492             :       // MIs[0] Vd
    5493             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    5494             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    5495             :       // MIs[0] Operand 1
    5496             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds,
    5497             :       // MIs[0] Vn
    5498             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    5499             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    5500             :       // MIs[0] Vm
    5501             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
    5502             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    5503             :       // (intrinsic_wo_chain:v8i8 630:iPTR, DPR:v8i8:$Vn, DPR:v8i8:$Vm)  =>  (VHADDsv8i8:v8i8 DPR:v8i8:$Vn, DPR:v8i8:$Vm)
    5504             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv8i8,
    5505             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    5506             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    5507             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    5508             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5509             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5510             :       GIR_EraseFromParent, /*InsnID*/0,
    5511             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5512             :       GIR_Done,
    5513             :     // Label 165: @12356
    5514             :     GIM_Try, /*On fail goto*//*Label 166*/ 12420,
    5515             :       GIM_CheckFeatures, GIFBS_HasNEON,
    5516             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5517             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5518             :       // MIs[0] Vd
    5519             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    5520             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    5521             :       // MIs[0] Operand 1
    5522             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds,
    5523             :       // MIs[0] Vn
    5524             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    5525             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    5526             :       // MIs[0] Vm
    5527             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
    5528             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    5529             :       // (intrinsic_wo_chain:v16i8 630:iPTR, QPR:v16i8:$Vn, QPR:v16i8:$Vm)  =>  (VHADDsv16i8:v16i8 QPR:v16i8:$Vn, QPR:v16i8:$Vm)
    5530             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv16i8,
    5531             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    5532             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    5533             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    5534             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5535             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5536             :       GIR_EraseFromParent, /*InsnID*/0,
    5537             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5538             :       GIR_Done,
    5539             :     // Label 166: @12420
    5540             :     GIM_Try, /*On fail goto*//*Label 167*/ 12484,
    5541             :       GIM_CheckFeatures, GIFBS_HasNEON,
    5542             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5543             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5544             :       // MIs[0] Vd
    5545             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    5546             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    5547             :       // MIs[0] Operand 1
    5548             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu,
    5549             :       // MIs[0] Vn
    5550             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    5551             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    5552             :       // MIs[0] Vm
    5553             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    5554             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    5555             :       // (intrinsic_wo_chain:v4i16 631:iPTR, DPR:v4i16:$Vn, DPR:v4i16:$Vm)  =>  (VHADDuv4i16:v4i16 DPR:v4i16:$Vn, DPR:v4i16:$Vm)
    5556             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv4i16,
    5557             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    5558             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    5559             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    5560             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5561             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5562             :       GIR_EraseFromParent, /*InsnID*/0,
    5563             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5564             :       GIR_Done,
    5565             :     // Label 167: @12484
    5566             :     GIM_Try, /*On fail goto*//*Label 168*/ 12548,
    5567             :       GIM_CheckFeatures, GIFBS_HasNEON,
    5568             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5569             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5570             :       // MIs[0] Vd
    5571             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    5572             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    5573             :       // MIs[0] Operand 1
    5574             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu,
    5575             :       // MIs[0] Vn
    5576             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    5577             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    5578             :       // MIs[0] Vm
    5579             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    5580             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    5581             :       // (intrinsic_wo_chain:v2i32 631:iPTR, DPR:v2i32:$Vn, DPR:v2i32:$Vm)  =>  (VHADDuv2i32:v2i32 DPR:v2i32:$Vn, DPR:v2i32:$Vm)
    5582             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv2i32,
    5583             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    5584             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    5585             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    5586             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5587             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5588             :       GIR_EraseFromParent, /*InsnID*/0,
    5589             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5590             :       GIR_Done,
    5591             :     // Label 168: @12548
    5592             :     GIM_Try, /*On fail goto*//*Label 169*/ 12612,
    5593             :       GIM_CheckFeatures, GIFBS_HasNEON,
    5594             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5595             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5596             :       // MIs[0] Vd
    5597             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    5598             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    5599             :       // MIs[0] Operand 1
    5600             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu,
    5601             :       // MIs[0] Vn
    5602             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    5603             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    5604             :       // MIs[0] Vm
    5605             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    5606             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    5607             :       // (intrinsic_wo_chain:v8i16 631:iPTR, QPR:v8i16:$Vn, QPR:v8i16:$Vm)  =>  (VHADDuv8i16:v8i16 QPR:v8i16:$Vn, QPR:v8i16:$Vm)
    5608             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv8i16,
    5609             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    5610             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    5611             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    5612             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5613             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5614             :       GIR_EraseFromParent, /*InsnID*/0,
    5615             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5616             :       GIR_Done,
    5617             :     // Label 169: @12612
    5618             :     GIM_Try, /*On fail goto*//*Label 170*/ 12676,
    5619             :       GIM_CheckFeatures, GIFBS_HasNEON,
    5620             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5621             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5622             :       // MIs[0] Vd
    5623             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    5624             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    5625             :       // MIs[0] Operand 1
    5626             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu,
    5627             :       // MIs[0] Vn
    5628             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    5629             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    5630             :       // MIs[0] Vm
    5631             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    5632             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    5633             :       // (intrinsic_wo_chain:v4i32 631:iPTR, QPR:v4i32:$Vn, QPR:v4i32:$Vm)  =>  (VHADDuv4i32:v4i32 QPR:v4i32:$Vn, QPR:v4i32:$Vm)
    5634             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv4i32,
    5635             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    5636             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    5637             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    5638             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5639             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5640             :       GIR_EraseFromParent, /*InsnID*/0,
    5641             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5642             :       GIR_Done,
    5643             :     // Label 170: @12676
    5644             :     GIM_Try, /*On fail goto*//*Label 171*/ 12740,
    5645             :       GIM_CheckFeatures, GIFBS_HasNEON,
    5646             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5647             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5648             :       // MIs[0] Vd
    5649             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    5650             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    5651             :       // MIs[0] Operand 1
    5652             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu,
    5653             :       // MIs[0] Vn
    5654             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    5655             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    5656             :       // MIs[0] Vm
    5657             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
    5658             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    5659             :       // (intrinsic_wo_chain:v8i8 631:iPTR, DPR:v8i8:$Vn, DPR:v8i8:$Vm)  =>  (VHADDuv8i8:v8i8 DPR:v8i8:$Vn, DPR:v8i8:$Vm)
    5660             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv8i8,
    5661             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    5662             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    5663             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    5664             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5665             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5666             :       GIR_EraseFromParent, /*InsnID*/0,
    5667             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5668             :       GIR_Done,
    5669             :     // Label 171: @12740
    5670             :     GIM_Try, /*On fail goto*//*Label 172*/ 12804,
    5671             :       GIM_CheckFeatures, GIFBS_HasNEON,
    5672             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5673             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5674             :       // MIs[0] Vd
    5675             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    5676             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    5677             :       // MIs[0] Operand 1
    5678             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu,
    5679             :       // MIs[0] Vn
    5680             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    5681             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    5682             :       // MIs[0] Vm
    5683             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
    5684             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    5685             :       // (intrinsic_wo_chain:v16i8 631:iPTR, QPR:v16i8:$Vn, QPR:v16i8:$Vm)  =>  (VHADDuv16i8:v16i8 QPR:v16i8:$Vn, QPR:v16i8:$Vm)
    5686             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv16i8,
    5687             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    5688             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    5689             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    5690             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5691             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5692             :       GIR_EraseFromParent, /*InsnID*/0,
    5693             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5694             :       GIR_Done,
    5695             :     // Label 172: @12804
    5696             :     GIM_Try, /*On fail goto*//*Label 173*/ 12868,
    5697             :       GIM_CheckFeatures, GIFBS_HasNEON,
    5698             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5699             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5700             :       // MIs[0] Vd
    5701             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    5702             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    5703             :       // MIs[0] Operand 1
    5704             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds,
    5705             :       // MIs[0] Vn
    5706             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    5707             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    5708             :       // MIs[0] Vm
    5709             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    5710             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    5711             :       // (intrinsic_wo_chain:v4i16 686:iPTR, DPR:v4i16:$Vn, DPR:v4i16:$Vm)  =>  (VRHADDsv4i16:v4i16 DPR:v4i16:$Vn, DPR:v4i16:$Vm)
    5712             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv4i16,
    5713             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    5714             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    5715             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    5716             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5717             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5718             :       GIR_EraseFromParent, /*InsnID*/0,
    5719             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5720             :       GIR_Done,
    5721             :     // Label 173: @12868
    5722             :     GIM_Try, /*On fail goto*//*Label 174*/ 12932,
    5723             :       GIM_CheckFeatures, GIFBS_HasNEON,
    5724             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5725             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5726             :       // MIs[0] Vd
    5727             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    5728             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    5729             :       // MIs[0] Operand 1
    5730             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds,
    5731             :       // MIs[0] Vn
    5732             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    5733             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    5734             :       // MIs[0] Vm
    5735             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    5736             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    5737             :       // (intrinsic_wo_chain:v2i32 686:iPTR, DPR:v2i32:$Vn, DPR:v2i32:$Vm)  =>  (VRHADDsv2i32:v2i32 DPR:v2i32:$Vn, DPR:v2i32:$Vm)
    5738             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv2i32,
    5739             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    5740             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    5741             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    5742             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5743             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5744             :       GIR_EraseFromParent, /*InsnID*/0,
    5745             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5746             :       GIR_Done,
    5747             :     // Label 174: @12932
    5748             :     GIM_Try, /*On fail goto*//*Label 175*/ 12996,
    5749             :       GIM_CheckFeatures, GIFBS_HasNEON,
    5750             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5751             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5752             :       // MIs[0] Vd
    5753             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    5754             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    5755             :       // MIs[0] Operand 1
    5756             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds,
    5757             :       // MIs[0] Vn
    5758             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    5759             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    5760             :       // MIs[0] Vm
    5761             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    5762             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    5763             :       // (intrinsic_wo_chain:v8i16 686:iPTR, QPR:v8i16:$Vn, QPR:v8i16:$Vm)  =>  (VRHADDsv8i16:v8i16 QPR:v8i16:$Vn, QPR:v8i16:$Vm)
    5764             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv8i16,
    5765             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    5766             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    5767             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    5768             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5769             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5770             :       GIR_EraseFromParent, /*InsnID*/0,
    5771             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5772             :       GIR_Done,
    5773             :     // Label 175: @12996
    5774             :     GIM_Try, /*On fail goto*//*Label 176*/ 13060,
    5775             :       GIM_CheckFeatures, GIFBS_HasNEON,
    5776             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5777             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5778             :       // MIs[0] Vd
    5779             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    5780             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    5781             :       // MIs[0] Operand 1
    5782             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds,
    5783             :       // MIs[0] Vn
    5784             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    5785             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    5786             :       // MIs[0] Vm
    5787             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    5788             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    5789             :       // (intrinsic_wo_chain:v4i32 686:iPTR, QPR:v4i32:$Vn, QPR:v4i32:$Vm)  =>  (VRHADDsv4i32:v4i32 QPR:v4i32:$Vn, QPR:v4i32:$Vm)
    5790             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv4i32,
    5791             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    5792             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    5793             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    5794             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5795             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5796             :       GIR_EraseFromParent, /*InsnID*/0,
    5797             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5798             :       GIR_Done,
    5799             :     // Label 176: @13060
    5800             :     GIM_Try, /*On fail goto*//*Label 177*/ 13124,
    5801             :       GIM_CheckFeatures, GIFBS_HasNEON,
    5802             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5803             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5804             :       // MIs[0] Vd
    5805             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    5806             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    5807             :       // MIs[0] Operand 1
    5808             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds,
    5809             :       // MIs[0] Vn
    5810             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    5811             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    5812             :       // MIs[0] Vm
    5813             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
    5814             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    5815             :       // (intrinsic_wo_chain:v8i8 686:iPTR, DPR:v8i8:$Vn, DPR:v8i8:$Vm)  =>  (VRHADDsv8i8:v8i8 DPR:v8i8:$Vn, DPR:v8i8:$Vm)
    5816             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv8i8,
    5817             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    5818             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    5819             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    5820             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5821             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5822             :       GIR_EraseFromParent, /*InsnID*/0,
    5823             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5824             :       GIR_Done,
    5825             :     // Label 177: @13124
    5826             :     GIM_Try, /*On fail goto*//*Label 178*/ 13188,
    5827             :       GIM_CheckFeatures, GIFBS_HasNEON,
    5828             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5829             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5830             :       // MIs[0] Vd
    5831             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    5832             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    5833             :       // MIs[0] Operand 1
    5834             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds,
    5835             :       // MIs[0] Vn
    5836             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    5837             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    5838             :       // MIs[0] Vm
    5839             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
    5840             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    5841             :       // (intrinsic_wo_chain:v16i8 686:iPTR, QPR:v16i8:$Vn, QPR:v16i8:$Vm)  =>  (VRHADDsv16i8:v16i8 QPR:v16i8:$Vn, QPR:v16i8:$Vm)
    5842             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv16i8,
    5843             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    5844             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    5845             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    5846             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5847             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5848             :       GIR_EraseFromParent, /*InsnID*/0,
    5849             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5850             :       GIR_Done,
    5851             :     // Label 178: @13188
    5852             :     GIM_Try, /*On fail goto*//*Label 179*/ 13252,
    5853             :       GIM_CheckFeatures, GIFBS_HasNEON,
    5854             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5855             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5856             :       // MIs[0] Vd
    5857             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    5858             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    5859             :       // MIs[0] Operand 1
    5860             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu,
    5861             :       // MIs[0] Vn
    5862             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    5863             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    5864             :       // MIs[0] Vm
    5865             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    5866             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    5867             :       // (intrinsic_wo_chain:v4i16 687:iPTR, DPR:v4i16:$Vn, DPR:v4i16:$Vm)  =>  (VRHADDuv4i16:v4i16 DPR:v4i16:$Vn, DPR:v4i16:$Vm)
    5868             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv4i16,
    5869             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    5870             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    5871             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    5872             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5873             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5874             :       GIR_EraseFromParent, /*InsnID*/0,
    5875             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5876             :       GIR_Done,
    5877             :     // Label 179: @13252
    5878             :     GIM_Try, /*On fail goto*//*Label 180*/ 13316,
    5879             :       GIM_CheckFeatures, GIFBS_HasNEON,
    5880             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5881             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5882             :       // MIs[0] Vd
    5883             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    5884             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    5885             :       // MIs[0] Operand 1
    5886             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu,
    5887             :       // MIs[0] Vn
    5888             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    5889             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    5890             :       // MIs[0] Vm
    5891             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    5892             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    5893             :       // (intrinsic_wo_chain:v2i32 687:iPTR, DPR:v2i32:$Vn, DPR:v2i32:$Vm)  =>  (VRHADDuv2i32:v2i32 DPR:v2i32:$Vn, DPR:v2i32:$Vm)
    5894             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv2i32,
    5895             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    5896             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    5897             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    5898             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5899             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5900             :       GIR_EraseFromParent, /*InsnID*/0,
    5901             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5902             :       GIR_Done,
    5903             :     // Label 180: @13316
    5904             :     GIM_Try, /*On fail goto*//*Label 181*/ 13380,
    5905             :       GIM_CheckFeatures, GIFBS_HasNEON,
    5906             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5907             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5908             :       // MIs[0] Vd
    5909             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    5910             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    5911             :       // MIs[0] Operand 1
    5912             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu,
    5913             :       // MIs[0] Vn
    5914             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    5915             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    5916             :       // MIs[0] Vm
    5917             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    5918             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    5919             :       // (intrinsic_wo_chain:v8i16 687:iPTR, QPR:v8i16:$Vn, QPR:v8i16:$Vm)  =>  (VRHADDuv8i16:v8i16 QPR:v8i16:$Vn, QPR:v8i16:$Vm)
    5920             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv8i16,
    5921             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    5922             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    5923             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    5924             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5925             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5926             :       GIR_EraseFromParent, /*InsnID*/0,
    5927             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5928             :       GIR_Done,
    5929             :     // Label 181: @13380
    5930             :     GIM_Try, /*On fail goto*//*Label 182*/ 13444,
    5931             :       GIM_CheckFeatures, GIFBS_HasNEON,
    5932             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5933             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5934             :       // MIs[0] Vd
    5935             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    5936             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    5937             :       // MIs[0] Operand 1
    5938             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu,
    5939             :       // MIs[0] Vn
    5940             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    5941             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    5942             :       // MIs[0] Vm
    5943             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    5944             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    5945             :       // (intrinsic_wo_chain:v4i32 687:iPTR, QPR:v4i32:$Vn, QPR:v4i32:$Vm)  =>  (VRHADDuv4i32:v4i32 QPR:v4i32:$Vn, QPR:v4i32:$Vm)
    5946             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv4i32,
    5947             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    5948             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    5949             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    5950             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5951             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5952             :       GIR_EraseFromParent, /*InsnID*/0,
    5953             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5954             :       GIR_Done,
    5955             :     // Label 182: @13444
    5956             :     GIM_Try, /*On fail goto*//*Label 183*/ 13508,
    5957             :       GIM_CheckFeatures, GIFBS_HasNEON,
    5958             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5959             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5960             :       // MIs[0] Vd
    5961             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    5962             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    5963             :       // MIs[0] Operand 1
    5964             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu,
    5965             :       // MIs[0] Vn
    5966             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    5967             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    5968             :       // MIs[0] Vm
    5969             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
    5970             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    5971             :       // (intrinsic_wo_chain:v8i8 687:iPTR, DPR:v8i8:$Vn, DPR:v8i8:$Vm)  =>  (VRHADDuv8i8:v8i8 DPR:v8i8:$Vn, DPR:v8i8:$Vm)
    5972             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv8i8,
    5973             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    5974             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    5975             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    5976             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    5977             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    5978             :       GIR_EraseFromParent, /*InsnID*/0,
    5979             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    5980             :       GIR_Done,
    5981             :     // Label 183: @13508
    5982             :     GIM_Try, /*On fail goto*//*Label 184*/ 13572,
    5983             :       GIM_CheckFeatures, GIFBS_HasNEON,
    5984             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    5985             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    5986             :       // MIs[0] Vd
    5987             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    5988             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    5989             :       // MIs[0] Operand 1
    5990             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu,
    5991             :       // MIs[0] Vn
    5992             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    5993             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    5994             :       // MIs[0] Vm
    5995             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
    5996             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    5997             :       // (intrinsic_wo_chain:v16i8 687:iPTR, QPR:v16i8:$Vn, QPR:v16i8:$Vm)  =>  (VRHADDuv16i8:v16i8 QPR:v16i8:$Vn, QPR:v16i8:$Vm)
    5998             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv16i8,
    5999             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6000             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6001             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6002             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6003             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6004             :       GIR_EraseFromParent, /*InsnID*/0,
    6005             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6006             :       GIR_Done,
    6007             :     // Label 184: @13572
    6008             :     GIM_Try, /*On fail goto*//*Label 185*/ 13636,
    6009             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6010             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6011             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6012             :       // MIs[0] Vd
    6013             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    6014             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    6015             :       // MIs[0] Operand 1
    6016             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
    6017             :       // MIs[0] Vn
    6018             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    6019             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    6020             :       // MIs[0] Vm
    6021             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    6022             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    6023             :       // (intrinsic_wo_chain:v4i16 661:iPTR, DPR:v4i16:$Vn, DPR:v4i16:$Vm)  =>  (VQADDsv4i16:v4i16 DPR:v4i16:$Vn, DPR:v4i16:$Vm)
    6024             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv4i16,
    6025             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6026             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6027             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6028             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6029             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6030             :       GIR_EraseFromParent, /*InsnID*/0,
    6031             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6032             :       GIR_Done,
    6033             :     // Label 185: @13636
    6034             :     GIM_Try, /*On fail goto*//*Label 186*/ 13700,
    6035             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6036             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6037             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6038             :       // MIs[0] Vd
    6039             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    6040             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    6041             :       // MIs[0] Operand 1
    6042             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
    6043             :       // MIs[0] Vn
    6044             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    6045             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    6046             :       // MIs[0] Vm
    6047             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    6048             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    6049             :       // (intrinsic_wo_chain:v2i32 661:iPTR, DPR:v2i32:$Vn, DPR:v2i32:$Vm)  =>  (VQADDsv2i32:v2i32 DPR:v2i32:$Vn, DPR:v2i32:$Vm)
    6050             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv2i32,
    6051             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6052             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6053             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6054             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6055             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6056             :       GIR_EraseFromParent, /*InsnID*/0,
    6057             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6058             :       GIR_Done,
    6059             :     // Label 186: @13700
    6060             :     GIM_Try, /*On fail goto*//*Label 187*/ 13764,
    6061             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6062             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6063             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6064             :       // MIs[0] Vd
    6065             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    6066             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    6067             :       // MIs[0] Operand 1
    6068             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
    6069             :       // MIs[0] Vn
    6070             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    6071             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    6072             :       // MIs[0] Vm
    6073             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    6074             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    6075             :       // (intrinsic_wo_chain:v8i16 661:iPTR, QPR:v8i16:$Vn, QPR:v8i16:$Vm)  =>  (VQADDsv8i16:v8i16 QPR:v8i16:$Vn, QPR:v8i16:$Vm)
    6076             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv8i16,
    6077             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6078             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6079             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6080             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6081             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6082             :       GIR_EraseFromParent, /*InsnID*/0,
    6083             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6084             :       GIR_Done,
    6085             :     // Label 187: @13764
    6086             :     GIM_Try, /*On fail goto*//*Label 188*/ 13828,
    6087             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6088             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6089             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6090             :       // MIs[0] Vd
    6091             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    6092             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    6093             :       // MIs[0] Operand 1
    6094             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
    6095             :       // MIs[0] Vn
    6096             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    6097             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    6098             :       // MIs[0] Vm
    6099             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    6100             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    6101             :       // (intrinsic_wo_chain:v4i32 661:iPTR, QPR:v4i32:$Vn, QPR:v4i32:$Vm)  =>  (VQADDsv4i32:v4i32 QPR:v4i32:$Vn, QPR:v4i32:$Vm)
    6102             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv4i32,
    6103             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6104             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6105             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6106             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6107             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6108             :       GIR_EraseFromParent, /*InsnID*/0,
    6109             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6110             :       GIR_Done,
    6111             :     // Label 188: @13828
    6112             :     GIM_Try, /*On fail goto*//*Label 189*/ 13892,
    6113             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6114             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6115             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6116             :       // MIs[0] Vd
    6117             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    6118             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    6119             :       // MIs[0] Operand 1
    6120             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
    6121             :       // MIs[0] Vn
    6122             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    6123             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    6124             :       // MIs[0] Vm
    6125             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
    6126             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    6127             :       // (intrinsic_wo_chain:v8i8 661:iPTR, DPR:v8i8:$Vn, DPR:v8i8:$Vm)  =>  (VQADDsv8i8:v8i8 DPR:v8i8:$Vn, DPR:v8i8:$Vm)
    6128             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv8i8,
    6129             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6130             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6131             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6132             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6133             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6134             :       GIR_EraseFromParent, /*InsnID*/0,
    6135             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6136             :       GIR_Done,
    6137             :     // Label 189: @13892
    6138             :     GIM_Try, /*On fail goto*//*Label 190*/ 13956,
    6139             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6140             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6141             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6142             :       // MIs[0] Vd
    6143             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    6144             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    6145             :       // MIs[0] Operand 1
    6146             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
    6147             :       // MIs[0] Vn
    6148             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    6149             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    6150             :       // MIs[0] Vm
    6151             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
    6152             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    6153             :       // (intrinsic_wo_chain:v16i8 661:iPTR, QPR:v16i8:$Vn, QPR:v16i8:$Vm)  =>  (VQADDsv16i8:v16i8 QPR:v16i8:$Vn, QPR:v16i8:$Vm)
    6154             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv16i8,
    6155             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6156             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6157             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6158             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6159             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6160             :       GIR_EraseFromParent, /*InsnID*/0,
    6161             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6162             :       GIR_Done,
    6163             :     // Label 190: @13956
    6164             :     GIM_Try, /*On fail goto*//*Label 191*/ 14020,
    6165             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6166             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6167             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6168             :       // MIs[0] Vd
    6169             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    6170             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    6171             :       // MIs[0] Operand 1
    6172             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
    6173             :       // MIs[0] Vn
    6174             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    6175             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    6176             :       // MIs[0] Vm
    6177             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    6178             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    6179             :       // (intrinsic_wo_chain:v1i64 661:iPTR, DPR:v1i64:$Vn, DPR:v1i64:$Vm)  =>  (VQADDsv1i64:v1i64 DPR:v1i64:$Vn, DPR:v1i64:$Vm)
    6180             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv1i64,
    6181             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6182             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6183             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6184             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6185             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6186             :       GIR_EraseFromParent, /*InsnID*/0,
    6187             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6188             :       GIR_Done,
    6189             :     // Label 191: @14020
    6190             :     GIM_Try, /*On fail goto*//*Label 192*/ 14084,
    6191             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6192             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6193             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6194             :       // MIs[0] Vd
    6195             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    6196             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    6197             :       // MIs[0] Operand 1
    6198             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
    6199             :       // MIs[0] Vn
    6200             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    6201             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    6202             :       // MIs[0] Vm
    6203             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
    6204             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    6205             :       // (intrinsic_wo_chain:v2i64 661:iPTR, QPR:v2i64:$Vn, QPR:v2i64:$Vm)  =>  (VQADDsv2i64:v2i64 QPR:v2i64:$Vn, QPR:v2i64:$Vm)
    6206             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv2i64,
    6207             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6208             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6209             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6210             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6211             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6212             :       GIR_EraseFromParent, /*InsnID*/0,
    6213             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6214             :       GIR_Done,
    6215             :     // Label 192: @14084
    6216             :     GIM_Try, /*On fail goto*//*Label 193*/ 14148,
    6217             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6218             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6219             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6220             :       // MIs[0] Vd
    6221             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    6222             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    6223             :       // MIs[0] Operand 1
    6224             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqaddu,
    6225             :       // MIs[0] Vn
    6226             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    6227             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    6228             :       // MIs[0] Vm
    6229             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    6230             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    6231             :       // (intrinsic_wo_chain:v4i16 662:iPTR, DPR:v4i16:$Vn, DPR:v4i16:$Vm)  =>  (VQADDuv4i16:v4i16 DPR:v4i16:$Vn, DPR:v4i16:$Vm)
    6232             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv4i16,
    6233             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6234             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6235             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6236             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6237             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6238             :       GIR_EraseFromParent, /*InsnID*/0,
    6239             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6240             :       GIR_Done,
    6241             :     // Label 193: @14148
    6242             :     GIM_Try, /*On fail goto*//*Label 194*/ 14212,
    6243             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6244             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6245             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6246             :       // MIs[0] Vd
    6247             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    6248             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    6249             :       // MIs[0] Operand 1
    6250             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqaddu,
    6251             :       // MIs[0] Vn
    6252             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    6253             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    6254             :       // MIs[0] Vm
    6255             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    6256             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    6257             :       // (intrinsic_wo_chain:v2i32 662:iPTR, DPR:v2i32:$Vn, DPR:v2i32:$Vm)  =>  (VQADDuv2i32:v2i32 DPR:v2i32:$Vn, DPR:v2i32:$Vm)
    6258             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv2i32,
    6259             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6260             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6261             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6262             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6263             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6264             :       GIR_EraseFromParent, /*InsnID*/0,
    6265             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6266             :       GIR_Done,
    6267             :     // Label 194: @14212
    6268             :     GIM_Try, /*On fail goto*//*Label 195*/ 14276,
    6269             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6270             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6271             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6272             :       // MIs[0] Vd
    6273             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    6274             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    6275             :       // MIs[0] Operand 1
    6276             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqaddu,
    6277             :       // MIs[0] Vn
    6278             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    6279             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    6280             :       // MIs[0] Vm
    6281             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    6282             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    6283             :       // (intrinsic_wo_chain:v8i16 662:iPTR, QPR:v8i16:$Vn, QPR:v8i16:$Vm)  =>  (VQADDuv8i16:v8i16 QPR:v8i16:$Vn, QPR:v8i16:$Vm)
    6284             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv8i16,
    6285             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6286             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6287             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6288             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6289             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6290             :       GIR_EraseFromParent, /*InsnID*/0,
    6291             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6292             :       GIR_Done,
    6293             :     // Label 195: @14276
    6294             :     GIM_Try, /*On fail goto*//*Label 196*/ 14340,
    6295             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6296             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6297             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6298             :       // MIs[0] Vd
    6299             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    6300             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    6301             :       // MIs[0] Operand 1
    6302             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqaddu,
    6303             :       // MIs[0] Vn
    6304             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    6305             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    6306             :       // MIs[0] Vm
    6307             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    6308             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    6309             :       // (intrinsic_wo_chain:v4i32 662:iPTR, QPR:v4i32:$Vn, QPR:v4i32:$Vm)  =>  (VQADDuv4i32:v4i32 QPR:v4i32:$Vn, QPR:v4i32:$Vm)
    6310             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv4i32,
    6311             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6312             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6313             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6314             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6315             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6316             :       GIR_EraseFromParent, /*InsnID*/0,
    6317             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6318             :       GIR_Done,
    6319             :     // Label 196: @14340
    6320             :     GIM_Try, /*On fail goto*//*Label 197*/ 14404,
    6321             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6322             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6323             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6324             :       // MIs[0] Vd
    6325             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    6326             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    6327             :       // MIs[0] Operand 1
    6328             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqaddu,
    6329             :       // MIs[0] Vn
    6330             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    6331             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    6332             :       // MIs[0] Vm
    6333             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
    6334             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    6335             :       // (intrinsic_wo_chain:v8i8 662:iPTR, DPR:v8i8:$Vn, DPR:v8i8:$Vm)  =>  (VQADDuv8i8:v8i8 DPR:v8i8:$Vn, DPR:v8i8:$Vm)
    6336             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv8i8,
    6337             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6338             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6339             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6340             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6341             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6342             :       GIR_EraseFromParent, /*InsnID*/0,
    6343             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6344             :       GIR_Done,
    6345             :     // Label 197: @14404
    6346             :     GIM_Try, /*On fail goto*//*Label 198*/ 14468,
    6347             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6348             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6349             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6350             :       // MIs[0] Vd
    6351             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    6352             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    6353             :       // MIs[0] Operand 1
    6354             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqaddu,
    6355             :       // MIs[0] Vn
    6356             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    6357             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    6358             :       // MIs[0] Vm
    6359             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
    6360             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    6361             :       // (intrinsic_wo_chain:v16i8 662:iPTR, QPR:v16i8:$Vn, QPR:v16i8:$Vm)  =>  (VQADDuv16i8:v16i8 QPR:v16i8:$Vn, QPR:v16i8:$Vm)
    6362             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv16i8,
    6363             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6364             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6365             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6366             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6367             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6368             :       GIR_EraseFromParent, /*InsnID*/0,
    6369             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6370             :       GIR_Done,
    6371             :     // Label 198: @14468
    6372             :     GIM_Try, /*On fail goto*//*Label 199*/ 14532,
    6373             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6374             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6375             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6376             :       // MIs[0] Vd
    6377             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    6378             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    6379             :       // MIs[0] Operand 1
    6380             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqaddu,
    6381             :       // MIs[0] Vn
    6382             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    6383             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    6384             :       // MIs[0] Vm
    6385             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    6386             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    6387             :       // (intrinsic_wo_chain:v1i64 662:iPTR, DPR:v1i64:$Vn, DPR:v1i64:$Vm)  =>  (VQADDuv1i64:v1i64 DPR:v1i64:$Vn, DPR:v1i64:$Vm)
    6388             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv1i64,
    6389             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6390             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6391             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6392             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6393             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6394             :       GIR_EraseFromParent, /*InsnID*/0,
    6395             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6396             :       GIR_Done,
    6397             :     // Label 199: @14532
    6398             :     GIM_Try, /*On fail goto*//*Label 200*/ 14596,
    6399             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6400             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6401             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6402             :       // MIs[0] Vd
    6403             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    6404             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    6405             :       // MIs[0] Operand 1
    6406             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqaddu,
    6407             :       // MIs[0] Vn
    6408             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    6409             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    6410             :       // MIs[0] Vm
    6411             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
    6412             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    6413             :       // (intrinsic_wo_chain:v2i64 662:iPTR, QPR:v2i64:$Vn, QPR:v2i64:$Vm)  =>  (VQADDuv2i64:v2i64 QPR:v2i64:$Vn, QPR:v2i64:$Vm)
    6414             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv2i64,
    6415             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6416             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6417             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6418             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6419             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6420             :       GIR_EraseFromParent, /*InsnID*/0,
    6421             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6422             :       GIR_Done,
    6423             :     // Label 200: @14596
    6424             :     GIM_Try, /*On fail goto*//*Label 201*/ 14660,
    6425             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6426             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6427             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6428             :       // MIs[0] Vd
    6429             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    6430             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    6431             :       // MIs[0] Operand 1
    6432             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vraddhn,
    6433             :       // MIs[0] Vn
    6434             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    6435             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    6436             :       // MIs[0] Vm
    6437             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    6438             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    6439             :       // (intrinsic_wo_chain:v8i8 683:iPTR, QPR:v8i16:$Vn, QPR:v8i16:$Vm)  =>  (VRADDHNv8i8:v8i8 QPR:v8i16:$Vn, QPR:v8i16:$Vm)
    6440             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRADDHNv8i8,
    6441             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6442             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6443             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6444             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6445             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6446             :       GIR_EraseFromParent, /*InsnID*/0,
    6447             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6448             :       GIR_Done,
    6449             :     // Label 201: @14660
    6450             :     GIM_Try, /*On fail goto*//*Label 202*/ 14724,
    6451             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6452             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6453             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6454             :       // MIs[0] Vd
    6455             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    6456             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    6457             :       // MIs[0] Operand 1
    6458             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vraddhn,
    6459             :       // MIs[0] Vn
    6460             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    6461             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    6462             :       // MIs[0] Vm
    6463             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    6464             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    6465             :       // (intrinsic_wo_chain:v4i16 683:iPTR, QPR:v4i32:$Vn, QPR:v4i32:$Vm)  =>  (VRADDHNv4i16:v4i16 QPR:v4i32:$Vn, QPR:v4i32:$Vm)
    6466             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRADDHNv4i16,
    6467             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6468             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6469             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6470             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6471             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6472             :       GIR_EraseFromParent, /*InsnID*/0,
    6473             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6474             :       GIR_Done,
    6475             :     // Label 202: @14724
    6476             :     GIM_Try, /*On fail goto*//*Label 203*/ 14788,
    6477             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6478             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6479             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6480             :       // MIs[0] Vd
    6481             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    6482             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    6483             :       // MIs[0] Operand 1
    6484             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vraddhn,
    6485             :       // MIs[0] Vn
    6486             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    6487             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    6488             :       // MIs[0] Vm
    6489             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
    6490             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    6491             :       // (intrinsic_wo_chain:v2i32 683:iPTR, QPR:v2i64:$Vn, QPR:v2i64:$Vm)  =>  (VRADDHNv2i32:v2i32 QPR:v2i64:$Vn, QPR:v2i64:$Vm)
    6492             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRADDHNv2i32,
    6493             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6494             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6495             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6496             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6497             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6498             :       GIR_EraseFromParent, /*InsnID*/0,
    6499             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6500             :       GIR_Done,
    6501             :     // Label 203: @14788
    6502             :     GIM_Try, /*On fail goto*//*Label 204*/ 14852,
    6503             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6504             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6505             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6506             :       // MIs[0] Vd
    6507             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    6508             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    6509             :       // MIs[0] Operand 1
    6510             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vmulp,
    6511             :       // MIs[0] Vn
    6512             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    6513             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    6514             :       // MIs[0] Vm
    6515             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
    6516             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    6517             :       // (intrinsic_wo_chain:v8i8 650:iPTR, DPR:v8i8:$Vn, DPR:v8i8:$Vm)  =>  (VMULpd:v8i8 DPR:v8i8:$Vn, DPR:v8i8:$Vm)
    6518             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULpd,
    6519             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6520             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6521             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6522             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6523             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6524             :       GIR_EraseFromParent, /*InsnID*/0,
    6525             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6526             :       GIR_Done,
    6527             :     // Label 204: @14852
    6528             :     GIM_Try, /*On fail goto*//*Label 205*/ 14916,
    6529             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6530             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6531             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6532             :       // MIs[0] Vd
    6533             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    6534             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    6535             :       // MIs[0] Operand 1
    6536             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vmulp,
    6537             :       // MIs[0] Vn
    6538             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    6539             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    6540             :       // MIs[0] Vm
    6541             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
    6542             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    6543             :       // (intrinsic_wo_chain:v16i8 650:iPTR, QPR:v16i8:$Vn, QPR:v16i8:$Vm)  =>  (VMULpq:v16i8 QPR:v16i8:$Vn, QPR:v16i8:$Vm)
    6544             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULpq,
    6545             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6546             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6547             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6548             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6549             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6550             :       GIR_EraseFromParent, /*InsnID*/0,
    6551             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6552             :       GIR_Done,
    6553             :     // Label 205: @14916
    6554             :     GIM_Try, /*On fail goto*//*Label 206*/ 14980,
    6555             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6556             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6557             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6558             :       // MIs[0] Vd
    6559             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    6560             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    6561             :       // MIs[0] Operand 1
    6562             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmulh,
    6563             :       // MIs[0] Vn
    6564             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    6565             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    6566             :       // MIs[0] Vm
    6567             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    6568             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    6569             :       // (intrinsic_wo_chain:v4i16 663:iPTR, DPR:v4i16:$Vn, DPR:v4i16:$Vm)  =>  (VQDMULHv4i16:v4i16 DPR:v4i16:$Vn, DPR:v4i16:$Vm)
    6570             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULHv4i16,
    6571             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6572             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6573             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6574             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6575             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6576             :       GIR_EraseFromParent, /*InsnID*/0,
    6577             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6578             :       GIR_Done,
    6579             :     // Label 206: @14980
    6580             :     GIM_Try, /*On fail goto*//*Label 207*/ 15044,
    6581             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6582             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6583             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6584             :       // MIs[0] Vd
    6585             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    6586             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    6587             :       // MIs[0] Operand 1
    6588             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmulh,
    6589             :       // MIs[0] Vn
    6590             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    6591             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    6592             :       // MIs[0] Vm
    6593             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    6594             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    6595             :       // (intrinsic_wo_chain:v2i32 663:iPTR, DPR:v2i32:$Vn, DPR:v2i32:$Vm)  =>  (VQDMULHv2i32:v2i32 DPR:v2i32:$Vn, DPR:v2i32:$Vm)
    6596             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULHv2i32,
    6597             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6598             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6599             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6600             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6601             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6602             :       GIR_EraseFromParent, /*InsnID*/0,
    6603             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6604             :       GIR_Done,
    6605             :     // Label 207: @15044
    6606             :     GIM_Try, /*On fail goto*//*Label 208*/ 15108,
    6607             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6608             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6609             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6610             :       // MIs[0] Vd
    6611             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    6612             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    6613             :       // MIs[0] Operand 1
    6614             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmulh,
    6615             :       // MIs[0] Vn
    6616             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    6617             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    6618             :       // MIs[0] Vm
    6619             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    6620             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    6621             :       // (intrinsic_wo_chain:v8i16 663:iPTR, QPR:v8i16:$Vn, QPR:v8i16:$Vm)  =>  (VQDMULHv8i16:v8i16 QPR:v8i16:$Vn, QPR:v8i16:$Vm)
    6622             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULHv8i16,
    6623             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6624             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6625             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6626             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6627             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6628             :       GIR_EraseFromParent, /*InsnID*/0,
    6629             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6630             :       GIR_Done,
    6631             :     // Label 208: @15108
    6632             :     GIM_Try, /*On fail goto*//*Label 209*/ 15172,
    6633             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6634             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6635             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6636             :       // MIs[0] Vd
    6637             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    6638             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    6639             :       // MIs[0] Operand 1
    6640             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmulh,
    6641             :       // MIs[0] Vn
    6642             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    6643             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    6644             :       // MIs[0] Vm
    6645             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    6646             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    6647             :       // (intrinsic_wo_chain:v4i32 663:iPTR, QPR:v4i32:$Vn, QPR:v4i32:$Vm)  =>  (VQDMULHv4i32:v4i32 QPR:v4i32:$Vn, QPR:v4i32:$Vm)
    6648             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULHv4i32,
    6649             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6650             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6651             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6652             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6653             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6654             :       GIR_EraseFromParent, /*InsnID*/0,
    6655             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6656             :       GIR_Done,
    6657             :     // Label 209: @15172
    6658             :     GIM_Try, /*On fail goto*//*Label 210*/ 15236,
    6659             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6660             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6661             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6662             :       // MIs[0] Vd
    6663             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    6664             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    6665             :       // MIs[0] Operand 1
    6666             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
    6667             :       // MIs[0] Vn
    6668             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    6669             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    6670             :       // MIs[0] Vm
    6671             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    6672             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    6673             :       // (intrinsic_wo_chain:v4i16 669:iPTR, DPR:v4i16:$Vn, DPR:v4i16:$Vm)  =>  (VQRDMULHv4i16:v4i16 DPR:v4i16:$Vn, DPR:v4i16:$Vm)
    6674             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMULHv4i16,
    6675             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6676             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6677             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6678             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6679             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6680             :       GIR_EraseFromParent, /*InsnID*/0,
    6681             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6682             :       GIR_Done,
    6683             :     // Label 210: @15236
    6684             :     GIM_Try, /*On fail goto*//*Label 211*/ 15300,
    6685             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6686             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6687             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6688             :       // MIs[0] Vd
    6689             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    6690             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    6691             :       // MIs[0] Operand 1
    6692             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
    6693             :       // MIs[0] Vn
    6694             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    6695             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    6696             :       // MIs[0] Vm
    6697             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    6698             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    6699             :       // (intrinsic_wo_chain:v2i32 669:iPTR, DPR:v2i32:$Vn, DPR:v2i32:$Vm)  =>  (VQRDMULHv2i32:v2i32 DPR:v2i32:$Vn, DPR:v2i32:$Vm)
    6700             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMULHv2i32,
    6701             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6702             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6703             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6704             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6705             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6706             :       GIR_EraseFromParent, /*InsnID*/0,
    6707             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6708             :       GIR_Done,
    6709             :     // Label 211: @15300
    6710             :     GIM_Try, /*On fail goto*//*Label 212*/ 15364,
    6711             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6712             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6713             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6714             :       // MIs[0] Vd
    6715             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    6716             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    6717             :       // MIs[0] Operand 1
    6718             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
    6719             :       // MIs[0] Vn
    6720             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    6721             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    6722             :       // MIs[0] Vm
    6723             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    6724             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    6725             :       // (intrinsic_wo_chain:v8i16 669:iPTR, QPR:v8i16:$Vn, QPR:v8i16:$Vm)  =>  (VQRDMULHv8i16:v8i16 QPR:v8i16:$Vn, QPR:v8i16:$Vm)
    6726             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMULHv8i16,
    6727             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6728             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6729             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6730             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6731             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6732             :       GIR_EraseFromParent, /*InsnID*/0,
    6733             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6734             :       GIR_Done,
    6735             :     // Label 212: @15364
    6736             :     GIM_Try, /*On fail goto*//*Label 213*/ 15428,
    6737             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6738             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6739             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6740             :       // MIs[0] Vd
    6741             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    6742             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    6743             :       // MIs[0] Operand 1
    6744             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
    6745             :       // MIs[0] Vn
    6746             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    6747             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    6748             :       // MIs[0] Vm
    6749             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    6750             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    6751             :       // (intrinsic_wo_chain:v4i32 669:iPTR, QPR:v4i32:$Vn, QPR:v4i32:$Vm)  =>  (VQRDMULHv4i32:v4i32 QPR:v4i32:$Vn, QPR:v4i32:$Vm)
    6752             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMULHv4i32,
    6753             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6754             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6755             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6756             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6757             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6758             :       GIR_EraseFromParent, /*InsnID*/0,
    6759             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6760             :       GIR_Done,
    6761             :     // Label 213: @15428
    6762             :     GIM_Try, /*On fail goto*//*Label 214*/ 15492,
    6763             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6764             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6765             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6766             :       // MIs[0] Vd
    6767             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    6768             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    6769             :       // MIs[0] Operand 1
    6770             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vmullp,
    6771             :       // MIs[0] Vn
    6772             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    6773             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    6774             :       // MIs[0] Vm
    6775             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
    6776             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    6777             :       // (intrinsic_wo_chain:v8i16 647:iPTR, DPR:v8i8:$Vn, DPR:v8i8:$Vm)  =>  (VMULLp8:v8i16 DPR:v8i8:$Vn, DPR:v8i8:$Vm)
    6778             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULLp8,
    6779             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6780             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6781             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6782             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6783             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6784             :       GIR_EraseFromParent, /*InsnID*/0,
    6785             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6786             :       GIR_Done,
    6787             :     // Label 214: @15492
    6788             :     GIM_Try, /*On fail goto*//*Label 215*/ 15550,
    6789             :       GIM_CheckFeatures, GIFBS_HasV8_HasCrypto,
    6790             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6791             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6792             :       // MIs[0] Vd
    6793             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    6794             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    6795             :       // MIs[0] Operand 1
    6796             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vmullp,
    6797             :       // MIs[0] Vn
    6798             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    6799             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    6800             :       // MIs[0] Vm
    6801             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    6802             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    6803             :       // (intrinsic_wo_chain:v2i64 647:iPTR, DPR:v1i64:$Vn, DPR:v1i64:$Vm)  =>  (VMULLp64:v2i64 DPR:v1i64:$Vn, DPR:v1i64:$Vm)
    6804             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULLp64,
    6805             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6806             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6807             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6808             :       GIR_EraseFromParent, /*InsnID*/0,
    6809             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6810             :       GIR_Done,
    6811             :     // Label 215: @15550
    6812             :     GIM_Try, /*On fail goto*//*Label 216*/ 15614,
    6813             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6814             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6815             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6816             :       // MIs[0] Vd
    6817             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    6818             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    6819             :       // MIs[0] Operand 1
    6820             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmull,
    6821             :       // MIs[0] Vn
    6822             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    6823             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    6824             :       // MIs[0] Vm
    6825             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    6826             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    6827             :       // (intrinsic_wo_chain:v4i32 664:iPTR, DPR:v4i16:$Vn, DPR:v4i16:$Vm)  =>  (VQDMULLv4i32:v4i32 DPR:v4i16:$Vn, DPR:v4i16:$Vm)
    6828             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULLv4i32,
    6829             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6830             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6831             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6832             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6833             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6834             :       GIR_EraseFromParent, /*InsnID*/0,
    6835             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6836             :       GIR_Done,
    6837             :     // Label 216: @15614
    6838             :     GIM_Try, /*On fail goto*//*Label 217*/ 15678,
    6839             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6840             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6841             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6842             :       // MIs[0] Vd
    6843             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    6844             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    6845             :       // MIs[0] Operand 1
    6846             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmull,
    6847             :       // MIs[0] Vn
    6848             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    6849             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    6850             :       // MIs[0] Vm
    6851             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    6852             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    6853             :       // (intrinsic_wo_chain:v2i64 664:iPTR, DPR:v2i32:$Vn, DPR:v2i32:$Vm)  =>  (VQDMULLv2i64:v2i64 DPR:v2i32:$Vn, DPR:v2i32:$Vm)
    6854             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULLv2i64,
    6855             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6856             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6857             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6858             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6859             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6860             :       GIR_EraseFromParent, /*InsnID*/0,
    6861             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6862             :       GIR_Done,
    6863             :     // Label 217: @15678
    6864             :     GIM_Try, /*On fail goto*//*Label 218*/ 15742,
    6865             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6866             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6867             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6868             :       // MIs[0] Vd
    6869             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    6870             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    6871             :       // MIs[0] Operand 1
    6872             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs,
    6873             :       // MIs[0] Vn
    6874             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    6875             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    6876             :       // MIs[0] Vm
    6877             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    6878             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    6879             :       // (intrinsic_wo_chain:v4i16 632:iPTR, DPR:v4i16:$Vn, DPR:v4i16:$Vm)  =>  (VHSUBsv4i16:v4i16 DPR:v4i16:$Vn, DPR:v4i16:$Vm)
    6880             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv4i16,
    6881             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6882             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6883             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6884             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6885             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6886             :       GIR_EraseFromParent, /*InsnID*/0,
    6887             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6888             :       GIR_Done,
    6889             :     // Label 218: @15742
    6890             :     GIM_Try, /*On fail goto*//*Label 219*/ 15806,
    6891             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6892             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6893             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6894             :       // MIs[0] Vd
    6895             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    6896             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    6897             :       // MIs[0] Operand 1
    6898             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs,
    6899             :       // MIs[0] Vn
    6900             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    6901             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    6902             :       // MIs[0] Vm
    6903             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    6904             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    6905             :       // (intrinsic_wo_chain:v2i32 632:iPTR, DPR:v2i32:$Vn, DPR:v2i32:$Vm)  =>  (VHSUBsv2i32:v2i32 DPR:v2i32:$Vn, DPR:v2i32:$Vm)
    6906             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv2i32,
    6907             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6908             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6909             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6910             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6911             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6912             :       GIR_EraseFromParent, /*InsnID*/0,
    6913             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6914             :       GIR_Done,
    6915             :     // Label 219: @15806
    6916             :     GIM_Try, /*On fail goto*//*Label 220*/ 15870,
    6917             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6918             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6919             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6920             :       // MIs[0] Vd
    6921             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    6922             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    6923             :       // MIs[0] Operand 1
    6924             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs,
    6925             :       // MIs[0] Vn
    6926             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    6927             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    6928             :       // MIs[0] Vm
    6929             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    6930             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    6931             :       // (intrinsic_wo_chain:v8i16 632:iPTR, QPR:v8i16:$Vn, QPR:v8i16:$Vm)  =>  (VHSUBsv8i16:v8i16 QPR:v8i16:$Vn, QPR:v8i16:$Vm)
    6932             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv8i16,
    6933             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6934             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6935             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6936             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6937             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6938             :       GIR_EraseFromParent, /*InsnID*/0,
    6939             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6940             :       GIR_Done,
    6941             :     // Label 220: @15870
    6942             :     GIM_Try, /*On fail goto*//*Label 221*/ 15934,
    6943             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6944             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6945             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6946             :       // MIs[0] Vd
    6947             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    6948             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    6949             :       // MIs[0] Operand 1
    6950             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs,
    6951             :       // MIs[0] Vn
    6952             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    6953             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    6954             :       // MIs[0] Vm
    6955             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    6956             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    6957             :       // (intrinsic_wo_chain:v4i32 632:iPTR, QPR:v4i32:$Vn, QPR:v4i32:$Vm)  =>  (VHSUBsv4i32:v4i32 QPR:v4i32:$Vn, QPR:v4i32:$Vm)
    6958             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv4i32,
    6959             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6960             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6961             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6962             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6963             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6964             :       GIR_EraseFromParent, /*InsnID*/0,
    6965             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6966             :       GIR_Done,
    6967             :     // Label 221: @15934
    6968             :     GIM_Try, /*On fail goto*//*Label 222*/ 15998,
    6969             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6970             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6971             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6972             :       // MIs[0] Vd
    6973             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    6974             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    6975             :       // MIs[0] Operand 1
    6976             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs,
    6977             :       // MIs[0] Vn
    6978             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    6979             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    6980             :       // MIs[0] Vm
    6981             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
    6982             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    6983             :       // (intrinsic_wo_chain:v8i8 632:iPTR, DPR:v8i8:$Vn, DPR:v8i8:$Vm)  =>  (VHSUBsv8i8:v8i8 DPR:v8i8:$Vn, DPR:v8i8:$Vm)
    6984             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv8i8,
    6985             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    6986             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    6987             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    6988             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    6989             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    6990             :       GIR_EraseFromParent, /*InsnID*/0,
    6991             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    6992             :       GIR_Done,
    6993             :     // Label 222: @15998
    6994             :     GIM_Try, /*On fail goto*//*Label 223*/ 16062,
    6995             :       GIM_CheckFeatures, GIFBS_HasNEON,
    6996             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    6997             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    6998             :       // MIs[0] Vd
    6999             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    7000             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    7001             :       // MIs[0] Operand 1
    7002             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs,
    7003             :       // MIs[0] Vn
    7004             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    7005             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    7006             :       // MIs[0] Vm
    7007             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
    7008             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    7009             :       // (intrinsic_wo_chain:v16i8 632:iPTR, QPR:v16i8:$Vn, QPR:v16i8:$Vm)  =>  (VHSUBsv16i8:v16i8 QPR:v16i8:$Vn, QPR:v16i8:$Vm)
    7010             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv16i8,
    7011             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7012             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7013             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7014             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7015             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7016             :       GIR_EraseFromParent, /*InsnID*/0,
    7017             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7018             :       GIR_Done,
    7019             :     // Label 223: @16062
    7020             :     GIM_Try, /*On fail goto*//*Label 224*/ 16126,
    7021             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7022             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7023             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7024             :       // MIs[0] Vd
    7025             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    7026             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    7027             :       // MIs[0] Operand 1
    7028             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu,
    7029             :       // MIs[0] Vn
    7030             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    7031             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    7032             :       // MIs[0] Vm
    7033             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    7034             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    7035             :       // (intrinsic_wo_chain:v4i16 633:iPTR, DPR:v4i16:$Vn, DPR:v4i16:$Vm)  =>  (VHSUBuv4i16:v4i16 DPR:v4i16:$Vn, DPR:v4i16:$Vm)
    7036             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv4i16,
    7037             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7038             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7039             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7040             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7041             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7042             :       GIR_EraseFromParent, /*InsnID*/0,
    7043             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7044             :       GIR_Done,
    7045             :     // Label 224: @16126
    7046             :     GIM_Try, /*On fail goto*//*Label 225*/ 16190,
    7047             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7048             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7049             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7050             :       // MIs[0] Vd
    7051             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    7052             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    7053             :       // MIs[0] Operand 1
    7054             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu,
    7055             :       // MIs[0] Vn
    7056             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    7057             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    7058             :       // MIs[0] Vm
    7059             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    7060             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    7061             :       // (intrinsic_wo_chain:v2i32 633:iPTR, DPR:v2i32:$Vn, DPR:v2i32:$Vm)  =>  (VHSUBuv2i32:v2i32 DPR:v2i32:$Vn, DPR:v2i32:$Vm)
    7062             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv2i32,
    7063             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7064             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7065             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7066             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7067             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7068             :       GIR_EraseFromParent, /*InsnID*/0,
    7069             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7070             :       GIR_Done,
    7071             :     // Label 225: @16190
    7072             :     GIM_Try, /*On fail goto*//*Label 226*/ 16254,
    7073             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7074             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7075             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7076             :       // MIs[0] Vd
    7077             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    7078             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    7079             :       // MIs[0] Operand 1
    7080             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu,
    7081             :       // MIs[0] Vn
    7082             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    7083             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    7084             :       // MIs[0] Vm
    7085             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    7086             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    7087             :       // (intrinsic_wo_chain:v8i16 633:iPTR, QPR:v8i16:$Vn, QPR:v8i16:$Vm)  =>  (VHSUBuv8i16:v8i16 QPR:v8i16:$Vn, QPR:v8i16:$Vm)
    7088             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv8i16,
    7089             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7090             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7091             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7092             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7093             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7094             :       GIR_EraseFromParent, /*InsnID*/0,
    7095             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7096             :       GIR_Done,
    7097             :     // Label 226: @16254
    7098             :     GIM_Try, /*On fail goto*//*Label 227*/ 16318,
    7099             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7100             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7101             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7102             :       // MIs[0] Vd
    7103             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    7104             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    7105             :       // MIs[0] Operand 1
    7106             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu,
    7107             :       // MIs[0] Vn
    7108             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    7109             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    7110             :       // MIs[0] Vm
    7111             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    7112             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    7113             :       // (intrinsic_wo_chain:v4i32 633:iPTR, QPR:v4i32:$Vn, QPR:v4i32:$Vm)  =>  (VHSUBuv4i32:v4i32 QPR:v4i32:$Vn, QPR:v4i32:$Vm)
    7114             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv4i32,
    7115             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7116             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7117             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7118             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7119             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7120             :       GIR_EraseFromParent, /*InsnID*/0,
    7121             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7122             :       GIR_Done,
    7123             :     // Label 227: @16318
    7124             :     GIM_Try, /*On fail goto*//*Label 228*/ 16382,
    7125             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7126             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7127             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7128             :       // MIs[0] Vd
    7129             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    7130             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    7131             :       // MIs[0] Operand 1
    7132             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu,
    7133             :       // MIs[0] Vn
    7134             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    7135             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    7136             :       // MIs[0] Vm
    7137             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
    7138             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    7139             :       // (intrinsic_wo_chain:v8i8 633:iPTR, DPR:v8i8:$Vn, DPR:v8i8:$Vm)  =>  (VHSUBuv8i8:v8i8 DPR:v8i8:$Vn, DPR:v8i8:$Vm)
    7140             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv8i8,
    7141             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7142             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7143             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7144             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7145             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7146             :       GIR_EraseFromParent, /*InsnID*/0,
    7147             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7148             :       GIR_Done,
    7149             :     // Label 228: @16382
    7150             :     GIM_Try, /*On fail goto*//*Label 229*/ 16446,
    7151             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7152             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7153             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7154             :       // MIs[0] Vd
    7155             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    7156             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    7157             :       // MIs[0] Operand 1
    7158             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu,
    7159             :       // MIs[0] Vn
    7160             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    7161             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    7162             :       // MIs[0] Vm
    7163             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
    7164             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    7165             :       // (intrinsic_wo_chain:v16i8 633:iPTR, QPR:v16i8:$Vn, QPR:v16i8:$Vm)  =>  (VHSUBuv16i8:v16i8 QPR:v16i8:$Vn, QPR:v16i8:$Vm)
    7166             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv16i8,
    7167             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7168             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7169             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7170             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7171             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7172             :       GIR_EraseFromParent, /*InsnID*/0,
    7173             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7174             :       GIR_Done,
    7175             :     // Label 229: @16446
    7176             :     GIM_Try, /*On fail goto*//*Label 230*/ 16510,
    7177             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7178             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7179             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7180             :       // MIs[0] Vd
    7181             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    7182             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    7183             :       // MIs[0] Operand 1
    7184             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubs,
    7185             :       // MIs[0] Vn
    7186             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    7187             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    7188             :       // MIs[0] Vm
    7189             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    7190             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    7191             :       // (intrinsic_wo_chain:v4i16 681:iPTR, DPR:v4i16:$Vn, DPR:v4i16:$Vm)  =>  (VQSUBsv4i16:v4i16 DPR:v4i16:$Vn, DPR:v4i16:$Vm)
    7192             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv4i16,
    7193             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7194             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7195             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7196             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7197             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7198             :       GIR_EraseFromParent, /*InsnID*/0,
    7199             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7200             :       GIR_Done,
    7201             :     // Label 230: @16510
    7202             :     GIM_Try, /*On fail goto*//*Label 231*/ 16574,
    7203             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7204             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7205             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7206             :       // MIs[0] Vd
    7207             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    7208             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    7209             :       // MIs[0] Operand 1
    7210             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubs,
    7211             :       // MIs[0] Vn
    7212             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    7213             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    7214             :       // MIs[0] Vm
    7215             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    7216             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    7217             :       // (intrinsic_wo_chain:v2i32 681:iPTR, DPR:v2i32:$Vn, DPR:v2i32:$Vm)  =>  (VQSUBsv2i32:v2i32 DPR:v2i32:$Vn, DPR:v2i32:$Vm)
    7218             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv2i32,
    7219             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7220             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7221             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7222             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7223             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7224             :       GIR_EraseFromParent, /*InsnID*/0,
    7225             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7226             :       GIR_Done,
    7227             :     // Label 231: @16574
    7228             :     GIM_Try, /*On fail goto*//*Label 232*/ 16638,
    7229             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7230             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7231             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7232             :       // MIs[0] Vd
    7233             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    7234             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    7235             :       // MIs[0] Operand 1
    7236             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubs,
    7237             :       // MIs[0] Vn
    7238             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    7239             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    7240             :       // MIs[0] Vm
    7241             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    7242             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    7243             :       // (intrinsic_wo_chain:v8i16 681:iPTR, QPR:v8i16:$Vn, QPR:v8i16:$Vm)  =>  (VQSUBsv8i16:v8i16 QPR:v8i16:$Vn, QPR:v8i16:$Vm)
    7244             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv8i16,
    7245             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7246             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7247             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7248             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7249             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7250             :       GIR_EraseFromParent, /*InsnID*/0,
    7251             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7252             :       GIR_Done,
    7253             :     // Label 232: @16638
    7254             :     GIM_Try, /*On fail goto*//*Label 233*/ 16702,
    7255             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7256             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7257             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7258             :       // MIs[0] Vd
    7259             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    7260             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    7261             :       // MIs[0] Operand 1
    7262             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubs,
    7263             :       // MIs[0] Vn
    7264             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    7265             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    7266             :       // MIs[0] Vm
    7267             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    7268             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    7269             :       // (intrinsic_wo_chain:v4i32 681:iPTR, QPR:v4i32:$Vn, QPR:v4i32:$Vm)  =>  (VQSUBsv4i32:v4i32 QPR:v4i32:$Vn, QPR:v4i32:$Vm)
    7270             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv4i32,
    7271             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7272             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7273             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7274             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7275             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7276             :       GIR_EraseFromParent, /*InsnID*/0,
    7277             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7278             :       GIR_Done,
    7279             :     // Label 233: @16702
    7280             :     GIM_Try, /*On fail goto*//*Label 234*/ 16766,
    7281             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7282             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7283             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7284             :       // MIs[0] Vd
    7285             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    7286             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    7287             :       // MIs[0] Operand 1
    7288             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubs,
    7289             :       // MIs[0] Vn
    7290             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    7291             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    7292             :       // MIs[0] Vm
    7293             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
    7294             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    7295             :       // (intrinsic_wo_chain:v8i8 681:iPTR, DPR:v8i8:$Vn, DPR:v8i8:$Vm)  =>  (VQSUBsv8i8:v8i8 DPR:v8i8:$Vn, DPR:v8i8:$Vm)
    7296             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv8i8,
    7297             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7298             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7299             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7300             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7301             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7302             :       GIR_EraseFromParent, /*InsnID*/0,
    7303             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7304             :       GIR_Done,
    7305             :     // Label 234: @16766
    7306             :     GIM_Try, /*On fail goto*//*Label 235*/ 16830,
    7307             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7308             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7309             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7310             :       // MIs[0] Vd
    7311             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    7312             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    7313             :       // MIs[0] Operand 1
    7314             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubs,
    7315             :       // MIs[0] Vn
    7316             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    7317             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    7318             :       // MIs[0] Vm
    7319             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
    7320             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    7321             :       // (intrinsic_wo_chain:v16i8 681:iPTR, QPR:v16i8:$Vn, QPR:v16i8:$Vm)  =>  (VQSUBsv16i8:v16i8 QPR:v16i8:$Vn, QPR:v16i8:$Vm)
    7322             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv16i8,
    7323             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7324             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7325             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7326             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7327             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7328             :       GIR_EraseFromParent, /*InsnID*/0,
    7329             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7330             :       GIR_Done,
    7331             :     // Label 235: @16830
    7332             :     GIM_Try, /*On fail goto*//*Label 236*/ 16894,
    7333             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7334             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7335             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7336             :       // MIs[0] Vd
    7337             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    7338             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    7339             :       // MIs[0] Operand 1
    7340             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubs,
    7341             :       // MIs[0] Vn
    7342             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    7343             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    7344             :       // MIs[0] Vm
    7345             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    7346             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    7347             :       // (intrinsic_wo_chain:v1i64 681:iPTR, DPR:v1i64:$Vn, DPR:v1i64:$Vm)  =>  (VQSUBsv1i64:v1i64 DPR:v1i64:$Vn, DPR:v1i64:$Vm)
    7348             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv1i64,
    7349             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7350             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7351             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7352             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7353             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7354             :       GIR_EraseFromParent, /*InsnID*/0,
    7355             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7356             :       GIR_Done,
    7357             :     // Label 236: @16894
    7358             :     GIM_Try, /*On fail goto*//*Label 237*/ 16958,
    7359             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7360             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7361             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7362             :       // MIs[0] Vd
    7363             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    7364             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    7365             :       // MIs[0] Operand 1
    7366             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubs,
    7367             :       // MIs[0] Vn
    7368             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    7369             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    7370             :       // MIs[0] Vm
    7371             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
    7372             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    7373             :       // (intrinsic_wo_chain:v2i64 681:iPTR, QPR:v2i64:$Vn, QPR:v2i64:$Vm)  =>  (VQSUBsv2i64:v2i64 QPR:v2i64:$Vn, QPR:v2i64:$Vm)
    7374             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv2i64,
    7375             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7376             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7377             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7378             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7379             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7380             :       GIR_EraseFromParent, /*InsnID*/0,
    7381             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7382             :       GIR_Done,
    7383             :     // Label 237: @16958
    7384             :     GIM_Try, /*On fail goto*//*Label 238*/ 17022,
    7385             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7386             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7387             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7388             :       // MIs[0] Vd
    7389             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    7390             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    7391             :       // MIs[0] Operand 1
    7392             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubu,
    7393             :       // MIs[0] Vn
    7394             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    7395             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    7396             :       // MIs[0] Vm
    7397             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    7398             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    7399             :       // (intrinsic_wo_chain:v4i16 682:iPTR, DPR:v4i16:$Vn, DPR:v4i16:$Vm)  =>  (VQSUBuv4i16:v4i16 DPR:v4i16:$Vn, DPR:v4i16:$Vm)
    7400             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv4i16,
    7401             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7402             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7403             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7404             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7405             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7406             :       GIR_EraseFromParent, /*InsnID*/0,
    7407             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7408             :       GIR_Done,
    7409             :     // Label 238: @17022
    7410             :     GIM_Try, /*On fail goto*//*Label 239*/ 17086,
    7411             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7412             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7413             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7414             :       // MIs[0] Vd
    7415             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    7416             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    7417             :       // MIs[0] Operand 1
    7418             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubu,
    7419             :       // MIs[0] Vn
    7420             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    7421             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    7422             :       // MIs[0] Vm
    7423             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    7424             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    7425             :       // (intrinsic_wo_chain:v2i32 682:iPTR, DPR:v2i32:$Vn, DPR:v2i32:$Vm)  =>  (VQSUBuv2i32:v2i32 DPR:v2i32:$Vn, DPR:v2i32:$Vm)
    7426             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv2i32,
    7427             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7428             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7429             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7430             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7431             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7432             :       GIR_EraseFromParent, /*InsnID*/0,
    7433             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7434             :       GIR_Done,
    7435             :     // Label 239: @17086
    7436             :     GIM_Try, /*On fail goto*//*Label 240*/ 17150,
    7437             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7438             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7439             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7440             :       // MIs[0] Vd
    7441             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    7442             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    7443             :       // MIs[0] Operand 1
    7444             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubu,
    7445             :       // MIs[0] Vn
    7446             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    7447             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    7448             :       // MIs[0] Vm
    7449             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    7450             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    7451             :       // (intrinsic_wo_chain:v8i16 682:iPTR, QPR:v8i16:$Vn, QPR:v8i16:$Vm)  =>  (VQSUBuv8i16:v8i16 QPR:v8i16:$Vn, QPR:v8i16:$Vm)
    7452             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv8i16,
    7453             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7454             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7455             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7456             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7457             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7458             :       GIR_EraseFromParent, /*InsnID*/0,
    7459             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7460             :       GIR_Done,
    7461             :     // Label 240: @17150
    7462             :     GIM_Try, /*On fail goto*//*Label 241*/ 17214,
    7463             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7464             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7465             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7466             :       // MIs[0] Vd
    7467             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    7468             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    7469             :       // MIs[0] Operand 1
    7470             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubu,
    7471             :       // MIs[0] Vn
    7472             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    7473             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    7474             :       // MIs[0] Vm
    7475             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    7476             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    7477             :       // (intrinsic_wo_chain:v4i32 682:iPTR, QPR:v4i32:$Vn, QPR:v4i32:$Vm)  =>  (VQSUBuv4i32:v4i32 QPR:v4i32:$Vn, QPR:v4i32:$Vm)
    7478             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv4i32,
    7479             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7480             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7481             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7482             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7483             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7484             :       GIR_EraseFromParent, /*InsnID*/0,
    7485             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7486             :       GIR_Done,
    7487             :     // Label 241: @17214
    7488             :     GIM_Try, /*On fail goto*//*Label 242*/ 17278,
    7489             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7490             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7491             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7492             :       // MIs[0] Vd
    7493             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    7494             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    7495             :       // MIs[0] Operand 1
    7496             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubu,
    7497             :       // MIs[0] Vn
    7498             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    7499             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    7500             :       // MIs[0] Vm
    7501             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
    7502             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    7503             :       // (intrinsic_wo_chain:v8i8 682:iPTR, DPR:v8i8:$Vn, DPR:v8i8:$Vm)  =>  (VQSUBuv8i8:v8i8 DPR:v8i8:$Vn, DPR:v8i8:$Vm)
    7504             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv8i8,
    7505             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7506             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7507             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7508             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7509             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7510             :       GIR_EraseFromParent, /*InsnID*/0,
    7511             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7512             :       GIR_Done,
    7513             :     // Label 242: @17278
    7514             :     GIM_Try, /*On fail goto*//*Label 243*/ 17342,
    7515             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7516             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7517             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7518             :       // MIs[0] Vd
    7519             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    7520             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    7521             :       // MIs[0] Operand 1
    7522             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubu,
    7523             :       // MIs[0] Vn
    7524             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    7525             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    7526             :       // MIs[0] Vm
    7527             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
    7528             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    7529             :       // (intrinsic_wo_chain:v16i8 682:iPTR, QPR:v16i8:$Vn, QPR:v16i8:$Vm)  =>  (VQSUBuv16i8:v16i8 QPR:v16i8:$Vn, QPR:v16i8:$Vm)
    7530             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv16i8,
    7531             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7532             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7533             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7534             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7535             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7536             :       GIR_EraseFromParent, /*InsnID*/0,
    7537             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7538             :       GIR_Done,
    7539             :     // Label 243: @17342
    7540             :     GIM_Try, /*On fail goto*//*Label 244*/ 17406,
    7541             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7542             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7543             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7544             :       // MIs[0] Vd
    7545             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    7546             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    7547             :       // MIs[0] Operand 1
    7548             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubu,
    7549             :       // MIs[0] Vn
    7550             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    7551             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    7552             :       // MIs[0] Vm
    7553             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    7554             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    7555             :       // (intrinsic_wo_chain:v1i64 682:iPTR, DPR:v1i64:$Vn, DPR:v1i64:$Vm)  =>  (VQSUBuv1i64:v1i64 DPR:v1i64:$Vn, DPR:v1i64:$Vm)
    7556             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv1i64,
    7557             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7558             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7559             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7560             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7561             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7562             :       GIR_EraseFromParent, /*InsnID*/0,
    7563             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7564             :       GIR_Done,
    7565             :     // Label 244: @17406
    7566             :     GIM_Try, /*On fail goto*//*Label 245*/ 17470,
    7567             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7568             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7569             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7570             :       // MIs[0] Vd
    7571             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    7572             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    7573             :       // MIs[0] Operand 1
    7574             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubu,
    7575             :       // MIs[0] Vn
    7576             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    7577             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    7578             :       // MIs[0] Vm
    7579             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
    7580             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    7581             :       // (intrinsic_wo_chain:v2i64 682:iPTR, QPR:v2i64:$Vn, QPR:v2i64:$Vm)  =>  (VQSUBuv2i64:v2i64 QPR:v2i64:$Vn, QPR:v2i64:$Vm)
    7582             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv2i64,
    7583             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7584             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7585             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7586             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7587             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7588             :       GIR_EraseFromParent, /*InsnID*/0,
    7589             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7590             :       GIR_Done,
    7591             :     // Label 245: @17470
    7592             :     GIM_Try, /*On fail goto*//*Label 246*/ 17534,
    7593             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7594             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7595             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7596             :       // MIs[0] Vd
    7597             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    7598             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    7599             :       // MIs[0] Operand 1
    7600             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsubhn,
    7601             :       // MIs[0] Vn
    7602             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    7603             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    7604             :       // MIs[0] Vm
    7605             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    7606             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    7607             :       // (intrinsic_wo_chain:v8i8 699:iPTR, QPR:v8i16:$Vn, QPR:v8i16:$Vm)  =>  (VRSUBHNv8i8:v8i8 QPR:v8i16:$Vn, QPR:v8i16:$Vm)
    7608             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSUBHNv8i8,
    7609             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7610             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7611             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7612             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7613             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7614             :       GIR_EraseFromParent, /*InsnID*/0,
    7615             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7616             :       GIR_Done,
    7617             :     // Label 246: @17534
    7618             :     GIM_Try, /*On fail goto*//*Label 247*/ 17598,
    7619             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7620             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7621             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7622             :       // MIs[0] Vd
    7623             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    7624             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    7625             :       // MIs[0] Operand 1
    7626             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsubhn,
    7627             :       // MIs[0] Vn
    7628             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    7629             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    7630             :       // MIs[0] Vm
    7631             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    7632             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    7633             :       // (intrinsic_wo_chain:v4i16 699:iPTR, QPR:v4i32:$Vn, QPR:v4i32:$Vm)  =>  (VRSUBHNv4i16:v4i16 QPR:v4i32:$Vn, QPR:v4i32:$Vm)
    7634             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSUBHNv4i16,
    7635             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7636             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7637             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7638             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7639             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7640             :       GIR_EraseFromParent, /*InsnID*/0,
    7641             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7642             :       GIR_Done,
    7643             :     // Label 247: @17598
    7644             :     GIM_Try, /*On fail goto*//*Label 248*/ 17662,
    7645             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7646             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7647             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7648             :       // MIs[0] Vd
    7649             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    7650             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    7651             :       // MIs[0] Operand 1
    7652             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsubhn,
    7653             :       // MIs[0] Vn
    7654             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    7655             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    7656             :       // MIs[0] Vm
    7657             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
    7658             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    7659             :       // (intrinsic_wo_chain:v2i32 699:iPTR, QPR:v2i64:$Vn, QPR:v2i64:$Vm)  =>  (VRSUBHNv2i32:v2i32 QPR:v2i64:$Vn, QPR:v2i64:$Vm)
    7660             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSUBHNv2i32,
    7661             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7662             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7663             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7664             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7665             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7666             :       GIR_EraseFromParent, /*InsnID*/0,
    7667             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7668             :       GIR_Done,
    7669             :     // Label 248: @17662
    7670             :     GIM_Try, /*On fail goto*//*Label 249*/ 17726,
    7671             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7672             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7673             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7674             :       // MIs[0] Vd
    7675             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    7676             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    7677             :       // MIs[0] Operand 1
    7678             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacge,
    7679             :       // MIs[0] Vn
    7680             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    7681             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    7682             :       // MIs[0] Vm
    7683             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    7684             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    7685             :       // (intrinsic_wo_chain:v2i32 612:iPTR, DPR:v2f32:$Vn, DPR:v2f32:$Vm)  =>  (VACGEfd:v2i32 DPR:v2f32:$Vn, DPR:v2f32:$Vm)
    7686             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGEfd,
    7687             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7688             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7689             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7690             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7691             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7692             :       GIR_EraseFromParent, /*InsnID*/0,
    7693             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7694             :       GIR_Done,
    7695             :     // Label 249: @17726
    7696             :     GIM_Try, /*On fail goto*//*Label 250*/ 17790,
    7697             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7698             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7699             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7700             :       // MIs[0] Vd
    7701             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    7702             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    7703             :       // MIs[0] Operand 1
    7704             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacge,
    7705             :       // MIs[0] Vn
    7706             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    7707             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    7708             :       // MIs[0] Vm
    7709             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    7710             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    7711             :       // (intrinsic_wo_chain:v4i32 612:iPTR, QPR:v4f32:$Vn, QPR:v4f32:$Vm)  =>  (VACGEfq:v4i32 QPR:v4f32:$Vn, QPR:v4f32:$Vm)
    7712             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGEfq,
    7713             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7714             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7715             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7716             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7717             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7718             :       GIR_EraseFromParent, /*InsnID*/0,
    7719             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7720             :       GIR_Done,
    7721             :     // Label 250: @17790
    7722             :     GIM_Try, /*On fail goto*//*Label 251*/ 17854,
    7723             :       GIM_CheckFeatures, GIFBS_HasNEON_HasFullFP16,
    7724             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7725             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7726             :       // MIs[0] Vd
    7727             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    7728             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    7729             :       // MIs[0] Operand 1
    7730             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacge,
    7731             :       // MIs[0] Vn
    7732             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    7733             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    7734             :       // MIs[0] Vm
    7735             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    7736             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    7737             :       // (intrinsic_wo_chain:v4i16 612:iPTR, DPR:v4f16:$Vn, DPR:v4f16:$Vm)  =>  (VACGEhd:v4i16 DPR:v4f16:$Vn, DPR:v4f16:$Vm)
    7738             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGEhd,
    7739             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7740             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7741             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7742             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7743             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7744             :       GIR_EraseFromParent, /*InsnID*/0,
    7745             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7746             :       GIR_Done,
    7747             :     // Label 251: @17854
    7748             :     GIM_Try, /*On fail goto*//*Label 252*/ 17918,
    7749             :       GIM_CheckFeatures, GIFBS_HasNEON_HasFullFP16,
    7750             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7751             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7752             :       // MIs[0] Vd
    7753             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    7754             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    7755             :       // MIs[0] Operand 1
    7756             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacge,
    7757             :       // MIs[0] Vn
    7758             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    7759             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    7760             :       // MIs[0] Vm
    7761             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    7762             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    7763             :       // (intrinsic_wo_chain:v8i16 612:iPTR, QPR:v8f16:$Vn, QPR:v8f16:$Vm)  =>  (VACGEhq:v8i16 QPR:v8f16:$Vn, QPR:v8f16:$Vm)
    7764             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGEhq,
    7765             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7766             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7767             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7768             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7769             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7770             :       GIR_EraseFromParent, /*InsnID*/0,
    7771             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7772             :       GIR_Done,
    7773             :     // Label 252: @17918
    7774             :     GIM_Try, /*On fail goto*//*Label 253*/ 17982,
    7775             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7776             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7777             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7778             :       // MIs[0] Vd
    7779             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    7780             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    7781             :       // MIs[0] Operand 1
    7782             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacgt,
    7783             :       // MIs[0] Vn
    7784             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    7785             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    7786             :       // MIs[0] Vm
    7787             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    7788             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    7789             :       // (intrinsic_wo_chain:v2i32 613:iPTR, DPR:v2f32:$Vn, DPR:v2f32:$Vm)  =>  (VACGTfd:v2i32 DPR:v2f32:$Vn, DPR:v2f32:$Vm)
    7790             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGTfd,
    7791             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7792             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7793             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7794             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7795             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7796             :       GIR_EraseFromParent, /*InsnID*/0,
    7797             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7798             :       GIR_Done,
    7799             :     // Label 253: @17982
    7800             :     GIM_Try, /*On fail goto*//*Label 254*/ 18046,
    7801             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7802             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7803             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7804             :       // MIs[0] Vd
    7805             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    7806             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    7807             :       // MIs[0] Operand 1
    7808             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacgt,
    7809             :       // MIs[0] Vn
    7810             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    7811             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    7812             :       // MIs[0] Vm
    7813             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    7814             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    7815             :       // (intrinsic_wo_chain:v4i32 613:iPTR, QPR:v4f32:$Vn, QPR:v4f32:$Vm)  =>  (VACGTfq:v4i32 QPR:v4f32:$Vn, QPR:v4f32:$Vm)
    7816             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGTfq,
    7817             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7818             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7819             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7820             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7821             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7822             :       GIR_EraseFromParent, /*InsnID*/0,
    7823             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7824             :       GIR_Done,
    7825             :     // Label 254: @18046
    7826             :     GIM_Try, /*On fail goto*//*Label 255*/ 18110,
    7827             :       GIM_CheckFeatures, GIFBS_HasNEON_HasFullFP16,
    7828             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7829             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7830             :       // MIs[0] Vd
    7831             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    7832             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    7833             :       // MIs[0] Operand 1
    7834             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacgt,
    7835             :       // MIs[0] Vn
    7836             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    7837             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    7838             :       // MIs[0] Vm
    7839             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    7840             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    7841             :       // (intrinsic_wo_chain:v4i16 613:iPTR, DPR:v4f16:$Vn, DPR:v4f16:$Vm)  =>  (VACGThd:v4i16 DPR:v4f16:$Vn, DPR:v4f16:$Vm)
    7842             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGThd,
    7843             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7844             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7845             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7846             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7847             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7848             :       GIR_EraseFromParent, /*InsnID*/0,
    7849             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7850             :       GIR_Done,
    7851             :     // Label 255: @18110
    7852             :     GIM_Try, /*On fail goto*//*Label 256*/ 18174,
    7853             :       GIM_CheckFeatures, GIFBS_HasNEON_HasFullFP16,
    7854             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7855             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7856             :       // MIs[0] Vd
    7857             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    7858             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    7859             :       // MIs[0] Operand 1
    7860             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacgt,
    7861             :       // MIs[0] Vn
    7862             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    7863             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    7864             :       // MIs[0] Vm
    7865             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    7866             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    7867             :       // (intrinsic_wo_chain:v8f16 613:iPTR, QPR:v8f16:$Vn, QPR:v8f16:$Vm)  =>  (VACGThq:v8f16 QPR:v8f16:$Vn, QPR:v8f16:$Vm)
    7868             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGThq,
    7869             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7870             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7871             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7872             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7873             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7874             :       GIR_EraseFromParent, /*InsnID*/0,
    7875             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7876             :       GIR_Done,
    7877             :     // Label 256: @18174
    7878             :     GIM_Try, /*On fail goto*//*Label 257*/ 18238,
    7879             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7880             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7881             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7882             :       // MIs[0] Vd
    7883             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    7884             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    7885             :       // MIs[0] Operand 1
    7886             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
    7887             :       // MIs[0] Vn
    7888             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    7889             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    7890             :       // MIs[0] Vm
    7891             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    7892             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    7893             :       // (intrinsic_wo_chain:v4i16 609:iPTR, DPR:v4i16:$Vn, DPR:v4i16:$Vm)  =>  (VABDsv4i16:v4i16 DPR:v4i16:$Vn, DPR:v4i16:$Vm)
    7894             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv4i16,
    7895             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7896             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7897             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7898             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7899             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7900             :       GIR_EraseFromParent, /*InsnID*/0,
    7901             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7902             :       GIR_Done,
    7903             :     // Label 257: @18238
    7904             :     GIM_Try, /*On fail goto*//*Label 258*/ 18302,
    7905             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7906             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7907             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7908             :       // MIs[0] Vd
    7909             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    7910             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    7911             :       // MIs[0] Operand 1
    7912             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
    7913             :       // MIs[0] Vn
    7914             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    7915             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    7916             :       // MIs[0] Vm
    7917             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    7918             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    7919             :       // (intrinsic_wo_chain:v2i32 609:iPTR, DPR:v2i32:$Vn, DPR:v2i32:$Vm)  =>  (VABDsv2i32:v2i32 DPR:v2i32:$Vn, DPR:v2i32:$Vm)
    7920             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv2i32,
    7921             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7922             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7923             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7924             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7925             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7926             :       GIR_EraseFromParent, /*InsnID*/0,
    7927             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7928             :       GIR_Done,
    7929             :     // Label 258: @18302
    7930             :     GIM_Try, /*On fail goto*//*Label 259*/ 18366,
    7931             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7932             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7933             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7934             :       // MIs[0] Vd
    7935             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    7936             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    7937             :       // MIs[0] Operand 1
    7938             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
    7939             :       // MIs[0] Vn
    7940             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    7941             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    7942             :       // MIs[0] Vm
    7943             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    7944             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    7945             :       // (intrinsic_wo_chain:v8i16 609:iPTR, QPR:v8i16:$Vn, QPR:v8i16:$Vm)  =>  (VABDsv8i16:v8i16 QPR:v8i16:$Vn, QPR:v8i16:$Vm)
    7946             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv8i16,
    7947             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7948             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7949             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7950             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7951             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7952             :       GIR_EraseFromParent, /*InsnID*/0,
    7953             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7954             :       GIR_Done,
    7955             :     // Label 259: @18366
    7956             :     GIM_Try, /*On fail goto*//*Label 260*/ 18430,
    7957             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7958             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7959             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7960             :       // MIs[0] Vd
    7961             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    7962             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    7963             :       // MIs[0] Operand 1
    7964             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
    7965             :       // MIs[0] Vn
    7966             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    7967             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    7968             :       // MIs[0] Vm
    7969             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    7970             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    7971             :       // (intrinsic_wo_chain:v4i32 609:iPTR, QPR:v4i32:$Vn, QPR:v4i32:$Vm)  =>  (VABDsv4i32:v4i32 QPR:v4i32:$Vn, QPR:v4i32:$Vm)
    7972             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv4i32,
    7973             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    7974             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    7975             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    7976             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    7977             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    7978             :       GIR_EraseFromParent, /*InsnID*/0,
    7979             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    7980             :       GIR_Done,
    7981             :     // Label 260: @18430
    7982             :     GIM_Try, /*On fail goto*//*Label 261*/ 18494,
    7983             :       GIM_CheckFeatures, GIFBS_HasNEON,
    7984             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    7985             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    7986             :       // MIs[0] Vd
    7987             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    7988             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    7989             :       // MIs[0] Operand 1
    7990             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
    7991             :       // MIs[0] Vn
    7992             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    7993             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    7994             :       // MIs[0] Vm
    7995             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
    7996             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    7997             :       // (intrinsic_wo_chain:v8i8 609:iPTR, DPR:v8i8:$Vn, DPR:v8i8:$Vm)  =>  (VABDsv8i8:v8i8 DPR:v8i8:$Vn, DPR:v8i8:$Vm)
    7998             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv8i8,
    7999             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8000             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    8001             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8002             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8003             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8004             :       GIR_EraseFromParent, /*InsnID*/0,
    8005             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8006             :       GIR_Done,
    8007             :     // Label 261: @18494
    8008             :     GIM_Try, /*On fail goto*//*Label 262*/ 18558,
    8009             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8010             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8011             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8012             :       // MIs[0] Vd
    8013             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    8014             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    8015             :       // MIs[0] Operand 1
    8016             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
    8017             :       // MIs[0] Vn
    8018             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    8019             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    8020             :       // MIs[0] Vm
    8021             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
    8022             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    8023             :       // (intrinsic_wo_chain:v16i8 609:iPTR, QPR:v16i8:$Vn, QPR:v16i8:$Vm)  =>  (VABDsv16i8:v16i8 QPR:v16i8:$Vn, QPR:v16i8:$Vm)
    8024             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv16i8,
    8025             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8026             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    8027             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8028             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8029             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8030             :       GIR_EraseFromParent, /*InsnID*/0,
    8031             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8032             :       GIR_Done,
    8033             :     // Label 262: @18558
    8034             :     GIM_Try, /*On fail goto*//*Label 263*/ 18622,
    8035             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8036             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8037             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8038             :       // MIs[0] Vd
    8039             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    8040             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    8041             :       // MIs[0] Operand 1
    8042             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu,
    8043             :       // MIs[0] Vn
    8044             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    8045             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    8046             :       // MIs[0] Vm
    8047             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    8048             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    8049             :       // (intrinsic_wo_chain:v4i16 610:iPTR, DPR:v4i16:$Vn, DPR:v4i16:$Vm)  =>  (VABDuv4i16:v4i16 DPR:v4i16:$Vn, DPR:v4i16:$Vm)
    8050             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv4i16,
    8051             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8052             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    8053             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8054             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8055             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8056             :       GIR_EraseFromParent, /*InsnID*/0,
    8057             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8058             :       GIR_Done,
    8059             :     // Label 263: @18622
    8060             :     GIM_Try, /*On fail goto*//*Label 264*/ 18686,
    8061             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8062             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8063             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8064             :       // MIs[0] Vd
    8065             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    8066             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    8067             :       // MIs[0] Operand 1
    8068             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu,
    8069             :       // MIs[0] Vn
    8070             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    8071             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    8072             :       // MIs[0] Vm
    8073             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    8074             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    8075             :       // (intrinsic_wo_chain:v2i32 610:iPTR, DPR:v2i32:$Vn, DPR:v2i32:$Vm)  =>  (VABDuv2i32:v2i32 DPR:v2i32:$Vn, DPR:v2i32:$Vm)
    8076             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv2i32,
    8077             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8078             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    8079             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8080             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8081             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8082             :       GIR_EraseFromParent, /*InsnID*/0,
    8083             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8084             :       GIR_Done,
    8085             :     // Label 264: @18686
    8086             :     GIM_Try, /*On fail goto*//*Label 265*/ 18750,
    8087             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8088             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8089             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8090             :       // MIs[0] Vd
    8091             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    8092             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    8093             :       // MIs[0] Operand 1
    8094             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu,
    8095             :       // MIs[0] Vn
    8096             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    8097             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    8098             :       // MIs[0] Vm
    8099             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    8100             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    8101             :       // (intrinsic_wo_chain:v8i16 610:iPTR, QPR:v8i16:$Vn, QPR:v8i16:$Vm)  =>  (VABDuv8i16:v8i16 QPR:v8i16:$Vn, QPR:v8i16:$Vm)
    8102             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv8i16,
    8103             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8104             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    8105             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8106             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8107             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8108             :       GIR_EraseFromParent, /*InsnID*/0,
    8109             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8110             :       GIR_Done,
    8111             :     // Label 265: @18750
    8112             :     GIM_Try, /*On fail goto*//*Label 266*/ 18814,
    8113             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8114             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8115             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8116             :       // MIs[0] Vd
    8117             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    8118             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    8119             :       // MIs[0] Operand 1
    8120             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu,
    8121             :       // MIs[0] Vn
    8122             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    8123             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    8124             :       // MIs[0] Vm
    8125             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    8126             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    8127             :       // (intrinsic_wo_chain:v4i32 610:iPTR, QPR:v4i32:$Vn, QPR:v4i32:$Vm)  =>  (VABDuv4i32:v4i32 QPR:v4i32:$Vn, QPR:v4i32:$Vm)
    8128             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv4i32,
    8129             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8130             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    8131             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8132             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8133             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8134             :       GIR_EraseFromParent, /*InsnID*/0,
    8135             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8136             :       GIR_Done,
    8137             :     // Label 266: @18814
    8138             :     GIM_Try, /*On fail goto*//*Label 267*/ 18878,
    8139             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8140             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8141             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8142             :       // MIs[0] Vd
    8143             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    8144             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    8145             :       // MIs[0] Operand 1
    8146             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu,
    8147             :       // MIs[0] Vn
    8148             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    8149             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    8150             :       // MIs[0] Vm
    8151             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
    8152             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    8153             :       // (intrinsic_wo_chain:v8i8 610:iPTR, DPR:v8i8:$Vn, DPR:v8i8:$Vm)  =>  (VABDuv8i8:v8i8 DPR:v8i8:$Vn, DPR:v8i8:$Vm)
    8154             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv8i8,
    8155             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8156             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    8157             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8158             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8159             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8160             :       GIR_EraseFromParent, /*InsnID*/0,
    8161             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8162             :       GIR_Done,
    8163             :     // Label 267: @18878
    8164             :     GIM_Try, /*On fail goto*//*Label 268*/ 18942,
    8165             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8166             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8167             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8168             :       // MIs[0] Vd
    8169             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    8170             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    8171             :       // MIs[0] Operand 1
    8172             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu,
    8173             :       // MIs[0] Vn
    8174             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    8175             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    8176             :       // MIs[0] Vm
    8177             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
    8178             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    8179             :       // (intrinsic_wo_chain:v16i8 610:iPTR, QPR:v16i8:$Vn, QPR:v16i8:$Vm)  =>  (VABDuv16i8:v16i8 QPR:v16i8:$Vn, QPR:v16i8:$Vm)
    8180             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv16i8,
    8181             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8182             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    8183             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8184             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8185             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8186             :       GIR_EraseFromParent, /*InsnID*/0,
    8187             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8188             :       GIR_Done,
    8189             :     // Label 268: @18942
    8190             :     GIM_Try, /*On fail goto*//*Label 269*/ 19006,
    8191             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8192             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8193             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8194             :       // MIs[0] Vd
    8195             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    8196             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    8197             :       // MIs[0] Operand 1
    8198             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
    8199             :       // MIs[0] Vn
    8200             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    8201             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    8202             :       // MIs[0] Vm
    8203             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    8204             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    8205             :       // (intrinsic_wo_chain:v2f32 609:iPTR, DPR:v2f32:$Vn, DPR:v2f32:$Vm)  =>  (VABDfd:v2f32 DPR:v2f32:$Vn, DPR:v2f32:$Vm)
    8206             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDfd,
    8207             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8208             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    8209             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8210             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8211             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8212             :       GIR_EraseFromParent, /*InsnID*/0,
    8213             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8214             :       GIR_Done,
    8215             :     // Label 269: @19006
    8216             :     GIM_Try, /*On fail goto*//*Label 270*/ 19070,
    8217             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8218             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8219             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8220             :       // MIs[0] Vd
    8221             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    8222             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    8223             :       // MIs[0] Operand 1
    8224             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
    8225             :       // MIs[0] Vn
    8226             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    8227             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    8228             :       // MIs[0] Vm
    8229             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    8230             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    8231             :       // (intrinsic_wo_chain:v4f32 609:iPTR, QPR:v4f32:$Vn, QPR:v4f32:$Vm)  =>  (VABDfq:v4f32 QPR:v4f32:$Vn, QPR:v4f32:$Vm)
    8232             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDfq,
    8233             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8234             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    8235             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8236             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8237             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8238             :       GIR_EraseFromParent, /*InsnID*/0,
    8239             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8240             :       GIR_Done,
    8241             :     // Label 270: @19070
    8242             :     GIM_Try, /*On fail goto*//*Label 271*/ 19134,
    8243             :       GIM_CheckFeatures, GIFBS_HasNEON_HasFullFP16,
    8244             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8245             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8246             :       // MIs[0] Vd
    8247             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    8248             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    8249             :       // MIs[0] Operand 1
    8250             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
    8251             :       // MIs[0] Vn
    8252             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    8253             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    8254             :       // MIs[0] Vm
    8255             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    8256             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    8257             :       // (intrinsic_wo_chain:v4f16 609:iPTR, DPR:v4f16:$Vn, DPR:v4f16:$Vm)  =>  (VABDhd:v4f16 DPR:v4f16:$Vn, DPR:v4f16:$Vm)
    8258             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDhd,
    8259             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8260             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    8261             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8262             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8263             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8264             :       GIR_EraseFromParent, /*InsnID*/0,
    8265             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8266             :       GIR_Done,
    8267             :     // Label 271: @19134
    8268             :     GIM_Try, /*On fail goto*//*Label 272*/ 19198,
    8269             :       GIM_CheckFeatures, GIFBS_HasNEON_HasFullFP16,
    8270             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8271             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8272             :       // MIs[0] Vd
    8273             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    8274             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    8275             :       // MIs[0] Operand 1
    8276             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
    8277             :       // MIs[0] Vn
    8278             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    8279             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    8280             :       // MIs[0] Vm
    8281             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    8282             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    8283             :       // (intrinsic_wo_chain:v8f16 609:iPTR, QPR:v8f16:$Vn, QPR:v8f16:$Vm)  =>  (VABDhq:v8f16 QPR:v8f16:$Vn, QPR:v8f16:$Vm)
    8284             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDhq,
    8285             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8286             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    8287             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8288             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8289             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8290             :       GIR_EraseFromParent, /*InsnID*/0,
    8291             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8292             :       GIR_Done,
    8293             :     // Label 272: @19198
    8294             :     GIM_Try, /*On fail goto*//*Label 273*/ 19262,
    8295             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8296             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8297             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8298             :       // MIs[0] Vd
    8299             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    8300             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    8301             :       // MIs[0] Operand 1
    8302             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadd,
    8303             :       // MIs[0] Vn
    8304             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    8305             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    8306             :       // MIs[0] Vm
    8307             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
    8308             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    8309             :       // (intrinsic_wo_chain:v8i8 653:iPTR, DPR:v8i8:$Vn, DPR:v8i8:$Vm)  =>  (VPADDi8:v8i8 DPR:v8i8:$Vn, DPR:v8i8:$Vm)
    8310             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDi8,
    8311             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8312             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    8313             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8314             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8315             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8316             :       GIR_EraseFromParent, /*InsnID*/0,
    8317             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8318             :       GIR_Done,
    8319             :     // Label 273: @19262
    8320             :     GIM_Try, /*On fail goto*//*Label 274*/ 19326,
    8321             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8322             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8323             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8324             :       // MIs[0] Vd
    8325             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    8326             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    8327             :       // MIs[0] Operand 1
    8328             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadd,
    8329             :       // MIs[0] Vn
    8330             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    8331             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    8332             :       // MIs[0] Vm
    8333             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    8334             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    8335             :       // (intrinsic_wo_chain:v4i16 653:iPTR, DPR:v4i16:$Vn, DPR:v4i16:$Vm)  =>  (VPADDi16:v4i16 DPR:v4i16:$Vn, DPR:v4i16:$Vm)
    8336             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDi16,
    8337             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8338             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    8339             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8340             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8341             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8342             :       GIR_EraseFromParent, /*InsnID*/0,
    8343             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8344             :       GIR_Done,
    8345             :     // Label 274: @19326
    8346             :     GIM_Try, /*On fail goto*//*Label 275*/ 19390,
    8347             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8348             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8349             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8350             :       // MIs[0] Vd
    8351             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    8352             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    8353             :       // MIs[0] Operand 1
    8354             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadd,
    8355             :       // MIs[0] Vn
    8356             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    8357             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    8358             :       // MIs[0] Vm
    8359             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    8360             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    8361             :       // (intrinsic_wo_chain:v2i32 653:iPTR, DPR:v2i32:$Vn, DPR:v2i32:$Vm)  =>  (VPADDi32:v2i32 DPR:v2i32:$Vn, DPR:v2i32:$Vm)
    8362             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDi32,
    8363             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8364             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    8365             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8366             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8367             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8368             :       GIR_EraseFromParent, /*InsnID*/0,
    8369             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8370             :       GIR_Done,
    8371             :     // Label 275: @19390
    8372             :     GIM_Try, /*On fail goto*//*Label 276*/ 19454,
    8373             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8374             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8375             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8376             :       // MIs[0] Vd
    8377             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    8378             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    8379             :       // MIs[0] Operand 1
    8380             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadd,
    8381             :       // MIs[0] Vn
    8382             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    8383             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    8384             :       // MIs[0] Vm
    8385             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    8386             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    8387             :       // (intrinsic_wo_chain:v2f32 653:iPTR, DPR:v2f32:$Vn, DPR:v2f32:$Vm)  =>  (VPADDf:v2f32 DPR:v2f32:$Vn, DPR:v2f32:$Vm)
    8388             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDf,
    8389             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8390             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    8391             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8392             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8393             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8394             :       GIR_EraseFromParent, /*InsnID*/0,
    8395             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8396             :       GIR_Done,
    8397             :     // Label 276: @19454
    8398             :     GIM_Try, /*On fail goto*//*Label 277*/ 19518,
    8399             :       GIM_CheckFeatures, GIFBS_HasNEON_HasFullFP16,
    8400             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8401             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8402             :       // MIs[0] Vd
    8403             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    8404             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    8405             :       // MIs[0] Operand 1
    8406             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadd,
    8407             :       // MIs[0] Vn
    8408             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    8409             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    8410             :       // MIs[0] Vm
    8411             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    8412             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    8413             :       // (intrinsic_wo_chain:v4f16 653:iPTR, DPR:v4f16:$Vn, DPR:v4f16:$Vm)  =>  (VPADDh:v4f16 DPR:v4f16:$Vn, DPR:v4f16:$Vm)
    8414             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDh,
    8415             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8416             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    8417             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8418             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8419             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8420             :       GIR_EraseFromParent, /*InsnID*/0,
    8421             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8422             :       GIR_Done,
    8423             :     // Label 277: @19518
    8424             :     GIM_Try, /*On fail goto*//*Label 278*/ 19582,
    8425             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8426             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8427             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8428             :       // MIs[0] Vd
    8429             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    8430             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    8431             :       // MIs[0] Operand 1
    8432             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals,
    8433             :       // MIs[0] src1
    8434             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    8435             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    8436             :       // MIs[0] Vm
    8437             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
    8438             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    8439             :       // (intrinsic_wo_chain:v4i16 651:iPTR, DPR:v4i16:$src1, DPR:v8i8:$Vm)  =>  (VPADALsv8i8:v4i16 DPR:v4i16:$src1, DPR:v8i8:$Vm)
    8440             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv8i8,
    8441             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8442             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    8443             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8444             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8445             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8446             :       GIR_EraseFromParent, /*InsnID*/0,
    8447             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8448             :       GIR_Done,
    8449             :     // Label 278: @19582
    8450             :     GIM_Try, /*On fail goto*//*Label 279*/ 19646,
    8451             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8452             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8453             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8454             :       // MIs[0] Vd
    8455             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    8456             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    8457             :       // MIs[0] Operand 1
    8458             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals,
    8459             :       // MIs[0] src1
    8460             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    8461             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    8462             :       // MIs[0] Vm
    8463             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    8464             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    8465             :       // (intrinsic_wo_chain:v2i32 651:iPTR, DPR:v2i32:$src1, DPR:v4i16:$Vm)  =>  (VPADALsv4i16:v2i32 DPR:v2i32:$src1, DPR:v4i16:$Vm)
    8466             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv4i16,
    8467             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8468             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    8469             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8470             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8471             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8472             :       GIR_EraseFromParent, /*InsnID*/0,
    8473             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8474             :       GIR_Done,
    8475             :     // Label 279: @19646
    8476             :     GIM_Try, /*On fail goto*//*Label 280*/ 19710,
    8477             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8478             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8479             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8480             :       // MIs[0] Vd
    8481             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    8482             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    8483             :       // MIs[0] Operand 1
    8484             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals,
    8485             :       // MIs[0] src1
    8486             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    8487             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    8488             :       // MIs[0] Vm
    8489             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    8490             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    8491             :       // (intrinsic_wo_chain:v1i64 651:iPTR, DPR:v1i64:$src1, DPR:v2i32:$Vm)  =>  (VPADALsv2i32:v1i64 DPR:v1i64:$src1, DPR:v2i32:$Vm)
    8492             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv2i32,
    8493             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8494             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    8495             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8496             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8497             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8498             :       GIR_EraseFromParent, /*InsnID*/0,
    8499             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8500             :       GIR_Done,
    8501             :     // Label 280: @19710
    8502             :     GIM_Try, /*On fail goto*//*Label 281*/ 19774,
    8503             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8504             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8505             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8506             :       // MIs[0] Vd
    8507             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    8508             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    8509             :       // MIs[0] Operand 1
    8510             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals,
    8511             :       // MIs[0] src1
    8512             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    8513             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    8514             :       // MIs[0] Vm
    8515             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
    8516             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    8517             :       // (intrinsic_wo_chain:v8i16 651:iPTR, QPR:v8i16:$src1, QPR:v16i8:$Vm)  =>  (VPADALsv16i8:v8i16 QPR:v8i16:$src1, QPR:v16i8:$Vm)
    8518             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv16i8,
    8519             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8520             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    8521             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8522             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8523             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8524             :       GIR_EraseFromParent, /*InsnID*/0,
    8525             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8526             :       GIR_Done,
    8527             :     // Label 281: @19774
    8528             :     GIM_Try, /*On fail goto*//*Label 282*/ 19838,
    8529             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8530             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8531             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8532             :       // MIs[0] Vd
    8533             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    8534             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    8535             :       // MIs[0] Operand 1
    8536             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals,
    8537             :       // MIs[0] src1
    8538             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    8539             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    8540             :       // MIs[0] Vm
    8541             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    8542             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    8543             :       // (intrinsic_wo_chain:v4i32 651:iPTR, QPR:v4i32:$src1, QPR:v8i16:$Vm)  =>  (VPADALsv8i16:v4i32 QPR:v4i32:$src1, QPR:v8i16:$Vm)
    8544             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv8i16,
    8545             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8546             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    8547             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8548             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8549             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8550             :       GIR_EraseFromParent, /*InsnID*/0,
    8551             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8552             :       GIR_Done,
    8553             :     // Label 282: @19838
    8554             :     GIM_Try, /*On fail goto*//*Label 283*/ 19902,
    8555             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8556             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8557             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8558             :       // MIs[0] Vd
    8559             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    8560             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    8561             :       // MIs[0] Operand 1
    8562             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals,
    8563             :       // MIs[0] src1
    8564             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    8565             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    8566             :       // MIs[0] Vm
    8567             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    8568             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    8569             :       // (intrinsic_wo_chain:v2i64 651:iPTR, QPR:v2i64:$src1, QPR:v4i32:$Vm)  =>  (VPADALsv4i32:v2i64 QPR:v2i64:$src1, QPR:v4i32:$Vm)
    8570             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv4i32,
    8571             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8572             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    8573             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8574             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8575             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8576             :       GIR_EraseFromParent, /*InsnID*/0,
    8577             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8578             :       GIR_Done,
    8579             :     // Label 283: @19902
    8580             :     GIM_Try, /*On fail goto*//*Label 284*/ 19966,
    8581             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8582             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8583             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8584             :       // MIs[0] Vd
    8585             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    8586             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    8587             :       // MIs[0] Operand 1
    8588             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu,
    8589             :       // MIs[0] src1
    8590             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    8591             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    8592             :       // MIs[0] Vm
    8593             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
    8594             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    8595             :       // (intrinsic_wo_chain:v4i16 652:iPTR, DPR:v4i16:$src1, DPR:v8i8:$Vm)  =>  (VPADALuv8i8:v4i16 DPR:v4i16:$src1, DPR:v8i8:$Vm)
    8596             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv8i8,
    8597             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8598             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    8599             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8600             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8601             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8602             :       GIR_EraseFromParent, /*InsnID*/0,
    8603             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8604             :       GIR_Done,
    8605             :     // Label 284: @19966
    8606             :     GIM_Try, /*On fail goto*//*Label 285*/ 20030,
    8607             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8608             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8609             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8610             :       // MIs[0] Vd
    8611             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    8612             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    8613             :       // MIs[0] Operand 1
    8614             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu,
    8615             :       // MIs[0] src1
    8616             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    8617             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    8618             :       // MIs[0] Vm
    8619             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    8620             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    8621             :       // (intrinsic_wo_chain:v2i32 652:iPTR, DPR:v2i32:$src1, DPR:v4i16:$Vm)  =>  (VPADALuv4i16:v2i32 DPR:v2i32:$src1, DPR:v4i16:$Vm)
    8622             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv4i16,
    8623             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8624             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    8625             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8626             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8627             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8628             :       GIR_EraseFromParent, /*InsnID*/0,
    8629             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8630             :       GIR_Done,
    8631             :     // Label 285: @20030
    8632             :     GIM_Try, /*On fail goto*//*Label 286*/ 20094,
    8633             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8634             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8635             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8636             :       // MIs[0] Vd
    8637             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    8638             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    8639             :       // MIs[0] Operand 1
    8640             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu,
    8641             :       // MIs[0] src1
    8642             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    8643             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    8644             :       // MIs[0] Vm
    8645             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    8646             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    8647             :       // (intrinsic_wo_chain:v1i64 652:iPTR, DPR:v1i64:$src1, DPR:v2i32:$Vm)  =>  (VPADALuv2i32:v1i64 DPR:v1i64:$src1, DPR:v2i32:$Vm)
    8648             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv2i32,
    8649             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8650             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    8651             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8652             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8653             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8654             :       GIR_EraseFromParent, /*InsnID*/0,
    8655             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8656             :       GIR_Done,
    8657             :     // Label 286: @20094
    8658             :     GIM_Try, /*On fail goto*//*Label 287*/ 20158,
    8659             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8660             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8661             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8662             :       // MIs[0] Vd
    8663             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    8664             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    8665             :       // MIs[0] Operand 1
    8666             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu,
    8667             :       // MIs[0] src1
    8668             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    8669             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    8670             :       // MIs[0] Vm
    8671             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
    8672             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    8673             :       // (intrinsic_wo_chain:v8i16 652:iPTR, QPR:v8i16:$src1, QPR:v16i8:$Vm)  =>  (VPADALuv16i8:v8i16 QPR:v8i16:$src1, QPR:v16i8:$Vm)
    8674             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv16i8,
    8675             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8676             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    8677             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8678             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8679             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8680             :       GIR_EraseFromParent, /*InsnID*/0,
    8681             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8682             :       GIR_Done,
    8683             :     // Label 287: @20158
    8684             :     GIM_Try, /*On fail goto*//*Label 288*/ 20222,
    8685             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8686             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8687             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8688             :       // MIs[0] Vd
    8689             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    8690             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    8691             :       // MIs[0] Operand 1
    8692             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu,
    8693             :       // MIs[0] src1
    8694             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    8695             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    8696             :       // MIs[0] Vm
    8697             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    8698             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    8699             :       // (intrinsic_wo_chain:v4i32 652:iPTR, QPR:v4i32:$src1, QPR:v8i16:$Vm)  =>  (VPADALuv8i16:v4i32 QPR:v4i32:$src1, QPR:v8i16:$Vm)
    8700             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv8i16,
    8701             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8702             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    8703             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8704             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8705             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8706             :       GIR_EraseFromParent, /*InsnID*/0,
    8707             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8708             :       GIR_Done,
    8709             :     // Label 288: @20222
    8710             :     GIM_Try, /*On fail goto*//*Label 289*/ 20286,
    8711             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8712             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8713             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8714             :       // MIs[0] Vd
    8715             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    8716             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    8717             :       // MIs[0] Operand 1
    8718             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu,
    8719             :       // MIs[0] src1
    8720             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    8721             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    8722             :       // MIs[0] Vm
    8723             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    8724             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    8725             :       // (intrinsic_wo_chain:v2i64 652:iPTR, QPR:v2i64:$src1, QPR:v4i32:$Vm)  =>  (VPADALuv4i32:v2i64 QPR:v2i64:$src1, QPR:v4i32:$Vm)
    8726             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv4i32,
    8727             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8728             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    8729             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8730             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8731             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8732             :       GIR_EraseFromParent, /*InsnID*/0,
    8733             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8734             :       GIR_Done,
    8735             :     // Label 289: @20286
    8736             :     GIM_Try, /*On fail goto*//*Label 290*/ 20350,
    8737             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8738             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8739             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8740             :       // MIs[0] Vd
    8741             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    8742             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    8743             :       // MIs[0] Operand 1
    8744             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxs,
    8745             :       // MIs[0] Vn
    8746             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    8747             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    8748             :       // MIs[0] Vm
    8749             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
    8750             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    8751             :       // (intrinsic_wo_chain:v8i8 656:iPTR, DPR:v8i8:$Vn, DPR:v8i8:$Vm)  =>  (VPMAXs8:v8i8 DPR:v8i8:$Vn, DPR:v8i8:$Vm)
    8752             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXs8,
    8753             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8754             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    8755             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8756             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8757             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8758             :       GIR_EraseFromParent, /*InsnID*/0,
    8759             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8760             :       GIR_Done,
    8761             :     // Label 290: @20350
    8762             :     GIM_Try, /*On fail goto*//*Label 291*/ 20414,
    8763             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8764             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8765             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8766             :       // MIs[0] Vd
    8767             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    8768             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    8769             :       // MIs[0] Operand 1
    8770             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxs,
    8771             :       // MIs[0] Vn
    8772             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    8773             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    8774             :       // MIs[0] Vm
    8775             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    8776             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    8777             :       // (intrinsic_wo_chain:v4i16 656:iPTR, DPR:v4i16:$Vn, DPR:v4i16:$Vm)  =>  (VPMAXs16:v4i16 DPR:v4i16:$Vn, DPR:v4i16:$Vm)
    8778             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXs16,
    8779             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8780             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    8781             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8782             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8783             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8784             :       GIR_EraseFromParent, /*InsnID*/0,
    8785             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8786             :       GIR_Done,
    8787             :     // Label 291: @20414
    8788             :     GIM_Try, /*On fail goto*//*Label 292*/ 20478,
    8789             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8790             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8791             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8792             :       // MIs[0] Vd
    8793             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    8794             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    8795             :       // MIs[0] Operand 1
    8796             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxs,
    8797             :       // MIs[0] Vn
    8798             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    8799             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    8800             :       // MIs[0] Vm
    8801             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    8802             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    8803             :       // (intrinsic_wo_chain:v2i32 656:iPTR, DPR:v2i32:$Vn, DPR:v2i32:$Vm)  =>  (VPMAXs32:v2i32 DPR:v2i32:$Vn, DPR:v2i32:$Vm)
    8804             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXs32,
    8805             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8806             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    8807             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8808             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8809             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8810             :       GIR_EraseFromParent, /*InsnID*/0,
    8811             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8812             :       GIR_Done,
    8813             :     // Label 292: @20478
    8814             :     GIM_Try, /*On fail goto*//*Label 293*/ 20542,
    8815             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8816             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8817             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8818             :       // MIs[0] Vd
    8819             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    8820             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    8821             :       // MIs[0] Operand 1
    8822             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxu,
    8823             :       // MIs[0] Vn
    8824             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    8825             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    8826             :       // MIs[0] Vm
    8827             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
    8828             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    8829             :       // (intrinsic_wo_chain:v8i8 657:iPTR, DPR:v8i8:$Vn, DPR:v8i8:$Vm)  =>  (VPMAXu8:v8i8 DPR:v8i8:$Vn, DPR:v8i8:$Vm)
    8830             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXu8,
    8831             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8832             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    8833             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8834             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8835             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8836             :       GIR_EraseFromParent, /*InsnID*/0,
    8837             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8838             :       GIR_Done,
    8839             :     // Label 293: @20542
    8840             :     GIM_Try, /*On fail goto*//*Label 294*/ 20606,
    8841             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8842             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8843             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8844             :       // MIs[0] Vd
    8845             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    8846             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    8847             :       // MIs[0] Operand 1
    8848             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxu,
    8849             :       // MIs[0] Vn
    8850             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    8851             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    8852             :       // MIs[0] Vm
    8853             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    8854             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    8855             :       // (intrinsic_wo_chain:v4i16 657:iPTR, DPR:v4i16:$Vn, DPR:v4i16:$Vm)  =>  (VPMAXu16:v4i16 DPR:v4i16:$Vn, DPR:v4i16:$Vm)
    8856             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXu16,
    8857             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8858             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    8859             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8860             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8861             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8862             :       GIR_EraseFromParent, /*InsnID*/0,
    8863             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8864             :       GIR_Done,
    8865             :     // Label 294: @20606
    8866             :     GIM_Try, /*On fail goto*//*Label 295*/ 20670,
    8867             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8868             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8869             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8870             :       // MIs[0] Vd
    8871             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    8872             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    8873             :       // MIs[0] Operand 1
    8874             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxu,
    8875             :       // MIs[0] Vn
    8876             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    8877             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    8878             :       // MIs[0] Vm
    8879             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    8880             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    8881             :       // (intrinsic_wo_chain:v2i32 657:iPTR, DPR:v2i32:$Vn, DPR:v2i32:$Vm)  =>  (VPMAXu32:v2i32 DPR:v2i32:$Vn, DPR:v2i32:$Vm)
    8882             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXu32,
    8883             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8884             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    8885             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8886             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8887             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8888             :       GIR_EraseFromParent, /*InsnID*/0,
    8889             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8890             :       GIR_Done,
    8891             :     // Label 295: @20670
    8892             :     GIM_Try, /*On fail goto*//*Label 296*/ 20734,
    8893             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8894             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8895             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8896             :       // MIs[0] Vd
    8897             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    8898             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    8899             :       // MIs[0] Operand 1
    8900             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxs,
    8901             :       // MIs[0] Vn
    8902             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    8903             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    8904             :       // MIs[0] Vm
    8905             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    8906             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    8907             :       // (intrinsic_wo_chain:v2f32 656:iPTR, DPR:v2f32:$Vn, DPR:v2f32:$Vm)  =>  (VPMAXf:v2f32 DPR:v2f32:$Vn, DPR:v2f32:$Vm)
    8908             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXf,
    8909             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8910             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    8911             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8912             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8913             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8914             :       GIR_EraseFromParent, /*InsnID*/0,
    8915             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8916             :       GIR_Done,
    8917             :     // Label 296: @20734
    8918             :     GIM_Try, /*On fail goto*//*Label 297*/ 20798,
    8919             :       GIM_CheckFeatures, GIFBS_HasNEON_HasFullFP16,
    8920             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8921             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8922             :       // MIs[0] Vd
    8923             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    8924             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    8925             :       // MIs[0] Operand 1
    8926             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxs,
    8927             :       // MIs[0] Vn
    8928             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    8929             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    8930             :       // MIs[0] Vm
    8931             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    8932             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    8933             :       // (intrinsic_wo_chain:v4f16 656:iPTR, DPR:v4f16:$Vn, DPR:v4f16:$Vm)  =>  (VPMAXh:v4f16 DPR:v4f16:$Vn, DPR:v4f16:$Vm)
    8934             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXh,
    8935             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8936             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    8937             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8938             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8939             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8940             :       GIR_EraseFromParent, /*InsnID*/0,
    8941             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8942             :       GIR_Done,
    8943             :     // Label 297: @20798
    8944             :     GIM_Try, /*On fail goto*//*Label 298*/ 20862,
    8945             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8946             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8947             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8948             :       // MIs[0] Vd
    8949             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    8950             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    8951             :       // MIs[0] Operand 1
    8952             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmins,
    8953             :       // MIs[0] Vn
    8954             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    8955             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    8956             :       // MIs[0] Vm
    8957             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
    8958             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    8959             :       // (intrinsic_wo_chain:v8i8 658:iPTR, DPR:v8i8:$Vn, DPR:v8i8:$Vm)  =>  (VPMINs8:v8i8 DPR:v8i8:$Vn, DPR:v8i8:$Vm)
    8960             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINs8,
    8961             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8962             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    8963             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8964             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8965             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8966             :       GIR_EraseFromParent, /*InsnID*/0,
    8967             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8968             :       GIR_Done,
    8969             :     // Label 298: @20862
    8970             :     GIM_Try, /*On fail goto*//*Label 299*/ 20926,
    8971             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8972             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8973             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    8974             :       // MIs[0] Vd
    8975             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    8976             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    8977             :       // MIs[0] Operand 1
    8978             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmins,
    8979             :       // MIs[0] Vn
    8980             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    8981             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    8982             :       // MIs[0] Vm
    8983             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    8984             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    8985             :       // (intrinsic_wo_chain:v4i16 658:iPTR, DPR:v4i16:$Vn, DPR:v4i16:$Vm)  =>  (VPMINs16:v4i16 DPR:v4i16:$Vn, DPR:v4i16:$Vm)
    8986             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINs16,
    8987             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    8988             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    8989             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    8990             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    8991             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    8992             :       GIR_EraseFromParent, /*InsnID*/0,
    8993             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    8994             :       GIR_Done,
    8995             :     // Label 299: @20926
    8996             :     GIM_Try, /*On fail goto*//*Label 300*/ 20990,
    8997             :       GIM_CheckFeatures, GIFBS_HasNEON,
    8998             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    8999             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9000             :       // MIs[0] Vd
    9001             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    9002             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    9003             :       // MIs[0] Operand 1
    9004             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmins,
    9005             :       // MIs[0] Vn
    9006             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    9007             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    9008             :       // MIs[0] Vm
    9009             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    9010             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    9011             :       // (intrinsic_wo_chain:v2i32 658:iPTR, DPR:v2i32:$Vn, DPR:v2i32:$Vm)  =>  (VPMINs32:v2i32 DPR:v2i32:$Vn, DPR:v2i32:$Vm)
    9012             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINs32,
    9013             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9014             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    9015             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    9016             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9017             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9018             :       GIR_EraseFromParent, /*InsnID*/0,
    9019             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9020             :       GIR_Done,
    9021             :     // Label 300: @20990
    9022             :     GIM_Try, /*On fail goto*//*Label 301*/ 21054,
    9023             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9024             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9025             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9026             :       // MIs[0] Vd
    9027             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    9028             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    9029             :       // MIs[0] Operand 1
    9030             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpminu,
    9031             :       // MIs[0] Vn
    9032             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    9033             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    9034             :       // MIs[0] Vm
    9035             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
    9036             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    9037             :       // (intrinsic_wo_chain:v8i8 659:iPTR, DPR:v8i8:$Vn, DPR:v8i8:$Vm)  =>  (VPMINu8:v8i8 DPR:v8i8:$Vn, DPR:v8i8:$Vm)
    9038             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINu8,
    9039             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9040             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    9041             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    9042             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9043             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9044             :       GIR_EraseFromParent, /*InsnID*/0,
    9045             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9046             :       GIR_Done,
    9047             :     // Label 301: @21054
    9048             :     GIM_Try, /*On fail goto*//*Label 302*/ 21118,
    9049             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9050             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9051             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9052             :       // MIs[0] Vd
    9053             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    9054             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    9055             :       // MIs[0] Operand 1
    9056             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpminu,
    9057             :       // MIs[0] Vn
    9058             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    9059             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    9060             :       // MIs[0] Vm
    9061             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    9062             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    9063             :       // (intrinsic_wo_chain:v4i16 659:iPTR, DPR:v4i16:$Vn, DPR:v4i16:$Vm)  =>  (VPMINu16:v4i16 DPR:v4i16:$Vn, DPR:v4i16:$Vm)
    9064             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINu16,
    9065             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9066             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    9067             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    9068             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9069             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9070             :       GIR_EraseFromParent, /*InsnID*/0,
    9071             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9072             :       GIR_Done,
    9073             :     // Label 302: @21118
    9074             :     GIM_Try, /*On fail goto*//*Label 303*/ 21182,
    9075             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9076             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9077             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9078             :       // MIs[0] Vd
    9079             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    9080             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    9081             :       // MIs[0] Operand 1
    9082             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpminu,
    9083             :       // MIs[0] Vn
    9084             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    9085             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    9086             :       // MIs[0] Vm
    9087             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    9088             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    9089             :       // (intrinsic_wo_chain:v2i32 659:iPTR, DPR:v2i32:$Vn, DPR:v2i32:$Vm)  =>  (VPMINu32:v2i32 DPR:v2i32:$Vn, DPR:v2i32:$Vm)
    9090             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINu32,
    9091             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9092             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    9093             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    9094             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9095             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9096             :       GIR_EraseFromParent, /*InsnID*/0,
    9097             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9098             :       GIR_Done,
    9099             :     // Label 303: @21182
    9100             :     GIM_Try, /*On fail goto*//*Label 304*/ 21246,
    9101             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9102             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9103             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9104             :       // MIs[0] Vd
    9105             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    9106             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    9107             :       // MIs[0] Operand 1
    9108             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmins,
    9109             :       // MIs[0] Vn
    9110             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    9111             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    9112             :       // MIs[0] Vm
    9113             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    9114             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    9115             :       // (intrinsic_wo_chain:v2f32 658:iPTR, DPR:v2f32:$Vn, DPR:v2f32:$Vm)  =>  (VPMINf:v2f32 DPR:v2f32:$Vn, DPR:v2f32:$Vm)
    9116             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINf,
    9117             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9118             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    9119             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    9120             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9121             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9122             :       GIR_EraseFromParent, /*InsnID*/0,
    9123             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9124             :       GIR_Done,
    9125             :     // Label 304: @21246
    9126             :     GIM_Try, /*On fail goto*//*Label 305*/ 21310,
    9127             :       GIM_CheckFeatures, GIFBS_HasNEON_HasFullFP16,
    9128             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9129             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9130             :       // MIs[0] Vd
    9131             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    9132             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    9133             :       // MIs[0] Operand 1
    9134             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmins,
    9135             :       // MIs[0] Vn
    9136             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    9137             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    9138             :       // MIs[0] Vm
    9139             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    9140             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    9141             :       // (intrinsic_wo_chain:v4f16 658:iPTR, DPR:v4f16:$Vn, DPR:v4f16:$Vm)  =>  (VPMINh:v4f16 DPR:v4f16:$Vn, DPR:v4f16:$Vm)
    9142             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINh,
    9143             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9144             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    9145             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    9146             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9147             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9148             :       GIR_EraseFromParent, /*InsnID*/0,
    9149             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9150             :       GIR_Done,
    9151             :     // Label 305: @21310
    9152             :     GIM_Try, /*On fail goto*//*Label 306*/ 21374,
    9153             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9154             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9155             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9156             :       // MIs[0] Vd
    9157             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    9158             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    9159             :       // MIs[0] Operand 1
    9160             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecps,
    9161             :       // MIs[0] Vn
    9162             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    9163             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    9164             :       // MIs[0] Vm
    9165             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    9166             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    9167             :       // (intrinsic_wo_chain:v2f32 685:iPTR, DPR:v2f32:$Vn, DPR:v2f32:$Vm)  =>  (VRECPSfd:v2f32 DPR:v2f32:$Vn, DPR:v2f32:$Vm)
    9168             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPSfd,
    9169             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9170             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    9171             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    9172             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9173             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9174             :       GIR_EraseFromParent, /*InsnID*/0,
    9175             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9176             :       GIR_Done,
    9177             :     // Label 306: @21374
    9178             :     GIM_Try, /*On fail goto*//*Label 307*/ 21438,
    9179             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9180             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9181             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9182             :       // MIs[0] Vd
    9183             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    9184             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    9185             :       // MIs[0] Operand 1
    9186             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecps,
    9187             :       // MIs[0] Vn
    9188             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    9189             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    9190             :       // MIs[0] Vm
    9191             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    9192             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    9193             :       // (intrinsic_wo_chain:v4f32 685:iPTR, QPR:v4f32:$Vn, QPR:v4f32:$Vm)  =>  (VRECPSfq:v4f32 QPR:v4f32:$Vn, QPR:v4f32:$Vm)
    9194             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPSfq,
    9195             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9196             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    9197             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    9198             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9199             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9200             :       GIR_EraseFromParent, /*InsnID*/0,
    9201             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9202             :       GIR_Done,
    9203             :     // Label 307: @21438
    9204             :     GIM_Try, /*On fail goto*//*Label 308*/ 21502,
    9205             :       GIM_CheckFeatures, GIFBS_HasNEON_HasFullFP16,
    9206             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9207             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9208             :       // MIs[0] Vd
    9209             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    9210             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    9211             :       // MIs[0] Operand 1
    9212             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecps,
    9213             :       // MIs[0] Vn
    9214             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    9215             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    9216             :       // MIs[0] Vm
    9217             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    9218             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    9219             :       // (intrinsic_wo_chain:v4f16 685:iPTR, DPR:v4f16:$Vn, DPR:v4f16:$Vm)  =>  (VRECPShd:v4f16 DPR:v4f16:$Vn, DPR:v4f16:$Vm)
    9220             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPShd,
    9221             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9222             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    9223             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    9224             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9225             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9226             :       GIR_EraseFromParent, /*InsnID*/0,
    9227             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9228             :       GIR_Done,
    9229             :     // Label 308: @21502
    9230             :     GIM_Try, /*On fail goto*//*Label 309*/ 21566,
    9231             :       GIM_CheckFeatures, GIFBS_HasNEON_HasFullFP16,
    9232             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9233             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9234             :       // MIs[0] Vd
    9235             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    9236             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    9237             :       // MIs[0] Operand 1
    9238             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecps,
    9239             :       // MIs[0] Vn
    9240             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    9241             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    9242             :       // MIs[0] Vm
    9243             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    9244             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    9245             :       // (intrinsic_wo_chain:v8f16 685:iPTR, QPR:v8f16:$Vn, QPR:v8f16:$Vm)  =>  (VRECPShq:v8f16 QPR:v8f16:$Vn, QPR:v8f16:$Vm)
    9246             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPShq,
    9247             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9248             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    9249             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    9250             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9251             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9252             :       GIR_EraseFromParent, /*InsnID*/0,
    9253             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9254             :       GIR_Done,
    9255             :     // Label 309: @21566
    9256             :     GIM_Try, /*On fail goto*//*Label 310*/ 21630,
    9257             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9258             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9259             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9260             :       // MIs[0] Vd
    9261             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    9262             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    9263             :       // MIs[0] Operand 1
    9264             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrts,
    9265             :       // MIs[0] Vn
    9266             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    9267             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    9268             :       // MIs[0] Vm
    9269             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    9270             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    9271             :       // (intrinsic_wo_chain:v2f32 698:iPTR, DPR:v2f32:$Vn, DPR:v2f32:$Vm)  =>  (VRSQRTSfd:v2f32 DPR:v2f32:$Vn, DPR:v2f32:$Vm)
    9272             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTSfd,
    9273             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9274             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    9275             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    9276             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9277             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9278             :       GIR_EraseFromParent, /*InsnID*/0,
    9279             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9280             :       GIR_Done,
    9281             :     // Label 310: @21630
    9282             :     GIM_Try, /*On fail goto*//*Label 311*/ 21694,
    9283             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9284             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9285             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9286             :       // MIs[0] Vd
    9287             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    9288             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    9289             :       // MIs[0] Operand 1
    9290             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrts,
    9291             :       // MIs[0] Vn
    9292             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    9293             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    9294             :       // MIs[0] Vm
    9295             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    9296             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    9297             :       // (intrinsic_wo_chain:v4f32 698:iPTR, QPR:v4f32:$Vn, QPR:v4f32:$Vm)  =>  (VRSQRTSfq:v4f32 QPR:v4f32:$Vn, QPR:v4f32:$Vm)
    9298             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTSfq,
    9299             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9300             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    9301             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    9302             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9303             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9304             :       GIR_EraseFromParent, /*InsnID*/0,
    9305             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9306             :       GIR_Done,
    9307             :     // Label 311: @21694
    9308             :     GIM_Try, /*On fail goto*//*Label 312*/ 21758,
    9309             :       GIM_CheckFeatures, GIFBS_HasNEON_HasFullFP16,
    9310             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9311             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9312             :       // MIs[0] Vd
    9313             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    9314             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    9315             :       // MIs[0] Operand 1
    9316             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrts,
    9317             :       // MIs[0] Vn
    9318             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    9319             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    9320             :       // MIs[0] Vm
    9321             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    9322             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    9323             :       // (intrinsic_wo_chain:v4f16 698:iPTR, DPR:v4f16:$Vn, DPR:v4f16:$Vm)  =>  (VRSQRTShd:v4f16 DPR:v4f16:$Vn, DPR:v4f16:$Vm)
    9324             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTShd,
    9325             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9326             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    9327             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    9328             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9329             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9330             :       GIR_EraseFromParent, /*InsnID*/0,
    9331             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9332             :       GIR_Done,
    9333             :     // Label 312: @21758
    9334             :     GIM_Try, /*On fail goto*//*Label 313*/ 21822,
    9335             :       GIM_CheckFeatures, GIFBS_HasNEON_HasFullFP16,
    9336             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9337             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9338             :       // MIs[0] Vd
    9339             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    9340             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    9341             :       // MIs[0] Operand 1
    9342             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrts,
    9343             :       // MIs[0] Vn
    9344             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    9345             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    9346             :       // MIs[0] Vm
    9347             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    9348             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    9349             :       // (intrinsic_wo_chain:v8f16 698:iPTR, QPR:v8f16:$Vn, QPR:v8f16:$Vm)  =>  (VRSQRTShq:v8f16 QPR:v8f16:$Vn, QPR:v8f16:$Vm)
    9350             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTShq,
    9351             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9352             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
    9353             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
    9354             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9355             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9356             :       GIR_EraseFromParent, /*InsnID*/0,
    9357             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9358             :       GIR_Done,
    9359             :     // Label 313: @21822
    9360             :     GIM_Try, /*On fail goto*//*Label 314*/ 21886,
    9361             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9362             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9363             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9364             :       // MIs[0] Vd
    9365             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    9366             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    9367             :       // MIs[0] Operand 1
    9368             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
    9369             :       // MIs[0] Vm
    9370             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    9371             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    9372             :       // MIs[0] Vn
    9373             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    9374             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    9375             :       // (intrinsic_wo_chain:v4i16 701:iPTR, DPR:v4i16:$Vm, DPR:v4i16:$Vn)  =>  (VSHLsv4i16:v4i16 DPR:v4i16:$Vm, DPR:v4i16:$Vn)
    9376             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv4i16,
    9377             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9378             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    9379             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    9380             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9381             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9382             :       GIR_EraseFromParent, /*InsnID*/0,
    9383             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9384             :       GIR_Done,
    9385             :     // Label 314: @21886
    9386             :     GIM_Try, /*On fail goto*//*Label 315*/ 21950,
    9387             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9388             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9389             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9390             :       // MIs[0] Vd
    9391             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    9392             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    9393             :       // MIs[0] Operand 1
    9394             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
    9395             :       // MIs[0] Vm
    9396             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    9397             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    9398             :       // MIs[0] Vn
    9399             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    9400             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    9401             :       // (intrinsic_wo_chain:v2i32 701:iPTR, DPR:v2i32:$Vm, DPR:v2i32:$Vn)  =>  (VSHLsv2i32:v2i32 DPR:v2i32:$Vm, DPR:v2i32:$Vn)
    9402             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv2i32,
    9403             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9404             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    9405             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    9406             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9407             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9408             :       GIR_EraseFromParent, /*InsnID*/0,
    9409             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9410             :       GIR_Done,
    9411             :     // Label 315: @21950
    9412             :     GIM_Try, /*On fail goto*//*Label 316*/ 22014,
    9413             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9414             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9415             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9416             :       // MIs[0] Vd
    9417             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    9418             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    9419             :       // MIs[0] Operand 1
    9420             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
    9421             :       // MIs[0] Vm
    9422             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    9423             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    9424             :       // MIs[0] Vn
    9425             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    9426             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    9427             :       // (intrinsic_wo_chain:v8i16 701:iPTR, QPR:v8i16:$Vm, QPR:v8i16:$Vn)  =>  (VSHLsv8i16:v8i16 QPR:v8i16:$Vm, QPR:v8i16:$Vn)
    9428             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv8i16,
    9429             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9430             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    9431             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    9432             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9433             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9434             :       GIR_EraseFromParent, /*InsnID*/0,
    9435             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9436             :       GIR_Done,
    9437             :     // Label 316: @22014
    9438             :     GIM_Try, /*On fail goto*//*Label 317*/ 22078,
    9439             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9440             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9441             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9442             :       // MIs[0] Vd
    9443             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    9444             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    9445             :       // MIs[0] Operand 1
    9446             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
    9447             :       // MIs[0] Vm
    9448             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    9449             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    9450             :       // MIs[0] Vn
    9451             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    9452             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    9453             :       // (intrinsic_wo_chain:v4i32 701:iPTR, QPR:v4i32:$Vm, QPR:v4i32:$Vn)  =>  (VSHLsv4i32:v4i32 QPR:v4i32:$Vm, QPR:v4i32:$Vn)
    9454             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv4i32,
    9455             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9456             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    9457             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    9458             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9459             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9460             :       GIR_EraseFromParent, /*InsnID*/0,
    9461             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9462             :       GIR_Done,
    9463             :     // Label 317: @22078
    9464             :     GIM_Try, /*On fail goto*//*Label 318*/ 22142,
    9465             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9466             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9467             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9468             :       // MIs[0] Vd
    9469             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    9470             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    9471             :       // MIs[0] Operand 1
    9472             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
    9473             :       // MIs[0] Vm
    9474             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    9475             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    9476             :       // MIs[0] Vn
    9477             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
    9478             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    9479             :       // (intrinsic_wo_chain:v8i8 701:iPTR, DPR:v8i8:$Vm, DPR:v8i8:$Vn)  =>  (VSHLsv8i8:v8i8 DPR:v8i8:$Vm, DPR:v8i8:$Vn)
    9480             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv8i8,
    9481             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9482             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    9483             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    9484             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9485             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9486             :       GIR_EraseFromParent, /*InsnID*/0,
    9487             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9488             :       GIR_Done,
    9489             :     // Label 318: @22142
    9490             :     GIM_Try, /*On fail goto*//*Label 319*/ 22206,
    9491             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9492             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9493             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9494             :       // MIs[0] Vd
    9495             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    9496             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    9497             :       // MIs[0] Operand 1
    9498             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
    9499             :       // MIs[0] Vm
    9500             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    9501             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    9502             :       // MIs[0] Vn
    9503             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
    9504             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    9505             :       // (intrinsic_wo_chain:v16i8 701:iPTR, QPR:v16i8:$Vm, QPR:v16i8:$Vn)  =>  (VSHLsv16i8:v16i8 QPR:v16i8:$Vm, QPR:v16i8:$Vn)
    9506             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv16i8,
    9507             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9508             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    9509             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    9510             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9511             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9512             :       GIR_EraseFromParent, /*InsnID*/0,
    9513             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9514             :       GIR_Done,
    9515             :     // Label 319: @22206
    9516             :     GIM_Try, /*On fail goto*//*Label 320*/ 22270,
    9517             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9518             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9519             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9520             :       // MIs[0] Vd
    9521             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    9522             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    9523             :       // MIs[0] Operand 1
    9524             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
    9525             :       // MIs[0] Vm
    9526             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    9527             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    9528             :       // MIs[0] Vn
    9529             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    9530             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    9531             :       // (intrinsic_wo_chain:v1i64 701:iPTR, DPR:v1i64:$Vm, DPR:v1i64:$Vn)  =>  (VSHLsv1i64:v1i64 DPR:v1i64:$Vm, DPR:v1i64:$Vn)
    9532             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv1i64,
    9533             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9534             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    9535             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    9536             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9537             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9538             :       GIR_EraseFromParent, /*InsnID*/0,
    9539             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9540             :       GIR_Done,
    9541             :     // Label 320: @22270
    9542             :     GIM_Try, /*On fail goto*//*Label 321*/ 22334,
    9543             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9544             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9545             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9546             :       // MIs[0] Vd
    9547             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    9548             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    9549             :       // MIs[0] Operand 1
    9550             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
    9551             :       // MIs[0] Vm
    9552             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    9553             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    9554             :       // MIs[0] Vn
    9555             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
    9556             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    9557             :       // (intrinsic_wo_chain:v2i64 701:iPTR, QPR:v2i64:$Vm, QPR:v2i64:$Vn)  =>  (VSHLsv2i64:v2i64 QPR:v2i64:$Vm, QPR:v2i64:$Vn)
    9558             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv2i64,
    9559             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9560             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    9561             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    9562             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9563             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9564             :       GIR_EraseFromParent, /*InsnID*/0,
    9565             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9566             :       GIR_Done,
    9567             :     // Label 321: @22334
    9568             :     GIM_Try, /*On fail goto*//*Label 322*/ 22398,
    9569             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9570             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9571             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9572             :       // MIs[0] Vd
    9573             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    9574             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    9575             :       // MIs[0] Operand 1
    9576             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
    9577             :       // MIs[0] Vm
    9578             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    9579             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    9580             :       // MIs[0] Vn
    9581             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    9582             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    9583             :       // (intrinsic_wo_chain:v4i16 702:iPTR, DPR:v4i16:$Vm, DPR:v4i16:$Vn)  =>  (VSHLuv4i16:v4i16 DPR:v4i16:$Vm, DPR:v4i16:$Vn)
    9584             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv4i16,
    9585             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9586             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    9587             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    9588             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9589             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9590             :       GIR_EraseFromParent, /*InsnID*/0,
    9591             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9592             :       GIR_Done,
    9593             :     // Label 322: @22398
    9594             :     GIM_Try, /*On fail goto*//*Label 323*/ 22462,
    9595             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9596             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9597             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9598             :       // MIs[0] Vd
    9599             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    9600             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    9601             :       // MIs[0] Operand 1
    9602             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
    9603             :       // MIs[0] Vm
    9604             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    9605             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    9606             :       // MIs[0] Vn
    9607             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    9608             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    9609             :       // (intrinsic_wo_chain:v2i32 702:iPTR, DPR:v2i32:$Vm, DPR:v2i32:$Vn)  =>  (VSHLuv2i32:v2i32 DPR:v2i32:$Vm, DPR:v2i32:$Vn)
    9610             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv2i32,
    9611             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9612             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    9613             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    9614             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9615             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9616             :       GIR_EraseFromParent, /*InsnID*/0,
    9617             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9618             :       GIR_Done,
    9619             :     // Label 323: @22462
    9620             :     GIM_Try, /*On fail goto*//*Label 324*/ 22526,
    9621             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9622             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9623             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9624             :       // MIs[0] Vd
    9625             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    9626             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    9627             :       // MIs[0] Operand 1
    9628             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
    9629             :       // MIs[0] Vm
    9630             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    9631             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    9632             :       // MIs[0] Vn
    9633             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    9634             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    9635             :       // (intrinsic_wo_chain:v8i16 702:iPTR, QPR:v8i16:$Vm, QPR:v8i16:$Vn)  =>  (VSHLuv8i16:v8i16 QPR:v8i16:$Vm, QPR:v8i16:$Vn)
    9636             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv8i16,
    9637             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9638             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    9639             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    9640             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9641             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9642             :       GIR_EraseFromParent, /*InsnID*/0,
    9643             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9644             :       GIR_Done,
    9645             :     // Label 324: @22526
    9646             :     GIM_Try, /*On fail goto*//*Label 325*/ 22590,
    9647             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9648             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9649             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9650             :       // MIs[0] Vd
    9651             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    9652             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    9653             :       // MIs[0] Operand 1
    9654             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
    9655             :       // MIs[0] Vm
    9656             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    9657             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    9658             :       // MIs[0] Vn
    9659             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    9660             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    9661             :       // (intrinsic_wo_chain:v4i32 702:iPTR, QPR:v4i32:$Vm, QPR:v4i32:$Vn)  =>  (VSHLuv4i32:v4i32 QPR:v4i32:$Vm, QPR:v4i32:$Vn)
    9662             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv4i32,
    9663             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9664             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    9665             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    9666             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9667             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9668             :       GIR_EraseFromParent, /*InsnID*/0,
    9669             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9670             :       GIR_Done,
    9671             :     // Label 325: @22590
    9672             :     GIM_Try, /*On fail goto*//*Label 326*/ 22654,
    9673             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9674             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9675             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9676             :       // MIs[0] Vd
    9677             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    9678             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    9679             :       // MIs[0] Operand 1
    9680             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
    9681             :       // MIs[0] Vm
    9682             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    9683             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    9684             :       // MIs[0] Vn
    9685             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
    9686             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    9687             :       // (intrinsic_wo_chain:v8i8 702:iPTR, DPR:v8i8:$Vm, DPR:v8i8:$Vn)  =>  (VSHLuv8i8:v8i8 DPR:v8i8:$Vm, DPR:v8i8:$Vn)
    9688             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv8i8,
    9689             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9690             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    9691             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    9692             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9693             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9694             :       GIR_EraseFromParent, /*InsnID*/0,
    9695             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9696             :       GIR_Done,
    9697             :     // Label 326: @22654
    9698             :     GIM_Try, /*On fail goto*//*Label 327*/ 22718,
    9699             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9700             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9701             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9702             :       // MIs[0] Vd
    9703             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    9704             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    9705             :       // MIs[0] Operand 1
    9706             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
    9707             :       // MIs[0] Vm
    9708             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    9709             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    9710             :       // MIs[0] Vn
    9711             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
    9712             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    9713             :       // (intrinsic_wo_chain:v16i8 702:iPTR, QPR:v16i8:$Vm, QPR:v16i8:$Vn)  =>  (VSHLuv16i8:v16i8 QPR:v16i8:$Vm, QPR:v16i8:$Vn)
    9714             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv16i8,
    9715             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9716             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    9717             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    9718             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9719             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9720             :       GIR_EraseFromParent, /*InsnID*/0,
    9721             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9722             :       GIR_Done,
    9723             :     // Label 327: @22718
    9724             :     GIM_Try, /*On fail goto*//*Label 328*/ 22782,
    9725             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9726             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9727             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9728             :       // MIs[0] Vd
    9729             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    9730             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    9731             :       // MIs[0] Operand 1
    9732             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
    9733             :       // MIs[0] Vm
    9734             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    9735             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    9736             :       // MIs[0] Vn
    9737             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    9738             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    9739             :       // (intrinsic_wo_chain:v1i64 702:iPTR, DPR:v1i64:$Vm, DPR:v1i64:$Vn)  =>  (VSHLuv1i64:v1i64 DPR:v1i64:$Vm, DPR:v1i64:$Vn)
    9740             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv1i64,
    9741             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9742             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    9743             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    9744             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9745             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9746             :       GIR_EraseFromParent, /*InsnID*/0,
    9747             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9748             :       GIR_Done,
    9749             :     // Label 328: @22782
    9750             :     GIM_Try, /*On fail goto*//*Label 329*/ 22846,
    9751             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9752             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9753             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9754             :       // MIs[0] Vd
    9755             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    9756             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    9757             :       // MIs[0] Operand 1
    9758             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
    9759             :       // MIs[0] Vm
    9760             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    9761             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    9762             :       // MIs[0] Vn
    9763             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
    9764             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    9765             :       // (intrinsic_wo_chain:v2i64 702:iPTR, QPR:v2i64:$Vm, QPR:v2i64:$Vn)  =>  (VSHLuv2i64:v2i64 QPR:v2i64:$Vm, QPR:v2i64:$Vn)
    9766             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv2i64,
    9767             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9768             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    9769             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    9770             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9771             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9772             :       GIR_EraseFromParent, /*InsnID*/0,
    9773             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9774             :       GIR_Done,
    9775             :     // Label 329: @22846
    9776             :     GIM_Try, /*On fail goto*//*Label 330*/ 22910,
    9777             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9778             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9779             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9780             :       // MIs[0] Vd
    9781             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
    9782             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    9783             :       // MIs[0] Operand 1
    9784             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
    9785             :       // MIs[0] Vm
    9786             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
    9787             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    9788             :       // MIs[0] Vn
    9789             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
    9790             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    9791             :       // (intrinsic_wo_chain:v4i16 695:iPTR, DPR:v4i16:$Vm, DPR:v4i16:$Vn)  =>  (VRSHLsv4i16:v4i16 DPR:v4i16:$Vm, DPR:v4i16:$Vn)
    9792             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv4i16,
    9793             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9794             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    9795             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    9796             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9797             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9798             :       GIR_EraseFromParent, /*InsnID*/0,
    9799             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9800             :       GIR_Done,
    9801             :     // Label 330: @22910
    9802             :     GIM_Try, /*On fail goto*//*Label 331*/ 22974,
    9803             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9804             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9805             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9806             :       // MIs[0] Vd
    9807             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
    9808             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    9809             :       // MIs[0] Operand 1
    9810             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
    9811             :       // MIs[0] Vm
    9812             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
    9813             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    9814             :       // MIs[0] Vn
    9815             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
    9816             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    9817             :       // (intrinsic_wo_chain:v2i32 695:iPTR, DPR:v2i32:$Vm, DPR:v2i32:$Vn)  =>  (VRSHLsv2i32:v2i32 DPR:v2i32:$Vm, DPR:v2i32:$Vn)
    9818             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv2i32,
    9819             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9820             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    9821             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    9822             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9823             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9824             :       GIR_EraseFromParent, /*InsnID*/0,
    9825             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9826             :       GIR_Done,
    9827             :     // Label 331: @22974
    9828             :     GIM_Try, /*On fail goto*//*Label 332*/ 23038,
    9829             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9830             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9831             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9832             :       // MIs[0] Vd
    9833             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
    9834             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    9835             :       // MIs[0] Operand 1
    9836             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
    9837             :       // MIs[0] Vm
    9838             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
    9839             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    9840             :       // MIs[0] Vn
    9841             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
    9842             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    9843             :       // (intrinsic_wo_chain:v8i16 695:iPTR, QPR:v8i16:$Vm, QPR:v8i16:$Vn)  =>  (VRSHLsv8i16:v8i16 QPR:v8i16:$Vm, QPR:v8i16:$Vn)
    9844             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv8i16,
    9845             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9846             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    9847             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    9848             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9849             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9850             :       GIR_EraseFromParent, /*InsnID*/0,
    9851             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9852             :       GIR_Done,
    9853             :     // Label 332: @23038
    9854             :     GIM_Try, /*On fail goto*//*Label 333*/ 23102,
    9855             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9856             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9857             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9858             :       // MIs[0] Vd
    9859             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    9860             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    9861             :       // MIs[0] Operand 1
    9862             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
    9863             :       // MIs[0] Vm
    9864             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
    9865             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    9866             :       // MIs[0] Vn
    9867             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
    9868             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    9869             :       // (intrinsic_wo_chain:v4i32 695:iPTR, QPR:v4i32:$Vm, QPR:v4i32:$Vn)  =>  (VRSHLsv4i32:v4i32 QPR:v4i32:$Vm, QPR:v4i32:$Vn)
    9870             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv4i32,
    9871             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9872             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    9873             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    9874             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9875             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9876             :       GIR_EraseFromParent, /*InsnID*/0,
    9877             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9878             :       GIR_Done,
    9879             :     // Label 333: @23102
    9880             :     GIM_Try, /*On fail goto*//*Label 334*/ 23166,
    9881             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9882             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9883             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9884             :       // MIs[0] Vd
    9885             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
    9886             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    9887             :       // MIs[0] Operand 1
    9888             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
    9889             :       // MIs[0] Vm
    9890             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
    9891             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    9892             :       // MIs[0] Vn
    9893             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
    9894             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    9895             :       // (intrinsic_wo_chain:v8i8 695:iPTR, DPR:v8i8:$Vm, DPR:v8i8:$Vn)  =>  (VRSHLsv8i8:v8i8 DPR:v8i8:$Vm, DPR:v8i8:$Vn)
    9896             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv8i8,
    9897             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9898             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    9899             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    9900             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9901             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9902             :       GIR_EraseFromParent, /*InsnID*/0,
    9903             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9904             :       GIR_Done,
    9905             :     // Label 334: @23166
    9906             :     GIM_Try, /*On fail goto*//*Label 335*/ 23230,
    9907             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9908             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9909             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9910             :       // MIs[0] Vd
    9911             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
    9912             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    9913             :       // MIs[0] Operand 1
    9914             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
    9915             :       // MIs[0] Vm
    9916             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
    9917             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    9918             :       // MIs[0] Vn
    9919             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
    9920             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    9921             :       // (intrinsic_wo_chain:v16i8 695:iPTR, QPR:v16i8:$Vm, QPR:v16i8:$Vn)  =>  (VRSHLsv16i8:v16i8 QPR:v16i8:$Vm, QPR:v16i8:$Vn)
    9922             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv16i8,
    9923             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9924             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    9925             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    9926             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9927             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9928             :       GIR_EraseFromParent, /*InsnID*/0,
    9929             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9930             :       GIR_Done,
    9931             :     // Label 335: @23230
    9932             :     GIM_Try, /*On fail goto*//*Label 336*/ 23294,
    9933             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9934             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9935             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9936             :       // MIs[0] Vd
    9937             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    9938             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
    9939             :       // MIs[0] Operand 1
    9940             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
    9941             :       // MIs[0] Vm
    9942             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    9943             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
    9944             :       // MIs[0] Vn
    9945             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    9946             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
    9947             :       // (intrinsic_wo_chain:v1i64 695:iPTR, DPR:v1i64:$Vm, DPR:v1i64:$Vn)  =>  (VRSHLsv1i64:v1i64 DPR:v1i64:$Vm, DPR:v1i64:$Vn)
    9948             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv1i64,
    9949             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9950             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    9951             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    9952             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9953             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9954             :       GIR_EraseFromParent, /*InsnID*/0,
    9955             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    9956             :       GIR_Done,
    9957             :     // Label 336: @23294
    9958             :     GIM_Try, /*On fail goto*//*Label 337*/ 23358,
    9959             :       GIM_CheckFeatures, GIFBS_HasNEON,
    9960             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    9961             :       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
    9962             :       // MIs[0] Vd
    9963             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
    9964             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
    9965             :       // MIs[0] Operand 1
    9966             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
    9967             :       // MIs[0] Vm
    9968             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
    9969             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
    9970             :       // MIs[0] Vn
    9971             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
    9972             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
    9973             :       // (intrinsic_wo_chain:v2i64 695:iPTR, QPR:v2i64:$Vm, QPR:v2i64:$Vn)  =>  (VRSHLsv2i64:v2i64 QPR:v2i64:$Vm, QPR:v2i64:$Vn)
    9974             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv2i64,
    9975             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
    9976             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
    9977             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
    9978             :       GIR_AddImm, /*InsnID*/0, /*Imm*/14,
    9979             :       GIR_AddRegister, /*InsnID*/0, ::zero_reg,
    9980             :       GIR_EraseFromParent, /*InsnID*/0,
    998