LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/ARM - ARMGenRegisterInfo.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 147 269 54.6 %
Date: 2017-09-14 15:23:50 Functions: 26 44 59.1 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Target Register Enum Values                                                *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : 
      10             : #ifdef GET_REGINFO_ENUM
      11             : #undef GET_REGINFO_ENUM
      12             : 
      13             : namespace llvm {
      14             : 
      15             : class MCRegisterClass;
      16             : extern const MCRegisterClass ARMMCRegisterClasses[];
      17             : 
      18             : namespace ARM {
      19             : enum {
      20             :   NoRegister,
      21             :   APSR = 1,
      22             :   APSR_NZCV = 2,
      23             :   CPSR = 3,
      24             :   FPEXC = 4,
      25             :   FPINST = 5,
      26             :   FPSCR = 6,
      27             :   FPSCR_NZCV = 7,
      28             :   FPSID = 8,
      29             :   ITSTATE = 9,
      30             :   LR = 10,
      31             :   PC = 11,
      32             :   SP = 12,
      33             :   SPSR = 13,
      34             :   D0 = 14,
      35             :   D1 = 15,
      36             :   D2 = 16,
      37             :   D3 = 17,
      38             :   D4 = 18,
      39             :   D5 = 19,
      40             :   D6 = 20,
      41             :   D7 = 21,
      42             :   D8 = 22,
      43             :   D9 = 23,
      44             :   D10 = 24,
      45             :   D11 = 25,
      46             :   D12 = 26,
      47             :   D13 = 27,
      48             :   D14 = 28,
      49             :   D15 = 29,
      50             :   D16 = 30,
      51             :   D17 = 31,
      52             :   D18 = 32,
      53             :   D19 = 33,
      54             :   D20 = 34,
      55             :   D21 = 35,
      56             :   D22 = 36,
      57             :   D23 = 37,
      58             :   D24 = 38,
      59             :   D25 = 39,
      60             :   D26 = 40,
      61             :   D27 = 41,
      62             :   D28 = 42,
      63             :   D29 = 43,
      64             :   D30 = 44,
      65             :   D31 = 45,
      66             :   FPINST2 = 46,
      67             :   MVFR0 = 47,
      68             :   MVFR1 = 48,
      69             :   MVFR2 = 49,
      70             :   Q0 = 50,
      71             :   Q1 = 51,
      72             :   Q2 = 52,
      73             :   Q3 = 53,
      74             :   Q4 = 54,
      75             :   Q5 = 55,
      76             :   Q6 = 56,
      77             :   Q7 = 57,
      78             :   Q8 = 58,
      79             :   Q9 = 59,
      80             :   Q10 = 60,
      81             :   Q11 = 61,
      82             :   Q12 = 62,
      83             :   Q13 = 63,
      84             :   Q14 = 64,
      85             :   Q15 = 65,
      86             :   R0 = 66,
      87             :   R1 = 67,
      88             :   R2 = 68,
      89             :   R3 = 69,
      90             :   R4 = 70,
      91             :   R5 = 71,
      92             :   R6 = 72,
      93             :   R7 = 73,
      94             :   R8 = 74,
      95             :   R9 = 75,
      96             :   R10 = 76,
      97             :   R11 = 77,
      98             :   R12 = 78,
      99             :   S0 = 79,
     100             :   S1 = 80,
     101             :   S2 = 81,
     102             :   S3 = 82,
     103             :   S4 = 83,
     104             :   S5 = 84,
     105             :   S6 = 85,
     106             :   S7 = 86,
     107             :   S8 = 87,
     108             :   S9 = 88,
     109             :   S10 = 89,
     110             :   S11 = 90,
     111             :   S12 = 91,
     112             :   S13 = 92,
     113             :   S14 = 93,
     114             :   S15 = 94,
     115             :   S16 = 95,
     116             :   S17 = 96,
     117             :   S18 = 97,
     118             :   S19 = 98,
     119             :   S20 = 99,
     120             :   S21 = 100,
     121             :   S22 = 101,
     122             :   S23 = 102,
     123             :   S24 = 103,
     124             :   S25 = 104,
     125             :   S26 = 105,
     126             :   S27 = 106,
     127             :   S28 = 107,
     128             :   S29 = 108,
     129             :   S30 = 109,
     130             :   S31 = 110,
     131             :   D0_D2 = 111,
     132             :   D1_D3 = 112,
     133             :   D2_D4 = 113,
     134             :   D3_D5 = 114,
     135             :   D4_D6 = 115,
     136             :   D5_D7 = 116,
     137             :   D6_D8 = 117,
     138             :   D7_D9 = 118,
     139             :   D8_D10 = 119,
     140             :   D9_D11 = 120,
     141             :   D10_D12 = 121,
     142             :   D11_D13 = 122,
     143             :   D12_D14 = 123,
     144             :   D13_D15 = 124,
     145             :   D14_D16 = 125,
     146             :   D15_D17 = 126,
     147             :   D16_D18 = 127,
     148             :   D17_D19 = 128,
     149             :   D18_D20 = 129,
     150             :   D19_D21 = 130,
     151             :   D20_D22 = 131,
     152             :   D21_D23 = 132,
     153             :   D22_D24 = 133,
     154             :   D23_D25 = 134,
     155             :   D24_D26 = 135,
     156             :   D25_D27 = 136,
     157             :   D26_D28 = 137,
     158             :   D27_D29 = 138,
     159             :   D28_D30 = 139,
     160             :   D29_D31 = 140,
     161             :   Q0_Q1 = 141,
     162             :   Q1_Q2 = 142,
     163             :   Q2_Q3 = 143,
     164             :   Q3_Q4 = 144,
     165             :   Q4_Q5 = 145,
     166             :   Q5_Q6 = 146,
     167             :   Q6_Q7 = 147,
     168             :   Q7_Q8 = 148,
     169             :   Q8_Q9 = 149,
     170             :   Q9_Q10 = 150,
     171             :   Q10_Q11 = 151,
     172             :   Q11_Q12 = 152,
     173             :   Q12_Q13 = 153,
     174             :   Q13_Q14 = 154,
     175             :   Q14_Q15 = 155,
     176             :   Q0_Q1_Q2_Q3 = 156,
     177             :   Q1_Q2_Q3_Q4 = 157,
     178             :   Q2_Q3_Q4_Q5 = 158,
     179             :   Q3_Q4_Q5_Q6 = 159,
     180             :   Q4_Q5_Q6_Q7 = 160,
     181             :   Q5_Q6_Q7_Q8 = 161,
     182             :   Q6_Q7_Q8_Q9 = 162,
     183             :   Q7_Q8_Q9_Q10 = 163,
     184             :   Q8_Q9_Q10_Q11 = 164,
     185             :   Q9_Q10_Q11_Q12 = 165,
     186             :   Q10_Q11_Q12_Q13 = 166,
     187             :   Q11_Q12_Q13_Q14 = 167,
     188             :   Q12_Q13_Q14_Q15 = 168,
     189             :   R12_SP = 169,
     190             :   R0_R1 = 170,
     191             :   R2_R3 = 171,
     192             :   R4_R5 = 172,
     193             :   R6_R7 = 173,
     194             :   R8_R9 = 174,
     195             :   R10_R11 = 175,
     196             :   D0_D1_D2 = 176,
     197             :   D1_D2_D3 = 177,
     198             :   D2_D3_D4 = 178,
     199             :   D3_D4_D5 = 179,
     200             :   D4_D5_D6 = 180,
     201             :   D5_D6_D7 = 181,
     202             :   D6_D7_D8 = 182,
     203             :   D7_D8_D9 = 183,
     204             :   D8_D9_D10 = 184,
     205             :   D9_D10_D11 = 185,
     206             :   D10_D11_D12 = 186,
     207             :   D11_D12_D13 = 187,
     208             :   D12_D13_D14 = 188,
     209             :   D13_D14_D15 = 189,
     210             :   D14_D15_D16 = 190,
     211             :   D15_D16_D17 = 191,
     212             :   D16_D17_D18 = 192,
     213             :   D17_D18_D19 = 193,
     214             :   D18_D19_D20 = 194,
     215             :   D19_D20_D21 = 195,
     216             :   D20_D21_D22 = 196,
     217             :   D21_D22_D23 = 197,
     218             :   D22_D23_D24 = 198,
     219             :   D23_D24_D25 = 199,
     220             :   D24_D25_D26 = 200,
     221             :   D25_D26_D27 = 201,
     222             :   D26_D27_D28 = 202,
     223             :   D27_D28_D29 = 203,
     224             :   D28_D29_D30 = 204,
     225             :   D29_D30_D31 = 205,
     226             :   D0_D2_D4 = 206,
     227             :   D1_D3_D5 = 207,
     228             :   D2_D4_D6 = 208,
     229             :   D3_D5_D7 = 209,
     230             :   D4_D6_D8 = 210,
     231             :   D5_D7_D9 = 211,
     232             :   D6_D8_D10 = 212,
     233             :   D7_D9_D11 = 213,
     234             :   D8_D10_D12 = 214,
     235             :   D9_D11_D13 = 215,
     236             :   D10_D12_D14 = 216,
     237             :   D11_D13_D15 = 217,
     238             :   D12_D14_D16 = 218,
     239             :   D13_D15_D17 = 219,
     240             :   D14_D16_D18 = 220,
     241             :   D15_D17_D19 = 221,
     242             :   D16_D18_D20 = 222,
     243             :   D17_D19_D21 = 223,
     244             :   D18_D20_D22 = 224,
     245             :   D19_D21_D23 = 225,
     246             :   D20_D22_D24 = 226,
     247             :   D21_D23_D25 = 227,
     248             :   D22_D24_D26 = 228,
     249             :   D23_D25_D27 = 229,
     250             :   D24_D26_D28 = 230,
     251             :   D25_D27_D29 = 231,
     252             :   D26_D28_D30 = 232,
     253             :   D27_D29_D31 = 233,
     254             :   D0_D2_D4_D6 = 234,
     255             :   D1_D3_D5_D7 = 235,
     256             :   D2_D4_D6_D8 = 236,
     257             :   D3_D5_D7_D9 = 237,
     258             :   D4_D6_D8_D10 = 238,
     259             :   D5_D7_D9_D11 = 239,
     260             :   D6_D8_D10_D12 = 240,
     261             :   D7_D9_D11_D13 = 241,
     262             :   D8_D10_D12_D14 = 242,
     263             :   D9_D11_D13_D15 = 243,
     264             :   D10_D12_D14_D16 = 244,
     265             :   D11_D13_D15_D17 = 245,
     266             :   D12_D14_D16_D18 = 246,
     267             :   D13_D15_D17_D19 = 247,
     268             :   D14_D16_D18_D20 = 248,
     269             :   D15_D17_D19_D21 = 249,
     270             :   D16_D18_D20_D22 = 250,
     271             :   D17_D19_D21_D23 = 251,
     272             :   D18_D20_D22_D24 = 252,
     273             :   D19_D21_D23_D25 = 253,
     274             :   D20_D22_D24_D26 = 254,
     275             :   D21_D23_D25_D27 = 255,
     276             :   D22_D24_D26_D28 = 256,
     277             :   D23_D25_D27_D29 = 257,
     278             :   D24_D26_D28_D30 = 258,
     279             :   D25_D27_D29_D31 = 259,
     280             :   D1_D2 = 260,
     281             :   D3_D4 = 261,
     282             :   D5_D6 = 262,
     283             :   D7_D8 = 263,
     284             :   D9_D10 = 264,
     285             :   D11_D12 = 265,
     286             :   D13_D14 = 266,
     287             :   D15_D16 = 267,
     288             :   D17_D18 = 268,
     289             :   D19_D20 = 269,
     290             :   D21_D22 = 270,
     291             :   D23_D24 = 271,
     292             :   D25_D26 = 272,
     293             :   D27_D28 = 273,
     294             :   D29_D30 = 274,
     295             :   D1_D2_D3_D4 = 275,
     296             :   D3_D4_D5_D6 = 276,
     297             :   D5_D6_D7_D8 = 277,
     298             :   D7_D8_D9_D10 = 278,
     299             :   D9_D10_D11_D12 = 279,
     300             :   D11_D12_D13_D14 = 280,
     301             :   D13_D14_D15_D16 = 281,
     302             :   D15_D16_D17_D18 = 282,
     303             :   D17_D18_D19_D20 = 283,
     304             :   D19_D20_D21_D22 = 284,
     305             :   D21_D22_D23_D24 = 285,
     306             :   D23_D24_D25_D26 = 286,
     307             :   D25_D26_D27_D28 = 287,
     308             :   D27_D28_D29_D30 = 288,
     309             :   NUM_TARGET_REGS       // 289
     310             : };
     311             : } // end namespace ARM
     312             : 
     313             : // Register classes
     314             : 
     315             : namespace ARM {
     316             : enum {
     317             :   SPRRegClassID = 0,
     318             :   GPRRegClassID = 1,
     319             :   GPRwithAPSRRegClassID = 2,
     320             :   SPR_8RegClassID = 3,
     321             :   GPRnopcRegClassID = 4,
     322             :   rGPRRegClassID = 5,
     323             :   tGPRwithpcRegClassID = 6,
     324             :   hGPRRegClassID = 7,
     325             :   tGPRRegClassID = 8,
     326             :   GPRnopc_and_hGPRRegClassID = 9,
     327             :   hGPR_and_rGPRRegClassID = 10,
     328             :   tcGPRRegClassID = 11,
     329             :   tGPR_and_tcGPRRegClassID = 12,
     330             :   CCRRegClassID = 13,
     331             :   GPRspRegClassID = 14,
     332             :   hGPR_and_tGPRwithpcRegClassID = 15,
     333             :   hGPR_and_tcGPRRegClassID = 16,
     334             :   DPRRegClassID = 17,
     335             :   DPR_VFP2RegClassID = 18,
     336             :   DPR_8RegClassID = 19,
     337             :   GPRPairRegClassID = 20,
     338             :   GPRPair_with_gsub_1_in_rGPRRegClassID = 21,
     339             :   GPRPair_with_gsub_0_in_tGPRRegClassID = 22,
     340             :   GPRPair_with_gsub_0_in_hGPRRegClassID = 23,
     341             :   GPRPair_with_gsub_0_in_tcGPRRegClassID = 24,
     342             :   GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClassID = 25,
     343             :   GPRPair_with_gsub_1_in_tcGPRRegClassID = 26,
     344             :   GPRPair_with_gsub_1_in_GPRspRegClassID = 27,
     345             :   DPairSpcRegClassID = 28,
     346             :   DPairSpc_with_ssub_0RegClassID = 29,
     347             :   DPairSpc_with_ssub_4RegClassID = 30,
     348             :   DPairSpc_with_dsub_0_in_DPR_8RegClassID = 31,
     349             :   DPairSpc_with_dsub_2_in_DPR_8RegClassID = 32,
     350             :   DPairRegClassID = 33,
     351             :   DPair_with_ssub_0RegClassID = 34,
     352             :   QPRRegClassID = 35,
     353             :   DPair_with_ssub_2RegClassID = 36,
     354             :   DPair_with_dsub_0_in_DPR_8RegClassID = 37,
     355             :   QPR_VFP2RegClassID = 38,
     356             :   DPair_with_dsub_1_in_DPR_8RegClassID = 39,
     357             :   QPR_8RegClassID = 40,
     358             :   DTripleRegClassID = 41,
     359             :   DTripleSpcRegClassID = 42,
     360             :   DTripleSpc_with_ssub_0RegClassID = 43,
     361             :   DTriple_with_ssub_0RegClassID = 44,
     362             :   DTriple_with_qsub_0_in_QPRRegClassID = 45,
     363             :   DTriple_with_ssub_2RegClassID = 46,
     364             :   DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 47,
     365             :   DTripleSpc_with_ssub_4RegClassID = 48,
     366             :   DTriple_with_ssub_4RegClassID = 49,
     367             :   DTripleSpc_with_ssub_8RegClassID = 50,
     368             :   DTripleSpc_with_dsub_0_in_DPR_8RegClassID = 51,
     369             :   DTriple_with_dsub_0_in_DPR_8RegClassID = 52,
     370             :   DTriple_with_qsub_0_in_QPR_VFP2RegClassID = 53,
     371             :   DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 54,
     372             :   DTriple_with_dsub_1_in_DPR_8RegClassID = 55,
     373             :   DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID = 56,
     374             :   DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClassID = 57,
     375             :   DTripleSpc_with_dsub_2_in_DPR_8RegClassID = 58,
     376             :   DTriple_with_dsub_2_in_DPR_8RegClassID = 59,
     377             :   DTripleSpc_with_dsub_4_in_DPR_8RegClassID = 60,
     378             :   DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 61,
     379             :   DTriple_with_qsub_0_in_QPR_8RegClassID = 62,
     380             :   DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClassID = 63,
     381             :   DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 64,
     382             :   DQuadSpcRegClassID = 65,
     383             :   DQuadSpc_with_ssub_0RegClassID = 66,
     384             :   DQuadSpc_with_ssub_4RegClassID = 67,
     385             :   DQuadSpc_with_ssub_8RegClassID = 68,
     386             :   DQuadSpc_with_dsub_0_in_DPR_8RegClassID = 69,
     387             :   DQuadSpc_with_dsub_2_in_DPR_8RegClassID = 70,
     388             :   DQuadSpc_with_dsub_4_in_DPR_8RegClassID = 71,
     389             :   DQuadRegClassID = 72,
     390             :   DQuad_with_ssub_0RegClassID = 73,
     391             :   DQuad_with_ssub_2RegClassID = 74,
     392             :   QQPRRegClassID = 75,
     393             :   DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 76,
     394             :   DQuad_with_ssub_4RegClassID = 77,
     395             :   DQuad_with_ssub_6RegClassID = 78,
     396             :   DQuad_with_dsub_0_in_DPR_8RegClassID = 79,
     397             :   DQuad_with_qsub_0_in_QPR_VFP2RegClassID = 80,
     398             :   DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 81,
     399             :   DQuad_with_dsub_1_in_DPR_8RegClassID = 82,
     400             :   DQuad_with_qsub_1_in_QPR_VFP2RegClassID = 83,
     401             :   DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID = 84,
     402             :   DQuad_with_dsub_2_in_DPR_8RegClassID = 85,
     403             :   DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 86,
     404             :   DQuad_with_dsub_3_in_DPR_8RegClassID = 87,
     405             :   DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 88,
     406             :   DQuad_with_qsub_0_in_QPR_8RegClassID = 89,
     407             :   DQuad_with_qsub_1_in_QPR_8RegClassID = 90,
     408             :   DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 91,
     409             :   DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 92,
     410             :   QQQQPRRegClassID = 93,
     411             :   QQQQPR_with_ssub_0RegClassID = 94,
     412             :   QQQQPR_with_ssub_4RegClassID = 95,
     413             :   QQQQPR_with_ssub_8RegClassID = 96,
     414             :   QQQQPR_with_ssub_12RegClassID = 97,
     415             :   QQQQPR_with_dsub_0_in_DPR_8RegClassID = 98,
     416             :   QQQQPR_with_dsub_2_in_DPR_8RegClassID = 99,
     417             :   QQQQPR_with_dsub_4_in_DPR_8RegClassID = 100,
     418             :   QQQQPR_with_dsub_6_in_DPR_8RegClassID = 101,
     419             : 
     420             :   };
     421             : } // end namespace ARM
     422             : 
     423             : 
     424             : // Subregister indices
     425             : 
     426             : namespace ARM {
     427             : enum {
     428             :   NoSubRegister,
     429             :   dsub_0,       // 1
     430             :   dsub_1,       // 2
     431             :   dsub_2,       // 3
     432             :   dsub_3,       // 4
     433             :   dsub_4,       // 5
     434             :   dsub_5,       // 6
     435             :   dsub_6,       // 7
     436             :   dsub_7,       // 8
     437             :   gsub_0,       // 9
     438             :   gsub_1,       // 10
     439             :   qqsub_0,      // 11
     440             :   qqsub_1,      // 12
     441             :   qsub_0,       // 13
     442             :   qsub_1,       // 14
     443             :   qsub_2,       // 15
     444             :   qsub_3,       // 16
     445             :   ssub_0,       // 17
     446             :   ssub_1,       // 18
     447             :   ssub_2,       // 19
     448             :   ssub_3,       // 20
     449             :   ssub_4,       // 21
     450             :   ssub_5,       // 22
     451             :   ssub_6,       // 23
     452             :   ssub_7,       // 24
     453             :   ssub_8,       // 25
     454             :   ssub_9,       // 26
     455             :   ssub_10,      // 27
     456             :   ssub_11,      // 28
     457             :   ssub_12,      // 29
     458             :   ssub_13,      // 30
     459             :   dsub_7_then_ssub_0,   // 31
     460             :   dsub_7_then_ssub_1,   // 32
     461             :   ssub_0_ssub_1_ssub_4_ssub_5,  // 33
     462             :   ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5,    // 34
     463             :   ssub_2_ssub_3_ssub_6_ssub_7,  // 35
     464             :   ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7,    // 36
     465             :   ssub_2_ssub_3_ssub_4_ssub_5,  // 37
     466             :   ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9,    // 38
     467             :   ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13,    // 39
     468             :   ssub_2_ssub_3_ssub_6_ssub_7_dsub_5,   // 40
     469             :   ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7,    // 41
     470             :   ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9,      // 42
     471             :   ssub_4_ssub_5_ssub_8_ssub_9,  // 43
     472             :   ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9,    // 44
     473             :   ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13,  // 45
     474             :   ssub_6_ssub_7_dsub_5, // 46
     475             :   ssub_6_ssub_7_ssub_8_ssub_9_dsub_5,   // 47
     476             :   ssub_6_ssub_7_dsub_5_dsub_7,  // 48
     477             :   ssub_6_ssub_7_ssub_8_ssub_9,  // 49
     478             :   ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13,   // 50
     479             :   ssub_8_ssub_9_ssub_12_ssub_13,        // 51
     480             :   ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, // 52
     481             :   dsub_5_dsub_7,        // 53
     482             :   dsub_5_ssub_12_ssub_13_dsub_7,        // 54
     483             :   dsub_5_ssub_12_ssub_13,       // 55
     484             :   ssub_4_ssub_5_ssub_6_ssub_7_qsub_2,   // 56
     485             :   NUM_TARGET_SUBREGS
     486             : };
     487             : } // end namespace ARM
     488             : 
     489             : } // end namespace llvm
     490             : 
     491             : #endif // GET_REGINFO_ENUM
     492             : 
     493             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
     494             : |*                                                                            *|
     495             : |* MC Register Information                                                    *|
     496             : |*                                                                            *|
     497             : |* Automatically generated file, do not edit!                                 *|
     498             : |*                                                                            *|
     499             : \*===----------------------------------------------------------------------===*/
     500             : 
     501             : 
     502             : #ifdef GET_REGINFO_MC_DESC
     503             : #undef GET_REGINFO_MC_DESC
     504             : 
     505             : namespace llvm {
     506             : 
     507             : extern const MCPhysReg ARMRegDiffLists[] = {
     508             :   /* 0 */ 64924, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
     509             :   /* 17 */ 32, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
     510             :   /* 32 */ 36, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
     511             :   /* 45 */ 40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
     512             :   /* 56 */ 64450, 1, 1, 1, 1, 1, 1, 1, 0,
     513             :   /* 65 */ 64984, 1, 1, 1, 1, 1, 1, 1, 0,
     514             :   /* 74 */ 65252, 1, 1, 1, 1, 1, 1, 1, 0,
     515             :   /* 83 */ 38, 1, 1, 1, 1, 1, 1, 0,
     516             :   /* 91 */ 40, 1, 1, 1, 1, 1, 0,
     517             :   /* 98 */ 65196, 1, 1, 1, 1, 1, 0,
     518             :   /* 105 */ 40, 1, 1, 1, 1, 0,
     519             :   /* 111 */ 42, 1, 1, 1, 1, 0,
     520             :   /* 117 */ 42, 1, 1, 1, 0,
     521             :   /* 122 */ 64510, 1, 1, 1, 0,
     522             :   /* 127 */ 65015, 1, 1, 1, 0,
     523             :   /* 132 */ 65282, 1, 1, 1, 0,
     524             :   /* 137 */ 65348, 1, 1, 1, 0,
     525             :   /* 142 */ 13, 1, 1, 0,
     526             :   /* 146 */ 42, 1, 1, 0,
     527             :   /* 150 */ 65388, 1, 1, 0,
     528             :   /* 154 */ 137, 65489, 48, 65489, 12, 121, 65416, 1, 1, 0,
     529             :   /* 164 */ 136, 65490, 47, 65490, 12, 121, 65416, 1, 1, 0,
     530             :   /* 174 */ 135, 65491, 46, 65491, 12, 121, 65416, 1, 1, 0,
     531             :   /* 184 */ 134, 65492, 45, 65492, 12, 121, 65416, 1, 1, 0,
     532             :   /* 194 */ 133, 65493, 44, 65493, 12, 121, 65416, 1, 1, 0,
     533             :   /* 204 */ 132, 65494, 43, 65494, 12, 121, 65416, 1, 1, 0,
     534             :   /* 214 */ 131, 65495, 42, 65495, 12, 121, 65416, 1, 1, 0,
     535             :   /* 224 */ 130, 65496, 41, 65496, 12, 121, 65416, 1, 1, 0,
     536             :   /* 234 */ 129, 65497, 40, 65497, 12, 121, 65416, 1, 1, 0,
     537             :   /* 244 */ 128, 65498, 39, 65498, 12, 121, 65416, 1, 1, 0,
     538             :   /* 254 */ 65489, 133, 65416, 1, 1, 0,
     539             :   /* 260 */ 65490, 133, 65416, 1, 1, 0,
     540             :   /* 266 */ 65491, 133, 65416, 1, 1, 0,
     541             :   /* 272 */ 65492, 133, 65416, 1, 1, 0,
     542             :   /* 278 */ 65493, 133, 65416, 1, 1, 0,
     543             :   /* 284 */ 65494, 133, 65416, 1, 1, 0,
     544             :   /* 290 */ 65495, 133, 65416, 1, 1, 0,
     545             :   /* 296 */ 65496, 133, 65416, 1, 1, 0,
     546             :   /* 302 */ 65497, 133, 65416, 1, 1, 0,
     547             :   /* 308 */ 65498, 133, 65416, 1, 1, 0,
     548             :   /* 314 */ 127, 65499, 38, 65499, 133, 65416, 1, 1, 0,
     549             :   /* 323 */ 65080, 1, 3, 1, 3, 1, 3, 1, 0,
     550             :   /* 332 */ 65136, 1, 3, 1, 3, 1, 0,
     551             :   /* 339 */ 65326, 1, 3, 1, 0,
     552             :   /* 344 */ 13, 1, 0,
     553             :   /* 347 */ 14, 1, 0,
     554             :   /* 350 */ 65, 1, 0,
     555             :   /* 353 */ 65500, 65, 1, 65471, 66, 1, 0,
     556             :   /* 360 */ 65291, 66, 1, 65470, 67, 1, 0,
     557             :   /* 367 */ 65439, 65, 1, 65472, 67, 1, 0,
     558             :   /* 374 */ 65501, 67, 1, 65469, 68, 1, 0,
     559             :   /* 381 */ 65439, 66, 1, 65471, 68, 1, 0,
     560             :   /* 388 */ 65292, 68, 1, 65468, 69, 1, 0,
     561             :   /* 395 */ 65439, 67, 1, 65470, 69, 1, 0,
     562             :   /* 402 */ 65502, 69, 1, 65467, 70, 1, 0,
     563             :   /* 409 */ 65439, 68, 1, 65469, 70, 1, 0,
     564             :   /* 416 */ 65293, 70, 1, 65466, 71, 1, 0,
     565             :   /* 423 */ 65439, 69, 1, 65468, 71, 1, 0,
     566             :   /* 430 */ 65503, 71, 1, 65465, 72, 1, 0,
     567             :   /* 437 */ 65439, 70, 1, 65467, 72, 1, 0,
     568             :   /* 444 */ 65294, 72, 1, 65464, 73, 1, 0,
     569             :   /* 451 */ 65439, 71, 1, 65466, 73, 1, 0,
     570             :   /* 458 */ 65504, 73, 1, 65463, 74, 1, 0,
     571             :   /* 465 */ 65439, 72, 1, 65465, 74, 1, 0,
     572             :   /* 472 */ 65295, 74, 1, 65462, 75, 1, 0,
     573             :   /* 479 */ 65439, 73, 1, 65464, 75, 1, 0,
     574             :   /* 486 */ 65505, 75, 1, 65461, 76, 1, 0,
     575             :   /* 493 */ 65439, 74, 1, 65463, 76, 1, 0,
     576             :   /* 500 */ 65296, 76, 1, 65460, 77, 1, 0,
     577             :   /* 507 */ 65439, 75, 1, 65462, 77, 1, 0,
     578             :   /* 514 */ 65506, 77, 1, 65459, 78, 1, 0,
     579             :   /* 521 */ 65439, 76, 1, 65461, 78, 1, 0,
     580             :   /* 528 */ 65297, 78, 1, 65458, 79, 1, 0,
     581             :   /* 535 */ 65439, 77, 1, 65460, 79, 1, 0,
     582             :   /* 542 */ 65507, 79, 1, 65457, 80, 1, 0,
     583             :   /* 549 */ 65439, 78, 1, 65459, 80, 1, 0,
     584             :   /* 556 */ 65045, 1, 0,
     585             :   /* 559 */ 65260, 1, 0,
     586             :   /* 562 */ 65299, 1, 0,
     587             :   /* 565 */ 65300, 1, 0,
     588             :   /* 568 */ 65301, 1, 0,
     589             :   /* 571 */ 65302, 1, 0,
     590             :   /* 574 */ 65303, 1, 0,
     591             :   /* 577 */ 65304, 1, 0,
     592             :   /* 580 */ 65305, 1, 0,
     593             :   /* 583 */ 65453, 1, 65499, 133, 1, 65416, 1, 0,
     594             :   /* 591 */ 138, 65488, 49, 65488, 12, 121, 65416, 1, 0,
     595             :   /* 600 */ 65488, 13, 121, 65416, 1, 0,
     596             :   /* 606 */ 65489, 13, 121, 65416, 1, 0,
     597             :   /* 612 */ 65490, 13, 121, 65416, 1, 0,
     598             :   /* 618 */ 65491, 13, 121, 65416, 1, 0,
     599             :   /* 624 */ 65492, 13, 121, 65416, 1, 0,
     600             :   /* 630 */ 65493, 13, 121, 65416, 1, 0,
     601             :   /* 636 */ 65494, 13, 121, 65416, 1, 0,
     602             :   /* 642 */ 65495, 13, 121, 65416, 1, 0,
     603             :   /* 648 */ 65496, 13, 121, 65416, 1, 0,
     604             :   /* 654 */ 65497, 13, 121, 65416, 1, 0,
     605             :   /* 660 */ 65498, 13, 121, 65416, 1, 0,
     606             :   /* 666 */ 65464, 1, 65488, 133, 65416, 121, 65416, 1, 0,
     607             :   /* 675 */ 65463, 1, 65489, 133, 65416, 121, 65416, 1, 0,
     608             :   /* 684 */ 65462, 1, 65490, 133, 65416, 121, 65416, 1, 0,
     609             :   /* 693 */ 65461, 1, 65491, 133, 65416, 121, 65416, 1, 0,
     610             :   /* 702 */ 65460, 1, 65492, 133, 65416, 121, 65416, 1, 0,
     611             :   /* 711 */ 65459, 1, 65493, 133, 65416, 121, 65416, 1, 0,
     612             :   /* 720 */ 65458, 1, 65494, 133, 65416, 121, 65416, 1, 0,
     613             :   /* 729 */ 65457, 1, 65495, 133, 65416, 121, 65416, 1, 0,
     614             :   /* 738 */ 65456, 1, 65496, 133, 65416, 121, 65416, 1, 0,
     615             :   /* 747 */ 65455, 1, 65497, 133, 65416, 121, 65416, 1, 0,
     616             :   /* 756 */ 65454, 1, 65498, 133, 65416, 121, 65416, 1, 0,
     617             :   /* 765 */ 65488, 133, 65416, 1, 0,
     618             :   /* 770 */ 65499, 134, 65416, 1, 0,
     619             :   /* 775 */ 126, 65500, 37, 65500, 133, 65417, 1, 0,
     620             :   /* 783 */ 65432, 1, 0,
     621             :   /* 786 */ 65433, 1, 0,
     622             :   /* 789 */ 65434, 1, 0,
     623             :   /* 792 */ 65435, 1, 0,
     624             :   /* 795 */ 65436, 1, 0,
     625             :   /* 798 */ 65437, 1, 0,
     626             :   /* 801 */ 65464, 1, 0,
     627             :   /* 804 */ 65508, 1, 0,
     628             :   /* 807 */ 65509, 1, 0,
     629             :   /* 810 */ 65510, 1, 0,
     630             :   /* 813 */ 65511, 1, 0,
     631             :   /* 816 */ 65512, 1, 0,
     632             :   /* 819 */ 65513, 1, 0,
     633             :   /* 822 */ 65514, 1, 0,
     634             :   /* 825 */ 65515, 1, 0,
     635             :   /* 828 */ 65520, 1, 0,
     636             :   /* 831 */ 65080, 1, 3, 1, 3, 1, 2, 0,
     637             :   /* 839 */ 65136, 1, 3, 1, 2, 0,
     638             :   /* 845 */ 65326, 1, 2, 0,
     639             :   /* 849 */ 65080, 1, 3, 1, 2, 2, 0,
     640             :   /* 856 */ 65136, 1, 2, 2, 0,
     641             :   /* 861 */ 65080, 1, 2, 2, 2, 0,
     642             :   /* 867 */ 65330, 2, 2, 2, 0,
     643             :   /* 872 */ 65080, 1, 3, 2, 2, 0,
     644             :   /* 878 */ 65358, 2, 2, 0,
     645             :   /* 882 */ 65080, 1, 3, 1, 3, 2, 0,
     646             :   /* 889 */ 65136, 1, 3, 2, 0,
     647             :   /* 894 */ 65344, 76, 1, 65461, 78, 1, 65459, 80, 1, 12, 2, 0,
     648             :   /* 906 */ 65344, 75, 1, 65462, 77, 1, 65460, 79, 1, 13, 2, 0,
     649             :   /* 918 */ 65344, 74, 1, 65463, 76, 1, 65461, 78, 1, 14, 2, 0,
     650             :   /* 930 */ 65344, 73, 1, 65464, 75, 1, 65462, 77, 1, 15, 2, 0,
     651             :   /* 942 */ 65344, 72, 1, 65465, 74, 1, 65463, 76, 1, 16, 2, 0,
     652             :   /* 954 */ 65344, 71, 1, 65466, 73, 1, 65464, 75, 1, 17, 2, 0,
     653             :   /* 966 */ 65344, 70, 1, 65467, 72, 1, 65465, 74, 1, 18, 2, 0,
     654             :   /* 978 */ 65344, 69, 1, 65468, 71, 1, 65466, 73, 1, 19, 2, 0,
     655             :   /* 990 */ 65344, 68, 1, 65469, 70, 1, 65467, 72, 1, 20, 2, 0,
     656             :   /* 1002 */ 65344, 67, 1, 65470, 69, 1, 65468, 71, 1, 21, 2, 0,
     657             :   /* 1014 */ 65344, 66, 1, 65471, 68, 1, 65469, 70, 1, 22, 2, 0,
     658             :   /* 1026 */ 65344, 65, 1, 65472, 67, 1, 65470, 69, 1, 23, 2, 0,
     659             :   /* 1038 */ 65344, 2, 2, 93, 2, 0,
     660             :   /* 1044 */ 65344, 80, 1, 65457, 2, 93, 2, 0,
     661             :   /* 1052 */ 65344, 79, 1, 65458, 2, 93, 2, 0,
     662             :   /* 1060 */ 65344, 78, 1, 65459, 80, 1, 65457, 93, 2, 0,
     663             :   /* 1070 */ 65344, 77, 1, 65460, 79, 1, 65458, 93, 2, 0,
     664             :   /* 1080 */ 65439, 2, 0,
     665             :   /* 1083 */ 65453, 2, 0,
     666             :   /* 1086 */ 65080, 1, 3, 1, 3, 1, 3, 0,
     667             :   /* 1094 */ 65136, 1, 3, 1, 3, 0,
     668             :   /* 1100 */ 65326, 1, 3, 0,
     669             :   /* 1104 */ 5, 0,
     670             :   /* 1106 */ 140, 65486, 13, 0,
     671             :   /* 1110 */ 14, 0,
     672             :   /* 1112 */ 126, 65501, 15, 0,
     673             :   /* 1116 */ 10, 66, 0,
     674             :   /* 1119 */ 65445, 65514, 1, 22, 65515, 1, 94, 65, 65472, 65, 69, 0,
     675             :   /* 1131 */ 65445, 65513, 1, 23, 65514, 1, 94, 65, 65472, 65, 70, 0,
     676             :   /* 1143 */ 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 0,
     677             :   /* 1155 */ 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 0,
     678             :   /* 1167 */ 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 0,
     679             :   /* 1179 */ 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 0,
     680             :   /* 1191 */ 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 0,
     681             :   /* 1203 */ 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 0,
     682             :   /* 1219 */ 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 0,
     683             :   /* 1239 */ 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 0,
     684             :   /* 1259 */ 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 0,
     685             :   /* 1279 */ 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 0,
     686             :   /* 1299 */ 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 0,
     687             :   /* 1319 */ 65445, 65501, 67, 1, 65469, 68, 1, 65502, 65502, 69, 1, 65467, 70, 1, 23, 65, 65472, 65, 82, 0,
     688             :   /* 1339 */ 65445, 65500, 65, 1, 65471, 66, 1, 65505, 65501, 67, 1, 65469, 68, 1, 25, 65, 65472, 65, 83, 0,
     689             :   /* 1359 */ 91, 0,
     690             :   /* 1361 */ 98, 0,
     691             :   /* 1363 */ 99, 0,
     692             :   /* 1365 */ 100, 0,
     693             :   /* 1367 */ 101, 0,
     694             :   /* 1369 */ 102, 0,
     695             :   /* 1371 */ 103, 0,
     696             :   /* 1373 */ 104, 0,
     697             :   /* 1375 */ 65374, 1, 1, 20, 75, 135, 0,
     698             :   /* 1382 */ 65374, 1, 1, 21, 74, 136, 0,
     699             :   /* 1389 */ 65374, 1, 1, 22, 73, 137, 0,
     700             :   /* 1396 */ 65374, 1, 1, 23, 72, 138, 0,
     701             :   /* 1403 */ 65374, 1, 1, 24, 71, 139, 0,
     702             :   /* 1410 */ 65374, 1, 1, 25, 70, 140, 0,
     703             :   /* 1417 */ 65374, 1, 1, 26, 69, 141, 0,
     704             :   /* 1424 */ 65374, 79, 1, 65457, 80, 1, 65456, 27, 68, 142, 0,
     705             :   /* 1435 */ 65374, 77, 1, 65459, 78, 1, 65458, 79, 1, 65484, 67, 143, 0,
     706             :   /* 1448 */ 65374, 75, 1, 65461, 76, 1, 65460, 77, 1, 65487, 66, 144, 0,
     707             :   /* 1461 */ 65374, 73, 1, 65463, 74, 1, 65462, 75, 1, 65490, 65, 145, 0,
     708             :   /* 1474 */ 65374, 71, 1, 65465, 72, 1, 65464, 73, 1, 65493, 64, 146, 0,
     709             :   /* 1487 */ 65374, 69, 1, 65467, 70, 1, 65466, 71, 1, 65496, 63, 147, 0,
     710             :   /* 1500 */ 65374, 67, 1, 65469, 68, 1, 65468, 69, 1, 65499, 62, 148, 0,
     711             :   /* 1513 */ 65374, 65, 1, 65471, 66, 1, 65470, 67, 1, 65502, 61, 149, 0,
     712             :   /* 1526 */ 157, 0,
     713             :   /* 1528 */ 65289, 1, 1, 1, 229, 1, 65400, 65, 65472, 65, 65396, 0,
     714             :   /* 1540 */ 65288, 1, 1, 1, 230, 1, 65399, 65, 65472, 65, 65397, 0,
     715             :   /* 1552 */ 65287, 1, 1, 1, 231, 1, 65398, 65, 65472, 65, 65398, 0,
     716             :   /* 1564 */ 65286, 1, 1, 1, 232, 1, 65397, 65, 65472, 65, 65399, 0,
     717             :   /* 1576 */ 65285, 1, 1, 1, 233, 1, 65396, 65, 65472, 65, 65400, 0,
     718             :   /* 1588 */ 65284, 1, 1, 1, 234, 1, 65395, 65, 65472, 65, 65401, 0,
     719             :   /* 1600 */ 65521, 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 65419, 65445, 65514, 1, 22, 65515, 1, 94, 65, 65472, 65, 69, 65492, 28, 65509, 28, 28, 65386, 65, 30, 65442, 65, 30, 40, 15, 65402, 0,
     720             :   /* 1639 */ 65521, 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 65419, 65445, 65513, 1, 23, 65514, 1, 94, 65, 65472, 65, 70, 65491, 28, 65509, 28, 29, 65385, 65, 30, 65442, 65, 30, 41, 15, 65402, 0,
     721             :   /* 1678 */ 65521, 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 65419, 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 65490, 28, 65509, 28, 30, 65384, 65, 30, 65442, 65, 30, 42, 15, 65402, 0,
     722             :   /* 1717 */ 65521, 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 65419, 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 65489, 28, 65509, 28, 31, 65383, 65, 30, 65442, 65, 30, 43, 15, 65402, 0,
     723             :   /* 1756 */ 65521, 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 65419, 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 65488, 28, 65509, 28, 32, 65382, 65, 30, 65442, 65, 30, 44, 15, 65402, 0,
     724             :   /* 1795 */ 65521, 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 65419, 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 65487, 28, 65509, 28, 33, 65381, 65, 30, 65442, 65, 30, 45, 15, 65402, 0,
     725             :   /* 1838 */ 65521, 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 65419, 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 65486, 28, 65509, 28, 34, 65380, 65, 30, 65442, 65, 30, 46, 15, 65402, 0,
     726             :   /* 1885 */ 65521, 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 65419, 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 65485, 28, 65509, 28, 35, 65379, 65, 30, 65442, 65, 30, 47, 15, 65402, 0,
     727             :   /* 1936 */ 65521, 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 65419, 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 65484, 28, 65509, 28, 36, 65378, 65, 30, 65442, 65, 30, 48, 15, 65402, 0,
     728             :   /* 1991 */ 65521, 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 65419, 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 65483, 28, 65509, 28, 37, 65377, 65, 30, 65442, 65, 30, 49, 15, 65402, 0,
     729             :   /* 2046 */ 65521, 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 65419, 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 65482, 28, 65509, 28, 38, 65376, 65, 30, 65442, 65, 30, 50, 15, 65402, 0,
     730             :   /* 2101 */ 65521, 65445, 65501, 67, 1, 65469, 68, 1, 65502, 65502, 69, 1, 65467, 70, 1, 23, 65, 65472, 65, 82, 65419, 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 65481, 28, 65509, 28, 39, 65375, 65, 30, 65442, 65, 30, 51, 15, 65402, 0,
     731             :   /* 2156 */ 65521, 65445, 65500, 65, 1, 65471, 66, 1, 65505, 65501, 67, 1, 65469, 68, 1, 25, 65, 65472, 65, 83, 65419, 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 65480, 28, 65509, 28, 40, 65374, 65, 30, 65442, 65, 30, 52, 15, 65402, 0,
     732             :   /* 2211 */ 65283, 80, 1, 65456, 1, 1, 235, 1, 65394, 65, 65472, 65, 65402, 0,
     733             :   /* 2225 */ 65282, 78, 1, 65458, 79, 1, 65457, 80, 1, 65456, 236, 1, 65393, 65, 65472, 65, 65403, 0,
     734             :   /* 2243 */ 65281, 76, 1, 65460, 77, 1, 65459, 78, 1, 65458, 79, 1, 157, 1, 65392, 65, 65472, 65, 65404, 0,
     735             :   /* 2263 */ 65280, 74, 1, 65462, 75, 1, 65461, 76, 1, 65460, 77, 1, 160, 1, 65391, 65, 65472, 65, 65405, 0,
     736             :   /* 2283 */ 65279, 72, 1, 65464, 73, 1, 65463, 74, 1, 65462, 75, 1, 163, 1, 65390, 65, 65472, 65, 65406, 0,
     737             :   /* 2303 */ 65278, 70, 1, 65466, 71, 1, 65465, 72, 1, 65464, 73, 1, 166, 1, 65389, 65, 65472, 65, 65407, 0,
     738             :   /* 2323 */ 65277, 68, 1, 65468, 69, 1, 65467, 70, 1, 65466, 71, 1, 169, 1, 65388, 65, 65472, 65, 65408, 0,
     739             :   /* 2343 */ 65276, 66, 1, 65470, 67, 1, 65469, 68, 1, 65468, 69, 1, 172, 1, 65387, 65, 65472, 65, 65409, 0,
     740             :   /* 2363 */ 22, 73, 2, 63, 65488, 120, 65465, 1, 65487, 75, 26, 65447, 65, 26, 30, 65416, 66, 26, 29, 65416, 0,
     741             :   /* 2384 */ 21, 74, 2, 63, 65487, 120, 65466, 1, 65486, 76, 26, 65446, 66, 26, 29, 65416, 0,
     742             :   /* 2401 */ 65, 65487, 77, 26, 65446, 66, 26, 29, 65416, 0,
     743             :   /* 2411 */ 22, 73, 2, 134, 65465, 1, 65487, 50, 65487, 75, 26, 31, 65416, 65, 26, 30, 65416, 0,
     744             :   /* 2429 */ 21, 74, 135, 65466, 1, 65486, 77, 26, 30, 65416, 0,
     745             :   /* 2440 */ 65, 65487, 77, 26, 30, 65416, 0,
     746             :   /* 2447 */ 139, 65487, 50, 65487, 12, 121, 65416, 0,
     747             :   /* 2455 */ 65487, 13, 121, 65416, 0,
     748             :   /* 2460 */ 65465, 1, 65487, 133, 65416, 121, 65416, 0,
     749             :   /* 2468 */ 65466, 1, 65486, 133, 65416, 0,
     750             :   /* 2474 */ 65487, 133, 65416, 0,
     751             :   /* 2478 */ 65469, 35, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0,
     752             :   /* 2490 */ 65470, 35, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0,
     753             :   /* 2502 */ 65, 65500, 66, 28, 40, 65417, 0,
     754             :   /* 2509 */ 65452, 1, 65500, 134, 65417, 0,
     755             :   /* 2515 */ 65316, 74, 1, 65463, 76, 1, 65461, 78, 1, 65459, 80, 1, 10, 95, 65443, 95, 65443, 0,
     756             :   /* 2533 */ 65316, 73, 1, 65464, 75, 1, 65462, 77, 1, 65460, 79, 1, 11, 95, 65443, 95, 65443, 0,
     757             :   /* 2551 */ 65316, 72, 1, 65465, 74, 1, 65463, 76, 1, 65461, 78, 1, 12, 95, 65443, 95, 65443, 0,
     758             :   /* 2569 */ 65316, 71, 1, 65466, 73, 1, 65464, 75, 1, 65462, 77, 1, 13, 95, 65443, 95, 65443, 0,
     759             :   /* 2587 */ 65316, 70, 1, 65467, 72, 1, 65465, 74, 1, 65463, 76, 1, 14, 95, 65443, 95, 65443, 0,
     760             :   /* 2605 */ 65316, 69, 1, 65468, 71, 1, 65466, 73, 1, 65464, 75, 1, 15, 95, 65443, 95, 65443, 0,
     761             :   /* 2623 */ 65316, 68, 1, 65469, 70, 1, 65467, 72, 1, 65465, 74, 1, 16, 95, 65443, 95, 65443, 0,
     762             :   /* 2641 */ 65316, 67, 1, 65470, 69, 1, 65468, 71, 1, 65466, 73, 1, 17, 95, 65443, 95, 65443, 0,
     763             :   /* 2659 */ 65316, 66, 1, 65471, 68, 1, 65469, 70, 1, 65467, 72, 1, 18, 95, 65443, 95, 65443, 0,
     764             :   /* 2677 */ 65316, 65, 1, 65472, 67, 1, 65470, 69, 1, 65468, 71, 1, 19, 95, 65443, 95, 65443, 0,
     765             :   /* 2695 */ 65316, 2, 2, 2, 91, 95, 65443, 95, 65443, 0,
     766             :   /* 2705 */ 65316, 80, 1, 65457, 2, 2, 91, 95, 65443, 95, 65443, 0,
     767             :   /* 2717 */ 65316, 79, 1, 65458, 2, 2, 91, 95, 65443, 95, 65443, 0,
     768             :   /* 2729 */ 65316, 78, 1, 65459, 80, 1, 65457, 2, 91, 95, 65443, 95, 65443, 0,
     769             :   /* 2743 */ 65316, 77, 1, 65460, 79, 1, 65458, 2, 91, 95, 65443, 95, 65443, 0,
     770             :   /* 2757 */ 65316, 76, 1, 65461, 78, 1, 65459, 80, 1, 65457, 91, 95, 65443, 95, 65443, 0,
     771             :   /* 2773 */ 65316, 75, 1, 65462, 77, 1, 65460, 79, 1, 65458, 91, 95, 65443, 95, 65443, 0,
     772             :   /* 2789 */ 20, 75, 65, 65486, 78, 26, 65445, 0,
     773             :   /* 2797 */ 23, 72, 2, 63, 65489, 120, 65464, 1, 65488, 74, 26, 65448, 64, 26, 31, 65416, 65, 26, 30, 65416, 92, 65445, 0,
     774             :   /* 2820 */ 65, 65488, 76, 26, 65447, 65, 26, 30, 65416, 92, 65445, 0,
     775             :   /* 2832 */ 26, 65446, 92, 65445, 0,
     776             :   /* 2837 */ 23, 72, 2, 135, 65464, 1, 65488, 49, 65488, 74, 26, 32, 65416, 64, 26, 31, 65416, 65, 26, 65446, 0,
     777             :   /* 2858 */ 65, 65488, 76, 26, 31, 65416, 65, 26, 65446, 0,
     778             :   /* 2868 */ 24, 71, 2, 63, 65490, 120, 65463, 1, 65489, 73, 26, 65449, 63, 26, 32, 65416, 64, 26, 31, 65416, 91, 65446, 0,
     779             :   /* 2891 */ 65, 65489, 75, 26, 65448, 64, 26, 31, 65416, 91, 65446, 0,
     780             :   /* 2903 */ 24, 71, 2, 136, 65463, 1, 65489, 48, 65489, 73, 26, 33, 65416, 63, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0,
     781             :   /* 2926 */ 65, 65489, 75, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0,
     782             :   /* 2938 */ 25, 70, 2, 63, 65491, 120, 65462, 1, 65490, 72, 26, 65450, 62, 26, 33, 65416, 63, 26, 32, 65416, 90, 65447, 0,
     783             :   /* 2961 */ 65, 65490, 74, 26, 65449, 63, 26, 32, 65416, 90, 65447, 0,
     784             :   /* 2973 */ 25, 70, 2, 137, 65462, 1, 65490, 47, 65490, 72, 26, 34, 65416, 62, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0,
     785             :   /* 2996 */ 65, 65490, 74, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0,
     786             :   /* 3008 */ 26, 69, 2, 63, 65492, 120, 65461, 1, 65491, 71, 26, 65451, 61, 26, 34, 65416, 62, 26, 33, 65416, 89, 65448, 0,
     787             :   /* 3031 */ 65, 65491, 73, 26, 65450, 62, 26, 33, 65416, 89, 65448, 0,
     788             :   /* 3043 */ 26, 69, 2, 138, 65461, 1, 65491, 46, 65491, 71, 26, 35, 65416, 61, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0,
     789             :   /* 3066 */ 65, 65491, 73, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0,
     790             :   /* 3078 */ 27, 68, 2, 63, 65493, 120, 65460, 1, 65492, 70, 26, 65452, 60, 26, 35, 65416, 61, 26, 34, 65416, 88, 65449, 0,
     791             :   /* 3101 */ 65, 65492, 72, 26, 65451, 61, 26, 34, 65416, 88, 65449, 0,
     792             :   /* 3113 */ 27, 68, 2, 139, 65460, 1, 65492, 45, 65492, 70, 26, 36, 65416, 60, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0,
     793             :   /* 3136 */ 65, 65492, 72, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0,
     794             :   /* 3148 */ 65455, 28, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0,
     795             :   /* 3172 */ 65456, 28, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0,
     796             :   /* 3196 */ 65, 65493, 71, 26, 65452, 60, 26, 35, 65416, 87, 65450, 0,
     797             :   /* 3208 */ 28, 67, 2, 140, 65459, 1, 65493, 44, 65493, 69, 26, 37, 65416, 59, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0,
     798             :   /* 3231 */ 65, 65493, 71, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0,
     799             :   /* 3243 */ 65457, 29, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0,
     800             :   /* 3267 */ 65458, 29, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0,
     801             :   /* 3291 */ 65, 65494, 70, 26, 65453, 59, 26, 36, 65416, 86, 65451, 0,
     802             :   /* 3303 */ 65456, 29, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0,
     803             :   /* 3327 */ 65457, 29, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0,
     804             :   /* 3351 */ 65, 65494, 70, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0,
     805             :   /* 3363 */ 65459, 30, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0,
     806             :   /* 3387 */ 65460, 30, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0,
     807             :   /* 3411 */ 65, 65495, 69, 26, 65454, 58, 26, 37, 65416, 85, 65452, 0,
     808             :   /* 3423 */ 65458, 30, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0,
     809             :   /* 3447 */ 65459, 30, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0,
     810             :   /* 3471 */ 65, 65495, 69, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0,
     811             :   /* 3483 */ 65461, 31, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0,
     812             :   /* 3507 */ 65462, 31, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0,
     813             :   /* 3531 */ 65, 65496, 68, 26, 65455, 57, 26, 38, 65416, 84, 65453, 0,
     814             :   /* 3543 */ 65460, 31, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0,
     815             :   /* 3567 */ 65461, 31, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0,
     816             :   /* 3591 */ 65, 65496, 68, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0,
     817             :   /* 3603 */ 65463, 32, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0,
     818             :   /* 3627 */ 65464, 32, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0,
     819             :   /* 3651 */ 65, 65497, 67, 26, 65456, 56, 26, 39, 65416, 83, 65454, 0,
     820             :   /* 3663 */ 65462, 32, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0,
     821             :   /* 3687 */ 65463, 32, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0,
     822             :   /* 3711 */ 65, 65497, 67, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0,
     823             :   /* 3723 */ 65465, 33, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0,
     824             :   /* 3745 */ 65466, 33, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0,
     825             :   /* 3767 */ 65, 65498, 66, 26, 65457, 55, 26, 40, 65416, 82, 65455, 0,
     826             :   /* 3779 */ 65464, 33, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0,
     827             :   /* 3803 */ 65465, 33, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0,
     828             :   /* 3827 */ 65, 65498, 66, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0,
     829             :   /* 3839 */ 65298, 80, 1, 65456, 0,
     830             :   /* 3844 */ 65467, 34, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0,
     831             :   /* 3863 */ 65468, 34, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0,
     832             :   /* 3882 */ 65, 65499, 65, 2, 26, 41, 65416, 81, 65456, 0,
     833             :   /* 3892 */ 65466, 34, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0,
     834             :   /* 3914 */ 65467, 34, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0,
     835             :   /* 3936 */ 65, 65499, 65, 26, 42, 65416, 54, 26, 65457, 81, 65456, 0,
     836             :   /* 3948 */ 65439, 80, 1, 65457, 0,
     837             :   /* 3953 */ 28, 65457, 0,
     838             :   /* 3956 */ 65468, 35, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0,
     839             :   /* 3974 */ 65469, 35, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0,
     840             :   /* 3992 */ 65, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0,
     841             :   /* 4002 */ 26, 65458, 80, 65457, 0,
     842             :   /* 4007 */ 65439, 79, 1, 65458, 0,
     843             :   /* 4012 */ 65470, 36, 61, 65, 65501, 65, 28, 65458, 0,
     844             :   /* 4021 */ 65471, 36, 61, 65, 65501, 65, 28, 65458, 0,
     845             :   /* 4030 */ 65374, 1, 1, 229, 65402, 65461, 0,
     846             :   /* 4037 */ 65374, 1, 1, 230, 65401, 65462, 0,
     847             :   /* 4044 */ 65374, 1, 1, 231, 65400, 65463, 0,
     848             :   /* 4051 */ 65374, 1, 1, 232, 65399, 65464, 0,
     849             :   /* 4058 */ 65374, 1, 1, 233, 65398, 65465, 0,
     850             :   /* 4065 */ 65374, 1, 1, 234, 65397, 65466, 0,
     851             :   /* 4072 */ 65374, 1, 1, 235, 65396, 65467, 0,
     852             :   /* 4079 */ 65374, 80, 1, 65456, 1, 236, 65395, 65468, 0,
     853             :   /* 4088 */ 65374, 78, 1, 65458, 79, 1, 65457, 80, 1, 156, 65394, 65469, 0,
     854             :   /* 4101 */ 65374, 76, 1, 65460, 77, 1, 65459, 78, 1, 159, 65393, 65470, 0,
     855             :   /* 4114 */ 65445, 65470, 0,
     856             :   /* 4117 */ 65374, 74, 1, 65462, 75, 1, 65461, 76, 1, 162, 65392, 65471, 0,
     857             :   /* 4130 */ 65374, 72, 1, 65464, 73, 1, 65463, 74, 1, 165, 65391, 65472, 0,
     858             :   /* 4143 */ 65374, 70, 1, 65466, 71, 1, 65465, 72, 1, 168, 65390, 65473, 0,
     859             :   /* 4156 */ 65374, 68, 1, 65468, 69, 1, 65467, 70, 1, 171, 65389, 65474, 0,
     860             :   /* 4169 */ 65374, 66, 1, 65470, 67, 1, 65469, 68, 1, 174, 65388, 65475, 0,
     861             :   /* 4182 */ 65534, 0,
     862             :   /* 4184 */ 65535, 0,
     863             : };
     864             : 
     865             : extern const LaneBitmask ARMLaneMaskLists[] = {
     866             :   /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
     867             :   /* 2 */ LaneBitmask(0x00000002), LaneBitmask(0x00000001), LaneBitmask::getAll(),
     868             :   /* 5 */ LaneBitmask(0x00000001), LaneBitmask(0x00000002), LaneBitmask::getAll(),
     869             :   /* 8 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask::getAll(),
     870             :   /* 11 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask::getAll(),
     871             :   /* 16 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000030), LaneBitmask::getAll(),
     872             :   /* 20 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask::getAll(),
     873             :   /* 23 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask::getAll(),
     874             :   /* 28 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask::getAll(),
     875             :   /* 35 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x000000C0), LaneBitmask::getAll(),
     876             :   /* 39 */ LaneBitmask(0x0000000C), LaneBitmask(0x000000C0), LaneBitmask::getAll(),
     877             :   /* 42 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x000000C0), LaneBitmask::getAll(),
     878             :   /* 48 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask::getAll(),
     879             :   /* 53 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask::getAll(),
     880             :   /* 57 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask::getAll(),
     881             :   /* 66 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000300), LaneBitmask::getAll(),
     882             :   /* 74 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask::getAll(),
     883             :   /* 81 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask::getAll(),
     884             :   /* 87 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask::getAll(),
     885             :   /* 92 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask::getAll(),
     886             :   /* 99 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000C00), LaneBitmask::getAll(),
     887             :   /* 105 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask::getAll(),
     888             :   /* 110 */ LaneBitmask(0x0000000C), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask::getAll(),
     889             :   /* 114 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x00004000), LaneBitmask(0x00008000), LaneBitmask::getAll(),
     890             :   /* 123 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x0000C000), LaneBitmask::getAll(),
     891             :   /* 131 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000C00), LaneBitmask(0x0000C000), LaneBitmask::getAll(),
     892             :   /* 138 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask(0x0000C000), LaneBitmask::getAll(),
     893             :   /* 144 */ LaneBitmask(0x0000000C), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask(0x0000C000), LaneBitmask::getAll(),
     894             :   /* 149 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x00001000), LaneBitmask(0x00002000), LaneBitmask(0x00004000), LaneBitmask(0x00008000), LaneBitmask(0x00010000), LaneBitmask(0x00020000), LaneBitmask::getAll(),
     895             :   /* 166 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x00001000), LaneBitmask(0x00002000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(),
     896             :   /* 181 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask(0x00000C00), LaneBitmask(0x00003000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(),
     897             :   /* 194 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask(0x00000C00), LaneBitmask(0x00003000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(),
     898             :   /* 205 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask(0x00000C00), LaneBitmask(0x00003000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(),
     899       72306 : };
     900             : 
     901             : extern const uint16_t ARMSubRegIdxLists[] = {
     902             :   /* 0 */ 1, 2, 0,
     903             :   /* 3 */ 1, 17, 18, 2, 0,
     904             :   /* 8 */ 1, 3, 0,
     905             :   /* 11 */ 1, 17, 18, 3, 0,
     906             :   /* 16 */ 9, 10, 0,
     907             :   /* 19 */ 17, 18, 0,
     908             :   /* 22 */ 1, 17, 18, 2, 19, 20, 0,
     909             :   /* 29 */ 1, 17, 18, 3, 21, 22, 0,
     910             :   /* 36 */ 1, 2, 3, 13, 33, 37, 0,
     911             :   /* 43 */ 1, 17, 18, 2, 3, 13, 33, 37, 0,
     912             :   /* 52 */ 1, 17, 18, 2, 19, 20, 3, 13, 33, 37, 0,
     913             :   /* 63 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 13, 33, 37, 0,
     914             :   /* 76 */ 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 0,
     915             :   /* 88 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 0,
     916             :   /* 104 */ 1, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0,
     917             :   /* 116 */ 1, 17, 18, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0,
     918             :   /* 130 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 13, 14, 33, 34, 35, 36, 37, 0,
     919             :   /* 148 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 23, 24, 13, 14, 33, 34, 35, 36, 37, 0,
     920             :   /* 168 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 0,
     921             :   /* 188 */ 1, 3, 5, 33, 43, 0,
     922             :   /* 194 */ 1, 17, 18, 3, 5, 33, 43, 0,
     923             :   /* 202 */ 1, 17, 18, 3, 21, 22, 5, 33, 43, 0,
     924             :   /* 212 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 33, 43, 0,
     925             :   /* 224 */ 1, 3, 5, 7, 33, 38, 43, 45, 51, 0,
     926             :   /* 234 */ 1, 17, 18, 3, 5, 7, 33, 38, 43, 45, 51, 0,
     927             :   /* 246 */ 1, 17, 18, 3, 21, 22, 5, 7, 33, 38, 43, 45, 51, 0,
     928             :   /* 260 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 33, 38, 43, 45, 51, 0,
     929             :   /* 276 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 29, 30, 33, 38, 43, 45, 51, 0,
     930             :   /* 294 */ 11, 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
     931             :   /* 333 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
     932             :   /* 376 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
     933             :   /* 423 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
     934             :   /* 474 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 29, 30, 8, 31, 32, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
     935             : };
     936             : 
     937             : extern const MCRegisterInfo::SubRegCoveredBits ARMSubRegIdxRanges[] = {
     938             :   { 65535, 65535 },
     939             :   { 0, 64 },    // dsub_0
     940             :   { 64, 64 },   // dsub_1
     941             :   { 128, 64 },  // dsub_2
     942             :   { 192, 64 },  // dsub_3
     943             :   { 256, 64 },  // dsub_4
     944             :   { 320, 64 },  // dsub_5
     945             :   { 384, 64 },  // dsub_6
     946             :   { 448, 64 },  // dsub_7
     947             :   { 0, 32 },    // gsub_0
     948             :   { 32, 32 },   // gsub_1
     949             :   { 0, 256 },   // qqsub_0
     950             :   { 256, 256 }, // qqsub_1
     951             :   { 0, 128 },   // qsub_0
     952             :   { 128, 128 }, // qsub_1
     953             :   { 256, 128 }, // qsub_2
     954             :   { 384, 128 }, // qsub_3
     955             :   { 0, 32 },    // ssub_0
     956             :   { 32, 32 },   // ssub_1
     957             :   { 64, 32 },   // ssub_2
     958             :   { 96, 32 },   // ssub_3
     959             :   { 128, 32 },  // ssub_4
     960             :   { 160, 32 },  // ssub_5
     961             :   { 192, 32 },  // ssub_6
     962             :   { 224, 32 },  // ssub_7
     963             :   { 256, 32 },  // ssub_8
     964             :   { 288, 32 },  // ssub_9
     965             :   { 320, 32 },  // ssub_10
     966             :   { 352, 32 },  // ssub_11
     967             :   { 384, 32 },  // ssub_12
     968             :   { 416, 32 },  // ssub_13
     969             :   { 448, 32 },  // dsub_7_then_ssub_0
     970             :   { 480, 32 },  // dsub_7_then_ssub_1
     971             :   { 65535, 128 },       // ssub_0_ssub_1_ssub_4_ssub_5
     972             :   { 0, 192 },   // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
     973             :   { 65535, 128 },       // ssub_2_ssub_3_ssub_6_ssub_7
     974             :   { 64, 192 },  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
     975             :   { 64, 128 },  // ssub_2_ssub_3_ssub_4_ssub_5
     976             :   { 65535, 192 },       // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
     977             :   { 65535, 256 },       // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
     978             :   { 65535, 192 },       // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
     979             :   { 65535, 256 },       // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
     980             :   { 64, 256 },  // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
     981             :   { 65535, 128 },       // ssub_4_ssub_5_ssub_8_ssub_9
     982             :   { 128, 192 }, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
     983             :   { 65535, 192 },       // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
     984             :   { 65535, 128 },       // ssub_6_ssub_7_dsub_5
     985             :   { 192, 192 }, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
     986             :   { 65535, 192 },       // ssub_6_ssub_7_dsub_5_dsub_7
     987             :   { 192, 128 }, // ssub_6_ssub_7_ssub_8_ssub_9
     988             :   { 192, 256 }, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
     989             :   { 65535, 128 },       // ssub_8_ssub_9_ssub_12_ssub_13
     990             :   { 256, 192 }, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
     991             :   { 65535, 128 },       // dsub_5_dsub_7
     992             :   { 320, 192 }, // dsub_5_ssub_12_ssub_13_dsub_7
     993             :   { 320, 128 }, // dsub_5_ssub_12_ssub_13
     994             :   { 128, 256 }, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
     995             : };
     996             : 
     997             : extern const char ARMRegStrings[] = {
     998             :   /* 0 */ 'D', '4', '_', 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', 0,
     999             :   /* 13 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
    1000             :   /* 26 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
    1001             :   /* 39 */ 'R', '1', '0', 0,
    1002             :   /* 43 */ 'S', '1', '0', 0,
    1003             :   /* 47 */ 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', 0,
    1004             :   /* 63 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0,
    1005             :   /* 79 */ 'S', '2', '0', 0,
    1006             :   /* 83 */ 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', '_', 'D', '3', '0', 0,
    1007             :   /* 99 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0,
    1008             :   /* 115 */ 'S', '3', '0', 0,
    1009             :   /* 119 */ 'D', '0', 0,
    1010             :   /* 122 */ 'Q', '0', 0,
    1011             :   /* 125 */ 'M', 'V', 'F', 'R', '0', 0,
    1012             :   /* 131 */ 'S', '0', 0,
    1013             :   /* 134 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0,
    1014             :   /* 145 */ 'D', '5', '_', 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', 0,
    1015             :   /* 158 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0,
    1016             :   /* 172 */ 'R', '1', '0', '_', 'R', '1', '1', 0,
    1017             :   /* 180 */ 'S', '1', '1', 0,
    1018             :   /* 184 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0,
    1019             :   /* 196 */ 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', 0,
    1020             :   /* 212 */ 'S', '2', '1', 0,
    1021             :   /* 216 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0,
    1022             :   /* 228 */ 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', '_', 'D', '3', '1', 0,
    1023             :   /* 244 */ 'S', '3', '1', 0,
    1024             :   /* 248 */ 'D', '1', 0,
    1025             :   /* 251 */ 'Q', '0', '_', 'Q', '1', 0,
    1026             :   /* 257 */ 'M', 'V', 'F', 'R', '1', 0,
    1027             :   /* 263 */ 'R', '0', '_', 'R', '1', 0,
    1028             :   /* 269 */ 'S', '1', 0,
    1029             :   /* 272 */ 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', 0,
    1030             :   /* 286 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0,
    1031             :   /* 301 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0,
    1032             :   /* 316 */ 'R', '1', '2', 0,
    1033             :   /* 320 */ 'S', '1', '2', 0,
    1034             :   /* 324 */ 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', 0,
    1035             :   /* 340 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0,
    1036             :   /* 356 */ 'S', '2', '2', 0,
    1037             :   /* 360 */ 'D', '0', '_', 'D', '2', 0,
    1038             :   /* 366 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', 0,
    1039             :   /* 375 */ 'Q', '1', '_', 'Q', '2', 0,
    1040             :   /* 381 */ 'M', 'V', 'F', 'R', '2', 0,
    1041             :   /* 387 */ 'S', '2', 0,
    1042             :   /* 390 */ 'F', 'P', 'I', 'N', 'S', 'T', '2', 0,
    1043             :   /* 398 */ 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', 0,
    1044             :   /* 412 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0,
    1045             :   /* 424 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0,
    1046             :   /* 440 */ 'S', '1', '3', 0,
    1047             :   /* 444 */ 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', 0,
    1048             :   /* 460 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0,
    1049             :   /* 472 */ 'S', '2', '3', 0,
    1050             :   /* 476 */ 'D', '1', '_', 'D', '3', 0,
    1051             :   /* 482 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', 0,
    1052             :   /* 491 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0,
    1053             :   /* 503 */ 'R', '2', '_', 'R', '3', 0,
    1054             :   /* 509 */ 'S', '3', 0,
    1055             :   /* 512 */ 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', 0,
    1056             :   /* 527 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0,
    1057             :   /* 543 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0,
    1058             :   /* 559 */ 'S', '1', '4', 0,
    1059             :   /* 563 */ 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', 0,
    1060             :   /* 579 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0,
    1061             :   /* 595 */ 'S', '2', '4', 0,
    1062             :   /* 599 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', 0,
    1063             :   /* 608 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0,
    1064             :   /* 620 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0,
    1065             :   /* 632 */ 'R', '4', 0,
    1066             :   /* 635 */ 'S', '4', 0,
    1067             :   /* 638 */ 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', 0,
    1068             :   /* 653 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0,
    1069             :   /* 665 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0,
    1070             :   /* 681 */ 'S', '1', '5', 0,
    1071             :   /* 685 */ 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', 0,
    1072             :   /* 701 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0,
    1073             :   /* 713 */ 'S', '2', '5', 0,
    1074             :   /* 717 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', 0,
    1075             :   /* 726 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', 0,
    1076             :   /* 735 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0,
    1077             :   /* 747 */ 'R', '4', '_', 'R', '5', 0,
    1078             :   /* 753 */ 'S', '5', 0,
    1079             :   /* 756 */ 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', 0,
    1080             :   /* 772 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0,
    1081             :   /* 788 */ 'S', '1', '6', 0,
    1082             :   /* 792 */ 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', 0,
    1083             :   /* 808 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0,
    1084             :   /* 824 */ 'S', '2', '6', 0,
    1085             :   /* 828 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', '_', 'D', '6', 0,
    1086             :   /* 840 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0,
    1087             :   /* 852 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0,
    1088             :   /* 864 */ 'R', '6', 0,
    1089             :   /* 867 */ 'S', '6', 0,
    1090             :   /* 870 */ 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', 0,
    1091             :   /* 886 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0,
    1092             :   /* 898 */ 'S', '1', '7', 0,
    1093             :   /* 902 */ 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', 0,
    1094             :   /* 918 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0,
    1095             :   /* 930 */ 'S', '2', '7', 0,
    1096             :   /* 934 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', '_', 'D', '7', 0,
    1097             :   /* 946 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', 0,
    1098             :   /* 955 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0,
    1099             :   /* 967 */ 'R', '6', '_', 'R', '7', 0,
    1100             :   /* 973 */ 'S', '7', 0,
    1101             :   /* 976 */ 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', 0,
    1102             :   /* 992 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0,
    1103             :   /* 1008 */ 'S', '1', '8', 0,
    1104             :   /* 1012 */ 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', 0,
    1105             :   /* 1028 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0,
    1106             :   /* 1044 */ 'S', '2', '8', 0,
    1107             :   /* 1048 */ 'D', '2', '_', 'D', '4', '_', 'D', '6', '_', 'D', '8', 0,
    1108             :   /* 1060 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0,
    1109             :   /* 1072 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0,
    1110             :   /* 1084 */ 'R', '8', 0,
    1111             :   /* 1087 */ 'S', '8', 0,
    1112             :   /* 1090 */ 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', 0,
    1113             :   /* 1106 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0,
    1114             :   /* 1118 */ 'S', '1', '9', 0,
    1115             :   /* 1122 */ 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', 0,
    1116             :   /* 1138 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0,
    1117             :   /* 1150 */ 'S', '2', '9', 0,
    1118             :   /* 1154 */ 'D', '3', '_', 'D', '5', '_', 'D', '7', '_', 'D', '9', 0,
    1119             :   /* 1166 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', 0,
    1120             :   /* 1175 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0,
    1121             :   /* 1187 */ 'R', '8', '_', 'R', '9', 0,
    1122             :   /* 1193 */ 'S', '9', 0,
    1123             :   /* 1196 */ 'P', 'C', 0,
    1124             :   /* 1199 */ 'F', 'P', 'E', 'X', 'C', 0,
    1125             :   /* 1205 */ 'F', 'P', 'S', 'I', 'D', 0,
    1126             :   /* 1211 */ 'I', 'T', 'S', 'T', 'A', 'T', 'E', 0,
    1127             :   /* 1219 */ 'R', '1', '2', '_', 'S', 'P', 0,
    1128             :   /* 1226 */ 'F', 'P', 'S', 'C', 'R', 0,
    1129             :   /* 1232 */ 'L', 'R', 0,
    1130             :   /* 1235 */ 'A', 'P', 'S', 'R', 0,
    1131             :   /* 1240 */ 'C', 'P', 'S', 'R', 0,
    1132             :   /* 1245 */ 'S', 'P', 'S', 'R', 0,
    1133             :   /* 1250 */ 'F', 'P', 'I', 'N', 'S', 'T', 0,
    1134             :   /* 1257 */ 'F', 'P', 'S', 'C', 'R', '_', 'N', 'Z', 'C', 'V', 0,
    1135             :   /* 1268 */ 'A', 'P', 'S', 'R', '_', 'N', 'Z', 'C', 'V', 0,
    1136             : };
    1137             : 
    1138             : extern const MCRegisterDesc ARMRegDesc[] = { // Descriptors
    1139             :   { 12, 0, 0, 0, 0, 0 },
    1140             :   { 1235, 16, 16, 2, 66945, 0 },
    1141             :   { 1268, 16, 16, 2, 66945, 0 },
    1142             :   { 1240, 16, 16, 2, 66945, 0 },
    1143             :   { 1199, 16, 16, 2, 66945, 0 },
    1144             :   { 1250, 16, 16, 2, 66945, 0 },
    1145             :   { 1226, 16, 16, 2, 17664, 0 },
    1146             :   { 1257, 16, 16, 2, 17664, 0 },
    1147             :   { 1205, 16, 16, 2, 66913, 0 },
    1148             :   { 1211, 16, 16, 2, 66913, 0 },
    1149             :   { 1232, 16, 16, 2, 66913, 0 },
    1150             :   { 1196, 16, 16, 2, 66913, 0 },
    1151             :   { 1223, 16, 1526, 2, 66913, 0 },
    1152             :   { 1245, 16, 16, 2, 66913, 0 },
    1153             :   { 119, 350, 4013, 19, 13250, 8 },
    1154             :   { 248, 357, 2479, 19, 13250, 8 },
    1155             :   { 363, 364, 3957, 19, 13250, 8 },
    1156             :   { 479, 378, 3845, 19, 13250, 8 },
    1157             :   { 605, 392, 3893, 19, 13250, 8 },
    1158             :   { 723, 406, 3724, 19, 13250, 8 },
    1159             :   { 837, 420, 3780, 19, 13250, 8 },
    1160             :   { 943, 434, 3604, 19, 13250, 8 },
    1161             :   { 1057, 448, 3664, 19, 13250, 8 },
    1162             :   { 1163, 462, 3484, 19, 13250, 8 },
    1163             :   { 9, 476, 3544, 19, 13250, 8 },
    1164             :   { 141, 490, 3364, 19, 13250, 8 },
    1165             :   { 282, 504, 3424, 19, 13250, 8 },
    1166             :   { 408, 518, 3244, 19, 13250, 8 },
    1167             :   { 523, 532, 3304, 19, 13250, 8 },
    1168             :   { 649, 546, 3149, 19, 13250, 8 },
    1169             :   { 768, 16, 3208, 2, 17761, 0 },
    1170             :   { 882, 16, 3078, 2, 17761, 0 },
    1171             :   { 988, 16, 3113, 2, 17761, 0 },
    1172             :   { 1102, 16, 3008, 2, 17761, 0 },
    1173             :   { 59, 16, 3043, 2, 17761, 0 },
    1174             :   { 192, 16, 2938, 2, 17761, 0 },
    1175             :   { 336, 16, 2973, 2, 17761, 0 },
    1176             :   { 456, 16, 2868, 2, 17761, 0 },
    1177             :   { 575, 16, 2903, 2, 17761, 0 },
    1178             :   { 697, 16, 2797, 2, 17761, 0 },
    1179             :   { 804, 16, 2837, 2, 17761, 0 },
    1180             :   { 914, 16, 2363, 2, 17761, 0 },
    1181             :   { 1024, 16, 2411, 2, 17761, 0 },
    1182             :   { 1134, 16, 2384, 2, 17761, 0 },
    1183             :   { 95, 16, 2429, 2, 17761, 0 },
    1184             :   { 224, 16, 2789, 2, 17761, 0 },
    1185             :   { 390, 16, 16, 2, 17761, 0 },
    1186             :   { 125, 16, 16, 2, 17761, 0 },
    1187             :   { 257, 16, 16, 2, 17761, 0 },
    1188             :   { 381, 16, 16, 2, 17761, 0 },
    1189             :   { 122, 353, 1112, 22, 2196, 11 },
    1190             :   { 254, 374, 775, 22, 2196, 11 },
    1191             :   { 378, 402, 314, 22, 2196, 11 },
    1192             :   { 500, 430, 244, 22, 2196, 11 },
    1193             :   { 629, 458, 234, 22, 2196, 11 },
    1194             :   { 744, 486, 224, 22, 2196, 11 },
    1195             :   { 861, 514, 214, 22, 2196, 11 },
    1196             :   { 964, 542, 204, 22, 2196, 11 },
    1197             :   { 1081, 804, 194, 0, 12818, 20 },
    1198             :   { 1184, 807, 184, 0, 12818, 20 },
    1199             :   { 35, 810, 174, 0, 12818, 20 },
    1200             :   { 168, 813, 164, 0, 12818, 20 },
    1201             :   { 312, 816, 154, 0, 12818, 20 },
    1202             :   { 436, 819, 591, 0, 12818, 20 },
    1203             :   { 555, 822, 2447, 0, 12818, 20 },
    1204             :   { 677, 825, 1106, 0, 12818, 20 },
    1205             :   { 128, 16, 1373, 2, 66913, 0 },
    1206             :   { 260, 16, 1371, 2, 66913, 0 },
    1207             :   { 384, 16, 1371, 2, 66913, 0 },
    1208             :   { 506, 16, 1369, 2, 66913, 0 },
    1209             :   { 632, 16, 1369, 2, 66913, 0 },
    1210             :   { 750, 16, 1367, 2, 66913, 0 },
    1211             :   { 864, 16, 1367, 2, 66913, 0 },
    1212             :   { 970, 16, 1365, 2, 66913, 0 },
    1213             :   { 1084, 16, 1365, 2, 66913, 0 },
    1214             :   { 1190, 16, 1363, 2, 66913, 0 },
    1215             :   { 39, 16, 1363, 2, 66913, 0 },
    1216             :   { 176, 16, 1361, 2, 66913, 0 },
    1217             :   { 316, 16, 1359, 2, 66913, 0 },
    1218             :   { 131, 16, 4021, 2, 65585, 0 },
    1219             :   { 269, 16, 4012, 2, 65585, 0 },
    1220             :   { 387, 16, 2490, 2, 65585, 0 },
    1221             :   { 509, 16, 2478, 2, 65585, 0 },
    1222             :   { 635, 16, 3974, 2, 65585, 0 },
    1223             :   { 753, 16, 3956, 2, 65585, 0 },
    1224             :   { 867, 16, 3863, 2, 65585, 0 },
    1225             :   { 973, 16, 3844, 2, 65585, 0 },
    1226             :   { 1087, 16, 3914, 2, 65585, 0 },
    1227             :   { 1193, 16, 3892, 2, 65585, 0 },
    1228             :   { 43, 16, 3745, 2, 65585, 0 },
    1229             :   { 180, 16, 3723, 2, 65585, 0 },
    1230             :   { 320, 16, 3803, 2, 65585, 0 },
    1231             :   { 440, 16, 3779, 2, 65585, 0 },
    1232             :   { 559, 16, 3627, 2, 65585, 0 },
    1233             :   { 681, 16, 3603, 2, 65585, 0 },
    1234             :   { 788, 16, 3687, 2, 65585, 0 },
    1235             :   { 898, 16, 3663, 2, 65585, 0 },
    1236             :   { 1008, 16, 3507, 2, 65585, 0 },
    1237             :   { 1118, 16, 3483, 2, 65585, 0 },
    1238             :   { 79, 16, 3567, 2, 65585, 0 },
    1239             :   { 212, 16, 3543, 2, 65585, 0 },
    1240             :   { 356, 16, 3387, 2, 65585, 0 },
    1241             :   { 472, 16, 3363, 2, 65585, 0 },
    1242             :   { 595, 16, 3447, 2, 65585, 0 },
    1243             :   { 713, 16, 3423, 2, 65585, 0 },
    1244             :   { 824, 16, 3267, 2, 65585, 0 },
    1245             :   { 930, 16, 3243, 2, 65585, 0 },
    1246             :   { 1044, 16, 3327, 2, 65585, 0 },
    1247             :   { 1150, 16, 3303, 2, 65585, 0 },
    1248             :   { 115, 16, 3172, 2, 65585, 0 },
    1249             :   { 244, 16, 3148, 2, 65585, 0 },
    1250             :   { 360, 367, 4015, 29, 5426, 23 },
    1251             :   { 476, 381, 2502, 29, 5426, 23 },
    1252             :   { 602, 395, 3992, 29, 5426, 23 },
    1253             :   { 720, 409, 3882, 29, 5426, 23 },
    1254             :   { 834, 423, 3936, 29, 5426, 23 },
    1255             :   { 940, 437, 3767, 29, 5426, 23 },
    1256             :   { 1054, 451, 3827, 29, 5426, 23 },
    1257             :   { 1160, 465, 3651, 29, 5426, 23 },
    1258             :   { 6, 479, 3711, 29, 5426, 23 },
    1259             :   { 151, 493, 3531, 29, 5426, 23 },
    1260             :   { 278, 507, 3591, 29, 5426, 23 },
    1261             :   { 404, 521, 3411, 29, 5426, 23 },
    1262             :   { 519, 535, 3471, 29, 5426, 23 },
    1263             :   { 645, 549, 3291, 29, 5426, 23 },
    1264             :   { 764, 4007, 3351, 11, 17602, 35 },
    1265             :   { 878, 3948, 3196, 11, 13522, 35 },
    1266             :   { 984, 1080, 3231, 8, 17329, 39 },
    1267             :   { 1098, 1080, 3101, 8, 17329, 39 },
    1268             :   { 55, 1080, 3136, 8, 17329, 39 },
    1269             :   { 204, 1080, 3031, 8, 17329, 39 },
    1270             :   { 332, 1080, 3066, 8, 17329, 39 },
    1271             :   { 452, 1080, 2961, 8, 17329, 39 },
    1272             :   { 571, 1080, 2996, 8, 17329, 39 },
    1273             :   { 693, 1080, 2891, 8, 17329, 39 },
    1274             :   { 800, 1080, 2926, 8, 17329, 39 },
    1275             :   { 910, 1080, 2820, 8, 17329, 39 },
    1276             :   { 1020, 1080, 2858, 8, 17329, 39 },
    1277             :   { 1130, 1080, 2401, 8, 17329, 39 },
    1278             :   { 91, 1080, 2440, 8, 17329, 39 },
    1279             :   { 236, 1080, 2791, 8, 17329, 39 },
    1280             :   { 251, 1339, 1114, 168, 1044, 57 },
    1281             :   { 375, 1319, 347, 168, 1044, 57 },
    1282             :   { 497, 1299, 142, 168, 1044, 57 },
    1283             :   { 626, 1279, 142, 168, 1044, 57 },
    1284             :   { 741, 1259, 142, 168, 1044, 57 },
    1285             :   { 858, 1239, 142, 168, 1044, 57 },
    1286             :   { 961, 1219, 142, 168, 1044, 57 },
    1287             :   { 1078, 1203, 142, 88, 1456, 74 },
    1288             :   { 1181, 1191, 142, 76, 2114, 87 },
    1289             :   { 32, 1179, 142, 76, 2114, 87 },
    1290             :   { 164, 1167, 142, 76, 2114, 87 },
    1291             :   { 308, 1155, 142, 76, 2114, 87 },
    1292             :   { 432, 1143, 142, 76, 2114, 87 },
    1293             :   { 551, 1131, 344, 76, 2114, 87 },
    1294             :   { 673, 1119, 1108, 76, 2114, 87 },
    1295             :   { 491, 2156, 16, 474, 4, 149 },
    1296             :   { 620, 2101, 16, 474, 4, 149 },
    1297             :   { 735, 2046, 16, 474, 4, 149 },
    1298             :   { 852, 1991, 16, 474, 4, 149 },
    1299             :   { 955, 1936, 16, 474, 4, 149 },
    1300             :   { 1072, 1885, 16, 423, 272, 166 },
    1301             :   { 1175, 1838, 16, 376, 512, 181 },
    1302             :   { 26, 1795, 16, 333, 720, 194 },
    1303             :   { 158, 1756, 16, 294, 1186, 205 },
    1304             :   { 301, 1717, 16, 294, 1186, 205 },
    1305             :   { 424, 1678, 16, 294, 1186, 205 },
    1306             :   { 543, 1639, 16, 294, 1186, 205 },
    1307             :   { 665, 1600, 16, 294, 1186, 205 },
    1308             :   { 1219, 4114, 16, 16, 17856, 2 },
    1309             :   { 263, 783, 16, 16, 8946, 5 },
    1310             :   { 503, 786, 16, 16, 8946, 5 },
    1311             :   { 747, 789, 16, 16, 8946, 5 },
    1312             :   { 967, 792, 16, 16, 8946, 5 },
    1313             :   { 1187, 795, 16, 16, 8946, 5 },
    1314             :   { 172, 798, 16, 16, 8946, 5 },
    1315             :   { 366, 1513, 1113, 63, 1570, 28 },
    1316             :   { 482, 4169, 2511, 63, 1570, 28 },
    1317             :   { 611, 1500, 778, 63, 1570, 28 },
    1318             :   { 726, 4156, 770, 63, 1570, 28 },
    1319             :   { 843, 1487, 317, 63, 1570, 28 },
    1320             :   { 946, 4143, 660, 63, 1570, 28 },
    1321             :   { 1063, 1474, 308, 63, 1570, 28 },
    1322             :   { 1166, 4130, 654, 63, 1570, 28 },
    1323             :   { 16, 1461, 302, 63, 1570, 28 },
    1324             :   { 134, 4117, 648, 63, 1570, 28 },
    1325             :   { 289, 1448, 296, 63, 1570, 28 },
    1326             :   { 412, 4101, 642, 63, 1570, 28 },
    1327             :   { 531, 1435, 290, 63, 1570, 28 },
    1328             :   { 653, 4088, 636, 63, 1570, 28 },
    1329             :   { 776, 1424, 284, 52, 1680, 42 },
    1330             :   { 886, 4079, 630, 43, 1872, 48 },
    1331             :   { 996, 1417, 278, 36, 2401, 53 },
    1332             :   { 1106, 4072, 624, 36, 2401, 53 },
    1333             :   { 67, 1410, 272, 36, 2401, 53 },
    1334             :   { 184, 4065, 618, 36, 2401, 53 },
    1335             :   { 344, 1403, 266, 36, 2401, 53 },
    1336             :   { 460, 4058, 612, 36, 2401, 53 },
    1337             :   { 583, 1396, 260, 36, 2401, 53 },
    1338             :   { 701, 4051, 606, 36, 2401, 53 },
    1339             :   { 812, 1389, 254, 36, 2401, 53 },
    1340             :   { 918, 4044, 600, 36, 2401, 53 },
    1341             :   { 1032, 1382, 765, 36, 2401, 53 },
    1342             :   { 1138, 4037, 2455, 36, 2401, 53 },
    1343             :   { 103, 1375, 2474, 36, 2401, 53 },
    1344             :   { 216, 4030, 1107, 36, 2401, 53 },
    1345             :   { 599, 1026, 4018, 212, 5314, 92 },
    1346             :   { 717, 1014, 3953, 212, 5314, 92 },
    1347             :   { 831, 1002, 4002, 212, 5314, 92 },
    1348             :   { 937, 990, 3909, 212, 5314, 92 },
    1349             :   { 1051, 978, 3909, 212, 5314, 92 },
    1350             :   { 1157, 966, 3798, 212, 5314, 92 },
    1351             :   { 3, 954, 3798, 212, 5314, 92 },
    1352             :   { 148, 942, 3682, 212, 5314, 92 },
    1353             :   { 275, 930, 3682, 212, 5314, 92 },
    1354             :   { 401, 918, 3562, 212, 5314, 92 },
    1355             :   { 515, 906, 3562, 212, 5314, 92 },
    1356             :   { 641, 894, 3442, 212, 5314, 92 },
    1357             :   { 760, 1070, 3442, 202, 17506, 99 },
    1358             :   { 874, 1060, 3322, 202, 13426, 99 },
    1359             :   { 980, 1052, 3322, 194, 14226, 105 },
    1360             :   { 1094, 1044, 3226, 194, 13698, 105 },
    1361             :   { 51, 1038, 3226, 188, 14049, 110 },
    1362             :   { 200, 1038, 3131, 188, 14049, 110 },
    1363             :   { 328, 1038, 3131, 188, 14049, 110 },
    1364             :   { 448, 1038, 3061, 188, 14049, 110 },
    1365             :   { 567, 1038, 3061, 188, 14049, 110 },
    1366             :   { 689, 1038, 2991, 188, 14049, 110 },
    1367             :   { 796, 1038, 2991, 188, 14049, 110 },
    1368             :   { 906, 1038, 2921, 188, 14049, 110 },
    1369             :   { 1016, 1038, 2921, 188, 14049, 110 },
    1370             :   { 1126, 1038, 2832, 188, 14049, 110 },
    1371             :   { 87, 1038, 2855, 188, 14049, 110 },
    1372             :   { 232, 1038, 2794, 188, 14049, 110 },
    1373             :   { 828, 2677, 4010, 276, 5170, 114 },
    1374             :   { 934, 2659, 3951, 276, 5170, 114 },
    1375             :   { 1048, 2641, 3951, 276, 5170, 114 },
    1376             :   { 1154, 2623, 3842, 276, 5170, 114 },
    1377             :   { 0, 2605, 3842, 276, 5170, 114 },
    1378             :   { 145, 2587, 3743, 276, 5170, 114 },
    1379             :   { 272, 2569, 3743, 276, 5170, 114 },
    1380             :   { 398, 2551, 3625, 276, 5170, 114 },
    1381             :   { 512, 2533, 3625, 276, 5170, 114 },
    1382             :   { 638, 2515, 3505, 276, 5170, 114 },
    1383             :   { 756, 2773, 3505, 260, 17378, 123 },
    1384             :   { 870, 2757, 3385, 260, 13298, 123 },
    1385             :   { 976, 2743, 3385, 246, 14114, 131 },
    1386             :   { 1090, 2729, 3265, 246, 13586, 131 },
    1387             :   { 47, 2717, 3265, 234, 13954, 138 },
    1388             :   { 196, 2705, 3170, 234, 13778, 138 },
    1389             :   { 324, 2695, 3170, 224, 13873, 144 },
    1390             :   { 444, 2695, 3099, 224, 13873, 144 },
    1391             :   { 563, 2695, 3099, 224, 13873, 144 },
    1392             :   { 685, 2695, 3029, 224, 13873, 144 },
    1393             :   { 792, 2695, 3029, 224, 13873, 144 },
    1394             :   { 902, 2695, 2959, 224, 13873, 144 },
    1395             :   { 1012, 2695, 2959, 224, 13873, 144 },
    1396             :   { 1122, 2695, 2856, 224, 13873, 144 },
    1397             :   { 83, 2695, 2856, 224, 13873, 144 },
    1398             :   { 228, 2695, 2795, 224, 13873, 144 },
    1399             :   { 369, 360, 2509, 22, 1956, 11 },
    1400             :   { 614, 388, 583, 22, 1956, 11 },
    1401             :   { 846, 416, 756, 22, 1956, 11 },
    1402             :   { 1066, 444, 747, 22, 1956, 11 },
    1403             :   { 19, 472, 738, 22, 1956, 11 },
    1404             :   { 293, 500, 729, 22, 1956, 11 },
    1405             :   { 535, 528, 720, 22, 1956, 11 },
    1406             :   { 780, 3839, 711, 3, 2336, 16 },
    1407             :   { 1000, 562, 702, 0, 8898, 20 },
    1408             :   { 71, 565, 693, 0, 8898, 20 },
    1409             :   { 348, 568, 684, 0, 8898, 20 },
    1410             :   { 587, 571, 675, 0, 8898, 20 },
    1411             :   { 816, 574, 666, 0, 8898, 20 },
    1412             :   { 1036, 577, 2460, 0, 8898, 20 },
    1413             :   { 107, 580, 2468, 0, 8898, 20 },
    1414             :   { 608, 2343, 2488, 148, 900, 57 },
    1415             :   { 840, 2323, 588, 148, 900, 57 },
    1416             :   { 1060, 2303, 588, 148, 900, 57 },
    1417             :   { 13, 2283, 588, 148, 900, 57 },
    1418             :   { 286, 2263, 588, 148, 900, 57 },
    1419             :   { 527, 2243, 588, 148, 900, 57 },
    1420             :   { 772, 2225, 588, 130, 1328, 66 },
    1421             :   { 992, 2211, 588, 116, 1776, 81 },
    1422             :   { 63, 1588, 588, 104, 2034, 87 },
    1423             :   { 340, 1576, 588, 104, 2034, 87 },
    1424             :   { 579, 1564, 588, 104, 2034, 87 },
    1425             :   { 808, 1552, 588, 104, 2034, 87 },
    1426             :   { 1028, 1540, 588, 104, 2034, 87 },
    1427             :   { 99, 1528, 2382, 104, 2034, 87 },
    1428             : };
    1429             : 
    1430             : extern const MCPhysReg ARMRegUnitRoots[][2] = {
    1431             :   { ARM::APSR },
    1432             :   { ARM::APSR_NZCV },
    1433             :   { ARM::CPSR },
    1434             :   { ARM::FPEXC },
    1435             :   { ARM::FPINST },
    1436             :   { ARM::FPSCR, ARM::FPSCR_NZCV },
    1437             :   { ARM::FPSID },
    1438             :   { ARM::ITSTATE },
    1439             :   { ARM::LR },
    1440             :   { ARM::PC },
    1441             :   { ARM::SP },
    1442             :   { ARM::SPSR },
    1443             :   { ARM::S0 },
    1444             :   { ARM::S1 },
    1445             :   { ARM::S2 },
    1446             :   { ARM::S3 },
    1447             :   { ARM::S4 },
    1448             :   { ARM::S5 },
    1449             :   { ARM::S6 },
    1450             :   { ARM::S7 },
    1451             :   { ARM::S8 },
    1452             :   { ARM::S9 },
    1453             :   { ARM::S10 },
    1454             :   { ARM::S11 },
    1455             :   { ARM::S12 },
    1456             :   { ARM::S13 },
    1457             :   { ARM::S14 },
    1458             :   { ARM::S15 },
    1459             :   { ARM::S16 },
    1460             :   { ARM::S17 },
    1461             :   { ARM::S18 },
    1462             :   { ARM::S19 },
    1463             :   { ARM::S20 },
    1464             :   { ARM::S21 },
    1465             :   { ARM::S22 },
    1466             :   { ARM::S23 },
    1467             :   { ARM::S24 },
    1468             :   { ARM::S25 },
    1469             :   { ARM::S26 },
    1470             :   { ARM::S27 },
    1471             :   { ARM::S28 },
    1472             :   { ARM::S29 },
    1473             :   { ARM::S30 },
    1474             :   { ARM::S31 },
    1475             :   { ARM::D16 },
    1476             :   { ARM::D17 },
    1477             :   { ARM::D18 },
    1478             :   { ARM::D19 },
    1479             :   { ARM::D20 },
    1480             :   { ARM::D21 },
    1481             :   { ARM::D22 },
    1482             :   { ARM::D23 },
    1483             :   { ARM::D24 },
    1484             :   { ARM::D25 },
    1485             :   { ARM::D26 },
    1486             :   { ARM::D27 },
    1487             :   { ARM::D28 },
    1488             :   { ARM::D29 },
    1489             :   { ARM::D30 },
    1490             :   { ARM::D31 },
    1491             :   { ARM::FPINST2 },
    1492             :   { ARM::MVFR0 },
    1493             :   { ARM::MVFR1 },
    1494             :   { ARM::MVFR2 },
    1495             :   { ARM::R0 },
    1496             :   { ARM::R1 },
    1497             :   { ARM::R2 },
    1498             :   { ARM::R3 },
    1499             :   { ARM::R4 },
    1500             :   { ARM::R5 },
    1501             :   { ARM::R6 },
    1502             :   { ARM::R7 },
    1503             :   { ARM::R8 },
    1504             :   { ARM::R9 },
    1505             :   { ARM::R10 },
    1506             :   { ARM::R11 },
    1507             :   { ARM::R12 },
    1508             : };
    1509             : 
    1510             : namespace {     // Register classes...
    1511             :   // SPR Register Class...
    1512             :   const MCPhysReg SPR[] = {
    1513             :     ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S28, ARM::S29, ARM::S30, ARM::S31, 
    1514             :   };
    1515             : 
    1516             :   // SPR Bit set.
    1517             :   const uint8_t SPRBits[] = {
    1518             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, 
    1519             :   };
    1520             : 
    1521             :   // GPR Register Class...
    1522             :   const MCPhysReg GPR[] = {
    1523             :     ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC, 
    1524             :   };
    1525             : 
    1526             :   // GPR Bit set.
    1527             :   const uint8_t GPRBits[] = {
    1528             :     0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 
    1529             :   };
    1530             : 
    1531             :   // GPRwithAPSR Register Class...
    1532             :   const MCPhysReg GPRwithAPSR[] = {
    1533             :     ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::APSR_NZCV, 
    1534             :   };
    1535             : 
    1536             :   // GPRwithAPSR Bit set.
    1537             :   const uint8_t GPRwithAPSRBits[] = {
    1538             :     0x04, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 
    1539             :   };
    1540             : 
    1541             :   // SPR_8 Register Class...
    1542             :   const MCPhysReg SPR_8[] = {
    1543             :     ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, 
    1544             :   };
    1545             : 
    1546             :   // SPR_8 Bit set.
    1547             :   const uint8_t SPR_8Bits[] = {
    1548             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 
    1549             :   };
    1550             : 
    1551             :   // GPRnopc Register Class...
    1552             :   const MCPhysReg GPRnopc[] = {
    1553             :     ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, 
    1554             :   };
    1555             : 
    1556             :   // GPRnopc Bit set.
    1557             :   const uint8_t GPRnopcBits[] = {
    1558             :     0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 
    1559             :   };
    1560             : 
    1561             :   // rGPR Register Class...
    1562             :   const MCPhysReg rGPR[] = {
    1563             :     ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, 
    1564             :   };
    1565             : 
    1566             :   // rGPR Bit set.
    1567             :   const uint8_t rGPRBits[] = {
    1568             :     0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 
    1569             :   };
    1570             : 
    1571             :   // tGPRwithpc Register Class...
    1572             :   const MCPhysReg tGPRwithpc[] = {
    1573             :     ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::PC, 
    1574             :   };
    1575             : 
    1576             :   // tGPRwithpc Bit set.
    1577             :   const uint8_t tGPRwithpcBits[] = {
    1578             :     0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 
    1579             :   };
    1580             : 
    1581             :   // hGPR Register Class...
    1582             :   const MCPhysReg hGPR[] = {
    1583             :     ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC, 
    1584             :   };
    1585             : 
    1586             :   // hGPR Bit set.
    1587             :   const uint8_t hGPRBits[] = {
    1588             :     0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 
    1589             :   };
    1590             : 
    1591             :   // tGPR Register Class...
    1592             :   const MCPhysReg tGPR[] = {
    1593             :     ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, 
    1594             :   };
    1595             : 
    1596             :   // tGPR Bit set.
    1597             :   const uint8_t tGPRBits[] = {
    1598             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 
    1599             :   };
    1600             : 
    1601             :   // GPRnopc_and_hGPR Register Class...
    1602             :   const MCPhysReg GPRnopc_and_hGPR[] = {
    1603             :     ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, 
    1604             :   };
    1605             : 
    1606             :   // GPRnopc_and_hGPR Bit set.
    1607             :   const uint8_t GPRnopc_and_hGPRBits[] = {
    1608             :     0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 
    1609             :   };
    1610             : 
    1611             :   // hGPR_and_rGPR Register Class...
    1612             :   const MCPhysReg hGPR_and_rGPR[] = {
    1613             :     ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, 
    1614             :   };
    1615             : 
    1616             :   // hGPR_and_rGPR Bit set.
    1617             :   const uint8_t hGPR_and_rGPRBits[] = {
    1618             :     0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 
    1619             :   };
    1620             : 
    1621             :   // tcGPR Register Class...
    1622             :   const MCPhysReg tcGPR[] = {
    1623             :     ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12, 
    1624             :   };
    1625             : 
    1626             :   // tcGPR Bit set.
    1627             :   const uint8_t tcGPRBits[] = {
    1628             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x40, 
    1629             :   };
    1630             : 
    1631             :   // tGPR_and_tcGPR Register Class...
    1632             :   const MCPhysReg tGPR_and_tcGPR[] = {
    1633             :     ARM::R0, ARM::R1, ARM::R2, ARM::R3, 
    1634             :   };
    1635             : 
    1636             :   // tGPR_and_tcGPR Bit set.
    1637             :   const uint8_t tGPR_and_tcGPRBits[] = {
    1638             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 
    1639             :   };
    1640             : 
    1641             :   // CCR Register Class...
    1642             :   const MCPhysReg CCR[] = {
    1643             :     ARM::CPSR, 
    1644             :   };
    1645             : 
    1646             :   // CCR Bit set.
    1647             :   const uint8_t CCRBits[] = {
    1648             :     0x08, 
    1649             :   };
    1650             : 
    1651             :   // GPRsp Register Class...
    1652             :   const MCPhysReg GPRsp[] = {
    1653             :     ARM::SP, 
    1654             :   };
    1655             : 
    1656             :   // GPRsp Bit set.
    1657             :   const uint8_t GPRspBits[] = {
    1658             :     0x00, 0x10, 
    1659             :   };
    1660             : 
    1661             :   // hGPR_and_tGPRwithpc Register Class...
    1662             :   const MCPhysReg hGPR_and_tGPRwithpc[] = {
    1663             :     ARM::PC, 
    1664             :   };
    1665             : 
    1666             :   // hGPR_and_tGPRwithpc Bit set.
    1667             :   const uint8_t hGPR_and_tGPRwithpcBits[] = {
    1668             :     0x00, 0x08, 
    1669             :   };
    1670             : 
    1671             :   // hGPR_and_tcGPR Register Class...
    1672             :   const MCPhysReg hGPR_and_tcGPR[] = {
    1673             :     ARM::R12, 
    1674             :   };
    1675             : 
    1676             :   // hGPR_and_tcGPR Bit set.
    1677             :   const uint8_t hGPR_and_tcGPRBits[] = {
    1678             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 
    1679             :   };
    1680             : 
    1681             :   // DPR Register Class...
    1682             :   const MCPhysReg DPR[] = {
    1683             :     ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, 
    1684             :   };
    1685             : 
    1686             :   // DPR Bit set.
    1687             :   const uint8_t DPRBits[] = {
    1688             :     0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 
    1689             :   };
    1690             : 
    1691             :   // DPR_VFP2 Register Class...
    1692             :   const MCPhysReg DPR_VFP2[] = {
    1693             :     ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, 
    1694             :   };
    1695             : 
    1696             :   // DPR_VFP2 Bit set.
    1697             :   const uint8_t DPR_VFP2Bits[] = {
    1698             :     0x00, 0xc0, 0xff, 0x3f, 
    1699             :   };
    1700             : 
    1701             :   // DPR_8 Register Class...
    1702             :   const MCPhysReg DPR_8[] = {
    1703             :     ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, 
    1704             :   };
    1705             : 
    1706             :   // DPR_8 Bit set.
    1707             :   const uint8_t DPR_8Bits[] = {
    1708             :     0x00, 0xc0, 0x3f, 
    1709             :   };
    1710             : 
    1711             :   // GPRPair Register Class...
    1712             :   const MCPhysReg GPRPair[] = {
    1713             :     ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, ARM::R8_R9, ARM::R10_R11, ARM::R12_SP, 
    1714             :   };
    1715             : 
    1716             :   // GPRPair Bit set.
    1717             :   const uint8_t GPRPairBits[] = {
    1718             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 
    1719             :   };
    1720             : 
    1721             :   // GPRPair_with_gsub_1_in_rGPR Register Class...
    1722             :   const MCPhysReg GPRPair_with_gsub_1_in_rGPR[] = {
    1723             :     ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, ARM::R8_R9, ARM::R10_R11, 
    1724             :   };
    1725             : 
    1726             :   // GPRPair_with_gsub_1_in_rGPR Bit set.
    1727             :   const uint8_t GPRPair_with_gsub_1_in_rGPRBits[] = {
    1728             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 
    1729             :   };
    1730             : 
    1731             :   // GPRPair_with_gsub_0_in_tGPR Register Class...
    1732             :   const MCPhysReg GPRPair_with_gsub_0_in_tGPR[] = {
    1733             :     ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 
    1734             :   };
    1735             : 
    1736             :   // GPRPair_with_gsub_0_in_tGPR Bit set.
    1737             :   const uint8_t GPRPair_with_gsub_0_in_tGPRBits[] = {
    1738             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 
    1739             :   };
    1740             : 
    1741             :   // GPRPair_with_gsub_0_in_hGPR Register Class...
    1742             :   const MCPhysReg GPRPair_with_gsub_0_in_hGPR[] = {
    1743             :     ARM::R8_R9, ARM::R10_R11, ARM::R12_SP, 
    1744             :   };
    1745             : 
    1746             :   // GPRPair_with_gsub_0_in_hGPR Bit set.
    1747             :   const uint8_t GPRPair_with_gsub_0_in_hGPRBits[] = {
    1748             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 
    1749             :   };
    1750             : 
    1751             :   // GPRPair_with_gsub_0_in_tcGPR Register Class...
    1752             :   const MCPhysReg GPRPair_with_gsub_0_in_tcGPR[] = {
    1753             :     ARM::R0_R1, ARM::R2_R3, ARM::R12_SP, 
    1754             :   };
    1755             : 
    1756             :   // GPRPair_with_gsub_0_in_tcGPR Bit set.
    1757             :   const uint8_t GPRPair_with_gsub_0_in_tcGPRBits[] = {
    1758             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 
    1759             :   };
    1760             : 
    1761             :   // GPRPair_with_gsub_1_in_hGPR_and_rGPR Register Class...
    1762             :   const MCPhysReg GPRPair_with_gsub_1_in_hGPR_and_rGPR[] = {
    1763             :     ARM::R8_R9, ARM::R10_R11, 
    1764             :   };
    1765             : 
    1766             :   // GPRPair_with_gsub_1_in_hGPR_and_rGPR Bit set.
    1767             :   const uint8_t GPRPair_with_gsub_1_in_hGPR_and_rGPRBits[] = {
    1768             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 
    1769             :   };
    1770             : 
    1771             :   // GPRPair_with_gsub_1_in_tcGPR Register Class...
    1772             :   const MCPhysReg GPRPair_with_gsub_1_in_tcGPR[] = {
    1773             :     ARM::R0_R1, ARM::R2_R3, 
    1774             :   };
    1775             : 
    1776             :   // GPRPair_with_gsub_1_in_tcGPR Bit set.
    1777             :   const uint8_t GPRPair_with_gsub_1_in_tcGPRBits[] = {
    1778             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 
    1779             :   };
    1780             : 
    1781             :   // GPRPair_with_gsub_1_in_GPRsp Register Class...
    1782             :   const MCPhysReg GPRPair_with_gsub_1_in_GPRsp[] = {
    1783             :     ARM::R12_SP, 
    1784             :   };
    1785             : 
    1786             :   // GPRPair_with_gsub_1_in_GPRsp Bit set.
    1787             :   const uint8_t GPRPair_with_gsub_1_in_GPRspBits[] = {
    1788             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 
    1789             :   };
    1790             : 
    1791             :   // DPairSpc Register Class...
    1792             :   const MCPhysReg DPairSpc[] = {
    1793             :     ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, ARM::D28_D30, ARM::D29_D31, 
    1794             :   };
    1795             : 
    1796             :   // DPairSpc Bit set.
    1797             :   const uint8_t DPairSpcBits[] = {
    1798             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f, 
    1799             :   };
    1800             : 
    1801             :   // DPairSpc_with_ssub_0 Register Class...
    1802             :   const MCPhysReg DPairSpc_with_ssub_0[] = {
    1803             :     ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 
    1804             :   };
    1805             : 
    1806             :   // DPairSpc_with_ssub_0 Bit set.
    1807             :   const uint8_t DPairSpc_with_ssub_0Bits[] = {
    1808             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 
    1809             :   };
    1810             : 
    1811             :   // DPairSpc_with_ssub_4 Register Class...
    1812             :   const MCPhysReg DPairSpc_with_ssub_4[] = {
    1813             :     ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, 
    1814             :   };
    1815             : 
    1816             :   // DPairSpc_with_ssub_4 Bit set.
    1817             :   const uint8_t DPairSpc_with_ssub_4Bits[] = {
    1818             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f, 
    1819             :   };
    1820             : 
    1821             :   // DPairSpc_with_dsub_0_in_DPR_8 Register Class...
    1822             :   const MCPhysReg DPairSpc_with_dsub_0_in_DPR_8[] = {
    1823             :     ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 
    1824             :   };
    1825             : 
    1826             :   // DPairSpc_with_dsub_0_in_DPR_8 Bit set.
    1827             :   const uint8_t DPairSpc_with_dsub_0_in_DPR_8Bits[] = {
    1828             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 
    1829             :   };
    1830             : 
    1831             :   // DPairSpc_with_dsub_2_in_DPR_8 Register Class...
    1832             :   const MCPhysReg DPairSpc_with_dsub_2_in_DPR_8[] = {
    1833             :     ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, 
    1834             :   };
    1835             : 
    1836             :   // DPairSpc_with_dsub_2_in_DPR_8 Bit set.
    1837             :   const uint8_t DPairSpc_with_dsub_2_in_DPR_8Bits[] = {
    1838             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, 
    1839             :   };
    1840             : 
    1841             :   // DPair Register Class...
    1842             :   const MCPhysReg DPair[] = {
    1843             :     ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, ARM::Q15, 
    1844             :   };
    1845             : 
    1846             :   // DPair Bit set.
    1847             :   const uint8_t DPairBits[] = {
    1848             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 
    1849             :   };
    1850             : 
    1851             :   // DPair_with_ssub_0 Register Class...
    1852             :   const MCPhysReg DPair_with_ssub_0[] = {
    1853             :     ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, 
    1854             :   };
    1855             : 
    1856             :   // DPair_with_ssub_0 Bit set.
    1857             :   const uint8_t DPair_with_ssub_0Bits[] = {
    1858             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, 
    1859             :   };
    1860             : 
    1861             :   // QPR Register Class...
    1862             :   const MCPhysReg QPR[] = {
    1863             :     ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, 
    1864             :   };
    1865             : 
    1866             :   // QPR Bit set.
    1867             :   const uint8_t QPRBits[] = {
    1868             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 
    1869             :   };
    1870             : 
    1871             :   // DPair_with_ssub_2 Register Class...
    1872             :   const MCPhysReg DPair_with_ssub_2[] = {
    1873             :     ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, 
    1874             :   };
    1875             : 
    1876             :   // DPair_with_ssub_2 Bit set.
    1877             :   const uint8_t DPair_with_ssub_2Bits[] = {
    1878             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, 
    1879             :   };
    1880             : 
    1881             :   // DPair_with_dsub_0_in_DPR_8 Register Class...
    1882             :   const MCPhysReg DPair_with_dsub_0_in_DPR_8[] = {
    1883             :     ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, 
    1884             :   };
    1885             : 
    1886             :   // DPair_with_dsub_0_in_DPR_8 Bit set.
    1887             :   const uint8_t DPair_with_dsub_0_in_DPR_8Bits[] = {
    1888             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 
    1889             :   };
    1890             : 
    1891             :   // QPR_VFP2 Register Class...
    1892             :   const MCPhysReg QPR_VFP2[] = {
    1893             :     ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 
    1894             :   };
    1895             : 
    1896             :   // QPR_VFP2 Bit set.
    1897             :   const uint8_t QPR_VFP2Bits[] = {
    1898             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 
    1899             :   };
    1900             : 
    1901             :   // DPair_with_dsub_1_in_DPR_8 Register Class...
    1902             :   const MCPhysReg DPair_with_dsub_1_in_DPR_8[] = {
    1903             :     ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, 
    1904             :   };
    1905             : 
    1906             :   // DPair_with_dsub_1_in_DPR_8 Bit set.
    1907             :   const uint8_t DPair_with_dsub_1_in_DPR_8Bits[] = {
    1908             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 
    1909             :   };
    1910             : 
    1911             :   // QPR_8 Register Class...
    1912             :   const MCPhysReg QPR_8[] = {
    1913             :     ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 
    1914             :   };
    1915             : 
    1916             :   // QPR_8 Bit set.
    1917             :   const uint8_t QPR_8Bits[] = {
    1918             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 
    1919             :   };
    1920             : 
    1921             :   // DTriple Register Class...
    1922             :   const MCPhysReg DTriple[] = {
    1923             :     ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, ARM::D15_D16_D17, ARM::D16_D17_D18, ARM::D17_D18_D19, ARM::D18_D19_D20, ARM::D19_D20_D21, ARM::D20_D21_D22, ARM::D21_D22_D23, ARM::D22_D23_D24, ARM::D23_D24_D25, ARM::D24_D25_D26, ARM::D25_D26_D27, ARM::D26_D27_D28, ARM::D27_D28_D29, ARM::D28_D29_D30, ARM::D29_D30_D31, 
    1924             :   };
    1925             : 
    1926             :   // DTriple Bit set.
    1927             :   const uint8_t DTripleBits[] = {
    1928             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x3f, 
    1929             :   };
    1930             : 
    1931             :   // DTripleSpc Register Class...
    1932             :   const MCPhysReg DTripleSpc[] = {
    1933             :     ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, ARM::D16_D18_D20, ARM::D17_D19_D21, ARM::D18_D20_D22, ARM::D19_D21_D23, ARM::D20_D22_D24, ARM::D21_D23_D25, ARM::D22_D24_D26, ARM::D23_D25_D27, ARM::D24_D26_D28, ARM::D25_D27_D29, ARM::D26_D28_D30, ARM::D27_D29_D31, 
    1934             :   };
    1935             : 
    1936             :   // DTripleSpc Bit set.
    1937             :   const uint8_t DTripleSpcBits[] = {
    1938             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03, 
    1939             :   };
    1940             : 
    1941             :   // DTripleSpc_with_ssub_0 Register Class...
    1942             :   const MCPhysReg DTripleSpc_with_ssub_0[] = {
    1943             :     ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, 
    1944             :   };
    1945             : 
    1946             :   // DTripleSpc_with_ssub_0 Bit set.
    1947             :   const uint8_t DTripleSpc_with_ssub_0Bits[] = {
    1948             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 
    1949             :   };
    1950             : 
    1951             :   // DTriple_with_ssub_0 Register Class...
    1952             :   const MCPhysReg DTriple_with_ssub_0[] = {
    1953             :     ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, ARM::D15_D16_D17, 
    1954             :   };
    1955             : 
    1956             :   // DTriple_with_ssub_0 Bit set.
    1957             :   const uint8_t DTriple_with_ssub_0Bits[] = {
    1958             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 
    1959             :   };
    1960             : 
    1961             :   // DTriple_with_qsub_0_in_QPR Register Class...
    1962             :   const MCPhysReg DTriple_with_qsub_0_in_QPR[] = {
    1963             :     ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, ARM::D14_D15_D16, ARM::D16_D17_D18, ARM::D18_D19_D20, ARM::D20_D21_D22, ARM::D22_D23_D24, ARM::D24_D25_D26, ARM::D26_D27_D28, ARM::D28_D29_D30, 
    1964             :   };
    1965             : 
    1966             :   // DTriple_with_qsub_0_in_QPR Bit set.
    1967             :   const uint8_t DTriple_with_qsub_0_in_QPRBits[] = {
    1968             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x55, 0x15, 
    1969             :   };
    1970             : 
    1971             :   // DTriple_with_ssub_2 Register Class...
    1972             :   const MCPhysReg DTriple_with_ssub_2[] = {
    1973             :     ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, 
    1974             :   };
    1975             : 
    1976             :   // DTriple_with_ssub_2 Bit set.
    1977             :   const uint8_t DTriple_with_ssub_2Bits[] = {
    1978             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x7f, 
    1979             :   };
    1980             : 
    1981             :   // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
    1982             :   const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
    1983             :     ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, ARM::D15_D16_D17, ARM::D17_D18_D19, ARM::D19_D20_D21, ARM::D21_D22_D23, ARM::D23_D24_D25, ARM::D25_D26_D27, ARM::D27_D28_D29, ARM::D29_D30_D31, 
    1984             :   };
    1985             : 
    1986             :   // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
    1987             :   const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
    1988             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0x2a, 
    1989             :   };
    1990             : 
    1991             :   // DTripleSpc_with_ssub_4 Register Class...
    1992             :   const MCPhysReg DTripleSpc_with_ssub_4[] = {
    1993             :     ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, 
    1994             :   };
    1995             : 
    1996             :   // DTripleSpc_with_ssub_4 Bit set.
    1997             :   const uint8_t DTripleSpc_with_ssub_4Bits[] = {
    1998             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, 
    1999             :   };
    2000             : 
    2001             :   // DTriple_with_ssub_4 Register Class...
    2002             :   const MCPhysReg DTriple_with_ssub_4[] = {
    2003             :     ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, 
    2004             :   };
    2005             : 
    2006             :   // DTriple_with_ssub_4 Bit set.
    2007             :   const uint8_t DTriple_with_ssub_4Bits[] = {
    2008             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x3f, 
    2009             :   };
    2010             : 
    2011             :   // DTripleSpc_with_ssub_8 Register Class...
    2012             :   const MCPhysReg DTripleSpc_with_ssub_8[] = {
    2013             :     ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, 
    2014             :   };
    2015             : 
    2016             :   // DTripleSpc_with_ssub_8 Bit set.
    2017             :   const uint8_t DTripleSpc_with_ssub_8Bits[] = {
    2018             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03, 
    2019             :   };
    2020             : 
    2021             :   // DTripleSpc_with_dsub_0_in_DPR_8 Register Class...
    2022             :   const MCPhysReg DTripleSpc_with_dsub_0_in_DPR_8[] = {
    2023             :     ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, 
    2024             :   };
    2025             : 
    2026             :   // DTripleSpc_with_dsub_0_in_DPR_8 Bit set.
    2027             :   const uint8_t DTripleSpc_with_dsub_0_in_DPR_8Bits[] = {
    2028             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
    2029             :   };
    2030             : 
    2031             :   // DTriple_with_dsub_0_in_DPR_8 Register Class...
    2032             :   const MCPhysReg DTriple_with_dsub_0_in_DPR_8[] = {
    2033             :     ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, 
    2034             :   };
    2035             : 
    2036             :   // DTriple_with_dsub_0_in_DPR_8 Bit set.
    2037             :   const uint8_t DTriple_with_dsub_0_in_DPR_8Bits[] = {
    2038             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 
    2039             :   };
    2040             : 
    2041             :   // DTriple_with_qsub_0_in_QPR_VFP2 Register Class...
    2042             :   const MCPhysReg DTriple_with_qsub_0_in_QPR_VFP2[] = {
    2043             :     ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, ARM::D14_D15_D16, 
    2044             :   };
    2045             : 
    2046             :   // DTriple_with_qsub_0_in_QPR_VFP2 Bit set.
    2047             :   const uint8_t DTriple_with_qsub_0_in_QPR_VFP2Bits[] = {
    2048             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 
    2049             :   };
    2050             : 
    2051             :   // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
    2052             :   const MCPhysReg DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
    2053             :     ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, ARM::D15_D16_D17, 
    2054             :   };
    2055             : 
    2056             :   // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
    2057             :   const uint8_t DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
    2058             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 
    2059             :   };
    2060             : 
    2061             :   // DTriple_with_dsub_1_in_DPR_8 Register Class...
    2062             :   const MCPhysReg DTriple_with_dsub_1_in_DPR_8[] = {
    2063             :     ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, 
    2064             :   };
    2065             : 
    2066             :   // DTriple_with_dsub_1_in_DPR_8 Bit set.
    2067             :   const uint8_t DTriple_with_dsub_1_in_DPR_8Bits[] = {
    2068             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 
    2069             :   };
    2070             : 
    2071             :   // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Register Class...
    2072             :   const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2[] = {
    2073             :     ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, 
    2074             :   };
    2075             : 
    2076             :   // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Bit set.
    2077             :   const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits[] = {
    2078             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x2a, 
    2079             :   };
    2080             : 
    2081             :   // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR Register Class...
    2082             :   const MCPhysReg DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR[] = {
    2083             :     ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, 
    2084             :   };
    2085             : 
    2086             :   // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR Bit set.
    2087             :   const uint8_t DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRBits[] = {
    2088             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x15, 
    2089             :   };
    2090             : 
    2091             :   // DTripleSpc_with_dsub_2_in_DPR_8 Register Class...
    2092             :   const MCPhysReg DTripleSpc_with_dsub_2_in_DPR_8[] = {
    2093             :     ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, 
    2094             :   };
    2095             : 
    2096             :   // DTripleSpc_with_dsub_2_in_DPR_8 Bit set.
    2097             :   const uint8_t DTripleSpc_with_dsub_2_in_DPR_8Bits[] = {
    2098             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 
    2099             :   };
    2100             : 
    2101             :   // DTriple_with_dsub_2_in_DPR_8 Register Class...
    2102             :   const MCPhysReg DTriple_with_dsub_2_in_DPR_8[] = {
    2103             :     ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, 
    2104             :   };
    2105             : 
    2106             :   // DTriple_with_dsub_2_in_DPR_8 Bit set.
    2107             :   const uint8_t DTriple_with_dsub_2_in_DPR_8Bits[] = {
    2108             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 
    2109             :   };
    2110             : 
    2111             :   // DTripleSpc_with_dsub_4_in_DPR_8 Register Class...
    2112             :   const MCPhysReg DTripleSpc_with_dsub_4_in_DPR_8[] = {
    2113             :     ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, 
    2114             :   };
    2115             : 
    2116             :   // DTripleSpc_with_dsub_4_in_DPR_8 Bit set.
    2117             :   const uint8_t DTripleSpc_with_dsub_4_in_DPR_8Bits[] = {
    2118             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, 
    2119             :   };
    2120             : 
    2121             :   // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
    2122             :   const MCPhysReg DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
    2123             :     ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, 
    2124             :   };
    2125             : 
    2126             :   // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
    2127             :   const uint8_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
    2128             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 
    2129             :   };
    2130             : 
    2131             :   // DTriple_with_qsub_0_in_QPR_8 Register Class...
    2132             :   const MCPhysReg DTriple_with_qsub_0_in_QPR_8[] = {
    2133             :     ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, 
    2134             :   };
    2135             : 
    2136             :   // DTriple_with_qsub_0_in_QPR_8 Bit set.
    2137             :   const uint8_t DTriple_with_qsub_0_in_QPR_8Bits[] = {
    2138             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 
    2139             :   };
    2140             : 
    2141             :   // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR Register Class...
    2142             :   const MCPhysReg DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR[] = {
    2143             :     ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, 
    2144             :   };
    2145             : 
    2146             :   // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR Bit set.
    2147             :   const uint8_t DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits[] = {
    2148             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 
    2149             :   };
    2150             : 
    2151             :   // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class...
    2152             :   const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = {
    2153             :     ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, 
    2154             :   };
    2155             : 
    2156             :   // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set.
    2157             :   const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = {
    2158             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 
    2159             :   };
    2160             : 
    2161             :   // DQuadSpc Register Class...
    2162             :   const MCPhysReg DQuadSpc[] = {
    2163             :     ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, ARM::D16_D18_D20, ARM::D17_D19_D21, ARM::D18_D20_D22, ARM::D19_D21_D23, ARM::D20_D22_D24, ARM::D21_D23_D25, ARM::D22_D24_D26, ARM::D23_D25_D27, ARM::D24_D26_D28, ARM::D25_D27_D29, ARM::D26_D28_D30, ARM::D27_D29_D31, 
    2164             :   };
    2165             : 
    2166             :   // DQuadSpc Bit set.
    2167             :   const uint8_t DQuadSpcBits[] = {
    2168             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03, 
    2169             :   };
    2170             : 
    2171             :   // DQuadSpc_with_ssub_0 Register Class...
    2172             :   const MCPhysReg DQuadSpc_with_ssub_0[] = {
    2173             :     ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, 
    2174             :   };
    2175             : 
    2176             :   // DQuadSpc_with_ssub_0 Bit set.
    2177             :   const uint8_t DQuadSpc_with_ssub_0Bits[] = {
    2178             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 
    2179             :   };
    2180             : 
    2181             :   // DQuadSpc_with_ssub_4 Register Class...
    2182             :   const MCPhysReg DQuadSpc_with_ssub_4[] = {
    2183             :     ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, 
    2184             :   };
    2185             : 
    2186             :   // DQuadSpc_with_ssub_4 Bit set.
    2187             :   const uint8_t DQuadSpc_with_ssub_4Bits[] = {
    2188             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, 
    2189             :   };
    2190             : 
    2191             :   // DQuadSpc_with_ssub_8 Register Class...
    2192             :   const MCPhysReg DQuadSpc_with_ssub_8[] = {
    2193             :     ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, 
    2194             :   };
    2195             : 
    2196             :   // DQuadSpc_with_ssub_8 Bit set.
    2197             :   const uint8_t DQuadSpc_with_ssub_8Bits[] = {
    2198             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03, 
    2199             :   };
    2200             : 
    2201             :   // DQuadSpc_with_dsub_0_in_DPR_8 Register Class...
    2202             :   const MCPhysReg DQuadSpc_with_dsub_0_in_DPR_8[] = {
    2203             :     ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, 
    2204             :   };
    2205             : 
    2206             :   // DQuadSpc_with_dsub_0_in_DPR_8 Bit set.
    2207             :   const uint8_t DQuadSpc_with_dsub_0_in_DPR_8Bits[] = {
    2208             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
    2209             :   };
    2210             : 
    2211             :   // DQuadSpc_with_dsub_2_in_DPR_8 Register Class...
    2212             :   const MCPhysReg DQuadSpc_with_dsub_2_in_DPR_8[] = {
    2213             :     ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, 
    2214             :   };
    2215             : 
    2216             :   // DQuadSpc_with_dsub_2_in_DPR_8 Bit set.
    2217             :   const uint8_t DQuadSpc_with_dsub_2_in_DPR_8Bits[] = {
    2218             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 
    2219             :   };
    2220             : 
    2221             :   // DQuadSpc_with_dsub_4_in_DPR_8 Register Class...
    2222             :   const MCPhysReg DQuadSpc_with_dsub_4_in_DPR_8[] = {
    2223             :     ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, 
    2224             :   };
    2225             : 
    2226             :   // DQuadSpc_with_dsub_4_in_DPR_8 Bit set.
    2227             :   const uint8_t DQuadSpc_with_dsub_4_in_DPR_8Bits[] = {
    2228             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, 
    2229             :   };
    2230             : 
    2231             :   // DQuad Register Class...
    2232             :   const MCPhysReg DQuad[] = {
    2233             :     ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, ARM::D15_D16_D17_D18, ARM::Q8_Q9, ARM::D17_D18_D19_D20, ARM::Q9_Q10, ARM::D19_D20_D21_D22, ARM::Q10_Q11, ARM::D21_D22_D23_D24, ARM::Q11_Q12, ARM::D23_D24_D25_D26, ARM::Q12_Q13, ARM::D25_D26_D27_D28, ARM::Q13_Q14, ARM::D27_D28_D29_D30, ARM::Q14_Q15, 
    2234             :   };
    2235             : 
    2236             :   // DQuad Bit set.
    2237             :   const uint8_t DQuadBits[] = {
    2238             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, 
    2239             :   };
    2240             : 
    2241             :   // DQuad_with_ssub_0 Register Class...
    2242             :   const MCPhysReg DQuad_with_ssub_0[] = {
    2243             :     ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, ARM::D15_D16_D17_D18, 
    2244             :   };
    2245             : 
    2246             :   // DQuad_with_ssub_0 Bit set.
    2247             :   const uint8_t DQuad_with_ssub_0Bits[] = {
    2248             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 
    2249             :   };
    2250             : 
    2251             :   // DQuad_with_ssub_2 Register Class...
    2252             :   const MCPhysReg DQuad_with_ssub_2[] = {
    2253             :     ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, 
    2254             :   };
    2255             : 
    2256             :   // DQuad_with_ssub_2 Bit set.
    2257             :   const uint8_t DQuad_with_ssub_2Bits[] = {
    2258             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 
    2259             :   };
    2260             : 
    2261             :   // QQPR Register Class...
    2262             :   const MCPhysReg QQPR[] = {
    2263             :     ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8, ARM::Q8_Q9, ARM::Q9_Q10, ARM::Q10_Q11, ARM::Q11_Q12, ARM::Q12_Q13, ARM::Q13_Q14, ARM::Q14_Q15, 
    2264             :   };
    2265             : 
    2266             :   // QQPR Bit set.
    2267             :   const uint8_t QQPRBits[] = {
    2268             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
    2269             :   };
    2270             : 
    2271             :   // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
    2272             :   const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
    2273             :     ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, ARM::D15_D16_D17_D18, ARM::D17_D18_D19_D20, ARM::D19_D20_D21_D22, ARM::D21_D22_D23_D24, ARM::D23_D24_D25_D26, ARM::D25_D26_D27_D28, ARM::D27_D28_D29_D30, 
    2274             :   };
    2275             : 
    2276             :   // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
    2277             :   const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
    2278             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, 
    2279             :   };
    2280             : 
    2281             :   // DQuad_with_ssub_4 Register Class...
    2282             :   const MCPhysReg DQuad_with_ssub_4[] = {
    2283             :     ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, 
    2284             :   };
    2285             : 
    2286             :   // DQuad_with_ssub_4 Bit set.
    2287             :   const uint8_t DQuad_with_ssub_4Bits[] = {
    2288             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 
    2289             :   };
    2290             : 
    2291             :   // DQuad_with_ssub_6 Register Class...
    2292             :   const MCPhysReg DQuad_with_ssub_6[] = {
    2293             :     ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, 
    2294             :   };
    2295             : 
    2296             :   // DQuad_with_ssub_6 Bit set.
    2297             :   const uint8_t DQuad_with_ssub_6Bits[] = {
    2298             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, 
    2299             :   };
    2300             : 
    2301             :   // DQuad_with_dsub_0_in_DPR_8 Register Class...
    2302             :   const MCPhysReg DQuad_with_dsub_0_in_DPR_8[] = {
    2303             :     ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, 
    2304             :   };
    2305             : 
    2306             :   // DQuad_with_dsub_0_in_DPR_8 Bit set.
    2307             :   const uint8_t DQuad_with_dsub_0_in_DPR_8Bits[] = {
    2308             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 
    2309             :   };
    2310             : 
    2311             :   // DQuad_with_qsub_0_in_QPR_VFP2 Register Class...
    2312             :   const MCPhysReg DQuad_with_qsub_0_in_QPR_VFP2[] = {
    2313             :     ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8, 
    2314             :   };
    2315             : 
    2316             :   // DQuad_with_qsub_0_in_QPR_VFP2 Bit set.
    2317             :   const uint8_t DQuad_with_qsub_0_in_QPR_VFP2Bits[] = {
    2318             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
    2319             :   };
    2320             : 
    2321             :   // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
    2322             :   const MCPhysReg DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
    2323             :     ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, ARM::D15_D16_D17_D18, 
    2324             :   };
    2325             : 
    2326             :   // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
    2327             :   const uint8_t DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
    2328             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 
    2329             :   };
    2330             : 
    2331             :   // DQuad_with_dsub_1_in_DPR_8 Register Class...
    2332             :   const MCPhysReg DQuad_with_dsub_1_in_DPR_8[] = {
    2333             :     ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, 
    2334             :   };
    2335             : 
    2336             :   // DQuad_with_dsub_1_in_DPR_8 Bit set.
    2337             :   const uint8_t DQuad_with_dsub_1_in_DPR_8Bits[] = {
    2338             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 
    2339             :   };
    2340             : 
    2341             :   // DQuad_with_qsub_1_in_QPR_VFP2 Register Class...
    2342             :   const MCPhysReg DQuad_with_qsub_1_in_QPR_VFP2[] = {
    2343             :     ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, 
    2344             :   };
    2345             : 
    2346             :   // DQuad_with_qsub_1_in_QPR_VFP2 Bit set.
    2347             :   const uint8_t DQuad_with_qsub_1_in_QPR_VFP2Bits[] = {
    2348             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 
    2349             :   };
    2350             : 
    2351             :   // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Register Class...
    2352             :   const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2[] = {
    2353             :     ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, 
    2354             :   };
    2355             : 
    2356             :   // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Bit set.
    2357             :   const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits[] = {
    2358             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 
    2359             :   };
    2360             : 
    2361             :   // DQuad_with_dsub_2_in_DPR_8 Register Class...
    2362             :   const MCPhysReg DQuad_with_dsub_2_in_DPR_8[] = {
    2363             :     ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, 
    2364             :   };
    2365             : 
    2366             :   // DQuad_with_dsub_2_in_DPR_8 Bit set.
    2367             :   const uint8_t DQuad_with_dsub_2_in_DPR_8Bits[] = {
    2368             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 
    2369             :   };
    2370             : 
    2371             :   // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
    2372             :   const MCPhysReg DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
    2373             :     ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, 
    2374             :   };
    2375             : 
    2376             :   // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
    2377             :   const uint8_t DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
    2378             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, 
    2379             :   };
    2380             : 
    2381             :   // DQuad_with_dsub_3_in_DPR_8 Register Class...
    2382             :   const MCPhysReg DQuad_with_dsub_3_in_DPR_8[] = {
    2383             :     ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, 
    2384             :   };
    2385             : 
    2386             :   // DQuad_with_dsub_3_in_DPR_8 Bit set.
    2387             :   const uint8_t DQuad_with_dsub_3_in_DPR_8Bits[] = {
    2388             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 
    2389             :   };
    2390             : 
    2391             :   // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
    2392             :   const MCPhysReg DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
    2393             :     ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, 
    2394             :   };
    2395             : 
    2396             :   // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
    2397             :   const uint8_t DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
    2398             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 
    2399             :   };
    2400             : 
    2401             :   // DQuad_with_qsub_0_in_QPR_8 Register Class...
    2402             :   const MCPhysReg DQuad_with_qsub_0_in_QPR_8[] = {
    2403             :     ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, 
    2404             :   };
    2405             : 
    2406             :   // DQuad_with_qsub_0_in_QPR_8 Bit set.
    2407             :   const uint8_t DQuad_with_qsub_0_in_QPR_8Bits[] = {
    2408             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 
    2409             :   };
    2410             : 
    2411             :   // DQuad_with_qsub_1_in_QPR_8 Register Class...
    2412             :   const MCPhysReg DQuad_with_qsub_1_in_QPR_8[] = {
    2413             :     ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, 
    2414             :   };
    2415             : 
    2416             :   // DQuad_with_qsub_1_in_QPR_8 Bit set.
    2417             :   const uint8_t DQuad_with_qsub_1_in_QPR_8Bits[] = {
    2418             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 
    2419             :   };
    2420             : 
    2421             :   // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class...
    2422             :   const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = {
    2423             :     ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, 
    2424             :   };
    2425             : 
    2426             :   // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set.
    2427             :   const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = {
    2428             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 
    2429             :   };
    2430             : 
    2431             :   // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
    2432             :   const MCPhysReg DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
    2433             :     ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, 
    2434             :   };
    2435             : 
    2436             :   // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
    2437             :   const uint8_t DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
    2438             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 
    2439             :   };
    2440             : 
    2441             :   // QQQQPR Register Class...
    2442             :   const MCPhysReg QQQQPR[] = {
    2443             :     ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10, ARM::Q8_Q9_Q10_Q11, ARM::Q9_Q10_Q11_Q12, ARM::Q10_Q11_Q12_Q13, ARM::Q11_Q12_Q13_Q14, ARM::Q12_Q13_Q14_Q15, 
    2444             :   };
    2445             : 
    2446             :   // QQQQPR Bit set.
    2447             :   const uint8_t QQQQPRBits[] = {
    2448             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 
    2449             :   };
    2450             : 
    2451             :   // QQQQPR_with_ssub_0 Register Class...
    2452             :   const MCPhysReg QQQQPR_with_ssub_0[] = {
    2453             :     ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10, 
    2454             :   };
    2455             : 
    2456             :   // QQQQPR_with_ssub_0 Bit set.
    2457             :   const uint8_t QQQQPR_with_ssub_0Bits[] = {
    2458             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, 
    2459             :   };
    2460             : 
    2461             :   // QQQQPR_with_ssub_4 Register Class...
    2462             :   const MCPhysReg QQQQPR_with_ssub_4[] = {
    2463             :     ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, 
    2464             :   };
    2465             : 
    2466             :   // QQQQPR_with_ssub_4 Bit set.
    2467             :   const uint8_t QQQQPR_with_ssub_4Bits[] = {
    2468             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, 
    2469             :   };
    2470             : 
    2471             :   // QQQQPR_with_ssub_8 Register Class...
    2472             :   const MCPhysReg QQQQPR_with_ssub_8[] = {
    2473             :     ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, 
    2474             :   };
    2475             : 
    2476             :   // QQQQPR_with_ssub_8 Bit set.
    2477             :   const uint8_t QQQQPR_with_ssub_8Bits[] = {
    2478             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03, 
    2479             :   };
    2480             : 
    2481             :   // QQQQPR_with_ssub_12 Register Class...
    2482             :   const MCPhysReg QQQQPR_with_ssub_12[] = {
    2483             :     ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, 
    2484             :   };
    2485             : 
    2486             :   // QQQQPR_with_ssub_12 Bit set.
    2487             :   const uint8_t QQQQPR_with_ssub_12Bits[] = {
    2488             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01, 
    2489             :   };
    2490             : 
    2491             :   // QQQQPR_with_dsub_0_in_DPR_8 Register Class...
    2492             :   const MCPhysReg QQQQPR_with_dsub_0_in_DPR_8[] = {
    2493             :     ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, 
    2494             :   };
    2495             : 
    2496             :   // QQQQPR_with_dsub_0_in_DPR_8 Bit set.
    2497             :   const uint8_t QQQQPR_with_dsub_0_in_DPR_8Bits[] = {
    2498             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 
    2499             :   };
    2500             : 
    2501             :   // QQQQPR_with_dsub_2_in_DPR_8 Register Class...
    2502             :   const MCPhysReg QQQQPR_with_dsub_2_in_DPR_8[] = {
    2503             :     ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, 
    2504             :   };
    2505             : 
    2506             :   // QQQQPR_with_dsub_2_in_DPR_8 Bit set.
    2507             :   const uint8_t QQQQPR_with_dsub_2_in_DPR_8Bits[] = {
    2508             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 
    2509             :   };
    2510             : 
    2511             :   // QQQQPR_with_dsub_4_in_DPR_8 Register Class...
    2512             :   const MCPhysReg QQQQPR_with_dsub_4_in_DPR_8[] = {
    2513             :     ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, 
    2514             :   };
    2515             : 
    2516             :   // QQQQPR_with_dsub_4_in_DPR_8 Bit set.
    2517             :   const uint8_t QQQQPR_with_dsub_4_in_DPR_8Bits[] = {
    2518             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 
    2519             :   };
    2520             : 
    2521             :   // QQQQPR_with_dsub_6_in_DPR_8 Register Class...
    2522             :   const MCPhysReg QQQQPR_with_dsub_6_in_DPR_8[] = {
    2523             :     ARM::Q0_Q1_Q2_Q3, 
    2524             :   };
    2525             : 
    2526             :   // QQQQPR_with_dsub_6_in_DPR_8 Bit set.
    2527             :   const uint8_t QQQQPR_with_dsub_6_in_DPR_8Bits[] = {
    2528             :     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 
    2529             :   };
    2530             : 
    2531             : } // end anonymous namespace
    2532             : 
    2533             : extern const char ARMRegClassStrings[] = {
    2534             :   /* 0 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
    2535             :   /* 19 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
    2536             :   /* 40 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
    2537             :   /* 63 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
    2538             :   /* 84 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
    2539             :   /* 102 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
    2540             :   /* 122 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
    2541             :   /* 140 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '1', '2', 0,
    2542             :   /* 160 */ 'D', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
    2543             :   /* 169 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
    2544             :   /* 199 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
    2545             :   /* 231 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
    2546             :   /* 261 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
    2547             :   /* 312 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
    2548             :   /* 365 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', 0,
    2549             :   /* 383 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', 0,
    2550             :   /* 403 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', 0,
    2551             :   /* 421 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
    2552             :   /* 440 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
    2553             :   /* 461 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
    2554             :   /* 484 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
    2555             :   /* 505 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
    2556             :   /* 523 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
    2557             :   /* 543 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '6', 0,
    2558             :   /* 561 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
    2559             :   /* 589 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
    2560             :   /* 619 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
    2561             :   /* 651 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
    2562             :   /* 681 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
    2563             :   /* 708 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
    2564             :   /* 737 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
    2565             :   /* 764 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
    2566             :   /* 791 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
    2567             :   /* 820 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
    2568             :   /* 847 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
    2569             :   /* 875 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
    2570             :   /* 905 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
    2571             :   /* 937 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
    2572             :   /* 967 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
    2573             :   /* 994 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
    2574             :   /* 1023 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '3', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
    2575             :   /* 1050 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '4', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
    2576             :   /* 1078 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '4', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
    2577             :   /* 1108 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '4', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
    2578             :   /* 1140 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '6', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
    2579             :   /* 1168 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
    2580             :   /* 1195 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
    2581             :   /* 1224 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
    2582             :   /* 1251 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
    2583             :   /* 1299 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
    2584             :   /* 1349 */ 'S', 'P', 'R', '_', '8', 0,
    2585             :   /* 1355 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '8', 0,
    2586             :   /* 1374 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '8', 0,
    2587             :   /* 1395 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '8', 0,
    2588             :   /* 1418 */ 'C', 'C', 'R', 0,
    2589             :   /* 1422 */ 'D', 'P', 'R', 0,
    2590             :   /* 1426 */ 'h', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'c', 'G', 'P', 'R', 0,
    2591             :   /* 1441 */ 't', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'c', 'G', 'P', 'R', 0,
    2592             :   /* 1456 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', 0,
    2593             :   /* 1485 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', 0,
    2594             :   /* 1514 */ 'G', 'P', 'R', 'n', 'o', 'p', 'c', '_', 'a', 'n', 'd', '_', 'h', 'G', 'P', 'R', 0,
    2595             :   /* 1531 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'h', 'G', 'P', 'R', 0,
    2596             :   /* 1559 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'h', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 'r', 'G', 'P', 'R', 0,
    2597             :   /* 1596 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'r', 'G', 'P', 'R', 0,
    2598             :   /* 1624 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 't', 'G', 'P', 'R', 0,
    2599             :   /* 1652 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', 0,
    2600             :   /* 1659 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
    2601             :   /* 1710 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
    2602             :   /* 1770 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
    2603             :   /* 1838 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '6', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
    2604             :   /* 1906 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
    2605             :   /* 1983 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '3', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
    2606             :   /* 2060 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
    2607             :   /* 2132 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
    2608             :   /* 2213 */ 'S', 'P', 'R', 0,
    2609             :   /* 2217 */ 'G', 'P', 'R', 'w', 'i', 't', 'h', 'A', 'P', 'S', 'R', 0,
    2610             :   /* 2229 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', 0,
    2611             :   /* 2238 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', 0,
    2612             :   /* 2249 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', 0,
    2613             :   /* 2258 */ 'h', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'G', 'P', 'R', 'w', 'i', 't', 'h', 'p', 'c', 0,
    2614             :   /* 2278 */ 'G', 'P', 'R', 'n', 'o', 'p', 'c', 0,
    2615             :   /* 2286 */ 'D', 'Q', 'u', 'a', 'd', 0,
    2616             :   /* 2292 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 0,
    2617             :   /* 2300 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'G', 'P', 'R', 's', 'p', 0,
    2618             :   /* 2329 */ 'D', 'P', 'a', 'i', 'r', 0,
    2619             :   /* 2335 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', 0,
    2620             : };
    2621             : 
    2622             : extern const MCRegisterClass ARMMCRegisterClasses[] = {
    2623             :   { SPR, SPRBits, 2213, 32, sizeof(SPRBits), ARM::SPRRegClassID, 4, 1, true },
    2624             :   { GPR, GPRBits, 1437, 16, sizeof(GPRBits), ARM::GPRRegClassID, 4, 1, true },
    2625             :   { GPRwithAPSR, GPRwithAPSRBits, 2217, 16, sizeof(GPRwithAPSRBits), ARM::GPRwithAPSRRegClassID, 4, 1, true },
    2626             :   { SPR_8, SPR_8Bits, 1349, 16, sizeof(SPR_8Bits), ARM::SPR_8RegClassID, 4, 1, true },
    2627             :   { GPRnopc, GPRnopcBits, 2278, 15, sizeof(GPRnopcBits), ARM::GPRnopcRegClassID, 4, 1, true },
    2628             :   { rGPR, rGPRBits, 1591, 14, sizeof(rGPRBits), ARM::rGPRRegClassID, 4, 1, true },
    2629             :   { tGPRwithpc, tGPRwithpcBits, 2267, 9, sizeof(tGPRwithpcBits), ARM::tGPRwithpcRegClassID, 4, 1, true },
    2630             :   { hGPR, hGPRBits, 1526, 8, sizeof(hGPRBits), ARM::hGPRRegClassID, 4, 1, true },
    2631             :   { tGPR, tGPRBits, 1647, 8, sizeof(tGPRBits), ARM::tGPRRegClassID, 4, 1, true },
    2632             :   { GPRnopc_and_hGPR, GPRnopc_and_hGPRBits, 1514, 7, sizeof(GPRnopc_and_hGPRBits), ARM::GPRnopc_and_hGPRRegClassID, 4, 1, true },
    2633             :   { hGPR_and_rGPR, hGPR_and_rGPRBits, 1582, 6, sizeof(hGPR_and_rGPRBits), ARM::hGPR_and_rGPRRegClassID, 4, 1, true },
    2634             :   { tcGPR, tcGPRBits, 1435, 5, sizeof(tcGPRBits), ARM::tcGPRRegClassID, 4, 1, true },
    2635             :   { tGPR_and_tcGPR, tGPR_and_tcGPRBits, 1441, 4, sizeof(tGPR_and_tcGPRBits), ARM::tGPR_and_tcGPRRegClassID, 4, 1, true },
    2636             :   { CCR, CCRBits, 1418, 1, sizeof(CCRBits), ARM::CCRRegClassID, 4, -1, false },
    2637             :   { GPRsp, GPRspBits, 2323, 1, sizeof(GPRspBits), ARM::GPRspRegClassID, 4, 1, true },
    2638             :   { hGPR_and_tGPRwithpc, hGPR_and_tGPRwithpcBits, 2258, 1, sizeof(hGPR_and_tGPRwithpcBits), ARM::hGPR_and_tGPRwithpcRegClassID, 4, 1, true },
    2639             :   { hGPR_and_tcGPR, hGPR_and_tcGPRBits, 1426, 1, sizeof(hGPR_and_tcGPRBits), ARM::hGPR_and_tcGPRRegClassID, 4, 1, true },
    2640             :   { DPR, DPRBits, 1422, 32, sizeof(DPRBits), ARM::DPRRegClassID, 8, 1, true },
    2641             :   { DPR_VFP2, DPR_VFP2Bits, 160, 16, sizeof(DPR_VFP2Bits), ARM::DPR_VFP2RegClassID, 8, 1, true },
    2642             :   { DPR_8, DPR_8Bits, 583, 8, sizeof(DPR_8Bits), ARM::DPR_8RegClassID, 8, 1, true },
    2643             :   { GPRPair, GPRPairBits, 2335, 7, sizeof(GPRPairBits), ARM::GPRPairRegClassID, 8, 1, true },
    2644             :   { GPRPair_with_gsub_1_in_rGPR, GPRPair_with_gsub_1_in_rGPRBits, 1596, 6, sizeof(GPRPair_with_gsub_1_in_rGPRBits), ARM::GPRPair_with_gsub_1_in_rGPRRegClassID, 8, 1, true },
    2645             :   { GPRPair_with_gsub_0_in_tGPR, GPRPair_with_gsub_0_in_tGPRBits, 1624, 4, sizeof(GPRPair_with_gsub_0_in_tGPRBits), ARM::GPRPair_with_gsub_0_in_tGPRRegClassID, 8, 1, true },
    2646             :   { GPRPair_with_gsub_0_in_hGPR, GPRPair_with_gsub_0_in_hGPRBits, 1531, 3, sizeof(GPRPair_with_gsub_0_in_hGPRBits), ARM::GPRPair_with_gsub_0_in_hGPRRegClassID, 8, 1, true },
    2647             :   { GPRPair_with_gsub_0_in_tcGPR, GPRPair_with_gsub_0_in_tcGPRBits, 1456, 3, sizeof(GPRPair_with_gsub_0_in_tcGPRBits), ARM::GPRPair_with_gsub_0_in_tcGPRRegClassID, 8, 1, true },
    2648             :   { GPRPair_with_gsub_1_in_hGPR_and_rGPR, GPRPair_with_gsub_1_in_hGPR_and_rGPRBits, 1559, 2, sizeof(GPRPair_with_gsub_1_in_hGPR_and_rGPRBits), ARM::GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClassID, 8, 1, true },
    2649             :   { GPRPair_with_gsub_1_in_tcGPR, GPRPair_with_gsub_1_in_tcGPRBits, 1485, 2, sizeof(GPRPair_with_gsub_1_in_tcGPRBits), ARM::GPRPair_with_gsub_1_in_tcGPRRegClassID, 8, 1, true },
    2650             :   { GPRPair_with_gsub_1_in_GPRsp, GPRPair_with_gsub_1_in_GPRspBits, 2300, 1, sizeof(GPRPair_with_gsub_1_in_GPRspBits), ARM::GPRPair_with_gsub_1_in_GPRspRegClassID, 8, 1, true },
    2651             :   { DPairSpc, DPairSpcBits, 2249, 30, sizeof(DPairSpcBits), ARM::DPairSpcRegClassID, 16, 1, true },
    2652             :   { DPairSpc_with_ssub_0, DPairSpc_with_ssub_0Bits, 63, 16, sizeof(DPairSpc_with_ssub_0Bits), ARM::DPairSpc_with_ssub_0RegClassID, 16, 1, true },
    2653             :   { DPairSpc_with_ssub_4, DPairSpc_with_ssub_4Bits, 484, 14, sizeof(DPairSpc_with_ssub_4Bits), ARM::DPairSpc_with_ssub_4RegClassID, 16, 1, true },
    2654             :   { DPairSpc_with_dsub_0_in_DPR_8, DPairSpc_with_dsub_0_in_DPR_8Bits, 651, 8, sizeof(DPairSpc_with_dsub_0_in_DPR_8Bits), ARM::DPairSpc_with_dsub_0_in_DPR_8RegClassID, 16, 1, true },
    2655             :   { DPairSpc_with_dsub_2_in_DPR_8, DPairSpc_with_dsub_2_in_DPR_8Bits, 937, 6, sizeof(DPairSpc_with_dsub_2_in_DPR_8Bits), ARM::DPairSpc_with_dsub_2_in_DPR_8RegClassID, 16, 1, true },
    2656             :   { DPair, DPairBits, 2329, 31, sizeof(DPairBits), ARM::DPairRegClassID, 16, 1, true },
    2657             :   { DPair_with_ssub_0, DPair_with_ssub_0Bits, 122, 16, sizeof(DPair_with_ssub_0Bits), ARM::DPair_with_ssub_0RegClassID, 16, 1, true },
    2658             :   { QPR, QPRBits, 1655, 16, sizeof(QPRBits), ARM::QPRRegClassID, 16, 1, true },
    2659             :   { DPair_with_ssub_2, DPair_with_ssub_2Bits, 403, 15, sizeof(DPair_with_ssub_2Bits), ARM::DPair_with_ssub_2RegClassID, 16, 1, true },
    2660             :   { DPair_with_dsub_0_in_DPR_8, DPair_with_dsub_0_in_DPR_8Bits, 737, 8, sizeof(DPair_with_dsub_0_in_DPR_8Bits), ARM::DPair_with_dsub_0_in_DPR_8RegClassID, 16, 1, true },
    2661             :   { QPR_VFP2, QPR_VFP2Bits, 190, 8, sizeof(QPR_VFP2Bits), ARM::QPR_VFP2RegClassID, 16, 1, true },
    2662             :   { DPair_with_dsub_1_in_DPR_8, DPair_with_dsub_1_in_DPR_8Bits, 820, 7, sizeof(DPair_with_dsub_1_in_DPR_8Bits), ARM::DPair_with_dsub_1_in_DPR_8RegClassID, 16, 1, true },
    2663             :   { QPR_8, QPR_8Bits, 1189, 4, sizeof(QPR_8Bits), ARM::QPR_8RegClassID, 16, 1, true },
    2664             :   { DTriple, DTripleBits, 2292, 30, sizeof(DTripleBits), ARM::DTripleRegClassID, 24, 1, true },
    2665             :   { DTripleSpc, DTripleSpcBits, 2238, 28, sizeof(DTripleSpcBits), ARM::DTripleSpcRegClassID, 24, 1, true },
    2666             :   { DTripleSpc_with_ssub_0, DTripleSpc_with_ssub_0Bits, 40, 16, sizeof(DTripleSpc_with_ssub_0Bits), ARM::DTripleSpc_with_ssub_0RegClassID, 24, 1, true },
    2667             :   { DTriple_with_ssub_0, DTriple_with_ssub_0Bits, 102, 16, sizeof(DTriple_with_ssub_0Bits), ARM::DTriple_with_ssub_0RegClassID, 24, 1, true },
    2668             :   { DTriple_with_qsub_0_in_QPR, DTriple_with_qsub_0_in_QPRBits, 1683, 15, sizeof(DTriple_with_qsub_0_in_QPRBits), ARM::DTriple_with_qsub_0_in_QPRRegClassID, 24, 1, true },
    2669             :   { DTriple_with_ssub_2, DTriple_with_ssub_2Bits, 383, 15, sizeof(DTriple_with_ssub_2Bits), ARM::DTriple_with_ssub_2RegClassID, 24, 1, true },
    2670             :   { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 2084, 15, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 24, 1, true },
    2671             :   { DTripleSpc_with_ssub_4, DTripleSpc_with_ssub_4Bits, 461, 14, sizeof(DTripleSpc_with_ssub_4Bits), ARM::DTripleSpc_with_ssub_4RegClassID, 24, 1, true },
    2672             :   { DTriple_with_ssub_4, DTriple_with_ssub_4Bits, 523, 14, sizeof(DTriple_with_ssub_4Bits), ARM::DTriple_with_ssub_4RegClassID, 24, 1, true },
    2673             :   { DTripleSpc_with_ssub_8, DTripleSpc_with_ssub_8Bits, 1395, 12, sizeof(DTripleSpc_with_ssub_8Bits), ARM::DTripleSpc_with_ssub_8RegClassID, 24, 1, true },
    2674             :   { DTripleSpc_with_dsub_0_in_DPR_8, DTripleSpc_with_dsub_0_in_DPR_8Bits, 619, 8, sizeof(DTripleSpc_with_dsub_0_in_DPR_8Bits), ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClassID, 24, 1, true },
    2675             :   { DTriple_with_dsub_0_in_DPR_8, DTriple_with_dsub_0_in_DPR_8Bits, 708, 8, sizeof(DTriple_with_dsub_0_in_DPR_8Bits), ARM::DTriple_with_dsub_0_in_DPR_8RegClassID, 24, 1, true },
    2676             :   { DTriple_with_qsub_0_in_QPR_VFP2, DTriple_with_qsub_0_in_QPR_VFP2Bits, 199, 8, sizeof(DTriple_with_qsub_0_in_QPR_VFP2Bits), ARM::DTriple_with_qsub_0_in_QPR_VFP2RegClassID, 24, 1, true },
    2677             :   { DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 2060, 8, sizeof(DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 24, 1, true },
    2678             :   { DTriple_with_dsub_1_in_DPR_8, DTriple_with_dsub_1_in_DPR_8Bits, 791, 7, sizeof(DTriple_with_dsub_1_in_DPR_8Bits), ARM::DTriple_with_dsub_1_in_DPR_8RegClassID, 24, 1, true },
    2679             :   { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits, 312, 7, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits), ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID, 24, 1, true },
    2680             :   { DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR, DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRBits, 1659, 7, sizeof(DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRBits), ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClassID, 24, 1, true },
    2681             :   { DTripleSpc_with_dsub_2_in_DPR_8, DTripleSpc_with_dsub_2_in_DPR_8Bits, 905, 6, sizeof(DTripleSpc_with_dsub_2_in_DPR_8Bits), ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClassID, 24, 1, true },
    2682             :   { DTriple_with_dsub_2_in_DPR_8, DTriple_with_dsub_2_in_DPR_8Bits, 994, 6, sizeof(DTriple_with_dsub_2_in_DPR_8Bits), ARM::DTriple_with_dsub_2_in_DPR_8RegClassID, 24, 1, true },
    2683             :   { DTripleSpc_with_dsub_4_in_DPR_8, DTripleSpc_with_dsub_4_in_DPR_8Bits, 1108, 4, sizeof(DTripleSpc_with_dsub_4_in_DPR_8Bits), ARM::DTripleSpc_with_dsub_4_in_DPR_8RegClassID, 24, 1, true },
    2684             :   { DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 2132, 4, sizeof(DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 24, 1, true },
    2685             :   { DTriple_with_qsub_0_in_QPR_8, DTriple_with_qsub_0_in_QPR_8Bits, 1195, 4, sizeof(DTriple_with_qsub_0_in_QPR_8Bits), ARM::DTriple_with_qsub_0_in_QPR_8RegClassID, 24, 1, true },
    2686             :   { DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR, DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits, 1710, 3, sizeof(DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits), ARM::DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClassID, 24, 1, true },
    2687             :   { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, 1299, 3, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits), ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID, 24, 1, true },
    2688             :   { DQuadSpc, DQuadSpcBits, 2229, 28, sizeof(DQuadSpcBits), ARM::DQuadSpcRegClassID, 32, 1, true },
    2689             :   { DQuadSpc_with_ssub_0, DQuadSpc_with_ssub_0Bits, 19, 16, sizeof(DQuadSpc_with_ssub_0Bits), ARM::DQuadSpc_with_ssub_0RegClassID, 32, 1, true },
    2690             :   { DQuadSpc_with_ssub_4, DQuadSpc_with_ssub_4Bits, 440, 14, sizeof(DQuadSpc_with_ssub_4Bits), ARM::DQuadSpc_with_ssub_4RegClassID, 32, 1, true },
    2691             :   { DQuadSpc_with_ssub_8, DQuadSpc_with_ssub_8Bits, 1374, 12, sizeof(DQuadSpc_with_ssub_8Bits), ARM::DQuadSpc_with_ssub_8RegClassID, 32, 1, true },
    2692             :   { DQuadSpc_with_dsub_0_in_DPR_8, DQuadSpc_with_dsub_0_in_DPR_8Bits, 589, 8, sizeof(DQuadSpc_with_dsub_0_in_DPR_8Bits), ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClassID, 32, 1, true },
    2693             :   { DQuadSpc_with_dsub_2_in_DPR_8, DQuadSpc_with_dsub_2_in_DPR_8Bits, 875, 6, sizeof(DQuadSpc_with_dsub_2_in_DPR_8Bits), ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClassID, 32, 1, true },
    2694             :   { DQuadSpc_with_dsub_4_in_DPR_8, DQuadSpc_with_dsub_4_in_DPR_8Bits, 1078, 4, sizeof(DQuadSpc_with_dsub_4_in_DPR_8Bits), ARM::DQuadSpc_with_dsub_4_in_DPR_8RegClassID, 32, 1, true },
    2695             :   { DQuad, DQuadBits, 2286, 29, sizeof(DQuadBits), ARM::DQuadRegClassID, 32, 1, true },
    2696             :   { DQuad_with_ssub_0, DQuad_with_ssub_0Bits, 84, 16, sizeof(DQuad_with_ssub_0Bits), ARM::DQuad_with_ssub_0RegClassID, 32, 1, true },
    2697             :   { DQuad_with_ssub_2, DQuad_with_ssub_2Bits, 365, 15, sizeof(DQuad_with_ssub_2Bits), ARM::DQuad_with_ssub_2RegClassID, 32, 1, true },
    2698             :   { QQPR, QQPRBits, 1654, 15, sizeof(QQPRBits), ARM::QQPRRegClassID, 32, 1, true },
    2699             :   { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 1792, 14, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 32, 1, true },
    2700             :   { DQuad_with_ssub_4, DQuad_with_ssub_4Bits, 505, 14, sizeof(DQuad_with_ssub_4Bits), ARM::DQuad_with_ssub_4RegClassID, 32, 1, true },
    2701             :   { DQuad_with_ssub_6, DQuad_with_ssub_6Bits, 543, 13, sizeof(DQuad_with_ssub_6Bits), ARM::DQuad_with_ssub_6RegClassID, 32, 1, true },
    2702             :   { DQuad_with_dsub_0_in_DPR_8, DQuad_with_dsub_0_in_DPR_8Bits, 681, 8, sizeof(DQuad_with_dsub_0_in_DPR_8Bits), ARM::DQuad_with_dsub_0_in_DPR_8RegClassID, 32, 1, true },
    2703             :   { DQuad_with_qsub_0_in_QPR_VFP2, DQuad_with_qsub_0_in_QPR_VFP2Bits, 169, 8, sizeof(DQuad_with_qsub_0_in_QPR_VFP2Bits), ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClassID, 32, 1, true },
    2704             :   { DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 1770, 8, sizeof(DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 32, 1, true },
    2705             :   { DQuad_with_dsub_1_in_DPR_8, DQuad_with_dsub_1_in_DPR_8Bits, 764, 7, sizeof(DQuad_with_dsub_1_in_DPR_8Bits), ARM::DQuad_with_dsub_1_in_DPR_8RegClassID, 32, 1, true },
    2706             :   { DQuad_with_qsub_1_in_QPR_VFP2, DQuad_with_qsub_1_in_QPR_VFP2Bits, 231, 7, sizeof(DQuad_with_qsub_1_in_QPR_VFP2Bits), ARM::DQuad_with_qsub_1_in_QPR_VFP2RegClassID, 32, 1, true },
    2707             :   { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits, 261, 7, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits), ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID, 32, 1, true },
    2708             :   { DQuad_with_dsub_2_in_DPR_8, DQuad_with_dsub_2_in_DPR_8Bits, 967, 6, sizeof(DQuad_with_dsub_2_in_DPR_8Bits), ARM::DQuad_with_dsub_2_in_DPR_8RegClassID, 32, 1, true },
    2709             :   { DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 1838, 6, sizeof(DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 32, 1, true },
    2710             :   { DQuad_with_dsub_3_in_DPR_8, DQuad_with_dsub_3_in_DPR_8Bits, 1023, 5, sizeof(DQuad_with_dsub_3_in_DPR_8Bits), ARM::DQuad_with_dsub_3_in_DPR_8RegClassID, 32, 1, true },
    2711             :   { DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 1906, 4, sizeof(DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 32, 1, true },
    2712             :   { DQuad_with_qsub_0_in_QPR_8, DQuad_with_qsub_0_in_QPR_8Bits, 1168, 4, sizeof(DQuad_with_qsub_0_in_QPR_8Bits), ARM::DQuad_with_qsub_0_in_QPR_8RegClassID, 32, 1, true },
    2713             :   { DQuad_with_qsub_1_in_QPR_8, DQuad_with_qsub_1_in_QPR_8Bits, 1224, 3, sizeof(DQuad_with_qsub_1_in_QPR_8Bits), ARM::DQuad_with_qsub_1_in_QPR_8RegClassID, 32, 1, true },
    2714             :   { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, 1251, 3, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits), ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID, 32, 1, true },
    2715             :   { DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 1983, 2, sizeof(DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 32, 1, true },
    2716             :   { QQQQPR, QQQQPRBits, 1652, 13, sizeof(QQQQPRBits), ARM::QQQQPRRegClassID, 64, 1, true },
    2717             :   { QQQQPR_with_ssub_0, QQQQPR_with_ssub_0Bits, 0, 8, sizeof(QQQQPR_with_ssub_0Bits), ARM::QQQQPR_with_ssub_0RegClassID, 64, 1, true },
    2718             :   { QQQQPR_with_ssub_4, QQQQPR_with_ssub_4Bits, 421, 7, sizeof(QQQQPR_with_ssub_4Bits), ARM::QQQQPR_with_ssub_4RegClassID, 64, 1, true },
    2719             :   { QQQQPR_with_ssub_8, QQQQPR_with_ssub_8Bits, 1355, 6, sizeof(QQQQPR_with_ssub_8Bits), ARM::QQQQPR_with_ssub_8RegClassID, 64, 1, true },
    2720             :   { QQQQPR_with_ssub_12, QQQQPR_with_ssub_12Bits, 140, 5, sizeof(QQQQPR_with_ssub_12Bits), ARM::QQQQPR_with_ssub_12RegClassID, 64, 1, true },
    2721             :   { QQQQPR_with_dsub_0_in_DPR_8, QQQQPR_with_dsub_0_in_DPR_8Bits, 561, 4, sizeof(QQQQPR_with_dsub_0_in_DPR_8Bits), ARM::QQQQPR_with_dsub_0_in_DPR_8RegClassID, 64, 1, true },
    2722             :   { QQQQPR_with_dsub_2_in_DPR_8, QQQQPR_with_dsub_2_in_DPR_8Bits, 847, 3, sizeof(QQQQPR_with_dsub_2_in_DPR_8Bits), ARM::QQQQPR_with_dsub_2_in_DPR_8RegClassID, 64, 1, true },
    2723             :   { QQQQPR_with_dsub_4_in_DPR_8, QQQQPR_with_dsub_4_in_DPR_8Bits, 1050, 2, sizeof(QQQQPR_with_dsub_4_in_DPR_8Bits), ARM::QQQQPR_with_dsub_4_in_DPR_8RegClassID, 64, 1, true },
    2724             :   { QQQQPR_with_dsub_6_in_DPR_8, QQQQPR_with_dsub_6_in_DPR_8Bits, 1140, 1, sizeof(QQQQPR_with_dsub_6_in_DPR_8Bits), ARM::QQQQPR_with_dsub_6_in_DPR_8RegClassID, 64, 1, true },
    2725             : };
    2726             : 
    2727             : // ARM Dwarf<->LLVM register mappings.
    2728             : extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0Dwarf2L[] = {
    2729             :   { 0U, ARM::R0 },
    2730             :   { 1U, ARM::R1 },
    2731             :   { 2U, ARM::R2 },
    2732             :   { 3U, ARM::R3 },
    2733             :   { 4U, ARM::R4 },
    2734             :   { 5U, ARM::R5 },
    2735             :   { 6U, ARM::R6 },
    2736             :   { 7U, ARM::R7 },
    2737             :   { 8U, ARM::R8 },
    2738             :   { 9U, ARM::R9 },
    2739             :   { 10U, ARM::R10 },
    2740             :   { 11U, ARM::R11 },
    2741             :   { 12U, ARM::R12 },
    2742             :   { 13U, ARM::SP },
    2743             :   { 14U, ARM::LR },
    2744             :   { 15U, ARM::PC },
    2745             :   { 256U, ARM::D0 },
    2746             :   { 257U, ARM::D1 },
    2747             :   { 258U, ARM::D2 },
    2748             :   { 259U, ARM::D3 },
    2749             :   { 260U, ARM::D4 },
    2750             :   { 261U, ARM::D5 },
    2751             :   { 262U, ARM::D6 },
    2752             :   { 263U, ARM::D7 },
    2753             :   { 264U, ARM::D8 },
    2754             :   { 265U, ARM::D9 },
    2755             :   { 266U, ARM::D10 },
    2756             :   { 267U, ARM::D11 },
    2757             :   { 268U, ARM::D12 },
    2758             :   { 269U, ARM::D13 },
    2759             :   { 270U, ARM::D14 },
    2760             :   { 271U, ARM::D15 },
    2761             :   { 272U, ARM::D16 },
    2762             :   { 273U, ARM::D17 },
    2763             :   { 274U, ARM::D18 },
    2764             :   { 275U, ARM::D19 },
    2765             :   { 276U, ARM::D20 },
    2766             :   { 277U, ARM::D21 },
    2767             :   { 278U, ARM::D22 },
    2768             :   { 279U, ARM::D23 },
    2769             :   { 280U, ARM::D24 },
    2770             :   { 281U, ARM::D25 },
    2771             :   { 282U, ARM::D26 },
    2772             :   { 283U, ARM::D27 },
    2773             :   { 284U, ARM::D28 },
    2774             :   { 285U, ARM::D29 },
    2775             :   { 286U, ARM::D30 },
    2776             :   { 287U, ARM::D31 },
    2777             : };
    2778             : extern const unsigned ARMDwarfFlavour0Dwarf2LSize = array_lengthof(ARMDwarfFlavour0Dwarf2L);
    2779             : 
    2780             : extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0Dwarf2L[] = {
    2781             :   { 0U, ARM::R0 },
    2782             :   { 1U, ARM::R1 },
    2783             :   { 2U, ARM::R2 },
    2784             :   { 3U, ARM::R3 },
    2785             :   { 4U, ARM::R4 },
    2786             :   { 5U, ARM::R5 },
    2787             :   { 6U, ARM::R6 },
    2788             :   { 7U, ARM::R7 },
    2789             :   { 8U, ARM::R8 },
    2790             :   { 9U, ARM::R9 },
    2791             :   { 10U, ARM::R10 },
    2792             :   { 11U, ARM::R11 },
    2793             :   { 12U, ARM::R12 },
    2794             :   { 13U, ARM::SP },
    2795             :   { 14U, ARM::LR },
    2796             :   { 15U, ARM::PC },
    2797             :   { 256U, ARM::D0 },
    2798             :   { 257U, ARM::D1 },
    2799             :   { 258U, ARM::D2 },
    2800             :   { 259U, ARM::D3 },
    2801             :   { 260U, ARM::D4 },
    2802             :   { 261U, ARM::D5 },
    2803             :   { 262U, ARM::D6 },
    2804             :   { 263U, ARM::D7 },
    2805             :   { 264U, ARM::D8 },
    2806             :   { 265U, ARM::D9 },
    2807             :   { 266U, ARM::D10 },
    2808             :   { 267U, ARM::D11 },
    2809             :   { 268U, ARM::D12 },
    2810             :   { 269U, ARM::D13 },
    2811             :   { 270U, ARM::D14 },
    2812             :   { 271U, ARM::D15 },
    2813             :   { 272U, ARM::D16 },
    2814             :   { 273U, ARM::D17 },
    2815             :   { 274U, ARM::D18 },
    2816             :   { 275U, ARM::D19 },
    2817             :   { 276U, ARM::D20 },
    2818             :   { 277U, ARM::D21 },
    2819             :   { 278U, ARM::D22 },
    2820             :   { 279U, ARM::D23 },
    2821             :   { 280U, ARM::D24 },
    2822             :   { 281U, ARM::D25 },
    2823             :   { 282U, ARM::D26 },
    2824             :   { 283U, ARM::D27 },
    2825             :   { 284U, ARM::D28 },
    2826             :   { 285U, ARM::D29 },
    2827             :   { 286U, ARM::D30 },
    2828             :   { 287U, ARM::D31 },
    2829             : };
    2830             : extern const unsigned ARMEHFlavour0Dwarf2LSize = array_lengthof(ARMEHFlavour0Dwarf2L);
    2831             : 
    2832             : extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0L2Dwarf[] = {
    2833             :   { ARM::LR, 14U },
    2834             :   { ARM::PC, 15U },
    2835             :   { ARM::SP, 13U },
    2836             :   { ARM::D0, 256U },
    2837             :   { ARM::D1, 257U },
    2838             :   { ARM::D2, 258U },
    2839             :   { ARM::D3, 259U },
    2840             :   { ARM::D4, 260U },
    2841             :   { ARM::D5, 261U },
    2842             :   { ARM::D6, 262U },
    2843             :   { ARM::D7, 263U },
    2844             :   { ARM::D8, 264U },
    2845             :   { ARM::D9, 265U },
    2846             :   { ARM::D10, 266U },
    2847             :   { ARM::D11, 267U },
    2848             :   { ARM::D12, 268U },
    2849             :   { ARM::D13, 269U },
    2850             :   { ARM::D14, 270U },
    2851             :   { ARM::D15, 271U },
    2852             :   { ARM::D16, 272U },
    2853             :   { ARM::D17, 273U },
    2854             :   { ARM::D18, 274U },
    2855             :   { ARM::D19, 275U },
    2856             :   { ARM::D20, 276U },
    2857             :   { ARM::D21, 277U },
    2858             :   { ARM::D22, 278U },
    2859             :   { ARM::D23, 279U },
    2860             :   { ARM::D24, 280U },
    2861             :   { ARM::D25, 281U },
    2862             :   { ARM::D26, 282U },
    2863             :   { ARM::D27, 283U },
    2864             :   { ARM::D28, 284U },
    2865             :   { ARM::D29, 285U },
    2866             :   { ARM::D30, 286U },
    2867             :   { ARM::D31, 287U },
    2868             :   { ARM::R0, 0U },
    2869             :   { ARM::R1, 1U },
    2870             :   { ARM::R2, 2U },
    2871             :   { ARM::R3, 3U },
    2872             :   { ARM::R4, 4U },
    2873             :   { ARM::R5, 5U },
    2874             :   { ARM::R6, 6U },
    2875             :   { ARM::R7, 7U },
    2876             :   { ARM::R8, 8U },
    2877             :   { ARM::R9, 9U },
    2878             :   { ARM::R10, 10U },
    2879             :   { ARM::R11, 11U },
    2880             :   { ARM::R12, 12U },
    2881             : };
    2882             : extern const unsigned ARMDwarfFlavour0L2DwarfSize = array_lengthof(ARMDwarfFlavour0L2Dwarf);
    2883             : 
    2884             : extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0L2Dwarf[] = {
    2885             :   { ARM::LR, 14U },
    2886             :   { ARM::PC, 15U },
    2887             :   { ARM::SP, 13U },
    2888             :   { ARM::D0, 256U },
    2889             :   { ARM::D1, 257U },
    2890             :   { ARM::D2, 258U },
    2891             :   { ARM::D3, 259U },
    2892             :   { ARM::D4, 260U },
    2893             :   { ARM::D5, 261U },
    2894             :   { ARM::D6, 262U },
    2895             :   { ARM::D7, 263U },
    2896             :   { ARM::D8, 264U },
    2897             :   { ARM::D9, 265U },
    2898             :   { ARM::D10, 266U },
    2899             :   { ARM::D11, 267U },
    2900             :   { ARM::D12, 268U },
    2901             :   { ARM::D13, 269U },
    2902             :   { ARM::D14, 270U },
    2903             :   { ARM::D15, 271U },
    2904             :   { ARM::D16, 272U },
    2905             :   { ARM::D17, 273U },
    2906             :   { ARM::D18, 274U },
    2907             :   { ARM::D19, 275U },
    2908             :   { ARM::D20, 276U },
    2909             :   { ARM::D21, 277U },
    2910             :   { ARM::D22, 278U },
    2911             :   { ARM::D23, 279U },
    2912             :   { ARM::D24, 280U },
    2913             :   { ARM::D25, 281U },
    2914             :   { ARM::D26, 282U },
    2915             :   { ARM::D27, 283U },
    2916             :   { ARM::D28, 284U },
    2917             :   { ARM::D29, 285U },
    2918             :   { ARM::D30, 286U },
    2919             :   { ARM::D31, 287U },
    2920             :   { ARM::R0, 0U },
    2921             :   { ARM::R1, 1U },
    2922             :   { ARM::R2, 2U },
    2923             :   { ARM::R3, 3U },
    2924             :   { ARM::R4, 4U },
    2925             :   { ARM::R5, 5U },
    2926             :   { ARM::R6, 6U },
    2927             :   { ARM::R7, 7U },
    2928             :   { ARM::R8, 8U },
    2929             :   { ARM::R9, 9U },
    2930             :   { ARM::R10, 10U },
    2931             :   { ARM::R11, 11U },
    2932             :   { ARM::R12, 12U },
    2933             : };
    2934             : extern const unsigned ARMEHFlavour0L2DwarfSize = array_lengthof(ARMEHFlavour0L2Dwarf);
    2935             : 
    2936             : extern const uint16_t ARMRegEncodingTable[] = {
    2937             :   0,
    2938             :   1,
    2939             :   15,
    2940             :   0,
    2941             :   8,
    2942             :   9,
    2943             :   3,
    2944             :   3,
    2945             :   0,
    2946             :   4,
    2947             :   14,
    2948             :   15,
    2949             :   13,
    2950             :   2,
    2951             :   0,
    2952             :   1,
    2953             :   2,
    2954             :   3,
    2955             :   4,
    2956             :   5,
    2957             :   6,
    2958             :   7,
    2959             :   8,
    2960             :   9,
    2961             :   10,
    2962             :   11,
    2963             :   12,
    2964             :   13,
    2965             :   14,
    2966             :   15,
    2967             :   16,
    2968             :   17,
    2969             :   18,
    2970             :   19,
    2971             :   20,
    2972             :   21,
    2973             :   22,
    2974             :   23,
    2975             :   24,
    2976             :   25,
    2977             :   26,
    2978             :   27,
    2979             :   28,
    2980             :   29,
    2981             :   30,
    2982             :   31,
    2983             :   10,
    2984             :   7,
    2985             :   6,
    2986             :   5,
    2987             :   0,
    2988             :   1,
    2989             :   2,
    2990             :   3,
    2991             :   4,
    2992             :   5,
    2993             :   6,
    2994             :   7,
    2995             :   8,
    2996             :   9,
    2997             :   10,
    2998             :   11,
    2999             :   12,
    3000             :   13,
    3001             :   14,
    3002             :   15,
    3003             :   0,
    3004             :   1,
    3005             :   2,
    3006             :   3,
    3007             :   4,
    3008             :   5,
    3009             :   6,
    3010             :   7,
    3011             :   8,
    3012             :   9,
    3013             :   10,
    3014             :   11,
    3015             :   12,
    3016             :   0,
    3017             :   1,
    3018             :   2,
    3019             :   3,
    3020             :   4,
    3021             :   5,
    3022             :   6,
    3023             :   7,
    3024             :   8,
    3025             :   9,
    3026             :   10,
    3027             :   11,
    3028             :   12,
    3029             :   13,
    3030             :   14,
    3031             :   15,
    3032             :   16,
    3033             :   17,
    3034             :   18,
    3035             :   19,
    3036             :   20,
    3037             :   21,
    3038             :   22,
    3039             :   23,
    3040             :   24,
    3041             :   25,
    3042             :   26,
    3043             :   27,
    3044             :   28,
    3045             :   29,
    3046             :   30,
    3047             :   31,
    3048             :   0,
    3049             :   1,
    3050             :   2,
    3051             :   3,
    3052             :   4,
    3053             :   5,
    3054             :   6,
    3055             :   7,
    3056             :   8,
    3057             :   9,
    3058             :   10,
    3059             :   11,
    3060             :   12,
    3061             :   13,
    3062             :   14,
    3063             :   15,
    3064             :   16,
    3065             :   17,
    3066             :   18,
    3067             :   19,
    3068             :   20,
    3069             :   21,
    3070             :   22,
    3071             :   23,
    3072             :   24,
    3073             :   25,
    3074             :   26,
    3075             :   27,
    3076             :   28,
    3077             :   29,
    3078             :   0,
    3079             :   1,
    3080             :   2,
    3081             :   3,
    3082             :   4,
    3083             :   5,
    3084             :   6,
    3085             :   7,
    3086             :   8,
    3087             :   9,
    3088             :   10,
    3089             :   11,
    3090             :   12,
    3091             :   13,
    3092             :   14,
    3093             :   0,
    3094             :   1,
    3095             :   2,
    3096             :   3,
    3097             :   4,
    3098             :   5,
    3099             :   6,
    3100             :   7,
    3101             :   8,
    3102             :   9,
    3103             :   10,
    3104             :   11,
    3105             :   12,
    3106             :   12,
    3107             :   0,
    3108             :   2,
    3109             :   4,
    3110             :   6,
    3111             :   8,
    3112             :   10,
    3113             :   0,
    3114             :   1,
    3115             :   2,
    3116             :   3,
    3117             :   4,
    3118             :   5,
    3119             :   6,
    3120             :   7,
    3121             :   8,
    3122             :   9,
    3123             :   10,
    3124             :   11,
    3125             :   12,
    3126             :   13,
    3127             :   14,
    3128             :   15,
    3129             :   16,
    3130             :   17,
    3131             :   18,
    3132             :   19,
    3133             :   20,
    3134             :   21,
    3135             :   22,
    3136             :   23,
    3137             :   24,
    3138             :   25,
    3139             :   26,
    3140             :   27,
    3141             :   28,
    3142             :   29,
    3143             :   0,
    3144             :   1,
    3145             :   2,
    3146             :   3,
    3147             :   4,
    3148             :   5,
    3149             :   6,
    3150             :   7,
    3151             :   8,
    3152             :   9,
    3153             :   10,
    3154             :   11,
    3155             :   12,
    3156             :   13,
    3157             :   14,
    3158             :   15,
    3159             :   16,
    3160             :   17,
    3161             :   18,
    3162             :   19,
    3163             :   20,
    3164             :   21,
    3165             :   22,
    3166             :   23,
    3167             :   24,
    3168             :   25,
    3169             :   26,
    3170             :   27,
    3171             :   0,
    3172             :   1,
    3173             :   2,
    3174             :   3,
    3175             :   4,
    3176             :   5,
    3177             :   6,
    3178             :   7,
    3179             :   8,
    3180             :   9,
    3181             :   10,
    3182             :   11,
    3183             :   12,
    3184             :   13,
    3185             :   14,
    3186             :   15,
    3187             :   16,
    3188             :   17,
    3189             :   18,
    3190             :   19,
    3191             :   20,
    3192             :   21,
    3193             :   22,
    3194             :   23,
    3195             :   24,
    3196             :   25,
    3197             :   1,
    3198             :   3,
    3199             :   5,
    3200             :   7,
    3201             :   9,
    3202             :   11,
    3203             :   13,
    3204             :   15,
    3205             :   17,
    3206             :   19,
    3207             :   21,
    3208             :   23,
    3209             :   25,
    3210             :   27,
    3211             :   29,
    3212             :   1,
    3213             :   3,
    3214             :   5,
    3215             :   7,
    3216             :   9,
    3217             :   11,
    3218             :   13,
    3219             :   15,
    3220             :   17,
    3221             :   19,
    3222             :   21,
    3223             :   23,
    3224             :   25,
    3225             :   27,
    3226             : };
    3227             : static inline void InitARMMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
    3228        4399 :   RI->InitMCRegisterInfo(ARMRegDesc, 289, RA, PC, ARMMCRegisterClasses, 102, ARMRegUnitRoots, 77, ARMRegDiffLists, ARMLaneMaskLists, ARMRegStrings, ARMRegClassStrings, ARMSubRegIdxLists, 57,
    3229             : ARMSubRegIdxRanges, ARMRegEncodingTable);
    3230             : 
    3231             :   switch (DwarfFlavour) {
    3232             :   default:
    3233             :     llvm_unreachable("Unknown DWARF flavour");
    3234        4399 :   case 0:
    3235        4399 :     RI->mapDwarfRegsToLLVMRegs(ARMDwarfFlavour0Dwarf2L, ARMDwarfFlavour0Dwarf2LSize, false);
    3236             :     break;
    3237             :   }
    3238             :   switch (EHFlavour) {
    3239             :   default:
    3240             :     llvm_unreachable("Unknown DWARF flavour");
    3241        4399 :   case 0:
    3242        4399 :     RI->mapDwarfRegsToLLVMRegs(ARMEHFlavour0Dwarf2L, ARMEHFlavour0Dwarf2LSize, true);
    3243             :     break;
    3244             :   }
    3245             :   switch (DwarfFlavour) {
    3246             :   default:
    3247             :     llvm_unreachable("Unknown DWARF flavour");
    3248        4399 :   case 0:
    3249        4399 :     RI->mapLLVMRegsToDwarfRegs(ARMDwarfFlavour0L2Dwarf, ARMDwarfFlavour0L2DwarfSize, false);
    3250             :     break;
    3251             :   }
    3252             :   switch (EHFlavour) {
    3253             :   default:
    3254             :     llvm_unreachable("Unknown DWARF flavour");
    3255        4399 :   case 0:
    3256        4399 :     RI->mapLLVMRegsToDwarfRegs(ARMEHFlavour0L2Dwarf, ARMEHFlavour0L2DwarfSize, true);
    3257             :     break;
    3258             :   }
    3259             : }
    3260             : 
    3261             : } // end namespace llvm
    3262             : 
    3263             : #endif // GET_REGINFO_MC_DESC
    3264             : 
    3265             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
    3266             : |*                                                                            *|
    3267             : |* Register Information Header Fragment                                       *|
    3268             : |*                                                                            *|
    3269             : |* Automatically generated file, do not edit!                                 *|
    3270             : |*                                                                            *|
    3271             : \*===----------------------------------------------------------------------===*/
    3272             : 
    3273             : 
    3274             : #ifdef GET_REGINFO_HEADER
    3275             : #undef GET_REGINFO_HEADER
    3276             : 
    3277             : #include "llvm/Target/TargetRegisterInfo.h"
    3278             : 
    3279             : namespace llvm {
    3280             : 
    3281             : class ARMFrameLowering;
    3282             : 
    3283        4445 : struct ARMGenRegisterInfo : public TargetRegisterInfo {
    3284             :   explicit ARMGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0, unsigned PC = 0);
    3285             :   unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
    3286             :   LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
    3287             :   LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
    3288             :   const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
    3289             :   const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
    3290             :   unsigned getRegUnitWeight(unsigned RegUnit) const override;
    3291             :   unsigned getNumRegPressureSets() const override;
    3292             :   const char *getRegPressureSetName(unsigned Idx) const override;
    3293             :   unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
    3294             :   const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
    3295             :   const int *getRegUnitPressureSets(unsigned RegUnit) const override;
    3296             :   ArrayRef<const char *> getRegMaskNames() const override;
    3297             :   ArrayRef<const uint32_t *> getRegMasks() const override;
    3298             :   /// Devirtualized TargetFrameLowering.
    3299             :   static const ARMFrameLowering *getFrameLowering(
    3300             :       const MachineFunction &MF);
    3301             : };
    3302             : 
    3303             : namespace ARM { // Register classes
    3304             :   extern const TargetRegisterClass SPRRegClass;
    3305             :   extern const TargetRegisterClass GPRRegClass;
    3306             :   extern const TargetRegisterClass GPRwithAPSRRegClass;
    3307             :   extern const TargetRegisterClass SPR_8RegClass;
    3308             :   extern const TargetRegisterClass GPRnopcRegClass;
    3309             :   extern const TargetRegisterClass rGPRRegClass;
    3310             :   extern const TargetRegisterClass tGPRwithpcRegClass;
    3311             :   extern const TargetRegisterClass hGPRRegClass;
    3312             :   extern const TargetRegisterClass tGPRRegClass;
    3313             :   extern const TargetRegisterClass GPRnopc_and_hGPRRegClass;
    3314             :   extern const TargetRegisterClass hGPR_and_rGPRRegClass;
    3315             :   extern const TargetRegisterClass tcGPRRegClass;
    3316             :   extern const TargetRegisterClass tGPR_and_tcGPRRegClass;
    3317             :   extern const TargetRegisterClass CCRRegClass;
    3318             :   extern const TargetRegisterClass GPRspRegClass;
    3319             :   extern const TargetRegisterClass hGPR_and_tGPRwithpcRegClass;
    3320             :   extern const TargetRegisterClass hGPR_and_tcGPRRegClass;
    3321             :   extern const TargetRegisterClass DPRRegClass;
    3322             :   extern const TargetRegisterClass DPR_VFP2RegClass;
    3323             :   extern const TargetRegisterClass DPR_8RegClass;
    3324             :   extern const TargetRegisterClass GPRPairRegClass;
    3325             :   extern const TargetRegisterClass GPRPair_with_gsub_1_in_rGPRRegClass;
    3326             :   extern const TargetRegisterClass GPRPair_with_gsub_0_in_tGPRRegClass;
    3327             :   extern const TargetRegisterClass GPRPair_with_gsub_0_in_hGPRRegClass;
    3328             :   extern const TargetRegisterClass GPRPair_with_gsub_0_in_tcGPRRegClass;
    3329             :   extern const TargetRegisterClass GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClass;
    3330             :   extern const TargetRegisterClass GPRPair_with_gsub_1_in_tcGPRRegClass;
    3331             :   extern const TargetRegisterClass GPRPair_with_gsub_1_in_GPRspRegClass;
    3332             :   extern const TargetRegisterClass DPairSpcRegClass;
    3333             :   extern const TargetRegisterClass DPairSpc_with_ssub_0RegClass;
    3334             :   extern const TargetRegisterClass DPairSpc_with_ssub_4RegClass;
    3335             :   extern const TargetRegisterClass DPairSpc_with_dsub_0_in_DPR_8RegClass;
    3336             :   extern const TargetRegisterClass DPairSpc_with_dsub_2_in_DPR_8RegClass;
    3337             :   extern const TargetRegisterClass DPairRegClass;
    3338             :   extern const TargetRegisterClass DPair_with_ssub_0RegClass;
    3339             :   extern const TargetRegisterClass QPRRegClass;
    3340             :   extern const TargetRegisterClass DPair_with_ssub_2RegClass;
    3341             :   extern const TargetRegisterClass DPair_with_dsub_0_in_DPR_8RegClass;
    3342             :   extern const TargetRegisterClass QPR_VFP2RegClass;
    3343             :   extern const TargetRegisterClass DPair_with_dsub_1_in_DPR_8RegClass;
    3344             :   extern const TargetRegisterClass QPR_8RegClass;
    3345             :   extern const TargetRegisterClass DTripleRegClass;
    3346             :   extern const TargetRegisterClass DTripleSpcRegClass;
    3347             :   extern const TargetRegisterClass DTripleSpc_with_ssub_0RegClass;
    3348             :   extern const TargetRegisterClass DTriple_with_ssub_0RegClass;
    3349             :   extern const TargetRegisterClass DTriple_with_qsub_0_in_QPRRegClass;
    3350             :   extern const TargetRegisterClass DTriple_with_ssub_2RegClass;
    3351             :   extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
    3352             :   extern const TargetRegisterClass DTripleSpc_with_ssub_4RegClass;
    3353             :   extern const TargetRegisterClass DTriple_with_ssub_4RegClass;
    3354             :   extern const TargetRegisterClass DTripleSpc_with_ssub_8RegClass;
    3355             :   extern const TargetRegisterClass DTripleSpc_with_dsub_0_in_DPR_8RegClass;
    3356             :   extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8RegClass;
    3357             :   extern const TargetRegisterClass DTriple_with_qsub_0_in_QPR_VFP2RegClass;
    3358             :   extern const TargetRegisterClass DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
    3359             :   extern const TargetRegisterClass DTriple_with_dsub_1_in_DPR_8RegClass;
    3360             :   extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass;
    3361             :   extern const TargetRegisterClass DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClass;
    3362             :   extern const TargetRegisterClass DTripleSpc_with_dsub_2_in_DPR_8RegClass;
    3363             :   extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8RegClass;
    3364             :   extern const TargetRegisterClass DTripleSpc_with_dsub_4_in_DPR_8RegClass;
    3365             :   extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
    3366             :   extern const TargetRegisterClass DTriple_with_qsub_0_in_QPR_8RegClass;
    3367             :   extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClass;
    3368             :   extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass;
    3369             :   extern const TargetRegisterClass DQuadSpcRegClass;
    3370             :   extern const TargetRegisterClass DQuadSpc_with_ssub_0RegClass;
    3371             :   extern const TargetRegisterClass DQuadSpc_with_ssub_4RegClass;
    3372             :   extern const TargetRegisterClass DQuadSpc_with_ssub_8RegClass;
    3373             :   extern const TargetRegisterClass DQuadSpc_with_dsub_0_in_DPR_8RegClass;
    3374             :   extern const TargetRegisterClass DQuadSpc_with_dsub_2_in_DPR_8RegClass;
    3375             :   extern const TargetRegisterClass DQuadSpc_with_dsub_4_in_DPR_8RegClass;
    3376             :   extern const TargetRegisterClass DQuadRegClass;
    3377             :   extern const TargetRegisterClass DQuad_with_ssub_0RegClass;
    3378             :   extern const TargetRegisterClass DQuad_with_ssub_2RegClass;
    3379             :   extern const TargetRegisterClass QQPRRegClass;
    3380             :   extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
    3381             :   extern const TargetRegisterClass DQuad_with_ssub_4RegClass;
    3382             :   extern const TargetRegisterClass DQuad_with_ssub_6RegClass;
    3383             :   extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8RegClass;
    3384             :   extern const TargetRegisterClass DQuad_with_qsub_0_in_QPR_VFP2RegClass;
    3385             :   extern const TargetRegisterClass DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
    3386             :   extern const TargetRegisterClass DQuad_with_dsub_1_in_DPR_8RegClass;
    3387             :   extern const TargetRegisterClass DQuad_with_qsub_1_in_QPR_VFP2RegClass;
    3388             :   extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass;
    3389             :   extern const TargetRegisterClass DQuad_with_dsub_2_in_DPR_8RegClass;
    3390             :   extern const TargetRegisterClass DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
    3391             :   extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8RegClass;
    3392             :   extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
    3393             :   extern const TargetRegisterClass DQuad_with_qsub_0_in_QPR_8RegClass;
    3394             :   extern const TargetRegisterClass DQuad_with_qsub_1_in_QPR_8RegClass;
    3395             :   extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass;
    3396             :   extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
    3397             :   extern const TargetRegisterClass QQQQPRRegClass;
    3398             :   extern const TargetRegisterClass QQQQPR_with_ssub_0RegClass;
    3399             :   extern const TargetRegisterClass QQQQPR_with_ssub_4RegClass;
    3400             :   extern const TargetRegisterClass QQQQPR_with_ssub_8RegClass;
    3401             :   extern const TargetRegisterClass QQQQPR_with_ssub_12RegClass;
    3402             :   extern const TargetRegisterClass QQQQPR_with_dsub_0_in_DPR_8RegClass;
    3403             :   extern const TargetRegisterClass QQQQPR_with_dsub_2_in_DPR_8RegClass;
    3404             :   extern const TargetRegisterClass QQQQPR_with_dsub_4_in_DPR_8RegClass;
    3405             :   extern const TargetRegisterClass QQQQPR_with_dsub_6_in_DPR_8RegClass;
    3406             : } // end namespace ARM
    3407             : 
    3408             : } // end namespace llvm
    3409             : 
    3410             : #endif // GET_REGINFO_HEADER
    3411             : 
    3412             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
    3413             : |*                                                                            *|
    3414             : |* Target Register and Register Classes Information                           *|
    3415             : |*                                                                            *|
    3416             : |* Automatically generated file, do not edit!                                 *|
    3417             : |*                                                                            *|
    3418             : \*===----------------------------------------------------------------------===*/
    3419             : 
    3420             : 
    3421             : #ifdef GET_REGINFO_TARGET_DESC
    3422             : #undef GET_REGINFO_TARGET_DESC
    3423             : 
    3424             : namespace llvm {
    3425             : 
    3426             : extern const MCRegisterClass ARMMCRegisterClasses[];
    3427             : 
    3428             : static const MVT::SimpleValueType VTLists[] = {
    3429             :   /* 0 */ MVT::i32, MVT::Other,
    3430             :   /* 2 */ MVT::f32, MVT::Other,
    3431             :   /* 4 */ MVT::v2i64, MVT::Other,
    3432             :   /* 6 */ MVT::v4i64, MVT::Other,
    3433             :   /* 8 */ MVT::v8i64, MVT::Other,
    3434             :   /* 10 */ MVT::f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64, MVT::v2f32, MVT::v4f16, MVT::Other,
    3435             :   /* 18 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::v8f16, MVT::Other,
    3436             :   /* 26 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::Other,
    3437             :   /* 33 */ MVT::Untyped, MVT::Other,
    3438             : };
    3439             : 
    3440             : static const char *const SubRegIndexNameTable[] = { "dsub_0", "dsub_1", "dsub_2", "dsub_3", "dsub_4", "dsub_5", "dsub_6", "dsub_7", "gsub_0", "gsub_1", "qqsub_0", "qqsub_1", "qsub_0", "qsub_1", "qsub_2", "qsub_3", "ssub_0", "ssub_1", "ssub_2", "ssub_3", "ssub_4", "ssub_5", "ssub_6", "ssub_7", "ssub_8", "ssub_9", "ssub_10", "ssub_11", "ssub_12", "ssub_13", "dsub_7_then_ssub_0", "dsub_7_then_ssub_1", "ssub_0_ssub_1_ssub_4_ssub_5", "ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5", "ssub_2_ssub_3_ssub_6_ssub_7", "ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7", "ssub_2_ssub_3_ssub_4_ssub_5", "ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9", "ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13", "ssub_2_ssub_3_ssub_6_ssub_7_dsub_5", "ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7", "ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9", "ssub_4_ssub_5_ssub_8_ssub_9", "ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9", "ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13", "ssub_6_ssub_7_dsub_5", "ssub_6_ssub_7_ssub_8_ssub_9_dsub_5", "ssub_6_ssub_7_dsub_5_dsub_7", "ssub_6_ssub_7_ssub_8_ssub_9", "ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13", "ssub_8_ssub_9_ssub_12_ssub_13", "ssub_8_ssub_9_dsub_5_ssub_12_ssub_13", "dsub_5_dsub_7", "dsub_5_ssub_12_ssub_13_dsub_7", "dsub_5_ssub_12_ssub_13", "ssub_4_ssub_5_ssub_6_ssub_7_qsub_2", "" };
    3441             : 
    3442             : 
    3443             : static const LaneBitmask SubRegIndexLaneMaskTable[] = {
    3444             :   LaneBitmask::getAll(),
    3445             :   LaneBitmask(0x0000000C), // dsub_0
    3446             :   LaneBitmask(0x00000030), // dsub_1
    3447             :   LaneBitmask(0x000000C0), // dsub_2
    3448             :   LaneBitmask(0x00000300), // dsub_3
    3449             :   LaneBitmask(0x00000C00), // dsub_4
    3450             :   LaneBitmask(0x00003000), // dsub_5
    3451             :   LaneBitmask(0x0000C000), // dsub_6
    3452             :   LaneBitmask(0x00030000), // dsub_7
    3453             :   LaneBitmask(0x00000001), // gsub_0
    3454             :   LaneBitmask(0x00000002), // gsub_1
    3455             :   LaneBitmask(0x000003FC), // qqsub_0
    3456             :   LaneBitmask(0x0003FC00), // qqsub_1
    3457             :   LaneBitmask(0x0000003C), // qsub_0
    3458             :   LaneBitmask(0x000003C0), // qsub_1
    3459             :   LaneBitmask(0x00003C00), // qsub_2
    3460             :   LaneBitmask(0x0003C000), // qsub_3
    3461             :   LaneBitmask(0x00000004), // ssub_0
    3462             :   LaneBitmask(0x00000008), // ssub_1
    3463             :   LaneBitmask(0x00000010), // ssub_2
    3464             :   LaneBitmask(0x00000020), // ssub_3
    3465             :   LaneBitmask(0x00000040), // ssub_4
    3466             :   LaneBitmask(0x00000080), // ssub_5
    3467             :   LaneBitmask(0x00000100), // ssub_6
    3468             :   LaneBitmask(0x00000200), // ssub_7
    3469             :   LaneBitmask(0x00000400), // ssub_8
    3470             :   LaneBitmask(0x00000800), // ssub_9
    3471             :   LaneBitmask(0x00001000), // ssub_10
    3472             :   LaneBitmask(0x00002000), // ssub_11
    3473             :   LaneBitmask(0x00004000), // ssub_12
    3474             :   LaneBitmask(0x00008000), // ssub_13
    3475             :   LaneBitmask(0x00010000), // dsub_7_then_ssub_0
    3476             :   LaneBitmask(0x00020000), // dsub_7_then_ssub_1
    3477             :   LaneBitmask(0x000000CC), // ssub_0_ssub_1_ssub_4_ssub_5
    3478             :   LaneBitmask(0x000000FC), // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    3479             :   LaneBitmask(0x00000330), // ssub_2_ssub_3_ssub_6_ssub_7
    3480             :   LaneBitmask(0x000003F0), // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    3481             :   LaneBitmask(0x000000F0), // ssub_2_ssub_3_ssub_4_ssub_5
    3482             :   LaneBitmask(0x00000CCC), // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    3483             :   LaneBitmask(0x0000CCCC), // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    3484             :   LaneBitmask(0x00003330), // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    3485             :   LaneBitmask(0x00033330), // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    3486             :   LaneBitmask(0x00000FF0), // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    3487             :   LaneBitmask(0x00000CC0), // ssub_4_ssub_5_ssub_8_ssub_9
    3488             :   LaneBitmask(0x00000FC0), // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    3489             :   LaneBitmask(0x0000CCC0), // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    3490             :   LaneBitmask(0x00003300), // ssub_6_ssub_7_dsub_5
    3491             :   LaneBitmask(0x00003F00), // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    3492             :   LaneBitmask(0x00033300), // ssub_6_ssub_7_dsub_5_dsub_7
    3493             :   LaneBitmask(0x00000F00), // ssub_6_ssub_7_ssub_8_ssub_9
    3494             :   LaneBitmask(0x0000FF00), // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    3495             :   LaneBitmask(0x0000CC00), // ssub_8_ssub_9_ssub_12_ssub_13
    3496             :   LaneBitmask(0x0000FC00), // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    3497             :   LaneBitmask(0x00033000), // dsub_5_dsub_7
    3498             :   LaneBitmask(0x0003F000), // dsub_5_ssub_12_ssub_13_dsub_7
    3499             :   LaneBitmask(0x0000F000), // dsub_5_ssub_12_ssub_13
    3500             :   LaneBitmask(0x00003FC0), // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    3501       72306 :  };
    3502             : 
    3503             : 
    3504             : 
    3505             : static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
    3506             : 
    3507             : static const uint32_t SPRSubClassMask[] = {
    3508             :   0x00000009, 0x00000000, 0x00000000, 0x00000000, 
    3509             :   0xe00c0000, 0xffff59f5, 0xdfffe6fd, 0x0000003f, // ssub_0
    3510             :   0xe00c0000, 0xffff59f5, 0xdfffe6fd, 0x0000003f, // ssub_1
    3511             :   0x00000000, 0xebb241f0, 0xdffde401, 0x0000003f, // ssub_2
    3512             :   0x00000000, 0xebb241f0, 0xdffde401, 0x0000003f, // ssub_3
    3513             :   0xc0000000, 0xff9f0001, 0x9ffce0f9, 0x0000003f, // ssub_4
    3514             :   0xc0000000, 0xff9f0001, 0x9ffce0f9, 0x0000003f, // ssub_5
    3515             :   0x00000000, 0x00000000, 0x9fecc000, 0x0000003f, // ssub_6
    3516             :   0x00000000, 0x00000000, 0x9fecc000, 0x0000003f, // ssub_7
    3517             :   0x00000000, 0x140c0000, 0x000000f0, 0x0000003f, // ssub_8
    3518             :   0x00000000, 0x140c0000, 0x000000f0, 0x0000003f, // ssub_9
    3519             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_10
    3520             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_11
    3521             :   0x00000000, 0x00000000, 0x00000000, 0x0000003e, // ssub_12
    3522             :   0x00000000, 0x00000000, 0x00000000, 0x0000003e, // ssub_13
    3523             :   0x00000000, 0x00000000, 0x00000000, 0x0000003e, // dsub_7_then_ssub_0
    3524             :   0x00000000, 0x00000000, 0x00000000, 0x0000003e, // dsub_7_then_ssub_1
    3525             : };
    3526             : 
    3527             : static const uint32_t GPRSubClassMask[] = {
    3528             :   0x0001dff2, 0x00000000, 0x00000000, 0x00000000, 
    3529             :   0x0ff00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
    3530             :   0x0ff00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
    3531             : };
    3532             : 
    3533             : static const uint32_t GPRwithAPSRSubClassMask[] = {
    3534             :   0x00015f34, 0x00000000, 0x00000000, 0x00000000, 
    3535             :   0x0ff00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
    3536             :   0x0ff00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
    3537             : };
    3538             : 
    3539             : static const uint32_t SPR_8SubClassMask[] = {
    3540             :   0x00000008, 0x00000000, 0x00000000, 0x00000000, 
    3541             :   0x80080000, 0xfc9801a1, 0x1fa480e1, 0x0000003c, // ssub_0
    3542             :   0x80080000, 0xfc9801a1, 0x1fa480e1, 0x0000003c, // ssub_1
    3543             :   0x00000000, 0xc8800180, 0x1ea40001, 0x0000003c, // ssub_2
    3544             :   0x00000000, 0xc8800180, 0x1ea40001, 0x0000003c, // ssub_3
    3545             :   0x00000000, 0x9c000001, 0x1ca000c1, 0x00000038, // ssub_4
    3546             :   0x00000000, 0x9c000001, 0x1ca000c1, 0x00000038, // ssub_5
    3547             :   0x00000000, 0x00000000, 0x14800000, 0x00000038, // ssub_6
    3548             :   0x00000000, 0x00000000, 0x14800000, 0x00000038, // ssub_7
    3549             :   0x00000000, 0x10000000, 0x00000080, 0x00000030, // ssub_8
    3550             :   0x00000000, 0x10000000, 0x00000080, 0x00000030, // ssub_9
    3551             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_10
    3552             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_11
    3553             :   0x00000000, 0x00000000, 0x00000000, 0x00000020, // ssub_12
    3554             :   0x00000000, 0x00000000, 0x00000000, 0x00000020, // ssub_13
    3555             :   0x00000000, 0x00000000, 0x00000000, 0x00000020, // dsub_7_then_ssub_0
    3556             :   0x00000000, 0x00000000, 0x00000000, 0x00000020, // dsub_7_then_ssub_1
    3557             : };
    3558             : 
    3559             : static const uint32_t GPRnopcSubClassMask[] = {
    3560             :   0x00015f30, 0x00000000, 0x00000000, 0x00000000, 
    3561             :   0x0ff00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
    3562             :   0x0ff00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
    3563             : };
    3564             : 
    3565             : static const uint32_t rGPRSubClassMask[] = {
    3566             :   0x00011d20, 0x00000000, 0x00000000, 0x00000000, 
    3567             :   0x0ff00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
    3568             :   0x06600000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
    3569             : };
    3570             : 
    3571             : static const uint32_t tGPRwithpcSubClassMask[] = {
    3572             :   0x00009140, 0x00000000, 0x00000000, 0x00000000, 
    3573             :   0x04400000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
    3574             :   0x04400000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
    3575             : };
    3576             : 
    3577             : static const uint32_t hGPRSubClassMask[] = {
    3578             :   0x0001c680, 0x00000000, 0x00000000, 0x00000000, 
    3579             :   0x0a800000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
    3580             :   0x0a800000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
    3581             : };
    3582             : 
    3583             : static const uint32_t tGPRSubClassMask[] = {
    3584             :   0x00001100, 0x00000000, 0x00000000, 0x00000000, 
    3585             :   0x04400000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
    3586             :   0x04400000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
    3587             : };
    3588             : 
    3589             : static const uint32_t GPRnopc_and_hGPRSubClassMask[] = {
    3590             :   0x00014600, 0x00000000, 0x00000000, 0x00000000, 
    3591             :   0x0a800000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
    3592             :   0x0a800000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
    3593             : };
    3594             : 
    3595             : static const uint32_t hGPR_and_rGPRSubClassMask[] = {
    3596             :   0x00010400, 0x00000000, 0x00000000, 0x00000000, 
    3597             :   0x0a800000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
    3598             :   0x02000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
    3599             : };
    3600             : 
    3601             : static const uint32_t tcGPRSubClassMask[] = {
    3602             :   0x00011800, 0x00000000, 0x00000000, 0x00000000, 
    3603             :   0x0d000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
    3604             :   0x04000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
    3605             : };
    3606             : 
    3607             : static const uint32_t tGPR_and_tcGPRSubClassMask[] = {
    3608             :   0x00001000, 0x00000000, 0x00000000, 0x00000000, 
    3609             :   0x04000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
    3610             :   0x04000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
    3611             : };
    3612             : 
    3613             : static const uint32_t CCRSubClassMask[] = {
    3614             :   0x00002000, 0x00000000, 0x00000000, 0x00000000, 
    3615             : };
    3616             : 
    3617             : static const uint32_t GPRspSubClassMask[] = {
    3618             :   0x00004000, 0x00000000, 0x00000000, 0x00000000, 
    3619             :   0x08000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
    3620             : };
    3621             : 
    3622             : static const uint32_t hGPR_and_tGPRwithpcSubClassMask[] = {
    3623             :   0x00008000, 0x00000000, 0x00000000, 0x00000000, 
    3624             : };
    3625             : 
    3626             : static const uint32_t hGPR_and_tcGPRSubClassMask[] = {
    3627             :   0x00010000, 0x00000000, 0x00000000, 0x00000000, 
    3628             :   0x08000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
    3629             : };
    3630             : 
    3631             : static const uint32_t DPRSubClassMask[] = {
    3632             :   0x000e0000, 0x00000000, 0x00000000, 0x00000000, 
    3633             :   0xf0000000, 0xffffffff, 0xffffffff, 0x0000003f, // dsub_0
    3634             :   0x00000000, 0xebf2f3fe, 0xffffff01, 0x0000003f, // dsub_1
    3635             :   0xf0000000, 0xfffffe01, 0xffffffff, 0x0000003f, // dsub_2
    3636             :   0x00000000, 0x00000000, 0xffffff00, 0x0000003f, // dsub_3
    3637             :   0x00000000, 0x140d0c00, 0xe00000fe, 0x0000003f, // dsub_4
    3638             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // dsub_5
    3639             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // dsub_6
    3640             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // dsub_7
    3641             : };
    3642             : 
    3643             : static const uint32_t DPR_VFP2SubClassMask[] = {
    3644             :   0x000c0000, 0x00000000, 0x00000000, 0x00000000, 
    3645             :   0xe0000000, 0xffff59f5, 0xdfffe6fd, 0x0000003f, // dsub_0
    3646             :   0x00000000, 0xebb241f0, 0xdffde401, 0x0000003f, // dsub_1
    3647             :   0xc0000000, 0xff9f0001, 0x9ffce0f9, 0x0000003f, // dsub_2
    3648             :   0x00000000, 0x00000000, 0x9fecc000, 0x0000003f, // dsub_3
    3649             :   0x00000000, 0x140c0000, 0x000000f0, 0x0000003f, // dsub_4
    3650             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // dsub_5
    3651             :   0x00000000, 0x00000000, 0x00000000, 0x0000003e, // dsub_6
    3652             :   0x00000000, 0x00000000, 0x00000000, 0x0000003e, // dsub_7
    3653             : };
    3654             : 
    3655             : static const uint32_t DPR_8SubClassMask[] = {
    3656             :   0x00080000, 0x00000000, 0x00000000, 0x00000000, 
    3657             :   0x80000000, 0xfc9801a1, 0x1fa480e1, 0x0000003c, // dsub_0
    3658             :   0x00000000, 0xc8800180, 0x1ea40001, 0x0000003c, // dsub_1
    3659             :   0x00000000, 0x9c000001, 0x1ca000c1, 0x00000038, // dsub_2
    3660             :   0x00000000, 0x00000000, 0x14800000, 0x00000038, // dsub_3
    3661             :   0x00000000, 0x10000000, 0x00000080, 0x00000030, // dsub_4
    3662             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // dsub_5
    3663             :   0x00000000, 0x00000000, 0x00000000, 0x00000020, // dsub_6
    3664             :   0x00000000, 0x00000000, 0x00000000, 0x00000020, // dsub_7
    3665             : };
    3666             : 
    3667             : static const uint32_t GPRPairSubClassMask[] = {
    3668             :   0x0ff00000, 0x00000000, 0x00000000, 0x00000000, 
    3669             : };
    3670             : 
    3671             : static const uint32_t GPRPair_with_gsub_1_in_rGPRSubClassMask[] = {
    3672             :   0x06600000, 0x00000000, 0x00000000, 0x00000000, 
    3673             : };
    3674             : 
    3675             : static const uint32_t GPRPair_with_gsub_0_in_tGPRSubClassMask[] = {
    3676             :   0x04400000, 0x00000000, 0x00000000, 0x00000000, 
    3677             : };
    3678             : 
    3679             : static const uint32_t GPRPair_with_gsub_0_in_hGPRSubClassMask[] = {
    3680             :   0x0a800000, 0x00000000, 0x00000000, 0x00000000, 
    3681             : };
    3682             : 
    3683             : static const uint32_t GPRPair_with_gsub_0_in_tcGPRSubClassMask[] = {
    3684             :   0x0d000000, 0x00000000, 0x00000000, 0x00000000, 
    3685             : };
    3686             : 
    3687             : static const uint32_t GPRPair_with_gsub_1_in_hGPR_and_rGPRSubClassMask[] = {
    3688             :   0x02000000, 0x00000000, 0x00000000, 0x00000000, 
    3689             : };
    3690             : 
    3691             : static const uint32_t GPRPair_with_gsub_1_in_tcGPRSubClassMask[] = {
    3692             :   0x04000000, 0x00000000, 0x00000000, 0x00000000, 
    3693             : };
    3694             : 
    3695             : static const uint32_t GPRPair_with_gsub_1_in_GPRspSubClassMask[] = {
    3696             :   0x08000000, 0x00000000, 0x00000000, 0x00000000, 
    3697             : };
    3698             : 
    3699             : static const uint32_t DPairSpcSubClassMask[] = {
    3700             :   0xf0000000, 0x00000001, 0x00000000, 0x00000000, 
    3701             :   0x00000000, 0xfffffe00, 0xffffffff, 0x0000003f, // ssub_0_ssub_1_ssub_4_ssub_5
    3702             :   0x00000000, 0x00000000, 0xffffff00, 0x0000003f, // ssub_2_ssub_3_ssub_6_ssub_7
    3703             :   0x00000000, 0x140d0c00, 0xe00000fe, 0x0000003f, // ssub_4_ssub_5_ssub_8_ssub_9
    3704             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_6_ssub_7_dsub_5
    3705             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_8_ssub_9_ssub_12_ssub_13
    3706             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // dsub_5_dsub_7
    3707             : };
    3708             : 
    3709             : static const uint32_t DPairSpc_with_ssub_0SubClassMask[] = {
    3710             :   0xe0000000, 0x00000001, 0x00000000, 0x00000000, 
    3711             :   0x00000000, 0xffff5800, 0xdfffe6fd, 0x0000003f, // ssub_0_ssub_1_ssub_4_ssub_5
    3712             :   0x00000000, 0x00000000, 0xdffde400, 0x0000003f, // ssub_2_ssub_3_ssub_6_ssub_7
    3713             :   0x00000000, 0x140d0000, 0x800000f8, 0x0000003f, // ssub_4_ssub_5_ssub_8_ssub_9
    3714             :   0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_6_ssub_7_dsub_5
    3715             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_8_ssub_9_ssub_12_ssub_13
    3716             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // dsub_5_dsub_7
    3717             : };
    3718             : 
    3719             : static const uint32_t DPairSpc_with_ssub_4SubClassMask[] = {
    3720             :   0xc0000000, 0x00000001, 0x00000000, 0x00000000, 
    3721             :   0x00000000, 0xff9f0000, 0x9ffce0f9, 0x0000003f, // ssub_0_ssub_1_ssub_4_ssub_5
    3722             :   0x00000000, 0x00000000, 0x9fecc000, 0x0000003f, // ssub_2_ssub_3_ssub_6_ssub_7
    3723             :   0x00000000, 0x140c0000, 0x000000f0, 0x0000003f, // ssub_4_ssub_5_ssub_8_ssub_9
    3724             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_6_ssub_7_dsub_5
    3725             :   0x00000000, 0x00000000, 0x00000000, 0x0000003e, // ssub_8_ssub_9_ssub_12_ssub_13
    3726             :   0x00000000, 0x00000000, 0x00000000, 0x0000003e, // dsub_5_dsub_7
    3727             : };
    3728             : 
    3729             : static const uint32_t DPairSpc_with_dsub_0_in_DPR_8SubClassMask[] = {
    3730             :   0x80000000, 0x00000001, 0x00000000, 0x00000000, 
    3731             :   0x00000000, 0xfc980000, 0x1fa480e1, 0x0000003c, // ssub_0_ssub_1_ssub_4_ssub_5
    3732             :   0x00000000, 0x00000000, 0x1ea40000, 0x0000003c, // ssub_2_ssub_3_ssub_6_ssub_7
    3733             :   0x00000000, 0x14000000, 0x000000c0, 0x00000038, // ssub_4_ssub_5_ssub_8_ssub_9
    3734             :   0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_6_ssub_7_dsub_5
    3735             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_8_ssub_9_ssub_12_ssub_13
    3736             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // dsub_5_dsub_7
    3737             : };
    3738             : 
    3739             : static const uint32_t DPairSpc_with_dsub_2_in_DPR_8SubClassMask[] = {
    3740             :   0x00000000, 0x00000001, 0x00000000, 0x00000000, 
    3741             :   0x00000000, 0x9c000000, 0x1ca000c1, 0x00000038, // ssub_0_ssub_1_ssub_4_ssub_5
    3742             :   0x00000000, 0x00000000, 0x14800000, 0x00000038, // ssub_2_ssub_3_ssub_6_ssub_7
    3743             :   0x00000000, 0x10000000, 0x00000080, 0x00000030, // ssub_4_ssub_5_ssub_8_ssub_9
    3744             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_6_ssub_7_dsub_5
    3745             :   0x00000000, 0x00000000, 0x00000000, 0x00000020, // ssub_8_ssub_9_ssub_12_ssub_13
    3746             :   0x00000000, 0x00000000, 0x00000000, 0x00000020, // dsub_5_dsub_7
    3747             : };
    3748             : 
    3749             : static const uint32_t DPairSubClassMask[] = {
    3750             :   0x00000000, 0x000001fe, 0x00000000, 0x00000000, 
    3751             :   0x00000000, 0xebf2f200, 0xffffff01, 0x0000003f, // qsub_0
    3752             :   0x00000000, 0x00000000, 0xffffff00, 0x0000003f, // qsub_1
    3753             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // qsub_2
    3754             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // qsub_3
    3755             :   0x00000000, 0xebf2f200, 0xffffff01, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5
    3756             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9
    3757             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // dsub_5_ssub_12_ssub_13
    3758             : };
    3759             : 
    3760             : static const uint32_t DPair_with_ssub_0SubClassMask[] = {
    3761             :   0x00000000, 0x000001f4, 0x00000000, 0x00000000, 
    3762             :   0x00000000, 0xebf25000, 0xdfffe601, 0x0000003f, // qsub_0
    3763             :   0x00000000, 0x00000000, 0x9ffce000, 0x0000003f, // qsub_1
    3764             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // qsub_2
    3765             :   0x00000000, 0x00000000, 0x00000000, 0x0000003e, // qsub_3
    3766             :   0x00000000, 0xebb24000, 0xdffde401, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5
    3767             :   0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9
    3768             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // dsub_5_ssub_12_ssub_13
    3769             : };
    3770             : 
    3771             : static const uint32_t QPRSubClassMask[] = {
    3772             :   0x00000000, 0x00000148, 0x00000000, 0x00000000, 
    3773             :   0x00000000, 0xc2202000, 0xe6090800, 0x0000003f, // qsub_0
    3774             :   0x00000000, 0x00000000, 0xe6090800, 0x0000003f, // qsub_1
    3775             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // qsub_2
    3776             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // qsub_3
    3777             :   0x00000000, 0x21408000, 0x19521001, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5
    3778             : };
    3779             : 
    3780             : static const uint32_t DPair_with_ssub_2SubClassMask[] = {
    3781             :   0x00000000, 0x000001f0, 0x00000000, 0x00000000, 
    3782             :   0x00000000, 0xebb24000, 0xdffde401, 0x0000003f, // qsub_0
    3783             :   0x00000000, 0x00000000, 0x9fecc000, 0x0000003f, // qsub_1
    3784             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // qsub_2
    3785             :   0x00000000, 0x00000000, 0x00000000, 0x0000003e, // qsub_3
    3786             :   0x00000000, 0xeb920000, 0x9ffce001, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5
    3787             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9
    3788             :   0x00000000, 0x00000000, 0x00000000, 0x0000003e, // dsub_5_ssub_12_ssub_13
    3789             : };
    3790             : 
    3791             : static const uint32_t DPair_with_dsub_0_in_DPR_8SubClassMask[] = {
    3792             :   0x00000000, 0x000001a0, 0x00000000, 0x00000000, 
    3793             :   0x00000000, 0xe8900000, 0x1fa48001, 0x0000003c, // qsub_0
    3794             :   0x00000000, 0x00000000, 0x1ca00000, 0x00000038, // qsub_1
    3795             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // qsub_2
    3796             :   0x00000000, 0x00000000, 0x00000000, 0x00000020, // qsub_3
    3797             :   0x00000000, 0xc8800000, 0x1ea40001, 0x0000003c, // ssub_2_ssub_3_ssub_4_ssub_5
    3798             :   0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_6_ssub_7_ssub_8_ssub_9
    3799             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // dsub_5_ssub_12_ssub_13
    3800             : };
    3801             : 
    3802             : static const uint32_t QPR_VFP2SubClassMask[] = {
    3803             :   0x00000000, 0x00000140, 0x00000000, 0x00000000, 
    3804             :   0x00000000, 0xc2200000, 0xc6090000, 0x0000003f, // qsub_0
    3805             :   0x00000000, 0x00000000, 0x86080000, 0x0000003f, // qsub_1
    3806             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // qsub_2
    3807             :   0x00000000, 0x00000000, 0x00000000, 0x0000003e, // qsub_3
    3808             :   0x00000000, 0x21000000, 0x19500001, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5
    3809             : };
    3810             : 
    3811             : static const uint32_t DPair_with_dsub_1_in_DPR_8SubClassMask[] = {
    3812             :   0x00000000, 0x00000180, 0x00000000, 0x00000000, 
    3813             :   0x00000000, 0xc8800000, 0x1ea40001, 0x0000003c, // qsub_0
    3814             :   0x00000000, 0x00000000, 0x14800000, 0x00000038, // qsub_1
    3815             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // qsub_2
    3816             :   0x00000000, 0x00000000, 0x00000000, 0x00000020, // qsub_3
    3817             :   0x00000000, 0x88000000, 0x1ca00001, 0x00000038, // ssub_2_ssub_3_ssub_4_ssub_5
    3818             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_6_ssub_7_ssub_8_ssub_9
    3819             :   0x00000000, 0x00000000, 0x00000000, 0x00000020, // dsub_5_ssub_12_ssub_13
    3820             : };
    3821             : 
    3822             : static const uint32_t QPR_8SubClassMask[] = {
    3823             :   0x00000000, 0x00000100, 0x00000000, 0x00000000, 
    3824             :   0x00000000, 0xc0000000, 0x06000000, 0x0000003c, // qsub_0
    3825             :   0x00000000, 0x00000000, 0x04000000, 0x00000038, // qsub_1
    3826             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // qsub_2
    3827             :   0x00000000, 0x00000000, 0x00000000, 0x00000020, // qsub_3
    3828             :   0x00000000, 0x00000000, 0x18000001, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5
    3829             : };
    3830             : 
    3831             : static const uint32_t DTripleSubClassMask[] = {
    3832             :   0x00000000, 0xebf2f200, 0x00000001, 0x00000000, 
    3833             :   0x00000000, 0x00000000, 0xffffff00, 0x0000003f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    3834             :   0x00000000, 0x00000000, 0xffffff00, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    3835             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    3836             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    3837             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    3838             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // dsub_5_ssub_12_ssub_13_dsub_7
    3839             : };
    3840             : 
    3841             : static const uint32_t DTripleSpcSubClassMask[] = {
    3842             :   0x00000000, 0x140d0c00, 0x000000fe, 0x00000000, 
    3843             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    3844             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    3845             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    3846             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_6_ssub_7_dsub_5_dsub_7
    3847             : };
    3848             : 
    3849             : static const uint32_t DTripleSpc_with_ssub_0SubClassMask[] = {
    3850             :   0x00000000, 0x140d0800, 0x000000fc, 0x00000000, 
    3851             :   0x00000000, 0x00000000, 0xc0000000, 0x0000003f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    3852             :   0x00000000, 0x00000000, 0xc0000000, 0x0000003f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    3853             :   0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    3854             :   0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_6_ssub_7_dsub_5_dsub_7
    3855             : };
    3856             : 
    3857             : static const uint32_t DTriple_with_ssub_0SubClassMask[] = {
    3858             :   0x00000000, 0xebf25000, 0x00000001, 0x00000000, 
    3859             :   0x00000000, 0x00000000, 0xdfffe600, 0x0000003f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    3860             :   0x00000000, 0x00000000, 0xdffde400, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    3861             :   0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    3862             :   0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    3863             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    3864             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // dsub_5_ssub_12_ssub_13_dsub_7
    3865             : };
    3866             : 
    3867             : static const uint32_t DTriple_with_qsub_0_in_QPRSubClassMask[] = {
    3868             :   0x00000000, 0xc2202000, 0x00000000, 0x00000000, 
    3869             :   0x00000000, 0x00000000, 0xe6090800, 0x0000003f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    3870             :   0x00000000, 0x00000000, 0x19521000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    3871             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    3872             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    3873             : };
    3874             : 
    3875             : static const uint32_t DTriple_with_ssub_2SubClassMask[] = {
    3876             :   0x00000000, 0xebb24000, 0x00000001, 0x00000000, 
    3877             :   0x00000000, 0x00000000, 0xdffde400, 0x0000003f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    3878             :   0x00000000, 0x00000000, 0x9ffce000, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    3879             :   0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    3880             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    3881             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    3882             :   0x00000000, 0x00000000, 0x00000000, 0x0000003e, // dsub_5_ssub_12_ssub_13_dsub_7
    3883             : };
    3884             : 
    3885             : static const uint32_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
    3886             :   0x00000000, 0x21408000, 0x00000001, 0x00000000, 
    3887             :   0x00000000, 0x00000000, 0x19521000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    3888             :   0x00000000, 0x00000000, 0xe6090800, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    3889             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    3890             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // dsub_5_ssub_12_ssub_13_dsub_7
    3891             : };
    3892             : 
    3893             : static const uint32_t DTripleSpc_with_ssub_4SubClassMask[] = {
    3894             :   0x00000000, 0x140d0000, 0x000000f8, 0x00000000, 
    3895             :   0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    3896             :   0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    3897             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    3898             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_6_ssub_7_dsub_5_dsub_7
    3899             : };
    3900             : 
    3901             : static const uint32_t DTriple_with_ssub_4SubClassMask[] = {
    3902             :   0x00000000, 0xeb920000, 0x00000001, 0x00000000, 
    3903             :   0x00000000, 0x00000000, 0x9ffce000, 0x0000003f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    3904             :   0x00000000, 0x00000000, 0x9fecc000, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    3905             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    3906             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    3907             :   0x00000000, 0x00000000, 0x00000000, 0x0000003e, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    3908             :   0x00000000, 0x00000000, 0x00000000, 0x0000003e, // dsub_5_ssub_12_ssub_13_dsub_7
    3909             : };
    3910             : 
    3911             : static const uint32_t DTripleSpc_with_ssub_8SubClassMask[] = {
    3912             :   0x00000000, 0x140c0000, 0x000000f0, 0x00000000, 
    3913             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    3914             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    3915             :   0x00000000, 0x00000000, 0x00000000, 0x0000003e, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    3916             :   0x00000000, 0x00000000, 0x00000000, 0x0000003e, // ssub_6_ssub_7_dsub_5_dsub_7
    3917             : };
    3918             : 
    3919             : static const uint32_t DTripleSpc_with_dsub_0_in_DPR_8SubClassMask[] = {
    3920             :   0x00000000, 0x14080000, 0x000000e0, 0x00000000, 
    3921             :   0x00000000, 0x00000000, 0x00000000, 0x0000003c, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    3922             :   0x00000000, 0x00000000, 0x00000000, 0x0000003c, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    3923             :   0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    3924             :   0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_6_ssub_7_dsub_5_dsub_7
    3925             : };
    3926             : 
    3927             : static const uint32_t DTriple_with_dsub_0_in_DPR_8SubClassMask[] = {
    3928             :   0x00000000, 0xe8900000, 0x00000001, 0x00000000, 
    3929             :   0x00000000, 0x00000000, 0x1fa48000, 0x0000003c, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    3930             :   0x00000000, 0x00000000, 0x1ea40000, 0x0000003c, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    3931             :   0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    3932             :   0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    3933             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    3934             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // dsub_5_ssub_12_ssub_13_dsub_7
    3935             : };
    3936             : 
    3937             : static const uint32_t DTriple_with_qsub_0_in_QPR_VFP2SubClassMask[] = {
    3938             :   0x00000000, 0xc2200000, 0x00000000, 0x00000000, 
    3939             :   0x00000000, 0x00000000, 0xc6090000, 0x0000003f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    3940             :   0x00000000, 0x00000000, 0x19500000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    3941             :   0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    3942             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    3943             : };
    3944             : 
    3945             : static const uint32_t DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
    3946             :   0x00000000, 0x21400000, 0x00000001, 0x00000000, 
    3947             :   0x00000000, 0x00000000, 0x19520000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    3948             :   0x00000000, 0x00000000, 0xc6090000, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    3949             :   0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    3950             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // dsub_5_ssub_12_ssub_13_dsub_7
    3951             : };
    3952             : 
    3953             : static const uint32_t DTriple_with_dsub_1_in_DPR_8SubClassMask[] = {
    3954             :   0x00000000, 0xc8800000, 0x00000001, 0x00000000, 
    3955             :   0x00000000, 0x00000000, 0x1ea40000, 0x0000003c, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    3956             :   0x00000000, 0x00000000, 0x1ca00000, 0x00000038, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    3957             :   0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    3958             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    3959             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    3960             :   0x00000000, 0x00000000, 0x00000000, 0x00000020, // dsub_5_ssub_12_ssub_13_dsub_7
    3961             : };
    3962             : 
    3963             : static const uint32_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2SubClassMask[] = {
    3964             :   0x00000000, 0x21000000, 0x00000001, 0x00000000, 
    3965             :   0x00000000, 0x00000000, 0x19500000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    3966             :   0x00000000, 0x00000000, 0x86080000, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    3967             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    3968             :   0x00000000, 0x00000000, 0x00000000, 0x0000003e, // dsub_5_ssub_12_ssub_13_dsub_7
    3969             : };
    3970             : 
    3971             : static const uint32_t DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRSubClassMask[] = {
    3972             :   0x00000000, 0xc2000000, 0x00000000, 0x00000000, 
    3973             :   0x00000000, 0x00000000, 0x86080000, 0x0000003f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    3974             :   0x00000000, 0x00000000, 0x19400000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    3975             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    3976             :   0x00000000, 0x00000000, 0x00000000, 0x0000003e, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    3977             : };
    3978             : 
    3979             : static const uint32_t DTripleSpc_with_dsub_2_in_DPR_8SubClassMask[] = {
    3980             :   0x00000000, 0x14000000, 0x000000c0, 0x00000000, 
    3981             :   0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    3982             :   0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    3983             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    3984             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_6_ssub_7_dsub_5_dsub_7
    3985             : };
    3986             : 
    3987             : static const uint32_t DTriple_with_dsub_2_in_DPR_8SubClassMask[] = {
    3988             :   0x00000000, 0x88000000, 0x00000001, 0x00000000, 
    3989             :   0x00000000, 0x00000000, 0x1ca00000, 0x00000038, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    3990             :   0x00000000, 0x00000000, 0x14800000, 0x00000038, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    3991             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    3992             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    3993             :   0x00000000, 0x00000000, 0x00000000, 0x00000020, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    3994             :   0x00000000, 0x00000000, 0x00000000, 0x00000020, // dsub_5_ssub_12_ssub_13_dsub_7
    3995             : };
    3996             : 
    3997             : static const uint32_t DTripleSpc_with_dsub_4_in_DPR_8SubClassMask[] = {
    3998             :   0x00000000, 0x10000000, 0x00000080, 0x00000000, 
    3999             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    4000             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    4001             :   0x00000000, 0x00000000, 0x00000000, 0x00000020, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    4002             :   0x00000000, 0x00000000, 0x00000000, 0x00000020, // ssub_6_ssub_7_dsub_5_dsub_7
    4003             : };
    4004             : 
    4005             : static const uint32_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
    4006             :   0x00000000, 0x20000000, 0x00000001, 0x00000000, 
    4007             :   0x00000000, 0x00000000, 0x19000000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    4008             :   0x00000000, 0x00000000, 0x06000000, 0x0000003c, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    4009             :   0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    4010             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // dsub_5_ssub_12_ssub_13_dsub_7
    4011             : };
    4012             : 
    4013             : static const uint32_t DTriple_with_qsub_0_in_QPR_8SubClassMask[] = {
    4014             :   0x00000000, 0xc0000000, 0x00000000, 0x00000000, 
    4015             :   0x00000000, 0x00000000, 0x06000000, 0x0000003c, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    4016             :   0x00000000, 0x00000000, 0x18000000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    4017             :   0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    4018             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    4019             : };
    4020             : 
    4021             : static const uint32_t DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRSubClassMask[] = {
    4022             :   0x00000000, 0x80000000, 0x00000000, 0x00000000, 
    4023             :   0x00000000, 0x00000000, 0x04000000, 0x00000038, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    4024             :   0x00000000, 0x00000000, 0x10000000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    4025             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    4026             :   0x00000000, 0x00000000, 0x00000000, 0x00000020, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    4027             : };
    4028             : 
    4029             : static const uint32_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8SubClassMask[] = {
    4030             :   0x00000000, 0x00000000, 0x00000001, 0x00000000, 
    4031             :   0x00000000, 0x00000000, 0x18000000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    4032             :   0x00000000, 0x00000000, 0x04000000, 0x00000038, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    4033             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    4034             :   0x00000000, 0x00000000, 0x00000000, 0x00000020, // dsub_5_ssub_12_ssub_13_dsub_7
    4035             : };
    4036             : 
    4037             : static const uint32_t DQuadSpcSubClassMask[] = {
    4038             :   0x00000000, 0x00000000, 0x000000fe, 0x00000000, 
    4039             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    4040             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    4041             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    4042             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_6_ssub_7_dsub_5_dsub_7
    4043             : };
    4044             : 
    4045             : static const uint32_t DQuadSpc_with_ssub_0SubClassMask[] = {
    4046             :   0x00000000, 0x00000000, 0x000000fc, 0x00000000, 
    4047             :   0x00000000, 0x00000000, 0xc0000000, 0x0000003f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    4048             :   0x00000000, 0x00000000, 0xc0000000, 0x0000003f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    4049             :   0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    4050             :   0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_6_ssub_7_dsub_5_dsub_7
    4051             : };
    4052             : 
    4053             : static const uint32_t DQuadSpc_with_ssub_4SubClassMask[] = {
    4054             :   0x00000000, 0x00000000, 0x000000f8, 0x00000000, 
    4055             :   0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    4056             :   0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    4057             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    4058             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_6_ssub_7_dsub_5_dsub_7
    4059             : };
    4060             : 
    4061             : static const uint32_t DQuadSpc_with_ssub_8SubClassMask[] = {
    4062             :   0x00000000, 0x00000000, 0x000000f0, 0x00000000, 
    4063             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    4064             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    4065             :   0x00000000, 0x00000000, 0x00000000, 0x0000003e, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    4066             :   0x00000000, 0x00000000, 0x00000000, 0x0000003e, // ssub_6_ssub_7_dsub_5_dsub_7
    4067             : };
    4068             : 
    4069             : static const uint32_t DQuadSpc_with_dsub_0_in_DPR_8SubClassMask[] = {
    4070             :   0x00000000, 0x00000000, 0x000000e0, 0x00000000, 
    4071             :   0x00000000, 0x00000000, 0x00000000, 0x0000003c, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    4072             :   0x00000000, 0x00000000, 0x00000000, 0x0000003c, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    4073             :   0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    4074             :   0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_6_ssub_7_dsub_5_dsub_7
    4075             : };
    4076             : 
    4077             : static const uint32_t DQuadSpc_with_dsub_2_in_DPR_8SubClassMask[] = {
    4078             :   0x00000000, 0x00000000, 0x000000c0, 0x00000000, 
    4079             :   0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    4080             :   0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    4081             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    4082             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_6_ssub_7_dsub_5_dsub_7
    4083             : };
    4084             : 
    4085             : static const uint32_t DQuadSpc_with_dsub_4_in_DPR_8SubClassMask[] = {
    4086             :   0x00000000, 0x00000000, 0x00000080, 0x00000000, 
    4087             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    4088             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    4089             :   0x00000000, 0x00000000, 0x00000000, 0x00000020, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    4090             :   0x00000000, 0x00000000, 0x00000000, 0x00000020, // ssub_6_ssub_7_dsub_5_dsub_7
    4091             : };
    4092             : 
    4093             : static const uint32_t DQuadSubClassMask[] = {
    4094             :   0x00000000, 0x00000000, 0x1fffff00, 0x00000000, 
    4095             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // qqsub_0
    4096             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // qqsub_1
    4097             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    4098             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    4099             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    4100             : };
    4101             : 
    4102             : static const uint32_t DQuad_with_ssub_0SubClassMask[] = {
    4103             :   0x00000000, 0x00000000, 0x1fffe600, 0x00000000, 
    4104             :   0x00000000, 0x00000000, 0xc0000000, 0x0000003f, // qqsub_0
    4105             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // qqsub_1
    4106             :   0x00000000, 0x00000000, 0xc0000000, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    4107             :   0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    4108             :   0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    4109             : };
    4110             : 
    4111             : static const uint32_t DQuad_with_ssub_2SubClassMask[] = {
    4112             :   0x00000000, 0x00000000, 0x1ffde400, 0x00000000, 
    4113             :   0x00000000, 0x00000000, 0xc0000000, 0x0000003f, // qqsub_0
    4114             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // qqsub_1
    4115             :   0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    4116             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    4117             :   0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    4118             : };
    4119             : 
    4120             : static const uint32_t QQPRSubClassMask[] = {
    4121             :   0x00000000, 0x00000000, 0x06090800, 0x00000000, 
    4122             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // qqsub_0
    4123             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // qqsub_1
    4124             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    4125             : };
    4126             : 
    4127             : static const uint32_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
    4128             :   0x00000000, 0x00000000, 0x19521000, 0x00000000, 
    4129             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    4130             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    4131             : };
    4132             : 
    4133             : static const uint32_t DQuad_with_ssub_4SubClassMask[] = {
    4134             :   0x00000000, 0x00000000, 0x1ffce000, 0x00000000, 
    4135             :   0x00000000, 0x00000000, 0x80000000, 0x0000003f, // qqsub_0
    4136             :   0x00000000, 0x00000000, 0x00000000, 0x0000003e, // qqsub_1
    4137             :   0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    4138             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    4139             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    4140             : };
    4141             : 
    4142             : static const uint32_t DQuad_with_ssub_6SubClassMask[] = {
    4143             :   0x00000000, 0x00000000, 0x1fecc000, 0x00000000, 
    4144             :   0x00000000, 0x00000000, 0x80000000, 0x0000003f, // qqsub_0
    4145             :   0x00000000, 0x00000000, 0x00000000, 0x0000003e, // qqsub_1
    4146             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    4147             :   0x00000000, 0x00000000, 0x00000000, 0x0000003e, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    4148             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    4149             : };
    4150             : 
    4151             : static const uint32_t DQuad_with_dsub_0_in_DPR_8SubClassMask[] = {
    4152             :   0x00000000, 0x00000000, 0x1fa48000, 0x00000000, 
    4153             :   0x00000000, 0x00000000, 0x00000000, 0x0000003c, // qqsub_0
    4154             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // qqsub_1
    4155             :   0x00000000, 0x00000000, 0x00000000, 0x0000003c, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    4156             :   0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    4157             :   0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    4158             : };
    4159             : 
    4160             : static const uint32_t DQuad_with_qsub_0_in_QPR_VFP2SubClassMask[] = {
    4161             :   0x00000000, 0x00000000, 0x06090000, 0x00000000, 
    4162             :   0x00000000, 0x00000000, 0xc0000000, 0x0000003f, // qqsub_0
    4163             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // qqsub_1
    4164             :   0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    4165             : };
    4166             : 
    4167             : static const uint32_t DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
    4168             :   0x00000000, 0x00000000, 0x19520000, 0x00000000, 
    4169             :   0x00000000, 0x00000000, 0xc0000000, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    4170             :   0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    4171             : };
    4172             : 
    4173             : static const uint32_t DQuad_with_dsub_1_in_DPR_8SubClassMask[] = {
    4174             :   0x00000000, 0x00000000, 0x1ea40000, 0x00000000, 
    4175             :   0x00000000, 0x00000000, 0x00000000, 0x0000003c, // qqsub_0
    4176             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // qqsub_1
    4177             :   0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    4178             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    4179             :   0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    4180             : };
    4181             : 
    4182             : static const uint32_t DQuad_with_qsub_1_in_QPR_VFP2SubClassMask[] = {
    4183             :   0x00000000, 0x00000000, 0x06080000, 0x00000000, 
    4184             :   0x00000000, 0x00000000, 0x80000000, 0x0000003f, // qqsub_0
    4185             :   0x00000000, 0x00000000, 0x00000000, 0x0000003e, // qqsub_1
    4186             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    4187             : };
    4188             : 
    4189             : static const uint32_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2SubClassMask[] = {
    4190             :   0x00000000, 0x00000000, 0x19500000, 0x00000000, 
    4191             :   0x00000000, 0x00000000, 0x80000000, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    4192             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    4193             : };
    4194             : 
    4195             : static const uint32_t DQuad_with_dsub_2_in_DPR_8SubClassMask[] = {
    4196             :   0x00000000, 0x00000000, 0x1ca00000, 0x00000000, 
    4197             :   0x00000000, 0x00000000, 0x00000000, 0x00000038, // qqsub_0
    4198             :   0x00000000, 0x00000000, 0x00000000, 0x00000020, // qqsub_1
    4199             :   0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    4200             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    4201             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    4202             : };
    4203             : 
    4204             : static const uint32_t DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
    4205             :   0x00000000, 0x00000000, 0x19400000, 0x00000000, 
    4206             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    4207             :   0x00000000, 0x00000000, 0x00000000, 0x0000003e, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    4208             : };
    4209             : 
    4210             : static const uint32_t DQuad_with_dsub_3_in_DPR_8SubClassMask[] = {
    4211             :   0x00000000, 0x00000000, 0x14800000, 0x00000000, 
    4212             :   0x00000000, 0x00000000, 0x00000000, 0x00000038, // qqsub_0
    4213             :   0x00000000, 0x00000000, 0x00000000, 0x00000020, // qqsub_1
    4214             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    4215             :   0x00000000, 0x00000000, 0x00000000, 0x00000020, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    4216             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    4217             : };
    4218             : 
    4219             : static const uint32_t DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
    4220             :   0x00000000, 0x00000000, 0x19000000, 0x00000000, 
    4221             :   0x00000000, 0x00000000, 0x00000000, 0x0000003c, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    4222             :   0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    4223             : };
    4224             : 
    4225             : static const uint32_t DQuad_with_qsub_0_in_QPR_8SubClassMask[] = {
    4226             :   0x00000000, 0x00000000, 0x06000000, 0x00000000, 
    4227             :   0x00000000, 0x00000000, 0x00000000, 0x0000003c, // qqsub_0
    4228             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // qqsub_1
    4229             :   0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    4230             : };
    4231             : 
    4232             : static const uint32_t DQuad_with_qsub_1_in_QPR_8SubClassMask[] = {
    4233             :   0x00000000, 0x00000000, 0x04000000, 0x00000000, 
    4234             :   0x00000000, 0x00000000, 0x00000000, 0x00000038, // qqsub_0
    4235             :   0x00000000, 0x00000000, 0x00000000, 0x00000020, // qqsub_1
    4236             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    4237             : };
    4238             : 
    4239             : static const uint32_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8SubClassMask[] = {
    4240             :   0x00000000, 0x00000000, 0x18000000, 0x00000000, 
    4241             :   0x00000000, 0x00000000, 0x00000000, 0x00000038, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    4242             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    4243             : };
    4244             : 
    4245             : static const uint32_t DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
    4246             :   0x00000000, 0x00000000, 0x10000000, 0x00000000, 
    4247             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    4248             :   0x00000000, 0x00000000, 0x00000000, 0x00000020, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    4249             : };
    4250             : 
    4251             : static const uint32_t QQQQPRSubClassMask[] = {
    4252             :   0x00000000, 0x00000000, 0xe0000000, 0x0000003f, 
    4253             : };
    4254             : 
    4255             : static const uint32_t QQQQPR_with_ssub_0SubClassMask[] = {
    4256             :   0x00000000, 0x00000000, 0xc0000000, 0x0000003f, 
    4257             : };
    4258             : 
    4259             : static const uint32_t QQQQPR_with_ssub_4SubClassMask[] = {
    4260             :   0x00000000, 0x00000000, 0x80000000, 0x0000003f, 
    4261             : };
    4262             : 
    4263             : static const uint32_t QQQQPR_with_ssub_8SubClassMask[] = {
    4264             :   0x00000000, 0x00000000, 0x00000000, 0x0000003f, 
    4265             : };
    4266             : 
    4267             : static const uint32_t QQQQPR_with_ssub_12SubClassMask[] = {
    4268             :   0x00000000, 0x00000000, 0x00000000, 0x0000003e, 
    4269             : };
    4270             : 
    4271             : static const uint32_t QQQQPR_with_dsub_0_in_DPR_8SubClassMask[] = {
    4272             :   0x00000000, 0x00000000, 0x00000000, 0x0000003c, 
    4273             : };
    4274             : 
    4275             : static const uint32_t QQQQPR_with_dsub_2_in_DPR_8SubClassMask[] = {
    4276             :   0x00000000, 0x00000000, 0x00000000, 0x00000038, 
    4277             : };
    4278             : 
    4279             : static const uint32_t QQQQPR_with_dsub_4_in_DPR_8SubClassMask[] = {
    4280             :   0x00000000, 0x00000000, 0x00000000, 0x00000030, 
    4281             : };
    4282             : 
    4283             : static const uint32_t QQQQPR_with_dsub_6_in_DPR_8SubClassMask[] = {
    4284             :   0x00000000, 0x00000000, 0x00000000, 0x00000020, 
    4285             : };
    4286             : 
    4287             : static const uint16_t SuperRegIdxSeqs[] = {
    4288             :   /* 0 */ 1, 2, 3, 4, 5, 6, 7, 8, 0,
    4289             :   /* 9 */ 9, 0,
    4290             :   /* 11 */ 9, 10, 0,
    4291             :   /* 14 */ 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 0,
    4292             :   /* 31 */ 13, 14, 15, 16, 37, 0,
    4293             :   /* 37 */ 38, 40, 45, 48, 0,
    4294             :   /* 42 */ 42, 50, 0,
    4295             :   /* 45 */ 34, 36, 44, 52, 0,
    4296             :   /* 50 */ 33, 35, 43, 46, 51, 53, 0,
    4297             :   /* 57 */ 34, 36, 47, 54, 0,
    4298             :   /* 62 */ 34, 36, 44, 47, 52, 54, 0,
    4299             :   /* 69 */ 13, 14, 15, 16, 37, 49, 55, 0,
    4300             :   /* 77 */ 11, 12, 56, 0,
    4301             :   /* 81 */ 11, 12, 42, 50, 56, 0,
    4302             : };
    4303             : 
    4304             : static const TargetRegisterClass *const SPR_8Superclasses[] = {
    4305             :   &ARM::SPRRegClass,
    4306             :   nullptr
    4307             : };
    4308             : 
    4309             : static const TargetRegisterClass *const GPRnopcSuperclasses[] = {
    4310             :   &ARM::GPRRegClass,
    4311             :   &ARM::GPRwithAPSRRegClass,
    4312             :   nullptr
    4313             : };
    4314             : 
    4315             : static const TargetRegisterClass *const rGPRSuperclasses[] = {
    4316             :   &ARM::GPRRegClass,
    4317             :   &ARM::GPRwithAPSRRegClass,
    4318             :   &ARM::GPRnopcRegClass,
    4319             :   nullptr
    4320             : };
    4321             : 
    4322             : static const TargetRegisterClass *const tGPRwithpcSuperclasses[] = {
    4323             :   &ARM::GPRRegClass,
    4324             :   nullptr
    4325             : };
    4326             : 
    4327             : static const TargetRegisterClass *const hGPRSuperclasses[] = {
    4328             :   &ARM::GPRRegClass,
    4329             :   nullptr
    4330             : };
    4331             : 
    4332             : static const TargetRegisterClass *const tGPRSuperclasses[] = {
    4333             :   &ARM::GPRRegClass,
    4334             :   &ARM::GPRwithAPSRRegClass,
    4335             :   &ARM::GPRnopcRegClass,
    4336             :   &ARM::rGPRRegClass,
    4337             :   &ARM::tGPRwithpcRegClass,
    4338             :   nullptr
    4339             : };
    4340             : 
    4341             : static const TargetRegisterClass *const GPRnopc_and_hGPRSuperclasses[] = {
    4342             :   &ARM::GPRRegClass,
    4343             :   &ARM::GPRwithAPSRRegClass,
    4344             :   &ARM::GPRnopcRegClass,
    4345             :   &ARM::hGPRRegClass,
    4346             :   nullptr
    4347             : };
    4348             : 
    4349             : static const TargetRegisterClass *const hGPR_and_rGPRSuperclasses[] = {
    4350             :   &ARM::GPRRegClass,
    4351             :   &ARM::GPRwithAPSRRegClass,
    4352             :   &ARM::GPRnopcRegClass,
    4353             :   &ARM::rGPRRegClass,
    4354             :   &ARM::hGPRRegClass,
    4355             :   &ARM::GPRnopc_and_hGPRRegClass,
    4356             :   nullptr
    4357             : };
    4358             : 
    4359             : static const TargetRegisterClass *const tcGPRSuperclasses[] = {
    4360             :   &ARM::GPRRegClass,
    4361             :   &ARM::GPRwithAPSRRegClass,
    4362             :   &ARM::GPRnopcRegClass,
    4363             :   &ARM::rGPRRegClass,
    4364             :   nullptr
    4365             : };
    4366             : 
    4367             : static const TargetRegisterClass *const tGPR_and_tcGPRSuperclasses[] = {
    4368             :   &ARM::GPRRegClass,
    4369             :   &ARM::GPRwithAPSRRegClass,
    4370             :   &ARM::GPRnopcRegClass,
    4371             :   &ARM::rGPRRegClass,
    4372             :   &ARM::tGPRwithpcRegClass,
    4373             :   &ARM::tGPRRegClass,
    4374             :   &ARM::tcGPRRegClass,
    4375             :   nullptr
    4376             : };
    4377             : 
    4378             : static const TargetRegisterClass *const GPRspSuperclasses[] = {
    4379             :   &ARM::GPRRegClass,
    4380             :   &ARM::GPRwithAPSRRegClass,
    4381             :   &ARM::GPRnopcRegClass,
    4382             :   &ARM::hGPRRegClass,
    4383             :   &ARM::GPRnopc_and_hGPRRegClass,
    4384             :   nullptr
    4385             : };
    4386             : 
    4387             : static const TargetRegisterClass *const hGPR_and_tGPRwithpcSuperclasses[] = {
    4388             :   &ARM::GPRRegClass,
    4389             :   &ARM::tGPRwithpcRegClass,
    4390             :   &ARM::hGPRRegClass,
    4391             :   nullptr
    4392             : };
    4393             : 
    4394             : static const TargetRegisterClass *const hGPR_and_tcGPRSuperclasses[] = {
    4395             :   &ARM::GPRRegClass,
    4396             :   &ARM::GPRwithAPSRRegClass,
    4397             :   &ARM::GPRnopcRegClass,
    4398             :   &ARM::rGPRRegClass,
    4399             :   &ARM::hGPRRegClass,
    4400             :   &ARM::GPRnopc_and_hGPRRegClass,
    4401             :   &ARM::hGPR_and_rGPRRegClass,
    4402             :   &ARM::tcGPRRegClass,
    4403             :   nullptr
    4404             : };
    4405             : 
    4406             : static const TargetRegisterClass *const DPR_VFP2Superclasses[] = {
    4407             :   &ARM::DPRRegClass,
    4408             :   nullptr
    4409             : };
    4410             : 
    4411             : static const TargetRegisterClass *const DPR_8Superclasses[] = {
    4412             :   &ARM::DPRRegClass,
    4413             :   &ARM::DPR_VFP2RegClass,
    4414             :   nullptr
    4415             : };
    4416             : 
    4417             : static const TargetRegisterClass *const GPRPair_with_gsub_1_in_rGPRSuperclasses[] = {
    4418             :   &ARM::GPRPairRegClass,
    4419             :   nullptr
    4420             : };
    4421             : 
    4422             : static const TargetRegisterClass *const GPRPair_with_gsub_0_in_tGPRSuperclasses[] = {
    4423             :   &ARM::GPRPairRegClass,
    4424             :   &ARM::GPRPair_with_gsub_1_in_rGPRRegClass,
    4425             :   nullptr
    4426             : };
    4427             : 
    4428             : static const TargetRegisterClass *const GPRPair_with_gsub_0_in_hGPRSuperclasses[] = {
    4429             :   &ARM::GPRPairRegClass,
    4430             :   nullptr
    4431             : };
    4432             : 
    4433             : static const TargetRegisterClass *const GPRPair_with_gsub_0_in_tcGPRSuperclasses[] = {
    4434             :   &ARM::GPRPairRegClass,
    4435             :   nullptr
    4436             : };
    4437             : 
    4438             : static const TargetRegisterClass *const GPRPair_with_gsub_1_in_hGPR_and_rGPRSuperclasses[] = {
    4439             :   &ARM::GPRPairRegClass,
    4440             :   &ARM::GPRPair_with_gsub_1_in_rGPRRegClass,
    4441             :   &ARM::GPRPair_with_gsub_0_in_hGPRRegClass,
    4442             :   nullptr
    4443             : };
    4444             : 
    4445             : static const TargetRegisterClass *const GPRPair_with_gsub_1_in_tcGPRSuperclasses[] = {
    4446             :   &ARM::GPRPairRegClass,
    4447             :   &ARM::GPRPair_with_gsub_1_in_rGPRRegClass,
    4448             :   &ARM::GPRPair_with_gsub_0_in_tGPRRegClass,
    4449             :   &ARM::GPRPair_with_gsub_0_in_tcGPRRegClass,
    4450             :   nullptr
    4451             : };
    4452             : 
    4453             : static const TargetRegisterClass *const GPRPair_with_gsub_1_in_GPRspSuperclasses[] = {
    4454             :   &ARM::GPRPairRegClass,
    4455             :   &ARM::GPRPair_with_gsub_0_in_hGPRRegClass,
    4456             :   &ARM::GPRPair_with_gsub_0_in_tcGPRRegClass,
    4457             :   nullptr
    4458             : };
    4459             : 
    4460             : static const TargetRegisterClass *const DPairSpc_with_ssub_0Superclasses[] = {
    4461             :   &ARM::DPairSpcRegClass,
    4462             :   nullptr
    4463             : };
    4464             : 
    4465             : static const TargetRegisterClass *const DPairSpc_with_ssub_4Superclasses[] = {
    4466             :   &ARM::DPairSpcRegClass,
    4467             :   &ARM::DPairSpc_with_ssub_0RegClass,
    4468             :   nullptr
    4469             : };
    4470             : 
    4471             : static const TargetRegisterClass *const DPairSpc_with_dsub_0_in_DPR_8Superclasses[] = {
    4472             :   &ARM::DPairSpcRegClass,
    4473             :   &ARM::DPairSpc_with_ssub_0RegClass,
    4474             :   &ARM::DPairSpc_with_ssub_4RegClass,
    4475             :   nullptr
    4476             : };
    4477             : 
    4478             : static const TargetRegisterClass *const DPairSpc_with_dsub_2_in_DPR_8Superclasses[] = {
    4479             :   &ARM::DPairSpcRegClass,
    4480             :   &ARM::DPairSpc_with_ssub_0RegClass,
    4481             :   &ARM::DPairSpc_with_ssub_4RegClass,
    4482             :   &ARM::DPairSpc_with_dsub_0_in_DPR_8RegClass,
    4483             :   nullptr
    4484             : };
    4485             : 
    4486             : static const TargetRegisterClass *const DPair_with_ssub_0Superclasses[] = {
    4487             :   &ARM::DPairRegClass,
    4488             :   nullptr
    4489             : };
    4490             : 
    4491             : static const TargetRegisterClass *const QPRSuperclasses[] = {
    4492             :   &ARM::DPairRegClass,
    4493             :   nullptr
    4494             : };
    4495             : 
    4496             : static const TargetRegisterClass *const DPair_with_ssub_2Superclasses[] = {
    4497             :   &ARM::DPairRegClass,
    4498             :   &ARM::DPair_with_ssub_0RegClass,
    4499             :   nullptr
    4500             : };
    4501             : 
    4502             : static const TargetRegisterClass *const DPair_with_dsub_0_in_DPR_8Superclasses[] = {
    4503             :   &ARM::DPairRegClass,
    4504             :   &ARM::DPair_with_ssub_0RegClass,
    4505             :   &ARM::DPair_with_ssub_2RegClass,
    4506             :   nullptr
    4507             : };
    4508             : 
    4509             : static const TargetRegisterClass *const QPR_VFP2Superclasses[] = {
    4510             :   &ARM::DPairRegClass,
    4511             :   &ARM::DPair_with_ssub_0RegClass,
    4512             :   &ARM::QPRRegClass,
    4513             :   &ARM::DPair_with_ssub_2RegClass,
    4514             :   nullptr
    4515             : };
    4516             : 
    4517             : static const TargetRegisterClass *const DPair_with_dsub_1_in_DPR_8Superclasses[] = {
    4518             :   &ARM::DPairRegClass,
    4519             :   &ARM::DPair_with_ssub_0RegClass,
    4520             :   &ARM::DPair_with_ssub_2RegClass,
    4521             :   &ARM::DPair_with_dsub_0_in_DPR_8RegClass,
    4522             :   nullptr
    4523             : };
    4524             : 
    4525             : static const TargetRegisterClass *const QPR_8Superclasses[] = {
    4526             :   &ARM::DPairRegClass,
    4527             :   &ARM::DPair_with_ssub_0RegClass,
    4528             :   &ARM::QPRRegClass,
    4529             :   &ARM::DPair_with_ssub_2RegClass,
    4530             :   &ARM::DPair_with_dsub_0_in_DPR_8RegClass,
    4531             :   &ARM::QPR_VFP2RegClass,
    4532             :   &ARM::DPair_with_dsub_1_in_DPR_8RegClass,
    4533             :   nullptr
    4534             : };
    4535             : 
    4536             : static const TargetRegisterClass *const DTripleSpc_with_ssub_0Superclasses[] = {
    4537             :   &ARM::DTripleSpcRegClass,
    4538             :   nullptr
    4539             : };
    4540             : 
    4541             : static const TargetRegisterClass *const DTriple_with_ssub_0Superclasses[] = {
    4542             :   &ARM::DTripleRegClass,
    4543             :   nullptr
    4544             : };
    4545             : 
    4546             : static const TargetRegisterClass *const DTriple_with_qsub_0_in_QPRSuperclasses[] = {
    4547             :   &ARM::DTripleRegClass,
    4548             :   nullptr
    4549             : };
    4550             : 
    4551             : static const TargetRegisterClass *const DTriple_with_ssub_2Superclasses[] = {
    4552             :   &ARM::DTripleRegClass,
    4553             :   &ARM::DTriple_with_ssub_0RegClass,
    4554             :   nullptr
    4555             : };
    4556             : 
    4557             : static const TargetRegisterClass *const DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
    4558             :   &ARM::DTripleRegClass,
    4559             :   nullptr
    4560             : };
    4561             : 
    4562             : static const TargetRegisterClass *const DTripleSpc_with_ssub_4Superclasses[] = {
    4563             :   &ARM::DTripleSpcRegClass,
    4564             :   &ARM::DTripleSpc_with_ssub_0RegClass,
    4565             :   nullptr
    4566             : };
    4567             : 
    4568             : static const TargetRegisterClass *const DTriple_with_ssub_4Superclasses[] = {
    4569             :   &ARM::DTripleRegClass,
    4570             :   &ARM::DTriple_with_ssub_0RegClass,
    4571             :   &ARM::DTriple_with_ssub_2RegClass,
    4572             :   nullptr
    4573             : };
    4574             : 
    4575             : static const TargetRegisterClass *const DTripleSpc_with_ssub_8Superclasses[] = {
    4576             :   &ARM::DTripleSpcRegClass,
    4577             :   &ARM::DTripleSpc_with_ssub_0RegClass,
    4578             :   &ARM::DTripleSpc_with_ssub_4RegClass,
    4579             :   nullptr
    4580             : };
    4581             : 
    4582             : static const TargetRegisterClass *const DTripleSpc_with_dsub_0_in_DPR_8Superclasses[] = {
    4583             :   &ARM::DTripleSpcRegClass,
    4584             :   &ARM::DTripleSpc_with_ssub_0RegClass,
    4585             :   &ARM::DTripleSpc_with_ssub_4RegClass,
    4586             :   &ARM::DTripleSpc_with_ssub_8RegClass,
    4587             :   nullptr
    4588             : };
    4589             : 
    4590             : static const TargetRegisterClass *const DTriple_with_dsub_0_in_DPR_8Superclasses[] = {
    4591             :   &ARM::DTripleRegClass,
    4592             :   &ARM::DTriple_with_ssub_0RegClass,
    4593             :   &ARM::DTriple_with_ssub_2RegClass,
    4594             :   &ARM::DTriple_with_ssub_4RegClass,
    4595             :   nullptr
    4596             : };
    4597             : 
    4598             : static const TargetRegisterClass *const DTriple_with_qsub_0_in_QPR_VFP2Superclasses[] = {
    4599             :   &ARM::DTripleRegClass,
    4600             :   &ARM::DTriple_with_ssub_0RegClass,
    4601             :   &ARM::DTriple_with_qsub_0_in_QPRRegClass,
    4602             :   &ARM::DTriple_with_ssub_2RegClass,
    4603             :   nullptr
    4604             : };
    4605             : 
    4606             : static const TargetRegisterClass *const DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
    4607             :   &ARM::DTripleRegClass,
    4608             :   &ARM::DTriple_with_ssub_0RegClass,
    4609             :   &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    4610             :   nullptr
    4611             : };
    4612             : 
    4613             : static const TargetRegisterClass *const DTriple_with_dsub_1_in_DPR_8Superclasses[] = {
    4614             :   &ARM::DTripleRegClass,
    4615             :   &ARM::DTriple_with_ssub_0RegClass,
    4616             :   &ARM::DTriple_with_ssub_2RegClass,
    4617             :   &ARM::DTriple_with_ssub_4RegClass,
    4618             :   &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
    4619             :   nullptr
    4620             : };
    4621             : 
    4622             : static const TargetRegisterClass *const DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Superclasses[] = {
    4623             :   &ARM::DTripleRegClass,
    4624             :   &ARM::DTriple_with_ssub_0RegClass,
    4625             :   &ARM::DTriple_with_ssub_2RegClass,
    4626             :   &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    4627             :   &ARM::DTriple_with_ssub_4RegClass,
    4628             :   &ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    4629             :   nullptr
    4630             : };
    4631             : 
    4632             : static const TargetRegisterClass *const DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRSuperclasses[] = {
    4633             :   &ARM::DTripleRegClass,
    4634             :   &ARM::DTriple_with_ssub_0RegClass,
    4635             :   &ARM::DTriple_with_qsub_0_in_QPRRegClass,
    4636             :   &ARM::DTriple_with_ssub_2RegClass,
    4637             :   &ARM::DTriple_with_ssub_4RegClass,
    4638             :   &ARM::DTriple_with_qsub_0_in_QPR_VFP2RegClass,
    4639             :   nullptr
    4640             : };
    4641             : 
    4642             : static const TargetRegisterClass *const DTripleSpc_with_dsub_2_in_DPR_8Superclasses[] = {
    4643             :   &ARM::DTripleSpcRegClass,
    4644             :   &ARM::DTripleSpc_with_ssub_0RegClass,
    4645             :   &ARM::DTripleSpc_with_ssub_4RegClass,
    4646             :   &ARM::DTripleSpc_with_ssub_8RegClass,
    4647             :   &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
    4648             :   nullptr
    4649             : };
    4650             : 
    4651             : static const TargetRegisterClass *const DTriple_with_dsub_2_in_DPR_8Superclasses[] = {
    4652             :   &ARM::DTripleRegClass,
    4653             :   &ARM::DTriple_with_ssub_0RegClass,
    4654             :   &ARM::DTriple_with_ssub_2RegClass,
    4655             :   &ARM::DTriple_with_ssub_4RegClass,
    4656             :   &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
    4657             :   &ARM::DTriple_with_dsub_1_in_DPR_8RegClass,
    4658             :   nullptr
    4659             : };
    4660             : 
    4661             : static const TargetRegisterClass *const DTripleSpc_with_dsub_4_in_DPR_8Superclasses[] = {
    4662             :   &ARM::DTripleSpcRegClass,
    4663             :   &ARM::DTripleSpc_with_ssub_0RegClass,
    4664             :   &ARM::DTripleSpc_with_ssub_4RegClass,
    4665             :   &ARM::DTripleSpc_with_ssub_8RegClass,
    4666             :   &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
    4667             :   &ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClass,
    4668             :   nullptr
    4669             : };
    4670             : 
    4671             : static const TargetRegisterClass *const DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
    4672             :   &ARM::DTripleRegClass,
    4673             :   &ARM::DTriple_with_ssub_0RegClass,
    4674             :   &ARM::DTriple_with_ssub_2RegClass,
    4675             :   &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    4676             :   &ARM::DTriple_with_ssub_4RegClass,
    4677             :   &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
    4678             :   &ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    4679             :   &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
    4680             :   nullptr
    4681             : };
    4682             : 
    4683             : static const TargetRegisterClass *const DTriple_with_qsub_0_in_QPR_8Superclasses[] = {
    4684             :   &ARM::DTripleRegClass,
    4685             :   &ARM::DTriple_with_ssub_0RegClass,
    4686             :   &ARM::DTriple_with_qsub_0_in_QPRRegClass,
    4687             :   &ARM::DTriple_with_ssub_2RegClass,
    4688             :   &ARM::DTriple_with_ssub_4RegClass,
    4689             :   &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
    4690             :   &ARM::DTriple_with_qsub_0_in_QPR_VFP2RegClass,
    4691             :   &ARM::DTriple_with_dsub_1_in_DPR_8RegClass,
    4692             :   &ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClass,
    4693             :   nullptr
    4694             : };
    4695             : 
    4696             : static const TargetRegisterClass *const DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRSuperclasses[] = {
    4697             :   &ARM::DTripleRegClass,
    4698             :   &ARM::DTriple_with_ssub_0RegClass,
    4699             :   &ARM::DTriple_with_qsub_0_in_QPRRegClass,
    4700             :   &ARM::DTriple_with_ssub_2RegClass,
    4701             :   &ARM::DTriple_with_ssub_4RegClass,
    4702             :   &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
    4703             :   &ARM::DTriple_with_qsub_0_in_QPR_VFP2RegClass,
    4704             :   &ARM::DTriple_with_dsub_1_in_DPR_8RegClass,
    4705             :   &ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClass,
    4706             :   &ARM::DTriple_with_dsub_2_in_DPR_8RegClass,
    4707             :   &ARM::DTriple_with_qsub_0_in_QPR_8RegClass,
    4708             :   nullptr
    4709             : };
    4710             : 
    4711             : static const TargetRegisterClass *const DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Superclasses[] = {
    4712             :   &ARM::DTripleRegClass,
    4713             :   &ARM::DTriple_with_ssub_0RegClass,
    4714             :   &ARM::DTriple_with_ssub_2RegClass,
    4715             :   &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    4716             :   &ARM::DTriple_with_ssub_4RegClass,
    4717             :   &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
    4718             :   &ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    4719             :   &ARM::DTriple_with_dsub_1_in_DPR_8RegClass,
    4720             :   &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
    4721             :   &ARM::DTriple_with_dsub_2_in_DPR_8RegClass,
    4722             :   &ARM::DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    4723             :   nullptr
    4724             : };
    4725             : 
    4726             : static const TargetRegisterClass *const DQuadSpcSuperclasses[] = {
    4727             :   &ARM::DTripleSpcRegClass,
    4728             :   nullptr
    4729             : };
    4730             : 
    4731             : static const TargetRegisterClass *const DQuadSpc_with_ssub_0Superclasses[] = {
    4732             :   &ARM::DTripleSpcRegClass,
    4733             :   &ARM::DTripleSpc_with_ssub_0RegClass,
    4734             :   &ARM::DQuadSpcRegClass,
    4735             :   nullptr
    4736             : };
    4737             : 
    4738             : static const TargetRegisterClass *const DQuadSpc_with_ssub_4Superclasses[] = {
    4739             :   &ARM::DTripleSpcRegClass,
    4740             :   &ARM::DTripleSpc_with_ssub_0RegClass,
    4741             :   &ARM::DTripleSpc_with_ssub_4RegClass,
    4742             :   &ARM::DQuadSpcRegClass,
    4743             :   &ARM::DQuadSpc_with_ssub_0RegClass,
    4744             :   nullptr
    4745             : };
    4746             : 
    4747             : static const TargetRegisterClass *const DQuadSpc_with_ssub_8Superclasses[] = {
    4748             :   &ARM::DTripleSpcRegClass,
    4749             :   &ARM::DTripleSpc_with_ssub_0RegClass,
    4750             :   &ARM::DTripleSpc_with_ssub_4RegClass,
    4751             :   &ARM::DTripleSpc_with_ssub_8RegClass,
    4752             :   &ARM::DQuadSpcRegClass,
    4753             :   &ARM::DQuadSpc_with_ssub_0RegClass,
    4754             :   &ARM::DQuadSpc_with_ssub_4RegClass,
    4755             :   nullptr
    4756             : };
    4757             : 
    4758             : static const TargetRegisterClass *const DQuadSpc_with_dsub_0_in_DPR_8Superclasses[] = {
    4759             :   &ARM::DTripleSpcRegClass,
    4760             :   &ARM::DTripleSpc_with_ssub_0RegClass,
    4761             :   &ARM::DTripleSpc_with_ssub_4RegClass,
    4762             :   &ARM::DTripleSpc_with_ssub_8RegClass,
    4763             :   &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
    4764             :   &ARM::DQuadSpcRegClass,
    4765             :   &ARM::DQuadSpc_with_ssub_0RegClass,
    4766             :   &ARM::DQuadSpc_with_ssub_4RegClass,
    4767             :   &ARM::DQuadSpc_with_ssub_8RegClass,
    4768             :   nullptr
    4769             : };
    4770             : 
    4771             : static const TargetRegisterClass *const DQuadSpc_with_dsub_2_in_DPR_8Superclasses[] = {
    4772             :   &ARM::DTripleSpcRegClass,
    4773             :   &ARM::DTripleSpc_with_ssub_0RegClass,
    4774             :   &ARM::DTripleSpc_with_ssub_4RegClass,
    4775             :   &ARM::DTripleSpc_with_ssub_8RegClass,
    4776             :   &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
    4777             :   &ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClass,
    4778             :   &ARM::DQuadSpcRegClass,
    4779             :   &ARM::DQuadSpc_with_ssub_0RegClass,
    4780             :   &ARM::DQuadSpc_with_ssub_4RegClass,
    4781             :   &ARM::DQuadSpc_with_ssub_8RegClass,
    4782             :   &ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClass,
    4783             :   nullptr
    4784             : };
    4785             : 
    4786             : static const TargetRegisterClass *const DQuadSpc_with_dsub_4_in_DPR_8Superclasses[] = {
    4787             :   &ARM::DTripleSpcRegClass,
    4788             :   &ARM::DTripleSpc_with_ssub_0RegClass,
    4789             :   &ARM::DTripleSpc_with_ssub_4RegClass,
    4790             :   &ARM::DTripleSpc_with_ssub_8RegClass,
    4791             :   &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
    4792             :   &ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClass,
    4793             :   &ARM::DTripleSpc_with_dsub_4_in_DPR_8RegClass,
    4794             :   &ARM::DQuadSpcRegClass,
    4795             :   &ARM::DQuadSpc_with_ssub_0RegClass,
    4796             :   &ARM::DQuadSpc_with_ssub_4RegClass,
    4797             :   &ARM::DQuadSpc_with_ssub_8RegClass,
    4798             :   &ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClass,
    4799             :   &ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClass,
    4800             :   nullptr
    4801             : };
    4802             : 
    4803             : static const TargetRegisterClass *const DQuad_with_ssub_0Superclasses[] = {
    4804             :   &ARM::DQuadRegClass,
    4805             :   nullptr
    4806             : };
    4807             : 
    4808             : static const TargetRegisterClass *const DQuad_with_ssub_2Superclasses[] = {
    4809             :   &ARM::DQuadRegClass,
    4810             :   &ARM::DQuad_with_ssub_0RegClass,
    4811             :   nullptr
    4812             : };
    4813             : 
    4814             : static const TargetRegisterClass *const QQPRSuperclasses[] = {
    4815             :   &ARM::DQuadRegClass,
    4816             :   nullptr
    4817             : };
    4818             : 
    4819             : static const TargetRegisterClass *const DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
    4820             :   &ARM::DQuadRegClass,
    4821             :   nullptr
    4822             : };
    4823             : 
    4824             : static const TargetRegisterClass *const DQuad_with_ssub_4Superclasses[] = {
    4825             :   &ARM::DQuadRegClass,
    4826             :   &ARM::DQuad_with_ssub_0RegClass,
    4827             :   &ARM::DQuad_with_ssub_2RegClass,
    4828             :   nullptr
    4829             : };
    4830             : 
    4831             : static const TargetRegisterClass *const DQuad_with_ssub_6Superclasses[] = {
    4832             :   &ARM::DQuadRegClass,
    4833             :   &ARM::DQuad_with_ssub_0RegClass,
    4834             :   &ARM::DQuad_with_ssub_2RegClass,
    4835             :   &ARM::DQuad_with_ssub_4RegClass,
    4836             :   nullptr
    4837             : };
    4838             : 
    4839             : static const TargetRegisterClass *const DQuad_with_dsub_0_in_DPR_8Superclasses[] = {
    4840             :   &ARM::DQuadRegClass,
    4841             :   &ARM::DQuad_with_ssub_0RegClass,
    4842             :   &ARM::DQuad_with_ssub_2RegClass,
    4843             :   &ARM::DQuad_with_ssub_4RegClass,
    4844             :   &ARM::DQuad_with_ssub_6RegClass,
    4845             :   nullptr
    4846             : };
    4847             : 
    4848             : static const TargetRegisterClass *const DQuad_with_qsub_0_in_QPR_VFP2Superclasses[] = {
    4849             :   &ARM::DQuadRegClass,
    4850             :   &ARM::DQuad_with_ssub_0RegClass,
    4851             :   &ARM::DQuad_with_ssub_2RegClass,
    4852             :   &ARM::QQPRRegClass,
    4853             :   nullptr
    4854             : };
    4855             : 
    4856             : static const TargetRegisterClass *const DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
    4857             :   &ARM::DQuadRegClass,
    4858             :   &ARM::DQuad_with_ssub_0RegClass,
    4859             :   &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    4860             :   nullptr
    4861             : };
    4862             : 
    4863             : static const TargetRegisterClass *const DQuad_with_dsub_1_in_DPR_8Superclasses[] = {
    4864             :   &ARM::DQuadRegClass,
    4865             :   &ARM::DQuad_with_ssub_0RegClass,
    4866             :   &ARM::DQuad_with_ssub_2RegClass,
    4867             :   &ARM::DQuad_with_ssub_4RegClass,
    4868             :   &ARM::DQuad_with_ssub_6RegClass,
    4869             :   &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
    4870             :   nullptr
    4871             : };
    4872             : 
    4873             : static const TargetRegisterClass *const DQuad_with_qsub_1_in_QPR_VFP2Superclasses[] = {
    4874             :   &ARM::DQuadRegClass,
    4875             :   &ARM::DQuad_with_ssub_0RegClass,
    4876             :   &ARM::DQuad_with_ssub_2RegClass,
    4877             :   &ARM::QQPRRegClass,
    4878             :   &ARM::DQuad_with_ssub_4RegClass,
    4879             :   &ARM::DQuad_with_ssub_6RegClass,
    4880             :   &ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClass,
    4881             :   nullptr
    4882             : };
    4883             : 
    4884             : static const TargetRegisterClass *const DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Superclasses[] = {
    4885             :   &ARM::DQuadRegClass,
    4886             :   &ARM::DQuad_with_ssub_0RegClass,
    4887             :   &ARM::DQuad_with_ssub_2RegClass,
    4888             :   &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    4889             :   &ARM::DQuad_with_ssub_4RegClass,
    4890             :   &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    4891             :   nullptr
    4892             : };
    4893             : 
    4894             : static const TargetRegisterClass *const DQuad_with_dsub_2_in_DPR_8Superclasses[] = {
    4895             :   &ARM::DQuadRegClass,
    4896             :   &ARM::DQuad_with_ssub_0RegClass,
    4897             :   &ARM::DQuad_with_ssub_2RegClass,
    4898             :   &ARM::DQuad_with_ssub_4RegClass,
    4899             :   &ARM::DQuad_with_ssub_6RegClass,
    4900             :   &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
    4901             :   &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
    4902             :   nullptr
    4903             : };
    4904             : 
    4905             : static const TargetRegisterClass *const DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
    4906             :   &ARM::DQuadRegClass,
    4907             :   &ARM::DQuad_with_ssub_0RegClass,
    4908             :   &ARM::DQuad_with_ssub_2RegClass,
    4909             :   &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    4910             :   &ARM::DQuad_with_ssub_4RegClass,
    4911             :   &ARM::DQuad_with_ssub_6RegClass,
    4912             :   &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    4913             :   &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
    4914             :   nullptr
    4915             : };
    4916             : 
    4917             : static const TargetRegisterClass *const DQuad_with_dsub_3_in_DPR_8Superclasses[] = {
    4918             :   &ARM::DQuadRegClass,
    4919             :   &ARM::DQuad_with_ssub_0RegClass,
    4920             :   &ARM::DQuad_with_ssub_2RegClass,
    4921             :   &ARM::DQuad_with_ssub_4RegClass,
    4922             :   &ARM::DQuad_with_ssub_6RegClass,
    4923             :   &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
    4924             :   &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
    4925             :   &ARM::DQuad_with_dsub_2_in_DPR_8RegClass,
    4926             :   nullptr
    4927             : };
    4928             : 
    4929             : static const TargetRegisterClass *const DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
    4930             :   &ARM::DQuadRegClass,
    4931             :   &ARM::DQuad_with_ssub_0RegClass,
    4932             :   &ARM::DQuad_with_ssub_2RegClass,
    4933             :   &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    4934             :   &ARM::DQuad_with_ssub_4RegClass,
    4935             :   &ARM::DQuad_with_ssub_6RegClass,
    4936             :   &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
    4937             :   &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    4938             :   &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
    4939             :   &ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    4940             :   nullptr
    4941             : };
    4942             : 
    4943             : static const TargetRegisterClass *const DQuad_with_qsub_0_in_QPR_8Superclasses[] = {
    4944             :   &ARM::DQuadRegClass,
    4945             :   &ARM::DQuad_with_ssub_0RegClass,
    4946             :   &ARM::DQuad_with_ssub_2RegClass,
    4947             :   &ARM::QQPRRegClass,
    4948             :   &ARM::DQuad_with_ssub_4RegClass,
    4949             :   &ARM::DQuad_with_ssub_6RegClass,
    4950             :   &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
    4951             :   &ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClass,
    4952             :   &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
    4953             :   &ARM::DQuad_with_qsub_1_in_QPR_VFP2RegClass,
    4954             :   nullptr
    4955             : };
    4956             : 
    4957             : static const TargetRegisterClass *const DQuad_with_qsub_1_in_QPR_8Superclasses[] = {
    4958             :   &ARM::DQuadRegClass,
    4959             :   &ARM::DQuad_with_ssub_0RegClass,
    4960             :   &ARM::DQuad_with_ssub_2RegClass,
    4961             :   &ARM::QQPRRegClass,
    4962             :   &ARM::DQuad_with_ssub_4RegClass,
    4963             :   &ARM::DQuad_with_ssub_6RegClass,
    4964             :   &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
    4965             :   &ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClass,
    4966             :   &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
    4967             :   &ARM::DQuad_with_qsub_1_in_QPR_VFP2RegClass,
    4968             :   &ARM::DQuad_with_dsub_2_in_DPR_8RegClass,
    4969             :   &ARM::DQuad_with_dsub_3_in_DPR_8RegClass,
    4970             :   &ARM::DQuad_with_qsub_0_in_QPR_8RegClass,
    4971             :   nullptr
    4972             : };
    4973             : 
    4974             : static const TargetRegisterClass *const DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Superclasses[] = {
    4975             :   &ARM::DQuadRegClass,
    4976             :   &ARM::DQuad_with_ssub_0RegClass,
    4977             :   &ARM::DQuad_with_ssub_2RegClass,
    4978             :   &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    4979             :   &ARM::DQuad_with_ssub_4RegClass,
    4980             :   &ARM::DQuad_with_ssub_6RegClass,
    4981             :   &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
    4982             :   &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    4983             :   &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
    4984             :   &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
    4985             :   &ARM::DQuad_with_dsub_2_in_DPR_8RegClass,
    4986             :   &ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    4987             :   &ARM::DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    4988             :   nullptr
    4989             : };
    4990             : 
    4991             : static const TargetRegisterClass *const DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
    4992             :   &ARM::DQuadRegClass,
    4993             :   &ARM::DQuad_with_ssub_0RegClass,
    4994             :   &ARM::DQuad_with_ssub_2RegClass,
    4995             :   &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    4996             :   &ARM::DQuad_with_ssub_4RegClass,
    4997             :   &ARM::DQuad_with_ssub_6RegClass,
    4998             :   &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
    4999             :   &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    5000             :   &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
    5001             :   &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
    5002             :   &ARM::DQuad_with_dsub_2_in_DPR_8RegClass,
    5003             :   &ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    5004             :   &ARM::DQuad_with_dsub_3_in_DPR_8RegClass,
    5005             :   &ARM::DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    5006             :   &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass,
    5007             :   nullptr
    5008             : };
    5009             : 
    5010             : static const TargetRegisterClass *const QQQQPR_with_ssub_0Superclasses[] = {
    5011             :   &ARM::QQQQPRRegClass,
    5012             :   nullptr
    5013             : };
    5014             : 
    5015             : static const TargetRegisterClass *const QQQQPR_with_ssub_4Superclasses[] = {
    5016             :   &ARM::QQQQPRRegClass,
    5017             :   &ARM::QQQQPR_with_ssub_0RegClass,
    5018             :   nullptr
    5019             : };
    5020             : 
    5021             : static const TargetRegisterClass *const QQQQPR_with_ssub_8Superclasses[] = {
    5022             :   &ARM::QQQQPRRegClass,
    5023             :   &ARM::QQQQPR_with_ssub_0RegClass,
    5024             :   &ARM::QQQQPR_with_ssub_4RegClass,
    5025             :   nullptr
    5026             : };
    5027             : 
    5028             : static const TargetRegisterClass *const QQQQPR_with_ssub_12Superclasses[] = {
    5029             :   &ARM::QQQQPRRegClass,
    5030             :   &ARM::QQQQPR_with_ssub_0RegClass,
    5031             :   &ARM::QQQQPR_with_ssub_4RegClass,
    5032             :   &ARM::QQQQPR_with_ssub_8RegClass,
    5033             :   nullptr
    5034             : };
    5035             : 
    5036             : static const TargetRegisterClass *const QQQQPR_with_dsub_0_in_DPR_8Superclasses[] = {
    5037             :   &ARM::QQQQPRRegClass,
    5038             :   &ARM::QQQQPR_with_ssub_0RegClass,
    5039             :   &ARM::QQQQPR_with_ssub_4RegClass,
    5040             :   &ARM::QQQQPR_with_ssub_8RegClass,
    5041             :   &ARM::QQQQPR_with_ssub_12RegClass,
    5042             :   nullptr
    5043             : };
    5044             : 
    5045             : static const TargetRegisterClass *const QQQQPR_with_dsub_2_in_DPR_8Superclasses[] = {
    5046             :   &ARM::QQQQPRRegClass,
    5047             :   &ARM::QQQQPR_with_ssub_0RegClass,
    5048             :   &ARM::QQQQPR_with_ssub_4RegClass,
    5049             :   &ARM::QQQQPR_with_ssub_8RegClass,
    5050             :   &ARM::QQQQPR_with_ssub_12RegClass,
    5051             :   &ARM::QQQQPR_with_dsub_0_in_DPR_8RegClass,
    5052             :   nullptr
    5053             : };
    5054             : 
    5055             : static const TargetRegisterClass *const QQQQPR_with_dsub_4_in_DPR_8Superclasses[] = {
    5056             :   &ARM::QQQQPRRegClass,
    5057             :   &ARM::QQQQPR_with_ssub_0RegClass,
    5058             :   &ARM::QQQQPR_with_ssub_4RegClass,
    5059             :   &ARM::QQQQPR_with_ssub_8RegClass,
    5060             :   &ARM::QQQQPR_with_ssub_12RegClass,
    5061             :   &ARM::QQQQPR_with_dsub_0_in_DPR_8RegClass,
    5062             :   &ARM::QQQQPR_with_dsub_2_in_DPR_8RegClass,
    5063             :   nullptr
    5064             : };
    5065             : 
    5066             : static const TargetRegisterClass *const QQQQPR_with_dsub_6_in_DPR_8Superclasses[] = {
    5067             :   &ARM::QQQQPRRegClass,
    5068             :   &ARM::QQQQPR_with_ssub_0RegClass,
    5069             :   &ARM::QQQQPR_with_ssub_4RegClass,
    5070             :   &ARM::QQQQPR_with_ssub_8RegClass,
    5071             :   &ARM::QQQQPR_with_ssub_12RegClass,
    5072             :   &ARM::QQQQPR_with_dsub_0_in_DPR_8RegClass,
    5073             :   &ARM::QQQQPR_with_dsub_2_in_DPR_8RegClass,
    5074             :   &ARM::QQQQPR_with_dsub_4_in_DPR_8RegClass,
    5075             :   nullptr
    5076             : };
    5077             : 
    5078             : 
    5079             : static inline unsigned SPRAltOrderSelect(const MachineFunction &MF) {
    5080         369 :     return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs(MF);
    5081             :   }
    5082             : 
    5083         369 : static ArrayRef<MCPhysReg> SPRGetRawAllocationOrder(const MachineFunction &MF) {
    5084             :   static const MCPhysReg AltOrder1[] = { ARM::S0, ARM::S2, ARM::S4, ARM::S6, ARM::S8, ARM::S10, ARM::S12, ARM::S14, ARM::S16, ARM::S18, ARM::S20, ARM::S22, ARM::S24, ARM::S26, ARM::S28, ARM::S30, ARM::S1, ARM::S3, ARM::S5, ARM::S7, ARM::S9, ARM::S11, ARM::S13, ARM::S15, ARM::S17, ARM::S19, ARM::S21, ARM::S23, ARM::S25, ARM::S27, ARM::S29, ARM::S31 };
    5085             :   static const MCPhysReg AltOrder2[] = { ARM::S0, ARM::S4, ARM::S8, ARM::S12, ARM::S16, ARM::S20, ARM::S24, ARM::S28, ARM::S2, ARM::S6, ARM::S10, ARM::S14, ARM::S18, ARM::S22, ARM::S26, ARM::S30, ARM::S1, ARM::S5, ARM::S9, ARM::S13, ARM::S17, ARM::S21, ARM::S25, ARM::S29, ARM::S3, ARM::S7, ARM::S11, ARM::S15, ARM::S19, ARM::S23, ARM::S27, ARM::S31 };
    5086         369 :   const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::SPRRegClassID];
    5087             :   const ArrayRef<MCPhysReg> Order[] = {
    5088         369 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    5089             :     makeArrayRef(AltOrder1),
    5090             :     makeArrayRef(AltOrder2)
    5091        1107 :   };
    5092         369 :   const unsigned Select = SPRAltOrderSelect(MF);
    5093             :   assert(Select < 3);
    5094         369 :   return Order[Select];
    5095             : }
    5096             : 
    5097             : static inline unsigned GPRAltOrderSelect(const MachineFunction &MF) {
    5098        8424 :       return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
    5099             :   }
    5100             : 
    5101        4212 : static ArrayRef<MCPhysReg> GPRGetRawAllocationOrder(const MachineFunction &MF) {
    5102             :   static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::PC };
    5103             :   static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
    5104        4212 :   const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRRegClassID];
    5105             :   const ArrayRef<MCPhysReg> Order[] = {
    5106        4212 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    5107             :     makeArrayRef(AltOrder1),
    5108             :     makeArrayRef(AltOrder2)
    5109       12636 :   };
    5110        4212 :   const unsigned Select = GPRAltOrderSelect(MF);
    5111             :   assert(Select < 3);
    5112        4212 :   return Order[Select];
    5113             : }
    5114             : 
    5115             : static inline unsigned GPRwithAPSRAltOrderSelect(const MachineFunction &MF) {
    5116           0 :       return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
    5117             :   }
    5118             : 
    5119           0 : static ArrayRef<MCPhysReg> GPRwithAPSRGetRawAllocationOrder(const MachineFunction &MF) {
    5120             :   static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP };
    5121             :   static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
    5122           0 :   const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRwithAPSRRegClassID];
    5123             :   const ArrayRef<MCPhysReg> Order[] = {
    5124           0 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    5125             :     makeArrayRef(AltOrder1),
    5126             :     makeArrayRef(AltOrder2)
    5127           0 :   };
    5128           0 :   const unsigned Select = GPRwithAPSRAltOrderSelect(MF);
    5129             :   assert(Select < 3);
    5130           0 :   return Order[Select];
    5131             : }
    5132             : 
    5133             : static inline unsigned GPRnopcAltOrderSelect(const MachineFunction &MF) {
    5134        1642 :       return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
    5135             :   }
    5136             : 
    5137         821 : static ArrayRef<MCPhysReg> GPRnopcGetRawAllocationOrder(const MachineFunction &MF) {
    5138             :   static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP };
    5139             :   static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
    5140         821 :   const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRnopcRegClassID];
    5141             :   const ArrayRef<MCPhysReg> Order[] = {
    5142         821 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    5143             :     makeArrayRef(AltOrder1),
    5144             :     makeArrayRef(AltOrder2)
    5145        2463 :   };
    5146         821 :   const unsigned Select = GPRnopcAltOrderSelect(MF);
    5147             :   assert(Select < 3);
    5148         821 :   return Order[Select];
    5149             : }
    5150             : 
    5151             : static inline unsigned rGPRAltOrderSelect(const MachineFunction &MF) {
    5152        1742 :       return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
    5153             :   }
    5154             : 
    5155         871 : static ArrayRef<MCPhysReg> rGPRGetRawAllocationOrder(const MachineFunction &MF) {
    5156             :   static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12 };
    5157             :   static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
    5158         871 :   const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::rGPRRegClassID];
    5159             :   const ArrayRef<MCPhysReg> Order[] = {
    5160         871 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    5161             :     makeArrayRef(AltOrder1),
    5162             :     makeArrayRef(AltOrder2)
    5163        2613 :   };
    5164         871 :   const unsigned Select = rGPRAltOrderSelect(MF);
    5165             :   assert(Select < 3);
    5166         871 :   return Order[Select];
    5167             : }
    5168             : 
    5169             : static inline unsigned tcGPRAltOrderSelect(const MachineFunction &MF) {
    5170          34 :       return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
    5171             :   }
    5172             : 
    5173          17 : static ArrayRef<MCPhysReg> tcGPRGetRawAllocationOrder(const MachineFunction &MF) {
    5174             :   static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
    5175          17 :   const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tcGPRRegClassID];
    5176             :   const ArrayRef<MCPhysReg> Order[] = {
    5177          17 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    5178             :     makeArrayRef(AltOrder1)
    5179          34 :   };
    5180          17 :   const unsigned Select = tcGPRAltOrderSelect(MF);
    5181             :   assert(Select < 2);
    5182          17 :   return Order[Select];
    5183             : }
    5184             : 
    5185             : static inline unsigned tGPR_and_tcGPRAltOrderSelect(const MachineFunction &MF) {
    5186           0 :       return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
    5187             :   }
    5188             : 
    5189           0 : static ArrayRef<MCPhysReg> tGPR_and_tcGPRGetRawAllocationOrder(const MachineFunction &MF) {
    5190             :   static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
    5191           0 :   const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tGPR_and_tcGPRRegClassID];
    5192             :   const ArrayRef<MCPhysReg> Order[] = {
    5193           0 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    5194             :     makeArrayRef(AltOrder1)
    5195           0 :   };
    5196           0 :   const unsigned Select = tGPR_and_tcGPRAltOrderSelect(MF);
    5197             :   assert(Select < 2);
    5198           0 :   return Order[Select];
    5199             : }
    5200             : 
    5201             : static inline unsigned hGPR_and_tcGPRAltOrderSelect(const MachineFunction &MF) {
    5202           0 :       return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
    5203             :   }
    5204             : 
    5205           0 : static ArrayRef<MCPhysReg> hGPR_and_tcGPRGetRawAllocationOrder(const MachineFunction &MF) {
    5206           0 :   const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::hGPR_and_tcGPRRegClassID];
    5207             :   const ArrayRef<MCPhysReg> Order[] = {
    5208           0 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    5209             :     ArrayRef<MCPhysReg>()
    5210           0 :   };
    5211           0 :   const unsigned Select = hGPR_and_tcGPRAltOrderSelect(MF);
    5212             :   assert(Select < 2);
    5213           0 :   return Order[Select];
    5214             : }
    5215             : 
    5216             : static inline unsigned DPRAltOrderSelect(const MachineFunction &MF) {
    5217         638 :     return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs(MF);
    5218             :   }
    5219             : 
    5220         638 : static ArrayRef<MCPhysReg> DPRGetRawAllocationOrder(const MachineFunction &MF) {
    5221             :   static const MCPhysReg AltOrder1[] = { ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15 };
    5222             :   static const MCPhysReg AltOrder2[] = { ARM::D16, ARM::D18, ARM::D20, ARM::D22, ARM::D24, ARM::D26, ARM::D28, ARM::D30, ARM::D0, ARM::D2, ARM::D4, ARM::D6, ARM::D8, ARM::D10, ARM::D12, ARM::D14, ARM::D17, ARM::D19, ARM::D21, ARM::D23, ARM::D25, ARM::D27, ARM::D29, ARM::D31, ARM::D1, ARM::D3, ARM::D5, ARM::D7, ARM::D9, ARM::D11, ARM::D13, ARM::D15 };
    5223         638 :   const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPRRegClassID];
    5224             :   const ArrayRef<MCPhysReg> Order[] = {
    5225         638 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    5226             :     makeArrayRef(AltOrder1),
    5227             :     makeArrayRef(AltOrder2)
    5228        1914 :   };
    5229         638 :   const unsigned Select = DPRAltOrderSelect(MF);
    5230             :   assert(Select < 3);
    5231         638 :   return Order[Select];
    5232             : }
    5233             : 
    5234             : static inline unsigned DPairAltOrderSelect(const MachineFunction &MF) { return 1; }
    5235             : 
    5236         169 : static ArrayRef<MCPhysReg> DPairGetRawAllocationOrder(const MachineFunction &MF) {
    5237             :   static const MCPhysReg AltOrder1[] = { ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::D17_D18, ARM::D19_D20, ARM::D21_D22, ARM::D23_D24, ARM::D25_D26, ARM::D27_D28, ARM::D29_D30, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8, ARM::D9_D10, ARM::D11_D12, ARM::D13_D14, ARM::D15_D16 };
    5238         169 :   const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPairRegClassID];
    5239             :   const ArrayRef<MCPhysReg> Order[] = {
    5240         169 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    5241             :     makeArrayRef(AltOrder1)
    5242         338 :   };
    5243         169 :   const unsigned Select = DPairAltOrderSelect(MF);
    5244             :   assert(Select < 2);
    5245         169 :   return Order[Select];
    5246             : }
    5247             : 
    5248             : static inline unsigned DPair_with_ssub_0AltOrderSelect(const MachineFunction &MF) { return 1; }
    5249             : 
    5250          34 : static ArrayRef<MCPhysReg> DPair_with_ssub_0GetRawAllocationOrder(const MachineFunction &MF) {
    5251             :   static const MCPhysReg AltOrder1[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8, ARM::D9_D10, ARM::D11_D12, ARM::D13_D14, ARM::D15_D16 };
    5252          34 :   const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPair_with_ssub_0RegClassID];
    5253             :   const ArrayRef<MCPhysReg> Order[] = {
    5254          34 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    5255             :     makeArrayRef(AltOrder1)
    5256          68 :   };
    5257          34 :   const unsigned Select = DPair_with_ssub_0AltOrderSelect(MF);
    5258             :   assert(Select < 2);
    5259          34 :   return Order[Select];
    5260             : }
    5261             : 
    5262             : static inline unsigned QPRAltOrderSelect(const MachineFunction &MF) { return 1; }
    5263             : 
    5264         359 : static ArrayRef<MCPhysReg> QPRGetRawAllocationOrder(const MachineFunction &MF) {
    5265             :   static const MCPhysReg AltOrder1[] = { ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7 };
    5266         359 :   const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QPRRegClassID];
    5267             :   const ArrayRef<MCPhysReg> Order[] = {
    5268         359 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    5269             :     makeArrayRef(AltOrder1)
    5270         718 :   };
    5271         359 :   const unsigned Select = QPRAltOrderSelect(MF);
    5272             :   assert(Select < 2);
    5273         359 :   return Order[Select];
    5274             : }
    5275             : 
    5276             : static inline unsigned DPair_with_ssub_2AltOrderSelect(const MachineFunction &MF) { return 1; }
    5277             : 
    5278           0 : static ArrayRef<MCPhysReg> DPair_with_ssub_2GetRawAllocationOrder(const MachineFunction &MF) {
    5279             :   static const MCPhysReg AltOrder1[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8, ARM::D9_D10, ARM::D11_D12, ARM::D13_D14 };
    5280           0 :   const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPair_with_ssub_2RegClassID];
    5281             :   const ArrayRef<MCPhysReg> Order[] = {
    5282           0 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    5283             :     makeArrayRef(AltOrder1)
    5284           0 :   };
    5285           0 :   const unsigned Select = DPair_with_ssub_2AltOrderSelect(MF);
    5286             :   assert(Select < 2);
    5287           0 :   return Order[Select];
    5288             : }
    5289             : 
    5290             : static inline unsigned DPair_with_dsub_0_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }
    5291             : 
    5292           6 : static ArrayRef<MCPhysReg> DPair_with_dsub_0_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) {
    5293             :   static const MCPhysReg AltOrder1[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8 };
    5294           6 :   const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPair_with_dsub_0_in_DPR_8RegClassID];
    5295             :   const ArrayRef<MCPhysReg> Order[] = {
    5296           6 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    5297             :     makeArrayRef(AltOrder1)
    5298          12 :   };
    5299           6 :   const unsigned Select = DPair_with_dsub_0_in_DPR_8AltOrderSelect(MF);
    5300             :   assert(Select < 2);
    5301           6 :   return Order[Select];
    5302             : }
    5303             : 
    5304             : static inline unsigned DPair_with_dsub_1_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }
    5305             : 
    5306           0 : static ArrayRef<MCPhysReg> DPair_with_dsub_1_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) {
    5307             :   static const MCPhysReg AltOrder1[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6 };
    5308           0 :   const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPair_with_dsub_1_in_DPR_8RegClassID];
    5309             :   const ArrayRef<MCPhysReg> Order[] = {
    5310           0 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    5311             :     makeArrayRef(AltOrder1)
    5312           0 :   };
    5313           0 :   const unsigned Select = DPair_with_dsub_1_in_DPR_8AltOrderSelect(MF);
    5314             :   assert(Select < 2);
    5315           0 :   return Order[Select];
    5316             : }
    5317             : 
    5318             : static inline unsigned QQPRAltOrderSelect(const MachineFunction &MF) { return 1; }
    5319             : 
    5320          38 : static ArrayRef<MCPhysReg> QQPRGetRawAllocationOrder(const MachineFunction &MF) {
    5321             :   static const MCPhysReg AltOrder1[] = { ARM::Q8_Q9, ARM::Q9_Q10, ARM::Q10_Q11, ARM::Q11_Q12, ARM::Q12_Q13, ARM::Q13_Q14, ARM::Q14_Q15, ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8 };
    5322          38 :   const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQPRRegClassID];
    5323             :   const ArrayRef<MCPhysReg> Order[] = {
    5324          38 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    5325             :     makeArrayRef(AltOrder1)
    5326          76 :   };
    5327          38 :   const unsigned Select = QQPRAltOrderSelect(MF);
    5328             :   assert(Select < 2);
    5329          38 :   return Order[Select];
    5330             : }
    5331             : 
    5332             : static inline unsigned DQuad_with_qsub_0_in_QPR_VFP2AltOrderSelect(const MachineFunction &MF) { return 1; }
    5333             : 
    5334           0 : static ArrayRef<MCPhysReg> DQuad_with_qsub_0_in_QPR_VFP2GetRawAllocationOrder(const MachineFunction &MF) {
    5335             :   static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8 };
    5336           0 :   const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClassID];
    5337             :   const ArrayRef<MCPhysReg> Order[] = {
    5338           0 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    5339             :     makeArrayRef(AltOrder1)
    5340           0 :   };
    5341           0 :   const unsigned Select = DQuad_with_qsub_0_in_QPR_VFP2AltOrderSelect(MF);
    5342             :   assert(Select < 2);
    5343           0 :   return Order[Select];
    5344             : }
    5345             : 
    5346             : static inline unsigned DQuad_with_qsub_1_in_QPR_VFP2AltOrderSelect(const MachineFunction &MF) { return 1; }
    5347             : 
    5348           0 : static ArrayRef<MCPhysReg> DQuad_with_qsub_1_in_QPR_VFP2GetRawAllocationOrder(const MachineFunction &MF) {
    5349             :   static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 };
    5350           0 :   const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DQuad_with_qsub_1_in_QPR_VFP2RegClassID];
    5351             :   const ArrayRef<MCPhysReg> Order[] = {
    5352           0 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    5353             :     makeArrayRef(AltOrder1)
    5354           0 :   };
    5355           0 :   const unsigned Select = DQuad_with_qsub_1_in_QPR_VFP2AltOrderSelect(MF);
    5356             :   assert(Select < 2);
    5357           0 :   return Order[Select];
    5358             : }
    5359             : 
    5360             : static inline unsigned DQuad_with_qsub_0_in_QPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }
    5361             : 
    5362           0 : static ArrayRef<MCPhysReg> DQuad_with_qsub_0_in_QPR_8GetRawAllocationOrder(const MachineFunction &MF) {
    5363             :   static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4 };
    5364           0 :   const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DQuad_with_qsub_0_in_QPR_8RegClassID];
    5365             :   const ArrayRef<MCPhysReg> Order[] = {
    5366           0 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    5367             :     makeArrayRef(AltOrder1)
    5368           0 :   };
    5369           0 :   const unsigned Select = DQuad_with_qsub_0_in_QPR_8AltOrderSelect(MF);
    5370             :   assert(Select < 2);
    5371           0 :   return Order[Select];
    5372             : }
    5373             : 
    5374             : static inline unsigned DQuad_with_qsub_1_in_QPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }
    5375             : 
    5376           0 : static ArrayRef<MCPhysReg> DQuad_with_qsub_1_in_QPR_8GetRawAllocationOrder(const MachineFunction &MF) {
    5377             :   static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3 };
    5378           0 :   const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DQuad_with_qsub_1_in_QPR_8RegClassID];
    5379             :   const ArrayRef<MCPhysReg> Order[] = {
    5380           0 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    5381             :     makeArrayRef(AltOrder1)
    5382           0 :   };
    5383           0 :   const unsigned Select = DQuad_with_qsub_1_in_QPR_8AltOrderSelect(MF);
    5384             :   assert(Select < 2);
    5385           0 :   return Order[Select];
    5386             : }
    5387             : 
    5388             : static inline unsigned QQQQPRAltOrderSelect(const MachineFunction &MF) { return 1; }
    5389             : 
    5390          56 : static ArrayRef<MCPhysReg> QQQQPRGetRawAllocationOrder(const MachineFunction &MF) {
    5391             :   static const MCPhysReg AltOrder1[] = { ARM::Q8_Q9_Q10_Q11, ARM::Q9_Q10_Q11_Q12, ARM::Q10_Q11_Q12_Q13, ARM::Q11_Q12_Q13_Q14, ARM::Q12_Q13_Q14_Q15, ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10 };
    5392          56 :   const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPRRegClassID];
    5393             :   const ArrayRef<MCPhysReg> Order[] = {
    5394          56 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    5395             :     makeArrayRef(AltOrder1)
    5396         112 :   };
    5397          56 :   const unsigned Select = QQQQPRAltOrderSelect(MF);
    5398             :   assert(Select < 2);
    5399          56 :   return Order[Select];
    5400             : }
    5401             : 
    5402             : static inline unsigned QQQQPR_with_ssub_0AltOrderSelect(const MachineFunction &MF) { return 1; }
    5403             : 
    5404          25 : static ArrayRef<MCPhysReg> QQQQPR_with_ssub_0GetRawAllocationOrder(const MachineFunction &MF) {
    5405             :   static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10 };
    5406          25 :   const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_ssub_0RegClassID];
    5407             :   const ArrayRef<MCPhysReg> Order[] = {
    5408          25 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    5409             :     makeArrayRef(AltOrder1)
    5410          50 :   };
    5411          25 :   const unsigned Select = QQQQPR_with_ssub_0AltOrderSelect(MF);
    5412             :   assert(Select < 2);
    5413          25 :   return Order[Select];
    5414             : }
    5415             : 
    5416             : static inline unsigned QQQQPR_with_ssub_4AltOrderSelect(const MachineFunction &MF) { return 1; }
    5417             : 
    5418           0 : static ArrayRef<MCPhysReg> QQQQPR_with_ssub_4GetRawAllocationOrder(const MachineFunction &MF) {
    5419             :   static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9 };
    5420           0 :   const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_ssub_4RegClassID];
    5421             :   const ArrayRef<MCPhysReg> Order[] = {
    5422           0 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    5423             :     makeArrayRef(AltOrder1)
    5424           0 :   };
    5425           0 :   const unsigned Select = QQQQPR_with_ssub_4AltOrderSelect(MF);
    5426             :   assert(Select < 2);
    5427           0 :   return Order[Select];
    5428             : }
    5429             : 
    5430             : static inline unsigned QQQQPR_with_ssub_8AltOrderSelect(const MachineFunction &MF) { return 1; }
    5431             : 
    5432           0 : static ArrayRef<MCPhysReg> QQQQPR_with_ssub_8GetRawAllocationOrder(const MachineFunction &MF) {
    5433             :   static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8 };
    5434           0 :   const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_ssub_8RegClassID];
    5435             :   const ArrayRef<MCPhysReg> Order[] = {
    5436           0 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    5437             :     makeArrayRef(AltOrder1)
    5438           0 :   };
    5439           0 :   const unsigned Select = QQQQPR_with_ssub_8AltOrderSelect(MF);
    5440             :   assert(Select < 2);
    5441           0 :   return Order[Select];
    5442             : }
    5443             : 
    5444             : static inline unsigned QQQQPR_with_ssub_12AltOrderSelect(const MachineFunction &MF) { return 1; }
    5445             : 
    5446           3 : static ArrayRef<MCPhysReg> QQQQPR_with_ssub_12GetRawAllocationOrder(const MachineFunction &MF) {
    5447             :   static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 };
    5448           3 :   const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_ssub_12RegClassID];
    5449             :   const ArrayRef<MCPhysReg> Order[] = {
    5450           3 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    5451             :     makeArrayRef(AltOrder1)
    5452           6 :   };
    5453           3 :   const unsigned Select = QQQQPR_with_ssub_12AltOrderSelect(MF);
    5454             :   assert(Select < 2);
    5455           3 :   return Order[Select];
    5456             : }
    5457             : 
    5458             : static inline unsigned QQQQPR_with_dsub_0_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }
    5459             : 
    5460           0 : static ArrayRef<MCPhysReg> QQQQPR_with_dsub_0_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) {
    5461             :   static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6 };
    5462           0 :   const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_dsub_0_in_DPR_8RegClassID];
    5463             :   const ArrayRef<MCPhysReg> Order[] = {
    5464           0 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    5465             :     makeArrayRef(AltOrder1)
    5466           0 :   };
    5467           0 :   const unsigned Select = QQQQPR_with_dsub_0_in_DPR_8AltOrderSelect(MF);
    5468             :   assert(Select < 2);
    5469           0 :   return Order[Select];
    5470             : }
    5471             : 
    5472             : static inline unsigned QQQQPR_with_dsub_2_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }
    5473             : 
    5474           0 : static ArrayRef<MCPhysReg> QQQQPR_with_dsub_2_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) {
    5475             :   static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5 };
    5476           0 :   const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_dsub_2_in_DPR_8RegClassID];
    5477             :   const ArrayRef<MCPhysReg> Order[] = {
    5478           0 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    5479             :     makeArrayRef(AltOrder1)
    5480           0 :   };
    5481           0 :   const unsigned Select = QQQQPR_with_dsub_2_in_DPR_8AltOrderSelect(MF);
    5482             :   assert(Select < 2);
    5483           0 :   return Order[Select];
    5484             : }
    5485             : 
    5486             : static inline unsigned QQQQPR_with_dsub_4_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }
    5487             : 
    5488           0 : static ArrayRef<MCPhysReg> QQQQPR_with_dsub_4_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) {
    5489             :   static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4 };
    5490           0 :   const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_dsub_4_in_DPR_8RegClassID];
    5491             :   const ArrayRef<MCPhysReg> Order[] = {
    5492           0 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    5493             :     makeArrayRef(AltOrder1)
    5494           0 :   };
    5495           0 :   const unsigned Select = QQQQPR_with_dsub_4_in_DPR_8AltOrderSelect(MF);
    5496             :   assert(Select < 2);
    5497           0 :   return Order[Select];
    5498             : }
    5499             : 
    5500             : static inline unsigned QQQQPR_with_dsub_6_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }
    5501             : 
    5502           0 : static ArrayRef<MCPhysReg> QQQQPR_with_dsub_6_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) {
    5503             :   static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3 };
    5504           0 :   const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_dsub_6_in_DPR_8RegClassID];
    5505             :   const ArrayRef<MCPhysReg> Order[] = {
    5506           0 :     makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    5507             :     makeArrayRef(AltOrder1)
    5508           0 :   };
    5509           0 :   const unsigned Select = QQQQPR_with_dsub_6_in_DPR_8AltOrderSelect(MF);
    5510             :   assert(Select < 2);
    5511           0 :   return Order[Select];
    5512             : }
    5513             : 
    5514             : namespace ARM {   // Register class instances
    5515             :   extern const TargetRegisterClass SPRRegClass = {
    5516             :     &ARMMCRegisterClasses[SPRRegClassID],
    5517             :     4, /* SpillSize */
    5518             :     4, /* SpillAlignment */
    5519             :     VTLists + 2,
    5520             :     SPRSubClassMask,
    5521             :     SuperRegIdxSeqs + 14,
    5522             :     LaneBitmask(0x00000001),
    5523             :     0,
    5524             :     false, /* HasDisjunctSubRegs */
    5525             :     false, /* CoveredBySubRegs */
    5526             :     NullRegClasses,
    5527             :     SPRGetRawAllocationOrder
    5528             :   };
    5529             : 
    5530             :   extern const TargetRegisterClass GPRRegClass = {
    5531             :     &ARMMCRegisterClasses[GPRRegClassID],
    5532             :     4, /* SpillSize */
    5533             :     4, /* SpillAlignment */
    5534             :     VTLists + 0,
    5535             :     GPRSubClassMask,
    5536             :     SuperRegIdxSeqs + 11,
    5537             :     LaneBitmask(0x00000001),
    5538             :     0,
    5539             :     false, /* HasDisjunctSubRegs */
    5540             :     true, /* CoveredBySubRegs */
    5541             :     NullRegClasses,
    5542             :     GPRGetRawAllocationOrder
    5543             :   };
    5544             : 
    5545             :   extern const TargetRegisterClass GPRwithAPSRRegClass = {
    5546             :     &ARMMCRegisterClasses[GPRwithAPSRRegClassID],
    5547             :     4, /* SpillSize */
    5548             :     4, /* SpillAlignment */
    5549             :     VTLists + 0,
    5550             :     GPRwithAPSRSubClassMask,
    5551             :     SuperRegIdxSeqs + 11,
    5552             :     LaneBitmask(0x00000001),
    5553             :     0,
    5554             :     false, /* HasDisjunctSubRegs */
    5555             :     true, /* CoveredBySubRegs */
    5556             :     NullRegClasses,
    5557             :     GPRwithAPSRGetRawAllocationOrder
    5558             :   };
    5559             : 
    5560             :   extern const TargetRegisterClass SPR_8RegClass = {
    5561             :     &ARMMCRegisterClasses[SPR_8RegClassID],
    5562             :     4, /* SpillSize */
    5563             :     4, /* SpillAlignment */
    5564             :     VTLists + 2,
    5565             :     SPR_8SubClassMask,
    5566             :     SuperRegIdxSeqs + 14,
    5567             :     LaneBitmask(0x00000001),
    5568             :     0,
    5569             :     false, /* HasDisjunctSubRegs */
    5570             :     false, /* CoveredBySubRegs */
    5571             :     SPR_8Superclasses,
    5572             :     nullptr
    5573             :   };
    5574             : 
    5575             :   extern const TargetRegisterClass GPRnopcRegClass = {
    5576             :     &ARMMCRegisterClasses[GPRnopcRegClassID],
    5577             :     4, /* SpillSize */
    5578             :     4, /* SpillAlignment */
    5579             :     VTLists + 0,
    5580             :     GPRnopcSubClassMask,
    5581             :     SuperRegIdxSeqs + 11,
    5582             :     LaneBitmask(0x00000001),
    5583             :     0,
    5584             :     false, /* HasDisjunctSubRegs */
    5585             :     true, /* CoveredBySubRegs */
    5586             :     GPRnopcSuperclasses,
    5587             :     GPRnopcGetRawAllocationOrder
    5588             :   };
    5589             : 
    5590             :   extern const TargetRegisterClass rGPRRegClass = {
    5591             :     &ARMMCRegisterClasses[rGPRRegClassID],
    5592             :     4, /* SpillSize */
    5593             :     4, /* SpillAlignment */
    5594             :     VTLists + 0,
    5595             :     rGPRSubClassMask,
    5596             :     SuperRegIdxSeqs + 11,
    5597             :     LaneBitmask(0x00000001),
    5598             :     0,
    5599             :     false, /* HasDisjunctSubRegs */
    5600             :     true, /* CoveredBySubRegs */
    5601             :     rGPRSuperclasses,
    5602             :     rGPRGetRawAllocationOrder
    5603             :   };
    5604             : 
    5605             :   extern const TargetRegisterClass tGPRwithpcRegClass = {
    5606             :     &ARMMCRegisterClasses[tGPRwithpcRegClassID],
    5607             :     4, /* SpillSize */
    5608             :     4, /* SpillAlignment */
    5609             :     VTLists + 0,
    5610             :     tGPRwithpcSubClassMask,
    5611             :     SuperRegIdxSeqs + 11,
    5612             :     LaneBitmask(0x00000001),
    5613             :     0,
    5614             :     false, /* HasDisjunctSubRegs */
    5615             :     true, /* CoveredBySubRegs */
    5616             :     tGPRwithpcSuperclasses,
    5617             :     nullptr
    5618             :   };
    5619             : 
    5620             :   extern const TargetRegisterClass hGPRRegClass = {
    5621             :     &ARMMCRegisterClasses[hGPRRegClassID],
    5622             :     4, /* SpillSize */
    5623             :     4, /* SpillAlignment */
    5624             :     VTLists + 0,
    5625             :     hGPRSubClassMask,
    5626             :     SuperRegIdxSeqs + 11,
    5627             :     LaneBitmask(0x00000001),
    5628             :     0,
    5629             :     false, /* HasDisjunctSubRegs */
    5630             :     true, /* CoveredBySubRegs */
    5631             :     hGPRSuperclasses,
    5632             :     nullptr
    5633             :   };
    5634             : 
    5635             :   extern const TargetRegisterClass tGPRRegClass = {
    5636             :     &ARMMCRegisterClasses[tGPRRegClassID],
    5637             :     4, /* SpillSize */
    5638             :     4, /* SpillAlignment */
    5639             :     VTLists + 0,
    5640             :     tGPRSubClassMask,
    5641             :     SuperRegIdxSeqs + 11,
    5642             :     LaneBitmask(0x00000001),
    5643             :     0,
    5644             :     false, /* HasDisjunctSubRegs */
    5645             :     true, /* CoveredBySubRegs */
    5646             :     tGPRSuperclasses,
    5647             :     nullptr
    5648             :   };
    5649             : 
    5650             :   extern const TargetRegisterClass GPRnopc_and_hGPRRegClass = {
    5651             :     &ARMMCRegisterClasses[GPRnopc_and_hGPRRegClassID],
    5652             :     4, /* SpillSize */
    5653             :     4, /* SpillAlignment */
    5654             :     VTLists + 0,
    5655             :     GPRnopc_and_hGPRSubClassMask,
    5656             :     SuperRegIdxSeqs + 11,
    5657             :     LaneBitmask(0x00000001),
    5658             :     0,
    5659             :     false, /* HasDisjunctSubRegs */
    5660             :     true, /* CoveredBySubRegs */
    5661             :     GPRnopc_and_hGPRSuperclasses,
    5662             :     nullptr
    5663             :   };
    5664             : 
    5665             :   extern const TargetRegisterClass hGPR_and_rGPRRegClass = {
    5666             :     &ARMMCRegisterClasses[hGPR_and_rGPRRegClassID],
    5667             :     4, /* SpillSize */
    5668             :     4, /* SpillAlignment */
    5669             :     VTLists + 0,
    5670             :     hGPR_and_rGPRSubClassMask,
    5671             :     SuperRegIdxSeqs + 11,
    5672             :     LaneBitmask(0x00000001),
    5673             :     0,
    5674             :     false, /* HasDisjunctSubRegs */
    5675             :     true, /* CoveredBySubRegs */
    5676             :     hGPR_and_rGPRSuperclasses,
    5677             :     nullptr
    5678             :   };
    5679             : 
    5680             :   extern const TargetRegisterClass tcGPRRegClass = {
    5681             :     &ARMMCRegisterClasses[tcGPRRegClassID],
    5682             :     4, /* SpillSize */
    5683             :     4, /* SpillAlignment */
    5684             :     VTLists + 0,
    5685             :     tcGPRSubClassMask,
    5686             :     SuperRegIdxSeqs + 11,
    5687             :     LaneBitmask(0x00000001),
    5688             :     0,
    5689             :     false, /* HasDisjunctSubRegs */
    5690             :     true, /* CoveredBySubRegs */
    5691             :     tcGPRSuperclasses,
    5692             :     tcGPRGetRawAllocationOrder
    5693             :   };
    5694             : 
    5695             :   extern const TargetRegisterClass tGPR_and_tcGPRRegClass = {
    5696             :     &ARMMCRegisterClasses[tGPR_and_tcGPRRegClassID],
    5697             :     4, /* SpillSize */
    5698             :     4, /* SpillAlignment */
    5699             :     VTLists + 0,
    5700             :     tGPR_and_tcGPRSubClassMask,
    5701             :     SuperRegIdxSeqs + 11,
    5702             :     LaneBitmask(0x00000001),
    5703             :     0,
    5704             :     false, /* HasDisjunctSubRegs */
    5705             :     true, /* CoveredBySubRegs */
    5706             :     tGPR_and_tcGPRSuperclasses,
    5707             :     tGPR_and_tcGPRGetRawAllocationOrder
    5708             :   };
    5709             : 
    5710             :   extern const TargetRegisterClass CCRRegClass = {
    5711             :     &ARMMCRegisterClasses[CCRRegClassID],
    5712             :     4, /* SpillSize */
    5713             :     4, /* SpillAlignment */
    5714             :     VTLists + 0,
    5715             :     CCRSubClassMask,
    5716             :     SuperRegIdxSeqs + 8,
    5717             :     LaneBitmask(0x00000001),
    5718             :     0,
    5719             :     false, /* HasDisjunctSubRegs */
    5720             :     true, /* CoveredBySubRegs */
    5721             :     NullRegClasses,
    5722             :     nullptr
    5723             :   };
    5724             : 
    5725             :   extern const TargetRegisterClass GPRspRegClass = {
    5726             :     &ARMMCRegisterClasses[GPRspRegClassID],
    5727             :     4, /* SpillSize */
    5728             :     4, /* SpillAlignment */
    5729             :     VTLists + 0,
    5730             :     GPRspSubClassMask,
    5731             :     SuperRegIdxSeqs + 12,
    5732             :     LaneBitmask(0x00000001),
    5733             :     0,
    5734             :     false, /* HasDisjunctSubRegs */
    5735             :     true, /* CoveredBySubRegs */
    5736             :     GPRspSuperclasses,
    5737             :     nullptr
    5738             :   };
    5739             : 
    5740             :   extern const TargetRegisterClass hGPR_and_tGPRwithpcRegClass = {
    5741             :     &ARMMCRegisterClasses[hGPR_and_tGPRwithpcRegClassID],
    5742             :     4, /* SpillSize */
    5743             :     4, /* SpillAlignment */
    5744             :     VTLists + 0,
    5745             :     hGPR_and_tGPRwithpcSubClassMask,
    5746             :     SuperRegIdxSeqs + 8,
    5747             :     LaneBitmask(0x00000001),
    5748             :     0,
    5749             :     false, /* HasDisjunctSubRegs */
    5750             :     true, /* CoveredBySubRegs */
    5751             :     hGPR_and_tGPRwithpcSuperclasses,
    5752             :     nullptr
    5753             :   };
    5754             : 
    5755             :   extern const TargetRegisterClass hGPR_and_tcGPRRegClass = {
    5756             :     &ARMMCRegisterClasses[hGPR_and_tcGPRRegClassID],
    5757             :     4, /* SpillSize */
    5758             :     4, /* SpillAlignment */
    5759             :     VTLists + 0,
    5760             :     hGPR_and_tcGPRSubClassMask,
    5761             :     SuperRegIdxSeqs + 9,
    5762             :     LaneBitmask(0x00000001),
    5763             :     0,
    5764             :     false, /* HasDisjunctSubRegs */
    5765             :     true, /* CoveredBySubRegs */
    5766             :     hGPR_and_tcGPRSuperclasses,
    5767             :     hGPR_and_tcGPRGetRawAllocationOrder
    5768             :   };
    5769             : 
    5770             :   extern const TargetRegisterClass DPRRegClass = {
    5771             :     &ARMMCRegisterClasses[DPRRegClassID],
    5772             :     8, /* SpillSize */
    5773             :     8, /* SpillAlignment */
    5774             :     VTLists + 10,
    5775             :     DPRSubClassMask,
    5776             :     SuperRegIdxSeqs + 0,
    5777             :     LaneBitmask(0x0000000C),
    5778             :     0,
    5779             :     true, /* HasDisjunctSubRegs */
    5780             :     false, /* CoveredBySubRegs */
    5781             :     NullRegClasses,
    5782             :     DPRGetRawAllocationOrder
    5783             :   };
    5784             : 
    5785             :   extern const TargetRegisterClass DPR_VFP2RegClass = {
    5786             :     &ARMMCRegisterClasses[DPR_VFP2RegClassID],
    5787             :     8, /* SpillSize */
    5788             :     8, /* SpillAlignment */
    5789             :     VTLists + 10,
    5790             :     DPR_VFP2SubClassMask,
    5791             :     SuperRegIdxSeqs + 0,
    5792             :     LaneBitmask(0x0000000C),
    5793             :     0,
    5794             :     true, /* HasDisjunctSubRegs */
    5795             :     true, /* CoveredBySubRegs */
    5796             :     DPR_VFP2Superclasses,
    5797             :     nullptr
    5798             :   };
    5799             : 
    5800             :   extern const TargetRegisterClass DPR_8RegClass = {
    5801             :     &ARMMCRegisterClasses[DPR_8RegClassID],
    5802             :     8, /* SpillSize */
    5803             :     8, /* SpillAlignment */
    5804             :     VTLists + 10,
    5805             :     DPR_8SubClassMask,
    5806             :     SuperRegIdxSeqs + 0,
    5807             :     LaneBitmask(0x0000000C),
    5808             :     0,
    5809             :     true, /* HasDisjunctSubRegs */
    5810             :     true, /* CoveredBySubRegs */
    5811             :     DPR_8Superclasses,
    5812             :     nullptr
    5813             :   };
    5814             : 
    5815             :   extern const TargetRegisterClass GPRPairRegClass = {
    5816             :     &ARMMCRegisterClasses[GPRPairRegClassID],
    5817             :     8, /* SpillSize */
    5818             :     8, /* SpillAlignment */
    5819             :     VTLists + 33,
    5820             :     GPRPairSubClassMask,
    5821             :     SuperRegIdxSeqs + 8,
    5822             :     LaneBitmask(0x00000003),
    5823             :     0,
    5824             :     true, /* HasDisjunctSubRegs */
    5825             :     true, /* CoveredBySubRegs */
    5826             :     NullRegClasses,
    5827             :     nullptr
    5828             :   };
    5829             : 
    5830             :   extern const TargetRegisterClass GPRPair_with_gsub_1_in_rGPRRegClass = {
    5831             :     &ARMMCRegisterClasses[GPRPair_with_gsub_1_in_rGPRRegClassID],
    5832             :     8, /* SpillSize */
    5833             :     8, /* SpillAlignment */
    5834             :     VTLists + 33,
    5835             :     GPRPair_with_gsub_1_in_rGPRSubClassMask,
    5836             :     SuperRegIdxSeqs + 8,
    5837             :     LaneBitmask(0x00000003),
    5838             :     0,
    5839             :     true, /* HasDisjunctSubRegs */
    5840             :     true, /* CoveredBySubRegs */
    5841             :     GPRPair_with_gsub_1_in_rGPRSuperclasses,
    5842             :     nullptr
    5843             :   };
    5844             : 
    5845             :   extern const TargetRegisterClass GPRPair_with_gsub_0_in_tGPRRegClass = {
    5846             :     &ARMMCRegisterClasses[GPRPair_with_gsub_0_in_tGPRRegClassID],
    5847             :     8, /* SpillSize */
    5848             :     8, /* SpillAlignment */
    5849             :     VTLists + 33,
    5850             :     GPRPair_with_gsub_0_in_tGPRSubClassMask,
    5851             :     SuperRegIdxSeqs + 8,
    5852             :     LaneBitmask(0x00000003),
    5853             :     0,
    5854             :     true, /* HasDisjunctSubRegs */
    5855             :     true, /* CoveredBySubRegs */
    5856             :     GPRPair_with_gsub_0_in_tGPRSuperclasses,
    5857             :     nullptr
    5858             :   };
    5859             : 
    5860             :   extern const TargetRegisterClass GPRPair_with_gsub_0_in_hGPRRegClass = {
    5861             :     &ARMMCRegisterClasses[GPRPair_with_gsub_0_in_hGPRRegClassID],
    5862             :     8, /* SpillSize */
    5863             :     8, /* SpillAlignment */
    5864             :     VTLists + 33,
    5865             :     GPRPair_with_gsub_0_in_hGPRSubClassMask,
    5866             :     SuperRegIdxSeqs + 8,
    5867             :     LaneBitmask(0x00000003),
    5868             :     0,
    5869             :     true, /* HasDisjunctSubRegs */
    5870             :     true, /* CoveredBySubRegs */
    5871             :     GPRPair_with_gsub_0_in_hGPRSuperclasses,
    5872             :     nullptr
    5873             :   };
    5874             : 
    5875             :   extern const TargetRegisterClass GPRPair_with_gsub_0_in_tcGPRRegClass = {
    5876             :     &ARMMCRegisterClasses[GPRPair_with_gsub_0_in_tcGPRRegClassID],
    5877             :     8, /* SpillSize */
    5878             :     8, /* SpillAlignment */
    5879             :     VTLists + 33,
    5880             :     GPRPair_with_gsub_0_in_tcGPRSubClassMask,
    5881             :     SuperRegIdxSeqs + 8,
    5882             :     LaneBitmask(0x00000003),
    5883             :     0,
    5884             :     true, /* HasDisjunctSubRegs */
    5885             :     true, /* CoveredBySubRegs */
    5886             :     GPRPair_with_gsub_0_in_tcGPRSuperclasses,
    5887             :     nullptr
    5888             :   };
    5889             : 
    5890             :   extern const TargetRegisterClass GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClass = {
    5891             :     &ARMMCRegisterClasses[GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClassID],
    5892             :     8, /* SpillSize */
    5893             :     8, /* SpillAlignment */
    5894             :     VTLists + 33,
    5895             :     GPRPair_with_gsub_1_in_hGPR_and_rGPRSubClassMask,
    5896             :     SuperRegIdxSeqs + 8,
    5897             :     LaneBitmask(0x00000003),
    5898             :     0,
    5899             :     true, /* HasDisjunctSubRegs */
    5900             :     true, /* CoveredBySubRegs */
    5901             :     GPRPair_with_gsub_1_in_hGPR_and_rGPRSuperclasses,
    5902             :     nullptr
    5903             :   };
    5904             : 
    5905             :   extern const TargetRegisterClass GPRPair_with_gsub_1_in_tcGPRRegClass = {
    5906             :     &ARMMCRegisterClasses[GPRPair_with_gsub_1_in_tcGPRRegClassID],
    5907             :     8, /* SpillSize */
    5908             :     8, /* SpillAlignment */
    5909             :     VTLists + 33,
    5910             :     GPRPair_with_gsub_1_in_tcGPRSubClassMask,
    5911             :     SuperRegIdxSeqs + 8,
    5912             :     LaneBitmask(0x00000003),
    5913             :     0,
    5914             :     true, /* HasDisjunctSubRegs */
    5915             :     true, /* CoveredBySubRegs */
    5916             :     GPRPair_with_gsub_1_in_tcGPRSuperclasses,
    5917             :     nullptr
    5918             :   };
    5919             : 
    5920             :   extern const TargetRegisterClass GPRPair_with_gsub_1_in_GPRspRegClass = {
    5921             :     &ARMMCRegisterClasses[GPRPair_with_gsub_1_in_GPRspRegClassID],
    5922             :     8, /* SpillSize */
    5923             :     8, /* SpillAlignment */
    5924             :     VTLists + 33,
    5925             :     GPRPair_with_gsub_1_in_GPRspSubClassMask,
    5926             :     SuperRegIdxSeqs + 8,
    5927             :     LaneBitmask(0x00000003),
    5928             :     0,
    5929             :     true, /* HasDisjunctSubRegs */
    5930             :     true, /* CoveredBySubRegs */
    5931             :     GPRPair_with_gsub_1_in_GPRspSuperclasses,
    5932             :     nullptr
    5933             :   };
    5934             : 
    5935             :   extern const TargetRegisterClass DPairSpcRegClass = {
    5936             :     &ARMMCRegisterClasses[DPairSpcRegClassID],
    5937             :     16, /* SpillSize */
    5938             :     8, /* SpillAlignment */
    5939             :     VTLists + 4,
    5940             :     DPairSpcSubClassMask,
    5941             :     SuperRegIdxSeqs + 50,
    5942             :     LaneBitmask(0x000000CC),
    5943             :     0,
    5944             :     true, /* HasDisjunctSubRegs */
    5945             :     true, /* CoveredBySubRegs */
    5946             :     NullRegClasses,
    5947             :     nullptr
    5948             :   };
    5949             : 
    5950             :   extern const TargetRegisterClass DPairSpc_with_ssub_0RegClass = {
    5951             :     &ARMMCRegisterClasses[DPairSpc_with_ssub_0RegClassID],
    5952             :     16, /* SpillSize */
    5953             :     8, /* SpillAlignment */
    5954             :     VTLists + 4,
    5955             :     DPairSpc_with_ssub_0SubClassMask,
    5956             :     SuperRegIdxSeqs + 50,
    5957             :     LaneBitmask(0x000000CC),
    5958             :     0,
    5959             :     true, /* HasDisjunctSubRegs */
    5960             :     true, /* CoveredBySubRegs */
    5961             :     DPairSpc_with_ssub_0Superclasses,
    5962             :     nullptr
    5963             :   };
    5964             : 
    5965             :   extern const TargetRegisterClass DPairSpc_with_ssub_4RegClass = {
    5966             :     &ARMMCRegisterClasses[DPairSpc_with_ssub_4RegClassID],
    5967             :     16, /* SpillSize */
    5968             :     8, /* SpillAlignment */
    5969             :     VTLists + 4,
    5970             :     DPairSpc_with_ssub_4SubClassMask,
    5971             :     SuperRegIdxSeqs + 50,
    5972             :     LaneBitmask(0x000000CC),
    5973             :     0,
    5974             :     true, /* HasDisjunctSubRegs */
    5975             :     true, /* CoveredBySubRegs */
    5976             :     DPairSpc_with_ssub_4Superclasses,
    5977             :     nullptr
    5978             :   };
    5979             : 
    5980             :   extern const TargetRegisterClass DPairSpc_with_dsub_0_in_DPR_8RegClass = {
    5981             :     &ARMMCRegisterClasses[DPairSpc_with_dsub_0_in_DPR_8RegClassID],
    5982             :     16, /* SpillSize */
    5983             :     8, /* SpillAlignment */
    5984             :     VTLists + 4,
    5985             :     DPairSpc_with_dsub_0_in_DPR_8SubClassMask,
    5986             :     SuperRegIdxSeqs + 50,
    5987             :     LaneBitmask(0x000000CC),
    5988             :     0,
    5989             :     true, /* HasDisjunctSubRegs */
    5990             :     true, /* CoveredBySubRegs */
    5991             :     DPairSpc_with_dsub_0_in_DPR_8Superclasses,
    5992             :     nullptr
    5993             :   };
    5994             : 
    5995             :   extern const TargetRegisterClass DPairSpc_with_dsub_2_in_DPR_8RegClass = {
    5996             :     &ARMMCRegisterClasses[DPairSpc_with_dsub_2_in_DPR_8RegClassID],
    5997             :     16, /* SpillSize */
    5998             :     8, /* SpillAlignment */
    5999             :     VTLists + 4,
    6000             :     DPairSpc_with_dsub_2_in_DPR_8SubClassMask,
    6001             :     SuperRegIdxSeqs + 50,
    6002             :     LaneBitmask(0x000000CC),
    6003             :     0,
    6004             :     true, /* HasDisjunctSubRegs */
    6005             :     true, /* CoveredBySubRegs */
    6006             :     DPairSpc_with_dsub_2_in_DPR_8Superclasses,
    6007             :     nullptr
    6008             :   };
    6009             : 
    6010             :   extern const TargetRegisterClass DPairRegClass = {
    6011             :     &ARMMCRegisterClasses[DPairRegClassID],
    6012             :     16, /* SpillSize */
    6013             :     16, /* SpillAlignment */
    6014             :     VTLists + 26,
    6015             :     DPairSubClassMask,
    6016             :     SuperRegIdxSeqs + 69,
    6017             :     LaneBitmask(0x0000003C),
    6018             :     0,
    6019             :     true, /* HasDisjunctSubRegs */
    6020             :     true, /* CoveredBySubRegs */
    6021             :     NullRegClasses,
    6022             :     DPairGetRawAllocationOrder
    6023             :   };
    6024             : 
    6025             :   extern const TargetRegisterClass DPair_with_ssub_0RegClass = {
    6026             :     &ARMMCRegisterClasses[DPair_with_ssub_0RegClassID],
    6027             :     16, /* SpillSize */
    6028             :     16, /* SpillAlignment */
    6029             :     VTLists + 26,
    6030             :     DPair_with_ssub_0SubClassMask,
    6031             :     SuperRegIdxSeqs + 69,
    6032             :     LaneBitmask(0x0000003C),
    6033             :     0,
    6034             :     true, /* HasDisjunctSubRegs */
    6035             :     true, /* CoveredBySubRegs */
    6036             :     DPair_with_ssub_0Superclasses,
    6037             :     DPair_with_ssub_0GetRawAllocationOrder
    6038             :   };
    6039             : 
    6040             :   extern const TargetRegisterClass QPRRegClass = {
    6041             :     &ARMMCRegisterClasses[QPRRegClassID],
    6042             :     16, /* SpillSize */
    6043             :     16, /* SpillAlignment */
    6044             :     VTLists + 18,
    6045             :     QPRSubClassMask,
    6046             :     SuperRegIdxSeqs + 31,
    6047             :     LaneBitmask(0x0000003C),
    6048             :     0,
    6049             :     true, /* HasDisjunctSubRegs */
    6050             :     true, /* CoveredBySubRegs */
    6051             :     QPRSuperclasses,
    6052             :     QPRGetRawAllocationOrder
    6053             :   };
    6054             : 
    6055             :   extern const TargetRegisterClass DPair_with_ssub_2RegClass = {
    6056             :     &ARMMCRegisterClasses[DPair_with_ssub_2RegClassID],
    6057             :     16, /* SpillSize */
    6058             :     16, /* SpillAlignment */
    6059             :     VTLists + 26,
    6060             :     DPair_with_ssub_2SubClassMask,
    6061             :     SuperRegIdxSeqs + 69,
    6062             :     LaneBitmask(0x0000003C),
    6063             :     0,
    6064             :     true, /* HasDisjunctSubRegs */
    6065             :     true, /* CoveredBySubRegs */
    6066             :     DPair_with_ssub_2Superclasses,
    6067             :     DPair_with_ssub_2GetRawAllocationOrder
    6068             :   };
    6069             : 
    6070             :   extern const TargetRegisterClass DPair_with_dsub_0_in_DPR_8RegClass = {
    6071             :     &ARMMCRegisterClasses[DPair_with_dsub_0_in_DPR_8RegClassID],
    6072             :     16, /* SpillSize */
    6073             :     16, /* SpillAlignment */
    6074             :     VTLists + 26,
    6075             :     DPair_with_dsub_0_in_DPR_8SubClassMask,
    6076             :     SuperRegIdxSeqs + 69,
    6077             :     LaneBitmask(0x0000003C),
    6078             :     0,
    6079             :     true, /* HasDisjunctSubRegs */
    6080             :     true, /* CoveredBySubRegs */
    6081             :     DPair_with_dsub_0_in_DPR_8Superclasses,
    6082             :     DPair_with_dsub_0_in_DPR_8GetRawAllocationOrder
    6083             :   };
    6084             : 
    6085             :   extern const TargetRegisterClass QPR_VFP2RegClass = {
    6086             :     &ARMMCRegisterClasses[QPR_VFP2RegClassID],
    6087             :     16, /* SpillSize */
    6088             :     16, /* SpillAlignment */
    6089             :     VTLists + 26,
    6090             :     QPR_VFP2SubClassMask,
    6091             :     SuperRegIdxSeqs + 31,
    6092             :     LaneBitmask(0x0000003C),
    6093             :     0,
    6094             :     true, /* HasDisjunctSubRegs */
    6095             :     true, /* CoveredBySubRegs */
    6096             :     QPR_VFP2Superclasses,
    6097             :     nullptr
    6098             :   };
    6099             : 
    6100             :   extern const TargetRegisterClass DPair_with_dsub_1_in_DPR_8RegClass = {
    6101             :     &ARMMCRegisterClasses[DPair_with_dsub_1_in_DPR_8RegClassID],
    6102             :     16, /* SpillSize */
    6103             :     16, /* SpillAlignment */
    6104             :     VTLists + 26,
    6105             :     DPair_with_dsub_1_in_DPR_8SubClassMask,
    6106             :     SuperRegIdxSeqs + 69,
    6107             :     LaneBitmask(0x0000003C),
    6108             :     0,
    6109             :     true, /* HasDisjunctSubRegs */
    6110             :     true, /* CoveredBySubRegs */
    6111             :     DPair_with_dsub_1_in_DPR_8Superclasses,
    6112             :     DPair_with_dsub_1_in_DPR_8GetRawAllocationOrder
    6113             :   };
    6114             : 
    6115             :   extern const TargetRegisterClass QPR_8RegClass = {
    6116             :     &ARMMCRegisterClasses[QPR_8RegClassID],
    6117             :     16, /* SpillSize */
    6118             :     16, /* SpillAlignment */
    6119             :     VTLists + 26,
    6120             :     QPR_8SubClassMask,
    6121             :     SuperRegIdxSeqs + 31,
    6122             :     LaneBitmask(0x0000003C),
    6123             :     0,
    6124             :     true, /* HasDisjunctSubRegs */
    6125             :     true, /* CoveredBySubRegs */
    6126             :     QPR_8Superclasses,
    6127             :     nullptr
    6128             :   };
    6129             : 
    6130             :   extern const TargetRegisterClass DTripleRegClass = {
    6131             :     &ARMMCRegisterClasses[DTripleRegClassID],
    6132             :     24, /* SpillSize */
    6133             :     8, /* SpillAlignment */
    6134             :     VTLists + 33,
    6135             :     DTripleSubClassMask,
    6136             :     SuperRegIdxSeqs + 62,
    6137             :     LaneBitmask(0x000000FC),
    6138             :     0,
    6139             :     true, /* HasDisjunctSubRegs */
    6140             :     true, /* CoveredBySubRegs */
    6141             :     NullRegClasses,
    6142             :     nullptr
    6143             :   };
    6144             : 
    6145             :   extern const TargetRegisterClass DTripleSpcRegClass = {
    6146             :     &ARMMCRegisterClasses[DTripleSpcRegClassID],
    6147             :     24, /* SpillSize */
    6148             :     8, /* SpillAlignment */
    6149             :     VTLists + 33,
    6150             :     DTripleSpcSubClassMask,
    6151             :     SuperRegIdxSeqs + 37,
    6152             :     LaneBitmask(0x00000CCC),
    6153             :     0,
    6154             :     true, /* HasDisjunctSubRegs */
    6155             :     true, /* CoveredBySubRegs */
    6156             :     NullRegClasses,
    6157             :     nullptr
    6158             :   };
    6159             : 
    6160             :   extern const TargetRegisterClass DTripleSpc_with_ssub_0RegClass = {
    6161             :     &ARMMCRegisterClasses[DTripleSpc_with_ssub_0RegClassID],
    6162             :     24, /* SpillSize */
    6163             :     8, /* SpillAlignment */
    6164             :     VTLists + 33,
    6165             :     DTripleSpc_with_ssub_0SubClassMask,
    6166             :     SuperRegIdxSeqs + 37,
    6167             :     LaneBitmask(0x00000CCC),
    6168             :     0,
    6169             :     true, /* HasDisjunctSubRegs */
    6170             :     true, /* CoveredBySubRegs */
    6171             :     DTripleSpc_with_ssub_0Superclasses,
    6172             :     nullptr
    6173             :   };
    6174             : 
    6175             :   extern const TargetRegisterClass DTriple_with_ssub_0RegClass = {
    6176             :     &ARMMCRegisterClasses[DTriple_with_ssub_0RegClassID],
    6177             :     24, /* SpillSize */
    6178             :     8, /* SpillAlignment */
    6179             :     VTLists + 33,
    6180             :     DTriple_with_ssub_0SubClassMask,
    6181             :     SuperRegIdxSeqs + 62,
    6182             :     LaneBitmask(0x000000FC),
    6183             :     0,
    6184             :     true, /* HasDisjunctSubRegs */
    6185             :     true, /* CoveredBySubRegs */
    6186             :     DTriple_with_ssub_0Superclasses,
    6187             :     nullptr
    6188             :   };
    6189             : 
    6190             :   extern const TargetRegisterClass DTriple_with_qsub_0_in_QPRRegClass = {
    6191             :     &ARMMCRegisterClasses[DTriple_with_qsub_0_in_QPRRegClassID],
    6192             :     24, /* SpillSize */
    6193             :     8, /* SpillAlignment */
    6194             :     VTLists + 33,
    6195             :     DTriple_with_qsub_0_in_QPRSubClassMask,
    6196             :     SuperRegIdxSeqs + 45,
    6197             :     LaneBitmask(0x000000FC),
    6198             :     0,
    6199             :     true, /* HasDisjunctSubRegs */
    6200             :     true, /* CoveredBySubRegs */
    6201             :     DTriple_with_qsub_0_in_QPRSuperclasses,
    6202             :     nullptr
    6203             :   };
    6204             : 
    6205             :   extern const TargetRegisterClass DTriple_with_ssub_2RegClass = {
    6206             :     &ARMMCRegisterClasses[DTriple_with_ssub_2RegClassID],
    6207             :     24, /* SpillSize */
    6208             :     8, /* SpillAlignment */
    6209             :     VTLists + 33,
    6210             :     DTriple_with_ssub_2SubClassMask,
    6211             :     SuperRegIdxSeqs + 62,
    6212             :     LaneBitmask(0x000000FC),
    6213             :     0,
    6214             :     true, /* HasDisjunctSubRegs */
    6215             :     true, /* CoveredBySubRegs */
    6216             :     DTriple_with_ssub_2Superclasses,
    6217             :     nullptr
    6218             :   };
    6219             : 
    6220             :   extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
    6221             :     &ARMMCRegisterClasses[DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
    6222             :     24, /* SpillSize */
    6223             :     8, /* SpillAlignment */
    6224             :     VTLists + 33,
    6225             :     DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
    6226             :     SuperRegIdxSeqs + 57,
    6227             :     LaneBitmask(0x000000FC),
    6228             :     0,
    6229             :     true, /* HasDisjunctSubRegs */
    6230             :     true, /* CoveredBySubRegs */
    6231             :     DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
    6232             :     nullptr
    6233             :   };
    6234             : 
    6235             :   extern const TargetRegisterClass DTripleSpc_with_ssub_4RegClass = {
    6236             :     &ARMMCRegisterClasses[DTripleSpc_with_ssub_4RegClassID],
    6237             :     24, /* SpillSize */
    6238             :     8, /* SpillAlignment */
    6239             :     VTLists + 33,
    6240             :     DTripleSpc_with_ssub_4SubClassMask,
    6241             :     SuperRegIdxSeqs + 37,
    6242             :     LaneBitmask(0x00000CCC),
    6243             :     0,
    6244             :     true, /* HasDisjunctSubRegs */
    6245             :     true, /* CoveredBySubRegs */
    6246             :     DTripleSpc_with_ssub_4Superclasses,
    6247             :     nullptr
    6248             :   };
    6249             : 
    6250             :   extern const TargetRegisterClass DTriple_with_ssub_4RegClass = {
    6251             :     &ARMMCRegisterClasses[DTriple_with_ssub_4RegClassID],
    6252             :     24, /* SpillSize */
    6253             :     8, /* SpillAlignment */
    6254             :     VTLists + 33,
    6255             :     DTriple_with_ssub_4SubClassMask,
    6256             :     SuperRegIdxSeqs + 62,
    6257             :     LaneBitmask(0x000000FC),
    6258             :     0,
    6259             :     true, /* HasDisjunctSubRegs */
    6260             :     true, /* CoveredBySubRegs */
    6261             :     DTriple_with_ssub_4Superclasses,
    6262             :     nullptr
    6263             :   };
    6264             : 
    6265             :   extern const TargetRegisterClass DTripleSpc_with_ssub_8RegClass = {
    6266             :     &ARMMCRegisterClasses[DTripleSpc_with_ssub_8RegClassID],
    6267             :     24, /* SpillSize */
    6268             :     8, /* SpillAlignment */
    6269             :     VTLists + 33,
    6270             :     DTripleSpc_with_ssub_8SubClassMask,
    6271             :     SuperRegIdxSeqs + 37,
    6272             :     LaneBitmask(0x00000CCC),
    6273             :     0,
    6274             :     true, /* HasDisjunctSubRegs */
    6275             :     true, /* CoveredBySubRegs */
    6276             :     DTripleSpc_with_ssub_8Superclasses,
    6277             :     nullptr
    6278             :   };
    6279             : 
    6280             :   extern const TargetRegisterClass DTripleSpc_with_dsub_0_in_DPR_8RegClass = {
    6281             :     &ARMMCRegisterClasses[DTripleSpc_with_dsub_0_in_DPR_8RegClassID],
    6282             :     24, /* SpillSize */
    6283             :     8, /* SpillAlignment */
    6284             :     VTLists + 33,
    6285             :     DTripleSpc_with_dsub_0_in_DPR_8SubClassMask,
    6286             :     SuperRegIdxSeqs + 37,
    6287             :     LaneBitmask(0x00000CCC),
    6288             :     0,
    6289             :     true, /* HasDisjunctSubRegs */
    6290             :     true, /* CoveredBySubRegs */
    6291             :     DTripleSpc_with_dsub_0_in_DPR_8Superclasses,
    6292             :     nullptr
    6293             :   };
    6294             : 
    6295             :   extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8RegClass = {
    6296             :     &ARMMCRegisterClasses[DTriple_with_dsub_0_in_DPR_8RegClassID],
    6297             :     24, /* SpillSize */
    6298             :     8, /* SpillAlignment */
    6299             :     VTLists + 33,
    6300             :     DTriple_with_dsub_0_in_DPR_8SubClassMask,
    6301             :     SuperRegIdxSeqs + 62,
    6302             :     LaneBitmask(0x000000FC),
    6303             :     0,
    6304             :     true, /* HasDisjunctSubRegs */
    6305             :     true, /* CoveredBySubRegs */
    6306             :     DTriple_with_dsub_0_in_DPR_8Superclasses,
    6307             :     nullptr
    6308             :   };
    6309             : 
    6310             :   extern const TargetRegisterClass DTriple_with_qsub_0_in_QPR_VFP2RegClass = {
    6311             :     &ARMMCRegisterClasses[DTriple_with_qsub_0_in_QPR_VFP2RegClassID],
    6312             :     24, /* SpillSize */
    6313             :     8, /* SpillAlignment */
    6314             :     VTLists + 33,
    6315             :     DTriple_with_qsub_0_in_QPR_VFP2SubClassMask,
    6316             :     SuperRegIdxSeqs + 45,
    6317             :     LaneBitmask(0x000000FC),
    6318             :     0,
    6319             :     true, /* HasDisjunctSubRegs */
    6320             :     true, /* CoveredBySubRegs */
    6321             :     DTriple_with_qsub_0_in_QPR_VFP2Superclasses,
    6322             :     nullptr
    6323             :   };
    6324             : 
    6325             :   extern const TargetRegisterClass DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
    6326             :     &ARMMCRegisterClasses[DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
    6327             :     24, /* SpillSize */
    6328             :     8, /* SpillAlignment */
    6329             :     VTLists + 33,
    6330             :     DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
    6331             :     SuperRegIdxSeqs + 57,
    6332             :     LaneBitmask(0x000000FC),
    6333             :     0,
    6334             :     true, /* HasDisjunctSubRegs */
    6335             :     true, /* CoveredBySubRegs */
    6336             :     DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
    6337             :     nullptr
    6338             :   };
    6339             : 
    6340             :   extern const TargetRegisterClass DTriple_with_dsub_1_in_DPR_8RegClass = {
    6341             :     &ARMMCRegisterClasses[DTriple_with_dsub_1_in_DPR_8RegClassID],
    6342             :     24, /* SpillSize */
    6343             :     8, /* SpillAlignment */
    6344             :     VTLists + 33,
    6345             :     DTriple_with_dsub_1_in_DPR_8SubClassMask,
    6346             :     SuperRegIdxSeqs + 62,
    6347             :     LaneBitmask(0x000000FC),
    6348             :     0,
    6349             :     true, /* HasDisjunctSubRegs */
    6350             :     true, /* CoveredBySubRegs */
    6351             :     DTriple_with_dsub_1_in_DPR_8Superclasses,
    6352             :     nullptr
    6353             :   };
    6354             : 
    6355             :   extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass = {
    6356             :     &ARMMCRegisterClasses[DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID],
    6357             :     24, /* SpillSize */
    6358             :     8, /* SpillAlignment */
    6359             :     VTLists + 33,
    6360             :     DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2SubClassMask,
    6361             :     SuperRegIdxSeqs + 57,
    6362             :     LaneBitmask(0x000000FC),
    6363             :     0,
    6364             :     true, /* HasDisjunctSubRegs */
    6365             :     true, /* CoveredBySubRegs */
    6366             :     DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Superclasses,
    6367             :     nullptr
    6368             :   };
    6369             : 
    6370             :   extern const TargetRegisterClass DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClass = {
    6371             :     &ARMMCRegisterClasses[DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClassID],
    6372             :     24, /* SpillSize */
    6373             :     8, /* SpillAlignment */
    6374             :     VTLists + 33,
    6375             :     DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRSubClassMask,
    6376             :     SuperRegIdxSeqs + 45,
    6377             :     LaneBitmask(0x000000FC),
    6378             :     0,
    6379             :     true, /* HasDisjunctSubRegs */
    6380             :     true, /* CoveredBySubRegs */
    6381             :     DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRSuperclasses,
    6382             :     nullptr
    6383             :   };
    6384             : 
    6385             :   extern const TargetRegisterClass DTripleSpc_with_dsub_2_in_DPR_8RegClass = {
    6386             :     &ARMMCRegisterClasses[DTripleSpc_with_dsub_2_in_DPR_8RegClassID],
    6387             :     24, /* SpillSize */
    6388             :     8, /* SpillAlignment */
    6389             :     VTLists + 33,
    6390             :     DTripleSpc_with_dsub_2_in_DPR_8SubClassMask,
    6391             :     SuperRegIdxSeqs + 37,
    6392             :     LaneBitmask(0x00000CCC),
    6393             :     0,
    6394             :     true, /* HasDisjunctSubRegs */
    6395             :     true, /* CoveredBySubRegs */
    6396             :     DTripleSpc_with_dsub_2_in_DPR_8Superclasses,
    6397             :     nullptr
    6398             :   };
    6399             : 
    6400             :   extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8RegClass = {
    6401             :     &ARMMCRegisterClasses[DTriple_with_dsub_2_in_DPR_8RegClassID],
    6402             :     24, /* SpillSize */
    6403             :     8, /* SpillAlignment */
    6404             :     VTLists + 33,
    6405             :     DTriple_with_dsub_2_in_DPR_8SubClassMask,
    6406             :     SuperRegIdxSeqs + 62,
    6407             :     LaneBitmask(0x000000FC),
    6408             :     0,
    6409             :     true, /* HasDisjunctSubRegs */
    6410             :     true, /* CoveredBySubRegs */
    6411             :     DTriple_with_dsub_2_in_DPR_8Superclasses,
    6412             :     nullptr
    6413             :   };
    6414             : 
    6415             :   extern const TargetRegisterClass DTripleSpc_with_dsub_4_in_DPR_8RegClass = {
    6416             :     &ARMMCRegisterClasses[DTripleSpc_with_dsub_4_in_DPR_8RegClassID],
    6417             :     24, /* SpillSize */
    6418             :     8, /* SpillAlignment */
    6419             :     VTLists + 33,
    6420             :     DTripleSpc_with_dsub_4_in_DPR_8SubClassMask,
    6421             :     SuperRegIdxSeqs + 37,
    6422             :     LaneBitmask(0x00000CCC),
    6423             :     0,
    6424             :     true, /* HasDisjunctSubRegs */
    6425             :     true, /* CoveredBySubRegs */
    6426             :     DTripleSpc_with_dsub_4_in_DPR_8Superclasses,
    6427             :     nullptr
    6428             :   };
    6429             : 
    6430             :   extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
    6431             :     &ARMMCRegisterClasses[DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
    6432             :     24, /* SpillSize */
    6433             :     8, /* SpillAlignment */
    6434             :     VTLists + 33,
    6435             :     DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
    6436             :     SuperRegIdxSeqs + 57,
    6437             :     LaneBitmask(0x000000FC),
    6438             :     0,
    6439             :     true, /* HasDisjunctSubRegs */
    6440             :     true, /* CoveredBySubRegs */
    6441             :     DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
    6442             :     nullptr
    6443             :   };
    6444             : 
    6445             :   extern const TargetRegisterClass DTriple_with_qsub_0_in_QPR_8RegClass = {
    6446             :     &ARMMCRegisterClasses[DTriple_with_qsub_0_in_QPR_8RegClassID],
    6447             :     24, /* SpillSize */
    6448             :     8, /* SpillAlignment */
    6449             :     VTLists + 33,
    6450             :     DTriple_with_qsub_0_in_QPR_8SubClassMask,
    6451             :     SuperRegIdxSeqs + 45,
    6452             :     LaneBitmask(0x000000FC),
    6453             :     0,
    6454             :     true, /* HasDisjunctSubRegs */
    6455             :     true, /* CoveredBySubRegs */
    6456             :     DTriple_with_qsub_0_in_QPR_8Superclasses,
    6457             :     nullptr
    6458             :   };
    6459             : 
    6460             :   extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClass = {
    6461             :     &ARMMCRegisterClasses[DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClassID],
    6462             :     24, /* SpillSize */
    6463             :     8, /* SpillAlignment */
    6464             :     VTLists + 33,
    6465             :     DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRSubClassMask,
    6466             :     SuperRegIdxSeqs + 45,
    6467             :     LaneBitmask(0x000000FC),
    6468             :     0,
    6469             :     true, /* HasDisjunctSubRegs */
    6470             :     true, /* CoveredBySubRegs */
    6471             :     DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRSuperclasses,
    6472             :     nullptr
    6473             :   };
    6474             : 
    6475             :   extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass = {
    6476             :     &ARMMCRegisterClasses[DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID],
    6477             :     24, /* SpillSize */
    6478             :     8, /* SpillAlignment */
    6479             :     VTLists + 33,
    6480             :     DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8SubClassMask,
    6481             :     SuperRegIdxSeqs + 57,
    6482             :     LaneBitmask(0x000000FC),
    6483             :     0,
    6484             :     true, /* HasDisjunctSubRegs */
    6485             :     true, /* CoveredBySubRegs */
    6486             :     DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Superclasses,
    6487             :     nullptr
    6488             :   };
    6489             : 
    6490             :   extern const TargetRegisterClass DQuadSpcRegClass = {
    6491             :     &ARMMCRegisterClasses[DQuadSpcRegClassID],
    6492             :     32, /* SpillSize */
    6493             :     8, /* SpillAlignment */
    6494             :     VTLists + 6,
    6495             :     DQuadSpcSubClassMask,
    6496             :     SuperRegIdxSeqs + 37,
    6497             :     LaneBitmask(0x00000CCC),
    6498             :     0,
    6499             :     true, /* HasDisjunctSubRegs */
    6500             :     true, /* CoveredBySubRegs */
    6501             :     DQuadSpcSuperclasses,
    6502             :     nullptr
    6503             :   };
    6504             : 
    6505             :   extern const TargetRegisterClass DQuadSpc_with_ssub_0RegClass = {
    6506             :     &ARMMCRegisterClasses[DQuadSpc_with_ssub_0RegClassID],
    6507             :     32, /* SpillSize */
    6508             :     8, /* SpillAlignment */
    6509             :     VTLists + 6,
    6510             :     DQuadSpc_with_ssub_0SubClassMask,
    6511             :     SuperRegIdxSeqs + 37,
    6512             :     LaneBitmask(0x00000CCC),
    6513             :     0,
    6514             :     true, /* HasDisjunctSubRegs */
    6515             :     true, /* CoveredBySubRegs */
    6516             :     DQuadSpc_with_ssub_0Superclasses,
    6517             :     nullptr
    6518             :   };
    6519             : 
    6520             :   extern const TargetRegisterClass DQuadSpc_with_ssub_4RegClass = {
    6521             :     &ARMMCRegisterClasses[DQuadSpc_with_ssub_4RegClassID],
    6522             :     32, /* SpillSize */
    6523             :     8, /* SpillAlignment */
    6524             :     VTLists + 6,
    6525             :     DQuadSpc_with_ssub_4SubClassMask,
    6526             :     SuperRegIdxSeqs + 37,
    6527             :     LaneBitmask(0x00000CCC),
    6528             :     0,
    6529             :     true, /* HasDisjunctSubRegs */
    6530             :     true, /* CoveredBySubRegs */
    6531             :     DQuadSpc_with_ssub_4Superclasses,
    6532             :     nullptr
    6533             :   };
    6534             : 
    6535             :   extern const TargetRegisterClass DQuadSpc_with_ssub_8RegClass = {
    6536             :     &ARMMCRegisterClasses[DQuadSpc_with_ssub_8RegClassID],
    6537             :     32, /* SpillSize */
    6538             :     8, /* SpillAlignment */
    6539             :     VTLists + 6,
    6540             :     DQuadSpc_with_ssub_8SubClassMask,
    6541             :     SuperRegIdxSeqs + 37,
    6542             :     LaneBitmask(0x00000CCC),
    6543             :     0,
    6544             :     true, /* HasDisjunctSubRegs */
    6545             :     true, /* CoveredBySubRegs */
    6546             :     DQuadSpc_with_ssub_8Superclasses,
    6547             :     nullptr
    6548             :   };
    6549             : 
    6550             :   extern const TargetRegisterClass DQuadSpc_with_dsub_0_in_DPR_8RegClass = {
    6551             :     &ARMMCRegisterClasses[DQuadSpc_with_dsub_0_in_DPR_8RegClassID],
    6552             :     32, /* SpillSize */
    6553             :     8, /* SpillAlignment */
    6554             :     VTLists + 6,
    6555             :     DQuadSpc_with_dsub_0_in_DPR_8SubClassMask,
    6556             :     SuperRegIdxSeqs + 37,
    6557             :     LaneBitmask(0x00000CCC),
    6558             :     0,
    6559             :     true, /* HasDisjunctSubRegs */
    6560             :     true, /* CoveredBySubRegs */
    6561             :     DQuadSpc_with_dsub_0_in_DPR_8Superclasses,
    6562             :     nullptr
    6563             :   };
    6564             : 
    6565             :   extern const TargetRegisterClass DQuadSpc_with_dsub_2_in_DPR_8RegClass = {
    6566             :     &ARMMCRegisterClasses[DQuadSpc_with_dsub_2_in_DPR_8RegClassID],
    6567             :     32, /* SpillSize */
    6568             :     8, /* SpillAlignment */
    6569             :     VTLists + 6,
    6570             :     DQuadSpc_with_dsub_2_in_DPR_8SubClassMask,
    6571             :     SuperRegIdxSeqs + 37,
    6572             :     LaneBitmask(0x00000CCC),
    6573             :     0,
    6574             :     true, /* HasDisjunctSubRegs */
    6575             :     true, /* CoveredBySubRegs */
    6576             :     DQuadSpc_with_dsub_2_in_DPR_8Superclasses,
    6577             :     nullptr
    6578             :   };
    6579             : 
    6580             :   extern const TargetRegisterClass DQuadSpc_with_dsub_4_in_DPR_8RegClass = {
    6581             :     &ARMMCRegisterClasses[DQuadSpc_with_dsub_4_in_DPR_8RegClassID],
    6582             :     32, /* SpillSize */
    6583             :     8, /* SpillAlignment */
    6584             :     VTLists + 6,
    6585             :     DQuadSpc_with_dsub_4_in_DPR_8SubClassMask,
    6586             :     SuperRegIdxSeqs + 37,
    6587             :     LaneBitmask(0x00000CCC),
    6588             :     0,
    6589             :     true, /* HasDisjunctSubRegs */
    6590             :     true, /* CoveredBySubRegs */
    6591             :     DQuadSpc_with_dsub_4_in_DPR_8Superclasses,
    6592             :     nullptr
    6593             :   };
    6594             : 
    6595             :   extern const TargetRegisterClass DQuadRegClass = {
    6596             :     &ARMMCRegisterClasses[DQuadRegClassID],
    6597             :     32, /* SpillSize */
    6598             :     32, /* SpillAlignment */
    6599             :     VTLists + 6,
    6600             :     DQuadSubClassMask,
    6601             :     SuperRegIdxSeqs + 81,
    6602             :     LaneBitmask(0x000003FC),
    6603             :     0,
    6604             :     true, /* HasDisjunctSubRegs */
    6605             :     true, /* CoveredBySubRegs */
    6606             :     NullRegClasses,
    6607             :     nullptr
    6608             :   };
    6609             : 
    6610             :   extern const TargetRegisterClass DQuad_with_ssub_0RegClass = {
    6611             :     &ARMMCRegisterClasses[DQuad_with_ssub_0RegClassID],
    6612             :     32, /* SpillSize */
    6613             :     32, /* SpillAlignment */
    6614             :     VTLists + 6,
    6615             :     DQuad_with_ssub_0SubClassMask,
    6616             :     SuperRegIdxSeqs + 81,
    6617             :     LaneBitmask(0x000003FC),
    6618             :     0,
    6619             :     true, /* HasDisjunctSubRegs */
    6620             :     true, /* CoveredBySubRegs */
    6621             :     DQuad_with_ssub_0Superclasses,
    6622             :     nullptr
    6623             :   };
    6624             : 
    6625             :   extern const TargetRegisterClass DQuad_with_ssub_2RegClass = {
    6626             :     &ARMMCRegisterClasses[DQuad_with_ssub_2RegClassID],
    6627             :     32, /* SpillSize */
    6628             :     32, /* SpillAlignment */
    6629             :     VTLists + 6,
    6630             :     DQuad_with_ssub_2SubClassMask,
    6631             :     SuperRegIdxSeqs + 81,
    6632             :     LaneBitmask(0x000003FC),
    6633             :     0,
    6634             :     true, /* HasDisjunctSubRegs */
    6635             :     true, /* CoveredBySubRegs */
    6636             :     DQuad_with_ssub_2Superclasses,
    6637             :     nullptr
    6638             :   };
    6639             : 
    6640             :   extern const TargetRegisterClass QQPRRegClass = {
    6641             :     &ARMMCRegisterClasses[QQPRRegClassID],
    6642             :     32, /* SpillSize */
    6643             :     32, /* SpillAlignment */
    6644             :     VTLists + 6,
    6645             :     QQPRSubClassMask,
    6646             :     SuperRegIdxSeqs + 77,
    6647             :     LaneBitmask(0x000003FC),
    6648             :     0,
    6649             :     true, /* HasDisjunctSubRegs */
    6650             :     true, /* CoveredBySubRegs */
    6651             :     QQPRSuperclasses,
    6652             :     QQPRGetRawAllocationOrder
    6653             :   };
    6654             : 
    6655             :   extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
    6656             :     &ARMMCRegisterClasses[DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
    6657             :     32, /* SpillSize */
    6658             :     32, /* SpillAlignment */
    6659             :     VTLists + 6,
    6660             :     DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
    6661             :     SuperRegIdxSeqs + 42,
    6662             :     LaneBitmask(0x000003FC),
    6663             :     0,
    6664             :     true, /* HasDisjunctSubRegs */
    6665             :     true, /* CoveredBySubRegs */
    6666             :     DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
    6667             :     nullptr
    6668             :   };
    6669             : 
    6670             :   extern const TargetRegisterClass DQuad_with_ssub_4RegClass = {
    6671             :     &ARMMCRegisterClasses[DQuad_with_ssub_4RegClassID],
    6672             :     32, /* SpillSize */
    6673             :     32, /* SpillAlignment */
    6674             :     VTLists + 6,
    6675             :     DQuad_with_ssub_4SubClassMask,
    6676             :     SuperRegIdxSeqs + 81,
    6677             :     LaneBitmask(0x000003FC),
    6678             :     0,
    6679             :     true, /* HasDisjunctSubRegs */
    6680             :     true, /* CoveredBySubRegs */
    6681             :     DQuad_with_ssub_4Superclasses,
    6682             :     nullptr
    6683             :   };
    6684             : 
    6685             :   extern const TargetRegisterClass DQuad_with_ssub_6RegClass = {
    6686             :     &ARMMCRegisterClasses[DQuad_with_ssub_6RegClassID],
    6687             :     32, /* SpillSize */
    6688             :     32, /* SpillAlignment */
    6689             :     VTLists + 6,
    6690             :     DQuad_with_ssub_6SubClassMask,
    6691             :     SuperRegIdxSeqs + 81,
    6692             :     LaneBitmask(0x000003FC),
    6693             :     0,
    6694             :     true, /* HasDisjunctSubRegs */
    6695             :     true, /* CoveredBySubRegs */
    6696             :     DQuad_with_ssub_6Superclasses,
    6697             :     nullptr
    6698             :   };
    6699             : 
    6700             :   extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8RegClass = {
    6701             :     &ARMMCRegisterClasses[DQuad_with_dsub_0_in_DPR_8RegClassID],
    6702             :     32, /* SpillSize */
    6703             :     32, /* SpillAlignment */
    6704             :     VTLists + 6,
    6705             :     DQuad_with_dsub_0_in_DPR_8SubClassMask,
    6706             :     SuperRegIdxSeqs + 81,
    6707             :     LaneBitmask(0x000003FC),
    6708             :     0,
    6709             :     true, /* HasDisjunctSubRegs */
    6710             :     true, /* CoveredBySubRegs */
    6711             :     DQuad_with_dsub_0_in_DPR_8Superclasses,
    6712             :     nullptr
    6713             :   };
    6714             : 
    6715             :   extern const TargetRegisterClass DQuad_with_qsub_0_in_QPR_VFP2RegClass = {
    6716             :     &ARMMCRegisterClasses[DQuad_with_qsub_0_in_QPR_VFP2RegClassID],
    6717             :     32, /* SpillSize */
    6718             :     32, /* SpillAlignment */
    6719             :     VTLists + 6,
    6720             :     DQuad_with_qsub_0_in_QPR_VFP2SubClassMask,
    6721             :     SuperRegIdxSeqs + 77,
    6722             :     LaneBitmask(0x000003FC),
    6723             :     0,
    6724             :     true, /* HasDisjunctSubRegs */
    6725             :     true, /* CoveredBySubRegs */
    6726             :     DQuad_with_qsub_0_in_QPR_VFP2Superclasses,
    6727             :     DQuad_with_qsub_0_in_QPR_VFP2GetRawAllocationOrder
    6728             :   };
    6729             : 
    6730             :   extern const TargetRegisterClass DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
    6731             :     &ARMMCRegisterClasses[DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
    6732             :     32, /* SpillSize */
    6733             :     32, /* SpillAlignment */
    6734             :     VTLists + 6,
    6735             :     DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
    6736             :     SuperRegIdxSeqs + 42,
    6737             :     LaneBitmask(0x000003FC),
    6738             :     0,
    6739             :     true, /* HasDisjunctSubRegs */
    6740             :     true, /* CoveredBySubRegs */
    6741             :     DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
    6742             :     nullptr
    6743             :   };
    6744             : 
    6745             :   extern const TargetRegisterClass DQuad_with_dsub_1_in_DPR_8RegClass = {
    6746             :     &ARMMCRegisterClasses[DQuad_with_dsub_1_in_DPR_8RegClassID],
    6747             :     32, /* SpillSize */
    6748             :     32, /* SpillAlignment */
    6749             :     VTLists + 6,
    6750             :     DQuad_with_dsub_1_in_DPR_8SubClassMask,
    6751             :     SuperRegIdxSeqs + 81,
    6752             :     LaneBitmask(0x000003FC),
    6753             :     0,
    6754             :     true, /* HasDisjunctSubRegs */
    6755             :     true, /* CoveredBySubRegs */
    6756             :     DQuad_with_dsub_1_in_DPR_8Superclasses,
    6757             :     nullptr
    6758             :   };
    6759             : 
    6760             :   extern const TargetRegisterClass DQuad_with_qsub_1_in_QPR_VFP2RegClass = {
    6761             :     &ARMMCRegisterClasses[DQuad_with_qsub_1_in_QPR_VFP2RegClassID],
    6762             :     32, /* SpillSize */
    6763             :     32, /* SpillAlignment */
    6764             :     VTLists + 6,
    6765             :     DQuad_with_qsub_1_in_QPR_VFP2SubClassMask,
    6766             :     SuperRegIdxSeqs + 77,
    6767             :     LaneBitmask(0x000003FC),
    6768             :     0,
    6769             :     true, /* HasDisjunctSubRegs */
    6770             :     true, /* CoveredBySubRegs */
    6771             :     DQuad_with_qsub_1_in_QPR_VFP2Superclasses,
    6772             :     DQuad_with_qsub_1_in_QPR_VFP2GetRawAllocationOrder
    6773             :   };
    6774             : 
    6775             :   extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass = {
    6776             :     &ARMMCRegisterClasses[DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID],
    6777             :     32, /* SpillSize */
    6778             :     32, /* SpillAlignment */
    6779             :     VTLists + 6,
    6780             :     DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2SubClassMask,
    6781             :     SuperRegIdxSeqs + 42,
    6782             :     LaneBitmask(0x000003FC),
    6783             :     0,
    6784             :     true, /* HasDisjunctSubRegs */
    6785             :     true, /* CoveredBySubRegs */
    6786             :     DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Superclasses,
    6787             :     nullptr
    6788             :   };
    6789             : 
    6790             :   extern const TargetRegisterClass DQuad_with_dsub_2_in_DPR_8RegClass = {
    6791             :     &ARMMCRegisterClasses[DQuad_with_dsub_2_in_DPR_8RegClassID],
    6792             :     32, /* SpillSize */
    6793             :     32, /* SpillAlignment */
    6794             :     VTLists + 6,
    6795             :     DQuad_with_dsub_2_in_DPR_8SubClassMask,
    6796             :     SuperRegIdxSeqs + 81,
    6797             :     LaneBitmask(0x000003FC),
    6798             :     0,
    6799             :     true, /* HasDisjunctSubRegs */
    6800             :     true, /* CoveredBySubRegs */
    6801             :     DQuad_with_dsub_2_in_DPR_8Superclasses,
    6802             :     nullptr
    6803             :   };
    6804             : 
    6805             :   extern const TargetRegisterClass DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
    6806             :     &ARMMCRegisterClasses[DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
    6807             :     32, /* SpillSize */
    6808             :     32, /* SpillAlignment */
    6809             :     VTLists + 6,
    6810             :     DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
    6811             :     SuperRegIdxSeqs + 42,
    6812             :     LaneBitmask(0x000003FC),
    6813             :     0,
    6814             :     true, /* HasDisjunctSubRegs */
    6815             :     true, /* CoveredBySubRegs */
    6816             :     DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
    6817             :     nullptr
    6818             :   };
    6819             : 
    6820             :   extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8RegClass = {
    6821             :     &ARMMCRegisterClasses[DQuad_with_dsub_3_in_DPR_8RegClassID],
    6822             :     32, /* SpillSize */
    6823             :     32, /* SpillAlignment */
    6824             :     VTLists + 6,
    6825             :     DQuad_with_dsub_3_in_DPR_8SubClassMask,
    6826             :     SuperRegIdxSeqs + 81,
    6827             :     LaneBitmask(0x000003FC),
    6828             :     0,
    6829             :     true, /* HasDisjunctSubRegs */
    6830             :     true, /* CoveredBySubRegs */
    6831             :     DQuad_with_dsub_3_in_DPR_8Superclasses,
    6832             :     nullptr
    6833             :   };
    6834             : 
    6835             :   extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
    6836             :     &ARMMCRegisterClasses[DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
    6837             :     32, /* SpillSize */
    6838             :     32, /* SpillAlignment */
    6839             :     VTLists + 6,
    6840             :     DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
    6841             :     SuperRegIdxSeqs + 42,
    6842             :     LaneBitmask(0x000003FC),
    6843             :     0,
    6844             :     true, /* HasDisjunctSubRegs */
    6845             :     true, /* CoveredBySubRegs */
    6846             :     DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
    6847             :     nullptr
    6848             :   };
    6849             : 
    6850             :   extern const TargetRegisterClass DQuad_with_qsub_0_in_QPR_8RegClass = {
    6851             :     &ARMMCRegisterClasses[DQuad_with_qsub_0_in_QPR_8RegClassID],
    6852             :     32, /* SpillSize */
    6853             :     32, /* SpillAlignment */
    6854             :     VTLists + 6,
    6855             :     DQuad_with_qsub_0_in_QPR_8SubClassMask,
    6856             :     SuperRegIdxSeqs + 77,
    6857             :     LaneBitmask(0x000003FC),
    6858             :     0,
    6859             :     true, /* HasDisjunctSubRegs */
    6860             :     true, /* CoveredBySubRegs */
    6861             :     DQuad_with_qsub_0_in_QPR_8Superclasses,
    6862             :     DQuad_with_qsub_0_in_QPR_8GetRawAllocationOrder
    6863             :   };
    6864             : 
    6865             :   extern const TargetRegisterClass DQuad_with_qsub_1_in_QPR_8RegClass = {
    6866             :     &ARMMCRegisterClasses[DQuad_with_qsub_1_in_QPR_8RegClassID],
    6867             :     32, /* SpillSize */
    6868             :     32, /* SpillAlignment */
    6869             :     VTLists + 6,
    6870             :     DQuad_with_qsub_1_in_QPR_8SubClassMask,
    6871             :     SuperRegIdxSeqs + 77,
    6872             :     LaneBitmask(0x000003FC),
    6873             :     0,
    6874             :     true, /* HasDisjunctSubRegs */
    6875             :     true, /* CoveredBySubRegs */
    6876             :     DQuad_with_qsub_1_in_QPR_8Superclasses,
    6877             :     DQuad_with_qsub_1_in_QPR_8GetRawAllocationOrder
    6878             :   };
    6879             : 
    6880             :   extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass = {
    6881             :     &ARMMCRegisterClasses[DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID],
    6882             :     32, /* SpillSize */
    6883             :     32, /* SpillAlignment */
    6884             :     VTLists + 6,
    6885             :     DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8SubClassMask,
    6886             :     SuperRegIdxSeqs + 42,
    6887             :     LaneBitmask(0x000003FC),
    6888             :     0,
    6889             :     true, /* HasDisjunctSubRegs */
    6890             :     true, /* CoveredBySubRegs */
    6891             :     DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Superclasses,
    6892             :     nullptr
    6893             :   };
    6894             : 
    6895             :   extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
    6896             :     &ARMMCRegisterClasses[DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
    6897             :     32, /* SpillSize */
    6898             :     32, /* SpillAlignment */
    6899             :     VTLists + 6,
    6900             :     DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
    6901             :     SuperRegIdxSeqs + 42,
    6902             :     LaneBitmask(0x000003FC),
    6903             :     0,
    6904             :     true, /* HasDisjunctSubRegs */
    6905             :     true, /* CoveredBySubRegs */
    6906             :     DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
    6907             :     nullptr
    6908             :   };
    6909             : 
    6910             :   extern const TargetRegisterClass QQQQPRRegClass = {
    6911             :     &ARMMCRegisterClasses[QQQQPRRegClassID],
    6912             :     64, /* SpillSize */
    6913             :     32, /* SpillAlignment */
    6914             :     VTLists + 8,
    6915             :     QQQQPRSubClassMask,
    6916             :     SuperRegIdxSeqs + 8,
    6917             :     LaneBitmask(0x0003FFFC),
    6918             :     0,
    6919             :     true, /* HasDisjunctSubRegs */
    6920             :     true, /* CoveredBySubRegs */
    6921             :     NullRegClasses,
    6922             :     QQQQPRGetRawAllocationOrder
    6923             :   };
    6924             : 
    6925             :   extern const TargetRegisterClass QQQQPR_with_ssub_0RegClass = {
    6926             :     &ARMMCRegisterClasses[QQQQPR_with_ssub_0RegClassID],
    6927             :     64, /* SpillSize */
    6928             :     32, /* SpillAlignment */
    6929             :     VTLists + 8,
    6930             :     QQQQPR_with_ssub_0SubClassMask,
    6931             :     SuperRegIdxSeqs + 8,
    6932             :     LaneBitmask(0x0003FFFC),
    6933             :     0,
    6934             :     true, /* HasDisjunctSubRegs */
    6935             :     true, /* CoveredBySubRegs */
    6936             :     QQQQPR_with_ssub_0Superclasses,
    6937             :     QQQQPR_with_ssub_0GetRawAllocationOrder
    6938             :   };
    6939             : 
    6940             :   extern const TargetRegisterClass QQQQPR_with_ssub_4RegClass = {
    6941             :     &ARMMCRegisterClasses[QQQQPR_with_ssub_4RegClassID],
    6942             :     64, /* SpillSize */
    6943             :     32, /* SpillAlignment */
    6944             :     VTLists + 8,
    6945             :     QQQQPR_with_ssub_4SubClassMask,
    6946             :     SuperRegIdxSeqs + 8,
    6947             :     LaneBitmask(0x0003FFFC),
    6948             :     0,
    6949             :     true, /* HasDisjunctSubRegs */
    6950             :     true, /* CoveredBySubRegs */
    6951             :     QQQQPR_with_ssub_4Superclasses,
    6952             :     QQQQPR_with_ssub_4GetRawAllocationOrder
    6953             :   };
    6954             : 
    6955             :   extern const TargetRegisterClass QQQQPR_with_ssub_8RegClass = {
    6956             :     &ARMMCRegisterClasses[QQQQPR_with_ssub_8RegClassID],
    6957             :     64, /* SpillSize */
    6958             :     32, /* SpillAlignment */
    6959             :     VTLists + 8,
    6960             :     QQQQPR_with_ssub_8SubClassMask,
    6961             :     SuperRegIdxSeqs + 8,
    6962             :     LaneBitmask(0x0003FFFC),
    6963             :     0,
    6964             :     true, /* HasDisjunctSubRegs */
    6965             :     true, /* CoveredBySubRegs */
    6966             :     QQQQPR_with_ssub_8Superclasses,
    6967             :     QQQQPR_with_ssub_8GetRawAllocationOrder
    6968             :   };
    6969             : 
    6970             :   extern const TargetRegisterClass QQQQPR_with_ssub_12RegClass = {
    6971             :     &ARMMCRegisterClasses[QQQQPR_with_ssub_12RegClassID],
    6972             :     64, /* SpillSize */
    6973             :     32, /* SpillAlignment */
    6974             :     VTLists + 8,
    6975             :     QQQQPR_with_ssub_12SubClassMask,
    6976             :     SuperRegIdxSeqs + 8,
    6977             :     LaneBitmask(0x0003FFFC),
    6978             :     0,
    6979             :     true, /* HasDisjunctSubRegs */
    6980             :     true, /* CoveredBySubRegs */
    6981             :     QQQQPR_with_ssub_12Superclasses,
    6982             :     QQQQPR_with_ssub_12GetRawAllocationOrder
    6983             :   };
    6984             : 
    6985             :   extern const TargetRegisterClass QQQQPR_with_dsub_0_in_DPR_8RegClass = {
    6986             :     &ARMMCRegisterClasses[QQQQPR_with_dsub_0_in_DPR_8RegClassID],
    6987             :     64, /* SpillSize */
    6988             :     32, /* SpillAlignment */
    6989             :     VTLists + 8,
    6990             :     QQQQPR_with_dsub_0_in_DPR_8SubClassMask,
    6991             :     SuperRegIdxSeqs + 8,
    6992             :     LaneBitmask(0x0003FFFC),
    6993             :     0,
    6994             :     true, /* HasDisjunctSubRegs */
    6995             :     true, /* CoveredBySubRegs */
    6996             :     QQQQPR_with_dsub_0_in_DPR_8Superclasses,
    6997             :     QQQQPR_with_dsub_0_in_DPR_8GetRawAllocationOrder
    6998             :   };
    6999             : 
    7000             :   extern const TargetRegisterClass QQQQPR_with_dsub_2_in_DPR_8RegClass = {
    7001             :     &ARMMCRegisterClasses[QQQQPR_with_dsub_2_in_DPR_8RegClassID],
    7002             :     64, /* SpillSize */
    7003             :     32, /* SpillAlignment */
    7004             :     VTLists + 8,
    7005             :     QQQQPR_with_dsub_2_in_DPR_8SubClassMask,
    7006             :     SuperRegIdxSeqs + 8,
    7007             :     LaneBitmask(0x0003FFFC),
    7008             :     0,
    7009             :     true, /* HasDisjunctSubRegs */
    7010             :     true, /* CoveredBySubRegs */
    7011             :     QQQQPR_with_dsub_2_in_DPR_8Superclasses,
    7012             :     QQQQPR_with_dsub_2_in_DPR_8GetRawAllocationOrder
    7013             :   };
    7014             : 
    7015             :   extern const TargetRegisterClass QQQQPR_with_dsub_4_in_DPR_8RegClass = {
    7016             :     &ARMMCRegisterClasses[QQQQPR_with_dsub_4_in_DPR_8RegClassID],
    7017             :     64, /* SpillSize */
    7018             :     32, /* SpillAlignment */
    7019             :     VTLists + 8,
    7020             :     QQQQPR_with_dsub_4_in_DPR_8SubClassMask,
    7021             :     SuperRegIdxSeqs + 8,
    7022             :     LaneBitmask(0x0003FFFC),
    7023             :     0,
    7024             :     true, /* HasDisjunctSubRegs */
    7025             :     true, /* CoveredBySubRegs */
    7026             :     QQQQPR_with_dsub_4_in_DPR_8Superclasses,
    7027             :     QQQQPR_with_dsub_4_in_DPR_8GetRawAllocationOrder
    7028             :   };
    7029             : 
    7030             :   extern const TargetRegisterClass QQQQPR_with_dsub_6_in_DPR_8RegClass = {
    7031             :     &ARMMCRegisterClasses[QQQQPR_with_dsub_6_in_DPR_8RegClassID],
    7032             :     64, /* SpillSize */
    7033             :     32, /* SpillAlignment */
    7034             :     VTLists + 8,
    7035             :     QQQQPR_with_dsub_6_in_DPR_8SubClassMask,
    7036             :     SuperRegIdxSeqs + 8,
    7037             :     LaneBitmask(0x0003FFFC),
    7038             :     0,
    7039             :     true, /* HasDisjunctSubRegs */
    7040             :     true, /* CoveredBySubRegs */
    7041             :     QQQQPR_with_dsub_6_in_DPR_8Superclasses,
    7042             :     QQQQPR_with_dsub_6_in_DPR_8GetRawAllocationOrder
    7043             :   };
    7044             : 
    7045             : } // end namespace ARM
    7046             : 
    7047             : namespace {
    7048             :   const TargetRegisterClass* const RegisterClasses[] = {
    7049             :     &ARM::SPRRegClass,
    7050             :     &ARM::GPRRegClass,
    7051             :     &ARM::GPRwithAPSRRegClass,
    7052             :     &ARM::SPR_8RegClass,
    7053             :     &ARM::GPRnopcRegClass,
    7054             :     &ARM::rGPRRegClass,
    7055             :     &ARM::tGPRwithpcRegClass,
    7056             :     &ARM::hGPRRegClass,
    7057             :     &ARM::tGPRRegClass,
    7058             :     &ARM::GPRnopc_and_hGPRRegClass,
    7059             :     &ARM::hGPR_and_rGPRRegClass,
    7060             :     &ARM::tcGPRRegClass,
    7061             :     &ARM::tGPR_and_tcGPRRegClass,
    7062             :     &ARM::CCRRegClass,
    7063             :     &ARM::GPRspRegClass,
    7064             :     &ARM::hGPR_and_tGPRwithpcRegClass,
    7065             :     &ARM::hGPR_and_tcGPRRegClass,
    7066             :     &ARM::DPRRegClass,
    7067             :     &ARM::DPR_VFP2RegClass,
    7068             :     &ARM::DPR_8RegClass,
    7069             :     &ARM::GPRPairRegClass,
    7070             :     &ARM::GPRPair_with_gsub_1_in_rGPRRegClass,
    7071             :     &ARM::GPRPair_with_gsub_0_in_tGPRRegClass,
    7072             :     &ARM::GPRPair_with_gsub_0_in_hGPRRegClass,
    7073             :     &ARM::GPRPair_with_gsub_0_in_tcGPRRegClass,
    7074             :     &ARM::GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClass,
    7075             :     &ARM::GPRPair_with_gsub_1_in_tcGPRRegClass,
    7076             :     &ARM::GPRPair_with_gsub_1_in_GPRspRegClass,
    7077             :     &ARM::DPairSpcRegClass,
    7078             :     &ARM::DPairSpc_with_ssub_0RegClass,
    7079             :     &ARM::DPairSpc_with_ssub_4RegClass,
    7080             :     &ARM::DPairSpc_with_dsub_0_in_DPR_8RegClass,
    7081             :     &ARM::DPairSpc_with_dsub_2_in_DPR_8RegClass,
    7082             :     &ARM::DPairRegClass,
    7083             :     &ARM::DPair_with_ssub_0RegClass,
    7084             :     &ARM::QPRRegClass,
    7085             :     &ARM::DPair_with_ssub_2RegClass,
    7086             :     &ARM::DPair_with_dsub_0_in_DPR_8RegClass,
    7087             :     &ARM::QPR_VFP2RegClass,
    7088             :     &ARM::DPair_with_dsub_1_in_DPR_8RegClass,
    7089             :     &ARM::QPR_8RegClass,
    7090             :     &ARM::DTripleRegClass,
    7091             :     &ARM::DTripleSpcRegClass,
    7092             :     &ARM::DTripleSpc_with_ssub_0RegClass,
    7093             :     &ARM::DTriple_with_ssub_0RegClass,
    7094             :     &ARM::DTriple_with_qsub_0_in_QPRRegClass,
    7095             :     &ARM::DTriple_with_ssub_2RegClass,
    7096             :     &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    7097             :     &ARM::DTripleSpc_with_ssub_4RegClass,
    7098             :     &ARM::DTriple_with_ssub_4RegClass,
    7099             :     &ARM::DTripleSpc_with_ssub_8RegClass,
    7100             :     &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
    7101             :     &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
    7102             :     &ARM::DTriple_with_qsub_0_in_QPR_VFP2RegClass,
    7103             :     &ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    7104             :     &ARM::DTriple_with_dsub_1_in_DPR_8RegClass,
    7105             :     &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
    7106             :     &ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClass,
    7107             :     &ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClass,
    7108             :     &ARM::DTriple_with_dsub_2_in_DPR_8RegClass,
    7109             :     &ARM::DTripleSpc_with_dsub_4_in_DPR_8RegClass,
    7110             :     &ARM::DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    7111             :     &ARM::DTriple_with_qsub_0_in_QPR_8RegClass,
    7112             :     &ARM::DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClass,
    7113             :     &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass,
    7114             :     &ARM::DQuadSpcRegClass,
    7115             :     &ARM::DQuadSpc_with_ssub_0RegClass,
    7116             :     &ARM::DQuadSpc_with_ssub_4RegClass,
    7117             :     &ARM::DQuadSpc_with_ssub_8RegClass,
    7118             :     &ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClass,
    7119             :     &ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClass,
    7120             :     &ARM::DQuadSpc_with_dsub_4_in_DPR_8RegClass,
    7121             :     &ARM::DQuadRegClass,
    7122             :     &ARM::DQuad_with_ssub_0RegClass,
    7123             :     &ARM::DQuad_with_ssub_2RegClass,
    7124             :     &ARM::QQPRRegClass,
    7125             :     &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    7126             :     &ARM::DQuad_with_ssub_4RegClass,
    7127             :     &ARM::DQuad_with_ssub_6RegClass,
    7128             :     &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
    7129             :     &ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClass,
    7130             :     &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    7131             :     &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
    7132             :     &ARM::DQuad_with_qsub_1_in_QPR_VFP2RegClass,
    7133             :     &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
    7134             :     &ARM::DQuad_with_dsub_2_in_DPR_8RegClass,
    7135             :     &ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    7136             :     &ARM::DQuad_with_dsub_3_in_DPR_8RegClass,
    7137             :     &ARM::DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    7138             :     &ARM::DQuad_with_qsub_0_in_QPR_8RegClass,
    7139             :     &ARM::DQuad_with_qsub_1_in_QPR_8RegClass,
    7140             :     &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass,
    7141             :     &ARM::DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    7142             :     &ARM::QQQQPRRegClass,
    7143             :     &ARM::QQQQPR_with_ssub_0RegClass,
    7144             :     &ARM::QQQQPR_with_ssub_4RegClass,
    7145             :     &ARM::QQQQPR_with_ssub_8RegClass,
    7146             :     &ARM::QQQQPR_with_ssub_12RegClass,
    7147             :     &ARM::QQQQPR_with_dsub_0_in_DPR_8RegClass,
    7148             :     &ARM::QQQQPR_with_dsub_2_in_DPR_8RegClass,
    7149             :     &ARM::QQQQPR_with_dsub_4_in_DPR_8RegClass,
    7150             :     &ARM::QQQQPR_with_dsub_6_in_DPR_8RegClass,
    7151             :   };
    7152             : } // end anonymous namespace
    7153             : 
    7154             : static const TargetRegisterInfoDesc ARMRegInfoDesc[] = { // Extra Descriptors
    7155             :   { 0, false },
    7156             :   { 0, false },
    7157             :   { 0, true },
    7158             :   { 0, false },
    7159             :   { 0, false },
    7160             :   { 0, false },
    7161             :   { 0, false },
    7162             :   { 0, false },
    7163             :   { 0, false },
    7164             :   { 0, false },
    7165             :   { 1, true },
    7166             :   { 1, true },
    7167             :   { 1, true },
    7168             :   { 0, false },
    7169             :   { 0, true },
    7170             :   { 0, true },
    7171             :   { 0, true },
    7172             :   { 0, true },
    7173             :   { 0, true },
    7174             :   { 0, true },
    7175             :   { 0, true },
    7176             :   { 0, true },
    7177             :   { 0, true },
    7178             :   { 0, true },
    7179             :   { 0, true },
    7180             :   { 0, true },
    7181             :   { 0, true },
    7182             :   { 0, true },
    7183             :   { 0, true },
    7184             :   { 0, true },
    7185             :   { 0, true },
    7186             :   { 0, true },
    7187             :   { 0, true },
    7188             :   { 0, true },
    7189             :   { 0, true },
    7190             :   { 0, true },
    7191             :   { 0, true },
    7192             :   { 0, true },
    7193             :   { 0, true },
    7194             :   { 0, true },
    7195             :   { 0, true },
    7196             :   { 0, true },
    7197             :   { 0, true },
    7198             :   { 0, true },
    7199             :   { 0, true },
    7200             :   { 0, true },
    7201             :   { 0, false },
    7202             :   { 0, false },
    7203             :   { 0, false },
    7204             :   { 0, false },
    7205             :   { 0, true },
    7206             :   { 0, true },
    7207             :   { 0, true },
    7208             :   { 0, true },
    7209             :   { 0, true },
    7210             :   { 0, true },
    7211             :   { 0, true },
    7212             :   { 0, true },
    7213             :   { 0, true },
    7214             :   { 0, true },
    7215             :   { 0, true },
    7216             :   { 0, true },
    7217             :   { 0, true },
    7218             :   { 0, true },
    7219             :   { 0, true },
    7220             :   { 0, true },
    7221             :   { 0, true },
    7222             :   { 0, true },
    7223             :   { 0, true },
    7224             :   { 0, true },
    7225             :   { 0, true },
    7226             :   { 0, true },
    7227             :   { 0, true },
    7228             :   { 0, true },
    7229             :   { 1, true },
    7230             :   { 1, true },
    7231             :   { 1, true },
    7232             :   { 1, true },
    7233             :   { 1, true },
    7234             :   { 0, true },
    7235             :   { 0, true },
    7236             :   { 0, true },
    7237             :   { 0, true },
    7238             :   { 0, true },
    7239             :   { 0, true },
    7240             :   { 0, true },
    7241             :   { 0, true },
    7242             :   { 0, true },
    7243             :   { 0, true },
    7244             :   { 0, true },
    7245             :   { 0, true },
    7246             :   { 0, true },
    7247             :   { 0, true },
    7248             :   { 0, true },
    7249             :   { 0, true },
    7250             :   { 0, true },
    7251             :   { 0, true },
    7252             :   { 0, true },
    7253             :   { 0, true },
    7254             :   { 0, true },
    7255             :   { 0, true },
    7256             :   { 0, true },
    7257             :   { 0, true },
    7258             :   { 0, true },
    7259             :   { 0, true },
    7260             :   { 0, true },
    7261             :   { 0, true },
    7262             :   { 0, true },
    7263             :   { 0, true },
    7264             :   { 0, true },
    7265             :   { 0, true },
    7266             :   { 0, true },
    7267             :   { 0, true },
    7268             :   { 0, true },
    7269             :   { 0, true },
    7270             :   { 0, true },
    7271             :   { 0, true },
    7272             :   { 0, true },
    7273             :   { 0, true },
    7274             :   { 0, true },
    7275             :   { 0, true },
    7276             :   { 0, true },
    7277             :   { 0, true },
    7278             :   { 0, true },
    7279             :   { 0, true },
    7280             :   { 0, true },
    7281             :   { 0, true },
    7282             :   { 0, true },
    7283             :   { 0, true },
    7284             :   { 0, true },
    7285             :   { 0, true },
    7286             :   { 0, true },
    7287             :   { 0, true },
    7288             :   { 0, true },
    7289             :   { 0, true },
    7290             :   { 0, true },
    7291             :   { 0, true },
    7292             :   { 0, true },
    7293             :   { 0, true },
    7294             :   { 0, true },
    7295             :   { 0, true },
    7296             :   { 0, true },
    7297             :   { 0, true },
    7298             :   { 0, true },
    7299             :   { 0, true },
    7300             :   { 0, true },
    7301             :   { 0, true },
    7302             :   { 0, true },
    7303             :   { 0, true },
    7304             :   { 0, true },
    7305             :   { 0, true },
    7306             :   { 0, true },
    7307             :   { 0, true },
    7308             :   { 0, true },
    7309             :   { 0, true },
    7310             :   { 0, true },
    7311             :   { 0, true },
    7312             :   { 0, true },
    7313             :   { 0, true },
    7314             :   { 0, true },
    7315             :   { 0, true },
    7316             :   { 0, true },
    7317             :   { 0, true },
    7318             :   { 0, true },
    7319             :   { 0, true },
    7320             :   { 0, true },
    7321             :   { 0, true },
    7322             :   { 0, true },
    7323             :   { 0, true },
    7324             :   { 1, true },
    7325             :   { 0, true },
    7326             :   { 0, true },
    7327             :   { 0, true },
    7328             :   { 0, true },
    7329             :   { 1, true },
    7330             :   { 1, true },
    7331             :   { 0, true },
    7332             :   { 0, true },
    7333             :   { 0, true },
    7334             :   { 0, true },
    7335             :   { 0, true },
    7336             :   { 0, true },
    7337             :   { 0, true },
    7338             :   { 0, true },
    7339             :   { 0, true },
    7340             :   { 0, true },
    7341             :   { 0, true },
    7342             :   { 0, true },
    7343             :   { 0, true },
    7344             :   { 0, true },
    7345             :   { 0, true },
    7346             :   { 0, true },
    7347             :   { 0, true },
    7348             :   { 0, true },
    7349             :   { 0, true },
    7350             :   { 0, true },
    7351             :   { 0, true },
    7352             :   { 0, true },
    7353             :   { 0, true },
    7354             :   { 0, true },
    7355             :   { 0, true },
    7356             :   { 0, true },
    7357             :   { 0, true },
    7358             :   { 0, true },
    7359             :   { 0, true },
    7360             :   { 0, true },
    7361             :   { 0, true },
    7362             :   { 0, true },
    7363             :   { 0, true },
    7364             :   { 0, true },
    7365             :   { 0, true },
    7366             :   { 0, true },
    7367             :   { 0, true },
    7368             :   { 0, true },
    7369             :   { 0, true },
    7370             :   { 0, true },
    7371             :   { 0, true },
    7372             :   { 0, true },
    7373             :   { 0, true },
    7374             :   { 0, true },
    7375             :   { 0, true },
    7376             :   { 0, true },
    7377             :   { 0, true },
    7378             :   { 0, true },
    7379             :   { 0, true },
    7380             :   { 0, true },
    7381             :   { 0, true },
    7382             :   { 0, true },
    7383             :   { 0, true },
    7384             :   { 0, true },
    7385             :   { 0, true },
    7386             :   { 0, true },
    7387             :   { 0, true },
    7388             :   { 0, true },
    7389             :   { 0, false },
    7390             :   { 0, false },
    7391             :   { 0, false },
    7392             :   { 0, false },
    7393             :   { 0, false },
    7394             :   { 0, false },
    7395             :   { 0, false },
    7396             :   { 0, false },
    7397             :   { 0, false },
    7398             :   { 0, false },
    7399             :   { 0, false },
    7400             :   { 0, false },
    7401             :   { 0, false },
    7402             :   { 0, false },
    7403             :   { 0, false },
    7404             :   { 0, false },
    7405             :   { 0, false },
    7406             :   { 0, false },
    7407             :   { 0, false },
    7408             :   { 0, false },
    7409             :   { 0, false },
    7410             :   { 0, false },
    7411             :   { 0, false },
    7412             :   { 0, false },
    7413             :   { 0, false },
    7414             :   { 0, false },
    7415             :   { 0, true },
    7416             :   { 0, true },
    7417             :   { 0, true },
    7418             :   { 0, true },
    7419             :   { 0, true },
    7420             :   { 0, true },
    7421             :   { 0, true },
    7422             :   { 0, true },
    7423             :   { 0, true },
    7424             :   { 0, true },
    7425             :   { 0, true },
    7426             :   { 0, true },
    7427             :   { 0, true },
    7428             :   { 0, true },
    7429             :   { 0, true },
    7430             :   { 0, true },
    7431             :   { 0, true },
    7432             :   { 0, true },
    7433             :   { 0, true },
    7434             :   { 0, true },
    7435             :   { 0, true },
    7436             :   { 0, true },
    7437             :   { 0, true },
    7438             :   { 0, true },
    7439             :   { 0, true },
    7440             :   { 0, true },
    7441             :   { 0, true },
    7442             :   { 0, true },
    7443             :   { 0, true },
    7444             : };
    7445        2305 : unsigned ARMGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
    7446             :   static const uint8_t RowMap[56] = {
    7447             :     0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 4, 0, 2, 4, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 5, 5, 5, 2, 
    7448             :   };
    7449             :   static const uint8_t Rows[8][56] = {
    7450             :     { 1, 2, 3, 4, 5, 0, 7, 0, 0, 0, 0, 0, 13, 14, 0, 0, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 0, 0, 29, 30, 0, 0, 33, 34, 35, 36, 37, 38, 0, 0, 0, 0, 43, 0, 45, 0, 0, 0, 0, 0, 51, 0, 0, 0, 0, 0, },
    7451             :     { 2, 3, 4, 5, 6, 0, 8, 0, 0, 0, 0, 0, 37, 49, 0, 0, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 0, 0, 31, 32, 0, 0, 35, 36, 43, 44, 14, 40, 0, 0, 0, 0, 46, 0, 48, 0, 0, 0, 0, 0, 53, 0, 0, 0, 0, 0, },
    7452             :     { 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 14, 15, 0, 0, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 0, 0, 0, 0, 0, 0, 43, 44, 46, 47, 49, 0, 0, 0, 0, 0, 51, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    7453             :     { 4, 5, 6, 7, 8, 0, 0, 0, 0, 0, 0, 0, 49, 55, 0, 0, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 0, 0, 0, 0, 0, 0, 46, 47, 51, 52, 15, 0, 0, 0, 0, 0, 53, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    7454             :     { 5, 6, 7, 8, 0, 0, 0, 0, 0, 0, 0, 0, 15, 16, 0, 0, 25, 26, 27, 28, 29, 30, 31, 32, 0, 0, 0, 0, 0, 0, 0, 0, 51, 52, 53, 54, 55, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    7455             :     { 6, 7, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 55, 0, 0, 0, 27, 28, 29, 30, 31, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 53, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    7456             :     { 7, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 29, 30, 31, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    7457             :     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    7458             :   };
    7459             : 
    7460        2305 :   --IdxA; assert(IdxA < 56);
    7461        2305 :   --IdxB; assert(IdxB < 56);
    7462        2305 :   return Rows[RowMap[IdxA]][IdxB];
    7463             : }
    7464             : 
    7465             :   struct MaskRolOp {
    7466             :     LaneBitmask Mask;
    7467             :     uint8_t  RotateLeft;
    7468             :   };
    7469             :   static const MaskRolOp LaneMaskComposeSequences[] = {
    7470             :     { LaneBitmask(0xFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 },   // Sequence 0
    7471             :     { LaneBitmask(0xFFFFFFFF),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 2
    7472             :     { LaneBitmask(0xFFFFFFFF),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 4
    7473             :     { LaneBitmask(0xFFFFFFFF),  6 }, { LaneBitmask::getNone(), 0 },   // Sequence 6
    7474             :     { LaneBitmask(0xFFFFFFFF),  8 }, { LaneBitmask::getNone(), 0 },   // Sequence 8
    7475             :     { LaneBitmask(0xFFFFFFFF), 10 }, { LaneBitmask::getNone(), 0 },   // Sequence 10
    7476             :     { LaneBitmask(0xFFFFFFFF), 12 }, { LaneBitmask::getNone(), 0 },   // Sequence 12
    7477             :     { LaneBitmask(0xFFFFFFFF), 14 }, { LaneBitmask::getNone(), 0 },   // Sequence 14
    7478             :     { LaneBitmask(0xFFFFFFFF),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 16
    7479             :     { LaneBitmask(0xFFFFFFFF),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 18
    7480             :     { LaneBitmask(0xFFFFFFFF),  5 }, { LaneBitmask::getNone(), 0 },   // Sequence 20
    7481             :     { LaneBitmask(0xFFFFFFFF),  7 }, { LaneBitmask::getNone(), 0 },   // Sequence 22
    7482             :     { LaneBitmask(0xFFFFFFFF),  9 }, { LaneBitmask::getNone(), 0 },   // Sequence 24
    7483             :     { LaneBitmask(0xFFFFFFFF), 11 }, { LaneBitmask::getNone(), 0 },   // Sequence 26
    7484             :     { LaneBitmask(0xFFFFFFFF), 13 }, { LaneBitmask::getNone(), 0 },   // Sequence 28
    7485             :     { LaneBitmask(0xFFFFFFFF), 15 }, { LaneBitmask::getNone(), 0 },   // Sequence 30
    7486             :     { LaneBitmask(0xFFFFFFFF), 16 }, { LaneBitmask::getNone(), 0 },   // Sequence 32
    7487             :     { LaneBitmask(0xFFFFFFFF), 17 }, { LaneBitmask::getNone(), 0 }  // Sequence 34
    7488     1301508 :   };
    7489             :   static const MaskRolOp *const CompositeSequences[] = {
    7490             :     &LaneMaskComposeSequences[0], // to dsub_0
    7491             :     &LaneMaskComposeSequences[2], // to dsub_1
    7492             :     &LaneMaskComposeSequences[4], // to dsub_2
    7493             :     &LaneMaskComposeSequences[6], // to dsub_3
    7494             :     &LaneMaskComposeSequences[8], // to dsub_4
    7495             :     &LaneMaskComposeSequences[10], // to dsub_5
    7496             :     &LaneMaskComposeSequences[12], // to dsub_6
    7497             :     &LaneMaskComposeSequences[14], // to dsub_7
    7498             :     &LaneMaskComposeSequences[0], // to gsub_0
    7499             :     &LaneMaskComposeSequences[16], // to gsub_1
    7500             :     &LaneMaskComposeSequences[0], // to qqsub_0
    7501             :     &LaneMaskComposeSequences[8], // to qqsub_1
    7502             :     &LaneMaskComposeSequences[0], // to qsub_0
    7503             :     &LaneMaskComposeSequences[4], // to qsub_1
    7504             :     &LaneMaskComposeSequences[8], // to qsub_2
    7505             :     &LaneMaskComposeSequences[12], // to qsub_3
    7506             :     &LaneMaskComposeSequences[2], // to ssub_0
    7507             :     &LaneMaskComposeSequences[18], // to ssub_1
    7508             :     &LaneMaskComposeSequences[4], // to ssub_2
    7509             :     &LaneMaskComposeSequences[20], // to ssub_3
    7510             :     &LaneMaskComposeSequences[6], // to ssub_4
    7511             :     &LaneMaskComposeSequences[22], // to ssub_5
    7512             :     &LaneMaskComposeSequences[8], // to ssub_6
    7513             :     &LaneMaskComposeSequences[24], // to ssub_7
    7514             :     &LaneMaskComposeSequences[10], // to ssub_8
    7515             :     &LaneMaskComposeSequences[26], // to ssub_9
    7516             :     &LaneMaskComposeSequences[12], // to ssub_10
    7517             :     &LaneMaskComposeSequences[28], // to ssub_11
    7518             :     &LaneMaskComposeSequences[14], // to ssub_12
    7519             :     &LaneMaskComposeSequences[30], // to ssub_13
    7520             :     &LaneMaskComposeSequences[32], // to dsub_7_then_ssub_0
    7521             :     &LaneMaskComposeSequences[34], // to dsub_7_then_ssub_1
    7522             :     &LaneMaskComposeSequences[0], // to ssub_0_ssub_1_ssub_4_ssub_5
    7523             :     &LaneMaskComposeSequences[0], // to ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    7524             :     &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_6_ssub_7
    7525             :     &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    7526             :     &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_4_ssub_5
    7527             :     &LaneMaskComposeSequences[0], // to ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    7528             :     &LaneMaskComposeSequences[0], // to ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    7529             :     &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    7530             :     &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    7531             :     &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    7532             :     &LaneMaskComposeSequences[4], // to ssub_4_ssub_5_ssub_8_ssub_9
    7533             :     &LaneMaskComposeSequences[4], // to ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    7534             :     &LaneMaskComposeSequences[4], // to ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    7535             :     &LaneMaskComposeSequences[6], // to ssub_6_ssub_7_dsub_5
    7536             :     &LaneMaskComposeSequences[6], // to ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    7537             :     &LaneMaskComposeSequences[6], // to ssub_6_ssub_7_dsub_5_dsub_7
    7538             :     &LaneMaskComposeSequences[6], // to ssub_6_ssub_7_ssub_8_ssub_9
    7539             :     &LaneMaskComposeSequences[6], // to ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    7540             :     &LaneMaskComposeSequences[8], // to ssub_8_ssub_9_ssub_12_ssub_13
    7541             :     &LaneMaskComposeSequences[8], // to ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    7542             :     &LaneMaskComposeSequences[10], // to dsub_5_dsub_7
    7543             :     &LaneMaskComposeSequences[10], // to dsub_5_ssub_12_ssub_13_dsub_7
    7544             :     &LaneMaskComposeSequences[10], // to dsub_5_ssub_12_ssub_13
    7545             :     &LaneMaskComposeSequences[4] // to ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    7546             :   };
    7547             : 
    7548           0 : LaneBitmask ARMGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
    7549           0 :   --IdxA; assert(IdxA < 56 && "Subregister index out of bounds");
    7550           0 :   LaneBitmask Result;
    7551           0 :   for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
    7552           0 :     LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
    7553           0 :     if (unsigned S = Ops->RotateLeft)
    7554           0 :       Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
    7555             :     else
    7556           0 :       Result |= LaneBitmask(M);
    7557             :   }
    7558           0 :   return Result;
    7559             : }
    7560             : 
    7561           0 : LaneBitmask ARMGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
    7562           0 :   LaneMask &= getSubRegIndexLaneMask(IdxA);
    7563           0 :   --IdxA; assert(IdxA < 56 && "Subregister index out of bounds");
    7564           0 :   LaneBitmask Result;
    7565           0 :   for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
    7566           0 :     LaneBitmask::Type M = LaneMask.getAsInteger();
    7567           0 :     if (unsigned S = Ops->RotateLeft)
    7568           0 :       Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
    7569             :     else
    7570           0 :       Result |= LaneBitmask(M);
    7571             :   }
    7572           0 :   return Result;
    7573             : }
    7574             : 
    7575       10868 : const TargetRegisterClass *ARMGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
    7576             :   static const uint8_t Table[102][56] = {
    7577             :     {   // SPR
    7578             :       0,        // dsub_0
    7579             :       0,        // dsub_1
    7580             :       0,        // dsub_2
    7581             :       0,        // dsub_3
    7582             :       0,        // dsub_4
    7583             :       0,        // dsub_5
    7584             :       0,        // dsub_6
    7585             :       0,        // dsub_7
    7586             :       0,        // gsub_0
    7587             :       0,        // gsub_1
    7588             :       0,        // qqsub_0
    7589             :       0,        // qqsub_1
    7590             :       0,        // qsub_0
    7591             :       0,        // qsub_1
    7592             :       0,        // qsub_2
    7593             :       0,        // qsub_3
    7594             :       0,        // ssub_0
    7595             :       0,        // ssub_1
    7596             :       0,        // ssub_2
    7597             :       0,        // ssub_3
    7598             :       0,        // ssub_4
    7599             :       0,        // ssub_5
    7600             :       0,        // ssub_6
    7601             :       0,        // ssub_7
    7602             :       0,        // ssub_8
    7603             :       0,        // ssub_9
    7604             :       0,        // ssub_10
    7605             :       0,        // ssub_11
    7606             :       0,        // ssub_12
    7607             :       0,        // ssub_13
    7608             :       0,        // dsub_7_then_ssub_0
    7609             :       0,        // dsub_7_then_ssub_1
    7610             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    7611             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    7612             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    7613             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    7614             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    7615             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    7616             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    7617             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    7618             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    7619             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    7620             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    7621             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    7622             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    7623             :       0,        // ssub_6_ssub_7_dsub_5
    7624             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    7625             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    7626             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    7627             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    7628             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    7629             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    7630             :       0,        // dsub_5_dsub_7
    7631             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    7632             :       0,        // dsub_5_ssub_12_ssub_13
    7633             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    7634             :     },
    7635             :     {   // GPR
    7636             :       0,        // dsub_0
    7637             :       0,        // dsub_1
    7638             :       0,        // dsub_2
    7639             :       0,        // dsub_3
    7640             :       0,        // dsub_4
    7641             :       0,        // dsub_5
    7642             :       0,        // dsub_6
    7643             :       0,        // dsub_7
    7644             :       0,        // gsub_0
    7645             :       0,        // gsub_1
    7646             :       0,        // qqsub_0
    7647             :       0,        // qqsub_1
    7648             :       0,        // qsub_0
    7649             :       0,        // qsub_1
    7650             :       0,        // qsub_2
    7651             :       0,        // qsub_3
    7652             :       0,        // ssub_0
    7653             :       0,        // ssub_1
    7654             :       0,        // ssub_2
    7655             :       0,        // ssub_3
    7656             :       0,        // ssub_4
    7657             :       0,        // ssub_5
    7658             :       0,        // ssub_6
    7659             :       0,        // ssub_7
    7660             :       0,        // ssub_8
    7661             :       0,        // ssub_9
    7662             :       0,        // ssub_10
    7663             :       0,        // ssub_11
    7664             :       0,        // ssub_12
    7665             :       0,        // ssub_13
    7666             :       0,        // dsub_7_then_ssub_0
    7667             :       0,        // dsub_7_then_ssub_1
    7668             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    7669             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    7670             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    7671             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    7672             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    7673             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    7674             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    7675             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    7676             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    7677             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    7678             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    7679             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    7680             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    7681             :       0,        // ssub_6_ssub_7_dsub_5
    7682             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    7683             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    7684             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    7685             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    7686             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    7687             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    7688             :       0,        // dsub_5_dsub_7
    7689             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    7690             :       0,        // dsub_5_ssub_12_ssub_13
    7691             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    7692             :     },
    7693             :     {   // GPRwithAPSR
    7694             :       0,        // dsub_0
    7695             :       0,        // dsub_1
    7696             :       0,        // dsub_2
    7697             :       0,        // dsub_3
    7698             :       0,        // dsub_4
    7699             :       0,        // dsub_5
    7700             :       0,        // dsub_6
    7701             :       0,        // dsub_7
    7702             :       0,        // gsub_0
    7703             :       0,        // gsub_1
    7704             :       0,        // qqsub_0
    7705             :       0,        // qqsub_1
    7706             :       0,        // qsub_0
    7707             :       0,        // qsub_1
    7708             :       0,        // qsub_2
    7709             :       0,        // qsub_3
    7710             :       0,        // ssub_0
    7711             :       0,        // ssub_1
    7712             :       0,        // ssub_2
    7713             :       0,        // ssub_3
    7714             :       0,        // ssub_4
    7715             :       0,        // ssub_5
    7716             :       0,        // ssub_6
    7717             :       0,        // ssub_7
    7718             :       0,        // ssub_8
    7719             :       0,        // ssub_9
    7720             :       0,        // ssub_10
    7721             :       0,        // ssub_11
    7722             :       0,        // ssub_12
    7723             :       0,        // ssub_13
    7724             :       0,        // dsub_7_then_ssub_0
    7725             :       0,        // dsub_7_then_ssub_1
    7726             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    7727             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    7728             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    7729             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    7730             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    7731             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    7732             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    7733             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    7734             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    7735             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    7736             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    7737             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    7738             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    7739             :       0,        // ssub_6_ssub_7_dsub_5
    7740             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    7741             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    7742             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    7743             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    7744             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    7745             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    7746             :       0,        // dsub_5_dsub_7
    7747             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    7748             :       0,        // dsub_5_ssub_12_ssub_13
    7749             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    7750             :     },
    7751             :     {   // SPR_8
    7752             :       0,        // dsub_0
    7753             :       0,        // dsub_1
    7754             :       0,        // dsub_2
    7755             :       0,        // dsub_3
    7756             :       0,        // dsub_4
    7757             :       0,        // dsub_5
    7758             :       0,        // dsub_6
    7759             :       0,        // dsub_7
    7760             :       0,        // gsub_0
    7761             :       0,        // gsub_1
    7762             :       0,        // qqsub_0
    7763             :       0,        // qqsub_1
    7764             :       0,        // qsub_0
    7765             :       0,        // qsub_1
    7766             :       0,        // qsub_2
    7767             :       0,        // qsub_3
    7768             :       0,        // ssub_0
    7769             :       0,        // ssub_1
    7770             :       0,        // ssub_2
    7771             :       0,        // ssub_3
    7772             :       0,        // ssub_4
    7773             :       0,        // ssub_5
    7774             :       0,        // ssub_6
    7775             :       0,        // ssub_7
    7776             :       0,        // ssub_8
    7777             :       0,        // ssub_9
    7778             :       0,        // ssub_10
    7779             :       0,        // ssub_11
    7780             :       0,        // ssub_12
    7781             :       0,        // ssub_13
    7782             :       0,        // dsub_7_then_ssub_0
    7783             :       0,        // dsub_7_then_ssub_1
    7784             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    7785             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    7786             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    7787             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    7788             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    7789             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    7790             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    7791             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    7792             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    7793             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    7794             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    7795             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    7796             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    7797             :       0,        // ssub_6_ssub_7_dsub_5
    7798             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    7799             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    7800             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    7801             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    7802             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    7803             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    7804             :       0,        // dsub_5_dsub_7
    7805             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    7806             :       0,        // dsub_5_ssub_12_ssub_13
    7807             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    7808             :     },
    7809             :     {   // GPRnopc
    7810             :       0,        // dsub_0
    7811             :       0,        // dsub_1
    7812             :       0,        // dsub_2
    7813             :       0,        // dsub_3
    7814             :       0,        // dsub_4
    7815             :       0,        // dsub_5
    7816             :       0,        // dsub_6
    7817             :       0,        // dsub_7
    7818             :       0,        // gsub_0
    7819             :       0,        // gsub_1
    7820             :       0,        // qqsub_0
    7821             :       0,        // qqsub_1
    7822             :       0,        // qsub_0
    7823             :       0,        // qsub_1
    7824             :       0,        // qsub_2
    7825             :       0,        // qsub_3
    7826             :       0,        // ssub_0
    7827             :       0,        // ssub_1
    7828             :       0,        // ssub_2
    7829             :       0,        // ssub_3
    7830             :       0,        // ssub_4
    7831             :       0,        // ssub_5
    7832             :       0,        // ssub_6
    7833             :       0,        // ssub_7
    7834             :       0,        // ssub_8
    7835             :       0,        // ssub_9
    7836             :       0,        // ssub_10
    7837             :       0,        // ssub_11
    7838             :       0,        // ssub_12
    7839             :       0,        // ssub_13
    7840             :       0,        // dsub_7_then_ssub_0
    7841             :       0,        // dsub_7_then_ssub_1
    7842             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    7843             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    7844             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    7845             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    7846             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    7847             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    7848             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    7849             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    7850             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    7851             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    7852             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    7853             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    7854             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    7855             :       0,        // ssub_6_ssub_7_dsub_5
    7856             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    7857             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    7858             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    7859             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    7860             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    7861             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    7862             :       0,        // dsub_5_dsub_7
    7863             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    7864             :       0,        // dsub_5_ssub_12_ssub_13
    7865             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    7866             :     },
    7867             :     {   // rGPR
    7868             :       0,        // dsub_0
    7869             :       0,        // dsub_1
    7870             :       0,        // dsub_2
    7871             :       0,        // dsub_3
    7872             :       0,        // dsub_4
    7873             :       0,        // dsub_5
    7874             :       0,        // dsub_6
    7875             :       0,        // dsub_7
    7876             :       0,        // gsub_0
    7877             :       0,        // gsub_1
    7878             :       0,        // qqsub_0
    7879             :       0,        // qqsub_1
    7880             :       0,        // qsub_0
    7881             :       0,        // qsub_1
    7882             :       0,        // qsub_2
    7883             :       0,        // qsub_3
    7884             :       0,        // ssub_0
    7885             :       0,        // ssub_1
    7886             :       0,        // ssub_2
    7887             :       0,        // ssub_3
    7888             :       0,        // ssub_4
    7889             :       0,        // ssub_5
    7890             :       0,        // ssub_6
    7891             :       0,        // ssub_7
    7892             :       0,        // ssub_8
    7893             :       0,        // ssub_9
    7894             :       0,        // ssub_10
    7895             :       0,        // ssub_11
    7896             :       0,        // ssub_12
    7897             :       0,        // ssub_13
    7898             :       0,        // dsub_7_then_ssub_0
    7899             :       0,        // dsub_7_then_ssub_1
    7900             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    7901             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    7902             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    7903             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    7904             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    7905             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    7906             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    7907             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    7908             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    7909             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    7910             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    7911             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    7912             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    7913             :       0,        // ssub_6_ssub_7_dsub_5
    7914             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    7915             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    7916             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    7917             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    7918             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    7919             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    7920             :       0,        // dsub_5_dsub_7
    7921             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    7922             :       0,        // dsub_5_ssub_12_ssub_13
    7923             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    7924             :     },
    7925             :     {   // tGPRwithpc
    7926             :       0,        // dsub_0
    7927             :       0,        // dsub_1
    7928             :       0,        // dsub_2
    7929             :       0,        // dsub_3
    7930             :       0,        // dsub_4
    7931             :       0,        // dsub_5
    7932             :       0,        // dsub_6
    7933             :       0,        // dsub_7
    7934             :       0,        // gsub_0
    7935             :       0,        // gsub_1
    7936             :       0,        // qqsub_0
    7937             :       0,        // qqsub_1
    7938             :       0,        // qsub_0
    7939             :       0,        // qsub_1
    7940             :       0,        // qsub_2
    7941             :       0,        // qsub_3
    7942             :       0,        // ssub_0
    7943             :       0,        // ssub_1
    7944             :       0,        // ssub_2
    7945             :       0,        // ssub_3
    7946             :       0,        // ssub_4
    7947             :       0,        // ssub_5
    7948             :       0,        // ssub_6
    7949             :       0,        // ssub_7
    7950             :       0,        // ssub_8
    7951             :       0,        // ssub_9
    7952             :       0,        // ssub_10
    7953             :       0,        // ssub_11
    7954             :       0,        // ssub_12
    7955             :       0,        // ssub_13
    7956             :       0,        // dsub_7_then_ssub_0
    7957             :       0,        // dsub_7_then_ssub_1
    7958             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    7959             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    7960             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    7961             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    7962             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    7963             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    7964             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    7965             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    7966             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    7967             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    7968             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    7969             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    7970             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    7971             :       0,        // ssub_6_ssub_7_dsub_5
    7972             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    7973             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    7974             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    7975             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    7976             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    7977             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    7978             :       0,        // dsub_5_dsub_7
    7979             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    7980             :       0,        // dsub_5_ssub_12_ssub_13
    7981             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    7982             :     },
    7983             :     {   // hGPR
    7984             :       0,        // dsub_0
    7985             :       0,        // dsub_1
    7986             :       0,        // dsub_2
    7987             :       0,        // dsub_3
    7988             :       0,        // dsub_4
    7989             :       0,        // dsub_5
    7990             :       0,        // dsub_6
    7991             :       0,        // dsub_7
    7992             :       0,        // gsub_0
    7993             :       0,        // gsub_1
    7994             :       0,        // qqsub_0
    7995             :       0,        // qqsub_1
    7996             :       0,        // qsub_0
    7997             :       0,        // qsub_1
    7998             :       0,        // qsub_2
    7999             :       0,        // qsub_3
    8000             :       0,        // ssub_0
    8001             :       0,        // ssub_1
    8002             :       0,        // ssub_2
    8003             :       0,        // ssub_3
    8004             :       0,        // ssub_4
    8005             :       0,        // ssub_5
    8006             :       0,        // ssub_6
    8007             :       0,        // ssub_7
    8008             :       0,        // ssub_8
    8009             :       0,        // ssub_9
    8010             :       0,        // ssub_10
    8011             :       0,        // ssub_11
    8012             :       0,        // ssub_12
    8013             :       0,        // ssub_13
    8014             :       0,        // dsub_7_then_ssub_0
    8015             :       0,        // dsub_7_then_ssub_1
    8016             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    8017             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    8018             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    8019             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    8020             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    8021             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    8022             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8023             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    8024             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    8025             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8026             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    8027             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8028             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8029             :       0,        // ssub_6_ssub_7_dsub_5
    8030             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    8031             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    8032             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    8033             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8034             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    8035             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8036             :       0,        // dsub_5_dsub_7
    8037             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    8038             :       0,        // dsub_5_ssub_12_ssub_13
    8039             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    8040             :     },
    8041             :     {   // tGPR
    8042             :       0,        // dsub_0
    8043             :       0,        // dsub_1
    8044             :       0,        // dsub_2
    8045             :       0,        // dsub_3
    8046             :       0,        // dsub_4
    8047             :       0,        // dsub_5
    8048             :       0,        // dsub_6
    8049             :       0,        // dsub_7
    8050             :       0,        // gsub_0
    8051             :       0,        // gsub_1
    8052             :       0,        // qqsub_0
    8053             :       0,        // qqsub_1
    8054             :       0,        // qsub_0
    8055             :       0,        // qsub_1
    8056             :       0,        // qsub_2
    8057             :       0,        // qsub_3
    8058             :       0,        // ssub_0
    8059             :       0,        // ssub_1
    8060             :       0,        // ssub_2
    8061             :       0,        // ssub_3
    8062             :       0,        // ssub_4
    8063             :       0,        // ssub_5
    8064             :       0,        // ssub_6
    8065             :       0,        // ssub_7
    8066             :       0,        // ssub_8
    8067             :       0,        // ssub_9
    8068             :       0,        // ssub_10
    8069             :       0,        // ssub_11
    8070             :       0,        // ssub_12
    8071             :       0,        // ssub_13
    8072             :       0,        // dsub_7_then_ssub_0
    8073             :       0,        // dsub_7_then_ssub_1
    8074             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    8075             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    8076             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    8077             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    8078             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    8079             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    8080             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8081             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    8082             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    8083             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8084             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    8085             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8086             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8087             :       0,        // ssub_6_ssub_7_dsub_5
    8088             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    8089             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    8090             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    8091             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8092             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    8093             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8094             :       0,        // dsub_5_dsub_7
    8095             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    8096             :       0,        // dsub_5_ssub_12_ssub_13
    8097             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    8098             :     },
    8099             :     {   // GPRnopc_and_hGPR
    8100             :       0,        // dsub_0
    8101             :       0,        // dsub_1
    8102             :       0,        // dsub_2
    8103             :       0,        // dsub_3
    8104             :       0,        // dsub_4
    8105             :       0,        // dsub_5
    8106             :       0,        // dsub_6
    8107             :       0,        // dsub_7
    8108             :       0,        // gsub_0
    8109             :       0,        // gsub_1
    8110             :       0,        // qqsub_0
    8111             :       0,        // qqsub_1
    8112             :       0,        // qsub_0
    8113             :       0,        // qsub_1
    8114             :       0,        // qsub_2
    8115             :       0,        // qsub_3
    8116             :       0,        // ssub_0
    8117             :       0,        // ssub_1
    8118             :       0,        // ssub_2
    8119             :       0,        // ssub_3
    8120             :       0,        // ssub_4
    8121             :       0,        // ssub_5
    8122             :       0,        // ssub_6
    8123             :       0,        // ssub_7
    8124             :       0,        // ssub_8
    8125             :       0,        // ssub_9
    8126             :       0,        // ssub_10
    8127             :       0,        // ssub_11
    8128             :       0,        // ssub_12
    8129             :       0,        // ssub_13
    8130             :       0,        // dsub_7_then_ssub_0
    8131             :       0,        // dsub_7_then_ssub_1
    8132             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    8133             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    8134             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    8135             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    8136             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    8137             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    8138             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8139             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    8140             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    8141             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8142             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    8143             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8144             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8145             :       0,        // ssub_6_ssub_7_dsub_5
    8146             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    8147             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    8148             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    8149             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8150             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    8151             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8152             :       0,        // dsub_5_dsub_7
    8153             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    8154             :       0,        // dsub_5_ssub_12_ssub_13
    8155             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    8156             :     },
    8157             :     {   // hGPR_and_rGPR
    8158             :       0,        // dsub_0
    8159             :       0,        // dsub_1
    8160             :       0,        // dsub_2
    8161             :       0,        // dsub_3
    8162             :       0,        // dsub_4
    8163             :       0,        // dsub_5
    8164             :       0,        // dsub_6
    8165             :       0,        // dsub_7
    8166             :       0,        // gsub_0
    8167             :       0,        // gsub_1
    8168             :       0,        // qqsub_0
    8169             :       0,        // qqsub_1
    8170             :       0,        // qsub_0
    8171             :       0,        // qsub_1
    8172             :       0,        // qsub_2
    8173             :       0,        // qsub_3
    8174             :       0,        // ssub_0
    8175             :       0,        // ssub_1
    8176             :       0,        // ssub_2
    8177             :       0,        // ssub_3
    8178             :       0,        // ssub_4
    8179             :       0,        // ssub_5
    8180             :       0,        // ssub_6
    8181             :       0,        // ssub_7
    8182             :       0,        // ssub_8
    8183             :       0,        // ssub_9
    8184             :       0,        // ssub_10
    8185             :       0,        // ssub_11
    8186             :       0,        // ssub_12
    8187             :       0,        // ssub_13
    8188             :       0,        // dsub_7_then_ssub_0
    8189             :       0,        // dsub_7_then_ssub_1
    8190             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    8191             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    8192             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    8193             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    8194             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    8195             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    8196             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8197             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    8198             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    8199             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8200             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    8201             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8202             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8203             :       0,        // ssub_6_ssub_7_dsub_5
    8204             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    8205             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    8206             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    8207             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8208             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    8209             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8210             :       0,        // dsub_5_dsub_7
    8211             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    8212             :       0,        // dsub_5_ssub_12_ssub_13
    8213             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    8214             :     },
    8215             :     {   // tcGPR
    8216             :       0,        // dsub_0
    8217             :       0,        // dsub_1
    8218             :       0,        // dsub_2
    8219             :       0,        // dsub_3
    8220             :       0,        // dsub_4
    8221             :       0,        // dsub_5
    8222             :       0,        // dsub_6
    8223             :       0,        // dsub_7
    8224             :       0,        // gsub_0
    8225             :       0,        // gsub_1
    8226             :       0,        // qqsub_0
    8227             :       0,        // qqsub_1
    8228             :       0,        // qsub_0
    8229             :       0,        // qsub_1
    8230             :       0,        // qsub_2
    8231             :       0,        // qsub_3
    8232             :       0,        // ssub_0
    8233             :       0,        // ssub_1
    8234             :       0,        // ssub_2
    8235             :       0,        // ssub_3
    8236             :       0,        // ssub_4
    8237             :       0,        // ssub_5
    8238             :       0,        // ssub_6
    8239             :       0,        // ssub_7
    8240             :       0,        // ssub_8
    8241             :       0,        // ssub_9
    8242             :       0,        // ssub_10
    8243             :       0,        // ssub_11
    8244             :       0,        // ssub_12
    8245             :       0,        // ssub_13
    8246             :       0,        // dsub_7_then_ssub_0
    8247             :       0,        // dsub_7_then_ssub_1
    8248             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    8249             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    8250             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    8251             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    8252             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    8253             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    8254             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8255             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    8256             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    8257             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8258             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    8259             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8260             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8261             :       0,        // ssub_6_ssub_7_dsub_5
    8262             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    8263             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    8264             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    8265             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8266             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    8267             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8268             :       0,        // dsub_5_dsub_7
    8269             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    8270             :       0,        // dsub_5_ssub_12_ssub_13
    8271             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    8272             :     },
    8273             :     {   // tGPR_and_tcGPR
    8274             :       0,        // dsub_0
    8275             :       0,        // dsub_1
    8276             :       0,        // dsub_2
    8277             :       0,        // dsub_3
    8278             :       0,        // dsub_4
    8279             :       0,        // dsub_5
    8280             :       0,        // dsub_6
    8281             :       0,        // dsub_7
    8282             :       0,        // gsub_0
    8283             :       0,        // gsub_1
    8284             :       0,        // qqsub_0
    8285             :       0,        // qqsub_1
    8286             :       0,        // qsub_0
    8287             :       0,        // qsub_1
    8288             :       0,        // qsub_2
    8289             :       0,        // qsub_3
    8290             :       0,        // ssub_0
    8291             :       0,        // ssub_1
    8292             :       0,        // ssub_2
    8293             :       0,        // ssub_3
    8294             :       0,        // ssub_4
    8295             :       0,        // ssub_5
    8296             :       0,        // ssub_6
    8297             :       0,        // ssub_7
    8298             :       0,        // ssub_8
    8299             :       0,        // ssub_9
    8300             :       0,        // ssub_10
    8301             :       0,        // ssub_11
    8302             :       0,        // ssub_12
    8303             :       0,        // ssub_13
    8304             :       0,        // dsub_7_then_ssub_0
    8305             :       0,        // dsub_7_then_ssub_1
    8306             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    8307             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    8308             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    8309             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    8310             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    8311             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    8312             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8313             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    8314             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    8315             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8316             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    8317             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8318             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8319             :       0,        // ssub_6_ssub_7_dsub_5
    8320             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    8321             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    8322             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    8323             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8324             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    8325             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8326             :       0,        // dsub_5_dsub_7
    8327             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    8328             :       0,        // dsub_5_ssub_12_ssub_13
    8329             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    8330             :     },
    8331             :     {   // CCR
    8332             :       0,        // dsub_0
    8333             :       0,        // dsub_1
    8334             :       0,        // dsub_2
    8335             :       0,        // dsub_3
    8336             :       0,        // dsub_4
    8337             :       0,        // dsub_5
    8338             :       0,        // dsub_6
    8339             :       0,        // dsub_7
    8340             :       0,        // gsub_0
    8341             :       0,        // gsub_1
    8342             :       0,        // qqsub_0
    8343             :       0,        // qqsub_1
    8344             :       0,        // qsub_0
    8345             :       0,        // qsub_1
    8346             :       0,        // qsub_2
    8347             :       0,        // qsub_3
    8348             :       0,        // ssub_0
    8349             :       0,        // ssub_1
    8350             :       0,        // ssub_2
    8351             :       0,        // ssub_3
    8352             :       0,        // ssub_4
    8353             :       0,        // ssub_5
    8354             :       0,        // ssub_6
    8355             :       0,        // ssub_7
    8356             :       0,        // ssub_8
    8357             :       0,        // ssub_9
    8358             :       0,        // ssub_10
    8359             :       0,        // ssub_11
    8360             :       0,        // ssub_12
    8361             :       0,        // ssub_13
    8362             :       0,        // dsub_7_then_ssub_0
    8363             :       0,        // dsub_7_then_ssub_1
    8364             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    8365             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    8366             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    8367             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    8368             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    8369             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    8370             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8371             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    8372             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    8373             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8374             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    8375             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8376             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8377             :       0,        // ssub_6_ssub_7_dsub_5
    8378             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    8379             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    8380             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    8381             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8382             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    8383             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8384             :       0,        // dsub_5_dsub_7
    8385             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    8386             :       0,        // dsub_5_ssub_12_ssub_13
    8387             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    8388             :     },
    8389             :     {   // GPRsp
    8390             :       0,        // dsub_0
    8391             :       0,        // dsub_1
    8392             :       0,        // dsub_2
    8393             :       0,        // dsub_3
    8394             :       0,        // dsub_4
    8395             :       0,        // dsub_5
    8396             :       0,        // dsub_6
    8397             :       0,        // dsub_7
    8398             :       0,        // gsub_0
    8399             :       0,        // gsub_1
    8400             :       0,        // qqsub_0
    8401             :       0,        // qqsub_1
    8402             :       0,        // qsub_0
    8403             :       0,        // qsub_1
    8404             :       0,        // qsub_2
    8405             :       0,        // qsub_3
    8406             :       0,        // ssub_0
    8407             :       0,        // ssub_1
    8408             :       0,        // ssub_2
    8409             :       0,        // ssub_3
    8410             :       0,        // ssub_4
    8411             :       0,        // ssub_5
    8412             :       0,        // ssub_6
    8413             :       0,        // ssub_7
    8414             :       0,        // ssub_8
    8415             :       0,        // ssub_9
    8416             :       0,        // ssub_10
    8417             :       0,        // ssub_11
    8418             :       0,        // ssub_12
    8419             :       0,        // ssub_13
    8420             :       0,        // dsub_7_then_ssub_0
    8421             :       0,        // dsub_7_then_ssub_1
    8422             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    8423             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    8424             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    8425             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    8426             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    8427             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    8428             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8429             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    8430             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    8431             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8432             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    8433             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8434             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8435             :       0,        // ssub_6_ssub_7_dsub_5
    8436             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    8437             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    8438             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    8439             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8440             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    8441             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8442             :       0,        // dsub_5_dsub_7
    8443             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    8444             :       0,        // dsub_5_ssub_12_ssub_13
    8445             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    8446             :     },
    8447             :     {   // hGPR_and_tGPRwithpc
    8448             :       0,        // dsub_0
    8449             :       0,        // dsub_1
    8450             :       0,        // dsub_2
    8451             :       0,        // dsub_3
    8452             :       0,        // dsub_4
    8453             :       0,        // dsub_5
    8454             :       0,        // dsub_6
    8455             :       0,        // dsub_7
    8456             :       0,        // gsub_0
    8457             :       0,        // gsub_1
    8458             :       0,        // qqsub_0
    8459             :       0,        // qqsub_1
    8460             :       0,        // qsub_0
    8461             :       0,        // qsub_1
    8462             :       0,        // qsub_2
    8463             :       0,        // qsub_3
    8464             :       0,        // ssub_0
    8465             :       0,        // ssub_1
    8466             :       0,        // ssub_2
    8467             :       0,        // ssub_3
    8468             :       0,        // ssub_4
    8469             :       0,        // ssub_5
    8470             :       0,        // ssub_6
    8471             :       0,        // ssub_7
    8472             :       0,        // ssub_8
    8473             :       0,        // ssub_9
    8474             :       0,        // ssub_10
    8475             :       0,        // ssub_11
    8476             :       0,        // ssub_12
    8477             :       0,        // ssub_13
    8478             :       0,        // dsub_7_then_ssub_0
    8479             :       0,        // dsub_7_then_ssub_1
    8480             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    8481             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    8482             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    8483             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    8484             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    8485             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    8486             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8487             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    8488             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    8489             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8490             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    8491             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8492             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8493             :       0,        // ssub_6_ssub_7_dsub_5
    8494             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    8495             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    8496             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    8497             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8498             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    8499             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8500             :       0,        // dsub_5_dsub_7
    8501             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    8502             :       0,        // dsub_5_ssub_12_ssub_13
    8503             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    8504             :     },
    8505             :     {   // hGPR_and_tcGPR
    8506             :       0,        // dsub_0
    8507             :       0,        // dsub_1
    8508             :       0,        // dsub_2
    8509             :       0,        // dsub_3
    8510             :       0,        // dsub_4
    8511             :       0,        // dsub_5
    8512             :       0,        // dsub_6
    8513             :       0,        // dsub_7
    8514             :       0,        // gsub_0
    8515             :       0,        // gsub_1
    8516             :       0,        // qqsub_0
    8517             :       0,        // qqsub_1
    8518             :       0,        // qsub_0
    8519             :       0,        // qsub_1
    8520             :       0,        // qsub_2
    8521             :       0,        // qsub_3
    8522             :       0,        // ssub_0
    8523             :       0,        // ssub_1
    8524             :       0,        // ssub_2
    8525             :       0,        // ssub_3
    8526             :       0,        // ssub_4
    8527             :       0,        // ssub_5
    8528             :       0,        // ssub_6
    8529             :       0,        // ssub_7
    8530             :       0,        // ssub_8
    8531             :       0,        // ssub_9
    8532             :       0,        // ssub_10
    8533             :       0,        // ssub_11
    8534             :       0,        // ssub_12
    8535             :       0,        // ssub_13
    8536             :       0,        // dsub_7_then_ssub_0
    8537             :       0,        // dsub_7_then_ssub_1
    8538             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    8539             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    8540             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    8541             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    8542             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    8543             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    8544             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8545             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    8546             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    8547             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8548             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    8549             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8550             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8551             :       0,        // ssub_6_ssub_7_dsub_5
    8552             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    8553             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    8554             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    8555             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8556             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    8557             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8558             :       0,        // dsub_5_dsub_7
    8559             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    8560             :       0,        // dsub_5_ssub_12_ssub_13
    8561             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    8562             :     },
    8563             :     {   // DPR
    8564             :       0,        // dsub_0
    8565             :       0,        // dsub_1
    8566             :       0,        // dsub_2
    8567             :       0,        // dsub_3
    8568             :       0,        // dsub_4
    8569             :       0,        // dsub_5
    8570             :       0,        // dsub_6
    8571             :       0,        // dsub_7
    8572             :       0,        // gsub_0
    8573             :       0,        // gsub_1
    8574             :       0,        // qqsub_0
    8575             :       0,        // qqsub_1
    8576             :       0,        // qsub_0
    8577             :       0,        // qsub_1
    8578             :       0,        // qsub_2
    8579             :       0,        // qsub_3
    8580             :       19,       // ssub_0 -> DPR_VFP2
    8581             :       19,       // ssub_1 -> DPR_VFP2
    8582             :       0,        // ssub_2
    8583             :       0,        // ssub_3
    8584             :       0,        // ssub_4
    8585             :       0,        // ssub_5
    8586             :       0,        // ssub_6
    8587             :       0,        // ssub_7
    8588             :       0,        // ssub_8
    8589             :       0,        // ssub_9
    8590             :       0,        // ssub_10
    8591             :       0,        // ssub_11
    8592             :       0,        // ssub_12
    8593             :       0,        // ssub_13
    8594             :       0,        // dsub_7_then_ssub_0
    8595             :       0,        // dsub_7_then_ssub_1
    8596             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    8597             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    8598             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    8599             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    8600             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    8601             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    8602             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8603             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    8604             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    8605             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8606             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    8607             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8608             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8609             :       0,        // ssub_6_ssub_7_dsub_5
    8610             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    8611             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    8612             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    8613             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8614             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    8615             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8616             :       0,        // dsub_5_dsub_7
    8617             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    8618             :       0,        // dsub_5_ssub_12_ssub_13
    8619             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    8620             :     },
    8621             :     {   // DPR_VFP2
    8622             :       0,        // dsub_0
    8623             :       0,        // dsub_1
    8624             :       0,        // dsub_2
    8625             :       0,        // dsub_3
    8626             :       0,        // dsub_4
    8627             :       0,        // dsub_5
    8628             :       0,        // dsub_6
    8629             :       0,        // dsub_7
    8630             :       0,        // gsub_0
    8631             :       0,        // gsub_1
    8632             :       0,        // qqsub_0
    8633             :       0,        // qqsub_1
    8634             :       0,        // qsub_0
    8635             :       0,        // qsub_1
    8636             :       0,        // qsub_2
    8637             :       0,        // qsub_3
    8638             :       19,       // ssub_0 -> DPR_VFP2
    8639             :       19,       // ssub_1 -> DPR_VFP2
    8640             :       0,        // ssub_2
    8641             :       0,        // ssub_3
    8642             :       0,        // ssub_4
    8643             :       0,        // ssub_5
    8644             :       0,        // ssub_6
    8645             :       0,        // ssub_7
    8646             :       0,        // ssub_8
    8647             :       0,        // ssub_9
    8648             :       0,        // ssub_10
    8649             :       0,        // ssub_11
    8650             :       0,        // ssub_12
    8651             :       0,        // ssub_13
    8652             :       0,        // dsub_7_then_ssub_0
    8653             :       0,        // dsub_7_then_ssub_1
    8654             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    8655             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    8656             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    8657             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    8658             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    8659             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    8660             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8661             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    8662             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    8663             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8664             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    8665             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8666             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8667             :       0,        // ssub_6_ssub_7_dsub_5
    8668             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    8669             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    8670             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    8671             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8672             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    8673             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8674             :       0,        // dsub_5_dsub_7
    8675             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    8676             :       0,        // dsub_5_ssub_12_ssub_13
    8677             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    8678             :     },
    8679             :     {   // DPR_8
    8680             :       0,        // dsub_0
    8681             :       0,        // dsub_1
    8682             :       0,        // dsub_2
    8683             :       0,        // dsub_3
    8684             :       0,        // dsub_4
    8685             :       0,        // dsub_5
    8686             :       0,        // dsub_6
    8687             :       0,        // dsub_7
    8688             :       0,        // gsub_0
    8689             :       0,        // gsub_1
    8690             :       0,        // qqsub_0
    8691             :       0,        // qqsub_1
    8692             :       0,        // qsub_0
    8693             :       0,        // qsub_1
    8694             :       0,        // qsub_2
    8695             :       0,        // qsub_3
    8696             :       20,       // ssub_0 -> DPR_8
    8697             :       20,       // ssub_1 -> DPR_8
    8698             :       0,        // ssub_2
    8699             :       0,        // ssub_3
    8700             :       0,        // ssub_4
    8701             :       0,        // ssub_5
    8702             :       0,        // ssub_6
    8703             :       0,        // ssub_7
    8704             :       0,        // ssub_8
    8705             :       0,        // ssub_9
    8706             :       0,        // ssub_10
    8707             :       0,        // ssub_11
    8708             :       0,        // ssub_12
    8709             :       0,        // ssub_13
    8710             :       0,        // dsub_7_then_ssub_0
    8711             :       0,        // dsub_7_then_ssub_1
    8712             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    8713             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    8714             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    8715             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    8716             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    8717             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    8718             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8719             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    8720             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    8721             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8722             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    8723             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8724             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8725             :       0,        // ssub_6_ssub_7_dsub_5
    8726             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    8727             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    8728             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    8729             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8730             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    8731             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8732             :       0,        // dsub_5_dsub_7
    8733             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    8734             :       0,        // dsub_5_ssub_12_ssub_13
    8735             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    8736             :     },
    8737             :     {   // GPRPair
    8738             :       0,        // dsub_0
    8739             :       0,        // dsub_1
    8740             :       0,        // dsub_2
    8741             :       0,        // dsub_3
    8742             :       0,        // dsub_4
    8743             :       0,        // dsub_5
    8744             :       0,        // dsub_6
    8745             :       0,        // dsub_7
    8746             :       21,       // gsub_0 -> GPRPair
    8747             :       21,       // gsub_1 -> GPRPair
    8748             :       0,        // qqsub_0
    8749             :       0,        // qqsub_1
    8750             :       0,        // qsub_0
    8751             :       0,        // qsub_1
    8752             :       0,        // qsub_2
    8753             :       0,        // qsub_3
    8754             :       0,        // ssub_0
    8755             :       0,        // ssub_1
    8756             :       0,        // ssub_2
    8757             :       0,        // ssub_3
    8758             :       0,        // ssub_4
    8759             :       0,        // ssub_5
    8760             :       0,        // ssub_6
    8761             :       0,        // ssub_7
    8762             :       0,        // ssub_8
    8763             :       0,        // ssub_9
    8764             :       0,        // ssub_10
    8765             :       0,        // ssub_11
    8766             :       0,        // ssub_12
    8767             :       0,        // ssub_13
    8768             :       0,        // dsub_7_then_ssub_0
    8769             :       0,        // dsub_7_then_ssub_1
    8770             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    8771             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    8772             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    8773             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    8774             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    8775             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    8776             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8777             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    8778             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    8779             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8780             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    8781             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8782             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8783             :       0,        // ssub_6_ssub_7_dsub_5
    8784             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    8785             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    8786             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    8787             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8788             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    8789             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8790             :       0,        // dsub_5_dsub_7
    8791             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    8792             :       0,        // dsub_5_ssub_12_ssub_13
    8793             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    8794             :     },
    8795             :     {   // GPRPair_with_gsub_1_in_rGPR
    8796             :       0,        // dsub_0
    8797             :       0,        // dsub_1
    8798             :       0,        // dsub_2
    8799             :       0,        // dsub_3
    8800             :       0,        // dsub_4
    8801             :       0,        // dsub_5
    8802             :       0,        // dsub_6
    8803             :       0,        // dsub_7
    8804             :       22,       // gsub_0 -> GPRPair_with_gsub_1_in_rGPR
    8805             :       22,       // gsub_1 -> GPRPair_with_gsub_1_in_rGPR
    8806             :       0,        // qqsub_0
    8807             :       0,        // qqsub_1
    8808             :       0,        // qsub_0
    8809             :       0,        // qsub_1
    8810             :       0,        // qsub_2
    8811             :       0,        // qsub_3
    8812             :       0,        // ssub_0
    8813             :       0,        // ssub_1
    8814             :       0,        // ssub_2
    8815             :       0,        // ssub_3
    8816             :       0,        // ssub_4
    8817             :       0,        // ssub_5
    8818             :       0,        // ssub_6
    8819             :       0,        // ssub_7
    8820             :       0,        // ssub_8
    8821             :       0,        // ssub_9
    8822             :       0,        // ssub_10
    8823             :       0,        // ssub_11
    8824             :       0,        // ssub_12
    8825             :       0,        // ssub_13
    8826             :       0,        // dsub_7_then_ssub_0
    8827             :       0,        // dsub_7_then_ssub_1
    8828             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    8829             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    8830             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    8831             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    8832             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    8833             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    8834             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8835             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    8836             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    8837             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8838             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    8839             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8840             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8841             :       0,        // ssub_6_ssub_7_dsub_5
    8842             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    8843             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    8844             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    8845             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8846             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    8847             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8848             :       0,        // dsub_5_dsub_7
    8849             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    8850             :       0,        // dsub_5_ssub_12_ssub_13
    8851             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    8852             :     },
    8853             :     {   // GPRPair_with_gsub_0_in_tGPR
    8854             :       0,        // dsub_0
    8855             :       0,        // dsub_1
    8856             :       0,        // dsub_2
    8857             :       0,        // dsub_3
    8858             :       0,        // dsub_4
    8859             :       0,        // dsub_5
    8860             :       0,        // dsub_6
    8861             :       0,        // dsub_7
    8862             :       23,       // gsub_0 -> GPRPair_with_gsub_0_in_tGPR
    8863             :       23,       // gsub_1 -> GPRPair_with_gsub_0_in_tGPR
    8864             :       0,        // qqsub_0
    8865             :       0,        // qqsub_1
    8866             :       0,        // qsub_0
    8867             :       0,        // qsub_1
    8868             :       0,        // qsub_2
    8869             :       0,        // qsub_3
    8870             :       0,        // ssub_0
    8871             :       0,        // ssub_1
    8872             :       0,        // ssub_2
    8873             :       0,        // ssub_3
    8874             :       0,        // ssub_4
    8875             :       0,        // ssub_5
    8876             :       0,        // ssub_6
    8877             :       0,        // ssub_7
    8878             :       0,        // ssub_8
    8879             :       0,        // ssub_9
    8880             :       0,        // ssub_10
    8881             :       0,        // ssub_11
    8882             :       0,        // ssub_12
    8883             :       0,        // ssub_13
    8884             :       0,        // dsub_7_then_ssub_0
    8885             :       0,        // dsub_7_then_ssub_1
    8886             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    8887             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    8888             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    8889             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    8890             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    8891             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    8892             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8893             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    8894             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    8895             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8896             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    8897             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8898             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8899             :       0,        // ssub_6_ssub_7_dsub_5
    8900             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    8901             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    8902             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    8903             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8904             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    8905             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8906             :       0,        // dsub_5_dsub_7
    8907             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    8908             :       0,        // dsub_5_ssub_12_ssub_13
    8909             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    8910             :     },
    8911             :     {   // GPRPair_with_gsub_0_in_hGPR
    8912             :       0,        // dsub_0
    8913             :       0,        // dsub_1
    8914             :       0,        // dsub_2
    8915             :       0,        // dsub_3
    8916             :       0,        // dsub_4
    8917             :       0,        // dsub_5
    8918             :       0,        // dsub_6
    8919             :       0,        // dsub_7
    8920             :       24,       // gsub_0 -> GPRPair_with_gsub_0_in_hGPR
    8921             :       24,       // gsub_1 -> GPRPair_with_gsub_0_in_hGPR
    8922             :       0,        // qqsub_0
    8923             :       0,        // qqsub_1
    8924             :       0,        // qsub_0
    8925             :       0,        // qsub_1
    8926             :       0,        // qsub_2
    8927             :       0,        // qsub_3
    8928             :       0,        // ssub_0
    8929             :       0,        // ssub_1
    8930             :       0,        // ssub_2
    8931             :       0,        // ssub_3
    8932             :       0,        // ssub_4
    8933             :       0,        // ssub_5
    8934             :       0,        // ssub_6
    8935             :       0,        // ssub_7
    8936             :       0,        // ssub_8
    8937             :       0,        // ssub_9
    8938             :       0,        // ssub_10
    8939             :       0,        // ssub_11
    8940             :       0,        // ssub_12
    8941             :       0,        // ssub_13
    8942             :       0,        // dsub_7_then_ssub_0
    8943             :       0,        // dsub_7_then_ssub_1
    8944             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    8945             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    8946             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    8947             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    8948             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    8949             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    8950             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8951             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    8952             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    8953             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8954             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    8955             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    8956             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    8957             :       0,        // ssub_6_ssub_7_dsub_5
    8958             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    8959             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    8960             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    8961             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8962             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    8963             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    8964             :       0,        // dsub_5_dsub_7
    8965             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    8966             :       0,        // dsub_5_ssub_12_ssub_13
    8967             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    8968             :     },
    8969             :     {   // GPRPair_with_gsub_0_in_tcGPR
    8970             :       0,        // dsub_0
    8971             :       0,        // dsub_1
    8972             :       0,        // dsub_2
    8973             :       0,        // dsub_3
    8974             :       0,        // dsub_4
    8975             :       0,        // dsub_5
    8976             :       0,        // dsub_6
    8977             :       0,        // dsub_7
    8978             :       25,       // gsub_0 -> GPRPair_with_gsub_0_in_tcGPR
    8979             :       25,       // gsub_1 -> GPRPair_with_gsub_0_in_tcGPR
    8980             :       0,        // qqsub_0
    8981             :       0,        // qqsub_1
    8982             :       0,        // qsub_0
    8983             :       0,        // qsub_1
    8984             :       0,        // qsub_2
    8985             :       0,        // qsub_3
    8986             :       0,        // ssub_0
    8987             :       0,        // ssub_1
    8988             :       0,        // ssub_2
    8989             :       0,        // ssub_3
    8990             :       0,        // ssub_4
    8991             :       0,        // ssub_5
    8992             :       0,        // ssub_6
    8993             :       0,        // ssub_7
    8994             :       0,        // ssub_8
    8995             :       0,        // ssub_9
    8996             :       0,        // ssub_10
    8997             :       0,        // ssub_11
    8998             :       0,        // ssub_12
    8999             :       0,        // ssub_13
    9000             :       0,        // dsub_7_then_ssub_0
    9001             :       0,        // dsub_7_then_ssub_1
    9002             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    9003             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    9004             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    9005             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    9006             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    9007             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    9008             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9009             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    9010             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    9011             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9012             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    9013             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9014             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9015             :       0,        // ssub_6_ssub_7_dsub_5
    9016             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    9017             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    9018             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    9019             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9020             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    9021             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9022             :       0,        // dsub_5_dsub_7
    9023             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    9024             :       0,        // dsub_5_ssub_12_ssub_13
    9025             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    9026             :     },
    9027             :     {   // GPRPair_with_gsub_1_in_hGPR_and_rGPR
    9028             :       0,        // dsub_0
    9029             :       0,        // dsub_1
    9030             :       0,        // dsub_2
    9031             :       0,        // dsub_3
    9032             :       0,        // dsub_4
    9033             :       0,        // dsub_5
    9034             :       0,        // dsub_6
    9035             :       0,        // dsub_7
    9036             :       26,       // gsub_0 -> GPRPair_with_gsub_1_in_hGPR_and_rGPR
    9037             :       26,       // gsub_1 -> GPRPair_with_gsub_1_in_hGPR_and_rGPR
    9038             :       0,        // qqsub_0
    9039             :       0,        // qqsub_1
    9040             :       0,        // qsub_0
    9041             :       0,        // qsub_1
    9042             :       0,        // qsub_2
    9043             :       0,        // qsub_3
    9044             :       0,        // ssub_0
    9045             :       0,        // ssub_1
    9046             :       0,        // ssub_2
    9047             :       0,        // ssub_3
    9048             :       0,        // ssub_4
    9049             :       0,        // ssub_5
    9050             :       0,        // ssub_6
    9051             :       0,        // ssub_7
    9052             :       0,        // ssub_8
    9053             :       0,        // ssub_9
    9054             :       0,        // ssub_10
    9055             :       0,        // ssub_11
    9056             :       0,        // ssub_12
    9057             :       0,        // ssub_13
    9058             :       0,        // dsub_7_then_ssub_0
    9059             :       0,        // dsub_7_then_ssub_1
    9060             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    9061             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    9062             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    9063             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    9064             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    9065             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    9066             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9067             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    9068             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    9069             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9070             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    9071             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9072             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9073             :       0,        // ssub_6_ssub_7_dsub_5
    9074             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    9075             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    9076             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    9077             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9078             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    9079             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9080             :       0,        // dsub_5_dsub_7
    9081             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    9082             :       0,        // dsub_5_ssub_12_ssub_13
    9083             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    9084             :     },
    9085             :     {   // GPRPair_with_gsub_1_in_tcGPR
    9086             :       0,        // dsub_0
    9087             :       0,        // dsub_1
    9088             :       0,        // dsub_2
    9089             :       0,        // dsub_3
    9090             :       0,        // dsub_4
    9091             :       0,        // dsub_5
    9092             :       0,        // dsub_6
    9093             :       0,        // dsub_7
    9094             :       27,       // gsub_0 -> GPRPair_with_gsub_1_in_tcGPR
    9095             :       27,       // gsub_1 -> GPRPair_with_gsub_1_in_tcGPR
    9096             :       0,        // qqsub_0
    9097             :       0,        // qqsub_1
    9098             :       0,        // qsub_0
    9099             :       0,        // qsub_1
    9100             :       0,        // qsub_2
    9101             :       0,        // qsub_3
    9102             :       0,        // ssub_0
    9103             :       0,        // ssub_1
    9104             :       0,        // ssub_2
    9105             :       0,        // ssub_3
    9106             :       0,        // ssub_4
    9107             :       0,        // ssub_5
    9108             :       0,        // ssub_6
    9109             :       0,        // ssub_7
    9110             :       0,        // ssub_8
    9111             :       0,        // ssub_9
    9112             :       0,        // ssub_10
    9113             :       0,        // ssub_11
    9114             :       0,        // ssub_12
    9115             :       0,        // ssub_13
    9116             :       0,        // dsub_7_then_ssub_0
    9117             :       0,        // dsub_7_then_ssub_1
    9118             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    9119             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    9120             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    9121             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    9122             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    9123             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    9124             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9125             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    9126             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    9127             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9128             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    9129             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9130             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9131             :       0,        // ssub_6_ssub_7_dsub_5
    9132             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    9133             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    9134             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    9135             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9136             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    9137             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9138             :       0,        // dsub_5_dsub_7
    9139             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    9140             :       0,        // dsub_5_ssub_12_ssub_13
    9141             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    9142             :     },
    9143             :     {   // GPRPair_with_gsub_1_in_GPRsp
    9144             :       0,        // dsub_0
    9145             :       0,        // dsub_1
    9146             :       0,        // dsub_2
    9147             :       0,        // dsub_3
    9148             :       0,        // dsub_4
    9149             :       0,        // dsub_5
    9150             :       0,        // dsub_6
    9151             :       0,        // dsub_7
    9152             :       28,       // gsub_0 -> GPRPair_with_gsub_1_in_GPRsp
    9153             :       28,       // gsub_1 -> GPRPair_with_gsub_1_in_GPRsp
    9154             :       0,        // qqsub_0
    9155             :       0,        // qqsub_1
    9156             :       0,        // qsub_0
    9157             :       0,        // qsub_1
    9158             :       0,        // qsub_2
    9159             :       0,        // qsub_3
    9160             :       0,        // ssub_0
    9161             :       0,        // ssub_1
    9162             :       0,        // ssub_2
    9163             :       0,        // ssub_3
    9164             :       0,        // ssub_4
    9165             :       0,        // ssub_5
    9166             :       0,        // ssub_6
    9167             :       0,        // ssub_7
    9168             :       0,        // ssub_8
    9169             :       0,        // ssub_9
    9170             :       0,        // ssub_10
    9171             :       0,        // ssub_11
    9172             :       0,        // ssub_12
    9173             :       0,        // ssub_13
    9174             :       0,        // dsub_7_then_ssub_0
    9175             :       0,        // dsub_7_then_ssub_1
    9176             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    9177             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    9178             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    9179             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    9180             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    9181             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    9182             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9183             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    9184             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    9185             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9186             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    9187             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9188             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9189             :       0,        // ssub_6_ssub_7_dsub_5
    9190             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    9191             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    9192             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    9193             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9194             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    9195             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9196             :       0,        // dsub_5_dsub_7
    9197             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    9198             :       0,        // dsub_5_ssub_12_ssub_13
    9199             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    9200             :     },
    9201             :     {   // DPairSpc
    9202             :       29,       // dsub_0 -> DPairSpc
    9203             :       0,        // dsub_1
    9204             :       29,       // dsub_2 -> DPairSpc
    9205             :       0,        // dsub_3
    9206             :       0,        // dsub_4
    9207             :       0,        // dsub_5
    9208             :       0,        // dsub_6
    9209             :       0,        // dsub_7
    9210             :       0,        // gsub_0
    9211             :       0,        // gsub_1
    9212             :       0,        // qqsub_0
    9213             :       0,        // qqsub_1
    9214             :       0,        // qsub_0
    9215             :       0,        // qsub_1
    9216             :       0,        // qsub_2
    9217             :       0,        // qsub_3
    9218             :       30,       // ssub_0 -> DPairSpc_with_ssub_0
    9219             :       30,       // ssub_1 -> DPairSpc_with_ssub_0
    9220             :       0,        // ssub_2
    9221             :       0,        // ssub_3
    9222             :       31,       // ssub_4 -> DPairSpc_with_ssub_4
    9223             :       31,       // ssub_5 -> DPairSpc_with_ssub_4
    9224             :       0,        // ssub_6
    9225             :       0,        // ssub_7
    9226             :       0,        // ssub_8
    9227             :       0,        // ssub_9
    9228             :       0,        // ssub_10
    9229             :       0,        // ssub_11
    9230             :       0,        // ssub_12
    9231             :       0,        // ssub_13
    9232             :       0,        // dsub_7_then_ssub_0
    9233             :       0,        // dsub_7_then_ssub_1
    9234             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    9235             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    9236             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    9237             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    9238             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    9239             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    9240             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9241             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    9242             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    9243             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9244             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    9245             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9246             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9247             :       0,        // ssub_6_ssub_7_dsub_5
    9248             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    9249             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    9250             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    9251             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9252             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    9253             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9254             :       0,        // dsub_5_dsub_7
    9255             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    9256             :       0,        // dsub_5_ssub_12_ssub_13
    9257             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    9258             :     },
    9259             :     {   // DPairSpc_with_ssub_0
    9260             :       30,       // dsub_0 -> DPairSpc_with_ssub_0
    9261             :       0,        // dsub_1
    9262             :       30,       // dsub_2 -> DPairSpc_with_ssub_0
    9263             :       0,        // dsub_3
    9264             :       0,        // dsub_4
    9265             :       0,        // dsub_5
    9266             :       0,        // dsub_6
    9267             :       0,        // dsub_7
    9268             :       0,        // gsub_0
    9269             :       0,        // gsub_1
    9270             :       0,        // qqsub_0
    9271             :       0,        // qqsub_1
    9272             :       0,        // qsub_0
    9273             :       0,        // qsub_1
    9274             :       0,        // qsub_2
    9275             :       0,        // qsub_3
    9276             :       30,       // ssub_0 -> DPairSpc_with_ssub_0
    9277             :       30,       // ssub_1 -> DPairSpc_with_ssub_0
    9278             :       0,        // ssub_2
    9279             :       0,        // ssub_3
    9280             :       31,       // ssub_4 -> DPairSpc_with_ssub_4
    9281             :       31,       // ssub_5 -> DPairSpc_with_ssub_4
    9282             :       0,        // ssub_6
    9283             :       0,        // ssub_7
    9284             :       0,        // ssub_8
    9285             :       0,        // ssub_9
    9286             :       0,        // ssub_10
    9287             :       0,        // ssub_11
    9288             :       0,        // ssub_12
    9289             :       0,        // ssub_13
    9290             :       0,        // dsub_7_then_ssub_0
    9291             :       0,        // dsub_7_then_ssub_1
    9292             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    9293             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    9294             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    9295             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    9296             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    9297             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    9298             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9299             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    9300             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    9301             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9302             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    9303             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9304             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9305             :       0,        // ssub_6_ssub_7_dsub_5
    9306             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    9307             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    9308             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    9309             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9310             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    9311             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9312             :       0,        // dsub_5_dsub_7
    9313             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    9314             :       0,        // dsub_5_ssub_12_ssub_13
    9315             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    9316             :     },
    9317             :     {   // DPairSpc_with_ssub_4
    9318             :       31,       // dsub_0 -> DPairSpc_with_ssub_4
    9319             :       0,        // dsub_1
    9320             :       31,       // dsub_2 -> DPairSpc_with_ssub_4
    9321             :       0,        // dsub_3
    9322             :       0,        // dsub_4
    9323             :       0,        // dsub_5
    9324             :       0,        // dsub_6
    9325             :       0,        // dsub_7
    9326             :       0,        // gsub_0
    9327             :       0,        // gsub_1
    9328             :       0,        // qqsub_0
    9329             :       0,        // qqsub_1
    9330             :       0,        // qsub_0
    9331             :       0,        // qsub_1
    9332             :       0,        // qsub_2
    9333             :       0,        // qsub_3
    9334             :       31,       // ssub_0 -> DPairSpc_with_ssub_4
    9335             :       31,       // ssub_1 -> DPairSpc_with_ssub_4
    9336             :       0,        // ssub_2
    9337             :       0,        // ssub_3
    9338             :       31,       // ssub_4 -> DPairSpc_with_ssub_4
    9339             :       31,       // ssub_5 -> DPairSpc_with_ssub_4
    9340             :       0,        // ssub_6
    9341             :       0,        // ssub_7
    9342             :       0,        // ssub_8
    9343             :       0,        // ssub_9
    9344             :       0,        // ssub_10
    9345             :       0,        // ssub_11
    9346             :       0,        // ssub_12
    9347             :       0,        // ssub_13
    9348             :       0,        // dsub_7_then_ssub_0
    9349             :       0,        // dsub_7_then_ssub_1
    9350             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    9351             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    9352             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    9353             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    9354             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    9355             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    9356             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9357             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    9358             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    9359             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9360             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    9361             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9362             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9363             :       0,        // ssub_6_ssub_7_dsub_5
    9364             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    9365             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    9366             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    9367             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9368             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    9369             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9370             :       0,        // dsub_5_dsub_7
    9371             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    9372             :       0,        // dsub_5_ssub_12_ssub_13
    9373             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    9374             :     },
    9375             :     {   // DPairSpc_with_dsub_0_in_DPR_8
    9376             :       32,       // dsub_0 -> DPairSpc_with_dsub_0_in_DPR_8
    9377             :       0,        // dsub_1
    9378             :       32,       // dsub_2 -> DPairSpc_with_dsub_0_in_DPR_8
    9379             :       0,        // dsub_3
    9380             :       0,        // dsub_4
    9381             :       0,        // dsub_5
    9382             :       0,        // dsub_6
    9383             :       0,        // dsub_7
    9384             :       0,        // gsub_0
    9385             :       0,        // gsub_1
    9386             :       0,        // qqsub_0
    9387             :       0,        // qqsub_1
    9388             :       0,        // qsub_0
    9389             :       0,        // qsub_1
    9390             :       0,        // qsub_2
    9391             :       0,        // qsub_3
    9392             :       32,       // ssub_0 -> DPairSpc_with_dsub_0_in_DPR_8
    9393             :       32,       // ssub_1 -> DPairSpc_with_dsub_0_in_DPR_8
    9394             :       0,        // ssub_2
    9395             :       0,        // ssub_3
    9396             :       32,       // ssub_4 -> DPairSpc_with_dsub_0_in_DPR_8
    9397             :       32,       // ssub_5 -> DPairSpc_with_dsub_0_in_DPR_8
    9398             :       0,        // ssub_6
    9399             :       0,        // ssub_7
    9400             :       0,        // ssub_8
    9401             :       0,        // ssub_9
    9402             :       0,        // ssub_10
    9403             :       0,        // ssub_11
    9404             :       0,        // ssub_12
    9405             :       0,        // ssub_13
    9406             :       0,        // dsub_7_then_ssub_0
    9407             :       0,        // dsub_7_then_ssub_1
    9408             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    9409             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    9410             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    9411             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    9412             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    9413             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    9414             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9415             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    9416             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    9417             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9418             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    9419             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9420             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9421             :       0,        // ssub_6_ssub_7_dsub_5
    9422             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    9423             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    9424             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    9425             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9426             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    9427             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9428             :       0,        // dsub_5_dsub_7
    9429             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    9430             :       0,        // dsub_5_ssub_12_ssub_13
    9431             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    9432             :     },
    9433             :     {   // DPairSpc_with_dsub_2_in_DPR_8
    9434             :       33,       // dsub_0 -> DPairSpc_with_dsub_2_in_DPR_8
    9435             :       0,        // dsub_1
    9436             :       33,       // dsub_2 -> DPairSpc_with_dsub_2_in_DPR_8
    9437             :       0,        // dsub_3
    9438             :       0,        // dsub_4
    9439             :       0,        // dsub_5
    9440             :       0,        // dsub_6
    9441             :       0,        // dsub_7
    9442             :       0,        // gsub_0
    9443             :       0,        // gsub_1
    9444             :       0,        // qqsub_0
    9445             :       0,        // qqsub_1
    9446             :       0,        // qsub_0
    9447             :       0,        // qsub_1
    9448             :       0,        // qsub_2
    9449             :       0,        // qsub_3
    9450             :       33,       // ssub_0 -> DPairSpc_with_dsub_2_in_DPR_8
    9451             :       33,       // ssub_1 -> DPairSpc_with_dsub_2_in_DPR_8
    9452             :       0,        // ssub_2
    9453             :       0,        // ssub_3
    9454             :       33,       // ssub_4 -> DPairSpc_with_dsub_2_in_DPR_8
    9455             :       33,       // ssub_5 -> DPairSpc_with_dsub_2_in_DPR_8
    9456             :       0,        // ssub_6
    9457             :       0,        // ssub_7
    9458             :       0,        // ssub_8
    9459             :       0,        // ssub_9
    9460             :       0,        // ssub_10
    9461             :       0,        // ssub_11
    9462             :       0,        // ssub_12
    9463             :       0,        // ssub_13
    9464             :       0,        // dsub_7_then_ssub_0
    9465             :       0,        // dsub_7_then_ssub_1
    9466             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    9467             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    9468             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    9469             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    9470             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    9471             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    9472             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9473             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    9474             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    9475             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9476             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    9477             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9478             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9479             :       0,        // ssub_6_ssub_7_dsub_5
    9480             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    9481             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    9482             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    9483             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9484             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    9485             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9486             :       0,        // dsub_5_dsub_7
    9487             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    9488             :       0,        // dsub_5_ssub_12_ssub_13
    9489             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    9490             :     },
    9491             :     {   // DPair
    9492             :       34,       // dsub_0 -> DPair
    9493             :       34,       // dsub_1 -> DPair
    9494             :       0,        // dsub_2
    9495             :       0,        // dsub_3
    9496             :       0,        // dsub_4
    9497             :       0,        // dsub_5
    9498             :       0,        // dsub_6
    9499             :       0,        // dsub_7
    9500             :       0,        // gsub_0
    9501             :       0,        // gsub_1
    9502             :       0,        // qqsub_0
    9503             :       0,        // qqsub_1
    9504             :       0,        // qsub_0
    9505             :       0,        // qsub_1
    9506             :       0,        // qsub_2
    9507             :       0,        // qsub_3
    9508             :       35,       // ssub_0 -> DPair_with_ssub_0
    9509             :       35,       // ssub_1 -> DPair_with_ssub_0
    9510             :       37,       // ssub_2 -> DPair_with_ssub_2
    9511             :       37,       // ssub_3 -> DPair_with_ssub_2
    9512             :       0,        // ssub_4
    9513             :       0,        // ssub_5
    9514             :       0,        // ssub_6
    9515             :       0,        // ssub_7
    9516             :       0,        // ssub_8
    9517             :       0,        // ssub_9
    9518             :       0,        // ssub_10
    9519             :       0,        // ssub_11
    9520             :       0,        // ssub_12
    9521             :       0,        // ssub_13
    9522             :       0,        // dsub_7_then_ssub_0
    9523             :       0,        // dsub_7_then_ssub_1
    9524             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    9525             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    9526             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    9527             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    9528             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    9529             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    9530             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9531             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    9532             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    9533             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9534             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    9535             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9536             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9537             :       0,        // ssub_6_ssub_7_dsub_5
    9538             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    9539             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    9540             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    9541             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9542             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    9543             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9544             :       0,        // dsub_5_dsub_7
    9545             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    9546             :       0,        // dsub_5_ssub_12_ssub_13
    9547             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    9548             :     },
    9549             :     {   // DPair_with_ssub_0
    9550             :       35,       // dsub_0 -> DPair_with_ssub_0
    9551             :       35,       // dsub_1 -> DPair_with_ssub_0
    9552             :       0,        // dsub_2
    9553             :       0,        // dsub_3
    9554             :       0,        // dsub_4
    9555             :       0,        // dsub_5
    9556             :       0,        // dsub_6
    9557             :       0,        // dsub_7
    9558             :       0,        // gsub_0
    9559             :       0,        // gsub_1
    9560             :       0,        // qqsub_0
    9561             :       0,        // qqsub_1
    9562             :       0,        // qsub_0
    9563             :       0,        // qsub_1
    9564             :       0,        // qsub_2
    9565             :       0,        // qsub_3
    9566             :       35,       // ssub_0 -> DPair_with_ssub_0
    9567             :       35,       // ssub_1 -> DPair_with_ssub_0
    9568             :       37,       // ssub_2 -> DPair_with_ssub_2
    9569             :       37,       // ssub_3 -> DPair_with_ssub_2
    9570             :       0,        // ssub_4
    9571             :       0,        // ssub_5
    9572             :       0,        // ssub_6
    9573             :       0,        // ssub_7
    9574             :       0,        // ssub_8
    9575             :       0,        // ssub_9
    9576             :       0,        // ssub_10
    9577             :       0,        // ssub_11
    9578             :       0,        // ssub_12
    9579             :       0,        // ssub_13
    9580             :       0,        // dsub_7_then_ssub_0
    9581             :       0,        // dsub_7_then_ssub_1
    9582             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    9583             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    9584             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    9585             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    9586             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    9587             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    9588             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9589             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    9590             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    9591             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9592             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    9593             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9594             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9595             :       0,        // ssub_6_ssub_7_dsub_5
    9596             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    9597             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    9598             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    9599             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9600             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    9601             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9602             :       0,        // dsub_5_dsub_7
    9603             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    9604             :       0,        // dsub_5_ssub_12_ssub_13
    9605             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    9606             :     },
    9607             :     {   // QPR
    9608             :       36,       // dsub_0 -> QPR
    9609             :       36,       // dsub_1 -> QPR
    9610             :       0,        // dsub_2
    9611             :       0,        // dsub_3
    9612             :       0,        // dsub_4
    9613             :       0,        // dsub_5
    9614             :       0,        // dsub_6
    9615             :       0,        // dsub_7
    9616             :       0,        // gsub_0
    9617             :       0,        // gsub_1
    9618             :       0,        // qqsub_0
    9619             :       0,        // qqsub_1
    9620             :       0,        // qsub_0
    9621             :       0,        // qsub_1
    9622             :       0,        // qsub_2
    9623             :       0,        // qsub_3
    9624             :       39,       // ssub_0 -> QPR_VFP2
    9625             :       39,       // ssub_1 -> QPR_VFP2
    9626             :       39,       // ssub_2 -> QPR_VFP2
    9627             :       39,       // ssub_3 -> QPR_VFP2
    9628             :       0,        // ssub_4
    9629             :       0,        // ssub_5
    9630             :       0,        // ssub_6
    9631             :       0,        // ssub_7
    9632             :       0,        // ssub_8
    9633             :       0,        // ssub_9
    9634             :       0,        // ssub_10
    9635             :       0,        // ssub_11
    9636             :       0,        // ssub_12
    9637             :       0,        // ssub_13
    9638             :       0,        // dsub_7_then_ssub_0
    9639             :       0,        // dsub_7_then_ssub_1
    9640             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    9641             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    9642             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    9643             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    9644             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    9645             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    9646             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9647             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    9648             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    9649             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9650             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    9651             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9652             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9653             :       0,        // ssub_6_ssub_7_dsub_5
    9654             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    9655             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    9656             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    9657             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9658             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    9659             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9660             :       0,        // dsub_5_dsub_7
    9661             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    9662             :       0,        // dsub_5_ssub_12_ssub_13
    9663             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    9664             :     },
    9665             :     {   // DPair_with_ssub_2
    9666             :       37,       // dsub_0 -> DPair_with_ssub_2
    9667             :       37,       // dsub_1 -> DPair_with_ssub_2
    9668             :       0,        // dsub_2
    9669             :       0,        // dsub_3
    9670             :       0,        // dsub_4
    9671             :       0,        // dsub_5
    9672             :       0,        // dsub_6
    9673             :       0,        // dsub_7
    9674             :       0,        // gsub_0
    9675             :       0,        // gsub_1
    9676             :       0,        // qqsub_0
    9677             :       0,        // qqsub_1
    9678             :       0,        // qsub_0
    9679             :       0,        // qsub_1
    9680             :       0,        // qsub_2
    9681             :       0,        // qsub_3
    9682             :       37,       // ssub_0 -> DPair_with_ssub_2
    9683             :       37,       // ssub_1 -> DPair_with_ssub_2
    9684             :       37,       // ssub_2 -> DPair_with_ssub_2
    9685             :       37,       // ssub_3 -> DPair_with_ssub_2
    9686             :       0,        // ssub_4
    9687             :       0,        // ssub_5
    9688             :       0,        // ssub_6
    9689             :       0,        // ssub_7
    9690             :       0,        // ssub_8
    9691             :       0,        // ssub_9
    9692             :       0,        // ssub_10
    9693             :       0,        // ssub_11
    9694             :       0,        // ssub_12
    9695             :       0,        // ssub_13
    9696             :       0,        // dsub_7_then_ssub_0
    9697             :       0,        // dsub_7_then_ssub_1
    9698             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    9699             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    9700             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    9701             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    9702             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    9703             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    9704             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9705             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    9706             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    9707             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9708             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    9709             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9710             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9711             :       0,        // ssub_6_ssub_7_dsub_5
    9712             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    9713             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    9714             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    9715             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9716             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    9717             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9718             :       0,        // dsub_5_dsub_7
    9719             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    9720             :       0,        // dsub_5_ssub_12_ssub_13
    9721             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    9722             :     },
    9723             :     {   // DPair_with_dsub_0_in_DPR_8
    9724             :       38,       // dsub_0 -> DPair_with_dsub_0_in_DPR_8
    9725             :       38,       // dsub_1 -> DPair_with_dsub_0_in_DPR_8
    9726             :       0,        // dsub_2
    9727             :       0,        // dsub_3
    9728             :       0,        // dsub_4
    9729             :       0,        // dsub_5
    9730             :       0,        // dsub_6
    9731             :       0,        // dsub_7
    9732             :       0,        // gsub_0
    9733             :       0,        // gsub_1
    9734             :       0,        // qqsub_0
    9735             :       0,        // qqsub_1
    9736             :       0,        // qsub_0
    9737             :       0,        // qsub_1
    9738             :       0,        // qsub_2
    9739             :       0,        // qsub_3
    9740             :       38,       // ssub_0 -> DPair_with_dsub_0_in_DPR_8
    9741             :       38,       // ssub_1 -> DPair_with_dsub_0_in_DPR_8
    9742             :       38,       // ssub_2 -> DPair_with_dsub_0_in_DPR_8
    9743             :       38,       // ssub_3 -> DPair_with_dsub_0_in_DPR_8
    9744             :       0,        // ssub_4
    9745             :       0,        // ssub_5
    9746             :       0,        // ssub_6
    9747             :       0,        // ssub_7
    9748             :       0,        // ssub_8
    9749             :       0,        // ssub_9
    9750             :       0,        // ssub_10
    9751             :       0,        // ssub_11
    9752             :       0,        // ssub_12
    9753             :       0,        // ssub_13
    9754             :       0,        // dsub_7_then_ssub_0
    9755             :       0,        // dsub_7_then_ssub_1
    9756             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    9757             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    9758             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    9759             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    9760             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    9761             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    9762             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9763             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    9764             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    9765             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9766             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    9767             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9768             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9769             :       0,        // ssub_6_ssub_7_dsub_5
    9770             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    9771             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    9772             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    9773             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9774             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    9775             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9776             :       0,        // dsub_5_dsub_7
    9777             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    9778             :       0,        // dsub_5_ssub_12_ssub_13
    9779             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    9780             :     },
    9781             :     {   // QPR_VFP2
    9782             :       39,       // dsub_0 -> QPR_VFP2
    9783             :       39,       // dsub_1 -> QPR_VFP2
    9784             :       0,        // dsub_2
    9785             :       0,        // dsub_3
    9786             :       0,        // dsub_4
    9787             :       0,        // dsub_5
    9788             :       0,        // dsub_6
    9789             :       0,        // dsub_7
    9790             :       0,        // gsub_0
    9791             :       0,        // gsub_1
    9792             :       0,        // qqsub_0
    9793             :       0,        // qqsub_1
    9794             :       0,        // qsub_0
    9795             :       0,        // qsub_1
    9796             :       0,        // qsub_2
    9797             :       0,        // qsub_3
    9798             :       39,       // ssub_0 -> QPR_VFP2
    9799             :       39,       // ssub_1 -> QPR_VFP2
    9800             :       39,       // ssub_2 -> QPR_VFP2
    9801             :       39,       // ssub_3 -> QPR_VFP2
    9802             :       0,        // ssub_4
    9803             :       0,        // ssub_5
    9804             :       0,        // ssub_6
    9805             :       0,        // ssub_7
    9806             :       0,        // ssub_8
    9807             :       0,        // ssub_9
    9808             :       0,        // ssub_10
    9809             :       0,        // ssub_11
    9810             :       0,        // ssub_12
    9811             :       0,        // ssub_13
    9812             :       0,        // dsub_7_then_ssub_0
    9813             :       0,        // dsub_7_then_ssub_1
    9814             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    9815             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    9816             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    9817             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    9818             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    9819             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    9820             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9821             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    9822             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    9823             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9824             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    9825             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9826             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9827             :       0,        // ssub_6_ssub_7_dsub_5
    9828             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    9829             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    9830             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    9831             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9832             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    9833             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9834             :       0,        // dsub_5_dsub_7
    9835             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    9836             :       0,        // dsub_5_ssub_12_ssub_13
    9837             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    9838             :     },
    9839             :     {   // DPair_with_dsub_1_in_DPR_8
    9840             :       40,       // dsub_0 -> DPair_with_dsub_1_in_DPR_8
    9841             :       40,       // dsub_1 -> DPair_with_dsub_1_in_DPR_8
    9842             :       0,        // dsub_2
    9843             :       0,        // dsub_3
    9844             :       0,        // dsub_4
    9845             :       0,        // dsub_5
    9846             :       0,        // dsub_6
    9847             :       0,        // dsub_7
    9848             :       0,        // gsub_0
    9849             :       0,        // gsub_1
    9850             :       0,        // qqsub_0
    9851             :       0,        // qqsub_1
    9852             :       0,        // qsub_0
    9853             :       0,        // qsub_1
    9854             :       0,        // qsub_2
    9855             :       0,        // qsub_3
    9856             :       40,       // ssub_0 -> DPair_with_dsub_1_in_DPR_8
    9857             :       40,       // ssub_1 -> DPair_with_dsub_1_in_DPR_8
    9858             :       40,       // ssub_2 -> DPair_with_dsub_1_in_DPR_8
    9859             :       40,       // ssub_3 -> DPair_with_dsub_1_in_DPR_8
    9860             :       0,        // ssub_4
    9861             :       0,        // ssub_5
    9862             :       0,        // ssub_6
    9863             :       0,        // ssub_7
    9864             :       0,        // ssub_8
    9865             :       0,        // ssub_9
    9866             :       0,        // ssub_10
    9867             :       0,        // ssub_11
    9868             :       0,        // ssub_12
    9869             :       0,        // ssub_13
    9870             :       0,        // dsub_7_then_ssub_0
    9871             :       0,        // dsub_7_then_ssub_1
    9872             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    9873             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    9874             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    9875             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    9876             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    9877             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    9878             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9879             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    9880             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    9881             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9882             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    9883             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9884             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9885             :       0,        // ssub_6_ssub_7_dsub_5
    9886             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    9887             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    9888             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    9889             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9890             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    9891             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9892             :       0,        // dsub_5_dsub_7
    9893             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    9894             :       0,        // dsub_5_ssub_12_ssub_13
    9895             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    9896             :     },
    9897             :     {   // QPR_8
    9898             :       41,       // dsub_0 -> QPR_8
    9899             :       41,       // dsub_1 -> QPR_8
    9900             :       0,        // dsub_2
    9901             :       0,        // dsub_3
    9902             :       0,        // dsub_4
    9903             :       0,        // dsub_5
    9904             :       0,        // dsub_6
    9905             :       0,        // dsub_7
    9906             :       0,        // gsub_0
    9907             :       0,        // gsub_1
    9908             :       0,        // qqsub_0
    9909             :       0,        // qqsub_1
    9910             :       0,        // qsub_0
    9911             :       0,        // qsub_1
    9912             :       0,        // qsub_2
    9913             :       0,        // qsub_3
    9914             :       41,       // ssub_0 -> QPR_8
    9915             :       41,       // ssub_1 -> QPR_8
    9916             :       41,       // ssub_2 -> QPR_8
    9917             :       41,       // ssub_3 -> QPR_8
    9918             :       0,        // ssub_4
    9919             :       0,        // ssub_5
    9920             :       0,        // ssub_6
    9921             :       0,        // ssub_7
    9922             :       0,        // ssub_8
    9923             :       0,        // ssub_9
    9924             :       0,        // ssub_10
    9925             :       0,        // ssub_11
    9926             :       0,        // ssub_12
    9927             :       0,        // ssub_13
    9928             :       0,        // dsub_7_then_ssub_0
    9929             :       0,        // dsub_7_then_ssub_1
    9930             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5
    9931             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    9932             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    9933             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    9934             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
    9935             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    9936             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9937             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    9938             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    9939             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9940             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    9941             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9942             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9943             :       0,        // ssub_6_ssub_7_dsub_5
    9944             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    9945             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
    9946             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
    9947             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9948             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
    9949             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    9950             :       0,        // dsub_5_dsub_7
    9951             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
    9952             :       0,        // dsub_5_ssub_12_ssub_13
    9953             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    9954             :     },
    9955             :     {   // DTriple
    9956             :       42,       // dsub_0 -> DTriple
    9957             :       42,       // dsub_1 -> DTriple
    9958             :       42,       // dsub_2 -> DTriple
    9959             :       0,        // dsub_3
    9960             :       0,        // dsub_4
    9961             :       0,        // dsub_5
    9962             :       0,        // dsub_6
    9963             :       0,        // dsub_7
    9964             :       0,        // gsub_0
    9965             :       0,        // gsub_1
    9966             :       0,        // qqsub_0
    9967             :       0,        // qqsub_1
    9968             :       42,       // qsub_0 -> DTriple
    9969             :       0,        // qsub_1
    9970             :       0,        // qsub_2
    9971             :       0,        // qsub_3
    9972             :       45,       // ssub_0 -> DTriple_with_ssub_0
    9973             :       45,       // ssub_1 -> DTriple_with_ssub_0
    9974             :       47,       // ssub_2 -> DTriple_with_ssub_2
    9975             :       47,       // ssub_3 -> DTriple_with_ssub_2
    9976             :       50,       // ssub_4 -> DTriple_with_ssub_4
    9977             :       50,       // ssub_5 -> DTriple_with_ssub_4
    9978             :       0,        // ssub_6
    9979             :       0,        // ssub_7
    9980             :       0,        // ssub_8
    9981             :       0,        // ssub_9
    9982             :       0,        // ssub_10
    9983             :       0,        // ssub_11
    9984             :       0,        // ssub_12
    9985             :       0,        // ssub_13
    9986             :       0,        // dsub_7_then_ssub_0
    9987             :       0,        // dsub_7_then_ssub_1
    9988             :       42,       // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple
    9989             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    9990             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
    9991             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    9992             :       42,       // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple
    9993             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    9994             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    9995             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    9996             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    9997             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    9998             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
    9999             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10000             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10001             :       0,        // ssub_6_ssub_7_dsub_5
   10002             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
   10003             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
   10004             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
   10005             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10006             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
   10007             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10008             :       0,        // dsub_5_dsub_7
   10009             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
   10010             :       0,        // dsub_5_ssub_12_ssub_13
   10011             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
   10012             :     },
   10013             :     {   // DTripleSpc
   10014             :       43,       // dsub_0 -> DTripleSpc
   10015             :       0,        // dsub_1
   10016             :       43,       // dsub_2 -> DTripleSpc
   10017             :       0,        // dsub_3
   10018             :       43,       // dsub_4 -> DTripleSpc
   10019             :       0,        // dsub_5
   10020             :       0,        // dsub_6
   10021             :       0,        // dsub_7
   10022             :       0,        // gsub_0
   10023             :       0,        // gsub_1
   10024             :       0,        // qqsub_0
   10025             :       0,        // qqsub_1
   10026             :       0,        // qsub_0
   10027             :       0,        // qsub_1
   10028             :       0,        // qsub_2
   10029             :       0,        // qsub_3
   10030             :       44,       // ssub_0 -> DTripleSpc_with_ssub_0
   10031             :       44,       // ssub_1 -> DTripleSpc_with_ssub_0
   10032             :       0,        // ssub_2
   10033             :       0,        // ssub_3
   10034             :       49,       // ssub_4 -> DTripleSpc_with_ssub_4
   10035             :       49,       // ssub_5 -> DTripleSpc_with_ssub_4
   10036             :       0,        // ssub_6
   10037             :       0,        // ssub_7
   10038             :       51,       // ssub_8 -> DTripleSpc_with_ssub_8
   10039             :       51,       // ssub_9 -> DTripleSpc_with_ssub_8
   10040             :       0,        // ssub_10
   10041             :       0,        // ssub_11
   10042             :       0,        // ssub_12
   10043             :       0,        // ssub_13
   10044             :       0,        // dsub_7_then_ssub_0
   10045             :       0,        // dsub_7_then_ssub_1
   10046             :       43,       // ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc
   10047             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
   10048             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
   10049             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
   10050             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
   10051             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
   10052             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10053             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
   10054             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
   10055             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10056             :       43,       // ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc
   10057             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10058             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10059             :       0,        // ssub_6_ssub_7_dsub_5
   10060             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
   10061             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
   10062             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
   10063             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10064             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
   10065             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10066             :       0,        // dsub_5_dsub_7
   10067             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
   10068             :       0,        // dsub_5_ssub_12_ssub_13
   10069             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
   10070             :     },
   10071             :     {   // DTripleSpc_with_ssub_0
   10072             :       44,       // dsub_0 -> DTripleSpc_with_ssub_0
   10073             :       0,        // dsub_1
   10074             :       44,       // dsub_2 -> DTripleSpc_with_ssub_0
   10075             :       0,        // dsub_3
   10076             :       44,       // dsub_4 -> DTripleSpc_with_ssub_0
   10077             :       0,        // dsub_5
   10078             :       0,        // dsub_6
   10079             :       0,        // dsub_7
   10080             :       0,        // gsub_0
   10081             :       0,        // gsub_1
   10082             :       0,        // qqsub_0
   10083             :       0,        // qqsub_1
   10084             :       0,        // qsub_0
   10085             :       0,        // qsub_1
   10086             :       0,        // qsub_2
   10087             :       0,        // qsub_3
   10088             :       44,       // ssub_0 -> DTripleSpc_with_ssub_0
   10089             :       44,       // ssub_1 -> DTripleSpc_with_ssub_0
   10090             :       0,        // ssub_2
   10091             :       0,        // ssub_3
   10092             :       49,       // ssub_4 -> DTripleSpc_with_ssub_4
   10093             :       49,       // ssub_5 -> DTripleSpc_with_ssub_4
   10094             :       0,        // ssub_6
   10095             :       0,        // ssub_7
   10096             :       51,       // ssub_8 -> DTripleSpc_with_ssub_8
   10097             :       51,       // ssub_9 -> DTripleSpc_with_ssub_8
   10098             :       0,        // ssub_10
   10099             :       0,        // ssub_11
   10100             :       0,        // ssub_12
   10101             :       0,        // ssub_13
   10102             :       0,        // dsub_7_then_ssub_0
   10103             :       0,        // dsub_7_then_ssub_1
   10104             :       44,       // ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_ssub_0
   10105             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
   10106             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
   10107             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
   10108             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
   10109             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
   10110             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10111             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
   10112             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
   10113             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10114             :       44,       // ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_ssub_0
   10115             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10116             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10117             :       0,        // ssub_6_ssub_7_dsub_5
   10118             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
   10119             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
   10120             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
   10121             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10122             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
   10123             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10124             :       0,        // dsub_5_dsub_7
   10125             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
   10126             :       0,        // dsub_5_ssub_12_ssub_13
   10127             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
   10128             :     },
   10129             :     {   // DTriple_with_ssub_0
   10130             :       45,       // dsub_0 -> DTriple_with_ssub_0
   10131             :       45,       // dsub_1 -> DTriple_with_ssub_0
   10132             :       45,       // dsub_2 -> DTriple_with_ssub_0
   10133             :       0,        // dsub_3
   10134             :       0,        // dsub_4
   10135             :       0,        // dsub_5
   10136             :       0,        // dsub_6
   10137             :       0,        // dsub_7
   10138             :       0,        // gsub_0
   10139             :       0,        // gsub_1
   10140             :       0,        // qqsub_0
   10141             :       0,        // qqsub_1
   10142             :       45,       // qsub_0 -> DTriple_with_ssub_0
   10143             :       0,        // qsub_1
   10144             :       0,        // qsub_2
   10145             :       0,        // qsub_3
   10146             :       45,       // ssub_0 -> DTriple_with_ssub_0
   10147             :       45,       // ssub_1 -> DTriple_with_ssub_0
   10148             :       47,       // ssub_2 -> DTriple_with_ssub_2
   10149             :       47,       // ssub_3 -> DTriple_with_ssub_2
   10150             :       50,       // ssub_4 -> DTriple_with_ssub_4
   10151             :       50,       // ssub_5 -> DTriple_with_ssub_4
   10152             :       0,        // ssub_6
   10153             :       0,        // ssub_7
   10154             :       0,        // ssub_8
   10155             :       0,        // ssub_9
   10156             :       0,        // ssub_10
   10157             :       0,        // ssub_11
   10158             :       0,        // ssub_12
   10159             :       0,        // ssub_13
   10160             :       0,        // dsub_7_then_ssub_0
   10161             :       0,        // dsub_7_then_ssub_1
   10162             :       45,       // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_0
   10163             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
   10164             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
   10165             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
   10166             :       45,       // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_0
   10167             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
   10168             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10169             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
   10170             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
   10171             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10172             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
   10173             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10174             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10175             :       0,        // ssub_6_ssub_7_dsub_5
   10176             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
   10177             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
   10178             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
   10179             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10180             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
   10181             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10182             :       0,        // dsub_5_dsub_7
   10183             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
   10184             :       0,        // dsub_5_ssub_12_ssub_13
   10185             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
   10186             :     },
   10187             :     {   // DTriple_with_qsub_0_in_QPR
   10188             :       46,       // dsub_0 -> DTriple_with_qsub_0_in_QPR
   10189             :       46,       // dsub_1 -> DTriple_with_qsub_0_in_QPR
   10190             :       46,       // dsub_2 -> DTriple_with_qsub_0_in_QPR
   10191             :       0,        // dsub_3
   10192             :       0,        // dsub_4
   10193             :       0,        // dsub_5
   10194             :       0,        // dsub_6
   10195             :       0,        // dsub_7
   10196             :       0,        // gsub_0
   10197             :       0,        // gsub_1
   10198             :       0,        // qqsub_0
   10199             :       0,        // qqsub_1
   10200             :       46,       // qsub_0 -> DTriple_with_qsub_0_in_QPR
   10201             :       0,        // qsub_1
   10202             :       0,        // qsub_2
   10203             :       0,        // qsub_3
   10204             :       54,       // ssub_0 -> DTriple_with_qsub_0_in_QPR_VFP2
   10205             :       54,       // ssub_1 -> DTriple_with_qsub_0_in_QPR_VFP2
   10206             :       54,       // ssub_2 -> DTriple_with_qsub_0_in_QPR_VFP2
   10207             :       54,       // ssub_3 -> DTriple_with_qsub_0_in_QPR_VFP2
   10208             :       58,       // ssub_4 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
   10209             :       58,       // ssub_5 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
   10210             :       0,        // ssub_6
   10211             :       0,        // ssub_7
   10212             :       0,        // ssub_8
   10213             :       0,        // ssub_9
   10214             :       0,        // ssub_10
   10215             :       0,        // ssub_11
   10216             :       0,        // ssub_12
   10217             :       0,        // ssub_13
   10218             :       0,        // dsub_7_then_ssub_0
   10219             :       0,        // dsub_7_then_ssub_1
   10220             :       46,       // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_QPR
   10221             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
   10222             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
   10223             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
   10224             :       46,       // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_QPR
   10225             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
   10226             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10227             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
   10228             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
   10229             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10230             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
   10231             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10232             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10233             :       0,        // ssub_6_ssub_7_dsub_5
   10234             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
   10235             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
   10236             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
   10237             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10238             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
   10239             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10240             :       0,        // dsub_5_dsub_7
   10241             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
   10242             :       0,        // dsub_5_ssub_12_ssub_13
   10243             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
   10244             :     },
   10245             :     {   // DTriple_with_ssub_2
   10246             :       47,       // dsub_0 -> DTriple_with_ssub_2
   10247             :       47,       // dsub_1 -> DTriple_with_ssub_2
   10248             :       47,       // dsub_2 -> DTriple_with_ssub_2
   10249             :       0,        // dsub_3
   10250             :       0,        // dsub_4
   10251             :       0,        // dsub_5
   10252             :       0,        // dsub_6
   10253             :       0,        // dsub_7
   10254             :       0,        // gsub_0
   10255             :       0,        // gsub_1
   10256             :       0,        // qqsub_0
   10257             :       0,        // qqsub_1
   10258             :       47,       // qsub_0 -> DTriple_with_ssub_2
   10259             :       0,        // qsub_1
   10260             :       0,        // qsub_2
   10261             :       0,        // qsub_3
   10262             :       47,       // ssub_0 -> DTriple_with_ssub_2
   10263             :       47,       // ssub_1 -> DTriple_with_ssub_2
   10264             :       47,       // ssub_2 -> DTriple_with_ssub_2
   10265             :       47,       // ssub_3 -> DTriple_with_ssub_2
   10266             :       50,       // ssub_4 -> DTriple_with_ssub_4
   10267             :       50,       // ssub_5 -> DTriple_with_ssub_4
   10268             :       0,        // ssub_6
   10269             :       0,        // ssub_7
   10270             :       0,        // ssub_8
   10271             :       0,        // ssub_9
   10272             :       0,        // ssub_10
   10273             :       0,        // ssub_11
   10274             :       0,        // ssub_12
   10275             :       0,        // ssub_13
   10276             :       0,        // dsub_7_then_ssub_0
   10277             :       0,        // dsub_7_then_ssub_1
   10278             :       47,       // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_2
   10279             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
   10280             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
   10281             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
   10282             :       47,       // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_2
   10283             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
   10284             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10285             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
   10286             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
   10287             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10288             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
   10289             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10290             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10291             :       0,        // ssub_6_ssub_7_dsub_5
   10292             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
   10293             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
   10294             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
   10295             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10296             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
   10297             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10298             :       0,        // dsub_5_dsub_7
   10299             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
   10300             :       0,        // dsub_5_ssub_12_ssub_13
   10301             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
   10302             :     },
   10303             :     {   // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
   10304             :       48,       // dsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
   10305             :       48,       // dsub_1 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
   10306             :       48,       // dsub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
   10307             :       0,        // dsub_3
   10308             :       0,        // dsub_4
   10309             :       0,        // dsub_5
   10310             :       0,        // dsub_6
   10311             :       0,        // dsub_7
   10312             :       0,        // gsub_0
   10313             :       0,        // gsub_1
   10314             :       0,        // qqsub_0
   10315             :       0,        // qqsub_1
   10316             :       48,       // qsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
   10317             :       0,        // qsub_1
   10318             :       0,        // qsub_2
   10319             :       0,        // qsub_3
   10320             :       55,       // ssub_0 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
   10321             :       55,       // ssub_1 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
   10322             :       57,       // ssub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
   10323             :       57,       // ssub_3 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
   10324             :       57,       // ssub_4 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
   10325             :       57,       // ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
   10326             :       0,        // ssub_6
   10327             :       0,        // ssub_7
   10328             :       0,        // ssub_8
   10329             :       0,        // ssub_9
   10330             :       0,        // ssub_10
   10331             :       0,        // ssub_11
   10332             :       0,        // ssub_12
   10333             :       0,        // ssub_13
   10334             :       0,        // dsub_7_then_ssub_0
   10335             :       0,        // dsub_7_then_ssub_1
   10336             :       48,       // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
   10337             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
   10338             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
   10339             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
   10340             :       48,       // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
   10341             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
   10342             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10343             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
   10344             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
   10345             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10346             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
   10347             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10348             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10349             :       0,        // ssub_6_ssub_7_dsub_5
   10350             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
   10351             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
   10352             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
   10353             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10354             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
   10355             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10356             :       0,        // dsub_5_dsub_7
   10357             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
   10358             :       0,        // dsub_5_ssub_12_ssub_13
   10359             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
   10360             :     },
   10361             :     {   // DTripleSpc_with_ssub_4
   10362             :       49,       // dsub_0 -> DTripleSpc_with_ssub_4
   10363             :       0,        // dsub_1
   10364             :       49,       // dsub_2 -> DTripleSpc_with_ssub_4
   10365             :       0,        // dsub_3
   10366             :       49,       // dsub_4 -> DTripleSpc_with_ssub_4
   10367             :       0,        // dsub_5
   10368             :       0,        // dsub_6
   10369             :       0,        // dsub_7
   10370             :       0,        // gsub_0
   10371             :       0,        // gsub_1
   10372             :       0,        // qqsub_0
   10373             :       0,        // qqsub_1
   10374             :       0,        // qsub_0
   10375             :       0,        // qsub_1
   10376             :       0,        // qsub_2
   10377             :       0,        // qsub_3
   10378             :       49,       // ssub_0 -> DTripleSpc_with_ssub_4
   10379             :       49,       // ssub_1 -> DTripleSpc_with_ssub_4
   10380             :       0,        // ssub_2
   10381             :       0,        // ssub_3
   10382             :       49,       // ssub_4 -> DTripleSpc_with_ssub_4
   10383             :       49,       // ssub_5 -> DTripleSpc_with_ssub_4
   10384             :       0,        // ssub_6
   10385             :       0,        // ssub_7
   10386             :       51,       // ssub_8 -> DTripleSpc_with_ssub_8
   10387             :       51,       // ssub_9 -> DTripleSpc_with_ssub_8
   10388             :       0,        // ssub_10
   10389             :       0,        // ssub_11
   10390             :       0,        // ssub_12
   10391             :       0,        // ssub_13
   10392             :       0,        // dsub_7_then_ssub_0
   10393             :       0,        // dsub_7_then_ssub_1
   10394             :       49,       // ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_ssub_4
   10395             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
   10396             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
   10397             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
   10398             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
   10399             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
   10400             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10401             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
   10402             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
   10403             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10404             :       49,       // ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_ssub_4
   10405             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10406             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10407             :       0,        // ssub_6_ssub_7_dsub_5
   10408             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
   10409             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
   10410             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
   10411             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10412             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
   10413             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10414             :       0,        // dsub_5_dsub_7
   10415             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
   10416             :       0,        // dsub_5_ssub_12_ssub_13
   10417             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
   10418             :     },
   10419             :     {   // DTriple_with_ssub_4
   10420             :       50,       // dsub_0 -> DTriple_with_ssub_4
   10421             :       50,       // dsub_1 -> DTriple_with_ssub_4
   10422             :       50,       // dsub_2 -> DTriple_with_ssub_4
   10423             :       0,        // dsub_3
   10424             :       0,        // dsub_4
   10425             :       0,        // dsub_5
   10426             :       0,        // dsub_6
   10427             :       0,        // dsub_7
   10428             :       0,        // gsub_0
   10429             :       0,        // gsub_1
   10430             :       0,        // qqsub_0
   10431             :       0,        // qqsub_1
   10432             :       50,       // qsub_0 -> DTriple_with_ssub_4
   10433             :       0,        // qsub_1
   10434             :       0,        // qsub_2
   10435             :       0,        // qsub_3
   10436             :       50,       // ssub_0 -> DTriple_with_ssub_4
   10437             :       50,       // ssub_1 -> DTriple_with_ssub_4
   10438             :       50,       // ssub_2 -> DTriple_with_ssub_4
   10439             :       50,       // ssub_3 -> DTriple_with_ssub_4
   10440             :       50,       // ssub_4 -> DTriple_with_ssub_4
   10441             :       50,       // ssub_5 -> DTriple_with_ssub_4
   10442             :       0,        // ssub_6
   10443             :       0,        // ssub_7
   10444             :       0,        // ssub_8
   10445             :       0,        // ssub_9
   10446             :       0,        // ssub_10
   10447             :       0,        // ssub_11
   10448             :       0,        // ssub_12
   10449             :       0,        // ssub_13
   10450             :       0,        // dsub_7_then_ssub_0
   10451             :       0,        // dsub_7_then_ssub_1
   10452             :       50,       // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_4
   10453             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
   10454             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
   10455             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
   10456             :       50,       // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_4
   10457             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
   10458             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10459             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
   10460             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
   10461             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10462             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
   10463             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10464             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10465             :       0,        // ssub_6_ssub_7_dsub_5
   10466             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
   10467             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
   10468             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
   10469             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10470             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
   10471             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10472             :       0,        // dsub_5_dsub_7
   10473             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
   10474             :       0,        // dsub_5_ssub_12_ssub_13
   10475             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
   10476             :     },
   10477             :     {   // DTripleSpc_with_ssub_8
   10478             :       51,       // dsub_0 -> DTripleSpc_with_ssub_8
   10479             :       0,        // dsub_1
   10480             :       51,       // dsub_2 -> DTripleSpc_with_ssub_8
   10481             :       0,        // dsub_3
   10482             :       51,       // dsub_4 -> DTripleSpc_with_ssub_8
   10483             :       0,        // dsub_5
   10484             :       0,        // dsub_6
   10485             :       0,        // dsub_7
   10486             :       0,        // gsub_0
   10487             :       0,        // gsub_1
   10488             :       0,        // qqsub_0
   10489             :       0,        // qqsub_1
   10490             :       0,        // qsub_0
   10491             :       0,        // qsub_1
   10492             :       0,        // qsub_2
   10493             :       0,        // qsub_3
   10494             :       51,       // ssub_0 -> DTripleSpc_with_ssub_8
   10495             :       51,       // ssub_1 -> DTripleSpc_with_ssub_8
   10496             :       0,        // ssub_2
   10497             :       0,        // ssub_3
   10498             :       51,       // ssub_4 -> DTripleSpc_with_ssub_8
   10499             :       51,       // ssub_5 -> DTripleSpc_with_ssub_8
   10500             :       0,        // ssub_6
   10501             :       0,        // ssub_7
   10502             :       51,       // ssub_8 -> DTripleSpc_with_ssub_8
   10503             :       51,       // ssub_9 -> DTripleSpc_with_ssub_8
   10504             :       0,        // ssub_10
   10505             :       0,        // ssub_11
   10506             :       0,        // ssub_12
   10507             :       0,        // ssub_13
   10508             :       0,        // dsub_7_then_ssub_0
   10509             :       0,        // dsub_7_then_ssub_1
   10510             :       51,       // ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_ssub_8
   10511             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
   10512             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
   10513             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
   10514             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
   10515             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
   10516             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10517             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
   10518             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
   10519             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10520             :       51,       // ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_ssub_8
   10521             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10522             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10523             :       0,        // ssub_6_ssub_7_dsub_5
   10524             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
   10525             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
   10526             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
   10527             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10528             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
   10529             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10530             :       0,        // dsub_5_dsub_7
   10531             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
   10532             :       0,        // dsub_5_ssub_12_ssub_13
   10533             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
   10534             :     },
   10535             :     {   // DTripleSpc_with_dsub_0_in_DPR_8
   10536             :       52,       // dsub_0 -> DTripleSpc_with_dsub_0_in_DPR_8
   10537             :       0,        // dsub_1
   10538             :       52,       // dsub_2 -> DTripleSpc_with_dsub_0_in_DPR_8
   10539             :       0,        // dsub_3
   10540             :       52,       // dsub_4 -> DTripleSpc_with_dsub_0_in_DPR_8
   10541             :       0,        // dsub_5
   10542             :       0,        // dsub_6
   10543             :       0,        // dsub_7
   10544             :       0,        // gsub_0
   10545             :       0,        // gsub_1
   10546             :       0,        // qqsub_0
   10547             :       0,        // qqsub_1
   10548             :       0,        // qsub_0
   10549             :       0,        // qsub_1
   10550             :       0,        // qsub_2
   10551             :       0,        // qsub_3
   10552             :       52,       // ssub_0 -> DTripleSpc_with_dsub_0_in_DPR_8
   10553             :       52,       // ssub_1 -> DTripleSpc_with_dsub_0_in_DPR_8
   10554             :       0,        // ssub_2
   10555             :       0,        // ssub_3
   10556             :       52,       // ssub_4 -> DTripleSpc_with_dsub_0_in_DPR_8
   10557             :       52,       // ssub_5 -> DTripleSpc_with_dsub_0_in_DPR_8
   10558             :       0,        // ssub_6
   10559             :       0,        // ssub_7
   10560             :       52,       // ssub_8 -> DTripleSpc_with_dsub_0_in_DPR_8
   10561             :       52,       // ssub_9 -> DTripleSpc_with_dsub_0_in_DPR_8
   10562             :       0,        // ssub_10
   10563             :       0,        // ssub_11
   10564             :       0,        // ssub_12
   10565             :       0,        // ssub_13
   10566             :       0,        // dsub_7_then_ssub_0
   10567             :       0,        // dsub_7_then_ssub_1
   10568             :       52,       // ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_dsub_0_in_DPR_8
   10569             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
   10570             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
   10571             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
   10572             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
   10573             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
   10574             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10575             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
   10576             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
   10577             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10578             :       52,       // ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_dsub_0_in_DPR_8
   10579             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10580             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10581             :       0,        // ssub_6_ssub_7_dsub_5
   10582             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
   10583             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
   10584             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
   10585             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10586             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
   10587             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10588             :       0,        // dsub_5_dsub_7
   10589             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
   10590             :       0,        // dsub_5_ssub_12_ssub_13
   10591             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
   10592             :     },
   10593             :     {   // DTriple_with_dsub_0_in_DPR_8
   10594             :       53,       // dsub_0 -> DTriple_with_dsub_0_in_DPR_8
   10595             :       53,       // dsub_1 -> DTriple_with_dsub_0_in_DPR_8
   10596             :       53,       // dsub_2 -> DTriple_with_dsub_0_in_DPR_8
   10597             :       0,        // dsub_3
   10598             :       0,        // dsub_4
   10599             :       0,        // dsub_5
   10600             :       0,        // dsub_6
   10601             :       0,        // dsub_7
   10602             :       0,        // gsub_0
   10603             :       0,        // gsub_1
   10604             :       0,        // qqsub_0
   10605             :       0,        // qqsub_1
   10606             :       53,       // qsub_0 -> DTriple_with_dsub_0_in_DPR_8
   10607             :       0,        // qsub_1
   10608             :       0,        // qsub_2
   10609             :       0,        // qsub_3
   10610             :       53,       // ssub_0 -> DTriple_with_dsub_0_in_DPR_8
   10611             :       53,       // ssub_1 -> DTriple_with_dsub_0_in_DPR_8
   10612             :       53,       // ssub_2 -> DTriple_with_dsub_0_in_DPR_8
   10613             :       53,       // ssub_3 -> DTriple_with_dsub_0_in_DPR_8
   10614             :       53,       // ssub_4 -> DTriple_with_dsub_0_in_DPR_8
   10615             :       53,       // ssub_5 -> DTriple_with_dsub_0_in_DPR_8
   10616             :       0,        // ssub_6
   10617             :       0,        // ssub_7
   10618             :       0,        // ssub_8
   10619             :       0,        // ssub_9
   10620             :       0,        // ssub_10
   10621             :       0,        // ssub_11
   10622             :       0,        // ssub_12
   10623             :       0,        // ssub_13
   10624             :       0,        // dsub_7_then_ssub_0
   10625             :       0,        // dsub_7_then_ssub_1
   10626             :       53,       // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_dsub_0_in_DPR_8
   10627             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
   10628             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
   10629             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
   10630             :       53,       // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_dsub_0_in_DPR_8
   10631             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
   10632             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10633             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
   10634             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
   10635             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10636             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
   10637             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10638             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10639             :       0,        // ssub_6_ssub_7_dsub_5
   10640             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
   10641             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
   10642             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
   10643             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10644             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
   10645             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10646             :       0,        // dsub_5_dsub_7
   10647             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
   10648             :       0,        // dsub_5_ssub_12_ssub_13
   10649             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
   10650             :     },
   10651             :     {   // DTriple_with_qsub_0_in_QPR_VFP2
   10652             :       54,       // dsub_0 -> DTriple_with_qsub_0_in_QPR_VFP2
   10653             :       54,       // dsub_1 -> DTriple_with_qsub_0_in_QPR_VFP2
   10654             :       54,       // dsub_2 -> DTriple_with_qsub_0_in_QPR_VFP2
   10655             :       0,        // dsub_3
   10656             :       0,        // dsub_4
   10657             :       0,        // dsub_5
   10658             :       0,        // dsub_6
   10659             :       0,        // dsub_7
   10660             :       0,        // gsub_0
   10661             :       0,        // gsub_1
   10662             :       0,        // qqsub_0
   10663             :       0,        // qqsub_1
   10664             :       54,       // qsub_0 -> DTriple_with_qsub_0_in_QPR_VFP2
   10665             :       0,        // qsub_1
   10666             :       0,        // qsub_2
   10667             :       0,        // qsub_3
   10668             :       54,       // ssub_0 -> DTriple_with_qsub_0_in_QPR_VFP2
   10669             :       54,       // ssub_1 -> DTriple_with_qsub_0_in_QPR_VFP2
   10670             :       54,       // ssub_2 -> DTriple_with_qsub_0_in_QPR_VFP2
   10671             :       54,       // ssub_3 -> DTriple_with_qsub_0_in_QPR_VFP2
   10672             :       58,       // ssub_4 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
   10673             :       58,       // ssub_5 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
   10674             :       0,        // ssub_6
   10675             :       0,        // ssub_7
   10676             :       0,        // ssub_8
   10677             :       0,        // ssub_9
   10678             :       0,        // ssub_10
   10679             :       0,        // ssub_11
   10680             :       0,        // ssub_12
   10681             :       0,        // ssub_13
   10682             :       0,        // dsub_7_then_ssub_0
   10683             :       0,        // dsub_7_then_ssub_1
   10684             :       54,       // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_QPR_VFP2
   10685             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
   10686             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
   10687             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
   10688             :       54,       // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_QPR_VFP2
   10689             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
   10690             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10691             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
   10692             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
   10693             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10694             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
   10695             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10696             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10697             :       0,        // ssub_6_ssub_7_dsub_5
   10698             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
   10699             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
   10700             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
   10701             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10702             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
   10703             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10704             :       0,        // dsub_5_dsub_7
   10705             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
   10706             :       0,        // dsub_5_ssub_12_ssub_13
   10707             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
   10708             :     },
   10709             :     {   // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
   10710             :       55,       // dsub_0 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
   10711             :       55,       // dsub_1 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
   10712             :       55,       // dsub_2 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
   10713             :       0,        // dsub_3
   10714             :       0,        // dsub_4
   10715             :       0,        // dsub_5
   10716             :       0,        // dsub_6
   10717             :       0,        // dsub_7
   10718             :       0,        // gsub_0
   10719             :       0,        // gsub_1
   10720             :       0,        // qqsub_0
   10721             :       0,        // qqsub_1
   10722             :       55,       // qsub_0 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
   10723             :       0,        // qsub_1
   10724             :       0,        // qsub_2
   10725             :       0,        // qsub_3
   10726             :       55,       // ssub_0 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
   10727             :       55,       // ssub_1 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
   10728             :       57,       // ssub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
   10729             :       57,       // ssub_3 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
   10730             :       57,       // ssub_4 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
   10731             :       57,       // ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
   10732             :       0,        // ssub_6
   10733             :       0,        // ssub_7
   10734             :       0,        // ssub_8
   10735             :       0,        // ssub_9
   10736             :       0,        // ssub_10
   10737             :       0,        // ssub_11
   10738             :       0,        // ssub_12
   10739             :       0,        // ssub_13
   10740             :       0,        // dsub_7_then_ssub_0
   10741             :       0,        // dsub_7_then_ssub_1
   10742             :       55,       // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
   10743             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
   10744             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
   10745             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
   10746             :       55,       // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
   10747             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
   10748             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10749             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
   10750             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
   10751             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10752             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
   10753             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10754             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10755             :       0,        // ssub_6_ssub_7_dsub_5
   10756             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
   10757             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
   10758             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
   10759             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10760             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
   10761             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10762             :       0,        // dsub_5_dsub_7
   10763             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
   10764             :       0,        // dsub_5_ssub_12_ssub_13
   10765             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
   10766             :     },
   10767             :     {   // DTriple_with_dsub_1_in_DPR_8
   10768             :       56,       // dsub_0 -> DTriple_with_dsub_1_in_DPR_8
   10769             :       56,       // dsub_1 -> DTriple_with_dsub_1_in_DPR_8
   10770             :       56,       // dsub_2 -> DTriple_with_dsub_1_in_DPR_8
   10771             :       0,        // dsub_3
   10772             :       0,        // dsub_4
   10773             :       0,        // dsub_5
   10774             :       0,        // dsub_6
   10775             :       0,        // dsub_7
   10776             :       0,        // gsub_0
   10777             :       0,        // gsub_1
   10778             :       0,        // qqsub_0
   10779             :       0,        // qqsub_1
   10780             :       56,       // qsub_0 -> DTriple_with_dsub_1_in_DPR_8
   10781             :       0,        // qsub_1
   10782             :       0,        // qsub_2
   10783             :       0,        // qsub_3
   10784             :       56,       // ssub_0 -> DTriple_with_dsub_1_in_DPR_8
   10785             :       56,       // ssub_1 -> DTriple_with_dsub_1_in_DPR_8
   10786             :       56,       // ssub_2 -> DTriple_with_dsub_1_in_DPR_8
   10787             :       56,       // ssub_3 -> DTriple_with_dsub_1_in_DPR_8
   10788             :       56,       // ssub_4 -> DTriple_with_dsub_1_in_DPR_8
   10789             :       56,       // ssub_5 -> DTriple_with_dsub_1_in_DPR_8
   10790             :       0,        // ssub_6
   10791             :       0,        // ssub_7
   10792             :       0,        // ssub_8
   10793             :       0,        // ssub_9
   10794             :       0,        // ssub_10
   10795             :       0,        // ssub_11
   10796             :       0,        // ssub_12
   10797             :       0,        // ssub_13
   10798             :       0,        // dsub_7_then_ssub_0
   10799             :       0,        // dsub_7_then_ssub_1
   10800             :       56,       // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_dsub_1_in_DPR_8
   10801             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
   10802             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
   10803             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
   10804             :       56,       // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_dsub_1_in_DPR_8
   10805             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
   10806             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10807             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
   10808             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
   10809             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10810             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
   10811             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10812             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10813             :       0,        // ssub_6_ssub_7_dsub_5
   10814             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
   10815             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
   10816             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
   10817             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10818             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
   10819             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10820             :       0,        // dsub_5_dsub_7
   10821             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
   10822             :       0,        // dsub_5_ssub_12_ssub_13
   10823             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
   10824             :     },
   10825             :     {   // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
   10826             :       57,       // dsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
   10827             :       57,       // dsub_1 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
   10828             :       57,       // dsub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
   10829             :       0,        // dsub_3
   10830             :       0,        // dsub_4
   10831             :       0,        // dsub_5
   10832             :       0,        // dsub_6
   10833             :       0,        // dsub_7
   10834             :       0,        // gsub_0
   10835             :       0,        // gsub_1
   10836             :       0,        // qqsub_0
   10837             :       0,        // qqsub_1
   10838             :       57,       // qsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
   10839             :       0,        // qsub_1
   10840             :       0,        // qsub_2
   10841             :       0,        // qsub_3
   10842             :       57,       // ssub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
   10843             :       57,       // ssub_1 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
   10844             :       57,       // ssub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
   10845             :       57,       // ssub_3 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
   10846             :       57,       // ssub_4 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
   10847             :       57,       // ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
   10848             :       0,        // ssub_6
   10849             :       0,        // ssub_7
   10850             :       0,        // ssub_8
   10851             :       0,        // ssub_9
   10852             :       0,        // ssub_10
   10853             :       0,        // ssub_11
   10854             :       0,        // ssub_12
   10855             :       0,        // ssub_13
   10856             :       0,        // dsub_7_then_ssub_0
   10857             :       0,        // dsub_7_then_ssub_1
   10858             :       57,       // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
   10859             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
   10860             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
   10861             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
   10862             :       57,       // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
   10863             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
   10864             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10865             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
   10866             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
   10867             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10868             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
   10869             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10870             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10871             :       0,        // ssub_6_ssub_7_dsub_5
   10872             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
   10873             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
   10874             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
   10875             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10876             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
   10877             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10878             :       0,        // dsub_5_dsub_7
   10879             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
   10880             :       0,        // dsub_5_ssub_12_ssub_13
   10881             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
   10882             :     },
   10883             :     {   // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
   10884             :       58,       // dsub_0 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
   10885             :       58,       // dsub_1 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
   10886             :       58,       // dsub_2 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
   10887             :       0,        // dsub_3
   10888             :       0,        // dsub_4
   10889             :       0,        // dsub_5
   10890             :       0,        // dsub_6
   10891             :       0,        // dsub_7
   10892             :       0,        // gsub_0
   10893             :       0,        // gsub_1
   10894             :       0,        // qqsub_0
   10895             :       0,        // qqsub_1
   10896             :       58,       // qsub_0 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
   10897             :       0,        // qsub_1
   10898             :       0,        // qsub_2
   10899             :       0,        // qsub_3
   10900             :       58,       // ssub_0 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
   10901             :       58,       // ssub_1 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
   10902             :       58,       // ssub_2 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
   10903             :       58,       // ssub_3 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
   10904             :       58,       // ssub_4 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
   10905             :       58,       // ssub_5 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
   10906             :       0,        // ssub_6
   10907             :       0,        // ssub_7
   10908             :       0,        // ssub_8
   10909             :       0,        // ssub_9
   10910             :       0,        // ssub_10
   10911             :       0,        // ssub_11
   10912             :       0,        // ssub_12
   10913             :       0,        // ssub_13
   10914             :       0,        // dsub_7_then_ssub_0
   10915             :       0,        // dsub_7_then_ssub_1
   10916             :       58,       // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
   10917             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
   10918             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
   10919             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
   10920             :       58,       // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
   10921             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
   10922             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10923             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
   10924             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
   10925             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10926             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9
   10927             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10928             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10929             :       0,        // ssub_6_ssub_7_dsub_5
   10930             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
   10931             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
   10932             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
   10933             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10934             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
   10935             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10936             :       0,        // dsub_5_dsub_7
   10937             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
   10938             :       0,        // dsub_5_ssub_12_ssub_13
   10939             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
   10940             :     },
   10941             :     {   // DTripleSpc_with_dsub_2_in_DPR_8
   10942             :       59,       // dsub_0 -> DTripleSpc_with_dsub_2_in_DPR_8
   10943             :       0,        // dsub_1
   10944             :       59,       // dsub_2 -> DTripleSpc_with_dsub_2_in_DPR_8
   10945             :       0,        // dsub_3
   10946             :       59,       // dsub_4 -> DTripleSpc_with_dsub_2_in_DPR_8
   10947             :       0,        // dsub_5
   10948             :       0,        // dsub_6
   10949             :       0,        // dsub_7
   10950             :       0,        // gsub_0
   10951             :       0,        // gsub_1
   10952             :       0,        // qqsub_0
   10953             :       0,        // qqsub_1
   10954             :       0,        // qsub_0
   10955             :       0,        // qsub_1
   10956             :       0,        // qsub_2
   10957             :       0,        // qsub_3
   10958             :       59,       // ssub_0 -> DTripleSpc_with_dsub_2_in_DPR_8
   10959             :       59,       // ssub_1 -> DTripleSpc_with_dsub_2_in_DPR_8
   10960             :       0,        // ssub_2
   10961             :       0,        // ssub_3
   10962             :       59,       // ssub_4 -> DTripleSpc_with_dsub_2_in_DPR_8
   10963             :       59,       // ssub_5 -> DTripleSpc_with_dsub_2_in_DPR_8
   10964             :       0,        // ssub_6
   10965             :       0,        // ssub_7
   10966             :       59,       // ssub_8 -> DTripleSpc_with_dsub_2_in_DPR_8
   10967             :       59,       // ssub_9 -> DTripleSpc_with_dsub_2_in_DPR_8
   10968             :       0,        // ssub_10
   10969             :       0,        // ssub_11
   10970             :       0,        // ssub_12
   10971             :       0,        // ssub_13
   10972             :       0,        // dsub_7_then_ssub_0
   10973             :       0,        // dsub_7_then_ssub_1
   10974             :       59,       // ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_dsub_2_in_DPR_8
   10975             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
   10976             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
   10977             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
   10978             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5
   10979             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
   10980             :       0,        // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10981             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
   10982             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
   10983             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10984             :       59,       // ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_dsub_2_in_DPR_8
   10985             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
   10986             :       0,        // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
   10987             :       0,        // ssub_6_ssub_7_dsub_5
   10988             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
   10989             :       0,        // ssub_6_ssub_7_dsub_5_dsub_7
   10990             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9
   10991             :       0,        // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10992             :       0,        // ssub_8_ssub_9_ssub_12_ssub_13
   10993             :       0,        // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
   10994             :       0,        // dsub_5_dsub_7
   10995             :       0,        // dsub_5_ssub_12_ssub_13_dsub_7
   10996             :       0,        // dsub_5_ssub_12_ssub_13
   10997             :       0,        // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
   10998             :     },
   10999             :     {   // DTriple_with_dsub_2_in_DPR_8
   11000             :       60,       // dsub_0 -> DTriple_with_dsub_2_in_DPR_8
   11001             :       60,       // dsub_1 -> DTriple_with_dsub_2_in_DPR_8
   11002             :       60,       // dsub_2 -> DTriple_with_dsub_2_in_DPR_8
   11003             :       0,        // dsub_3
   11004             :       0,        // dsub_4
   11005             :       0,        // dsub_5
   11006             :       0,        // dsub_6
   11007             :       0,        // dsub_7
   11008             :       0,        // gsub_0
   11009             :       0,        // gsub_1
   11010             :       0,        // qqsub_0
   11011             :       0,        // qqsub_1
   11012             :       60,       // qsub_0 -> DTriple_with_dsub_2_in_DPR_8
   11013             :       0,        // qsub_1
   11014             :       0,        // qsub_2
   11015             :       0,        // qsub_3
   11016             :       60,       // ssub_0 -> DTriple_with_dsub_2_in_DPR_8
   11017             :       60,       // ssub_1 -> DTriple_with_dsub_2_in_DPR_8
   11018             :       60,       // ssub_2 -> DTriple_with_dsub_2_in_DPR_8
   11019             :       60,       // ssub_3 -> DTriple_with_dsub_2_in_DPR_8
   11020             :       60,       // ssub_4 -> DTriple_with_dsub_2_in_DPR_8
   11021             :       60,       // ssub_5 -> DTriple_with_dsub_2_in_DPR_8
   11022             :       0,        // ssub_6
   11023             :       0,        // ssub_7
   11024             :       0,        // ssub_8
   11025             :       0,        // ssub_9
   11026             :       0,        // ssub_10
   11027             :       0,        // ssub_11
   11028             :       0,        // ssub_12
   11029             :       0,        // ssub_13
   11030             :       0,        // dsub_7_then_ssub_0
   11031             :       0,        // dsub_7_then_ssub_1
   11032             :       60,       // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_dsub_2_in_DPR_8
   11033             :       0,        // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
   11034             :       0,        // ssub_2_ssub_3_ssub_6_ssub_7
   11035             :       0,        // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
   11036