LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/Lanai - LanaiGenAsmMatcher.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 167 337 49.6 %
Date: 2018-06-17 00:07:59 Functions: 8 9 88.9 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Assembly Matcher Source Fragment                                           *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : 
      10             : #ifdef GET_ASSEMBLER_HEADER
      11             : #undef GET_ASSEMBLER_HEADER
      12             :   // This should be included into the middle of the declaration of
      13             :   // your subclasses implementation of MCTargetAsmParser.
      14             :   uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;
      15             :   void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
      16             :                        const OperandVector &Operands);
      17             :   void convertToMapAndConstraints(unsigned Kind,
      18             :                            const OperandVector &Operands) override;
      19             :   unsigned MatchInstructionImpl(const OperandVector &Operands,
      20             :                                 MCInst &Inst,
      21             :                                 uint64_t &ErrorInfo,
      22             :                                 bool matchingInlineAsm,
      23             :                                 unsigned VariantID = 0);
      24             :   OperandMatchResultTy MatchOperandParserImpl(
      25             :     OperandVector &Operands,
      26             :     StringRef Mnemonic,
      27             :     bool ParseForAllFeatures = false);
      28             :   OperandMatchResultTy tryCustomParseOperand(
      29             :     OperandVector &Operands,
      30             :     unsigned MCK);
      31             : 
      32             : #endif // GET_ASSEMBLER_HEADER_INFO
      33             : 
      34             : 
      35             : #ifdef GET_OPERAND_DIAGNOSTIC_TYPES
      36             : #undef GET_OPERAND_DIAGNOSTIC_TYPES
      37             : 
      38             : #endif // GET_OPERAND_DIAGNOSTIC_TYPES
      39             : 
      40             : 
      41             : #ifdef GET_REGISTER_MATCHER
      42             : #undef GET_REGISTER_MATCHER
      43             : 
      44             : // Flags for subtarget features that participate in instruction matching.
      45             : enum SubtargetFeatureFlag : uint8_t {
      46             :   Feature_None = 0
      47             : };
      48             : 
      49         996 : static unsigned MatchRegisterName(StringRef Name) {
      50         996 :   switch (Name.size()) {
      51             :   default: break;
      52          65 :   case 2:        // 15 strings to match.
      53          65 :     switch (Name[0]) {
      54             :     default: break;
      55           0 :     case 'f':    // 1 string to match.
      56           0 :       if (Name[1] != 'p')
      57             :         break;
      58             :       return 1;  // "fp"
      59           3 :     case 'p':    // 1 string to match.
      60           3 :       if (Name[1] != 'c')
      61             :         break;
      62             :       return 2;  // "pc"
      63          60 :     case 'r':    // 11 strings to match.
      64          60 :       switch (Name[1]) {
      65             :       default: break;
      66             :       case '0':  // 1 string to match.
      67             :         return 7;        // "r0"
      68             :       case '1':  // 1 string to match.
      69             :         return 8;        // "r1"
      70             :       case '2':  // 1 string to match.
      71             :         return 9;        // "r2"
      72             :       case '3':  // 1 string to match.
      73             :         return 10;       // "r3"
      74             :       case '4':  // 1 string to match.
      75             :         return 11;       // "r4"
      76             :       case '5':  // 1 string to match.
      77             :         return 12;       // "r5"
      78             :       case '6':  // 1 string to match.
      79             :         return 13;       // "r6"
      80             :       case '7':  // 1 string to match.
      81             :         return 14;       // "r7"
      82             :       case '8':  // 1 string to match.
      83             :         return 15;       // "r8"
      84             :       case '9':  // 1 string to match.
      85             :         return 16;       // "r9"
      86             :       case 'v':  // 1 string to match.
      87             :         return 4;        // "rv"
      88             :       }
      89             :       break;
      90           0 :     case 's':    // 2 strings to match.
      91           0 :       switch (Name[1]) {
      92             :       default: break;
      93             :       case 'p':  // 1 string to match.
      94             :         return 5;        // "sp"
      95           0 :       case 'w':  // 1 string to match.
      96           0 :         return 6;        // "sw"
      97             :       }
      98             :       break;
      99             :     }
     100             :     break;
     101         929 :   case 3:        // 25 strings to match.
     102         929 :     if (Name[0] != 'r')
     103             :       break;
     104         928 :     switch (Name[1]) {
     105             :     default: break;
     106         613 :     case '1':    // 10 strings to match.
     107         613 :       switch (Name[2]) {
     108             :       default: break;
     109             :       case '0':  // 1 string to match.
     110             :         return 17;       // "r10"
     111             :       case '1':  // 1 string to match.
     112             :         return 18;       // "r11"
     113             :       case '2':  // 1 string to match.
     114             :         return 19;       // "r12"
     115             :       case '3':  // 1 string to match.
     116             :         return 20;       // "r13"
     117             :       case '4':  // 1 string to match.
     118             :         return 21;       // "r14"
     119             :       case '5':  // 1 string to match.
     120             :         return 22;       // "r15"
     121             :       case '6':  // 1 string to match.
     122             :         return 23;       // "r16"
     123             :       case '7':  // 1 string to match.
     124             :         return 24;       // "r17"
     125             :       case '8':  // 1 string to match.
     126             :         return 25;       // "r18"
     127             :       case '9':  // 1 string to match.
     128             :         return 26;       // "r19"
     129             :       }
     130             :       break;
     131         314 :     case '2':    // 10 strings to match.
     132         314 :       switch (Name[2]) {
     133             :       default: break;
     134             :       case '0':  // 1 string to match.
     135             :         return 27;       // "r20"
     136             :       case '1':  // 1 string to match.
     137             :         return 28;       // "r21"
     138             :       case '2':  // 1 string to match.
     139             :         return 29;       // "r22"
     140             :       case '3':  // 1 string to match.
     141             :         return 30;       // "r23"
     142             :       case '4':  // 1 string to match.
     143             :         return 31;       // "r24"
     144             :       case '5':  // 1 string to match.
     145             :         return 32;       // "r25"
     146             :       case '6':  // 1 string to match.
     147             :         return 33;       // "r26"
     148             :       case '7':  // 1 string to match.
     149             :         return 34;       // "r27"
     150             :       case '8':  // 1 string to match.
     151             :         return 35;       // "r28"
     152             :       case '9':  // 1 string to match.
     153             :         return 36;       // "r29"
     154             :       }
     155             :       break;
     156           1 :     case '3':    // 2 strings to match.
     157           1 :       switch (Name[2]) {
     158             :       default: break;
     159             :       case '0':  // 1 string to match.
     160             :         return 37;       // "r30"
     161           0 :       case '1':  // 1 string to match.
     162           0 :         return 38;       // "r31"
     163             :       }
     164             :       break;
     165           0 :     case 'c':    // 1 string to match.
     166           0 :       if (Name[2] != 'a')
     167             :         break;
     168             :       return 3;  // "rca"
     169           0 :     case 'r':    // 2 strings to match.
     170           0 :       switch (Name[2]) {
     171             :       default: break;
     172             :       case '1':  // 1 string to match.
     173             :         return 39;       // "rr1"
     174           0 :       case '2':  // 1 string to match.
     175           0 :         return 40;       // "rr2"
     176             :       }
     177             :       break;
     178             :     }
     179             :     break;
     180             :   }
     181             :   return 0;
     182             : }
     183             : 
     184             : #endif // GET_REGISTER_MATCHER
     185             : 
     186             : 
     187             : #ifdef GET_SUBTARGET_FEATURE_NAME
     188             : #undef GET_SUBTARGET_FEATURE_NAME
     189             : 
     190             : // User-level names for subtarget features that participate in
     191             : // instruction matching.
     192             : static const char *getSubtargetFeatureName(uint64_t Val) {
     193             :   return "(unknown)";
     194             : }
     195             : 
     196             : #endif // GET_SUBTARGET_FEATURE_NAME
     197             : 
     198             : 
     199             : #ifdef GET_MATCHER_IMPLEMENTATION
     200             : #undef GET_MATCHER_IMPLEMENTATION
     201             : 
     202             : const char TiedAsmOperandTable[][3] = { /* empty  */ {0, 0, 0} };
     203             : 
     204             : namespace {
     205             : enum OperatorConversionKind {
     206             :   CVT_Done,
     207             :   CVT_Reg,
     208             :   CVT_Tied,
     209             :   CVT_95_addImmOperands,
     210             :   CVT_95_Reg,
     211             :   CVT_95_addHiImm16Operands,
     212             :   CVT_95_addLoImm16Operands,
     213             :   CVT_95_addCondCodeOperands,
     214             :   CVT_95_addHiImm16AndOperands,
     215             :   CVT_95_addLoImm16AndOperands,
     216             :   CVT_95_addBrTargetOperands,
     217             :   CVT_95_addMemImmOperands,
     218             :   CVT_95_addMemRegImmOperands,
     219             :   CVT_95_addMemRegRegOperands,
     220             :   CVT_95_addMemSplsOperands,
     221             :   CVT_regR0,
     222             :   CVT_imm_95_0,
     223             :   CVT_regR1,
     224             :   CVT_95_addLoImm21Operands,
     225             :   CVT_95_addImmShiftOperands,
     226             :   CVT_NUM_CONVERTERS
     227             : };
     228             : 
     229             : enum InstructionConversionKind {
     230             :   Convert__Imm1_0__Imm1_1,
     231             :   Convert__Reg1_0__Reg1_1,
     232             :   Convert__Reg1_2__Reg1_0__HiImm161_1,
     233             :   Convert__Reg1_2__Reg1_0__LoImm161_1,
     234             :   Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0,
     235             :   Convert__Reg1_2__Reg1_0__HiImm16And1_1,
     236             :   Convert__Reg1_2__Reg1_0__LoImm16And1_1,
     237             :   Convert__Reg1_1__Imm1_0,
     238             :   Convert__BrTarget1_1__Imm1_0,
     239             :   Convert__Imm1_2__Imm1_0,
     240             :   Convert__Reg1_1__Reg1_3__Imm1_0,
     241             :   Convert__Reg1_0,
     242             :   Convert__BrTarget1_0,
     243             :   Convert__Reg1_1__MemImm1_0,
     244             :   Convert__Reg1_1__MemRegImm3_0,
     245             :   Convert__Reg1_1__MemRegReg3_0,
     246             :   Convert_NoOperands,
     247             :   Convert__Reg1_1__MemSpls3_0,
     248             :   Convert__Reg1_1__Reg1_0,
     249             :   Convert__Reg1_1__Reg1_0__regR0__imm_95_0,
     250             :   Convert__Reg1_1__regR1__HiImm16And1_0,
     251             :   Convert__Reg1_1__regR0__HiImm161_0,
     252             :   Convert__Reg1_1__regR1__LoImm16And1_0,
     253             :   Convert__Reg1_1__regR0__LoImm161_0,
     254             :   Convert__Reg1_1__LoImm211_0,
     255             :   Convert__Reg1_3__Reg1_1__Reg1_2__Imm1_0,
     256             :   Convert__Reg1_2__Reg1_0__ImmShift1_1,
     257             :   Convert__Reg1_0__MemImm1_1,
     258             :   Convert__Reg1_0__MemRegImm3_1,
     259             :   Convert__Reg1_0__MemRegReg3_1,
     260             :   Convert__Reg1_0__MemSpls3_1,
     261             :   CVT_NUM_SIGNATURES
     262             : };
     263             : 
     264             : } // end anonymous namespace
     265             : 
     266             : static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][9] = {
     267             :   // Convert__Imm1_0__Imm1_1
     268             :   { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
     269             :   // Convert__Reg1_0__Reg1_1
     270             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
     271             :   // Convert__Reg1_2__Reg1_0__HiImm161_1
     272             :   { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addHiImm16Operands, 2, CVT_Done },
     273             :   // Convert__Reg1_2__Reg1_0__LoImm161_1
     274             :   { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addLoImm16Operands, 2, CVT_Done },
     275             :   // Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0
     276             :   { CVT_95_Reg, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
     277             :   // Convert__Reg1_2__Reg1_0__HiImm16And1_1
     278             :   { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addHiImm16AndOperands, 2, CVT_Done },
     279             :   // Convert__Reg1_2__Reg1_0__LoImm16And1_1
     280             :   { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addLoImm16AndOperands, 2, CVT_Done },
     281             :   // Convert__Reg1_1__Imm1_0
     282             :   { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
     283             :   // Convert__BrTarget1_1__Imm1_0
     284             :   { CVT_95_addBrTargetOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
     285             :   // Convert__Imm1_2__Imm1_0
     286             :   { CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
     287             :   // Convert__Reg1_1__Reg1_3__Imm1_0
     288             :   { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addImmOperands, 1, CVT_Done },
     289             :   // Convert__Reg1_0
     290             :   { CVT_95_Reg, 1, CVT_Done },
     291             :   // Convert__BrTarget1_0
     292             :   { CVT_95_addBrTargetOperands, 1, CVT_Done },
     293             :   // Convert__Reg1_1__MemImm1_0
     294             :   { CVT_95_Reg, 2, CVT_95_addMemImmOperands, 1, CVT_Done },
     295             :   // Convert__Reg1_1__MemRegImm3_0
     296             :   { CVT_95_Reg, 2, CVT_95_addMemRegImmOperands, 1, CVT_Done },
     297             :   // Convert__Reg1_1__MemRegReg3_0
     298             :   { CVT_95_Reg, 2, CVT_95_addMemRegRegOperands, 1, CVT_Done },
     299             :   // Convert_NoOperands
     300             :   { CVT_Done },
     301             :   // Convert__Reg1_1__MemSpls3_0
     302             :   { CVT_95_Reg, 2, CVT_95_addMemSplsOperands, 1, CVT_Done },
     303             :   // Convert__Reg1_1__Reg1_0
     304             :   { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
     305             :   // Convert__Reg1_1__Reg1_0__regR0__imm_95_0
     306             :   { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_regR0, 0, CVT_imm_95_0, 0, CVT_Done },
     307             :   // Convert__Reg1_1__regR1__HiImm16And1_0
     308             :   { CVT_95_Reg, 2, CVT_regR1, 0, CVT_95_addHiImm16AndOperands, 1, CVT_Done },
     309             :   // Convert__Reg1_1__regR0__HiImm161_0
     310             :   { CVT_95_Reg, 2, CVT_regR0, 0, CVT_95_addHiImm16Operands, 1, CVT_Done },
     311             :   // Convert__Reg1_1__regR1__LoImm16And1_0
     312             :   { CVT_95_Reg, 2, CVT_regR1, 0, CVT_95_addLoImm16AndOperands, 1, CVT_Done },
     313             :   // Convert__Reg1_1__regR0__LoImm161_0
     314             :   { CVT_95_Reg, 2, CVT_regR0, 0, CVT_95_addLoImm16Operands, 1, CVT_Done },
     315             :   // Convert__Reg1_1__LoImm211_0
     316             :   { CVT_95_Reg, 2, CVT_95_addLoImm21Operands, 1, CVT_Done },
     317             :   // Convert__Reg1_3__Reg1_1__Reg1_2__Imm1_0
     318             :   { CVT_95_Reg, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
     319             :   // Convert__Reg1_2__Reg1_0__ImmShift1_1
     320             :   { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmShiftOperands, 2, CVT_Done },
     321             :   // Convert__Reg1_0__MemImm1_1
     322             :   { CVT_95_Reg, 1, CVT_95_addMemImmOperands, 2, CVT_Done },
     323             :   // Convert__Reg1_0__MemRegImm3_1
     324             :   { CVT_95_Reg, 1, CVT_95_addMemRegImmOperands, 2, CVT_Done },
     325             :   // Convert__Reg1_0__MemRegReg3_1
     326             :   { CVT_95_Reg, 1, CVT_95_addMemRegRegOperands, 2, CVT_Done },
     327             :   // Convert__Reg1_0__MemSpls3_1
     328             :   { CVT_95_Reg, 1, CVT_95_addMemSplsOperands, 2, CVT_Done },
     329             : };
     330             : 
     331         481 : void LanaiAsmParser::
     332             : convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
     333             :                 const OperandVector &Operands) {
     334             :   assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
     335         481 :   const uint8_t *Converter = ConversionTable[Kind];
     336             :   unsigned OpIdx;
     337             :   Inst.setOpcode(Opcode);
     338        2673 :   for (const uint8_t *p = Converter; *p; p+= 2) {
     339        1096 :     OpIdx = *(p + 1);
     340        1096 :     switch (*p) {
     341           0 :     default: llvm_unreachable("invalid conversion entry!");
     342           0 :     case CVT_Reg:
     343           0 :       static_cast<LanaiOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
     344             :       break;
     345           0 :     case CVT_Tied: {
     346             :       assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
     347             :                           std::begin(TiedAsmOperandTable)) &&
     348             :              "Tied operand not found");
     349           0 :       unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0];
     350             :       Inst.addOperand(Inst.getOperand(TiedResOpnd));
     351             :       break;
     352             :     }
     353          99 :     case CVT_95_addImmOperands:
     354          99 :       static_cast<LanaiOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
     355             :       break;
     356         573 :     case CVT_95_Reg:
     357        1146 :       static_cast<LanaiOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
     358             :       break;
     359          16 :     case CVT_95_addHiImm16Operands:
     360          32 :       static_cast<LanaiOperand&>(*Operands[OpIdx]).addHiImm16Operands(Inst, 1);
     361             :       break;
     362          26 :     case CVT_95_addLoImm16Operands:
     363          52 :       static_cast<LanaiOperand&>(*Operands[OpIdx]).addLoImm16Operands(Inst, 1);
     364             :       break;
     365          23 :     case CVT_95_addCondCodeOperands:
     366          23 :       static_cast<LanaiOperand&>(*Operands[OpIdx]).addCondCodeOperands(Inst, 1);
     367             :       break;
     368           3 :     case CVT_95_addHiImm16AndOperands:
     369           6 :       static_cast<LanaiOperand&>(*Operands[OpIdx]).addHiImm16AndOperands(Inst, 1);
     370             :       break;
     371           3 :     case CVT_95_addLoImm16AndOperands:
     372           6 :       static_cast<LanaiOperand&>(*Operands[OpIdx]).addLoImm16AndOperands(Inst, 1);
     373             :       break;
     374          27 :     case CVT_95_addBrTargetOperands:
     375          27 :       static_cast<LanaiOperand&>(*Operands[OpIdx]).addBrTargetOperands(Inst, 1);
     376             :       break;
     377           5 :     case CVT_95_addMemImmOperands:
     378           5 :       static_cast<LanaiOperand&>(*Operands[OpIdx]).addMemImmOperands(Inst, 1);
     379             :       break;
     380          65 :     case CVT_95_addMemRegImmOperands:
     381         130 :       static_cast<LanaiOperand&>(*Operands[OpIdx]).addMemRegImmOperands(Inst, 3);
     382             :       break;
     383         127 :     case CVT_95_addMemRegRegOperands:
     384         254 :       static_cast<LanaiOperand&>(*Operands[OpIdx]).addMemRegRegOperands(Inst, 3);
     385             :       break;
     386         102 :     case CVT_95_addMemSplsOperands:
     387         204 :       static_cast<LanaiOperand&>(*Operands[OpIdx]).addMemSplsOperands(Inst, 3);
     388             :       break;
     389             :     case CVT_regR0:
     390          14 :       Inst.addOperand(MCOperand::createReg(Lanai::R0));
     391             :       break;
     392             :     case CVT_imm_95_0:
     393           2 :       Inst.addOperand(MCOperand::createImm(0));
     394             :       break;
     395             :     case CVT_regR1:
     396           4 :       Inst.addOperand(MCOperand::createReg(Lanai::R1));
     397             :       break;
     398           1 :     case CVT_95_addLoImm21Operands:
     399           2 :       static_cast<LanaiOperand&>(*Operands[OpIdx]).addLoImm21Operands(Inst, 1);
     400             :       break;
     401          16 :     case CVT_95_addImmShiftOperands:
     402          16 :       static_cast<LanaiOperand&>(*Operands[OpIdx]).addImmShiftOperands(Inst, 1);
     403             :       break;
     404             :     }
     405             :   }
     406         481 : }
     407             : 
     408           0 : void LanaiAsmParser::
     409             : convertToMapAndConstraints(unsigned Kind,
     410             :                            const OperandVector &Operands) {
     411             :   assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
     412             :   unsigned NumMCOperands = 0;
     413           0 :   const uint8_t *Converter = ConversionTable[Kind];
     414           0 :   for (const uint8_t *p = Converter; *p; p+= 2) {
     415           0 :     switch (*p) {
     416           0 :     default: llvm_unreachable("invalid conversion entry!");
     417           0 :     case CVT_Reg:
     418           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
     419           0 :       Operands[*(p + 1)]->setConstraint("r");
     420           0 :       ++NumMCOperands;
     421           0 :       break;
     422           0 :     case CVT_Tied:
     423           0 :       ++NumMCOperands;
     424           0 :       break;
     425           0 :     case CVT_95_addImmOperands:
     426           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
     427           0 :       Operands[*(p + 1)]->setConstraint("m");
     428           0 :       NumMCOperands += 1;
     429           0 :       break;
     430           0 :     case CVT_95_Reg:
     431           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
     432           0 :       Operands[*(p + 1)]->setConstraint("r");
     433           0 :       NumMCOperands += 1;
     434           0 :       break;
     435           0 :     case CVT_95_addHiImm16Operands:
     436           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
     437           0 :       Operands[*(p + 1)]->setConstraint("m");
     438           0 :       NumMCOperands += 1;
     439           0 :       break;
     440           0 :     case CVT_95_addLoImm16Operands:
     441           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
     442           0 :       Operands[*(p + 1)]->setConstraint("m");
     443           0 :       NumMCOperands += 1;
     444           0 :       break;
     445           0 :     case CVT_95_addCondCodeOperands:
     446           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
     447           0 :       Operands[*(p + 1)]->setConstraint("m");
     448           0 :       NumMCOperands += 1;
     449           0 :       break;
     450           0 :     case CVT_95_addHiImm16AndOperands:
     451           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
     452           0 :       Operands[*(p + 1)]->setConstraint("m");
     453           0 :       NumMCOperands += 1;
     454           0 :       break;
     455           0 :     case CVT_95_addLoImm16AndOperands:
     456           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
     457           0 :       Operands[*(p + 1)]->setConstraint("m");
     458           0 :       NumMCOperands += 1;
     459           0 :       break;
     460           0 :     case CVT_95_addBrTargetOperands:
     461           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
     462           0 :       Operands[*(p + 1)]->setConstraint("m");
     463           0 :       NumMCOperands += 1;
     464           0 :       break;
     465           0 :     case CVT_95_addMemImmOperands:
     466           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
     467           0 :       Operands[*(p + 1)]->setConstraint("m");
     468           0 :       NumMCOperands += 1;
     469           0 :       break;
     470           0 :     case CVT_95_addMemRegImmOperands:
     471           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
     472           0 :       Operands[*(p + 1)]->setConstraint("m");
     473           0 :       NumMCOperands += 3;
     474           0 :       break;
     475           0 :     case CVT_95_addMemRegRegOperands:
     476           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
     477           0 :       Operands[*(p + 1)]->setConstraint("m");
     478           0 :       NumMCOperands += 3;
     479           0 :       break;
     480           0 :     case CVT_95_addMemSplsOperands:
     481           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
     482           0 :       Operands[*(p + 1)]->setConstraint("m");
     483           0 :       NumMCOperands += 3;
     484           0 :       break;
     485           0 :     case CVT_regR0:
     486           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
     487           0 :       Operands[*(p + 1)]->setConstraint("m");
     488           0 :       ++NumMCOperands;
     489           0 :       break;
     490           0 :     case CVT_imm_95_0:
     491           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
     492           0 :       Operands[*(p + 1)]->setConstraint("");
     493           0 :       ++NumMCOperands;
     494           0 :       break;
     495           0 :     case CVT_regR1:
     496           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
     497           0 :       Operands[*(p + 1)]->setConstraint("m");
     498           0 :       ++NumMCOperands;
     499           0 :       break;
     500           0 :     case CVT_95_addLoImm21Operands:
     501           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
     502           0 :       Operands[*(p + 1)]->setConstraint("m");
     503           0 :       NumMCOperands += 1;
     504           0 :       break;
     505           0 :     case CVT_95_addImmShiftOperands:
     506           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
     507           0 :       Operands[*(p + 1)]->setConstraint("m");
     508           0 :       NumMCOperands += 1;
     509           0 :       break;
     510             :     }
     511             :   }
     512           0 : }
     513             : 
     514             : namespace {
     515             : 
     516             : /// MatchClassKind - The kinds of classes which participate in
     517             : /// instruction matching.
     518             : enum MatchClassKind {
     519             :   InvalidMatchClass = 0,
     520             :   OptionalMatchClass = 1,
     521             :   MCK__EXCLAIM_, // '!'
     522             :   MCK__PCT_fp, // '%fp'
     523             :   MCK__PCT_pc, // '%pc'
     524             :   MCK__MINUS_4, // '-4'
     525             :   MCK__DOT_r, // '.r'
     526             :   MCK__91_, // '['
     527             :   MCK__93_, // ']'
     528             :   MCK_add, // 'add'
     529             :   MCK_return, // 'return'
     530             :   MCK_LAST_TOKEN = MCK_return,
     531             :   MCK_CCR, // register class 'CCR'
     532             :   MCK_Reg1, // derived register class
     533             :   MCK_GPR, // register class 'GPR'
     534             :   MCK_LAST_REGISTER = MCK_GPR,
     535             :   MCK_BrTarget, // user defined class 'BrTargetAsmOperand'
     536             :   MCK_CallTarget, // user defined class 'CallTargetAsmOperand'
     537             :   MCK_CondCode, // user defined class 'CondCodeOperand'
     538             :   MCK_HiImm16And, // user defined class 'HiImm16AndAsmOperand'
     539             :   MCK_HiImm16, // user defined class 'HiImm16AsmOperand'
     540             :   MCK_Imm10, // user defined class 'Imm10AsmOperand'
     541             :   MCK_Imm, // user defined class 'ImmAsmOperand'
     542             :   MCK_ImmShift, // user defined class 'ImmShiftAsmOperand'
     543             :   MCK_LoImm16And, // user defined class 'LoImm16AndAsmOperand'
     544             :   MCK_LoImm16, // user defined class 'LoImm16AsmOperand'
     545             :   MCK_LoImm21, // user defined class 'LoImm21AsmOperand'
     546             :   MCK_MemImm, // user defined class 'MemImmAsmOperand'
     547             :   MCK_MemRegImm, // user defined class 'MemRegImmAsmOperand'
     548             :   MCK_MemRegReg, // user defined class 'MemRegRegAsmOperand'
     549             :   MCK_MemSpls, // user defined class 'MemSplsAsmOperand'
     550             :   NumMatchClassKinds
     551             : };
     552             : 
     553             : }
     554             : 
     555             : static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
     556             :   return MCTargetAsmParser::Match_InvalidOperand;
     557             : }
     558             : 
     559          20 : static MatchClassKind matchTokenString(StringRef Name) {
     560          20 :   switch (Name.size()) {
     561             :   default: break;
     562           0 :   case 1:        // 3 strings to match.
     563           0 :     switch (Name[0]) {
     564             :     default: break;
     565             :     case '!':    // 1 string to match.
     566             :       return MCK__EXCLAIM_;      // "!"
     567           0 :     case '[':    // 1 string to match.
     568           0 :       return MCK__91_;   // "["
     569           0 :     case ']':    // 1 string to match.
     570           0 :       return MCK__93_;   // "]"
     571             :     }
     572             :     break;
     573          20 :   case 2:        // 2 strings to match.
     574          20 :     switch (Name[0]) {
     575             :     default: break;
     576           0 :     case '-':    // 1 string to match.
     577           0 :       if (Name[1] != '4')
     578             :         break;
     579             :       return MCK__MINUS_4;       // "-4"
     580          20 :     case '.':    // 1 string to match.
     581          20 :       if (Name[1] != 'r')
     582             :         break;
     583             :       return MCK__DOT_r;         // ".r"
     584             :     }
     585             :     break;
     586           0 :   case 3:        // 3 strings to match.
     587           0 :     switch (Name[0]) {
     588             :     default: break;
     589           0 :     case '%':    // 2 strings to match.
     590           0 :       switch (Name[1]) {
     591             :       default: break;
     592           0 :       case 'f':  // 1 string to match.
     593           0 :         if (Name[2] != 'p')
     594             :           break;
     595             :         return MCK__PCT_fp;      // "%fp"
     596           0 :       case 'p':  // 1 string to match.
     597           0 :         if (Name[2] != 'c')
     598             :           break;
     599             :         return MCK__PCT_pc;      // "%pc"
     600             :       }
     601             :       break;
     602             :     case 'a':    // 1 string to match.
     603           0 :       if (memcmp(Name.data()+1, "dd", 2) != 0)
     604             :         break;
     605             :       return MCK_add;    // "add"
     606             :     }
     607             :     break;
     608             :   case 6:        // 1 string to match.
     609           0 :     if (memcmp(Name.data()+0, "return", 6) != 0)
     610             :       break;
     611             :     return MCK_return;   // "return"
     612             :   }
     613             :   return InvalidMatchClass;
     614             : }
     615             : 
     616             : /// isSubclass - Compute whether \p A is a subclass of \p B.
     617             : static bool isSubclass(MatchClassKind A, MatchClassKind B) {
     618        1180 :   if (A == B)
     619             :     return true;
     620             : 
     621           3 :   switch (A) {
     622             :   default:
     623             :     return false;
     624             : 
     625           3 :   case MCK_Reg1:
     626           3 :     return B == MCK_GPR;
     627             :   }
     628             : }
     629             : 
     630        1774 : static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
     631             :   LanaiOperand &Operand = (LanaiOperand&)GOp;
     632        1774 :   if (Kind == InvalidMatchClass)
     633             :     return MCTargetAsmParser::Match_InvalidOperand;
     634             : 
     635        1754 :   if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)
     636          40 :     return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
     637             :              MCTargetAsmParser::Match_Success :
     638             :              MCTargetAsmParser::Match_InvalidOperand;
     639             : 
     640        1734 :   switch (Kind) {
     641             :   default: break;
     642             :   // 'BrTarget' class
     643             :   case MCK_BrTarget: {
     644             :     DiagnosticPredicate DP(Operand.isBrTarget());
     645          47 :     if (DP.isMatch())
     646             :       return MCTargetAsmParser::Match_Success;
     647             :     break;
     648             :     }
     649             :   // 'CallTarget' class
     650           0 :   case MCK_CallTarget: {
     651             :     DiagnosticPredicate DP(Operand.isCallTarget());
     652           0 :     if (DP.isMatch())
     653             :       return MCTargetAsmParser::Match_Success;
     654             :     break;
     655             :     }
     656             :   // 'CondCode' class
     657          23 :   case MCK_CondCode: {
     658             :     DiagnosticPredicate DP(Operand.isCondCode());
     659          23 :     if (DP.isMatch())
     660             :       return MCTargetAsmParser::Match_Success;
     661             :     break;
     662             :     }
     663             :   // 'HiImm16And' class
     664          13 :   case MCK_HiImm16And: {
     665             :     DiagnosticPredicate DP(Operand.isHiImm16And());
     666          13 :     if (DP.isMatch())
     667             :       return MCTargetAsmParser::Match_Success;
     668             :     break;
     669             :     }
     670             :   // 'HiImm16' class
     671          44 :   case MCK_HiImm16: {
     672          44 :     DiagnosticPredicate DP(Operand.isHiImm16());
     673          44 :     if (DP.isMatch())
     674             :       return MCTargetAsmParser::Match_Success;
     675             :     break;
     676             :     }
     677             :   // 'Imm10' class
     678           0 :   case MCK_Imm10: {
     679             :     DiagnosticPredicate DP(Operand.isImm10());
     680           0 :     if (DP.isMatch())
     681             :       return MCTargetAsmParser::Match_Success;
     682             :     break;
     683             :     }
     684             :   // 'Imm' class
     685         160 :   case MCK_Imm: {
     686             :     DiagnosticPredicate DP(Operand.isImm());
     687         160 :     if (DP.isMatch())
     688             :       return MCTargetAsmParser::Match_Success;
     689             :     break;
     690             :     }
     691             :   // 'ImmShift' class
     692          16 :   case MCK_ImmShift: {
     693             :     DiagnosticPredicate DP(Operand.isImmShift());
     694          16 :     if (DP.isMatch())
     695             :       return MCTargetAsmParser::Match_Success;
     696             :     break;
     697             :     }
     698             :   // 'LoImm16And' class
     699           6 :   case MCK_LoImm16And: {
     700             :     DiagnosticPredicate DP(Operand.isLoImm16And());
     701           6 :     if (DP.isMatch())
     702             :       return MCTargetAsmParser::Match_Success;
     703             :     break;
     704             :     }
     705             :   // 'LoImm16' class
     706          27 :   case MCK_LoImm16: {
     707          27 :     DiagnosticPredicate DP(Operand.isLoImm16());
     708          27 :     if (DP.isMatch())
     709             :       return MCTargetAsmParser::Match_Success;
     710             :     break;
     711             :     }
     712             :   // 'LoImm21' class
     713           1 :   case MCK_LoImm21: {
     714           1 :     DiagnosticPredicate DP(Operand.isLoImm21());
     715           1 :     if (DP.isMatch())
     716             :       return MCTargetAsmParser::Match_Success;
     717             :     break;
     718             :     }
     719             :   // 'MemImm' class
     720         119 :   case MCK_MemImm: {
     721             :     DiagnosticPredicate DP(Operand.isMemImm());
     722         119 :     if (DP.isMatch())
     723             :       return MCTargetAsmParser::Match_Success;
     724             :     break;
     725             :     }
     726             :   // 'MemRegImm' class
     727         132 :   case MCK_MemRegImm: {
     728             :     DiagnosticPredicate DP(Operand.isMemRegImm());
     729         132 :     if (DP.isMatch())
     730             :       return MCTargetAsmParser::Match_Success;
     731             :     break;
     732             :     }
     733             :   // 'MemRegReg' class
     734         229 :   case MCK_MemRegReg: {
     735             :     DiagnosticPredicate DP(Operand.isMemRegReg());
     736         229 :     if (DP.isMatch())
     737             :       return MCTargetAsmParser::Match_Success;
     738             :     break;
     739             :     }
     740             :   // 'MemSpls' class
     741             :   case MCK_MemSpls: {
     742             :     DiagnosticPredicate DP(Operand.isMemSpls());
     743         102 :     if (DP.isMatch())
     744             :       return MCTargetAsmParser::Match_Success;
     745             :     break;
     746             :     }
     747             :   } // end switch (Kind)
     748             : 
     749        1140 :   if (Operand.isReg()) {
     750             :     MatchClassKind OpKind;
     751             :     switch (Operand.getReg()) {
     752             :     default: OpKind = InvalidMatchClass; break;
     753             :     case Lanai::R0: OpKind = MCK_GPR; break;
     754             :     case Lanai::R1: OpKind = MCK_GPR; break;
     755             :     case Lanai::R2: OpKind = MCK_GPR; break;
     756             :     case Lanai::R3: OpKind = MCK_GPR; break;
     757             :     case Lanai::R4: OpKind = MCK_GPR; break;
     758             :     case Lanai::R5: OpKind = MCK_GPR; break;
     759             :     case Lanai::R6: OpKind = MCK_GPR; break;
     760             :     case Lanai::R7: OpKind = MCK_GPR; break;
     761             :     case Lanai::R8: OpKind = MCK_GPR; break;
     762             :     case Lanai::R9: OpKind = MCK_GPR; break;
     763             :     case Lanai::R10: OpKind = MCK_GPR; break;
     764             :     case Lanai::R11: OpKind = MCK_GPR; break;
     765             :     case Lanai::R12: OpKind = MCK_GPR; break;
     766             :     case Lanai::R13: OpKind = MCK_GPR; break;
     767             :     case Lanai::R14: OpKind = MCK_GPR; break;
     768             :     case Lanai::R15: OpKind = MCK_GPR; break;
     769             :     case Lanai::R16: OpKind = MCK_GPR; break;
     770             :     case Lanai::R17: OpKind = MCK_GPR; break;
     771             :     case Lanai::R18: OpKind = MCK_GPR; break;
     772             :     case Lanai::R19: OpKind = MCK_GPR; break;
     773             :     case Lanai::R20: OpKind = MCK_GPR; break;
     774             :     case Lanai::R21: OpKind = MCK_GPR; break;
     775             :     case Lanai::R22: OpKind = MCK_GPR; break;
     776             :     case Lanai::R23: OpKind = MCK_GPR; break;
     777             :     case Lanai::R24: OpKind = MCK_GPR; break;
     778             :     case Lanai::R25: OpKind = MCK_GPR; break;
     779             :     case Lanai::R26: OpKind = MCK_GPR; break;
     780             :     case Lanai::R27: OpKind = MCK_GPR; break;
     781             :     case Lanai::R28: OpKind = MCK_GPR; break;
     782             :     case Lanai::R29: OpKind = MCK_GPR; break;
     783             :     case Lanai::R30: OpKind = MCK_GPR; break;
     784             :     case Lanai::R31: OpKind = MCK_GPR; break;
     785             :     case Lanai::PC: OpKind = MCK_Reg1; break;
     786             :     case Lanai::SP: OpKind = MCK_Reg1; break;
     787             :     case Lanai::FP: OpKind = MCK_Reg1; break;
     788             :     case Lanai::RV: OpKind = MCK_Reg1; break;
     789             :     case Lanai::RR1: OpKind = MCK_Reg1; break;
     790             :     case Lanai::RR2: OpKind = MCK_Reg1; break;
     791             :     case Lanai::RCA: OpKind = MCK_Reg1; break;
     792             :     case Lanai::SR: OpKind = MCK_CCR; break;
     793             :     }
     794           3 :     return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
     795             :                                       getDiagKindFromRegisterClass(Kind);
     796             :   }
     797             : 
     798             :   if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)
     799             :     return getDiagKindFromRegisterClass(Kind);
     800             : 
     801             :   return MCTargetAsmParser::Match_InvalidOperand;
     802             : }
     803             : 
     804             : #ifndef NDEBUG
     805             : const char *getMatchClassName(MatchClassKind Kind) {
     806             :   switch (Kind) {
     807             :   case InvalidMatchClass: return "InvalidMatchClass";
     808             :   case OptionalMatchClass: return "OptionalMatchClass";
     809             :   case MCK__EXCLAIM_: return "MCK__EXCLAIM_";
     810             :   case MCK__PCT_fp: return "MCK__PCT_fp";
     811             :   case MCK__PCT_pc: return "MCK__PCT_pc";
     812             :   case MCK__MINUS_4: return "MCK__MINUS_4";
     813             :   case MCK__DOT_r: return "MCK__DOT_r";
     814             :   case MCK__91_: return "MCK__91_";
     815             :   case MCK__93_: return "MCK__93_";
     816             :   case MCK_add: return "MCK_add";
     817             :   case MCK_return: return "MCK_return";
     818             :   case MCK_CCR: return "MCK_CCR";
     819             :   case MCK_Reg1: return "MCK_Reg1";
     820             :   case MCK_GPR: return "MCK_GPR";
     821             :   case MCK_BrTarget: return "MCK_BrTarget";
     822             :   case MCK_CallTarget: return "MCK_CallTarget";
     823             :   case MCK_CondCode: return "MCK_CondCode";
     824             :   case MCK_HiImm16And: return "MCK_HiImm16And";
     825             :   case MCK_HiImm16: return "MCK_HiImm16";
     826             :   case MCK_Imm10: return "MCK_Imm10";
     827             :   case MCK_Imm: return "MCK_Imm";
     828             :   case MCK_ImmShift: return "MCK_ImmShift";
     829             :   case MCK_LoImm16And: return "MCK_LoImm16And";
     830             :   case MCK_LoImm16: return "MCK_LoImm16";
     831             :   case MCK_LoImm21: return "MCK_LoImm21";
     832             :   case MCK_MemImm: return "MCK_MemImm";
     833             :   case MCK_MemRegImm: return "MCK_MemRegImm";
     834             :   case MCK_MemRegReg: return "MCK_MemRegReg";
     835             :   case MCK_MemSpls: return "MCK_MemSpls";
     836             :   case NumMatchClassKinds: return "NumMatchClassKinds";
     837             :   }
     838             :   llvm_unreachable("unhandled MatchClassKind!");
     839             : }
     840             : 
     841             : #endif // NDEBUG
     842             : uint64_t LanaiAsmParser::
     843             : ComputeAvailableFeatures(const FeatureBitset& FB) const {
     844             :   uint64_t Features = 0;
     845             :   return Features;
     846             : }
     847             : 
     848         481 : static bool checkAsmTiedOperandConstraints(unsigned Kind,
     849             :                                const OperandVector &Operands,
     850             :                                uint64_t &ErrorInfo) {
     851             :   assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
     852         481 :   const uint8_t *Converter = ConversionTable[Kind];
     853        2673 :   for (const uint8_t *p = Converter; *p; p+= 2) {
     854        1096 :     switch (*p) {
     855           0 :     case CVT_Tied: {
     856           0 :       unsigned OpIdx = *(p+1);
     857             :       assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
     858             :                               std::begin(TiedAsmOperandTable)) &&
     859             :              "Tied operand not found");
     860           0 :       unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1];
     861             :       unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2];
     862           0 :       if (OpndNum1 != OpndNum2) {
     863           0 :         auto &SrcOp1 = Operands[OpndNum1];
     864             :         auto &SrcOp2 = Operands[OpndNum2];
     865           0 :         if (SrcOp1->isReg() && SrcOp2->isReg() &&
     866           0 :             SrcOp1->getReg() != SrcOp2->getReg()) {
     867           0 :           ErrorInfo = OpndNum2;
     868           0 :           return false;
     869             :         }
     870             :       }
     871             :       break;
     872             :     }
     873             :     default:
     874             :       break;
     875             :     }
     876             :   }
     877             :   return true;
     878             : }
     879             : 
     880             : static const char *const MnemonicTable =
     881             :     "\021#ADJCALLSTACKDOWN\017#ADJCALLSTACKUP\014#ADJDYNALLOC\003add\005add."
     882             :     "f\004addc\006addc.f\003and\005and.f\001b\002bt\002ld\004ld.b\004ld.h\005"
     883             :     "leadz\005log_0\005log_1\005log_2\005log_3\005log_4\003mov\003nop\002or\004"
     884             :     "or.f\004popc\001s\004sel.\002sh\004sh.f\003sha\005sha.f\002st\004st.b\004"
     885             :     "st.h\003sub\005sub.f\004subb\006subb.f\006trailz\003uld\005uld.b\005uld"
     886             :     ".h\003xor\005xor.f";
     887             : 
     888             : namespace {
     889             :   struct MatchEntry {
     890             :     uint8_t Mnemonic;
     891             :     uint16_t Opcode;
     892             :     uint8_t ConvertFn;
     893             :     uint8_t RequiredFeatures;
     894             :     uint8_t Classes[7];
     895             :     StringRef getMnemonic() const {
     896        5448 :       return StringRef(MnemonicTable + Mnemonic + 1,
     897        5448 :                        MnemonicTable[Mnemonic]);
     898             :     }
     899             :   };
     900             : 
     901             :   // Predicate for searching for an opcode.
     902             :   struct LessOpcode {
     903             :     bool operator()(const MatchEntry &LHS, StringRef RHS) {
     904        6244 :       return LHS.getMnemonic() < RHS;
     905             :     }
     906             :     bool operator()(StringRef LHS, const MatchEntry &RHS) {
     907        4652 :       return LHS < RHS.getMnemonic();
     908             :     }
     909             :     bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
     910             :       return LHS.getMnemonic() < RHS.getMnemonic();
     911             :     }
     912             :   };
     913             : } // end anonymous namespace.
     914             : 
     915             : static const MatchEntry MatchTable0[] = {
     916             :   { 0 /* #ADJCALLSTACKDOWN */, Lanai::ADJCALLSTACKDOWN, Convert__Imm1_0__Imm1_1, 0, { MCK_Imm, MCK_Imm }, },
     917             :   { 18 /* #ADJCALLSTACKUP */, Lanai::ADJCALLSTACKUP, Convert__Imm1_0__Imm1_1, 0, { MCK_Imm, MCK_Imm }, },
     918             :   { 34 /* #ADJDYNALLOC */, Lanai::ADJDYNALLOC, Convert__Reg1_0__Reg1_1, 0, { MCK_GPR, MCK_GPR }, },
     919             :   { 47 /* add */, Lanai::ADD_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
     920             :   { 47 /* add */, Lanai::ADD_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
     921             :   { 47 /* add */, Lanai::ADD_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
     922             :   { 51 /* add.f */, Lanai::ADD_F_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
     923             :   { 51 /* add.f */, Lanai::ADD_F_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
     924             :   { 51 /* add.f */, Lanai::ADD_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
     925             :   { 57 /* addc */, Lanai::ADDC_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
     926             :   { 57 /* addc */, Lanai::ADDC_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
     927             :   { 57 /* addc */, Lanai::ADDC_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
     928             :   { 62 /* addc.f */, Lanai::ADDC_F_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
     929             :   { 62 /* addc.f */, Lanai::ADDC_F_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
     930             :   { 62 /* addc.f */, Lanai::ADDC_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
     931             :   { 69 /* and */, Lanai::AND_I_HI, Convert__Reg1_2__Reg1_0__HiImm16And1_1, 0, { MCK_GPR, MCK_HiImm16And, MCK_GPR }, },
     932             :   { 69 /* and */, Lanai::AND_I_LO, Convert__Reg1_2__Reg1_0__LoImm16And1_1, 0, { MCK_GPR, MCK_LoImm16And, MCK_GPR }, },
     933             :   { 69 /* and */, Lanai::AND_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
     934             :   { 73 /* and.f */, Lanai::AND_F_I_HI, Convert__Reg1_2__Reg1_0__HiImm16And1_1, 0, { MCK_GPR, MCK_HiImm16And, MCK_GPR }, },
     935             :   { 73 /* and.f */, Lanai::AND_F_I_LO, Convert__Reg1_2__Reg1_0__LoImm16And1_1, 0, { MCK_GPR, MCK_LoImm16And, MCK_GPR }, },
     936             :   { 73 /* and.f */, Lanai::AND_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
     937             :   { 79 /* b */, Lanai::BRIND_CC, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GPR }, },
     938             :   { 79 /* b */, Lanai::BRCC, Convert__BrTarget1_1__Imm1_0, 0, { MCK_Imm, MCK_BrTarget }, },
     939             :   { 79 /* b */, Lanai::BRR, Convert__Imm1_2__Imm1_0, 0, { MCK_Imm, MCK__DOT_r, MCK_Imm }, },
     940             :   { 79 /* b */, Lanai::BRIND_CCA, Convert__Reg1_1__Reg1_3__Imm1_0, 0, { MCK_Imm, MCK_GPR, MCK_add, MCK_GPR }, },
     941             :   { 81 /* bt */, Lanai::JR, Convert__Reg1_0, 0, { MCK_GPR }, },
     942             :   { 81 /* bt */, Lanai::BT, Convert__BrTarget1_0, 0, { MCK_BrTarget }, },
     943             :   { 84 /* ld */, Lanai::LDADDR, Convert__Reg1_1__MemImm1_0, 0, { MCK_MemImm, MCK_GPR }, },
     944             :   { 84 /* ld */, Lanai::LDW_RI, Convert__Reg1_1__MemRegImm3_0, 0, { MCK_MemRegImm, MCK_GPR }, },
     945             :   { 84 /* ld */, Lanai::LDW_RR, Convert__Reg1_1__MemRegReg3_0, 0, { MCK_MemRegReg, MCK_GPR }, },
     946             :   { 84 /* ld */, Lanai::RET, Convert_NoOperands, 0, { MCK__MINUS_4, MCK__91_, MCK__PCT_fp, MCK__93_, MCK__PCT_pc, MCK__EXCLAIM_, MCK_return }, },
     947             :   { 87 /* ld.b */, Lanai::LDBs_RR, Convert__Reg1_1__MemRegReg3_0, 0, { MCK_MemRegReg, MCK_GPR }, },
     948             :   { 87 /* ld.b */, Lanai::LDBs_RI, Convert__Reg1_1__MemSpls3_0, 0, { MCK_MemSpls, MCK_GPR }, },
     949             :   { 92 /* ld.h */, Lanai::LDHs_RR, Convert__Reg1_1__MemRegReg3_0, 0, { MCK_MemRegReg, MCK_GPR }, },
     950             :   { 92 /* ld.h */, Lanai::LDHs_RI, Convert__Reg1_1__MemSpls3_0, 0, { MCK_MemSpls, MCK_GPR }, },
     951             :   { 97 /* leadz */, Lanai::LEADZ, Convert__Reg1_1__Reg1_0, 0, { MCK_GPR, MCK_GPR }, },
     952             :   { 103 /* log_0 */, Lanai::LOG0, Convert_NoOperands, 0, {  }, },
     953             :   { 109 /* log_1 */, Lanai::LOG1, Convert_NoOperands, 0, {  }, },
     954             :   { 115 /* log_2 */, Lanai::LOG2, Convert_NoOperands, 0, {  }, },
     955             :   { 121 /* log_3 */, Lanai::LOG3, Convert_NoOperands, 0, {  }, },
     956             :   { 127 /* log_4 */, Lanai::LOG4, Convert_NoOperands, 0, {  }, },
     957             :   { 133 /* mov */, Lanai::ADD_R, Convert__Reg1_1__Reg1_0__regR0__imm_95_0, 0, { MCK_GPR, MCK_GPR }, },
     958             :   { 133 /* mov */, Lanai::AND_I_HI, Convert__Reg1_1__regR1__HiImm16And1_0, 0, { MCK_HiImm16And, MCK_GPR }, },
     959             :   { 133 /* mov */, Lanai::ADD_I_HI, Convert__Reg1_1__regR0__HiImm161_0, 0, { MCK_HiImm16, MCK_GPR }, },
     960             :   { 133 /* mov */, Lanai::AND_I_LO, Convert__Reg1_1__regR1__LoImm16And1_0, 0, { MCK_LoImm16And, MCK_GPR }, },
     961             :   { 133 /* mov */, Lanai::ADD_I_LO, Convert__Reg1_1__regR0__LoImm161_0, 0, { MCK_LoImm16, MCK_GPR }, },
     962             :   { 133 /* mov */, Lanai::SLI, Convert__Reg1_1__LoImm211_0, 0, { MCK_LoImm21, MCK_GPR }, },
     963             :   { 137 /* nop */, Lanai::NOP, Convert_NoOperands, 0, {  }, },
     964             :   { 141 /* or */, Lanai::OR_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
     965             :   { 141 /* or */, Lanai::OR_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
     966             :   { 141 /* or */, Lanai::OR_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
     967             :   { 144 /* or.f */, Lanai::OR_F_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
     968             :   { 144 /* or.f */, Lanai::OR_F_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
     969             :   { 144 /* or.f */, Lanai::OR_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
     970             :   { 149 /* popc */, Lanai::POPC, Convert__Reg1_1__Reg1_0, 0, { MCK_GPR, MCK_GPR }, },
     971             :   { 154 /* s */, Lanai::SCC, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GPR }, },
     972             :   { 156 /* sel. */, Lanai::SELECT, Convert__Reg1_3__Reg1_1__Reg1_2__Imm1_0, 0, { MCK_Imm, MCK_GPR, MCK_GPR, MCK_GPR }, },
     973             :   { 161 /* sh */, Lanai::SL_I, Convert__Reg1_2__Reg1_0__ImmShift1_1, 0, { MCK_GPR, MCK_ImmShift, MCK_GPR }, },
     974             :   { 161 /* sh */, Lanai::SHL_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
     975             :   { 164 /* sh.f */, Lanai::SL_F_I, Convert__Reg1_2__Reg1_0__ImmShift1_1, 0, { MCK_GPR, MCK_ImmShift, MCK_GPR }, },
     976             :   { 164 /* sh.f */, Lanai::SHL_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
     977             :   { 169 /* sha */, Lanai::SA_I, Convert__Reg1_2__Reg1_0__ImmShift1_1, 0, { MCK_GPR, MCK_ImmShift, MCK_GPR }, },
     978             :   { 169 /* sha */, Lanai::SRA_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
     979             :   { 173 /* sha.f */, Lanai::SA_F_I, Convert__Reg1_2__Reg1_0__ImmShift1_1, 0, { MCK_GPR, MCK_ImmShift, MCK_GPR }, },
     980             :   { 173 /* sha.f */, Lanai::SRA_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
     981             :   { 179 /* st */, Lanai::STADDR, Convert__Reg1_0__MemImm1_1, 0, { MCK_GPR, MCK_MemImm }, },
     982             :   { 179 /* st */, Lanai::SW_RI, Convert__Reg1_0__MemRegImm3_1, 0, { MCK_GPR, MCK_MemRegImm }, },
     983             :   { 179 /* st */, Lanai::SW_RR, Convert__Reg1_0__MemRegReg3_1, 0, { MCK_GPR, MCK_MemRegReg }, },
     984             :   { 182 /* st.b */, Lanai::STB_RR, Convert__Reg1_0__MemRegReg3_1, 0, { MCK_GPR, MCK_MemRegReg }, },
     985             :   { 182 /* st.b */, Lanai::STB_RI, Convert__Reg1_0__MemSpls3_1, 0, { MCK_GPR, MCK_MemSpls }, },
     986             :   { 187 /* st.h */, Lanai::STH_RR, Convert__Reg1_0__MemRegReg3_1, 0, { MCK_GPR, MCK_MemRegReg }, },
     987             :   { 187 /* st.h */, Lanai::STH_RI, Convert__Reg1_0__MemSpls3_1, 0, { MCK_GPR, MCK_MemSpls }, },
     988             :   { 192 /* sub */, Lanai::SUB_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
     989             :   { 192 /* sub */, Lanai::SUB_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
     990             :   { 192 /* sub */, Lanai::SUB_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
     991             :   { 196 /* sub.f */, Lanai::SUB_F_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
     992             :   { 196 /* sub.f */, Lanai::SUB_F_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
     993             :   { 196 /* sub.f */, Lanai::SUB_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
     994             :   { 202 /* subb */, Lanai::SUBB_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
     995             :   { 202 /* subb */, Lanai::SUBB_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
     996             :   { 202 /* subb */, Lanai::SUBB_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
     997             :   { 207 /* subb.f */, Lanai::SUBB_F_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
     998             :   { 207 /* subb.f */, Lanai::SUBB_F_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
     999             :   { 207 /* subb.f */, Lanai::SUBB_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
    1000             :   { 214 /* trailz */, Lanai::TRAILZ, Convert__Reg1_1__Reg1_0, 0, { MCK_GPR, MCK_GPR }, },
    1001             :   { 221 /* uld */, Lanai::LDW_RI, Convert__Reg1_1__MemRegImm3_0, 0, { MCK_MemRegImm, MCK_GPR }, },
    1002             :   { 221 /* uld */, Lanai::LDWz_RR, Convert__Reg1_1__MemRegReg3_0, 0, { MCK_MemRegReg, MCK_GPR }, },
    1003             :   { 225 /* uld.b */, Lanai::LDBz_RR, Convert__Reg1_1__MemRegReg3_0, 0, { MCK_MemRegReg, MCK_GPR }, },
    1004             :   { 225 /* uld.b */, Lanai::LDBz_RI, Convert__Reg1_1__MemSpls3_0, 0, { MCK_MemSpls, MCK_GPR }, },
    1005             :   { 231 /* uld.h */, Lanai::LDHz_RR, Convert__Reg1_1__MemRegReg3_0, 0, { MCK_MemRegReg, MCK_GPR }, },
    1006             :   { 231 /* uld.h */, Lanai::LDHz_RI, Convert__Reg1_1__MemSpls3_0, 0, { MCK_MemSpls, MCK_GPR }, },
    1007             :   { 237 /* xor */, Lanai::XOR_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
    1008             :   { 237 /* xor */, Lanai::XOR_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
    1009             :   { 237 /* xor */, Lanai::XOR_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
    1010             :   { 241 /* xor.f */, Lanai::XOR_F_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
    1011             :   { 241 /* xor.f */, Lanai::XOR_F_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
    1012             :   { 241 /* xor.f */, Lanai::XOR_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
    1013             : };
    1014             : 
    1015             : #include "llvm/Support/Debug.h"
    1016             : #include "llvm/Support/Format.h"
    1017             : 
    1018         481 : unsigned LanaiAsmParser::
    1019             : MatchInstructionImpl(const OperandVector &Operands,
    1020             :                      MCInst &Inst,
    1021             :                      uint64_t &ErrorInfo,
    1022             :                      bool matchingInlineAsm, unsigned VariantID) {
    1023             :   // Eliminate obvious mismatches.
    1024         481 :   if (Operands.size() > 8) {
    1025           0 :     ErrorInfo = 8;
    1026           0 :     return Match_InvalidOperand;
    1027             :   }
    1028             : 
    1029             :   // Get the current feature set.
    1030         481 :   uint64_t AvailableFeatures = getAvailableFeatures();
    1031             : 
    1032             :   // Get the instruction mnemonic, which is the first token.
    1033         962 :   StringRef Mnemonic = ((LanaiOperand&)*Operands[0]).getToken();
    1034             : 
    1035             :   // Some state to try to produce better error messages.
    1036             :   bool HadMatchOtherThanFeatures = false;
    1037             :   bool HadMatchOtherThanPredicate = false;
    1038             :   unsigned RetCode = Match_InvalidOperand;
    1039             :   uint64_t MissingFeatures = ~0ULL;
    1040             :   // Set ErrorInfo to the operand that mismatches if it is
    1041             :   // wrong for all instances of the instruction.
    1042         481 :   ErrorInfo = ~0ULL;
    1043             :   // Find the appropriate table for this asm variant.
    1044             :   const MatchEntry *Start, *End;
    1045         481 :   switch (VariantID) {
    1046           0 :   default: llvm_unreachable("invalid variant!");
    1047             :   case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
    1048             :   }
    1049             :   // Search the table.
    1050             :   auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
    1051             : 
    1052             :   DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " <<
    1053             :   std::distance(MnemonicRange.first, MnemonicRange.second) << 
    1054             :   " encodings with mnemonic '" << Mnemonic << "'\n");
    1055             : 
    1056             :   // Return a more specific error code if no mnemonics match.
    1057         481 :   if (MnemonicRange.first == MnemonicRange.second)
    1058             :     return Match_MnemonicFail;
    1059             : 
    1060         443 :   for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
    1061         924 :        it != ie; ++it) {
    1062         924 :     bool HasRequiredFeatures =
    1063         924 :       (AvailableFeatures & it->RequiredFeatures) == it->RequiredFeatures;
    1064             :     DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode "
    1065             :                                           << MII.getName(it->Opcode) << "\n");
    1066             :     // equal_range guarantees that instruction mnemonic matches.
    1067             :     assert(Mnemonic == it->getMnemonic());
    1068             :     bool OperandsValid = true;
    1069        3586 :     for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 7; ++FormalIdx) {
    1070        2255 :       auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);
    1071             :       DEBUG_WITH_TYPE("asm-matcher",
    1072             :                       dbgs() << "  Matching formal operand class " << getMatchClassName(Formal)
    1073             :                              << " against actual operand at index " << ActualIdx);
    1074        2255 :       if (ActualIdx < Operands.size())
    1075             :         DEBUG_WITH_TYPE("asm-matcher", dbgs() << " (";
    1076             :                         Operands[ActualIdx]->print(dbgs()); dbgs() << "): ");
    1077             :       else
    1078             :         DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": ");
    1079        2255 :       if (ActualIdx >= Operands.size()) {
    1080             :         DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range ");
    1081         481 :         OperandsValid = (Formal == InvalidMatchClass) || isSubclass(Formal, OptionalMatchClass);
    1082           0 :         if (!OperandsValid) ErrorInfo = ActualIdx;
    1083             :         break;
    1084             :       }
    1085             :       MCParsedAsmOperand &Actual = *Operands[ActualIdx];
    1086        1774 :       unsigned Diag = validateOperandClass(Actual, Formal);
    1087        3105 :       if (Diag == Match_Success) {
    1088             :         DEBUG_WITH_TYPE("asm-matcher",
    1089             :                         dbgs() << "match success using generic matcher\n");
    1090        1331 :         ++ActualIdx;
    1091        1331 :         continue;
    1092             :       }
    1093             :       // If the generic handler indicates an invalid operand
    1094             :       // failure, check for a special case.
    1095             :       if (Diag != Match_Success) {
    1096         443 :         unsigned TargetDiag = validateTargetOperandClass(Actual, Formal);
    1097         443 :         if (TargetDiag == Match_Success) {
    1098             :           DEBUG_WITH_TYPE("asm-matcher",
    1099             :                           dbgs() << "match success using target matcher\n");
    1100           0 :           ++ActualIdx;
    1101           0 :           continue;
    1102             :         }
    1103             :         // If the target matcher returned a specific error code use
    1104             :         // that, else use the one from the generic matcher.
    1105         443 :         if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures)
    1106             :           Diag = TargetDiag;
    1107             :       }
    1108             :       // If current formal operand wasn't matched and it is optional
    1109             :       // then try to match next formal operand
    1110         443 :       if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) {
    1111             :         DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n");
    1112           0 :         continue;
    1113             :       }
    1114             :       // If this operand is broken for all of the instances of this
    1115             :       // mnemonic, keep track of it so we can report loc info.
    1116             :       // If we already had a match that only failed due to a
    1117             :       // target predicate, that diagnostic is preferred.
    1118         886 :       if (!HadMatchOtherThanPredicate &&
    1119         119 :           (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {
    1120         443 :         if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag != Match_InvalidOperand))
    1121             :           RetCode = Diag;
    1122         443 :         ErrorInfo = ActualIdx;
    1123             :       }
    1124             :       // Otherwise, just reject this instance of the mnemonic.
    1125             :       OperandsValid = false;
    1126             :       break;
    1127             :     }
    1128             : 
    1129         924 :     if (!OperandsValid) {
    1130             :       DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
    1131             :                                                "operand mismatches, ignoring "
    1132             :                                                "this opcode\n");
    1133         443 :       continue;
    1134             :     }
    1135         481 :     if (!HasRequiredFeatures) {
    1136             :       HadMatchOtherThanFeatures = true;
    1137           0 :       uint64_t NewMissingFeatures = it->RequiredFeatures & ~AvailableFeatures;
    1138             :       DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features: "
    1139             :                                             << format_hex(NewMissingFeatures, 18)
    1140             :                                             << "\n");
    1141           0 :       if (countPopulation(NewMissingFeatures) <=
    1142             :           countPopulation(MissingFeatures))
    1143             :         MissingFeatures = NewMissingFeatures;
    1144           0 :       continue;
    1145             :     }
    1146             : 
    1147             :     Inst.clear();
    1148             : 
    1149         481 :     Inst.setOpcode(it->Opcode);
    1150             :     // We have a potential match but have not rendered the operands.
    1151             :     // Check the target predicate to handle any context sensitive
    1152             :     // constraints.
    1153             :     // For example, Ties that are referenced multiple times must be
    1154             :     // checked here to ensure the input is the same for each match
    1155             :     // constraints. If we leave it any later the ties will have been
    1156             :     // canonicalized
    1157             :     unsigned MatchResult;
    1158         481 :     if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) {
    1159             :       Inst.clear();
    1160             :       DEBUG_WITH_TYPE(
    1161             :           "asm-matcher",
    1162             :           dbgs() << "Early target match predicate failed with diag code "
    1163             :                  << MatchResult << "\n");
    1164             :       RetCode = MatchResult;
    1165             :       HadMatchOtherThanPredicate = true;
    1166           0 :       continue;
    1167             :     }
    1168             : 
    1169         481 :     if (matchingInlineAsm) {
    1170           0 :       convertToMapAndConstraints(it->ConvertFn, Operands);
    1171           0 :       if (!checkAsmTiedOperandConstraints(it->ConvertFn, Operands, ErrorInfo))
    1172             :         return Match_InvalidTiedOperand;
    1173             : 
    1174           0 :       return Match_Success;
    1175             :     }
    1176             : 
    1177             :     // We have selected a definite instruction, convert the parsed
    1178             :     // operands into the appropriate MCInst.
    1179         481 :     convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);
    1180             : 
    1181             :     // We have a potential match. Check the target predicate to
    1182             :     // handle any context sensitive constraints.
    1183         481 :     if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
    1184             :       DEBUG_WITH_TYPE("asm-matcher",
    1185             :                       dbgs() << "Target match predicate failed with diag code "
    1186             :                              << MatchResult << "\n");
    1187             :       Inst.clear();
    1188             :       RetCode = MatchResult;
    1189             :       HadMatchOtherThanPredicate = true;
    1190           0 :       continue;
    1191             :     }
    1192             : 
    1193         481 :     if (!checkAsmTiedOperandConstraints(it->ConvertFn, Operands, ErrorInfo))
    1194             :       return Match_InvalidTiedOperand;
    1195             : 
    1196             :     DEBUG_WITH_TYPE(
    1197             :         "asm-matcher",
    1198             :         dbgs() << "Opcode result: complete match, selecting this opcode\n");
    1199         481 :     return Match_Success;
    1200             :   }
    1201             : 
    1202             :   // Okay, we had no match.  Try to return a useful error code.
    1203           0 :   if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)
    1204             :     return RetCode;
    1205             : 
    1206             :   // Missing feature matches return which features were missing
    1207           0 :   ErrorInfo = MissingFeatures;
    1208           0 :   return Match_MissingFeature;
    1209             : }
    1210             : 
    1211             : namespace {
    1212             :   struct OperandMatchEntry {
    1213             :     uint8_t RequiredFeatures;
    1214             :     uint8_t Mnemonic;
    1215             :     uint8_t Class;
    1216             :     uint8_t OperandMask;
    1217             : 
    1218             :     StringRef getMnemonic() const {
    1219        8194 :       return StringRef(MnemonicTable + Mnemonic + 1,
    1220        8194 :                        MnemonicTable[Mnemonic]);
    1221             :     }
    1222             :   };
    1223             : 
    1224             :   // Predicate for searching for an opcode.
    1225             :   struct LessOpcodeOperand {
    1226             :     bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
    1227        9280 :       return LHS.getMnemonic()  < RHS;
    1228             :     }
    1229             :     bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
    1230        7108 :       return LHS < RHS.getMnemonic();
    1231             :     }
    1232             :     bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
    1233             :       return LHS.getMnemonic() < RHS.getMnemonic();
    1234             :     }
    1235             :   };
    1236             : } // end anonymous namespace.
    1237             : 
    1238             : static const OperandMatchEntry OperandMatchTable[20] = {
    1239             :   /* Operand List Mask, Mnemonic, Operand Class, Features */
    1240             :   { 0, 84 /* ld */, MCK_MemImm, 1 /* 0 */ },
    1241             :   { 0, 84 /* ld */, MCK_MemRegImm, 1 /* 0 */ },
    1242             :   { 0, 84 /* ld */, MCK_MemRegReg, 1 /* 0 */ },
    1243             :   { 0, 87 /* ld.b */, MCK_MemRegReg, 1 /* 0 */ },
    1244             :   { 0, 87 /* ld.b */, MCK_MemSpls, 1 /* 0 */ },
    1245             :   { 0, 92 /* ld.h */, MCK_MemRegReg, 1 /* 0 */ },
    1246             :   { 0, 92 /* ld.h */, MCK_MemSpls, 1 /* 0 */ },
    1247             :   { 0, 179 /* st */, MCK_MemImm, 2 /* 1 */ },
    1248             :   { 0, 179 /* st */, MCK_MemRegImm, 2 /* 1 */ },
    1249             :   { 0, 179 /* st */, MCK_MemRegReg, 2 /* 1 */ },
    1250             :   { 0, 182 /* st.b */, MCK_MemRegReg, 2 /* 1 */ },
    1251             :   { 0, 182 /* st.b */, MCK_MemSpls, 2 /* 1 */ },
    1252             :   { 0, 187 /* st.h */, MCK_MemRegReg, 2 /* 1 */ },
    1253             :   { 0, 187 /* st.h */, MCK_MemSpls, 2 /* 1 */ },
    1254             :   { 0, 221 /* uld */, MCK_MemRegImm, 1 /* 0 */ },
    1255             :   { 0, 221 /* uld */, MCK_MemRegReg, 1 /* 0 */ },
    1256             :   { 0, 225 /* uld.b */, MCK_MemRegReg, 1 /* 0 */ },
    1257             :   { 0, 225 /* uld.b */, MCK_MemSpls, 1 /* 0 */ },
    1258             :   { 0, 231 /* uld.h */, MCK_MemRegReg, 1 /* 0 */ },
    1259             :   { 0, 231 /* uld.h */, MCK_MemSpls, 1 /* 0 */ },
    1260             : };
    1261             : 
    1262         299 : OperandMatchResultTy LanaiAsmParser::
    1263             : tryCustomParseOperand(OperandVector &Operands,
    1264             :                       unsigned MCK) {
    1265             : 
    1266         299 :   switch(MCK) {
    1267         119 :   case MCK_MemImm:
    1268         119 :     return parseMemoryOperand(Operands);
    1269          18 :   case MCK_MemRegImm:
    1270          18 :     return parseMemoryOperand(Operands);
    1271         162 :   case MCK_MemRegReg:
    1272         162 :     return parseMemoryOperand(Operands);
    1273           0 :   case MCK_MemSpls:
    1274           0 :     return parseMemoryOperand(Operands);
    1275             :   default:
    1276             :     return MatchOperand_NoMatch;
    1277             :   }
    1278             :   return MatchOperand_NoMatch;
    1279             : }
    1280             : 
    1281         984 : OperandMatchResultTy LanaiAsmParser::
    1282             : MatchOperandParserImpl(OperandVector &Operands,
    1283             :                        StringRef Mnemonic,
    1284             :                        bool ParseForAllFeatures) {
    1285             :   // Get the current feature set.
    1286         984 :   uint64_t AvailableFeatures = getAvailableFeatures();
    1287             : 
    1288             :   // Get the next operand index.
    1289         984 :   unsigned NextOpNum = Operands.size() - 1;
    1290             :   // Search the table.
    1291             :   auto MnemonicRange =
    1292             :     std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable),
    1293             :                      Mnemonic, LessOpcodeOperand());
    1294             : 
    1295         984 :   if (MnemonicRange.first == MnemonicRange.second)
    1296             :     return MatchOperand_NoMatch;
    1297             : 
    1298         720 :   for (const OperandMatchEntry *it = MnemonicRange.first,
    1299        1319 :        *ie = MnemonicRange.second; it != ie; ++it) {
    1300             :     // equal_range guarantees that instruction mnemonic matches.
    1301             :     assert(Mnemonic == it->getMnemonic());
    1302             : 
    1303             :     // check if the available features match
    1304        1019 :     if (!ParseForAllFeatures && (AvailableFeatures & it->RequiredFeatures) != it->RequiredFeatures)
    1305           0 :         continue;
    1306             : 
    1307             :     // check if the operand in question has a custom parser.
    1308        1019 :     if (!(it->OperandMask & (1 << NextOpNum)))
    1309         720 :       continue;
    1310             : 
    1311             :     // call custom parse method to handle the operand
    1312         299 :     OperandMatchResultTy Result = tryCustomParseOperand(Operands, it->Class);
    1313         299 :     if (Result != MatchOperand_NoMatch)
    1314             :       return Result;
    1315             :   }
    1316             : 
    1317             :   // Okay, we had no match.
    1318             :   return MatchOperand_NoMatch;
    1319             : }
    1320             : 
    1321             : #endif // GET_MATCHER_IMPLEMENTATION
    1322             : 
    1323             : 
    1324             : #ifdef GET_MNEMONIC_SPELL_CHECKER
    1325             : #undef GET_MNEMONIC_SPELL_CHECKER
    1326             : 
    1327             : static std::string LanaiMnemonicSpellCheck(StringRef S, uint64_t FBS, unsigned VariantID) {
    1328             :   const unsigned MaxEditDist = 2;
    1329             :   std::vector<StringRef> Candidates;
    1330             :   StringRef Prev = "";
    1331             : 
    1332             :   // Find the appropriate table for this asm variant.
    1333             :   const MatchEntry *Start, *End;
    1334             :   switch (VariantID) {
    1335             :   default: llvm_unreachable("invalid variant!");
    1336             :   case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
    1337             :   }
    1338             : 
    1339             :   for (auto I = Start; I < End; I++) {
    1340             :     // Ignore unsupported instructions.
    1341             :     if ((FBS & I->RequiredFeatures) != I->RequiredFeatures)
    1342             :       continue;
    1343             : 
    1344             :     StringRef T = I->getMnemonic();
    1345             :     // Avoid recomputing the edit distance for the same string.
    1346             :     if (T.equals(Prev))
    1347             :       continue;
    1348             : 
    1349             :     Prev = T;
    1350             :     unsigned Dist = S.edit_distance(T, false, MaxEditDist);
    1351             :     if (Dist <= MaxEditDist)
    1352             :       Candidates.push_back(T);
    1353             :   }
    1354             : 
    1355             :   if (Candidates.empty())
    1356             :     return "";
    1357             : 
    1358             :   std::string Res = ", did you mean: ";
    1359             :   unsigned i = 0;
    1360             :   for( ; i < Candidates.size() - 1; i++)
    1361             :     Res += Candidates[i].str() + ", ";
    1362             :   return Res + Candidates[i].str() + "?";
    1363             : }
    1364             : 
    1365             : #endif // GET_MNEMONIC_SPELL_CHECKER
    1366             : 

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