LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/Lanai - LanaiGenInstrInfo.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 12 12 100.0 %
Date: 2018-02-19 17:12:42 Functions: 2 4 50.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Target Instruction Enum Values and Descriptors                             *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : #ifdef GET_INSTRINFO_ENUM
      10             : #undef GET_INSTRINFO_ENUM
      11             : namespace llvm {
      12             : 
      13             : namespace Lanai {
      14             :   enum {
      15             :     PHI = 0,
      16             :     INLINEASM   = 1,
      17             :     CFI_INSTRUCTION     = 2,
      18             :     EH_LABEL    = 3,
      19             :     GC_LABEL    = 4,
      20             :     ANNOTATION_LABEL    = 5,
      21             :     KILL        = 6,
      22             :     EXTRACT_SUBREG      = 7,
      23             :     INSERT_SUBREG       = 8,
      24             :     IMPLICIT_DEF        = 9,
      25             :     SUBREG_TO_REG       = 10,
      26             :     COPY_TO_REGCLASS    = 11,
      27             :     DBG_VALUE   = 12,
      28             :     REG_SEQUENCE        = 13,
      29             :     COPY        = 14,
      30             :     BUNDLE      = 15,
      31             :     LIFETIME_START      = 16,
      32             :     LIFETIME_END        = 17,
      33             :     STACKMAP    = 18,
      34             :     FENTRY_CALL = 19,
      35             :     PATCHPOINT  = 20,
      36             :     LOAD_STACK_GUARD    = 21,
      37             :     STATEPOINT  = 22,
      38             :     LOCAL_ESCAPE        = 23,
      39             :     FAULTING_OP = 24,
      40             :     PATCHABLE_OP        = 25,
      41             :     PATCHABLE_FUNCTION_ENTER    = 26,
      42             :     PATCHABLE_RET       = 27,
      43             :     PATCHABLE_FUNCTION_EXIT     = 28,
      44             :     PATCHABLE_TAIL_CALL = 29,
      45             :     PATCHABLE_EVENT_CALL        = 30,
      46             :     G_ADD       = 31,
      47             :     G_SUB       = 32,
      48             :     G_MUL       = 33,
      49             :     G_SDIV      = 34,
      50             :     G_UDIV      = 35,
      51             :     G_SREM      = 36,
      52             :     G_UREM      = 37,
      53             :     G_AND       = 38,
      54             :     G_OR        = 39,
      55             :     G_XOR       = 40,
      56             :     G_IMPLICIT_DEF      = 41,
      57             :     G_PHI       = 42,
      58             :     G_FRAME_INDEX       = 43,
      59             :     G_GLOBAL_VALUE      = 44,
      60             :     G_EXTRACT   = 45,
      61             :     G_UNMERGE_VALUES    = 46,
      62             :     G_INSERT    = 47,
      63             :     G_MERGE_VALUES      = 48,
      64             :     G_PTRTOINT  = 49,
      65             :     G_INTTOPTR  = 50,
      66             :     G_BITCAST   = 51,
      67             :     G_LOAD      = 52,
      68             :     G_STORE     = 53,
      69             :     G_ATOMIC_CMPXCHG_WITH_SUCCESS       = 54,
      70             :     G_ATOMIC_CMPXCHG    = 55,
      71             :     G_ATOMICRMW_XCHG    = 56,
      72             :     G_ATOMICRMW_ADD     = 57,
      73             :     G_ATOMICRMW_SUB     = 58,
      74             :     G_ATOMICRMW_AND     = 59,
      75             :     G_ATOMICRMW_NAND    = 60,
      76             :     G_ATOMICRMW_OR      = 61,
      77             :     G_ATOMICRMW_XOR     = 62,
      78             :     G_ATOMICRMW_MAX     = 63,
      79             :     G_ATOMICRMW_MIN     = 64,
      80             :     G_ATOMICRMW_UMAX    = 65,
      81             :     G_ATOMICRMW_UMIN    = 66,
      82             :     G_BRCOND    = 67,
      83             :     G_BRINDIRECT        = 68,
      84             :     G_INTRINSIC = 69,
      85             :     G_INTRINSIC_W_SIDE_EFFECTS  = 70,
      86             :     G_ANYEXT    = 71,
      87             :     G_TRUNC     = 72,
      88             :     G_CONSTANT  = 73,
      89             :     G_FCONSTANT = 74,
      90             :     G_VASTART   = 75,
      91             :     G_VAARG     = 76,
      92             :     G_SEXT      = 77,
      93             :     G_ZEXT      = 78,
      94             :     G_SHL       = 79,
      95             :     G_LSHR      = 80,
      96             :     G_ASHR      = 81,
      97             :     G_ICMP      = 82,
      98             :     G_FCMP      = 83,
      99             :     G_SELECT    = 84,
     100             :     G_UADDE     = 85,
     101             :     G_USUBE     = 86,
     102             :     G_SADDO     = 87,
     103             :     G_SSUBO     = 88,
     104             :     G_UMULO     = 89,
     105             :     G_SMULO     = 90,
     106             :     G_UMULH     = 91,
     107             :     G_SMULH     = 92,
     108             :     G_FADD      = 93,
     109             :     G_FSUB      = 94,
     110             :     G_FMUL      = 95,
     111             :     G_FMA       = 96,
     112             :     G_FDIV      = 97,
     113             :     G_FREM      = 98,
     114             :     G_FPOW      = 99,
     115             :     G_FEXP      = 100,
     116             :     G_FEXP2     = 101,
     117             :     G_FLOG      = 102,
     118             :     G_FLOG2     = 103,
     119             :     G_FNEG      = 104,
     120             :     G_FPEXT     = 105,
     121             :     G_FPTRUNC   = 106,
     122             :     G_FPTOSI    = 107,
     123             :     G_FPTOUI    = 108,
     124             :     G_SITOFP    = 109,
     125             :     G_UITOFP    = 110,
     126             :     G_GEP       = 111,
     127             :     G_PTR_MASK  = 112,
     128             :     G_BR        = 113,
     129             :     G_INSERT_VECTOR_ELT = 114,
     130             :     G_EXTRACT_VECTOR_ELT        = 115,
     131             :     G_SHUFFLE_VECTOR    = 116,
     132             :     G_BSWAP     = 117,
     133             :     ADDC_F_I_HI = 118,
     134             :     ADDC_F_I_LO = 119,
     135             :     ADDC_F_R    = 120,
     136             :     ADDC_I_HI   = 121,
     137             :     ADDC_I_LO   = 122,
     138             :     ADDC_R      = 123,
     139             :     ADD_F_I_HI  = 124,
     140             :     ADD_F_I_LO  = 125,
     141             :     ADD_F_R     = 126,
     142             :     ADD_I_HI    = 127,
     143             :     ADD_I_LO    = 128,
     144             :     ADD_R       = 129,
     145             :     ADJCALLSTACKDOWN    = 130,
     146             :     ADJCALLSTACKUP      = 131,
     147             :     ADJDYNALLOC = 132,
     148             :     AND_F_I_HI  = 133,
     149             :     AND_F_I_LO  = 134,
     150             :     AND_F_R     = 135,
     151             :     AND_I_HI    = 136,
     152             :     AND_I_LO    = 137,
     153             :     AND_R       = 138,
     154             :     BRCC        = 139,
     155             :     BRIND_CC    = 140,
     156             :     BRIND_CCA   = 141,
     157             :     BRR = 142,
     158             :     BT  = 143,
     159             :     CALL        = 144,
     160             :     CALLR       = 145,
     161             :     JR  = 146,
     162             :     LDADDR      = 147,
     163             :     LDBs_RI     = 148,
     164             :     LDBs_RR     = 149,
     165             :     LDBz_RI     = 150,
     166             :     LDBz_RR     = 151,
     167             :     LDHs_RI     = 152,
     168             :     LDHs_RR     = 153,
     169             :     LDHz_RI     = 154,
     170             :     LDHz_RR     = 155,
     171             :     LDW_RI      = 156,
     172             :     LDW_RR      = 157,
     173             :     LDWz_RR     = 158,
     174             :     LEADZ       = 159,
     175             :     LOG0        = 160,
     176             :     LOG1        = 161,
     177             :     LOG2        = 162,
     178             :     LOG3        = 163,
     179             :     LOG4        = 164,
     180             :     MOVHI       = 165,
     181             :     NOP = 166,
     182             :     OR_F_I_HI   = 167,
     183             :     OR_F_I_LO   = 168,
     184             :     OR_F_R      = 169,
     185             :     OR_I_HI     = 170,
     186             :     OR_I_LO     = 171,
     187             :     OR_R        = 172,
     188             :     POPC        = 173,
     189             :     RET = 174,
     190             :     SA_F_I      = 175,
     191             :     SA_I        = 176,
     192             :     SCC = 177,
     193             :     SELECT      = 178,
     194             :     SFSUB_F_RI_HI       = 179,
     195             :     SFSUB_F_RI_LO       = 180,
     196             :     SFSUB_F_RR  = 181,
     197             :     SHL_F_R     = 182,
     198             :     SHL_R       = 183,
     199             :     SLI = 184,
     200             :     SL_F_I      = 185,
     201             :     SL_I        = 186,
     202             :     SRA_F_R     = 187,
     203             :     SRA_R       = 188,
     204             :     SRL_F_R     = 189,
     205             :     SRL_R       = 190,
     206             :     STADDR      = 191,
     207             :     STB_RI      = 192,
     208             :     STB_RR      = 193,
     209             :     STH_RI      = 194,
     210             :     STH_RR      = 195,
     211             :     SUBB_F_I_HI = 196,
     212             :     SUBB_F_I_LO = 197,
     213             :     SUBB_F_R    = 198,
     214             :     SUBB_I_HI   = 199,
     215             :     SUBB_I_LO   = 200,
     216             :     SUBB_R      = 201,
     217             :     SUB_F_I_HI  = 202,
     218             :     SUB_F_I_LO  = 203,
     219             :     SUB_F_R     = 204,
     220             :     SUB_I_HI    = 205,
     221             :     SUB_I_LO    = 206,
     222             :     SUB_R       = 207,
     223             :     SW_RI       = 208,
     224             :     SW_RR       = 209,
     225             :     TRAILZ      = 210,
     226             :     XOR_F_I_HI  = 211,
     227             :     XOR_F_I_LO  = 212,
     228             :     XOR_F_R     = 213,
     229             :     XOR_I_HI    = 214,
     230             :     XOR_I_LO    = 215,
     231             :     XOR_R       = 216,
     232             :     INSTRUCTION_LIST_END = 217
     233             :   };
     234             : 
     235             : } // end Lanai namespace
     236             : } // end llvm namespace
     237             : #endif // GET_INSTRINFO_ENUM
     238             : 
     239             : #ifdef GET_INSTRINFO_SCHED_ENUM
     240             : #undef GET_INSTRINFO_SCHED_ENUM
     241             : namespace llvm {
     242             : 
     243             : namespace Lanai {
     244             : namespace Sched {
     245             :   enum {
     246             :     NoInstrModel        = 0,
     247             :     IIC_ALU_WriteALU    = 1,
     248             :     IIC_ALU     = 2,
     249             :     IIC_LD_WriteLD      = 3,
     250             :     IIC_LDSW_WriteLDSW  = 4,
     251             :     WriteLD     = 5,
     252             :     IIC_ST_WriteST      = 6,
     253             :     IIC_STSW_WriteSTSW  = 7,
     254             :     SCHED_LIST_END = 8
     255             :   };
     256             : } // end Sched namespace
     257             : } // end Lanai namespace
     258             : } // end llvm namespace
     259             : #endif // GET_INSTRINFO_SCHED_ENUM
     260             : 
     261             : #ifdef GET_INSTRINFO_MC_DESC
     262             : #undef GET_INSTRINFO_MC_DESC
     263             : namespace llvm {
     264             : 
     265             : static const MCPhysReg ImplicitList1[] = { Lanai::SR, 0 };
     266             : static const MCPhysReg ImplicitList2[] = { Lanai::SP, 0 };
     267             : static const MCPhysReg ImplicitList3[] = { Lanai::RCA, 0 };
     268             : 
     269             : static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     270             : static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     271             : static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     272             : static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     273             : static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     274             : static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     275             : static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     276             : static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     277             : static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
     278             : static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     279             : static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     280             : static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     281             : static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     282             : static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     283             : static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
     284             : static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     285             : static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     286             : static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     287             : static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     288             : static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
     289             : static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
     290             : static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     291             : static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     292             : static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
     293             : static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     294             : static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
     295             : static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
     296             : static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
     297             : static const MCOperandInfo OperandInfo30[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     298             : static const MCOperandInfo OperandInfo31[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
     299             : static const MCOperandInfo OperandInfo32[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     300             : static const MCOperandInfo OperandInfo33[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     301             : static const MCOperandInfo OperandInfo34[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     302             : static const MCOperandInfo OperandInfo35[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     303             : static const MCOperandInfo OperandInfo36[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     304             : static const MCOperandInfo OperandInfo37[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     305             : static const MCOperandInfo OperandInfo38[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     306             : 
     307             : extern const MCInstrDesc LanaiInsts[] = {
     308             :   { 0,  1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #0 = PHI
     309             :   { 1,  0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
     310             :   { 2,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #2 = CFI_INSTRUCTION
     311             :   { 3,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #3 = EH_LABEL
     312             :   { 4,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #4 = GC_LABEL
     313             :   { 5,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #5 = ANNOTATION_LABEL
     314             :   { 6,  0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #6 = KILL
     315             :   { 7,  3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #7 = EXTRACT_SUBREG
     316             :   { 8,  4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #8 = INSERT_SUBREG
     317             :   { 9,  1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #9 = IMPLICIT_DEF
     318             :   { 10, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #10 = SUBREG_TO_REG
     319             :   { 11, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #11 = COPY_TO_REGCLASS
     320             :   { 12, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #12 = DBG_VALUE
     321             :   { 13, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #13 = REG_SEQUENCE
     322             :   { 14, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #14 = COPY
     323             :   { 15, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #15 = BUNDLE
     324             :   { 16, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #16 = LIFETIME_START
     325             :   { 17, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #17 = LIFETIME_END
     326             :   { 18, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #18 = STACKMAP
     327             :   { 19, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #19 = FENTRY_CALL
     328             :   { 20, 6,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #20 = PATCHPOINT
     329             :   { 21, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #21 = LOAD_STACK_GUARD
     330             :   { 22, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #22 = STATEPOINT
     331             :   { 23, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #23 = LOCAL_ESCAPE
     332             :   { 24, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #24 = FAULTING_OP
     333             :   { 25, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #25 = PATCHABLE_OP
     334             :   { 26, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #26 = PATCHABLE_FUNCTION_ENTER
     335             :   { 27, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #27 = PATCHABLE_RET
     336             :   { 28, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #28 = PATCHABLE_FUNCTION_EXIT
     337             :   { 29, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #29 = PATCHABLE_TAIL_CALL
     338             :   { 30, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #30 = PATCHABLE_EVENT_CALL
     339             :   { 31, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #31 = G_ADD
     340             :   { 32, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #32 = G_SUB
     341             :   { 33, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #33 = G_MUL
     342             :   { 34, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #34 = G_SDIV
     343             :   { 35, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #35 = G_UDIV
     344             :   { 36, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #36 = G_SREM
     345             :   { 37, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #37 = G_UREM
     346             :   { 38, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #38 = G_AND
     347             :   { 39, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #39 = G_OR
     348             :   { 40, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #40 = G_XOR
     349             :   { 41, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #41 = G_IMPLICIT_DEF
     350             :   { 42, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #42 = G_PHI
     351             :   { 43, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #43 = G_FRAME_INDEX
     352             :   { 44, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #44 = G_GLOBAL_VALUE
     353             :   { 45, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #45 = G_EXTRACT
     354             :   { 46, 2,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #46 = G_UNMERGE_VALUES
     355             :   { 47, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #47 = G_INSERT
     356             :   { 48, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #48 = G_MERGE_VALUES
     357             :   { 49, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #49 = G_PTRTOINT
     358             :   { 50, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #50 = G_INTTOPTR
     359             :   { 51, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #51 = G_BITCAST
     360             :   { 52, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #52 = G_LOAD
     361             :   { 53, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #53 = G_STORE
     362             :   { 54, 5,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #54 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
     363             :   { 55, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #55 = G_ATOMIC_CMPXCHG
     364             :   { 56, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #56 = G_ATOMICRMW_XCHG
     365             :   { 57, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #57 = G_ATOMICRMW_ADD
     366             :   { 58, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #58 = G_ATOMICRMW_SUB
     367             :   { 59, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #59 = G_ATOMICRMW_AND
     368             :   { 60, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #60 = G_ATOMICRMW_NAND
     369             :   { 61, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #61 = G_ATOMICRMW_OR
     370             :   { 62, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #62 = G_ATOMICRMW_XOR
     371             :   { 63, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #63 = G_ATOMICRMW_MAX
     372             :   { 64, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #64 = G_ATOMICRMW_MIN
     373             :   { 65, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #65 = G_ATOMICRMW_UMAX
     374             :   { 66, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #66 = G_ATOMICRMW_UMIN
     375             :   { 67, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #67 = G_BRCOND
     376             :   { 68, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #68 = G_BRINDIRECT
     377             :   { 69, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #69 = G_INTRINSIC
     378             :   { 70, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #70 = G_INTRINSIC_W_SIDE_EFFECTS
     379             :   { 71, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #71 = G_ANYEXT
     380             :   { 72, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #72 = G_TRUNC
     381             :   { 73, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #73 = G_CONSTANT
     382             :   { 74, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #74 = G_FCONSTANT
     383             :   { 75, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #75 = G_VASTART
     384             :   { 76, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #76 = G_VAARG
     385             :   { 77, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #77 = G_SEXT
     386             :   { 78, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #78 = G_ZEXT
     387             :   { 79, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #79 = G_SHL
     388             :   { 80, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #80 = G_LSHR
     389             :   { 81, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #81 = G_ASHR
     390             :   { 82, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #82 = G_ICMP
     391             :   { 83, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #83 = G_FCMP
     392             :   { 84, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #84 = G_SELECT
     393             :   { 85, 5,      2,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #85 = G_UADDE
     394             :   { 86, 5,      2,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #86 = G_USUBE
     395             :   { 87, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #87 = G_SADDO
     396             :   { 88, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #88 = G_SSUBO
     397             :   { 89, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #89 = G_UMULO
     398             :   { 90, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #90 = G_SMULO
     399             :   { 91, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #91 = G_UMULH
     400             :   { 92, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #92 = G_SMULH
     401             :   { 93, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #93 = G_FADD
     402             :   { 94, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #94 = G_FSUB
     403             :   { 95, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #95 = G_FMUL
     404             :   { 96, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #96 = G_FMA
     405             :   { 97, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #97 = G_FDIV
     406             :   { 98, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #98 = G_FREM
     407             :   { 99, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #99 = G_FPOW
     408             :   { 100,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #100 = G_FEXP
     409             :   { 101,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #101 = G_FEXP2
     410             :   { 102,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #102 = G_FLOG
     411             :   { 103,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #103 = G_FLOG2
     412             :   { 104,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #104 = G_FNEG
     413             :   { 105,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #105 = G_FPEXT
     414             :   { 106,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #106 = G_FPTRUNC
     415             :   { 107,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #107 = G_FPTOSI
     416             :   { 108,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #108 = G_FPTOUI
     417             :   { 109,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #109 = G_SITOFP
     418             :   { 110,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #110 = G_UITOFP
     419             :   { 111,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #111 = G_GEP
     420             :   { 112,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #112 = G_PTR_MASK
     421             :   { 113,        1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #113 = G_BR
     422             :   { 114,        4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #114 = G_INSERT_VECTOR_ELT
     423             :   { 115,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #115 = G_EXTRACT_VECTOR_ELT
     424             :   { 116,        4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #116 = G_SHUFFLE_VECTOR
     425             :   { 117,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #117 = G_BSWAP
     426             :   { 118,        3,      1,      4,      1,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo30, -1 ,nullptr },  // Inst #118 = ADDC_F_I_HI
     427             :   { 119,        3,      1,      4,      1,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo30, -1 ,nullptr },  // Inst #119 = ADDC_F_I_LO
     428             :   { 120,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #120 = ADDC_F_R
     429             :   { 121,        3,      1,      4,      1,      0, 0x0ULL, ImplicitList1, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #121 = ADDC_I_HI
     430             :   { 122,        3,      1,      4,      1,      0, 0x0ULL, ImplicitList1, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #122 = ADDC_I_LO
     431             :   { 123,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable), 0x0ULL, ImplicitList1, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #123 = ADDC_R
     432             :   { 124,        3,      1,      4,      1,      0, 0x0ULL, nullptr, ImplicitList1, OperandInfo30, -1 ,nullptr },  // Inst #124 = ADD_F_I_HI
     433             :   { 125,        3,      1,      4,      1,      0, 0x0ULL, nullptr, ImplicitList1, OperandInfo30, -1 ,nullptr },  // Inst #125 = ADD_F_I_LO
     434             :   { 126,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #126 = ADD_F_R
     435             :   { 127,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #127 = ADD_I_HI
     436             :   { 128,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #128 = ADD_I_LO
     437             :   { 129,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #129 = ADD_R
     438             :   { 130,        2,      0,      4,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo8, -1 ,nullptr },  // Inst #130 = ADJCALLSTACKDOWN
     439             :   { 131,        2,      0,      4,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo8, -1 ,nullptr },  // Inst #131 = ADJCALLSTACKUP
     440             :   { 132,        2,      1,      4,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo32, -1 ,nullptr },  // Inst #132 = ADJDYNALLOC
     441             :   { 133,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, ImplicitList1, OperandInfo30, -1 ,nullptr },  // Inst #133 = AND_F_I_HI
     442             :   { 134,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, ImplicitList1, OperandInfo30, -1 ,nullptr },  // Inst #134 = AND_F_I_LO
     443             :   { 135,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #135 = AND_F_R
     444             :   { 136,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #136 = AND_I_HI
     445             :   { 137,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #137 = AND_I_LO
     446             :   { 138,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #138 = AND_R
     447             :   { 139,        2,      0,      4,      2,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #139 = BRCC
     448             :   { 140,        2,      0,      4,      1,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #140 = BRIND_CC
     449             :   { 141,        3,      0,      4,      1,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #141 = BRIND_CCA
     450             :   { 142,        2,      0,      4,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #142 = BRR
     451             :   { 143,        1,      0,      4,      2,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #143 = BT
     452             :   { 144,        1,      0,      4,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo2, -1 ,nullptr },  // Inst #144 = CALL
     453             :   { 145,        1,      0,      4,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo35, -1 ,nullptr },  // Inst #145 = CALLR
     454             :   { 146,        1,      0,      4,      1,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #146 = JR
     455             :   { 147,        2,      1,      4,      3,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #147 = LDADDR
     456             :   { 148,        4,      1,      4,      4,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #148 = LDBs_RI
     457             :   { 149,        4,      1,      4,      5,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #149 = LDBs_RR
     458             :   { 150,        4,      1,      4,      4,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #150 = LDBz_RI
     459             :   { 151,        4,      1,      4,      5,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #151 = LDBz_RR
     460             :   { 152,        4,      1,      4,      4,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #152 = LDHs_RI
     461             :   { 153,        4,      1,      4,      5,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #153 = LDHs_RR
     462             :   { 154,        4,      1,      4,      4,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #154 = LDHz_RI
     463             :   { 155,        4,      1,      4,      5,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #155 = LDHz_RR
     464             :   { 156,        4,      1,      4,      3,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #156 = LDW_RI
     465             :   { 157,        4,      1,      4,      5,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #157 = LDW_RR
     466             :   { 158,        4,      1,      4,      5,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #158 = LDWz_RR
     467             :   { 159,        2,      1,      4,      1,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #159 = LEADZ
     468             :   { 160,        0,      0,      4,      0,      0, 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #160 = LOG0
     469             :   { 161,        0,      0,      4,      0,      0, 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #161 = LOG1
     470             :   { 162,        0,      0,      4,      0,      0, 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #162 = LOG2
     471             :   { 163,        0,      0,      4,      0,      0, 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #163 = LOG3
     472             :   { 164,        0,      0,      4,      0,      0, 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #164 = LOG4
     473             :   { 165,        2,      1,      4,      1,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #165 = MOVHI
     474             :   { 166,        0,      0,      4,      0,      0, 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #166 = NOP
     475             :   { 167,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, ImplicitList1, OperandInfo30, -1 ,nullptr },  // Inst #167 = OR_F_I_HI
     476             :   { 168,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, ImplicitList1, OperandInfo30, -1 ,nullptr },  // Inst #168 = OR_F_I_LO
     477             :   { 169,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #169 = OR_F_R
     478             :   { 170,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #170 = OR_I_HI
     479             :   { 171,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #171 = OR_I_LO
     480             :   { 172,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #172 = OR_R
     481             :   { 173,        2,      1,      4,      1,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #173 = POPC
     482             :   { 174,        0,      0,      4,      0,      0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList3, nullptr, nullptr, -1 ,nullptr },  // Inst #174 = RET
     483             :   { 175,        3,      1,      4,      1,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo30, -1 ,nullptr },  // Inst #175 = SA_F_I
     484             :   { 176,        3,      1,      4,      1,      0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #176 = SA_I
     485             :   { 177,        2,      1,      4,      2,      0, 0x0ULL, ImplicitList1, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #177 = SCC
     486             :   { 178,        4,      1,      4,      1,      0|(1ULL<<MCID::Select), 0x0ULL, ImplicitList1, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #178 = SELECT
     487             :   { 179,        2,      0,      4,      1,      0|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #179 = SFSUB_F_RI_HI
     488             :   { 180,        2,      0,      4,      1,      0|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #180 = SFSUB_F_RI_LO
     489             :   { 181,        2,      0,      4,      1,      0|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #181 = SFSUB_F_RR
     490             :   { 182,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #182 = SHL_F_R
     491             :   { 183,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #183 = SHL_R
     492             :   { 184,        2,      1,      4,      0,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #184 = SLI
     493             :   { 185,        3,      1,      4,      1,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo30, -1 ,nullptr },  // Inst #185 = SL_F_I
     494             :   { 186,        3,      1,      4,      1,      0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #186 = SL_I
     495             :   { 187,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #187 = SRA_F_R
     496             :   { 188,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #188 = SRA_R
     497             :   { 189,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #189 = SRL_F_R
     498             :   { 190,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #190 = SRL_R
     499             :   { 191,        2,      0,      4,      6,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #191 = STADDR
     500             :   { 192,        4,      0,      4,      7,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #192 = STB_RI
     501             :   { 193,        4,      0,      4,      6,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #193 = STB_RR
     502             :   { 194,        4,      0,      4,      7,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #194 = STH_RI
     503             :   { 195,        4,      0,      4,      6,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #195 = STH_RR
     504             :   { 196,        3,      1,      4,      1,      0|(1ULL<<MCID::CheapAsAMove), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo30, -1 ,nullptr },  // Inst #196 = SUBB_F_I_HI
     505             :   { 197,        3,      1,      4,      1,      0|(1ULL<<MCID::CheapAsAMove), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo30, -1 ,nullptr },  // Inst #197 = SUBB_F_I_LO
     506             :   { 198,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #198 = SUBB_F_R
     507             :   { 199,        3,      1,      4,      1,      0, 0x0ULL, ImplicitList1, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #199 = SUBB_I_HI
     508             :   { 200,        3,      1,      4,      1,      0, 0x0ULL, ImplicitList1, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #200 = SUBB_I_LO
     509             :   { 201,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable), 0x0ULL, ImplicitList1, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #201 = SUBB_R
     510             :   { 202,        3,      1,      4,      1,      0, 0x0ULL, nullptr, ImplicitList1, OperandInfo30, -1 ,nullptr },  // Inst #202 = SUB_F_I_HI
     511             :   { 203,        3,      1,      4,      1,      0, 0x0ULL, nullptr, ImplicitList1, OperandInfo30, -1 ,nullptr },  // Inst #203 = SUB_F_I_LO
     512             :   { 204,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #204 = SUB_F_R
     513             :   { 205,        3,      1,      4,      1,      0|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #205 = SUB_I_HI
     514             :   { 206,        3,      1,      4,      1,      0|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #206 = SUB_I_LO
     515             :   { 207,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #207 = SUB_R
     516             :   { 208,        4,      0,      4,      6,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #208 = SW_RI
     517             :   { 209,        4,      0,      4,      6,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #209 = SW_RR
     518             :   { 210,        2,      1,      4,      1,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #210 = TRAILZ
     519             :   { 211,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, ImplicitList1, OperandInfo30, -1 ,nullptr },  // Inst #211 = XOR_F_I_HI
     520             :   { 212,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, ImplicitList1, OperandInfo30, -1 ,nullptr },  // Inst #212 = XOR_F_I_LO
     521             :   { 213,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #213 = XOR_F_R
     522             :   { 214,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #214 = XOR_I_HI
     523             :   { 215,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #215 = XOR_I_LO
     524             :   { 216,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #216 = XOR_R
     525             : };
     526             : 
     527             : extern const char LanaiInstrNameData[] = {
     528             :   /* 0 */ 'L', 'O', 'G', '0', 0,
     529             :   /* 5 */ 'L', 'O', 'G', '1', 0,
     530             :   /* 10 */ 'G', '_', 'F', 'L', 'O', 'G', '2', 0,
     531             :   /* 18 */ 'G', '_', 'F', 'E', 'X', 'P', '2', 0,
     532             :   /* 26 */ 'L', 'O', 'G', '3', 0,
     533             :   /* 31 */ 'L', 'O', 'G', '4', 0,
     534             :   /* 36 */ 'B', 'R', 'I', 'N', 'D', '_', 'C', 'C', 'A', 0,
     535             :   /* 46 */ 'G', '_', 'F', 'M', 'A', 0,
     536             :   /* 52 */ 'G', '_', 'F', 'S', 'U', 'B', 0,
     537             :   /* 59 */ 'G', '_', 'S', 'U', 'B', 0,
     538             :   /* 65 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'S', 'U', 'B', 0,
     539             :   /* 81 */ 'B', 'R', 'C', 'C', 0,
     540             :   /* 86 */ 'S', 'C', 'C', 0,
     541             :   /* 90 */ 'B', 'R', 'I', 'N', 'D', '_', 'C', 'C', 0,
     542             :   /* 99 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', 0,
     543             :   /* 111 */ 'G', '_', 'F', 'P', 'T', 'R', 'U', 'N', 'C', 0,
     544             :   /* 121 */ 'G', '_', 'T', 'R', 'U', 'N', 'C', 0,
     545             :   /* 129 */ 'A', 'D', 'J', 'D', 'Y', 'N', 'A', 'L', 'L', 'O', 'C', 0,
     546             :   /* 141 */ 'P', 'O', 'P', 'C', 0,
     547             :   /* 146 */ 'G', '_', 'L', 'O', 'A', 'D', 0,
     548             :   /* 153 */ 'G', '_', 'F', 'A', 'D', 'D', 0,
     549             :   /* 160 */ 'G', '_', 'A', 'D', 'D', 0,
     550             :   /* 166 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'D', 'D', 0,
     551             :   /* 182 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'N', 'A', 'N', 'D', 0,
     552             :   /* 199 */ 'G', '_', 'A', 'N', 'D', 0,
     553             :   /* 205 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'N', 'D', 0,
     554             :   /* 221 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
     555             :   /* 234 */ 'G', '_', 'B', 'R', 'C', 'O', 'N', 'D', 0,
     556             :   /* 243 */ 'L', 'O', 'A', 'D', '_', 'S', 'T', 'A', 'C', 'K', '_', 'G', 'U', 'A', 'R', 'D', 0,
     557             :   /* 260 */ 'G', '_', 'U', 'S', 'U', 'B', 'E', 0,
     558             :   /* 268 */ 'R', 'E', 'G', '_', 'S', 'E', 'Q', 'U', 'E', 'N', 'C', 'E', 0,
     559             :   /* 281 */ 'G', '_', 'U', 'A', 'D', 'D', 'E', 0,
     560             :   /* 289 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
     561             :   /* 296 */ 'L', 'O', 'C', 'A', 'L', '_', 'E', 'S', 'C', 'A', 'P', 'E', 0,
     562             :   /* 309 */ 'G', '_', 'S', 'T', 'O', 'R', 'E', 0,
     563             :   /* 317 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
     564             :   /* 327 */ 'G', '_', 'G', 'L', 'O', 'B', 'A', 'L', '_', 'V', 'A', 'L', 'U', 'E', 0,
     565             :   /* 342 */ 'G', '_', 'I', 'M', 'P', 'L', 'I', 'C', 'I', 'T', '_', 'D', 'E', 'F', 0,
     566             :   /* 357 */ 'G', '_', 'F', 'N', 'E', 'G', 0,
     567             :   /* 364 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
     568             :   /* 379 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
     569             :   /* 393 */ 'S', 'U', 'B', 'R', 'E', 'G', '_', 'T', 'O', '_', 'R', 'E', 'G', 0,
     570             :   /* 407 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', 0,
     571             :   /* 424 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'C', 'H', 'G', 0,
     572             :   /* 441 */ 'G', '_', 'F', 'L', 'O', 'G', 0,
     573             :   /* 448 */ 'G', '_', 'V', 'A', 'A', 'R', 'G', 0,
     574             :   /* 456 */ 'G', '_', 'S', 'M', 'U', 'L', 'H', 0,
     575             :   /* 464 */ 'G', '_', 'U', 'M', 'U', 'L', 'H', 0,
     576             :   /* 472 */ 'G', '_', 'P', 'H', 'I', 0,
     577             :   /* 478 */ 'M', 'O', 'V', 'H', 'I', 0,
     578             :   /* 484 */ 'S', 'F', 'S', 'U', 'B', '_', 'F', '_', 'R', 'I', '_', 'H', 'I', 0,
     579             :   /* 498 */ 'S', 'U', 'B', 'B', '_', 'I', '_', 'H', 'I', 0,
     580             :   /* 508 */ 'S', 'U', 'B', '_', 'I', '_', 'H', 'I', 0,
     581             :   /* 517 */ 'A', 'D', 'D', 'C', '_', 'I', '_', 'H', 'I', 0,
     582             :   /* 527 */ 'A', 'D', 'D', '_', 'I', '_', 'H', 'I', 0,
     583             :   /* 536 */ 'A', 'N', 'D', '_', 'I', '_', 'H', 'I', 0,
     584             :   /* 545 */ 'S', 'U', 'B', 'B', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
     585             :   /* 557 */ 'S', 'U', 'B', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
     586             :   /* 568 */ 'A', 'D', 'D', 'C', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
     587             :   /* 580 */ 'A', 'D', 'D', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
     588             :   /* 591 */ 'A', 'N', 'D', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
     589             :   /* 602 */ 'X', 'O', 'R', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
     590             :   /* 613 */ 'X', 'O', 'R', '_', 'I', '_', 'H', 'I', 0,
     591             :   /* 622 */ 'S', 'L', 'I', 0,
     592             :   /* 626 */ 'S', 'T', 'B', '_', 'R', 'I', 0,
     593             :   /* 633 */ 'S', 'T', 'H', '_', 'R', 'I', 0,
     594             :   /* 640 */ 'L', 'D', 'W', '_', 'R', 'I', 0,
     595             :   /* 647 */ 'S', 'W', '_', 'R', 'I', 0,
     596             :   /* 653 */ 'L', 'D', 'B', 's', '_', 'R', 'I', 0,
     597             :   /* 661 */ 'L', 'D', 'H', 's', '_', 'R', 'I', 0,
     598             :   /* 669 */ 'L', 'D', 'B', 'z', '_', 'R', 'I', 0,
     599             :   /* 677 */ 'L', 'D', 'H', 'z', '_', 'R', 'I', 0,
     600             :   /* 685 */ 'G', '_', 'F', 'P', 'T', 'O', 'S', 'I', 0,
     601             :   /* 694 */ 'G', '_', 'F', 'P', 'T', 'O', 'U', 'I', 0,
     602             :   /* 703 */ 'S', 'A', '_', 'I', 0,
     603             :   /* 708 */ 'S', 'A', '_', 'F', '_', 'I', 0,
     604             :   /* 715 */ 'S', 'L', '_', 'F', '_', 'I', 0,
     605             :   /* 722 */ 'S', 'L', '_', 'I', 0,
     606             :   /* 727 */ 'G', '_', 'P', 'T', 'R', '_', 'M', 'A', 'S', 'K', 0,
     607             :   /* 738 */ 'G', 'C', '_', 'L', 'A', 'B', 'E', 'L', 0,
     608             :   /* 747 */ 'E', 'H', '_', 'L', 'A', 'B', 'E', 'L', 0,
     609             :   /* 756 */ 'A', 'N', 'N', 'O', 'T', 'A', 'T', 'I', 'O', 'N', '_', 'L', 'A', 'B', 'E', 'L', 0,
     610             :   /* 773 */ 'G', '_', 'S', 'H', 'L', 0,
     611             :   /* 779 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'A', 'I', 'L', '_', 'C', 'A', 'L', 'L', 0,
     612             :   /* 799 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
     613             :   /* 820 */ 'F', 'E', 'N', 'T', 'R', 'Y', '_', 'C', 'A', 'L', 'L', 0,
     614             :   /* 832 */ 'K', 'I', 'L', 'L', 0,
     615             :   /* 837 */ 'G', '_', 'F', 'M', 'U', 'L', 0,
     616             :   /* 844 */ 'G', '_', 'M', 'U', 'L', 0,
     617             :   /* 850 */ 'G', '_', 'F', 'R', 'E', 'M', 0,
     618             :   /* 857 */ 'G', '_', 'S', 'R', 'E', 'M', 0,
     619             :   /* 864 */ 'G', '_', 'U', 'R', 'E', 'M', 0,
     620             :   /* 871 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', 0,
     621             :   /* 881 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'I', 'N', 0,
     622             :   /* 898 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'I', 'N', 0,
     623             :   /* 914 */ 'C', 'F', 'I', '_', 'I', 'N', 'S', 'T', 'R', 'U', 'C', 'T', 'I', 'O', 'N', 0,
     624             :   /* 930 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 0,
     625             :   /* 947 */ 'G', '_', 'S', 'S', 'U', 'B', 'O', 0,
     626             :   /* 955 */ 'G', '_', 'S', 'A', 'D', 'D', 'O', 0,
     627             :   /* 963 */ 'G', '_', 'S', 'M', 'U', 'L', 'O', 0,
     628             :   /* 971 */ 'G', '_', 'U', 'M', 'U', 'L', 'O', 0,
     629             :   /* 979 */ 'S', 'F', 'S', 'U', 'B', '_', 'F', '_', 'R', 'I', '_', 'L', 'O', 0,
     630             :   /* 993 */ 'S', 'U', 'B', 'B', '_', 'I', '_', 'L', 'O', 0,
     631             :   /* 1003 */ 'S', 'U', 'B', '_', 'I', '_', 'L', 'O', 0,
     632             :   /* 1012 */ 'A', 'D', 'D', 'C', '_', 'I', '_', 'L', 'O', 0,
     633             :   /* 1022 */ 'A', 'D', 'D', '_', 'I', '_', 'L', 'O', 0,
     634             :   /* 1031 */ 'A', 'N', 'D', '_', 'I', '_', 'L', 'O', 0,
     635             :   /* 1040 */ 'S', 'U', 'B', 'B', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
     636             :   /* 1052 */ 'S', 'U', 'B', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
     637             :   /* 1063 */ 'A', 'D', 'D', 'C', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
     638             :   /* 1075 */ 'A', 'D', 'D', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
     639             :   /* 1086 */ 'A', 'N', 'D', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
     640             :   /* 1097 */ 'X', 'O', 'R', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
     641             :   /* 1108 */ 'X', 'O', 'R', '_', 'I', '_', 'L', 'O', 0,
     642             :   /* 1117 */ 'S', 'T', 'A', 'C', 'K', 'M', 'A', 'P', 0,
     643             :   /* 1126 */ 'G', '_', 'B', 'S', 'W', 'A', 'P', 0,
     644             :   /* 1134 */ 'G', '_', 'G', 'E', 'P', 0,
     645             :   /* 1140 */ 'G', '_', 'S', 'I', 'T', 'O', 'F', 'P', 0,
     646             :   /* 1149 */ 'G', '_', 'U', 'I', 'T', 'O', 'F', 'P', 0,
     647             :   /* 1158 */ 'G', '_', 'F', 'C', 'M', 'P', 0,
     648             :   /* 1165 */ 'G', '_', 'I', 'C', 'M', 'P', 0,
     649             :   /* 1172 */ 'N', 'O', 'P', 0,
     650             :   /* 1176 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'O', 'P', 0,
     651             :   /* 1189 */ 'F', 'A', 'U', 'L', 'T', 'I', 'N', 'G', '_', 'O', 'P', 0,
     652             :   /* 1201 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 0,
     653             :   /* 1216 */ 'G', '_', 'F', 'E', 'X', 'P', 0,
     654             :   /* 1223 */ 'G', '_', 'B', 'R', 0,
     655             :   /* 1228 */ 'L', 'D', 'A', 'D', 'D', 'R', 0,
     656             :   /* 1235 */ 'S', 'T', 'A', 'D', 'D', 'R', 0,
     657             :   /* 1242 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'N', 'T', 'E', 'R', 0,
     658             :   /* 1267 */ 'G', '_', 'A', 'S', 'H', 'R', 0,
     659             :   /* 1274 */ 'G', '_', 'L', 'S', 'H', 'R', 0,
     660             :   /* 1281 */ 'J', 'R', 0,
     661             :   /* 1284 */ 'C', 'A', 'L', 'L', 'R', 0,
     662             :   /* 1290 */ 'G', '_', 'S', 'H', 'U', 'F', 'F', 'L', 'E', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
     663             :   /* 1307 */ 'G', '_', 'X', 'O', 'R', 0,
     664             :   /* 1313 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'O', 'R', 0,
     665             :   /* 1329 */ 'G', '_', 'O', 'R', 0,
     666             :   /* 1334 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'O', 'R', 0,
     667             :   /* 1349 */ 'B', 'R', 'R', 0,
     668             :   /* 1353 */ 'S', 'T', 'B', '_', 'R', 'R', 0,
     669             :   /* 1360 */ 'S', 'F', 'S', 'U', 'B', '_', 'F', '_', 'R', 'R', 0,
     670             :   /* 1371 */ 'S', 'T', 'H', '_', 'R', 'R', 0,
     671             :   /* 1378 */ 'L', 'D', 'W', '_', 'R', 'R', 0,
     672             :   /* 1385 */ 'S', 'W', '_', 'R', 'R', 0,
     673             :   /* 1391 */ 'L', 'D', 'B', 's', '_', 'R', 'R', 0,
     674             :   /* 1399 */ 'L', 'D', 'H', 's', '_', 'R', 'R', 0,
     675             :   /* 1407 */ 'L', 'D', 'B', 'z', '_', 'R', 'R', 0,
     676             :   /* 1415 */ 'L', 'D', 'H', 'z', '_', 'R', 'R', 0,
     677             :   /* 1423 */ 'L', 'D', 'W', 'z', '_', 'R', 'R', 0,
     678             :   /* 1431 */ 'G', '_', 'I', 'N', 'T', 'T', 'O', 'P', 'T', 'R', 0,
     679             :   /* 1442 */ 'S', 'R', 'A', '_', 'R', 0,
     680             :   /* 1448 */ 'S', 'U', 'B', 'B', '_', 'R', 0,
     681             :   /* 1455 */ 'S', 'U', 'B', '_', 'R', 0,
     682             :   /* 1461 */ 'A', 'D', 'D', 'C', '_', 'R', 0,
     683             :   /* 1468 */ 'A', 'D', 'D', '_', 'R', 0,
     684             :   /* 1474 */ 'A', 'N', 'D', '_', 'R', 0,
     685             :   /* 1480 */ 'S', 'R', 'A', '_', 'F', '_', 'R', 0,
     686             :   /* 1488 */ 'S', 'U', 'B', 'B', '_', 'F', '_', 'R', 0,
     687             :   /* 1497 */ 'S', 'U', 'B', '_', 'F', '_', 'R', 0,
     688             :   /* 1505 */ 'A', 'D', 'D', 'C', '_', 'F', '_', 'R', 0,
     689             :   /* 1514 */ 'A', 'D', 'D', '_', 'F', '_', 'R', 0,
     690             :   /* 1522 */ 'A', 'N', 'D', '_', 'F', '_', 'R', 0,
     691             :   /* 1530 */ 'S', 'H', 'L', '_', 'F', '_', 'R', 0,
     692             :   /* 1538 */ 'S', 'R', 'L', '_', 'F', '_', 'R', 0,
     693             :   /* 1546 */ 'X', 'O', 'R', '_', 'F', '_', 'R', 0,
     694             :   /* 1554 */ 'S', 'H', 'L', '_', 'R', 0,
     695             :   /* 1560 */ 'S', 'R', 'L', '_', 'R', 0,
     696             :   /* 1566 */ 'X', 'O', 'R', '_', 'R', 0,
     697             :   /* 1572 */ 'G', '_', 'U', 'N', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
     698             :   /* 1589 */ 'G', '_', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
     699             :   /* 1604 */ 'C', 'O', 'P', 'Y', '_', 'T', 'O', '_', 'R', 'E', 'G', 'C', 'L', 'A', 'S', 'S', 0,
     700             :   /* 1621 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'W', 'I', 'T', 'H', '_', 'S', 'U', 'C', 'C', 'E', 'S', 'S', 0,
     701             :   /* 1651 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'W', '_', 'S', 'I', 'D', 'E', '_', 'E', 'F', 'F', 'E', 'C', 'T', 'S', 0,
     702             :   /* 1678 */ 'B', 'T', 0,
     703             :   /* 1681 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', 0,
     704             :   /* 1691 */ 'G', '_', 'S', 'E', 'L', 'E', 'C', 'T', 0,
     705             :   /* 1700 */ 'G', '_', 'B', 'R', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', 0,
     706             :   /* 1713 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'R', 'E', 'T', 0,
     707             :   /* 1727 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'X', 'I', 'T', 0,
     708             :   /* 1751 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
     709             :   /* 1772 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
     710             :   /* 1792 */ 'G', '_', 'F', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
     711             :   /* 1804 */ 'G', '_', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
     712             :   /* 1815 */ 'S', 'T', 'A', 'T', 'E', 'P', 'O', 'I', 'N', 'T', 0,
     713             :   /* 1826 */ 'P', 'A', 'T', 'C', 'H', 'P', 'O', 'I', 'N', 'T', 0,
     714             :   /* 1837 */ 'G', '_', 'P', 'T', 'R', 'T', 'O', 'I', 'N', 'T', 0,
     715             :   /* 1848 */ 'G', '_', 'V', 'A', 'S', 'T', 'A', 'R', 'T', 0,
     716             :   /* 1858 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
     717             :   /* 1873 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', 0,
     718             :   /* 1882 */ 'G', '_', 'B', 'I', 'T', 'C', 'A', 'S', 'T', 0,
     719             :   /* 1892 */ 'G', '_', 'F', 'P', 'E', 'X', 'T', 0,
     720             :   /* 1900 */ 'G', '_', 'S', 'E', 'X', 'T', 0,
     721             :   /* 1907 */ 'G', '_', 'A', 'N', 'Y', 'E', 'X', 'T', 0,
     722             :   /* 1916 */ 'G', '_', 'Z', 'E', 'X', 'T', 0,
     723             :   /* 1923 */ 'G', '_', 'F', 'D', 'I', 'V', 0,
     724             :   /* 1930 */ 'G', '_', 'S', 'D', 'I', 'V', 0,
     725             :   /* 1937 */ 'G', '_', 'U', 'D', 'I', 'V', 0,
     726             :   /* 1944 */ 'G', '_', 'F', 'P', 'O', 'W', 0,
     727             :   /* 1951 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'A', 'X', 0,
     728             :   /* 1968 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'A', 'X', 0,
     729             :   /* 1984 */ 'G', '_', 'F', 'R', 'A', 'M', 'E', '_', 'I', 'N', 'D', 'E', 'X', 0,
     730             :   /* 1998 */ 'C', 'O', 'P', 'Y', 0,
     731             :   /* 2003 */ 'L', 'E', 'A', 'D', 'Z', 0,
     732             :   /* 2009 */ 'T', 'R', 'A', 'I', 'L', 'Z', 0,
     733             : };
     734             : 
     735             : extern const unsigned LanaiInstrNameIndices[] = {
     736             :     474U, 871U, 914U, 747U, 738U, 756U, 832U, 364U, 
     737             :     379U, 344U, 393U, 1604U, 317U, 268U, 1998U, 289U, 
     738             :     1858U, 221U, 1117U, 820U, 1826U, 243U, 1815U, 296U, 
     739             :     1189U, 1176U, 1242U, 1713U, 1727U, 779U, 799U, 160U, 
     740             :     59U, 844U, 1930U, 1937U, 857U, 864U, 199U, 1329U, 
     741             :     1307U, 342U, 472U, 1984U, 327U, 1681U, 1572U, 1873U, 
     742             :     1589U, 1837U, 1431U, 1882U, 146U, 309U, 1621U, 407U, 
     743             :     424U, 166U, 65U, 205U, 182U, 1334U, 1313U, 1968U, 
     744             :     898U, 1951U, 881U, 234U, 1700U, 99U, 1651U, 1907U, 
     745             :     121U, 1804U, 1792U, 1848U, 448U, 1900U, 1916U, 773U, 
     746             :     1274U, 1267U, 1165U, 1158U, 1691U, 281U, 260U, 955U, 
     747             :     947U, 971U, 963U, 464U, 456U, 153U, 52U, 837U, 
     748             :     46U, 1923U, 850U, 1944U, 1216U, 18U, 441U, 10U, 
     749             :     357U, 1892U, 111U, 685U, 694U, 1140U, 1149U, 1134U, 
     750             :     727U, 1223U, 1772U, 1751U, 1290U, 1126U, 568U, 1063U, 
     751             :     1505U, 517U, 1012U, 1461U, 580U, 1075U, 1514U, 527U, 
     752             :     1022U, 1468U, 930U, 1201U, 129U, 591U, 1086U, 1522U, 
     753             :     536U, 1031U, 1474U, 81U, 90U, 36U, 1349U, 1678U, 
     754             :     794U, 1284U, 1281U, 1228U, 653U, 1391U, 669U, 1407U, 
     755             :     661U, 1399U, 677U, 1415U, 640U, 1378U, 1423U, 2003U, 
     756             :     0U, 5U, 13U, 26U, 31U, 478U, 1172U, 603U, 
     757             :     1098U, 1547U, 614U, 1109U, 1567U, 141U, 1723U, 708U, 
     758             :     703U, 86U, 1693U, 484U, 979U, 1360U, 1530U, 1554U, 
     759             :     622U, 715U, 722U, 1480U, 1442U, 1538U, 1560U, 1235U, 
     760             :     626U, 1353U, 633U, 1371U, 545U, 1040U, 1488U, 498U, 
     761             :     993U, 1448U, 557U, 1052U, 1497U, 508U, 1003U, 1455U, 
     762             :     647U, 1385U, 2009U, 602U, 1097U, 1546U, 613U, 1108U, 
     763             :     1566U, 
     764             : };
     765             : 
     766             : static inline void InitLanaiMCInstrInfo(MCInstrInfo *II) {
     767             :   II->InitMCInstrInfo(LanaiInsts, LanaiInstrNameIndices, LanaiInstrNameData, 217);
     768             : }
     769             : 
     770             : } // end llvm namespace
     771             : #endif // GET_INSTRINFO_MC_DESC
     772             : 
     773             : #ifdef GET_INSTRINFO_HEADER
     774             : #undef GET_INSTRINFO_HEADER
     775             : namespace llvm {
     776             : struct LanaiGenInstrInfo : public TargetInstrInfo {
     777             :   explicit LanaiGenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);
     778          25 :   ~LanaiGenInstrInfo() override = default;
     779             : };
     780             : } // end llvm namespace
     781             : #endif // GET_INSTRINFO_HEADER
     782             : 
     783             : #ifdef GET_INSTRINFO_CTOR_DTOR
     784             : #undef GET_INSTRINFO_CTOR_DTOR
     785             : namespace llvm {
     786             : extern const MCInstrDesc LanaiInsts[];
     787             : extern const unsigned LanaiInstrNameIndices[];
     788             : extern const char LanaiInstrNameData[];
     789          26 : LanaiGenInstrInfo::LanaiGenInstrInfo(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode)
     790          52 :   : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
     791             :   InitMCInstrInfo(LanaiInsts, LanaiInstrNameIndices, LanaiInstrNameData, 217);
     792          26 : }
     793             : } // end llvm namespace
     794             : #endif // GET_INSTRINFO_CTOR_DTOR
     795             : 
     796             : #ifdef GET_INSTRINFO_OPERAND_ENUM
     797             : #undef GET_INSTRINFO_OPERAND_ENUM
     798             : namespace llvm {
     799             : namespace Lanai {
     800             : namespace OpName {
     801             : enum {
     802             : OPERAND_LAST
     803             : };
     804             : } // end namespace OpName
     805             : } // end namespace Lanai
     806             : } // end namespace llvm
     807             : #endif //GET_INSTRINFO_OPERAND_ENUM
     808             : 
     809             : #ifdef GET_INSTRINFO_NAMED_OPS
     810             : #undef GET_INSTRINFO_NAMED_OPS
     811             : namespace llvm {
     812             : namespace Lanai {
     813             : LLVM_READONLY
     814             : int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
     815             :   return -1;
     816             : }
     817             : } // end namespace Lanai
     818             : } // end namespace llvm
     819             : #endif //GET_INSTRINFO_NAMED_OPS
     820             : 
     821             : #ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
     822             : #undef GET_INSTRINFO_OPERAND_TYPES_ENUM
     823             : namespace llvm {
     824             : namespace Lanai {
     825             : namespace OpTypes {
     826             : enum OperandType {
     827             :   AluOp = 0,
     828             :   BrTarget = 1,
     829             :   CCOp = 2,
     830             :   CallTarget = 3,
     831             :   MEMi = 4,
     832             :   MEMri = 5,
     833             :   MEMrr = 6,
     834             :   MEMspls = 7,
     835             :   f32imm = 8,
     836             :   f64imm = 9,
     837             :   i16imm = 10,
     838             :   i1imm = 11,
     839             :   i32hi16 = 12,
     840             :   i32hi16and = 13,
     841             :   i32imm = 14,
     842             :   i32lo16and = 15,
     843             :   i32lo16s = 16,
     844             :   i32lo16z = 17,
     845             :   i32lo21 = 18,
     846             :   i32neg16 = 19,
     847             :   i64imm = 20,
     848             :   i8imm = 21,
     849             :   imm10 = 22,
     850             :   immShift = 23,
     851             :   pred = 24,
     852             :   ptype0 = 25,
     853             :   ptype1 = 26,
     854             :   ptype2 = 27,
     855             :   ptype3 = 28,
     856             :   ptype4 = 29,
     857             :   ptype5 = 30,
     858             :   type0 = 31,
     859             :   type1 = 32,
     860             :   type2 = 33,
     861             :   type3 = 34,
     862             :   type4 = 35,
     863             :   type5 = 36,
     864             :   OPERAND_TYPE_LIST_END
     865             : };
     866             : } // end namespace OpTypes
     867             : } // end namespace Lanai
     868             : } // end namespace llvm
     869             : #endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
     870             : 
     871             : #ifdef GET_INSTRMAP_INFO
     872             : #undef GET_INSTRMAP_INFO
     873             : namespace llvm {
     874             : 
     875             : namespace Lanai {
     876             : 
     877             : enum PostEncoderMethod {
     878             :         PostEncoderMethod_adjustPqBitsSpls
     879             : };
     880             : 
     881             : // splsIdempotent
     882             : LLVM_READONLY
     883         128 : int splsIdempotent(uint16_t Opcode) {
     884             : static const uint16_t splsIdempotentTable[][2] = {
     885             :   { Lanai::LDBs_RI, Lanai::LDBs_RI },
     886             :   { Lanai::LDBz_RI, Lanai::LDBz_RI },
     887             :   { Lanai::LDHs_RI, Lanai::LDHs_RI },
     888             :   { Lanai::LDHz_RI, Lanai::LDHz_RI },
     889             :   { Lanai::STB_RI, Lanai::STB_RI },
     890             :   { Lanai::STH_RI, Lanai::STH_RI },
     891             : }; // End of splsIdempotentTable
     892             : 
     893             :   unsigned mid;
     894             :   unsigned start = 0;
     895             :   unsigned end = 6;
     896         488 :   while (start < end) {
     897         368 :     mid = start + (end - start)/2;
     898         368 :     if (Opcode == splsIdempotentTable[mid][0]) {
     899             :       break;
     900             :     }
     901         360 :     if (Opcode < splsIdempotentTable[mid][0])
     902             :       end = mid;
     903             :     else
     904         128 :       start = mid + 1;
     905             :   }
     906         128 :   if (start == end)
     907             :     return -1; // Instruction doesn't exist in this table.
     908             : 
     909           8 :   return splsIdempotentTable[mid][1];
     910             : }
     911             : 
     912             : } // End Lanai namespace
     913             : } // End llvm namespace
     914             : #endif // GET_INSTRMAP_INFO
     915             : 

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