LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/Lanai - LanaiGenInstrInfo.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 16 16 100.0 %
Date: 2017-09-14 15:23:50 Functions: 2 4 50.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Target Instruction Enum Values and Descriptors                             *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : #ifdef GET_INSTRINFO_ENUM
      10             : #undef GET_INSTRINFO_ENUM
      11             : namespace llvm {
      12             : 
      13             : namespace Lanai {
      14             :   enum {
      15             :     PHI = 0,
      16             :     INLINEASM   = 1,
      17             :     CFI_INSTRUCTION     = 2,
      18             :     EH_LABEL    = 3,
      19             :     GC_LABEL    = 4,
      20             :     ANNOTATION_LABEL    = 5,
      21             :     KILL        = 6,
      22             :     EXTRACT_SUBREG      = 7,
      23             :     INSERT_SUBREG       = 8,
      24             :     IMPLICIT_DEF        = 9,
      25             :     SUBREG_TO_REG       = 10,
      26             :     COPY_TO_REGCLASS    = 11,
      27             :     DBG_VALUE   = 12,
      28             :     REG_SEQUENCE        = 13,
      29             :     COPY        = 14,
      30             :     BUNDLE      = 15,
      31             :     LIFETIME_START      = 16,
      32             :     LIFETIME_END        = 17,
      33             :     STACKMAP    = 18,
      34             :     FENTRY_CALL = 19,
      35             :     PATCHPOINT  = 20,
      36             :     LOAD_STACK_GUARD    = 21,
      37             :     STATEPOINT  = 22,
      38             :     LOCAL_ESCAPE        = 23,
      39             :     FAULTING_OP = 24,
      40             :     PATCHABLE_OP        = 25,
      41             :     PATCHABLE_FUNCTION_ENTER    = 26,
      42             :     PATCHABLE_RET       = 27,
      43             :     PATCHABLE_FUNCTION_EXIT     = 28,
      44             :     PATCHABLE_TAIL_CALL = 29,
      45             :     PATCHABLE_EVENT_CALL        = 30,
      46             :     G_ADD       = 31,
      47             :     G_SUB       = 32,
      48             :     G_MUL       = 33,
      49             :     G_SDIV      = 34,
      50             :     G_UDIV      = 35,
      51             :     G_SREM      = 36,
      52             :     G_UREM      = 37,
      53             :     G_AND       = 38,
      54             :     G_OR        = 39,
      55             :     G_XOR       = 40,
      56             :     G_IMPLICIT_DEF      = 41,
      57             :     G_PHI       = 42,
      58             :     G_FRAME_INDEX       = 43,
      59             :     G_GLOBAL_VALUE      = 44,
      60             :     G_EXTRACT   = 45,
      61             :     G_UNMERGE_VALUES    = 46,
      62             :     G_INSERT    = 47,
      63             :     G_MERGE_VALUES      = 48,
      64             :     G_PTRTOINT  = 49,
      65             :     G_INTTOPTR  = 50,
      66             :     G_BITCAST   = 51,
      67             :     G_LOAD      = 52,
      68             :     G_STORE     = 53,
      69             :     G_BRCOND    = 54,
      70             :     G_BRINDIRECT        = 55,
      71             :     G_INTRINSIC = 56,
      72             :     G_INTRINSIC_W_SIDE_EFFECTS  = 57,
      73             :     G_ANYEXT    = 58,
      74             :     G_TRUNC     = 59,
      75             :     G_CONSTANT  = 60,
      76             :     G_FCONSTANT = 61,
      77             :     G_VASTART   = 62,
      78             :     G_VAARG     = 63,
      79             :     G_SEXT      = 64,
      80             :     G_ZEXT      = 65,
      81             :     G_SHL       = 66,
      82             :     G_LSHR      = 67,
      83             :     G_ASHR      = 68,
      84             :     G_ICMP      = 69,
      85             :     G_FCMP      = 70,
      86             :     G_SELECT    = 71,
      87             :     G_UADDE     = 72,
      88             :     G_USUBE     = 73,
      89             :     G_SADDO     = 74,
      90             :     G_SSUBO     = 75,
      91             :     G_UMULO     = 76,
      92             :     G_SMULO     = 77,
      93             :     G_UMULH     = 78,
      94             :     G_SMULH     = 79,
      95             :     G_FADD      = 80,
      96             :     G_FSUB      = 81,
      97             :     G_FMUL      = 82,
      98             :     G_FMA       = 83,
      99             :     G_FDIV      = 84,
     100             :     G_FREM      = 85,
     101             :     G_FPOW      = 86,
     102             :     G_FEXP      = 87,
     103             :     G_FEXP2     = 88,
     104             :     G_FLOG      = 89,
     105             :     G_FLOG2     = 90,
     106             :     G_FNEG      = 91,
     107             :     G_FPEXT     = 92,
     108             :     G_FPTRUNC   = 93,
     109             :     G_FPTOSI    = 94,
     110             :     G_FPTOUI    = 95,
     111             :     G_SITOFP    = 96,
     112             :     G_UITOFP    = 97,
     113             :     G_GEP       = 98,
     114             :     G_PTR_MASK  = 99,
     115             :     G_BR        = 100,
     116             :     G_INSERT_VECTOR_ELT = 101,
     117             :     G_EXTRACT_VECTOR_ELT        = 102,
     118             :     G_SHUFFLE_VECTOR    = 103,
     119             :     ADDC_F_I_HI = 104,
     120             :     ADDC_F_I_LO = 105,
     121             :     ADDC_F_R    = 106,
     122             :     ADDC_I_HI   = 107,
     123             :     ADDC_I_LO   = 108,
     124             :     ADDC_R      = 109,
     125             :     ADD_F_I_HI  = 110,
     126             :     ADD_F_I_LO  = 111,
     127             :     ADD_F_R     = 112,
     128             :     ADD_I_HI    = 113,
     129             :     ADD_I_LO    = 114,
     130             :     ADD_R       = 115,
     131             :     ADJCALLSTACKDOWN    = 116,
     132             :     ADJCALLSTACKUP      = 117,
     133             :     ADJDYNALLOC = 118,
     134             :     AND_F_I_HI  = 119,
     135             :     AND_F_I_LO  = 120,
     136             :     AND_F_R     = 121,
     137             :     AND_I_HI    = 122,
     138             :     AND_I_LO    = 123,
     139             :     AND_R       = 124,
     140             :     BRCC        = 125,
     141             :     BRIND_CC    = 126,
     142             :     BRIND_CCA   = 127,
     143             :     BRR = 128,
     144             :     BT  = 129,
     145             :     CALL        = 130,
     146             :     CALLR       = 131,
     147             :     JR  = 132,
     148             :     LDADDR      = 133,
     149             :     LDBs_RI     = 134,
     150             :     LDBs_RR     = 135,
     151             :     LDBz_RI     = 136,
     152             :     LDBz_RR     = 137,
     153             :     LDHs_RI     = 138,
     154             :     LDHs_RR     = 139,
     155             :     LDHz_RI     = 140,
     156             :     LDHz_RR     = 141,
     157             :     LDW_RI      = 142,
     158             :     LDW_RR      = 143,
     159             :     LDWz_RR     = 144,
     160             :     LEADZ       = 145,
     161             :     LOG0        = 146,
     162             :     LOG1        = 147,
     163             :     LOG2        = 148,
     164             :     LOG3        = 149,
     165             :     LOG4        = 150,
     166             :     MOVHI       = 151,
     167             :     NOP = 152,
     168             :     OR_F_I_HI   = 153,
     169             :     OR_F_I_LO   = 154,
     170             :     OR_F_R      = 155,
     171             :     OR_I_HI     = 156,
     172             :     OR_I_LO     = 157,
     173             :     OR_R        = 158,
     174             :     POPC        = 159,
     175             :     RET = 160,
     176             :     SA_F_I      = 161,
     177             :     SA_I        = 162,
     178             :     SCC = 163,
     179             :     SELECT      = 164,
     180             :     SFSUB_F_RI_HI       = 165,
     181             :     SFSUB_F_RI_LO       = 166,
     182             :     SFSUB_F_RR  = 167,
     183             :     SHL_F_R     = 168,
     184             :     SHL_R       = 169,
     185             :     SLI = 170,
     186             :     SL_F_I      = 171,
     187             :     SL_I        = 172,
     188             :     SRA_F_R     = 173,
     189             :     SRA_R       = 174,
     190             :     SRL_F_R     = 175,
     191             :     SRL_R       = 176,
     192             :     STADDR      = 177,
     193             :     STB_RI      = 178,
     194             :     STB_RR      = 179,
     195             :     STH_RI      = 180,
     196             :     STH_RR      = 181,
     197             :     SUBB_F_I_HI = 182,
     198             :     SUBB_F_I_LO = 183,
     199             :     SUBB_F_R    = 184,
     200             :     SUBB_I_HI   = 185,
     201             :     SUBB_I_LO   = 186,
     202             :     SUBB_R      = 187,
     203             :     SUB_F_I_HI  = 188,
     204             :     SUB_F_I_LO  = 189,
     205             :     SUB_F_R     = 190,
     206             :     SUB_I_HI    = 191,
     207             :     SUB_I_LO    = 192,
     208             :     SUB_R       = 193,
     209             :     SW_RI       = 194,
     210             :     SW_RR       = 195,
     211             :     TRAILZ      = 196,
     212             :     XOR_F_I_HI  = 197,
     213             :     XOR_F_I_LO  = 198,
     214             :     XOR_F_R     = 199,
     215             :     XOR_I_HI    = 200,
     216             :     XOR_I_LO    = 201,
     217             :     XOR_R       = 202,
     218             :     INSTRUCTION_LIST_END = 203
     219             :   };
     220             : 
     221             : namespace Sched {
     222             :   enum {
     223             :     NoInstrModel        = 0,
     224             :     IIC_ALU_WriteALU    = 1,
     225             :     IIC_ALU     = 2,
     226             :     IIC_LD_WriteLD      = 3,
     227             :     IIC_LDSW_WriteLDSW  = 4,
     228             :     WriteLD     = 5,
     229             :     IIC_ST_WriteST      = 6,
     230             :     IIC_STSW_WriteSTSW  = 7,
     231             :     SCHED_LIST_END = 8
     232             :   };
     233             : } // end Sched namespace
     234             : } // end Lanai namespace
     235             : } // end llvm namespace
     236             : #endif // GET_INSTRINFO_ENUM
     237             : 
     238             : #ifdef GET_INSTRINFO_MC_DESC
     239             : #undef GET_INSTRINFO_MC_DESC
     240             : namespace llvm {
     241             : 
     242             : static const MCPhysReg ImplicitList1[] = { Lanai::SR, 0 };
     243             : static const MCPhysReg ImplicitList2[] = { Lanai::SP, 0 };
     244             : static const MCPhysReg ImplicitList3[] = { Lanai::RCA, 0 };
     245             : 
     246             : static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     247             : static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     248             : static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     249             : static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     250             : static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     251             : static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     252             : static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     253             : static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     254             : static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
     255             : static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     256             : static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     257             : static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     258             : static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     259             : static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     260             : static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     261             : static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
     262             : static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
     263             : static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     264             : static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
     265             : static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     266             : static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     267             : static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
     268             : static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     269             : static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
     270             : static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
     271             : static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
     272             : static const MCOperandInfo OperandInfo28[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     273             : static const MCOperandInfo OperandInfo29[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
     274             : static const MCOperandInfo OperandInfo30[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     275             : static const MCOperandInfo OperandInfo31[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     276             : static const MCOperandInfo OperandInfo32[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     277             : static const MCOperandInfo OperandInfo33[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     278             : static const MCOperandInfo OperandInfo34[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     279             : static const MCOperandInfo OperandInfo35[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     280             : static const MCOperandInfo OperandInfo36[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     281             : 
     282             : extern const MCInstrDesc LanaiInsts[] = {
     283             :   { 0,  1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #0 = PHI
     284             :   { 1,  0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
     285             :   { 2,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #2 = CFI_INSTRUCTION
     286             :   { 3,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #3 = EH_LABEL
     287             :   { 4,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #4 = GC_LABEL
     288             :   { 5,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #5 = ANNOTATION_LABEL
     289             :   { 6,  0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #6 = KILL
     290             :   { 7,  3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #7 = EXTRACT_SUBREG
     291             :   { 8,  4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #8 = INSERT_SUBREG
     292             :   { 9,  1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #9 = IMPLICIT_DEF
     293             :   { 10, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #10 = SUBREG_TO_REG
     294             :   { 11, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #11 = COPY_TO_REGCLASS
     295             :   { 12, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #12 = DBG_VALUE
     296             :   { 13, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #13 = REG_SEQUENCE
     297             :   { 14, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #14 = COPY
     298             :   { 15, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #15 = BUNDLE
     299             :   { 16, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #16 = LIFETIME_START
     300             :   { 17, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #17 = LIFETIME_END
     301             :   { 18, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #18 = STACKMAP
     302             :   { 19, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #19 = FENTRY_CALL
     303             :   { 20, 6,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #20 = PATCHPOINT
     304             :   { 21, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #21 = LOAD_STACK_GUARD
     305             :   { 22, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #22 = STATEPOINT
     306             :   { 23, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #23 = LOCAL_ESCAPE
     307             :   { 24, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #24 = FAULTING_OP
     308             :   { 25, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #25 = PATCHABLE_OP
     309             :   { 26, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #26 = PATCHABLE_FUNCTION_ENTER
     310             :   { 27, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #27 = PATCHABLE_RET
     311             :   { 28, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #28 = PATCHABLE_FUNCTION_EXIT
     312             :   { 29, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #29 = PATCHABLE_TAIL_CALL
     313             :   { 30, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #30 = PATCHABLE_EVENT_CALL
     314             :   { 31, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #31 = G_ADD
     315             :   { 32, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #32 = G_SUB
     316             :   { 33, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #33 = G_MUL
     317             :   { 34, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #34 = G_SDIV
     318             :   { 35, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #35 = G_UDIV
     319             :   { 36, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #36 = G_SREM
     320             :   { 37, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #37 = G_UREM
     321             :   { 38, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #38 = G_AND
     322             :   { 39, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #39 = G_OR
     323             :   { 40, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #40 = G_XOR
     324             :   { 41, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #41 = G_IMPLICIT_DEF
     325             :   { 42, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #42 = G_PHI
     326             :   { 43, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #43 = G_FRAME_INDEX
     327             :   { 44, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #44 = G_GLOBAL_VALUE
     328             :   { 45, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #45 = G_EXTRACT
     329             :   { 46, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #46 = G_UNMERGE_VALUES
     330             :   { 47, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #47 = G_INSERT
     331             :   { 48, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #48 = G_MERGE_VALUES
     332             :   { 49, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #49 = G_PTRTOINT
     333             :   { 50, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #50 = G_INTTOPTR
     334             :   { 51, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #51 = G_BITCAST
     335             :   { 52, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #52 = G_LOAD
     336             :   { 53, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #53 = G_STORE
     337             :   { 54, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #54 = G_BRCOND
     338             :   { 55, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #55 = G_BRINDIRECT
     339             :   { 56, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #56 = G_INTRINSIC
     340             :   { 57, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #57 = G_INTRINSIC_W_SIDE_EFFECTS
     341             :   { 58, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #58 = G_ANYEXT
     342             :   { 59, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #59 = G_TRUNC
     343             :   { 60, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #60 = G_CONSTANT
     344             :   { 61, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #61 = G_FCONSTANT
     345             :   { 62, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #62 = G_VASTART
     346             :   { 63, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #63 = G_VAARG
     347             :   { 64, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #64 = G_SEXT
     348             :   { 65, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #65 = G_ZEXT
     349             :   { 66, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #66 = G_SHL
     350             :   { 67, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #67 = G_LSHR
     351             :   { 68, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #68 = G_ASHR
     352             :   { 69, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #69 = G_ICMP
     353             :   { 70, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #70 = G_FCMP
     354             :   { 71, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #71 = G_SELECT
     355             :   { 72, 5,      2,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #72 = G_UADDE
     356             :   { 73, 5,      2,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #73 = G_USUBE
     357             :   { 74, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #74 = G_SADDO
     358             :   { 75, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #75 = G_SSUBO
     359             :   { 76, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #76 = G_UMULO
     360             :   { 77, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #77 = G_SMULO
     361             :   { 78, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #78 = G_UMULH
     362             :   { 79, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #79 = G_SMULH
     363             :   { 80, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #80 = G_FADD
     364             :   { 81, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #81 = G_FSUB
     365             :   { 82, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #82 = G_FMUL
     366             :   { 83, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #83 = G_FMA
     367             :   { 84, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #84 = G_FDIV
     368             :   { 85, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #85 = G_FREM
     369             :   { 86, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #86 = G_FPOW
     370             :   { 87, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #87 = G_FEXP
     371             :   { 88, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #88 = G_FEXP2
     372             :   { 89, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #89 = G_FLOG
     373             :   { 90, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #90 = G_FLOG2
     374             :   { 91, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #91 = G_FNEG
     375             :   { 92, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #92 = G_FPEXT
     376             :   { 93, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #93 = G_FPTRUNC
     377             :   { 94, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #94 = G_FPTOSI
     378             :   { 95, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #95 = G_FPTOUI
     379             :   { 96, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #96 = G_SITOFP
     380             :   { 97, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #97 = G_UITOFP
     381             :   { 98, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #98 = G_GEP
     382             :   { 99, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #99 = G_PTR_MASK
     383             :   { 100,        1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #100 = G_BR
     384             :   { 101,        4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #101 = G_INSERT_VECTOR_ELT
     385             :   { 102,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #102 = G_EXTRACT_VECTOR_ELT
     386             :   { 103,        4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #103 = G_SHUFFLE_VECTOR
     387             :   { 104,        3,      1,      4,      1,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #104 = ADDC_F_I_HI
     388             :   { 105,        3,      1,      4,      1,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #105 = ADDC_F_I_LO
     389             :   { 106,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo29, -1 ,nullptr },  // Inst #106 = ADDC_F_R
     390             :   { 107,        3,      1,      4,      1,      0, 0x0ULL, ImplicitList1, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #107 = ADDC_I_HI
     391             :   { 108,        3,      1,      4,      1,      0, 0x0ULL, ImplicitList1, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #108 = ADDC_I_LO
     392             :   { 109,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable), 0x0ULL, ImplicitList1, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #109 = ADDC_R
     393             :   { 110,        3,      1,      4,      1,      0, 0x0ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #110 = ADD_F_I_HI
     394             :   { 111,        3,      1,      4,      1,      0, 0x0ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #111 = ADD_F_I_LO
     395             :   { 112,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, ImplicitList1, OperandInfo29, -1 ,nullptr },  // Inst #112 = ADD_F_R
     396             :   { 113,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #113 = ADD_I_HI
     397             :   { 114,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #114 = ADD_I_LO
     398             :   { 115,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #115 = ADD_R
     399             :   { 116,        2,      0,      4,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo8, -1 ,nullptr },  // Inst #116 = ADJCALLSTACKDOWN
     400             :   { 117,        2,      0,      4,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo8, -1 ,nullptr },  // Inst #117 = ADJCALLSTACKUP
     401             :   { 118,        2,      1,      4,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo30, -1 ,nullptr },  // Inst #118 = ADJDYNALLOC
     402             :   { 119,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #119 = AND_F_I_HI
     403             :   { 120,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #120 = AND_F_I_LO
     404             :   { 121,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, ImplicitList1, OperandInfo29, -1 ,nullptr },  // Inst #121 = AND_F_R
     405             :   { 122,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #122 = AND_I_HI
     406             :   { 123,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #123 = AND_I_LO
     407             :   { 124,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #124 = AND_R
     408             :   { 125,        2,      0,      4,      2,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #125 = BRCC
     409             :   { 126,        2,      0,      4,      1,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #126 = BRIND_CC
     410             :   { 127,        3,      0,      4,      1,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #127 = BRIND_CCA
     411             :   { 128,        2,      0,      4,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #128 = BRR
     412             :   { 129,        1,      0,      4,      2,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #129 = BT
     413             :   { 130,        1,      0,      4,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo2, -1 ,nullptr },  // Inst #130 = CALL
     414             :   { 131,        1,      0,      4,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #131 = CALLR
     415             :   { 132,        1,      0,      4,      1,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #132 = JR
     416             :   { 133,        2,      1,      4,      3,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #133 = LDADDR
     417             :   { 134,        4,      1,      4,      4,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #134 = LDBs_RI
     418             :   { 135,        4,      1,      4,      5,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #135 = LDBs_RR
     419             :   { 136,        4,      1,      4,      4,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #136 = LDBz_RI
     420             :   { 137,        4,      1,      4,      5,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #137 = LDBz_RR
     421             :   { 138,        4,      1,      4,      4,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #138 = LDHs_RI
     422             :   { 139,        4,      1,      4,      5,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #139 = LDHs_RR
     423             :   { 140,        4,      1,      4,      4,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #140 = LDHz_RI
     424             :   { 141,        4,      1,      4,      5,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #141 = LDHz_RR
     425             :   { 142,        4,      1,      4,      3,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #142 = LDW_RI
     426             :   { 143,        4,      1,      4,      5,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #143 = LDW_RR
     427             :   { 144,        4,      1,      4,      5,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #144 = LDWz_RR
     428             :   { 145,        2,      1,      4,      1,      0, 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #145 = LEADZ
     429             :   { 146,        0,      0,      4,      0,      0, 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #146 = LOG0
     430             :   { 147,        0,      0,      4,      0,      0, 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #147 = LOG1
     431             :   { 148,        0,      0,      4,      0,      0, 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #148 = LOG2
     432             :   { 149,        0,      0,      4,      0,      0, 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #149 = LOG3
     433             :   { 150,        0,      0,      4,      0,      0, 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #150 = LOG4
     434             :   { 151,        2,      1,      4,      1,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #151 = MOVHI
     435             :   { 152,        0,      0,      4,      0,      0, 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #152 = NOP
     436             :   { 153,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #153 = OR_F_I_HI
     437             :   { 154,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #154 = OR_F_I_LO
     438             :   { 155,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, ImplicitList1, OperandInfo29, -1 ,nullptr },  // Inst #155 = OR_F_R
     439             :   { 156,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #156 = OR_I_HI
     440             :   { 157,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #157 = OR_I_LO
     441             :   { 158,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #158 = OR_R
     442             :   { 159,        2,      1,      4,      1,      0, 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #159 = POPC
     443             :   { 160,        0,      0,      4,      0,      0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList3, nullptr, nullptr, -1 ,nullptr },  // Inst #160 = RET
     444             :   { 161,        3,      1,      4,      1,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #161 = SA_F_I
     445             :   { 162,        3,      1,      4,      1,      0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #162 = SA_I
     446             :   { 163,        2,      1,      4,      2,      0, 0x0ULL, ImplicitList1, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #163 = SCC
     447             :   { 164,        4,      1,      4,      1,      0|(1ULL<<MCID::Select), 0x0ULL, ImplicitList1, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #164 = SELECT
     448             :   { 165,        2,      0,      4,      1,      0|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #165 = SFSUB_F_RI_HI
     449             :   { 166,        2,      0,      4,      1,      0|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #166 = SFSUB_F_RI_LO
     450             :   { 167,        2,      0,      4,      1,      0|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo30, -1 ,nullptr },  // Inst #167 = SFSUB_F_RR
     451             :   { 168,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo29, -1 ,nullptr },  // Inst #168 = SHL_F_R
     452             :   { 169,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #169 = SHL_R
     453             :   { 170,        2,      1,      4,      0,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #170 = SLI
     454             :   { 171,        3,      1,      4,      1,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #171 = SL_F_I
     455             :   { 172,        3,      1,      4,      1,      0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #172 = SL_I
     456             :   { 173,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo29, -1 ,nullptr },  // Inst #173 = SRA_F_R
     457             :   { 174,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #174 = SRA_R
     458             :   { 175,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo29, -1 ,nullptr },  // Inst #175 = SRL_F_R
     459             :   { 176,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #176 = SRL_R
     460             :   { 177,        2,      0,      4,      6,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #177 = STADDR
     461             :   { 178,        4,      0,      4,      7,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #178 = STB_RI
     462             :   { 179,        4,      0,      4,      6,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #179 = STB_RR
     463             :   { 180,        4,      0,      4,      7,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #180 = STH_RI
     464             :   { 181,        4,      0,      4,      6,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #181 = STH_RR
     465             :   { 182,        3,      1,      4,      1,      0|(1ULL<<MCID::CheapAsAMove), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #182 = SUBB_F_I_HI
     466             :   { 183,        3,      1,      4,      1,      0|(1ULL<<MCID::CheapAsAMove), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #183 = SUBB_F_I_LO
     467             :   { 184,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo29, -1 ,nullptr },  // Inst #184 = SUBB_F_R
     468             :   { 185,        3,      1,      4,      1,      0, 0x0ULL, ImplicitList1, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #185 = SUBB_I_HI
     469             :   { 186,        3,      1,      4,      1,      0, 0x0ULL, ImplicitList1, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #186 = SUBB_I_LO
     470             :   { 187,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable), 0x0ULL, ImplicitList1, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #187 = SUBB_R
     471             :   { 188,        3,      1,      4,      1,      0, 0x0ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #188 = SUB_F_I_HI
     472             :   { 189,        3,      1,      4,      1,      0, 0x0ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #189 = SUB_F_I_LO
     473             :   { 190,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, ImplicitList1, OperandInfo29, -1 ,nullptr },  // Inst #190 = SUB_F_R
     474             :   { 191,        3,      1,      4,      1,      0|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #191 = SUB_I_HI
     475             :   { 192,        3,      1,      4,      1,      0|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #192 = SUB_I_LO
     476             :   { 193,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #193 = SUB_R
     477             :   { 194,        4,      0,      4,      6,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #194 = SW_RI
     478             :   { 195,        4,      0,      4,      6,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #195 = SW_RR
     479             :   { 196,        2,      1,      4,      1,      0, 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #196 = TRAILZ
     480             :   { 197,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #197 = XOR_F_I_HI
     481             :   { 198,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #198 = XOR_F_I_LO
     482             :   { 199,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, ImplicitList1, OperandInfo29, -1 ,nullptr },  // Inst #199 = XOR_F_R
     483             :   { 200,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #200 = XOR_I_HI
     484             :   { 201,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #201 = XOR_I_LO
     485             :   { 202,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #202 = XOR_R
     486             : };
     487             : 
     488             : extern const char LanaiInstrNameData[] = {
     489             :   /* 0 */ 'L', 'O', 'G', '0', 0,
     490             :   /* 5 */ 'L', 'O', 'G', '1', 0,
     491             :   /* 10 */ 'G', '_', 'F', 'L', 'O', 'G', '2', 0,
     492             :   /* 18 */ 'G', '_', 'F', 'E', 'X', 'P', '2', 0,
     493             :   /* 26 */ 'L', 'O', 'G', '3', 0,
     494             :   /* 31 */ 'L', 'O', 'G', '4', 0,
     495             :   /* 36 */ 'B', 'R', 'I', 'N', 'D', '_', 'C', 'C', 'A', 0,
     496             :   /* 46 */ 'G', '_', 'F', 'M', 'A', 0,
     497             :   /* 52 */ 'G', '_', 'F', 'S', 'U', 'B', 0,
     498             :   /* 59 */ 'G', '_', 'S', 'U', 'B', 0,
     499             :   /* 65 */ 'B', 'R', 'C', 'C', 0,
     500             :   /* 70 */ 'S', 'C', 'C', 0,
     501             :   /* 74 */ 'B', 'R', 'I', 'N', 'D', '_', 'C', 'C', 0,
     502             :   /* 83 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', 0,
     503             :   /* 95 */ 'G', '_', 'F', 'P', 'T', 'R', 'U', 'N', 'C', 0,
     504             :   /* 105 */ 'G', '_', 'T', 'R', 'U', 'N', 'C', 0,
     505             :   /* 113 */ 'A', 'D', 'J', 'D', 'Y', 'N', 'A', 'L', 'L', 'O', 'C', 0,
     506             :   /* 125 */ 'P', 'O', 'P', 'C', 0,
     507             :   /* 130 */ 'G', '_', 'L', 'O', 'A', 'D', 0,
     508             :   /* 137 */ 'G', '_', 'F', 'A', 'D', 'D', 0,
     509             :   /* 144 */ 'G', '_', 'A', 'D', 'D', 0,
     510             :   /* 150 */ 'G', '_', 'A', 'N', 'D', 0,
     511             :   /* 156 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
     512             :   /* 169 */ 'G', '_', 'B', 'R', 'C', 'O', 'N', 'D', 0,
     513             :   /* 178 */ 'L', 'O', 'A', 'D', '_', 'S', 'T', 'A', 'C', 'K', '_', 'G', 'U', 'A', 'R', 'D', 0,
     514             :   /* 195 */ 'G', '_', 'U', 'S', 'U', 'B', 'E', 0,
     515             :   /* 203 */ 'R', 'E', 'G', '_', 'S', 'E', 'Q', 'U', 'E', 'N', 'C', 'E', 0,
     516             :   /* 216 */ 'G', '_', 'U', 'A', 'D', 'D', 'E', 0,
     517             :   /* 224 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
     518             :   /* 231 */ 'L', 'O', 'C', 'A', 'L', '_', 'E', 'S', 'C', 'A', 'P', 'E', 0,
     519             :   /* 244 */ 'G', '_', 'S', 'T', 'O', 'R', 'E', 0,
     520             :   /* 252 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
     521             :   /* 262 */ 'G', '_', 'G', 'L', 'O', 'B', 'A', 'L', '_', 'V', 'A', 'L', 'U', 'E', 0,
     522             :   /* 277 */ 'G', '_', 'I', 'M', 'P', 'L', 'I', 'C', 'I', 'T', '_', 'D', 'E', 'F', 0,
     523             :   /* 292 */ 'G', '_', 'F', 'N', 'E', 'G', 0,
     524             :   /* 299 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
     525             :   /* 314 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
     526             :   /* 328 */ 'S', 'U', 'B', 'R', 'E', 'G', '_', 'T', 'O', '_', 'R', 'E', 'G', 0,
     527             :   /* 342 */ 'G', '_', 'F', 'L', 'O', 'G', 0,
     528             :   /* 349 */ 'G', '_', 'V', 'A', 'A', 'R', 'G', 0,
     529             :   /* 357 */ 'G', '_', 'S', 'M', 'U', 'L', 'H', 0,
     530             :   /* 365 */ 'G', '_', 'U', 'M', 'U', 'L', 'H', 0,
     531             :   /* 373 */ 'G', '_', 'P', 'H', 'I', 0,
     532             :   /* 379 */ 'M', 'O', 'V', 'H', 'I', 0,
     533             :   /* 385 */ 'S', 'F', 'S', 'U', 'B', '_', 'F', '_', 'R', 'I', '_', 'H', 'I', 0,
     534             :   /* 399 */ 'S', 'U', 'B', 'B', '_', 'I', '_', 'H', 'I', 0,
     535             :   /* 409 */ 'S', 'U', 'B', '_', 'I', '_', 'H', 'I', 0,
     536             :   /* 418 */ 'A', 'D', 'D', 'C', '_', 'I', '_', 'H', 'I', 0,
     537             :   /* 428 */ 'A', 'D', 'D', '_', 'I', '_', 'H', 'I', 0,
     538             :   /* 437 */ 'A', 'N', 'D', '_', 'I', '_', 'H', 'I', 0,
     539             :   /* 446 */ 'S', 'U', 'B', 'B', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
     540             :   /* 458 */ 'S', 'U', 'B', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
     541             :   /* 469 */ 'A', 'D', 'D', 'C', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
     542             :   /* 481 */ 'A', 'D', 'D', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
     543             :   /* 492 */ 'A', 'N', 'D', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
     544             :   /* 503 */ 'X', 'O', 'R', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
     545             :   /* 514 */ 'X', 'O', 'R', '_', 'I', '_', 'H', 'I', 0,
     546             :   /* 523 */ 'S', 'L', 'I', 0,
     547             :   /* 527 */ 'S', 'T', 'B', '_', 'R', 'I', 0,
     548             :   /* 534 */ 'S', 'T', 'H', '_', 'R', 'I', 0,
     549             :   /* 541 */ 'L', 'D', 'W', '_', 'R', 'I', 0,
     550             :   /* 548 */ 'S', 'W', '_', 'R', 'I', 0,
     551             :   /* 554 */ 'L', 'D', 'B', 's', '_', 'R', 'I', 0,
     552             :   /* 562 */ 'L', 'D', 'H', 's', '_', 'R', 'I', 0,
     553             :   /* 570 */ 'L', 'D', 'B', 'z', '_', 'R', 'I', 0,
     554             :   /* 578 */ 'L', 'D', 'H', 'z', '_', 'R', 'I', 0,
     555             :   /* 586 */ 'G', '_', 'F', 'P', 'T', 'O', 'S', 'I', 0,
     556             :   /* 595 */ 'G', '_', 'F', 'P', 'T', 'O', 'U', 'I', 0,
     557             :   /* 604 */ 'S', 'A', '_', 'I', 0,
     558             :   /* 609 */ 'S', 'A', '_', 'F', '_', 'I', 0,
     559             :   /* 616 */ 'S', 'L', '_', 'F', '_', 'I', 0,
     560             :   /* 623 */ 'S', 'L', '_', 'I', 0,
     561             :   /* 628 */ 'G', '_', 'P', 'T', 'R', '_', 'M', 'A', 'S', 'K', 0,
     562             :   /* 639 */ 'G', 'C', '_', 'L', 'A', 'B', 'E', 'L', 0,
     563             :   /* 648 */ 'E', 'H', '_', 'L', 'A', 'B', 'E', 'L', 0,
     564             :   /* 657 */ 'A', 'N', 'N', 'O', 'T', 'A', 'T', 'I', 'O', 'N', '_', 'L', 'A', 'B', 'E', 'L', 0,
     565             :   /* 674 */ 'G', '_', 'S', 'H', 'L', 0,
     566             :   /* 680 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'A', 'I', 'L', '_', 'C', 'A', 'L', 'L', 0,
     567             :   /* 700 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
     568             :   /* 721 */ 'F', 'E', 'N', 'T', 'R', 'Y', '_', 'C', 'A', 'L', 'L', 0,
     569             :   /* 733 */ 'K', 'I', 'L', 'L', 0,
     570             :   /* 738 */ 'G', '_', 'F', 'M', 'U', 'L', 0,
     571             :   /* 745 */ 'G', '_', 'M', 'U', 'L', 0,
     572             :   /* 751 */ 'G', '_', 'F', 'R', 'E', 'M', 0,
     573             :   /* 758 */ 'G', '_', 'S', 'R', 'E', 'M', 0,
     574             :   /* 765 */ 'G', '_', 'U', 'R', 'E', 'M', 0,
     575             :   /* 772 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', 0,
     576             :   /* 782 */ 'C', 'F', 'I', '_', 'I', 'N', 'S', 'T', 'R', 'U', 'C', 'T', 'I', 'O', 'N', 0,
     577             :   /* 798 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 0,
     578             :   /* 815 */ 'G', '_', 'S', 'S', 'U', 'B', 'O', 0,
     579             :   /* 823 */ 'G', '_', 'S', 'A', 'D', 'D', 'O', 0,
     580             :   /* 831 */ 'G', '_', 'S', 'M', 'U', 'L', 'O', 0,
     581             :   /* 839 */ 'G', '_', 'U', 'M', 'U', 'L', 'O', 0,
     582             :   /* 847 */ 'S', 'F', 'S', 'U', 'B', '_', 'F', '_', 'R', 'I', '_', 'L', 'O', 0,
     583             :   /* 861 */ 'S', 'U', 'B', 'B', '_', 'I', '_', 'L', 'O', 0,
     584             :   /* 871 */ 'S', 'U', 'B', '_', 'I', '_', 'L', 'O', 0,
     585             :   /* 880 */ 'A', 'D', 'D', 'C', '_', 'I', '_', 'L', 'O', 0,
     586             :   /* 890 */ 'A', 'D', 'D', '_', 'I', '_', 'L', 'O', 0,
     587             :   /* 899 */ 'A', 'N', 'D', '_', 'I', '_', 'L', 'O', 0,
     588             :   /* 908 */ 'S', 'U', 'B', 'B', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
     589             :   /* 920 */ 'S', 'U', 'B', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
     590             :   /* 931 */ 'A', 'D', 'D', 'C', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
     591             :   /* 943 */ 'A', 'D', 'D', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
     592             :   /* 954 */ 'A', 'N', 'D', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
     593             :   /* 965 */ 'X', 'O', 'R', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
     594             :   /* 976 */ 'X', 'O', 'R', '_', 'I', '_', 'L', 'O', 0,
     595             :   /* 985 */ 'S', 'T', 'A', 'C', 'K', 'M', 'A', 'P', 0,
     596             :   /* 994 */ 'G', '_', 'G', 'E', 'P', 0,
     597             :   /* 1000 */ 'G', '_', 'S', 'I', 'T', 'O', 'F', 'P', 0,
     598             :   /* 1009 */ 'G', '_', 'U', 'I', 'T', 'O', 'F', 'P', 0,
     599             :   /* 1018 */ 'G', '_', 'F', 'C', 'M', 'P', 0,
     600             :   /* 1025 */ 'G', '_', 'I', 'C', 'M', 'P', 0,
     601             :   /* 1032 */ 'N', 'O', 'P', 0,
     602             :   /* 1036 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'O', 'P', 0,
     603             :   /* 1049 */ 'F', 'A', 'U', 'L', 'T', 'I', 'N', 'G', '_', 'O', 'P', 0,
     604             :   /* 1061 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 0,
     605             :   /* 1076 */ 'G', '_', 'F', 'E', 'X', 'P', 0,
     606             :   /* 1083 */ 'G', '_', 'B', 'R', 0,
     607             :   /* 1088 */ 'L', 'D', 'A', 'D', 'D', 'R', 0,
     608             :   /* 1095 */ 'S', 'T', 'A', 'D', 'D', 'R', 0,
     609             :   /* 1102 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'N', 'T', 'E', 'R', 0,
     610             :   /* 1127 */ 'G', '_', 'A', 'S', 'H', 'R', 0,
     611             :   /* 1134 */ 'G', '_', 'L', 'S', 'H', 'R', 0,
     612             :   /* 1141 */ 'J', 'R', 0,
     613             :   /* 1144 */ 'C', 'A', 'L', 'L', 'R', 0,
     614             :   /* 1150 */ 'G', '_', 'S', 'H', 'U', 'F', 'F', 'L', 'E', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
     615             :   /* 1167 */ 'G', '_', 'X', 'O', 'R', 0,
     616             :   /* 1173 */ 'G', '_', 'O', 'R', 0,
     617             :   /* 1178 */ 'B', 'R', 'R', 0,
     618             :   /* 1182 */ 'S', 'T', 'B', '_', 'R', 'R', 0,
     619             :   /* 1189 */ 'S', 'F', 'S', 'U', 'B', '_', 'F', '_', 'R', 'R', 0,
     620             :   /* 1200 */ 'S', 'T', 'H', '_', 'R', 'R', 0,
     621             :   /* 1207 */ 'L', 'D', 'W', '_', 'R', 'R', 0,
     622             :   /* 1214 */ 'S', 'W', '_', 'R', 'R', 0,
     623             :   /* 1220 */ 'L', 'D', 'B', 's', '_', 'R', 'R', 0,
     624             :   /* 1228 */ 'L', 'D', 'H', 's', '_', 'R', 'R', 0,
     625             :   /* 1236 */ 'L', 'D', 'B', 'z', '_', 'R', 'R', 0,
     626             :   /* 1244 */ 'L', 'D', 'H', 'z', '_', 'R', 'R', 0,
     627             :   /* 1252 */ 'L', 'D', 'W', 'z', '_', 'R', 'R', 0,
     628             :   /* 1260 */ 'G', '_', 'I', 'N', 'T', 'T', 'O', 'P', 'T', 'R', 0,
     629             :   /* 1271 */ 'S', 'R', 'A', '_', 'R', 0,
     630             :   /* 1277 */ 'S', 'U', 'B', 'B', '_', 'R', 0,
     631             :   /* 1284 */ 'S', 'U', 'B', '_', 'R', 0,
     632             :   /* 1290 */ 'A', 'D', 'D', 'C', '_', 'R', 0,
     633             :   /* 1297 */ 'A', 'D', 'D', '_', 'R', 0,
     634             :   /* 1303 */ 'A', 'N', 'D', '_', 'R', 0,
     635             :   /* 1309 */ 'S', 'R', 'A', '_', 'F', '_', 'R', 0,
     636             :   /* 1317 */ 'S', 'U', 'B', 'B', '_', 'F', '_', 'R', 0,
     637             :   /* 1326 */ 'S', 'U', 'B', '_', 'F', '_', 'R', 0,
     638             :   /* 1334 */ 'A', 'D', 'D', 'C', '_', 'F', '_', 'R', 0,
     639             :   /* 1343 */ 'A', 'D', 'D', '_', 'F', '_', 'R', 0,
     640             :   /* 1351 */ 'A', 'N', 'D', '_', 'F', '_', 'R', 0,
     641             :   /* 1359 */ 'S', 'H', 'L', '_', 'F', '_', 'R', 0,
     642             :   /* 1367 */ 'S', 'R', 'L', '_', 'F', '_', 'R', 0,
     643             :   /* 1375 */ 'X', 'O', 'R', '_', 'F', '_', 'R', 0,
     644             :   /* 1383 */ 'S', 'H', 'L', '_', 'R', 0,
     645             :   /* 1389 */ 'S', 'R', 'L', '_', 'R', 0,
     646             :   /* 1395 */ 'X', 'O', 'R', '_', 'R', 0,
     647             :   /* 1401 */ 'G', '_', 'U', 'N', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
     648             :   /* 1418 */ 'G', '_', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
     649             :   /* 1433 */ 'C', 'O', 'P', 'Y', '_', 'T', 'O', '_', 'R', 'E', 'G', 'C', 'L', 'A', 'S', 'S', 0,
     650             :   /* 1450 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'W', '_', 'S', 'I', 'D', 'E', '_', 'E', 'F', 'F', 'E', 'C', 'T', 'S', 0,
     651             :   /* 1477 */ 'B', 'T', 0,
     652             :   /* 1480 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', 0,
     653             :   /* 1490 */ 'G', '_', 'S', 'E', 'L', 'E', 'C', 'T', 0,
     654             :   /* 1499 */ 'G', '_', 'B', 'R', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', 0,
     655             :   /* 1512 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'R', 'E', 'T', 0,
     656             :   /* 1526 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'X', 'I', 'T', 0,
     657             :   /* 1550 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
     658             :   /* 1571 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
     659             :   /* 1591 */ 'G', '_', 'F', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
     660             :   /* 1603 */ 'G', '_', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
     661             :   /* 1614 */ 'S', 'T', 'A', 'T', 'E', 'P', 'O', 'I', 'N', 'T', 0,
     662             :   /* 1625 */ 'P', 'A', 'T', 'C', 'H', 'P', 'O', 'I', 'N', 'T', 0,
     663             :   /* 1636 */ 'G', '_', 'P', 'T', 'R', 'T', 'O', 'I', 'N', 'T', 0,
     664             :   /* 1647 */ 'G', '_', 'V', 'A', 'S', 'T', 'A', 'R', 'T', 0,
     665             :   /* 1657 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
     666             :   /* 1672 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', 0,
     667             :   /* 1681 */ 'G', '_', 'B', 'I', 'T', 'C', 'A', 'S', 'T', 0,
     668             :   /* 1691 */ 'G', '_', 'F', 'P', 'E', 'X', 'T', 0,
     669             :   /* 1699 */ 'G', '_', 'S', 'E', 'X', 'T', 0,
     670             :   /* 1706 */ 'G', '_', 'A', 'N', 'Y', 'E', 'X', 'T', 0,
     671             :   /* 1715 */ 'G', '_', 'Z', 'E', 'X', 'T', 0,
     672             :   /* 1722 */ 'G', '_', 'F', 'D', 'I', 'V', 0,
     673             :   /* 1729 */ 'G', '_', 'S', 'D', 'I', 'V', 0,
     674             :   /* 1736 */ 'G', '_', 'U', 'D', 'I', 'V', 0,
     675             :   /* 1743 */ 'G', '_', 'F', 'P', 'O', 'W', 0,
     676             :   /* 1750 */ 'G', '_', 'F', 'R', 'A', 'M', 'E', '_', 'I', 'N', 'D', 'E', 'X', 0,
     677             :   /* 1764 */ 'C', 'O', 'P', 'Y', 0,
     678             :   /* 1769 */ 'L', 'E', 'A', 'D', 'Z', 0,
     679             :   /* 1775 */ 'T', 'R', 'A', 'I', 'L', 'Z', 0,
     680             : };
     681             : 
     682             : extern const unsigned LanaiInstrNameIndices[] = {
     683             :     375U, 772U, 782U, 648U, 639U, 657U, 733U, 299U, 
     684             :     314U, 279U, 328U, 1433U, 252U, 203U, 1764U, 224U, 
     685             :     1657U, 156U, 985U, 721U, 1625U, 178U, 1614U, 231U, 
     686             :     1049U, 1036U, 1102U, 1512U, 1526U, 680U, 700U, 144U, 
     687             :     59U, 745U, 1729U, 1736U, 758U, 765U, 150U, 1173U, 
     688             :     1167U, 277U, 373U, 1750U, 262U, 1480U, 1401U, 1672U, 
     689             :     1418U, 1636U, 1260U, 1681U, 130U, 244U, 169U, 1499U, 
     690             :     83U, 1450U, 1706U, 105U, 1603U, 1591U, 1647U, 349U, 
     691             :     1699U, 1715U, 674U, 1134U, 1127U, 1025U, 1018U, 1490U, 
     692             :     216U, 195U, 823U, 815U, 839U, 831U, 365U, 357U, 
     693             :     137U, 52U, 738U, 46U, 1722U, 751U, 1743U, 1076U, 
     694             :     18U, 342U, 10U, 292U, 1691U, 95U, 586U, 595U, 
     695             :     1000U, 1009U, 994U, 628U, 1083U, 1571U, 1550U, 1150U, 
     696             :     469U, 931U, 1334U, 418U, 880U, 1290U, 481U, 943U, 
     697             :     1343U, 428U, 890U, 1297U, 798U, 1061U, 113U, 492U, 
     698             :     954U, 1351U, 437U, 899U, 1303U, 65U, 74U, 36U, 
     699             :     1178U, 1477U, 695U, 1144U, 1141U, 1088U, 554U, 1220U, 
     700             :     570U, 1236U, 562U, 1228U, 578U, 1244U, 541U, 1207U, 
     701             :     1252U, 1769U, 0U, 5U, 13U, 26U, 31U, 379U, 
     702             :     1032U, 504U, 966U, 1376U, 515U, 977U, 1396U, 125U, 
     703             :     1522U, 609U, 604U, 70U, 1492U, 385U, 847U, 1189U, 
     704             :     1359U, 1383U, 523U, 616U, 623U, 1309U, 1271U, 1367U, 
     705             :     1389U, 1095U, 527U, 1182U, 534U, 1200U, 446U, 908U, 
     706             :     1317U, 399U, 861U, 1277U, 458U, 920U, 1326U, 409U, 
     707             :     871U, 1284U, 548U, 1214U, 1775U, 503U, 965U, 1375U, 
     708             :     514U, 976U, 1395U, 
     709             : };
     710             : 
     711             : static inline void InitLanaiMCInstrInfo(MCInstrInfo *II) {
     712          31 :   II->InitMCInstrInfo(LanaiInsts, LanaiInstrNameIndices, LanaiInstrNameData, 203);
     713             : }
     714             : 
     715             : } // end llvm namespace
     716             : #endif // GET_INSTRINFO_MC_DESC
     717             : 
     718             : #ifdef GET_INSTRINFO_HEADER
     719             : #undef GET_INSTRINFO_HEADER
     720             : namespace llvm {
     721             : struct LanaiGenInstrInfo : public TargetInstrInfo {
     722             :   explicit LanaiGenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);
     723          25 :   ~LanaiGenInstrInfo() override = default;
     724             : };
     725             : } // end llvm namespace
     726             : #endif // GET_INSTRINFO_HEADER
     727             : 
     728             : #ifdef GET_INSTRINFO_CTOR_DTOR
     729             : #undef GET_INSTRINFO_CTOR_DTOR
     730             : namespace llvm {
     731             : extern const MCInstrDesc LanaiInsts[];
     732             : extern const unsigned LanaiInstrNameIndices[];
     733             : extern const char LanaiInstrNameData[];
     734          26 : LanaiGenInstrInfo::LanaiGenInstrInfo(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode)
     735          52 :   : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
     736          52 :   InitMCInstrInfo(LanaiInsts, LanaiInstrNameIndices, LanaiInstrNameData, 203);
     737          26 : }
     738             : } // end llvm namespace
     739             : #endif // GET_INSTRINFO_CTOR_DTOR
     740             : 
     741             : #ifdef GET_INSTRINFO_OPERAND_ENUM
     742             : #undef GET_INSTRINFO_OPERAND_ENUM
     743             : namespace llvm {
     744             : namespace Lanai {
     745             : namespace OpName {
     746             : enum {
     747             : OPERAND_LAST
     748             : };
     749             : } // end namespace OpName
     750             : } // end namespace Lanai
     751             : } // end namespace llvm
     752             : #endif //GET_INSTRINFO_OPERAND_ENUM
     753             : 
     754             : #ifdef GET_INSTRINFO_NAMED_OPS
     755             : #undef GET_INSTRINFO_NAMED_OPS
     756             : namespace llvm {
     757             : namespace Lanai {
     758             : LLVM_READONLY
     759             : int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
     760             :   return -1;
     761             : }
     762             : } // end namespace Lanai
     763             : } // end namespace llvm
     764             : #endif //GET_INSTRINFO_NAMED_OPS
     765             : 
     766             : #ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
     767             : #undef GET_INSTRINFO_OPERAND_TYPES_ENUM
     768             : namespace llvm {
     769             : namespace Lanai {
     770             : namespace OpTypes {
     771             : enum OperandType {
     772             :   AluOp = 0,
     773             :   BrTarget = 1,
     774             :   CCOp = 2,
     775             :   CallTarget = 3,
     776             :   MEMi = 4,
     777             :   MEMri = 5,
     778             :   MEMrr = 6,
     779             :   MEMspls = 7,
     780             :   f32imm = 8,
     781             :   f64imm = 9,
     782             :   i16imm = 10,
     783             :   i1imm = 11,
     784             :   i32hi16 = 12,
     785             :   i32hi16and = 13,
     786             :   i32imm = 14,
     787             :   i32lo16and = 15,
     788             :   i32lo16s = 16,
     789             :   i32lo16z = 17,
     790             :   i32lo21 = 18,
     791             :   i32neg16 = 19,
     792             :   i64imm = 20,
     793             :   i8imm = 21,
     794             :   imm10 = 22,
     795             :   immShift = 23,
     796             :   pred = 24,
     797             :   type0 = 25,
     798             :   type1 = 26,
     799             :   type2 = 27,
     800             :   type3 = 28,
     801             :   type4 = 29,
     802             :   type5 = 30,
     803             :   OPERAND_TYPE_LIST_END
     804             : };
     805             : } // end namespace OpTypes
     806             : } // end namespace Lanai
     807             : } // end namespace llvm
     808             : #endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
     809             : 
     810             : #ifdef GET_INSTRMAP_INFO
     811             : #undef GET_INSTRMAP_INFO
     812             : namespace llvm {
     813             : 
     814             : namespace Lanai {
     815             : 
     816             : enum PostEncoderMethod {
     817             :         PostEncoderMethod_adjustPqBitsSpls
     818             : };
     819             : 
     820             : // splsIdempotent
     821             : LLVM_READONLY
     822         128 : int splsIdempotent(uint16_t Opcode) {
     823             : static const uint16_t splsIdempotentTable[][2] = {
     824             :   { Lanai::LDBs_RI, Lanai::LDBs_RI },
     825             :   { Lanai::LDBz_RI, Lanai::LDBz_RI },
     826             :   { Lanai::LDHs_RI, Lanai::LDHs_RI },
     827             :   { Lanai::LDHz_RI, Lanai::LDHz_RI },
     828             :   { Lanai::STB_RI, Lanai::STB_RI },
     829             :   { Lanai::STH_RI, Lanai::STH_RI },
     830             : }; // End of splsIdempotentTable
     831             : 
     832             :   unsigned mid;
     833         128 :   unsigned start = 0;
     834         128 :   unsigned end = 6;
     835         488 :   while (start < end) {
     836         368 :     mid = start + (end - start)/2;
     837         368 :     if (Opcode == splsIdempotentTable[mid][0]) {
     838             :       break;
     839             :     }
     840         360 :     if (Opcode < splsIdempotentTable[mid][0])
     841             :       end = mid;
     842             :     else
     843         128 :       start = mid + 1;
     844             :   }
     845         128 :   if (start == end)
     846             :     return -1; // Instruction doesn't exist in this table.
     847             : 
     848           8 :   return splsIdempotentTable[mid][1];
     849             : }
     850             : 
     851             : } // End Lanai namespace
     852             : } // End llvm namespace
     853             : #endif // GET_INSTRMAP_INFO
     854             : 

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