LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/Lanai - LanaiGenInstrInfo.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 12 12 100.0 %
Date: 2018-07-13 00:08:38 Functions: 2 4 50.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Target Instruction Enum Values and Descriptors                             *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : #ifdef GET_INSTRINFO_ENUM
      10             : #undef GET_INSTRINFO_ENUM
      11             : namespace llvm {
      12             : 
      13             : namespace Lanai {
      14             :   enum {
      15             :     PHI = 0,
      16             :     INLINEASM   = 1,
      17             :     CFI_INSTRUCTION     = 2,
      18             :     EH_LABEL    = 3,
      19             :     GC_LABEL    = 4,
      20             :     ANNOTATION_LABEL    = 5,
      21             :     KILL        = 6,
      22             :     EXTRACT_SUBREG      = 7,
      23             :     INSERT_SUBREG       = 8,
      24             :     IMPLICIT_DEF        = 9,
      25             :     SUBREG_TO_REG       = 10,
      26             :     COPY_TO_REGCLASS    = 11,
      27             :     DBG_VALUE   = 12,
      28             :     DBG_LABEL   = 13,
      29             :     REG_SEQUENCE        = 14,
      30             :     COPY        = 15,
      31             :     BUNDLE      = 16,
      32             :     LIFETIME_START      = 17,
      33             :     LIFETIME_END        = 18,
      34             :     STACKMAP    = 19,
      35             :     FENTRY_CALL = 20,
      36             :     PATCHPOINT  = 21,
      37             :     LOAD_STACK_GUARD    = 22,
      38             :     STATEPOINT  = 23,
      39             :     LOCAL_ESCAPE        = 24,
      40             :     FAULTING_OP = 25,
      41             :     PATCHABLE_OP        = 26,
      42             :     PATCHABLE_FUNCTION_ENTER    = 27,
      43             :     PATCHABLE_RET       = 28,
      44             :     PATCHABLE_FUNCTION_EXIT     = 29,
      45             :     PATCHABLE_TAIL_CALL = 30,
      46             :     PATCHABLE_EVENT_CALL        = 31,
      47             :     PATCHABLE_TYPED_EVENT_CALL  = 32,
      48             :     ICALL_BRANCH_FUNNEL = 33,
      49             :     G_ADD       = 34,
      50             :     G_SUB       = 35,
      51             :     G_MUL       = 36,
      52             :     G_SDIV      = 37,
      53             :     G_UDIV      = 38,
      54             :     G_SREM      = 39,
      55             :     G_UREM      = 40,
      56             :     G_AND       = 41,
      57             :     G_OR        = 42,
      58             :     G_XOR       = 43,
      59             :     G_IMPLICIT_DEF      = 44,
      60             :     G_PHI       = 45,
      61             :     G_FRAME_INDEX       = 46,
      62             :     G_GLOBAL_VALUE      = 47,
      63             :     G_EXTRACT   = 48,
      64             :     G_UNMERGE_VALUES    = 49,
      65             :     G_INSERT    = 50,
      66             :     G_MERGE_VALUES      = 51,
      67             :     G_PTRTOINT  = 52,
      68             :     G_INTTOPTR  = 53,
      69             :     G_BITCAST   = 54,
      70             :     G_LOAD      = 55,
      71             :     G_SEXTLOAD  = 56,
      72             :     G_ZEXTLOAD  = 57,
      73             :     G_STORE     = 58,
      74             :     G_ATOMIC_CMPXCHG_WITH_SUCCESS       = 59,
      75             :     G_ATOMIC_CMPXCHG    = 60,
      76             :     G_ATOMICRMW_XCHG    = 61,
      77             :     G_ATOMICRMW_ADD     = 62,
      78             :     G_ATOMICRMW_SUB     = 63,
      79             :     G_ATOMICRMW_AND     = 64,
      80             :     G_ATOMICRMW_NAND    = 65,
      81             :     G_ATOMICRMW_OR      = 66,
      82             :     G_ATOMICRMW_XOR     = 67,
      83             :     G_ATOMICRMW_MAX     = 68,
      84             :     G_ATOMICRMW_MIN     = 69,
      85             :     G_ATOMICRMW_UMAX    = 70,
      86             :     G_ATOMICRMW_UMIN    = 71,
      87             :     G_BRCOND    = 72,
      88             :     G_BRINDIRECT        = 73,
      89             :     G_INTRINSIC = 74,
      90             :     G_INTRINSIC_W_SIDE_EFFECTS  = 75,
      91             :     G_ANYEXT    = 76,
      92             :     G_TRUNC     = 77,
      93             :     G_CONSTANT  = 78,
      94             :     G_FCONSTANT = 79,
      95             :     G_VASTART   = 80,
      96             :     G_VAARG     = 81,
      97             :     G_SEXT      = 82,
      98             :     G_ZEXT      = 83,
      99             :     G_SHL       = 84,
     100             :     G_LSHR      = 85,
     101             :     G_ASHR      = 86,
     102             :     G_ICMP      = 87,
     103             :     G_FCMP      = 88,
     104             :     G_SELECT    = 89,
     105             :     G_UADDE     = 90,
     106             :     G_USUBE     = 91,
     107             :     G_SADDO     = 92,
     108             :     G_SSUBO     = 93,
     109             :     G_UMULO     = 94,
     110             :     G_SMULO     = 95,
     111             :     G_UMULH     = 96,
     112             :     G_SMULH     = 97,
     113             :     G_FADD      = 98,
     114             :     G_FSUB      = 99,
     115             :     G_FMUL      = 100,
     116             :     G_FMA       = 101,
     117             :     G_FDIV      = 102,
     118             :     G_FREM      = 103,
     119             :     G_FPOW      = 104,
     120             :     G_FEXP      = 105,
     121             :     G_FEXP2     = 106,
     122             :     G_FLOG      = 107,
     123             :     G_FLOG2     = 108,
     124             :     G_FNEG      = 109,
     125             :     G_FPEXT     = 110,
     126             :     G_FPTRUNC   = 111,
     127             :     G_FPTOSI    = 112,
     128             :     G_FPTOUI    = 113,
     129             :     G_SITOFP    = 114,
     130             :     G_UITOFP    = 115,
     131             :     G_FABS      = 116,
     132             :     G_GEP       = 117,
     133             :     G_PTR_MASK  = 118,
     134             :     G_BR        = 119,
     135             :     G_INSERT_VECTOR_ELT = 120,
     136             :     G_EXTRACT_VECTOR_ELT        = 121,
     137             :     G_SHUFFLE_VECTOR    = 122,
     138             :     G_BSWAP     = 123,
     139             :     G_ADDRSPACE_CAST    = 124,
     140             :     ADJCALLSTACKDOWN    = 125,
     141             :     ADJCALLSTACKUP      = 126,
     142             :     ADJDYNALLOC = 127,
     143             :     CALL        = 128,
     144             :     CALLR       = 129,
     145             :     ADDC_F_I_HI = 130,
     146             :     ADDC_F_I_LO = 131,
     147             :     ADDC_F_R    = 132,
     148             :     ADDC_I_HI   = 133,
     149             :     ADDC_I_LO   = 134,
     150             :     ADDC_R      = 135,
     151             :     ADD_F_I_HI  = 136,
     152             :     ADD_F_I_LO  = 137,
     153             :     ADD_F_R     = 138,
     154             :     ADD_I_HI    = 139,
     155             :     ADD_I_LO    = 140,
     156             :     ADD_R       = 141,
     157             :     AND_F_I_HI  = 142,
     158             :     AND_F_I_LO  = 143,
     159             :     AND_F_R     = 144,
     160             :     AND_I_HI    = 145,
     161             :     AND_I_LO    = 146,
     162             :     AND_R       = 147,
     163             :     BRCC        = 148,
     164             :     BRIND_CC    = 149,
     165             :     BRIND_CCA   = 150,
     166             :     BRR = 151,
     167             :     BT  = 152,
     168             :     JR  = 153,
     169             :     LDADDR      = 154,
     170             :     LDBs_RI     = 155,
     171             :     LDBs_RR     = 156,
     172             :     LDBz_RI     = 157,
     173             :     LDBz_RR     = 158,
     174             :     LDHs_RI     = 159,
     175             :     LDHs_RR     = 160,
     176             :     LDHz_RI     = 161,
     177             :     LDHz_RR     = 162,
     178             :     LDW_RI      = 163,
     179             :     LDW_RR      = 164,
     180             :     LDWz_RR     = 165,
     181             :     LEADZ       = 166,
     182             :     LOG0        = 167,
     183             :     LOG1        = 168,
     184             :     LOG2        = 169,
     185             :     LOG3        = 170,
     186             :     LOG4        = 171,
     187             :     MOVHI       = 172,
     188             :     NOP = 173,
     189             :     OR_F_I_HI   = 174,
     190             :     OR_F_I_LO   = 175,
     191             :     OR_F_R      = 176,
     192             :     OR_I_HI     = 177,
     193             :     OR_I_LO     = 178,
     194             :     OR_R        = 179,
     195             :     POPC        = 180,
     196             :     RET = 181,
     197             :     SA_F_I      = 182,
     198             :     SA_I        = 183,
     199             :     SCC = 184,
     200             :     SELECT      = 185,
     201             :     SFSUB_F_RI_HI       = 186,
     202             :     SFSUB_F_RI_LO       = 187,
     203             :     SFSUB_F_RR  = 188,
     204             :     SHL_F_R     = 189,
     205             :     SHL_R       = 190,
     206             :     SLI = 191,
     207             :     SL_F_I      = 192,
     208             :     SL_I        = 193,
     209             :     SRA_F_R     = 194,
     210             :     SRA_R       = 195,
     211             :     SRL_F_R     = 196,
     212             :     SRL_R       = 197,
     213             :     STADDR      = 198,
     214             :     STB_RI      = 199,
     215             :     STB_RR      = 200,
     216             :     STH_RI      = 201,
     217             :     STH_RR      = 202,
     218             :     SUBB_F_I_HI = 203,
     219             :     SUBB_F_I_LO = 204,
     220             :     SUBB_F_R    = 205,
     221             :     SUBB_I_HI   = 206,
     222             :     SUBB_I_LO   = 207,
     223             :     SUBB_R      = 208,
     224             :     SUB_F_I_HI  = 209,
     225             :     SUB_F_I_LO  = 210,
     226             :     SUB_F_R     = 211,
     227             :     SUB_I_HI    = 212,
     228             :     SUB_I_LO    = 213,
     229             :     SUB_R       = 214,
     230             :     SW_RI       = 215,
     231             :     SW_RR       = 216,
     232             :     TRAILZ      = 217,
     233             :     XOR_F_I_HI  = 218,
     234             :     XOR_F_I_LO  = 219,
     235             :     XOR_F_R     = 220,
     236             :     XOR_I_HI    = 221,
     237             :     XOR_I_LO    = 222,
     238             :     XOR_R       = 223,
     239             :     INSTRUCTION_LIST_END = 224
     240             :   };
     241             : 
     242             : } // end Lanai namespace
     243             : } // end llvm namespace
     244             : #endif // GET_INSTRINFO_ENUM
     245             : 
     246             : #ifdef GET_INSTRINFO_SCHED_ENUM
     247             : #undef GET_INSTRINFO_SCHED_ENUM
     248             : namespace llvm {
     249             : 
     250             : namespace Lanai {
     251             : namespace Sched {
     252             :   enum {
     253             :     NoInstrModel        = 0,
     254             :     IIC_ALU_WriteALU    = 1,
     255             :     IIC_ALU     = 2,
     256             :     IIC_LD_WriteLD      = 3,
     257             :     IIC_LDSW_WriteLDSW  = 4,
     258             :     WriteLD     = 5,
     259             :     IIC_ST_WriteST      = 6,
     260             :     IIC_STSW_WriteSTSW  = 7,
     261             :     SCHED_LIST_END = 8
     262             :   };
     263             : } // end Sched namespace
     264             : } // end Lanai namespace
     265             : } // end llvm namespace
     266             : #endif // GET_INSTRINFO_SCHED_ENUM
     267             : 
     268             : #ifdef GET_INSTRINFO_MC_DESC
     269             : #undef GET_INSTRINFO_MC_DESC
     270             : namespace llvm {
     271             : 
     272             : static const MCPhysReg ImplicitList1[] = { Lanai::SP, 0 };
     273             : static const MCPhysReg ImplicitList2[] = { Lanai::RCA, 0 };
     274             : static const MCPhysReg ImplicitList3[] = { Lanai::SR, 0 };
     275             : 
     276             : static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     277             : static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     278             : static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     279             : static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     280             : static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     281             : static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     282             : static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     283             : static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     284             : static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
     285             : static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     286             : static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     287             : static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     288             : static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     289             : static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     290             : static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     291             : static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
     292             : static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     293             : static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     294             : static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     295             : static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     296             : static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
     297             : static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
     298             : static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     299             : static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     300             : static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
     301             : static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     302             : static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
     303             : static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
     304             : static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
     305             : static const MCOperandInfo OperandInfo31[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     306             : static const MCOperandInfo OperandInfo32[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     307             : static const MCOperandInfo OperandInfo33[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     308             : static const MCOperandInfo OperandInfo34[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
     309             : static const MCOperandInfo OperandInfo35[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     310             : static const MCOperandInfo OperandInfo36[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     311             : static const MCOperandInfo OperandInfo37[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     312             : static const MCOperandInfo OperandInfo38[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     313             : static const MCOperandInfo OperandInfo39[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     314             : 
     315             : extern const MCInstrDesc LanaiInsts[] = {
     316             :   { 0,  1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #0 = PHI
     317             :   { 1,  0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
     318             :   { 2,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #2 = CFI_INSTRUCTION
     319             :   { 3,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #3 = EH_LABEL
     320             :   { 4,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #4 = GC_LABEL
     321             :   { 5,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #5 = ANNOTATION_LABEL
     322             :   { 6,  0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #6 = KILL
     323             :   { 7,  3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #7 = EXTRACT_SUBREG
     324             :   { 8,  4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #8 = INSERT_SUBREG
     325             :   { 9,  1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #9 = IMPLICIT_DEF
     326             :   { 10, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #10 = SUBREG_TO_REG
     327             :   { 11, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #11 = COPY_TO_REGCLASS
     328             :   { 12, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #12 = DBG_VALUE
     329             :   { 13, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #13 = DBG_LABEL
     330             :   { 14, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #14 = REG_SEQUENCE
     331             :   { 15, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #15 = COPY
     332             :   { 16, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #16 = BUNDLE
     333             :   { 17, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #17 = LIFETIME_START
     334             :   { 18, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #18 = LIFETIME_END
     335             :   { 19, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #19 = STACKMAP
     336             :   { 20, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #20 = FENTRY_CALL
     337             :   { 21, 6,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #21 = PATCHPOINT
     338             :   { 22, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #22 = LOAD_STACK_GUARD
     339             :   { 23, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #23 = STATEPOINT
     340             :   { 24, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #24 = LOCAL_ESCAPE
     341             :   { 25, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #25 = FAULTING_OP
     342             :   { 26, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #26 = PATCHABLE_OP
     343             :   { 27, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #27 = PATCHABLE_FUNCTION_ENTER
     344             :   { 28, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #28 = PATCHABLE_RET
     345             :   { 29, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #29 = PATCHABLE_FUNCTION_EXIT
     346             :   { 30, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #30 = PATCHABLE_TAIL_CALL
     347             :   { 31, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #31 = PATCHABLE_EVENT_CALL
     348             :   { 32, 3,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #32 = PATCHABLE_TYPED_EVENT_CALL
     349             :   { 33, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #33 = ICALL_BRANCH_FUNNEL
     350             :   { 34, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #34 = G_ADD
     351             :   { 35, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #35 = G_SUB
     352             :   { 36, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #36 = G_MUL
     353             :   { 37, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #37 = G_SDIV
     354             :   { 38, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #38 = G_UDIV
     355             :   { 39, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #39 = G_SREM
     356             :   { 40, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #40 = G_UREM
     357             :   { 41, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #41 = G_AND
     358             :   { 42, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #42 = G_OR
     359             :   { 43, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #43 = G_XOR
     360             :   { 44, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #44 = G_IMPLICIT_DEF
     361             :   { 45, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #45 = G_PHI
     362             :   { 46, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #46 = G_FRAME_INDEX
     363             :   { 47, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #47 = G_GLOBAL_VALUE
     364             :   { 48, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #48 = G_EXTRACT
     365             :   { 49, 2,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #49 = G_UNMERGE_VALUES
     366             :   { 50, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #50 = G_INSERT
     367             :   { 51, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #51 = G_MERGE_VALUES
     368             :   { 52, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #52 = G_PTRTOINT
     369             :   { 53, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #53 = G_INTTOPTR
     370             :   { 54, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #54 = G_BITCAST
     371             :   { 55, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #55 = G_LOAD
     372             :   { 56, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #56 = G_SEXTLOAD
     373             :   { 57, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #57 = G_ZEXTLOAD
     374             :   { 58, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #58 = G_STORE
     375             :   { 59, 5,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #59 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
     376             :   { 60, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #60 = G_ATOMIC_CMPXCHG
     377             :   { 61, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #61 = G_ATOMICRMW_XCHG
     378             :   { 62, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #62 = G_ATOMICRMW_ADD
     379             :   { 63, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #63 = G_ATOMICRMW_SUB
     380             :   { 64, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #64 = G_ATOMICRMW_AND
     381             :   { 65, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #65 = G_ATOMICRMW_NAND
     382             :   { 66, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #66 = G_ATOMICRMW_OR
     383             :   { 67, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #67 = G_ATOMICRMW_XOR
     384             :   { 68, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #68 = G_ATOMICRMW_MAX
     385             :   { 69, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #69 = G_ATOMICRMW_MIN
     386             :   { 70, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #70 = G_ATOMICRMW_UMAX
     387             :   { 71, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #71 = G_ATOMICRMW_UMIN
     388             :   { 72, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #72 = G_BRCOND
     389             :   { 73, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #73 = G_BRINDIRECT
     390             :   { 74, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #74 = G_INTRINSIC
     391             :   { 75, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #75 = G_INTRINSIC_W_SIDE_EFFECTS
     392             :   { 76, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #76 = G_ANYEXT
     393             :   { 77, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #77 = G_TRUNC
     394             :   { 78, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #78 = G_CONSTANT
     395             :   { 79, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #79 = G_FCONSTANT
     396             :   { 80, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #80 = G_VASTART
     397             :   { 81, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #81 = G_VAARG
     398             :   { 82, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #82 = G_SEXT
     399             :   { 83, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #83 = G_ZEXT
     400             :   { 84, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #84 = G_SHL
     401             :   { 85, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #85 = G_LSHR
     402             :   { 86, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #86 = G_ASHR
     403             :   { 87, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #87 = G_ICMP
     404             :   { 88, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #88 = G_FCMP
     405             :   { 89, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #89 = G_SELECT
     406             :   { 90, 5,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #90 = G_UADDE
     407             :   { 91, 5,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #91 = G_USUBE
     408             :   { 92, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #92 = G_SADDO
     409             :   { 93, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #93 = G_SSUBO
     410             :   { 94, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #94 = G_UMULO
     411             :   { 95, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #95 = G_SMULO
     412             :   { 96, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #96 = G_UMULH
     413             :   { 97, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #97 = G_SMULH
     414             :   { 98, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #98 = G_FADD
     415             :   { 99, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #99 = G_FSUB
     416             :   { 100,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #100 = G_FMUL
     417             :   { 101,        4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #101 = G_FMA
     418             :   { 102,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #102 = G_FDIV
     419             :   { 103,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #103 = G_FREM
     420             :   { 104,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #104 = G_FPOW
     421             :   { 105,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #105 = G_FEXP
     422             :   { 106,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #106 = G_FEXP2
     423             :   { 107,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #107 = G_FLOG
     424             :   { 108,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #108 = G_FLOG2
     425             :   { 109,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #109 = G_FNEG
     426             :   { 110,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #110 = G_FPEXT
     427             :   { 111,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #111 = G_FPTRUNC
     428             :   { 112,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #112 = G_FPTOSI
     429             :   { 113,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #113 = G_FPTOUI
     430             :   { 114,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #114 = G_SITOFP
     431             :   { 115,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #115 = G_UITOFP
     432             :   { 116,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #116 = G_FABS
     433             :   { 117,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #117 = G_GEP
     434             :   { 118,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #118 = G_PTR_MASK
     435             :   { 119,        1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #119 = G_BR
     436             :   { 120,        4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #120 = G_INSERT_VECTOR_ELT
     437             :   { 121,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #121 = G_EXTRACT_VECTOR_ELT
     438             :   { 122,        4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #122 = G_SHUFFLE_VECTOR
     439             :   { 123,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #123 = G_BSWAP
     440             :   { 124,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #124 = G_ADDRSPACE_CAST
     441             :   { 125,        2,      0,      4,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr },  // Inst #125 = ADJCALLSTACKDOWN
     442             :   { 126,        2,      0,      4,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr },  // Inst #126 = ADJCALLSTACKUP
     443             :   { 127,        2,      1,      4,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #127 = ADJDYNALLOC
     444             :   { 128,        1,      0,      4,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo2, -1 ,nullptr },  // Inst #128 = CALL
     445             :   { 129,        1,      0,      4,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo32, -1 ,nullptr },  // Inst #129 = CALLR
     446             :   { 130,        3,      1,      4,      1,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #130 = ADDC_F_I_HI
     447             :   { 131,        3,      1,      4,      1,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #131 = ADDC_F_I_LO
     448             :   { 132,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #132 = ADDC_F_R
     449             :   { 133,        3,      1,      4,      1,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #133 = ADDC_I_HI
     450             :   { 134,        3,      1,      4,      1,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #134 = ADDC_I_LO
     451             :   { 135,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #135 = ADDC_R
     452             :   { 136,        3,      1,      4,      1,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #136 = ADD_F_I_HI
     453             :   { 137,        3,      1,      4,      1,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #137 = ADD_F_I_LO
     454             :   { 138,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #138 = ADD_F_R
     455             :   { 139,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #139 = ADD_I_HI
     456             :   { 140,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #140 = ADD_I_LO
     457             :   { 141,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #141 = ADD_R
     458             :   { 142,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #142 = AND_F_I_HI
     459             :   { 143,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #143 = AND_F_I_LO
     460             :   { 144,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #144 = AND_F_R
     461             :   { 145,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #145 = AND_I_HI
     462             :   { 146,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #146 = AND_I_LO
     463             :   { 147,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #147 = AND_R
     464             :   { 148,        2,      0,      4,      2,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #148 = BRCC
     465             :   { 149,        2,      0,      4,      1,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #149 = BRIND_CC
     466             :   { 150,        3,      0,      4,      1,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #150 = BRIND_CCA
     467             :   { 151,        2,      0,      4,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #151 = BRR
     468             :   { 152,        1,      0,      4,      2,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #152 = BT
     469             :   { 153,        1,      0,      4,      1,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #153 = JR
     470             :   { 154,        2,      1,      4,      3,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #154 = LDADDR
     471             :   { 155,        4,      1,      4,      4,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #155 = LDBs_RI
     472             :   { 156,        4,      1,      4,      5,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #156 = LDBs_RR
     473             :   { 157,        4,      1,      4,      4,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #157 = LDBz_RI
     474             :   { 158,        4,      1,      4,      5,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #158 = LDBz_RR
     475             :   { 159,        4,      1,      4,      4,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #159 = LDHs_RI
     476             :   { 160,        4,      1,      4,      5,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #160 = LDHs_RR
     477             :   { 161,        4,      1,      4,      4,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #161 = LDHz_RI
     478             :   { 162,        4,      1,      4,      5,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #162 = LDHz_RR
     479             :   { 163,        4,      1,      4,      3,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #163 = LDW_RI
     480             :   { 164,        4,      1,      4,      5,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #164 = LDW_RR
     481             :   { 165,        4,      1,      4,      5,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #165 = LDWz_RR
     482             :   { 166,        2,      1,      4,      1,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #166 = LEADZ
     483             :   { 167,        0,      0,      4,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #167 = LOG0
     484             :   { 168,        0,      0,      4,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #168 = LOG1
     485             :   { 169,        0,      0,      4,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #169 = LOG2
     486             :   { 170,        0,      0,      4,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #170 = LOG3
     487             :   { 171,        0,      0,      4,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #171 = LOG4
     488             :   { 172,        2,      1,      4,      1,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #172 = MOVHI
     489             :   { 173,        0,      0,      4,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #173 = NOP
     490             :   { 174,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #174 = OR_F_I_HI
     491             :   { 175,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #175 = OR_F_I_LO
     492             :   { 176,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #176 = OR_F_R
     493             :   { 177,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #177 = OR_I_HI
     494             :   { 178,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #178 = OR_I_LO
     495             :   { 179,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #179 = OR_R
     496             :   { 180,        2,      1,      4,      1,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #180 = POPC
     497             :   { 181,        0,      0,      4,      0,      0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, nullptr, nullptr, -1 ,nullptr },  // Inst #181 = RET
     498             :   { 182,        3,      1,      4,      1,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #182 = SA_F_I
     499             :   { 183,        3,      1,      4,      1,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #183 = SA_I
     500             :   { 184,        2,      1,      4,      2,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #184 = SCC
     501             :   { 185,        4,      1,      4,      1,      0|(1ULL<<MCID::Select)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #185 = SELECT
     502             :   { 186,        2,      0,      4,      1,      0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo35, -1 ,nullptr },  // Inst #186 = SFSUB_F_RI_HI
     503             :   { 187,        2,      0,      4,      1,      0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo35, -1 ,nullptr },  // Inst #187 = SFSUB_F_RI_LO
     504             :   { 188,        2,      0,      4,      1,      0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo31, -1 ,nullptr },  // Inst #188 = SFSUB_F_RR
     505             :   { 189,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #189 = SHL_F_R
     506             :   { 190,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #190 = SHL_R
     507             :   { 191,        2,      1,      4,      0,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #191 = SLI
     508             :   { 192,        3,      1,      4,      1,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #192 = SL_F_I
     509             :   { 193,        3,      1,      4,      1,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #193 = SL_I
     510             :   { 194,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #194 = SRA_F_R
     511             :   { 195,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #195 = SRA_R
     512             :   { 196,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #196 = SRL_F_R
     513             :   { 197,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #197 = SRL_R
     514             :   { 198,        2,      0,      4,      6,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #198 = STADDR
     515             :   { 199,        4,      0,      4,      7,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #199 = STB_RI
     516             :   { 200,        4,      0,      4,      6,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #200 = STB_RR
     517             :   { 201,        4,      0,      4,      7,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #201 = STH_RI
     518             :   { 202,        4,      0,      4,      6,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #202 = STH_RR
     519             :   { 203,        3,      1,      4,      1,      0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #203 = SUBB_F_I_HI
     520             :   { 204,        3,      1,      4,      1,      0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #204 = SUBB_F_I_LO
     521             :   { 205,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #205 = SUBB_F_R
     522             :   { 206,        3,      1,      4,      1,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #206 = SUBB_I_HI
     523             :   { 207,        3,      1,      4,      1,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #207 = SUBB_I_LO
     524             :   { 208,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #208 = SUBB_R
     525             :   { 209,        3,      1,      4,      1,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #209 = SUB_F_I_HI
     526             :   { 210,        3,      1,      4,      1,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #210 = SUB_F_I_LO
     527             :   { 211,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #211 = SUB_F_R
     528             :   { 212,        3,      1,      4,      1,      0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #212 = SUB_I_HI
     529             :   { 213,        3,      1,      4,      1,      0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #213 = SUB_I_LO
     530             :   { 214,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #214 = SUB_R
     531             :   { 215,        4,      0,      4,      6,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #215 = SW_RI
     532             :   { 216,        4,      0,      4,      6,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #216 = SW_RR
     533             :   { 217,        2,      1,      4,      1,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #217 = TRAILZ
     534             :   { 218,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #218 = XOR_F_I_HI
     535             :   { 219,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #219 = XOR_F_I_LO
     536             :   { 220,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #220 = XOR_F_R
     537             :   { 221,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #221 = XOR_I_HI
     538             :   { 222,        3,      1,      4,      1,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #222 = XOR_I_LO
     539             :   { 223,        4,      1,      4,      1,      0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #223 = XOR_R
     540             : };
     541             : 
     542             : extern const char LanaiInstrNameData[] = {
     543             :   /* 0 */ 'L', 'O', 'G', '0', 0,
     544             :   /* 5 */ 'L', 'O', 'G', '1', 0,
     545             :   /* 10 */ 'G', '_', 'F', 'L', 'O', 'G', '2', 0,
     546             :   /* 18 */ 'G', '_', 'F', 'E', 'X', 'P', '2', 0,
     547             :   /* 26 */ 'L', 'O', 'G', '3', 0,
     548             :   /* 31 */ 'L', 'O', 'G', '4', 0,
     549             :   /* 36 */ 'B', 'R', 'I', 'N', 'D', '_', 'C', 'C', 'A', 0,
     550             :   /* 46 */ 'G', '_', 'F', 'M', 'A', 0,
     551             :   /* 52 */ 'G', '_', 'F', 'S', 'U', 'B', 0,
     552             :   /* 59 */ 'G', '_', 'S', 'U', 'B', 0,
     553             :   /* 65 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'S', 'U', 'B', 0,
     554             :   /* 81 */ 'B', 'R', 'C', 'C', 0,
     555             :   /* 86 */ 'S', 'C', 'C', 0,
     556             :   /* 90 */ 'B', 'R', 'I', 'N', 'D', '_', 'C', 'C', 0,
     557             :   /* 99 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', 0,
     558             :   /* 111 */ 'G', '_', 'F', 'P', 'T', 'R', 'U', 'N', 'C', 0,
     559             :   /* 121 */ 'G', '_', 'T', 'R', 'U', 'N', 'C', 0,
     560             :   /* 129 */ 'A', 'D', 'J', 'D', 'Y', 'N', 'A', 'L', 'L', 'O', 'C', 0,
     561             :   /* 141 */ 'P', 'O', 'P', 'C', 0,
     562             :   /* 146 */ 'G', '_', 'S', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
     563             :   /* 157 */ 'G', '_', 'Z', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
     564             :   /* 168 */ 'G', '_', 'L', 'O', 'A', 'D', 0,
     565             :   /* 175 */ 'G', '_', 'F', 'A', 'D', 'D', 0,
     566             :   /* 182 */ 'G', '_', 'A', 'D', 'D', 0,
     567             :   /* 188 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'D', 'D', 0,
     568             :   /* 204 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'N', 'A', 'N', 'D', 0,
     569             :   /* 221 */ 'G', '_', 'A', 'N', 'D', 0,
     570             :   /* 227 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'N', 'D', 0,
     571             :   /* 243 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
     572             :   /* 256 */ 'G', '_', 'B', 'R', 'C', 'O', 'N', 'D', 0,
     573             :   /* 265 */ 'L', 'O', 'A', 'D', '_', 'S', 'T', 'A', 'C', 'K', '_', 'G', 'U', 'A', 'R', 'D', 0,
     574             :   /* 282 */ 'G', '_', 'U', 'S', 'U', 'B', 'E', 0,
     575             :   /* 290 */ 'R', 'E', 'G', '_', 'S', 'E', 'Q', 'U', 'E', 'N', 'C', 'E', 0,
     576             :   /* 303 */ 'G', '_', 'U', 'A', 'D', 'D', 'E', 0,
     577             :   /* 311 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
     578             :   /* 318 */ 'L', 'O', 'C', 'A', 'L', '_', 'E', 'S', 'C', 'A', 'P', 'E', 0,
     579             :   /* 331 */ 'G', '_', 'S', 'T', 'O', 'R', 'E', 0,
     580             :   /* 339 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
     581             :   /* 349 */ 'G', '_', 'G', 'L', 'O', 'B', 'A', 'L', '_', 'V', 'A', 'L', 'U', 'E', 0,
     582             :   /* 364 */ 'G', '_', 'I', 'M', 'P', 'L', 'I', 'C', 'I', 'T', '_', 'D', 'E', 'F', 0,
     583             :   /* 379 */ 'G', '_', 'F', 'N', 'E', 'G', 0,
     584             :   /* 386 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
     585             :   /* 401 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
     586             :   /* 415 */ 'S', 'U', 'B', 'R', 'E', 'G', '_', 'T', 'O', '_', 'R', 'E', 'G', 0,
     587             :   /* 429 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', 0,
     588             :   /* 446 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'C', 'H', 'G', 0,
     589             :   /* 463 */ 'G', '_', 'F', 'L', 'O', 'G', 0,
     590             :   /* 470 */ 'G', '_', 'V', 'A', 'A', 'R', 'G', 0,
     591             :   /* 478 */ 'G', '_', 'S', 'M', 'U', 'L', 'H', 0,
     592             :   /* 486 */ 'G', '_', 'U', 'M', 'U', 'L', 'H', 0,
     593             :   /* 494 */ 'G', '_', 'P', 'H', 'I', 0,
     594             :   /* 500 */ 'M', 'O', 'V', 'H', 'I', 0,
     595             :   /* 506 */ 'S', 'F', 'S', 'U', 'B', '_', 'F', '_', 'R', 'I', '_', 'H', 'I', 0,
     596             :   /* 520 */ 'S', 'U', 'B', 'B', '_', 'I', '_', 'H', 'I', 0,
     597             :   /* 530 */ 'S', 'U', 'B', '_', 'I', '_', 'H', 'I', 0,
     598             :   /* 539 */ 'A', 'D', 'D', 'C', '_', 'I', '_', 'H', 'I', 0,
     599             :   /* 549 */ 'A', 'D', 'D', '_', 'I', '_', 'H', 'I', 0,
     600             :   /* 558 */ 'A', 'N', 'D', '_', 'I', '_', 'H', 'I', 0,
     601             :   /* 567 */ 'S', 'U', 'B', 'B', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
     602             :   /* 579 */ 'S', 'U', 'B', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
     603             :   /* 590 */ 'A', 'D', 'D', 'C', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
     604             :   /* 602 */ 'A', 'D', 'D', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
     605             :   /* 613 */ 'A', 'N', 'D', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
     606             :   /* 624 */ 'X', 'O', 'R', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
     607             :   /* 635 */ 'X', 'O', 'R', '_', 'I', '_', 'H', 'I', 0,
     608             :   /* 644 */ 'S', 'L', 'I', 0,
     609             :   /* 648 */ 'S', 'T', 'B', '_', 'R', 'I', 0,
     610             :   /* 655 */ 'S', 'T', 'H', '_', 'R', 'I', 0,
     611             :   /* 662 */ 'L', 'D', 'W', '_', 'R', 'I', 0,
     612             :   /* 669 */ 'S', 'W', '_', 'R', 'I', 0,
     613             :   /* 675 */ 'L', 'D', 'B', 's', '_', 'R', 'I', 0,
     614             :   /* 683 */ 'L', 'D', 'H', 's', '_', 'R', 'I', 0,
     615             :   /* 691 */ 'L', 'D', 'B', 'z', '_', 'R', 'I', 0,
     616             :   /* 699 */ 'L', 'D', 'H', 'z', '_', 'R', 'I', 0,
     617             :   /* 707 */ 'G', '_', 'F', 'P', 'T', 'O', 'S', 'I', 0,
     618             :   /* 716 */ 'G', '_', 'F', 'P', 'T', 'O', 'U', 'I', 0,
     619             :   /* 725 */ 'S', 'A', '_', 'I', 0,
     620             :   /* 730 */ 'S', 'A', '_', 'F', '_', 'I', 0,
     621             :   /* 737 */ 'S', 'L', '_', 'F', '_', 'I', 0,
     622             :   /* 744 */ 'S', 'L', '_', 'I', 0,
     623             :   /* 749 */ 'G', '_', 'P', 'T', 'R', '_', 'M', 'A', 'S', 'K', 0,
     624             :   /* 760 */ 'G', 'C', '_', 'L', 'A', 'B', 'E', 'L', 0,
     625             :   /* 769 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0,
     626             :   /* 779 */ 'E', 'H', '_', 'L', 'A', 'B', 'E', 'L', 0,
     627             :   /* 788 */ 'A', 'N', 'N', 'O', 'T', 'A', 'T', 'I', 'O', 'N', '_', 'L', 'A', 'B', 'E', 'L', 0,
     628             :   /* 805 */ 'I', 'C', 'A', 'L', 'L', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'F', 'U', 'N', 'N', 'E', 'L', 0,
     629             :   /* 825 */ 'G', '_', 'S', 'H', 'L', 0,
     630             :   /* 831 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'A', 'I', 'L', '_', 'C', 'A', 'L', 'L', 0,
     631             :   /* 851 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'Y', 'P', 'E', 'D', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
     632             :   /* 878 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
     633             :   /* 899 */ 'F', 'E', 'N', 'T', 'R', 'Y', '_', 'C', 'A', 'L', 'L', 0,
     634             :   /* 911 */ 'K', 'I', 'L', 'L', 0,
     635             :   /* 916 */ 'G', '_', 'F', 'M', 'U', 'L', 0,
     636             :   /* 923 */ 'G', '_', 'M', 'U', 'L', 0,
     637             :   /* 929 */ 'G', '_', 'F', 'R', 'E', 'M', 0,
     638             :   /* 936 */ 'G', '_', 'S', 'R', 'E', 'M', 0,
     639             :   /* 943 */ 'G', '_', 'U', 'R', 'E', 'M', 0,
     640             :   /* 950 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', 0,
     641             :   /* 960 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'I', 'N', 0,
     642             :   /* 977 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'I', 'N', 0,
     643             :   /* 993 */ 'C', 'F', 'I', '_', 'I', 'N', 'S', 'T', 'R', 'U', 'C', 'T', 'I', 'O', 'N', 0,
     644             :   /* 1009 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 0,
     645             :   /* 1026 */ 'G', '_', 'S', 'S', 'U', 'B', 'O', 0,
     646             :   /* 1034 */ 'G', '_', 'S', 'A', 'D', 'D', 'O', 0,
     647             :   /* 1042 */ 'G', '_', 'S', 'M', 'U', 'L', 'O', 0,
     648             :   /* 1050 */ 'G', '_', 'U', 'M', 'U', 'L', 'O', 0,
     649             :   /* 1058 */ 'S', 'F', 'S', 'U', 'B', '_', 'F', '_', 'R', 'I', '_', 'L', 'O', 0,
     650             :   /* 1072 */ 'S', 'U', 'B', 'B', '_', 'I', '_', 'L', 'O', 0,
     651             :   /* 1082 */ 'S', 'U', 'B', '_', 'I', '_', 'L', 'O', 0,
     652             :   /* 1091 */ 'A', 'D', 'D', 'C', '_', 'I', '_', 'L', 'O', 0,
     653             :   /* 1101 */ 'A', 'D', 'D', '_', 'I', '_', 'L', 'O', 0,
     654             :   /* 1110 */ 'A', 'N', 'D', '_', 'I', '_', 'L', 'O', 0,
     655             :   /* 1119 */ 'S', 'U', 'B', 'B', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
     656             :   /* 1131 */ 'S', 'U', 'B', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
     657             :   /* 1142 */ 'A', 'D', 'D', 'C', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
     658             :   /* 1154 */ 'A', 'D', 'D', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
     659             :   /* 1165 */ 'A', 'N', 'D', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
     660             :   /* 1176 */ 'X', 'O', 'R', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
     661             :   /* 1187 */ 'X', 'O', 'R', '_', 'I', '_', 'L', 'O', 0,
     662             :   /* 1196 */ 'S', 'T', 'A', 'C', 'K', 'M', 'A', 'P', 0,
     663             :   /* 1205 */ 'G', '_', 'B', 'S', 'W', 'A', 'P', 0,
     664             :   /* 1213 */ 'G', '_', 'G', 'E', 'P', 0,
     665             :   /* 1219 */ 'G', '_', 'S', 'I', 'T', 'O', 'F', 'P', 0,
     666             :   /* 1228 */ 'G', '_', 'U', 'I', 'T', 'O', 'F', 'P', 0,
     667             :   /* 1237 */ 'G', '_', 'F', 'C', 'M', 'P', 0,
     668             :   /* 1244 */ 'G', '_', 'I', 'C', 'M', 'P', 0,
     669             :   /* 1251 */ 'N', 'O', 'P', 0,
     670             :   /* 1255 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'O', 'P', 0,
     671             :   /* 1268 */ 'F', 'A', 'U', 'L', 'T', 'I', 'N', 'G', '_', 'O', 'P', 0,
     672             :   /* 1280 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 0,
     673             :   /* 1295 */ 'G', '_', 'F', 'E', 'X', 'P', 0,
     674             :   /* 1302 */ 'G', '_', 'B', 'R', 0,
     675             :   /* 1307 */ 'L', 'D', 'A', 'D', 'D', 'R', 0,
     676             :   /* 1314 */ 'S', 'T', 'A', 'D', 'D', 'R', 0,
     677             :   /* 1321 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'N', 'T', 'E', 'R', 0,
     678             :   /* 1346 */ 'G', '_', 'A', 'S', 'H', 'R', 0,
     679             :   /* 1353 */ 'G', '_', 'L', 'S', 'H', 'R', 0,
     680             :   /* 1360 */ 'J', 'R', 0,
     681             :   /* 1363 */ 'C', 'A', 'L', 'L', 'R', 0,
     682             :   /* 1369 */ 'G', '_', 'S', 'H', 'U', 'F', 'F', 'L', 'E', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
     683             :   /* 1386 */ 'G', '_', 'X', 'O', 'R', 0,
     684             :   /* 1392 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'O', 'R', 0,
     685             :   /* 1408 */ 'G', '_', 'O', 'R', 0,
     686             :   /* 1413 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'O', 'R', 0,
     687             :   /* 1428 */ 'B', 'R', 'R', 0,
     688             :   /* 1432 */ 'S', 'T', 'B', '_', 'R', 'R', 0,
     689             :   /* 1439 */ 'S', 'F', 'S', 'U', 'B', '_', 'F', '_', 'R', 'R', 0,
     690             :   /* 1450 */ 'S', 'T', 'H', '_', 'R', 'R', 0,
     691             :   /* 1457 */ 'L', 'D', 'W', '_', 'R', 'R', 0,
     692             :   /* 1464 */ 'S', 'W', '_', 'R', 'R', 0,
     693             :   /* 1470 */ 'L', 'D', 'B', 's', '_', 'R', 'R', 0,
     694             :   /* 1478 */ 'L', 'D', 'H', 's', '_', 'R', 'R', 0,
     695             :   /* 1486 */ 'L', 'D', 'B', 'z', '_', 'R', 'R', 0,
     696             :   /* 1494 */ 'L', 'D', 'H', 'z', '_', 'R', 'R', 0,
     697             :   /* 1502 */ 'L', 'D', 'W', 'z', '_', 'R', 'R', 0,
     698             :   /* 1510 */ 'G', '_', 'I', 'N', 'T', 'T', 'O', 'P', 'T', 'R', 0,
     699             :   /* 1521 */ 'S', 'R', 'A', '_', 'R', 0,
     700             :   /* 1527 */ 'S', 'U', 'B', 'B', '_', 'R', 0,
     701             :   /* 1534 */ 'S', 'U', 'B', '_', 'R', 0,
     702             :   /* 1540 */ 'A', 'D', 'D', 'C', '_', 'R', 0,
     703             :   /* 1547 */ 'A', 'D', 'D', '_', 'R', 0,
     704             :   /* 1553 */ 'A', 'N', 'D', '_', 'R', 0,
     705             :   /* 1559 */ 'S', 'R', 'A', '_', 'F', '_', 'R', 0,
     706             :   /* 1567 */ 'S', 'U', 'B', 'B', '_', 'F', '_', 'R', 0,
     707             :   /* 1576 */ 'S', 'U', 'B', '_', 'F', '_', 'R', 0,
     708             :   /* 1584 */ 'A', 'D', 'D', 'C', '_', 'F', '_', 'R', 0,
     709             :   /* 1593 */ 'A', 'D', 'D', '_', 'F', '_', 'R', 0,
     710             :   /* 1601 */ 'A', 'N', 'D', '_', 'F', '_', 'R', 0,
     711             :   /* 1609 */ 'S', 'H', 'L', '_', 'F', '_', 'R', 0,
     712             :   /* 1617 */ 'S', 'R', 'L', '_', 'F', '_', 'R', 0,
     713             :   /* 1625 */ 'X', 'O', 'R', '_', 'F', '_', 'R', 0,
     714             :   /* 1633 */ 'S', 'H', 'L', '_', 'R', 0,
     715             :   /* 1639 */ 'S', 'R', 'L', '_', 'R', 0,
     716             :   /* 1645 */ 'X', 'O', 'R', '_', 'R', 0,
     717             :   /* 1651 */ 'G', '_', 'F', 'A', 'B', 'S', 0,
     718             :   /* 1658 */ 'G', '_', 'U', 'N', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
     719             :   /* 1675 */ 'G', '_', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
     720             :   /* 1690 */ 'C', 'O', 'P', 'Y', '_', 'T', 'O', '_', 'R', 'E', 'G', 'C', 'L', 'A', 'S', 'S', 0,
     721             :   /* 1707 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'W', 'I', 'T', 'H', '_', 'S', 'U', 'C', 'C', 'E', 'S', 'S', 0,
     722             :   /* 1737 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'W', '_', 'S', 'I', 'D', 'E', '_', 'E', 'F', 'F', 'E', 'C', 'T', 'S', 0,
     723             :   /* 1764 */ 'B', 'T', 0,
     724             :   /* 1767 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', 0,
     725             :   /* 1777 */ 'G', '_', 'S', 'E', 'L', 'E', 'C', 'T', 0,
     726             :   /* 1786 */ 'G', '_', 'B', 'R', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', 0,
     727             :   /* 1799 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'R', 'E', 'T', 0,
     728             :   /* 1813 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'X', 'I', 'T', 0,
     729             :   /* 1837 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
     730             :   /* 1858 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
     731             :   /* 1878 */ 'G', '_', 'F', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
     732             :   /* 1890 */ 'G', '_', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
     733             :   /* 1901 */ 'S', 'T', 'A', 'T', 'E', 'P', 'O', 'I', 'N', 'T', 0,
     734             :   /* 1912 */ 'P', 'A', 'T', 'C', 'H', 'P', 'O', 'I', 'N', 'T', 0,
     735             :   /* 1923 */ 'G', '_', 'P', 'T', 'R', 'T', 'O', 'I', 'N', 'T', 0,
     736             :   /* 1934 */ 'G', '_', 'V', 'A', 'S', 'T', 'A', 'R', 'T', 0,
     737             :   /* 1944 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
     738             :   /* 1959 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', 0,
     739             :   /* 1968 */ 'G', '_', 'B', 'I', 'T', 'C', 'A', 'S', 'T', 0,
     740             :   /* 1978 */ 'G', '_', 'A', 'D', 'D', 'R', 'S', 'P', 'A', 'C', 'E', '_', 'C', 'A', 'S', 'T', 0,
     741             :   /* 1995 */ 'G', '_', 'F', 'P', 'E', 'X', 'T', 0,
     742             :   /* 2003 */ 'G', '_', 'S', 'E', 'X', 'T', 0,
     743             :   /* 2010 */ 'G', '_', 'A', 'N', 'Y', 'E', 'X', 'T', 0,
     744             :   /* 2019 */ 'G', '_', 'Z', 'E', 'X', 'T', 0,
     745             :   /* 2026 */ 'G', '_', 'F', 'D', 'I', 'V', 0,
     746             :   /* 2033 */ 'G', '_', 'S', 'D', 'I', 'V', 0,
     747             :   /* 2040 */ 'G', '_', 'U', 'D', 'I', 'V', 0,
     748             :   /* 2047 */ 'G', '_', 'F', 'P', 'O', 'W', 0,
     749             :   /* 2054 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'A', 'X', 0,
     750             :   /* 2071 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'A', 'X', 0,
     751             :   /* 2087 */ 'G', '_', 'F', 'R', 'A', 'M', 'E', '_', 'I', 'N', 'D', 'E', 'X', 0,
     752             :   /* 2101 */ 'C', 'O', 'P', 'Y', 0,
     753             :   /* 2106 */ 'L', 'E', 'A', 'D', 'Z', 0,
     754             :   /* 2112 */ 'T', 'R', 'A', 'I', 'L', 'Z', 0,
     755             : };
     756             : 
     757             : extern const unsigned LanaiInstrNameIndices[] = {
     758             :     496U, 950U, 993U, 779U, 760U, 788U, 911U, 386U, 
     759             :     401U, 366U, 415U, 1690U, 339U, 769U, 290U, 2101U, 
     760             :     311U, 1944U, 243U, 1196U, 899U, 1912U, 265U, 1901U, 
     761             :     318U, 1268U, 1255U, 1321U, 1799U, 1813U, 831U, 878U, 
     762             :     851U, 805U, 182U, 59U, 923U, 2033U, 2040U, 936U, 
     763             :     943U, 221U, 1408U, 1386U, 364U, 494U, 2087U, 349U, 
     764             :     1767U, 1658U, 1959U, 1675U, 1923U, 1510U, 1968U, 168U, 
     765             :     146U, 157U, 331U, 1707U, 429U, 446U, 188U, 65U, 
     766             :     227U, 204U, 1413U, 1392U, 2071U, 977U, 2054U, 960U, 
     767             :     256U, 1786U, 99U, 1737U, 2010U, 121U, 1890U, 1878U, 
     768             :     1934U, 470U, 2003U, 2019U, 825U, 1353U, 1346U, 1244U, 
     769             :     1237U, 1777U, 303U, 282U, 1034U, 1026U, 1050U, 1042U, 
     770             :     486U, 478U, 175U, 52U, 916U, 46U, 2026U, 929U, 
     771             :     2047U, 1295U, 18U, 463U, 10U, 379U, 1995U, 111U, 
     772             :     707U, 716U, 1219U, 1228U, 1651U, 1213U, 749U, 1302U, 
     773             :     1858U, 1837U, 1369U, 1205U, 1978U, 1009U, 1280U, 129U, 
     774             :     846U, 1363U, 590U, 1142U, 1584U, 539U, 1091U, 1540U, 
     775             :     602U, 1154U, 1593U, 549U, 1101U, 1547U, 613U, 1165U, 
     776             :     1601U, 558U, 1110U, 1553U, 81U, 90U, 36U, 1428U, 
     777             :     1764U, 1360U, 1307U, 675U, 1470U, 691U, 1486U, 683U, 
     778             :     1478U, 699U, 1494U, 662U, 1457U, 1502U, 2106U, 0U, 
     779             :     5U, 13U, 26U, 31U, 500U, 1251U, 625U, 1177U, 
     780             :     1626U, 636U, 1188U, 1646U, 141U, 1809U, 730U, 725U, 
     781             :     86U, 1779U, 506U, 1058U, 1439U, 1609U, 1633U, 644U, 
     782             :     737U, 744U, 1559U, 1521U, 1617U, 1639U, 1314U, 648U, 
     783             :     1432U, 655U, 1450U, 567U, 1119U, 1567U, 520U, 1072U, 
     784             :     1527U, 579U, 1131U, 1576U, 530U, 1082U, 1534U, 669U, 
     785             :     1464U, 2112U, 624U, 1176U, 1625U, 635U, 1187U, 1645U, 
     786             : };
     787             : 
     788             : static inline void InitLanaiMCInstrInfo(MCInstrInfo *II) {
     789             :   II->InitMCInstrInfo(LanaiInsts, LanaiInstrNameIndices, LanaiInstrNameData, 224);
     790             : }
     791             : 
     792             : } // end llvm namespace
     793             : #endif // GET_INSTRINFO_MC_DESC
     794             : 
     795             : #ifdef GET_INSTRINFO_HEADER
     796             : #undef GET_INSTRINFO_HEADER
     797             : namespace llvm {
     798             : struct LanaiGenInstrInfo : public TargetInstrInfo {
     799             :   explicit LanaiGenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);
     800          25 :   ~LanaiGenInstrInfo() override = default;
     801             : 
     802             : };
     803             : } // end llvm namespace
     804             : #endif // GET_INSTRINFO_HEADER
     805             : 
     806             : #ifdef GET_INSTRINFO_CTOR_DTOR
     807             : #undef GET_INSTRINFO_CTOR_DTOR
     808             : namespace llvm {
     809             : extern const MCInstrDesc LanaiInsts[];
     810             : extern const unsigned LanaiInstrNameIndices[];
     811             : extern const char LanaiInstrNameData[];
     812          26 : LanaiGenInstrInfo::LanaiGenInstrInfo(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode)
     813          52 :   : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
     814             :   InitMCInstrInfo(LanaiInsts, LanaiInstrNameIndices, LanaiInstrNameData, 224);
     815          26 : }
     816             : } // end llvm namespace
     817             : #endif // GET_INSTRINFO_CTOR_DTOR
     818             : 
     819             : #ifdef GET_INSTRINFO_OPERAND_ENUM
     820             : #undef GET_INSTRINFO_OPERAND_ENUM
     821             : namespace llvm {
     822             : namespace Lanai {
     823             : namespace OpName {
     824             : enum {
     825             : OPERAND_LAST
     826             : };
     827             : } // end namespace OpName
     828             : } // end namespace Lanai
     829             : } // end namespace llvm
     830             : #endif //GET_INSTRINFO_OPERAND_ENUM
     831             : 
     832             : #ifdef GET_INSTRINFO_NAMED_OPS
     833             : #undef GET_INSTRINFO_NAMED_OPS
     834             : namespace llvm {
     835             : namespace Lanai {
     836             : LLVM_READONLY
     837             : int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
     838             :   return -1;
     839             : }
     840             : } // end namespace Lanai
     841             : } // end namespace llvm
     842             : #endif //GET_INSTRINFO_NAMED_OPS
     843             : 
     844             : #ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
     845             : #undef GET_INSTRINFO_OPERAND_TYPES_ENUM
     846             : namespace llvm {
     847             : namespace Lanai {
     848             : namespace OpTypes {
     849             : enum OperandType {
     850             :   AluOp = 0,
     851             :   BrTarget = 1,
     852             :   CCOp = 2,
     853             :   CallTarget = 3,
     854             :   MEMi = 4,
     855             :   MEMri = 5,
     856             :   MEMrr = 6,
     857             :   MEMspls = 7,
     858             :   f32imm = 8,
     859             :   f64imm = 9,
     860             :   i16imm = 10,
     861             :   i1imm = 11,
     862             :   i32hi16 = 12,
     863             :   i32hi16and = 13,
     864             :   i32imm = 14,
     865             :   i32lo16and = 15,
     866             :   i32lo16s = 16,
     867             :   i32lo16z = 17,
     868             :   i32lo21 = 18,
     869             :   i32neg16 = 19,
     870             :   i64imm = 20,
     871             :   i8imm = 21,
     872             :   imm10 = 22,
     873             :   immShift = 23,
     874             :   pred = 24,
     875             :   ptype0 = 25,
     876             :   ptype1 = 26,
     877             :   ptype2 = 27,
     878             :   ptype3 = 28,
     879             :   ptype4 = 29,
     880             :   ptype5 = 30,
     881             :   type0 = 31,
     882             :   type1 = 32,
     883             :   type2 = 33,
     884             :   type3 = 34,
     885             :   type4 = 35,
     886             :   type5 = 36,
     887             :   OPERAND_TYPE_LIST_END
     888             : };
     889             : } // end namespace OpTypes
     890             : } // end namespace Lanai
     891             : } // end namespace llvm
     892             : #endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
     893             : 
     894             : #ifdef GET_INSTRMAP_INFO
     895             : #undef GET_INSTRMAP_INFO
     896             : namespace llvm {
     897             : 
     898             : namespace Lanai {
     899             : 
     900             : enum PostEncoderMethod {
     901             :         PostEncoderMethod_adjustPqBitsSpls
     902             : };
     903             : 
     904             : // splsIdempotent
     905             : LLVM_READONLY
     906         128 : int splsIdempotent(uint16_t Opcode) {
     907             : static const uint16_t splsIdempotentTable[][2] = {
     908             :   { Lanai::LDBs_RI, Lanai::LDBs_RI },
     909             :   { Lanai::LDBz_RI, Lanai::LDBz_RI },
     910             :   { Lanai::LDHs_RI, Lanai::LDHs_RI },
     911             :   { Lanai::LDHz_RI, Lanai::LDHz_RI },
     912             :   { Lanai::STB_RI, Lanai::STB_RI },
     913             :   { Lanai::STH_RI, Lanai::STH_RI },
     914             : }; // End of splsIdempotentTable
     915             : 
     916             :   unsigned mid;
     917             :   unsigned start = 0;
     918             :   unsigned end = 6;
     919         488 :   while (start < end) {
     920         368 :     mid = start + (end - start)/2;
     921         368 :     if (Opcode == splsIdempotentTable[mid][0]) {
     922             :       break;
     923             :     }
     924         360 :     if (Opcode < splsIdempotentTable[mid][0])
     925             :       end = mid;
     926             :     else
     927         128 :       start = mid + 1;
     928             :   }
     929         128 :   if (start == end)
     930             :     return -1; // Instruction doesn't exist in this table.
     931             : 
     932           8 :   return splsIdempotentTable[mid][1];
     933             : }
     934             : 
     935             : } // End Lanai namespace
     936             : } // End llvm namespace
     937             : #endif // GET_INSTRMAP_INFO
     938             : 

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