LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/Lanai - LanaiGenSubtargetInfo.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 7 9 77.8 %
Date: 2017-09-14 15:23:50 Functions: 3 6 50.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Subtarget Enumeration Source Fragment                                      *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : 
      10             : #ifdef GET_SUBTARGETINFO_ENUM
      11             : #undef GET_SUBTARGETINFO_ENUM
      12             : 
      13             : namespace llvm {
      14             : } // end namespace llvm
      15             : 
      16             : #endif // GET_SUBTARGETINFO_ENUM
      17             : 
      18             : 
      19             : #ifdef GET_SUBTARGETINFO_MC_DESC
      20             : #undef GET_SUBTARGETINFO_MC_DESC
      21             : 
      22             : namespace llvm {
      23             : 
      24             : // Sorted (by key) array of values for CPU subtype.
      25             : extern const llvm::SubtargetFeatureKV LanaiSubTypeKV[] = {
      26             :   { "generic", "Select the generic processor", { }, { } },
      27             :   { "v11", "Select the v11 processor", { }, { } }
      28             : };
      29             : 
      30             : #ifdef DBGFIELD
      31             : #error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
      32             : #endif
      33             : #ifndef NDEBUG
      34             : #define DBGFIELD(x) x,
      35             : #else
      36             : #define DBGFIELD(x)
      37             : #endif
      38             : 
      39             : // Functional units for "LanaiItinerary"
      40             : namespace LanaiItineraryFU {
      41             :   const unsigned ALU_FU = 1 << 0;
      42             :   const unsigned LDST_FU = 1 << 1;
      43             : } // end namespace LanaiItineraryFU
      44             : 
      45             : extern const llvm::InstrStage LanaiStages[] = {
      46             :   { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
      47             :   { 1, LanaiItineraryFU::ALU_FU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 1
      48             :   { 1, LanaiItineraryFU::LDST_FU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 2
      49             :   { 2, LanaiItineraryFU::LDST_FU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 3
      50             :   { 0, 0, 0, llvm::InstrStage::Required } // End stages
      51             : };
      52             : extern const unsigned LanaiOperandCycles[] = {
      53             :   0, // No itinerary
      54             :   0 // End operand cycles
      55             : };
      56             : extern const unsigned LanaiForwardingPaths[] = {
      57             :  0, // No itinerary
      58             :  0 // End bypass tables
      59             : };
      60             : 
      61             : static const llvm::InstrItinerary LanaiItinerary[] = {
      62             :   { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
      63             :   { 1, 1, 2, 0, 0 }, // 1 IIC_ALU_WriteALU
      64             :   { 1, 1, 2, 0, 0 }, // 2 IIC_ALU
      65             :   { 1, 2, 3, 0, 0 }, // 3 IIC_LD_WriteLD
      66             :   { 1, 3, 4, 0, 0 }, // 4 IIC_LDSW_WriteLDSW
      67             :   { 0, 0, 0, 0, 0 }, // 5 WriteLD
      68             :   { 1, 2, 3, 0, 0 }, // 6 IIC_ST_WriteST
      69             :   { 1, 3, 4, 0, 0 }, // 7 IIC_STSW_WriteSTSW
      70             :   { 0, ~0U, ~0U, ~0U, ~0U } // end marker
      71             : };
      72             : 
      73             : // ===============================================================
      74             : // Data tables for the new per-operand machine model.
      75             : 
      76             : // {ProcResourceIdx, Cycles}
      77             : extern const llvm::MCWriteProcResEntry LanaiWriteProcResTable[] = {
      78             :   { 0,  0}, // Invalid
      79             :   { 1,  1}, // #1
      80             :   { 2,  1} // #2
      81             : }; // LanaiWriteProcResTable
      82             : 
      83             : // {Cycles, WriteResourceID}
      84             : extern const llvm::MCWriteLatencyEntry LanaiWriteLatencyTable[] = {
      85             :   { 0,  0}, // Invalid
      86             :   { 1,  0}, // #1 WriteALU
      87             :   { 2,  0}, // #2 WriteLD_WriteLDSW_WriteST
      88             :   { 4,  0} // #3 WriteSTSW
      89             : }; // LanaiWriteLatencyTable
      90             : 
      91             : // {UseIdx, WriteResourceID, Cycles}
      92             : extern const llvm::MCReadAdvanceEntry LanaiReadAdvanceTable[] = {
      93             :   {0,  0,  0}, // Invalid
      94             : }; // LanaiReadAdvanceTable
      95             : 
      96             : // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
      97             : static const llvm::MCSchedClassDesc LanaiSchedModelSchedClasses[] = {
      98             :   {DBGFIELD("InvalidSchedClass")  65535, false, false,  0, 0,  0, 0,  0, 0},
      99             :   {DBGFIELD("IIC_ALU_WriteALU")   1, false, false,  1, 1,  1, 1,  0, 0}, // #1
     100             :   {DBGFIELD("IIC_ALU")            0, false, false,  0, 0,  0, 0,  0, 0}, // #2
     101             :   {DBGFIELD("IIC_LD_WriteLD")     1, false, false,  2, 1,  2, 1,  0, 0}, // #3
     102             :   {DBGFIELD("IIC_LDSW_WriteLDSW") 1, false, false,  2, 1,  2, 1,  0, 0}, // #4
     103             :   {DBGFIELD("WriteLD")            1, false, false,  2, 1,  2, 1,  0, 0}, // #5
     104             :   {DBGFIELD("IIC_ST_WriteST")     1, false, false,  2, 1,  2, 1,  0, 0}, // #6
     105             :   {DBGFIELD("IIC_STSW_WriteSTSW") 1, false, false,  2, 1,  3, 1,  0, 0} // #7
     106             : }; // LanaiSchedModelSchedClasses
     107             : 
     108             : static const llvm::MCSchedModel NoSchedModel = {
     109             :   MCSchedModel::DefaultIssueWidth,
     110             :   MCSchedModel::DefaultMicroOpBufferSize,
     111             :   MCSchedModel::DefaultLoopMicroOpBufferSize,
     112             :   MCSchedModel::DefaultLoadLatency,
     113             :   MCSchedModel::DefaultHighLatency,
     114             :   MCSchedModel::DefaultMispredictPenalty,
     115             :   false, // PostRAScheduler
     116             :   false, // CompleteModel
     117             :   0, // Processor ID
     118             :   nullptr, nullptr, 0, 0, // No instruction-level machine model.
     119             :   nullptr}; // No Itinerary
     120             : 
     121             : // {Name, NumUnits, SuperIdx, IsBuffered}
     122             : static const llvm::MCProcResourceDesc LanaiSchedModelProcResources[] = {
     123             :   {DBGFIELD("InvalidUnit")     0, 0, 0},
     124             :   {DBGFIELD("ALU")             1, 0, 0}, // #1
     125             :   {DBGFIELD("LdSt")            1, 0, 0}  // #2
     126             : };
     127             : 
     128             : static const llvm::MCSchedModel LanaiSchedModel = {
     129             :   1, // IssueWidth
     130             :   0, // MicroOpBufferSize
     131             :   0, // LoopMicroOpBufferSize
     132             :   2, // LoadLatency
     133             :   MCSchedModel::DefaultHighLatency,
     134             :   10, // MispredictPenalty
     135             :   false, // PostRAScheduler
     136             :   false, // CompleteModel
     137             :   1, // Processor ID
     138             :   LanaiSchedModelProcResources,
     139             :   LanaiSchedModelSchedClasses,
     140             :   3,
     141             :   8,
     142             :   LanaiItinerary};
     143             : 
     144             : // Sorted (by key) array of itineraries for CPU subtype.
     145             : extern const llvm::SubtargetInfoKV LanaiProcSchedKV[] = {
     146             :   { "generic", (const void *)&LanaiSchedModel },
     147             :   { "v11", (const void *)&LanaiSchedModel }
     148             : };
     149             : #undef DBGFIELD
     150          31 : static inline MCSubtargetInfo *createLanaiMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef FS) {
     151             :   return new MCSubtargetInfo(TT, CPU, FS, None, LanaiSubTypeKV, 
     152             :                       LanaiProcSchedKV, LanaiWriteProcResTable, LanaiWriteLatencyTable, LanaiReadAdvanceTable, 
     153          93 :                       LanaiStages, LanaiOperandCycles, LanaiForwardingPaths);
     154             : }
     155             : 
     156             : } // end namespace llvm
     157             : 
     158             : #endif // GET_SUBTARGETINFO_MC_DESC
     159             : 
     160             : 
     161             : #ifdef GET_SUBTARGETINFO_TARGET_DESC
     162             : #undef GET_SUBTARGETINFO_TARGET_DESC
     163             : 
     164             : #include "llvm/Support/Debug.h"
     165             : #include "llvm/Support/raw_ostream.h"
     166             : 
     167             : // ParseSubtargetFeatures - Parses features string setting specified
     168             : // subtarget options.
     169          26 : void llvm::LanaiSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {
     170             :   DEBUG(dbgs() << "\nFeatures:" << FS);
     171             :   DEBUG(dbgs() << "\nCPU:" << CPU << "\n\n");
     172          26 : }
     173             : #endif // GET_SUBTARGETINFO_TARGET_DESC
     174             : 
     175             : 
     176             : #ifdef GET_SUBTARGETINFO_HEADER
     177             : #undef GET_SUBTARGETINFO_HEADER
     178             : 
     179             : namespace llvm {
     180             : class DFAPacketizer;
     181          25 : struct LanaiGenSubtargetInfo : public TargetSubtargetInfo {
     182             :   explicit LanaiGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS);
     183             : public:
     184             :   unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
     185             :   DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
     186             : };
     187             : } // end namespace llvm
     188             : 
     189             : #endif // GET_SUBTARGETINFO_HEADER
     190             : 
     191             : 
     192             : #ifdef GET_SUBTARGETINFO_CTOR
     193             : #undef GET_SUBTARGETINFO_CTOR
     194             : 
     195             : #include "llvm/CodeGen/TargetSchedule.h"
     196             : 
     197             : namespace llvm {
     198             : extern const llvm::SubtargetFeatureKV LanaiFeatureKV[];
     199             : extern const llvm::SubtargetFeatureKV LanaiSubTypeKV[];
     200             : extern const llvm::SubtargetInfoKV LanaiProcSchedKV[];
     201             : extern const llvm::MCWriteProcResEntry LanaiWriteProcResTable[];
     202             : extern const llvm::MCWriteLatencyEntry LanaiWriteLatencyTable[];
     203             : extern const llvm::MCReadAdvanceEntry LanaiReadAdvanceTable[];
     204             : extern const llvm::InstrStage LanaiStages[];
     205             : extern const unsigned LanaiOperandCycles[];
     206             : extern const unsigned LanaiForwardingPaths[];
     207          26 : LanaiGenSubtargetInfo::LanaiGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
     208             :   : TargetSubtargetInfo(TT, CPU, FS, None, makeArrayRef(LanaiSubTypeKV, 2), 
     209             :                         LanaiProcSchedKV, LanaiWriteProcResTable, LanaiWriteLatencyTable, LanaiReadAdvanceTable, 
     210          78 :                         LanaiStages, LanaiOperandCycles, LanaiForwardingPaths) {}
     211             : 
     212           0 : unsigned LanaiGenSubtargetInfo
     213             : ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
     214           0 :   report_fatal_error("Expected a variant SchedClass");
     215             : } // LanaiGenSubtargetInfo::resolveSchedClass
     216             : } // end namespace llvm
     217             : 
     218             : #endif // GET_SUBTARGETINFO_CTOR
     219             : 

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