LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/MSP430 - MSP430GenInstrInfo.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 4 4 100.0 %
Date: 2018-06-17 00:07:59 Functions: 1 3 33.3 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Target Instruction Enum Values and Descriptors                             *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : #ifdef GET_INSTRINFO_ENUM
      10             : #undef GET_INSTRINFO_ENUM
      11             : namespace llvm {
      12             : 
      13             : namespace MSP430 {
      14             :   enum {
      15             :     PHI = 0,
      16             :     INLINEASM   = 1,
      17             :     CFI_INSTRUCTION     = 2,
      18             :     EH_LABEL    = 3,
      19             :     GC_LABEL    = 4,
      20             :     ANNOTATION_LABEL    = 5,
      21             :     KILL        = 6,
      22             :     EXTRACT_SUBREG      = 7,
      23             :     INSERT_SUBREG       = 8,
      24             :     IMPLICIT_DEF        = 9,
      25             :     SUBREG_TO_REG       = 10,
      26             :     COPY_TO_REGCLASS    = 11,
      27             :     DBG_VALUE   = 12,
      28             :     DBG_LABEL   = 13,
      29             :     REG_SEQUENCE        = 14,
      30             :     COPY        = 15,
      31             :     BUNDLE      = 16,
      32             :     LIFETIME_START      = 17,
      33             :     LIFETIME_END        = 18,
      34             :     STACKMAP    = 19,
      35             :     FENTRY_CALL = 20,
      36             :     PATCHPOINT  = 21,
      37             :     LOAD_STACK_GUARD    = 22,
      38             :     STATEPOINT  = 23,
      39             :     LOCAL_ESCAPE        = 24,
      40             :     FAULTING_OP = 25,
      41             :     PATCHABLE_OP        = 26,
      42             :     PATCHABLE_FUNCTION_ENTER    = 27,
      43             :     PATCHABLE_RET       = 28,
      44             :     PATCHABLE_FUNCTION_EXIT     = 29,
      45             :     PATCHABLE_TAIL_CALL = 30,
      46             :     PATCHABLE_EVENT_CALL        = 31,
      47             :     PATCHABLE_TYPED_EVENT_CALL  = 32,
      48             :     ICALL_BRANCH_FUNNEL = 33,
      49             :     G_ADD       = 34,
      50             :     G_SUB       = 35,
      51             :     G_MUL       = 36,
      52             :     G_SDIV      = 37,
      53             :     G_UDIV      = 38,
      54             :     G_SREM      = 39,
      55             :     G_UREM      = 40,
      56             :     G_AND       = 41,
      57             :     G_OR        = 42,
      58             :     G_XOR       = 43,
      59             :     G_IMPLICIT_DEF      = 44,
      60             :     G_PHI       = 45,
      61             :     G_FRAME_INDEX       = 46,
      62             :     G_GLOBAL_VALUE      = 47,
      63             :     G_EXTRACT   = 48,
      64             :     G_UNMERGE_VALUES    = 49,
      65             :     G_INSERT    = 50,
      66             :     G_MERGE_VALUES      = 51,
      67             :     G_PTRTOINT  = 52,
      68             :     G_INTTOPTR  = 53,
      69             :     G_BITCAST   = 54,
      70             :     G_LOAD      = 55,
      71             :     G_SEXTLOAD  = 56,
      72             :     G_ZEXTLOAD  = 57,
      73             :     G_STORE     = 58,
      74             :     G_ATOMIC_CMPXCHG_WITH_SUCCESS       = 59,
      75             :     G_ATOMIC_CMPXCHG    = 60,
      76             :     G_ATOMICRMW_XCHG    = 61,
      77             :     G_ATOMICRMW_ADD     = 62,
      78             :     G_ATOMICRMW_SUB     = 63,
      79             :     G_ATOMICRMW_AND     = 64,
      80             :     G_ATOMICRMW_NAND    = 65,
      81             :     G_ATOMICRMW_OR      = 66,
      82             :     G_ATOMICRMW_XOR     = 67,
      83             :     G_ATOMICRMW_MAX     = 68,
      84             :     G_ATOMICRMW_MIN     = 69,
      85             :     G_ATOMICRMW_UMAX    = 70,
      86             :     G_ATOMICRMW_UMIN    = 71,
      87             :     G_BRCOND    = 72,
      88             :     G_BRINDIRECT        = 73,
      89             :     G_INTRINSIC = 74,
      90             :     G_INTRINSIC_W_SIDE_EFFECTS  = 75,
      91             :     G_ANYEXT    = 76,
      92             :     G_TRUNC     = 77,
      93             :     G_CONSTANT  = 78,
      94             :     G_FCONSTANT = 79,
      95             :     G_VASTART   = 80,
      96             :     G_VAARG     = 81,
      97             :     G_SEXT      = 82,
      98             :     G_ZEXT      = 83,
      99             :     G_SHL       = 84,
     100             :     G_LSHR      = 85,
     101             :     G_ASHR      = 86,
     102             :     G_ICMP      = 87,
     103             :     G_FCMP      = 88,
     104             :     G_SELECT    = 89,
     105             :     G_UADDE     = 90,
     106             :     G_USUBE     = 91,
     107             :     G_SADDO     = 92,
     108             :     G_SSUBO     = 93,
     109             :     G_UMULO     = 94,
     110             :     G_SMULO     = 95,
     111             :     G_UMULH     = 96,
     112             :     G_SMULH     = 97,
     113             :     G_FADD      = 98,
     114             :     G_FSUB      = 99,
     115             :     G_FMUL      = 100,
     116             :     G_FMA       = 101,
     117             :     G_FDIV      = 102,
     118             :     G_FREM      = 103,
     119             :     G_FPOW      = 104,
     120             :     G_FEXP      = 105,
     121             :     G_FEXP2     = 106,
     122             :     G_FLOG      = 107,
     123             :     G_FLOG2     = 108,
     124             :     G_FNEG      = 109,
     125             :     G_FPEXT     = 110,
     126             :     G_FPTRUNC   = 111,
     127             :     G_FPTOSI    = 112,
     128             :     G_FPTOUI    = 113,
     129             :     G_SITOFP    = 114,
     130             :     G_UITOFP    = 115,
     131             :     G_FABS      = 116,
     132             :     G_GEP       = 117,
     133             :     G_PTR_MASK  = 118,
     134             :     G_BR        = 119,
     135             :     G_INSERT_VECTOR_ELT = 120,
     136             :     G_EXTRACT_VECTOR_ELT        = 121,
     137             :     G_SHUFFLE_VECTOR    = 122,
     138             :     G_BSWAP     = 123,
     139             :     ADC16mi     = 124,
     140             :     ADC16mm     = 125,
     141             :     ADC16mr     = 126,
     142             :     ADC16ri     = 127,
     143             :     ADC16rm     = 128,
     144             :     ADC16rr     = 129,
     145             :     ADC8mi      = 130,
     146             :     ADC8mm      = 131,
     147             :     ADC8mr      = 132,
     148             :     ADC8ri      = 133,
     149             :     ADC8rm      = 134,
     150             :     ADC8rr      = 135,
     151             :     ADD16mi     = 136,
     152             :     ADD16mm     = 137,
     153             :     ADD16mr     = 138,
     154             :     ADD16ri     = 139,
     155             :     ADD16rm     = 140,
     156             :     ADD16rm_POST        = 141,
     157             :     ADD16rr     = 142,
     158             :     ADD8mi      = 143,
     159             :     ADD8mm      = 144,
     160             :     ADD8mr      = 145,
     161             :     ADD8ri      = 146,
     162             :     ADD8rm      = 147,
     163             :     ADD8rm_POST = 148,
     164             :     ADD8rr      = 149,
     165             :     ADDframe    = 150,
     166             :     ADJCALLSTACKDOWN    = 151,
     167             :     ADJCALLSTACKUP      = 152,
     168             :     AND16mi     = 153,
     169             :     AND16mm     = 154,
     170             :     AND16mr     = 155,
     171             :     AND16ri     = 156,
     172             :     AND16rm     = 157,
     173             :     AND16rm_POST        = 158,
     174             :     AND16rr     = 159,
     175             :     AND8mi      = 160,
     176             :     AND8mm      = 161,
     177             :     AND8mr      = 162,
     178             :     AND8ri      = 163,
     179             :     AND8rm      = 164,
     180             :     AND8rm_POST = 165,
     181             :     AND8rr      = 166,
     182             :     BIC16mm     = 167,
     183             :     BIC16mr     = 168,
     184             :     BIC16rm     = 169,
     185             :     BIC16rr     = 170,
     186             :     BIC8mm      = 171,
     187             :     BIC8mr      = 172,
     188             :     BIC8rm      = 173,
     189             :     BIC8rr      = 174,
     190             :     BIT16mi     = 175,
     191             :     BIT16mm     = 176,
     192             :     BIT16mr     = 177,
     193             :     BIT16ri     = 178,
     194             :     BIT16rm     = 179,
     195             :     BIT16rr     = 180,
     196             :     BIT8mi      = 181,
     197             :     BIT8mm      = 182,
     198             :     BIT8mr      = 183,
     199             :     BIT8ri      = 184,
     200             :     BIT8rm      = 185,
     201             :     BIT8rr      = 186,
     202             :     Bi  = 187,
     203             :     Bm  = 188,
     204             :     Br  = 189,
     205             :     CALLi       = 190,
     206             :     CALLm       = 191,
     207             :     CALLr       = 192,
     208             :     CMP16mi     = 193,
     209             :     CMP16mr     = 194,
     210             :     CMP16ri     = 195,
     211             :     CMP16rm     = 196,
     212             :     CMP16rr     = 197,
     213             :     CMP8mi      = 198,
     214             :     CMP8mr      = 199,
     215             :     CMP8ri      = 200,
     216             :     CMP8rm      = 201,
     217             :     CMP8rr      = 202,
     218             :     JCC = 203,
     219             :     JMP = 204,
     220             :     MOV16mi     = 205,
     221             :     MOV16mm     = 206,
     222             :     MOV16mr     = 207,
     223             :     MOV16ri     = 208,
     224             :     MOV16rm     = 209,
     225             :     MOV16rm_POST        = 210,
     226             :     MOV16rr     = 211,
     227             :     MOV8mi      = 212,
     228             :     MOV8mm      = 213,
     229             :     MOV8mr      = 214,
     230             :     MOV8ri      = 215,
     231             :     MOV8rm      = 216,
     232             :     MOV8rm_POST = 217,
     233             :     MOV8rr      = 218,
     234             :     MOVZX16rm8  = 219,
     235             :     MOVZX16rr8  = 220,
     236             :     NOP = 221,
     237             :     OR16mi      = 222,
     238             :     OR16mm      = 223,
     239             :     OR16mr      = 224,
     240             :     OR16ri      = 225,
     241             :     OR16rm      = 226,
     242             :     OR16rm_POST = 227,
     243             :     OR16rr      = 228,
     244             :     OR8mi       = 229,
     245             :     OR8mm       = 230,
     246             :     OR8mr       = 231,
     247             :     OR8ri       = 232,
     248             :     OR8rm       = 233,
     249             :     OR8rm_POST  = 234,
     250             :     OR8rr       = 235,
     251             :     POP16r      = 236,
     252             :     PUSH16r     = 237,
     253             :     RET = 238,
     254             :     RETI        = 239,
     255             :     SAR16r1     = 240,
     256             :     SAR16r1c    = 241,
     257             :     SAR8r1      = 242,
     258             :     SAR8r1c     = 243,
     259             :     SBC16mi     = 244,
     260             :     SBC16mm     = 245,
     261             :     SBC16mr     = 246,
     262             :     SBC16ri     = 247,
     263             :     SBC16rm     = 248,
     264             :     SBC16rr     = 249,
     265             :     SBC8mi      = 250,
     266             :     SBC8mm      = 251,
     267             :     SBC8mr      = 252,
     268             :     SBC8ri      = 253,
     269             :     SBC8rm      = 254,
     270             :     SBC8rr      = 255,
     271             :     SEXT16r     = 256,
     272             :     SHL16r1     = 257,
     273             :     SHL8r1      = 258,
     274             :     SUB16mi     = 259,
     275             :     SUB16mm     = 260,
     276             :     SUB16mr     = 261,
     277             :     SUB16ri     = 262,
     278             :     SUB16rm     = 263,
     279             :     SUB16rm_POST        = 264,
     280             :     SUB16rr     = 265,
     281             :     SUB8mi      = 266,
     282             :     SUB8mm      = 267,
     283             :     SUB8mr      = 268,
     284             :     SUB8ri      = 269,
     285             :     SUB8rm      = 270,
     286             :     SUB8rm_POST = 271,
     287             :     SUB8rr      = 272,
     288             :     SWPB16r     = 273,
     289             :     Select16    = 274,
     290             :     Select8     = 275,
     291             :     Shl16       = 276,
     292             :     Shl8        = 277,
     293             :     Sra16       = 278,
     294             :     Sra8        = 279,
     295             :     Srl16       = 280,
     296             :     Srl8        = 281,
     297             :     XOR16mi     = 282,
     298             :     XOR16mm     = 283,
     299             :     XOR16mr     = 284,
     300             :     XOR16ri     = 285,
     301             :     XOR16rm     = 286,
     302             :     XOR16rm_POST        = 287,
     303             :     XOR16rr     = 288,
     304             :     XOR8mi      = 289,
     305             :     XOR8mm      = 290,
     306             :     XOR8mr      = 291,
     307             :     XOR8ri      = 292,
     308             :     XOR8rm      = 293,
     309             :     XOR8rm_POST = 294,
     310             :     XOR8rr      = 295,
     311             :     ZEXT16r     = 296,
     312             :     INSTRUCTION_LIST_END = 297
     313             :   };
     314             : 
     315             : } // end MSP430 namespace
     316             : } // end llvm namespace
     317             : #endif // GET_INSTRINFO_ENUM
     318             : 
     319             : #ifdef GET_INSTRINFO_SCHED_ENUM
     320             : #undef GET_INSTRINFO_SCHED_ENUM
     321             : namespace llvm {
     322             : 
     323             : namespace MSP430 {
     324             : namespace Sched {
     325             :   enum {
     326             :     NoInstrModel        = 0,
     327             :     SCHED_LIST_END = 1
     328             :   };
     329             : } // end Sched namespace
     330             : } // end MSP430 namespace
     331             : } // end llvm namespace
     332             : #endif // GET_INSTRINFO_SCHED_ENUM
     333             : 
     334             : #ifdef GET_INSTRINFO_MC_DESC
     335             : #undef GET_INSTRINFO_MC_DESC
     336             : namespace llvm {
     337             : 
     338             : static const MCPhysReg ImplicitList1[] = { MSP430::SR, 0 };
     339             : static const MCPhysReg ImplicitList2[] = { MSP430::SP, 0 };
     340             : static const MCPhysReg ImplicitList3[] = { MSP430::SP, MSP430::SR, 0 };
     341             : static const MCPhysReg ImplicitList4[] = { MSP430::R11, MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, MSP430::SR, 0 };
     342             : 
     343             : static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     344             : static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     345             : static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     346             : static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     347             : static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     348             : static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     349             : static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     350             : static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     351             : static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
     352             : static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     353             : static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     354             : static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     355             : static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     356             : static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     357             : static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     358             : static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
     359             : static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     360             : static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     361             : static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     362             : static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     363             : static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
     364             : static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
     365             : static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     366             : static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     367             : static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
     368             : static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     369             : static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
     370             : static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
     371             : static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
     372             : static const MCOperandInfo OperandInfo31[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     373             : static const MCOperandInfo OperandInfo32[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     374             : static const MCOperandInfo OperandInfo33[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     375             : static const MCOperandInfo OperandInfo34[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     376             : static const MCOperandInfo OperandInfo35[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     377             : static const MCOperandInfo OperandInfo36[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     378             : static const MCOperandInfo OperandInfo37[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     379             : static const MCOperandInfo OperandInfo38[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     380             : static const MCOperandInfo OperandInfo39[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     381             : static const MCOperandInfo OperandInfo40[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     382             : static const MCOperandInfo OperandInfo41[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
     383             : static const MCOperandInfo OperandInfo42[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
     384             : static const MCOperandInfo OperandInfo43[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     385             : static const MCOperandInfo OperandInfo44[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     386             : static const MCOperandInfo OperandInfo45[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     387             : static const MCOperandInfo OperandInfo46[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     388             : static const MCOperandInfo OperandInfo47[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     389             : static const MCOperandInfo OperandInfo48[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     390             : static const MCOperandInfo OperandInfo49[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     391             : static const MCOperandInfo OperandInfo50[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     392             : static const MCOperandInfo OperandInfo51[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     393             : static const MCOperandInfo OperandInfo52[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
     394             : static const MCOperandInfo OperandInfo53[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
     395             : static const MCOperandInfo OperandInfo54[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     396             : static const MCOperandInfo OperandInfo55[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
     397             : static const MCOperandInfo OperandInfo56[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
     398             : static const MCOperandInfo OperandInfo57[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     399             : static const MCOperandInfo OperandInfo58[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     400             : static const MCOperandInfo OperandInfo59[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     401             : static const MCOperandInfo OperandInfo60[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     402             : 
     403             : extern const MCInstrDesc MSP430Insts[] = {
     404             :   { 0,  1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #0 = PHI
     405             :   { 1,  0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
     406             :   { 2,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #2 = CFI_INSTRUCTION
     407             :   { 3,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #3 = EH_LABEL
     408             :   { 4,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #4 = GC_LABEL
     409             :   { 5,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #5 = ANNOTATION_LABEL
     410             :   { 6,  0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #6 = KILL
     411             :   { 7,  3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #7 = EXTRACT_SUBREG
     412             :   { 8,  4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #8 = INSERT_SUBREG
     413             :   { 9,  1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #9 = IMPLICIT_DEF
     414             :   { 10, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #10 = SUBREG_TO_REG
     415             :   { 11, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #11 = COPY_TO_REGCLASS
     416             :   { 12, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #12 = DBG_VALUE
     417             :   { 13, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #13 = DBG_LABEL
     418             :   { 14, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #14 = REG_SEQUENCE
     419             :   { 15, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #15 = COPY
     420             :   { 16, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #16 = BUNDLE
     421             :   { 17, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #17 = LIFETIME_START
     422             :   { 18, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #18 = LIFETIME_END
     423             :   { 19, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #19 = STACKMAP
     424             :   { 20, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #20 = FENTRY_CALL
     425             :   { 21, 6,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #21 = PATCHPOINT
     426             :   { 22, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #22 = LOAD_STACK_GUARD
     427             :   { 23, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #23 = STATEPOINT
     428             :   { 24, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #24 = LOCAL_ESCAPE
     429             :   { 25, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #25 = FAULTING_OP
     430             :   { 26, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #26 = PATCHABLE_OP
     431             :   { 27, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #27 = PATCHABLE_FUNCTION_ENTER
     432             :   { 28, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #28 = PATCHABLE_RET
     433             :   { 29, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #29 = PATCHABLE_FUNCTION_EXIT
     434             :   { 30, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #30 = PATCHABLE_TAIL_CALL
     435             :   { 31, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #31 = PATCHABLE_EVENT_CALL
     436             :   { 32, 3,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #32 = PATCHABLE_TYPED_EVENT_CALL
     437             :   { 33, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #33 = ICALL_BRANCH_FUNNEL
     438             :   { 34, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #34 = G_ADD
     439             :   { 35, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #35 = G_SUB
     440             :   { 36, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #36 = G_MUL
     441             :   { 37, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #37 = G_SDIV
     442             :   { 38, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #38 = G_UDIV
     443             :   { 39, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #39 = G_SREM
     444             :   { 40, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #40 = G_UREM
     445             :   { 41, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #41 = G_AND
     446             :   { 42, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #42 = G_OR
     447             :   { 43, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #43 = G_XOR
     448             :   { 44, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #44 = G_IMPLICIT_DEF
     449             :   { 45, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #45 = G_PHI
     450             :   { 46, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #46 = G_FRAME_INDEX
     451             :   { 47, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #47 = G_GLOBAL_VALUE
     452             :   { 48, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #48 = G_EXTRACT
     453             :   { 49, 2,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #49 = G_UNMERGE_VALUES
     454             :   { 50, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #50 = G_INSERT
     455             :   { 51, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #51 = G_MERGE_VALUES
     456             :   { 52, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #52 = G_PTRTOINT
     457             :   { 53, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #53 = G_INTTOPTR
     458             :   { 54, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #54 = G_BITCAST
     459             :   { 55, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #55 = G_LOAD
     460             :   { 56, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #56 = G_SEXTLOAD
     461             :   { 57, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #57 = G_ZEXTLOAD
     462             :   { 58, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #58 = G_STORE
     463             :   { 59, 5,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #59 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
     464             :   { 60, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #60 = G_ATOMIC_CMPXCHG
     465             :   { 61, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #61 = G_ATOMICRMW_XCHG
     466             :   { 62, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #62 = G_ATOMICRMW_ADD
     467             :   { 63, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #63 = G_ATOMICRMW_SUB
     468             :   { 64, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #64 = G_ATOMICRMW_AND
     469             :   { 65, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #65 = G_ATOMICRMW_NAND
     470             :   { 66, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #66 = G_ATOMICRMW_OR
     471             :   { 67, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #67 = G_ATOMICRMW_XOR
     472             :   { 68, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #68 = G_ATOMICRMW_MAX
     473             :   { 69, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #69 = G_ATOMICRMW_MIN
     474             :   { 70, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #70 = G_ATOMICRMW_UMAX
     475             :   { 71, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #71 = G_ATOMICRMW_UMIN
     476             :   { 72, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #72 = G_BRCOND
     477             :   { 73, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #73 = G_BRINDIRECT
     478             :   { 74, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #74 = G_INTRINSIC
     479             :   { 75, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #75 = G_INTRINSIC_W_SIDE_EFFECTS
     480             :   { 76, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #76 = G_ANYEXT
     481             :   { 77, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #77 = G_TRUNC
     482             :   { 78, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #78 = G_CONSTANT
     483             :   { 79, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #79 = G_FCONSTANT
     484             :   { 80, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #80 = G_VASTART
     485             :   { 81, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #81 = G_VAARG
     486             :   { 82, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #82 = G_SEXT
     487             :   { 83, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #83 = G_ZEXT
     488             :   { 84, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #84 = G_SHL
     489             :   { 85, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #85 = G_LSHR
     490             :   { 86, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #86 = G_ASHR
     491             :   { 87, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #87 = G_ICMP
     492             :   { 88, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #88 = G_FCMP
     493             :   { 89, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #89 = G_SELECT
     494             :   { 90, 5,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #90 = G_UADDE
     495             :   { 91, 5,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #91 = G_USUBE
     496             :   { 92, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #92 = G_SADDO
     497             :   { 93, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #93 = G_SSUBO
     498             :   { 94, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #94 = G_UMULO
     499             :   { 95, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #95 = G_SMULO
     500             :   { 96, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #96 = G_UMULH
     501             :   { 97, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #97 = G_SMULH
     502             :   { 98, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #98 = G_FADD
     503             :   { 99, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #99 = G_FSUB
     504             :   { 100,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #100 = G_FMUL
     505             :   { 101,        4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #101 = G_FMA
     506             :   { 102,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #102 = G_FDIV
     507             :   { 103,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #103 = G_FREM
     508             :   { 104,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #104 = G_FPOW
     509             :   { 105,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #105 = G_FEXP
     510             :   { 106,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #106 = G_FEXP2
     511             :   { 107,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #107 = G_FLOG
     512             :   { 108,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #108 = G_FLOG2
     513             :   { 109,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #109 = G_FNEG
     514             :   { 110,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #110 = G_FPEXT
     515             :   { 111,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #111 = G_FPTRUNC
     516             :   { 112,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #112 = G_FPTOSI
     517             :   { 113,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #113 = G_FPTOUI
     518             :   { 114,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #114 = G_SITOFP
     519             :   { 115,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #115 = G_UITOFP
     520             :   { 116,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #116 = G_FABS
     521             :   { 117,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #117 = G_GEP
     522             :   { 118,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #118 = G_PTR_MASK
     523             :   { 119,        1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #119 = G_BR
     524             :   { 120,        4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #120 = G_INSERT_VECTOR_ELT
     525             :   { 121,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #121 = G_EXTRACT_VECTOR_ELT
     526             :   { 122,        4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #122 = G_SHUFFLE_VECTOR
     527             :   { 123,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #123 = G_BSWAP
     528             :   { 124,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #124 = ADC16mi
     529             :   { 125,        4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, ImplicitList1, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #125 = ADC16mm
     530             :   { 126,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #126 = ADC16mr
     531             :   { 127,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #127 = ADC16ri
     532             :   { 128,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #128 = ADC16rm
     533             :   { 129,        3,      1,      0,      0,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #129 = ADC16rr
     534             :   { 130,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #130 = ADC8mi
     535             :   { 131,        4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, ImplicitList1, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #131 = ADC8mm
     536             :   { 132,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #132 = ADC8mr
     537             :   { 133,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #133 = ADC8ri
     538             :   { 134,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #134 = ADC8rm
     539             :   { 135,        3,      1,      0,      0,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #135 = ADC8rr
     540             :   { 136,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #136 = ADD16mi
     541             :   { 137,        4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #137 = ADD16mm
     542             :   { 138,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #138 = ADD16mr
     543             :   { 139,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #139 = ADD16ri
     544             :   { 140,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #140 = ADD16rm
     545             :   { 141,        4,      2,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #141 = ADD16rm_POST
     546             :   { 142,        3,      1,      0,      0,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #142 = ADD16rr
     547             :   { 143,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #143 = ADD8mi
     548             :   { 144,        4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #144 = ADD8mm
     549             :   { 145,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #145 = ADD8mr
     550             :   { 146,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #146 = ADD8ri
     551             :   { 147,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #147 = ADD8rm
     552             :   { 148,        4,      2,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #148 = ADD8rm_POST
     553             :   { 149,        3,      1,      0,      0,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #149 = ADD8rr
     554             :   { 150,        3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, ImplicitList2, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #150 = ADDframe
     555             :   { 151,        2,      0,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, ImplicitList2, ImplicitList3, OperandInfo8, -1 ,nullptr },  // Inst #151 = ADJCALLSTACKDOWN
     556             :   { 152,        2,      0,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, ImplicitList2, ImplicitList3, OperandInfo8, -1 ,nullptr },  // Inst #152 = ADJCALLSTACKUP
     557             :   { 153,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #153 = AND16mi
     558             :   { 154,        4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #154 = AND16mm
     559             :   { 155,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #155 = AND16mr
     560             :   { 156,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #156 = AND16ri
     561             :   { 157,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #157 = AND16rm
     562             :   { 158,        4,      2,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #158 = AND16rm_POST
     563             :   { 159,        3,      1,      0,      0,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #159 = AND16rr
     564             :   { 160,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #160 = AND8mi
     565             :   { 161,        4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #161 = AND8mm
     566             :   { 162,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #162 = AND8mr
     567             :   { 163,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #163 = AND8ri
     568             :   { 164,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #164 = AND8rm
     569             :   { 165,        4,      2,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #165 = AND8rm_POST
     570             :   { 166,        3,      1,      0,      0,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #166 = AND8rr
     571             :   { 167,        4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #167 = BIC16mm
     572             :   { 168,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #168 = BIC16mr
     573             :   { 169,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #169 = BIC16rm
     574             :   { 170,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #170 = BIC16rr
     575             :   { 171,        4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #171 = BIC8mm
     576             :   { 172,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #172 = BIC8mr
     577             :   { 173,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #173 = BIC8rm
     578             :   { 174,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #174 = BIC8rr
     579             :   { 175,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #175 = BIT16mi
     580             :   { 176,        4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #176 = BIT16mm
     581             :   { 177,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #177 = BIT16mr
     582             :   { 178,        2,      0,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #178 = BIT16ri
     583             :   { 179,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #179 = BIT16rm
     584             :   { 180,        2,      0,      0,      0,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #180 = BIT16rr
     585             :   { 181,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #181 = BIT8mi
     586             :   { 182,        4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #182 = BIT8mm
     587             :   { 183,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #183 = BIT8mr
     588             :   { 184,        2,      0,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #184 = BIT8ri
     589             :   { 185,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #185 = BIT8rm
     590             :   { 186,        2,      0,      0,      0,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo49, -1 ,nullptr },  // Inst #186 = BIT8rr
     591             :   { 187,        1,      0,      0,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #187 = Bi
     592             :   { 188,        2,      0,      0,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #188 = Bm
     593             :   { 189,        1,      0,      0,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #189 = Br
     594             :   { 190,        1,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xdULL, ImplicitList2, ImplicitList4, OperandInfo3, -1 ,nullptr },  // Inst #190 = CALLi
     595             :   { 191,        2,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xdULL, ImplicitList2, ImplicitList4, OperandInfo50, -1 ,nullptr },  // Inst #191 = CALLm
     596             :   { 192,        1,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x9ULL, ImplicitList2, ImplicitList4, OperandInfo51, -1 ,nullptr },  // Inst #192 = CALLr
     597             :   { 193,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #193 = CMP16mi
     598             :   { 194,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #194 = CMP16mr
     599             :   { 195,        2,      0,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #195 = CMP16ri
     600             :   { 196,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #196 = CMP16rm
     601             :   { 197,        2,      0,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #197 = CMP16rr
     602             :   { 198,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #198 = CMP8mi
     603             :   { 199,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #199 = CMP8mr
     604             :   { 200,        2,      0,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #200 = CMP8ri
     605             :   { 201,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #201 = CMP8rm
     606             :   { 202,        2,      0,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo49, -1 ,nullptr },  // Inst #202 = CMP8rr
     607             :   { 203,        2,      0,      0,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xbULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #203 = JCC
     608             :   { 204,        1,      0,      0,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xbULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #204 = JMP
     609             :   { 205,        3,      0,      0,      0,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #205 = MOV16mi
     610             :   { 206,        4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #206 = MOV16mm
     611             :   { 207,        3,      0,      0,      0,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #207 = MOV16mr
     612             :   { 208,        2,      1,      0,      0,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #208 = MOV16ri
     613             :   { 209,        3,      1,      0,      0,      0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #209 = MOV16rm
     614             :   { 210,        3,      2,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #210 = MOV16rm_POST
     615             :   { 211,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #211 = MOV16rr
     616             :   { 212,        3,      0,      0,      0,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #212 = MOV8mi
     617             :   { 213,        4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #213 = MOV8mm
     618             :   { 214,        3,      0,      0,      0,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #214 = MOV8mr
     619             :   { 215,        2,      1,      0,      0,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #215 = MOV8ri
     620             :   { 216,        3,      1,      0,      0,      0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #216 = MOV8rm
     621             :   { 217,        3,      2,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #217 = MOV8rm_POST
     622             :   { 218,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #218 = MOV8rr
     623             :   { 219,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #219 = MOVZX16rm8
     624             :   { 220,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #220 = MOVZX16rr8
     625             :   { 221,        0,      0,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #221 = NOP
     626             :   { 222,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #222 = OR16mi
     627             :   { 223,        4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #223 = OR16mm
     628             :   { 224,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #224 = OR16mr
     629             :   { 225,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #225 = OR16ri
     630             :   { 226,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #226 = OR16rm
     631             :   { 227,        4,      2,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #227 = OR16rm_POST
     632             :   { 228,        3,      1,      0,      0,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #228 = OR16rr
     633             :   { 229,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #229 = OR8mi
     634             :   { 230,        4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #230 = OR8mm
     635             :   { 231,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #231 = OR8mr
     636             :   { 232,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #232 = OR8ri
     637             :   { 233,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #233 = OR8rm
     638             :   { 234,        4,      2,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #234 = OR8rm_POST
     639             :   { 235,        3,      1,      0,      0,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #235 = OR8rr
     640             :   { 236,        1,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, ImplicitList2, ImplicitList2, OperandInfo51, -1 ,nullptr },  // Inst #236 = POP16r
     641             :   { 237,        1,      0,      0,      0,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x9ULL, ImplicitList2, ImplicitList2, OperandInfo51, -1 ,nullptr },  // Inst #237 = PUSH16r
     642             :   { 238,        0,      0,      0,      0,      0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #238 = RET
     643             :   { 239,        0,      0,      0,      0,      0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x9ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #239 = RETI
     644             :   { 240,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x9ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #240 = SAR16r1
     645             :   { 241,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #241 = SAR16r1c
     646             :   { 242,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x9ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #242 = SAR8r1
     647             :   { 243,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #243 = SAR8r1c
     648             :   { 244,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #244 = SBC16mi
     649             :   { 245,        4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, ImplicitList1, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #245 = SBC16mm
     650             :   { 246,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #246 = SBC16mr
     651             :   { 247,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #247 = SBC16ri
     652             :   { 248,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #248 = SBC16rm
     653             :   { 249,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #249 = SBC16rr
     654             :   { 250,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #250 = SBC8mi
     655             :   { 251,        4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, ImplicitList1, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #251 = SBC8mm
     656             :   { 252,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #252 = SBC8mr
     657             :   { 253,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #253 = SBC8ri
     658             :   { 254,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #254 = SBC8rm
     659             :   { 255,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #255 = SBC8rr
     660             :   { 256,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x9ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #256 = SEXT16r
     661             :   { 257,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #257 = SHL16r1
     662             :   { 258,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #258 = SHL8r1
     663             :   { 259,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #259 = SUB16mi
     664             :   { 260,        4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #260 = SUB16mm
     665             :   { 261,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #261 = SUB16mr
     666             :   { 262,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #262 = SUB16ri
     667             :   { 263,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #263 = SUB16rm
     668             :   { 264,        4,      2,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #264 = SUB16rm_POST
     669             :   { 265,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #265 = SUB16rr
     670             :   { 266,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #266 = SUB8mi
     671             :   { 267,        4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #267 = SUB8mm
     672             :   { 268,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #268 = SUB8mr
     673             :   { 269,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #269 = SUB8ri
     674             :   { 270,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #270 = SUB8rm
     675             :   { 271,        4,      2,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #271 = SUB8rm_POST
     676             :   { 272,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #272 = SUB8rr
     677             :   { 273,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x9ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #273 = SWPB16r
     678             :   { 274,        4,      1,      0,      0,      0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, ImplicitList1, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #274 = Select16
     679             :   { 275,        4,      1,      0,      0,      0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #275 = Select8
     680             :   { 276,        3,      1,      0,      0,      0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #276 = Shl16
     681             :   { 277,        3,      1,      0,      0,      0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, nullptr, ImplicitList1, OperandInfo60, -1 ,nullptr },  // Inst #277 = Shl8
     682             :   { 278,        3,      1,      0,      0,      0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #278 = Sra16
     683             :   { 279,        3,      1,      0,      0,      0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, nullptr, ImplicitList1, OperandInfo60, -1 ,nullptr },  // Inst #279 = Sra8
     684             :   { 280,        3,      1,      0,      0,      0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #280 = Srl16
     685             :   { 281,        3,      1,      0,      0,      0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, nullptr, ImplicitList1, OperandInfo60, -1 ,nullptr },  // Inst #281 = Srl8
     686             :   { 282,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #282 = XOR16mi
     687             :   { 283,        4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #283 = XOR16mm
     688             :   { 284,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #284 = XOR16mr
     689             :   { 285,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #285 = XOR16ri
     690             :   { 286,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #286 = XOR16rm
     691             :   { 287,        4,      2,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #287 = XOR16rm_POST
     692             :   { 288,        3,      1,      0,      0,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #288 = XOR16rr
     693             :   { 289,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #289 = XOR8mi
     694             :   { 290,        4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #290 = XOR8mm
     695             :   { 291,        3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #291 = XOR8mr
     696             :   { 292,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #292 = XOR8ri
     697             :   { 293,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #293 = XOR8rm
     698             :   { 294,        4,      2,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #294 = XOR8rm_POST
     699             :   { 295,        3,      1,      0,      0,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #295 = XOR8rr
     700             :   { 296,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #296 = ZEXT16r
     701             : };
     702             : 
     703             : extern const char MSP430InstrNameData[] = {
     704             :   /* 0 */ 'S', 'H', 'L', '1', '6', 'r', '1', 0,
     705             :   /* 8 */ 'S', 'A', 'R', '1', '6', 'r', '1', 0,
     706             :   /* 16 */ 'S', 'H', 'L', '8', 'r', '1', 0,
     707             :   /* 23 */ 'S', 'A', 'R', '8', 'r', '1', 0,
     708             :   /* 30 */ 'G', '_', 'F', 'L', 'O', 'G', '2', 0,
     709             :   /* 38 */ 'G', '_', 'F', 'E', 'X', 'P', '2', 0,
     710             :   /* 46 */ 'S', 'r', 'a', '1', '6', 0,
     711             :   /* 52 */ 'S', 'h', 'l', '1', '6', 0,
     712             :   /* 58 */ 'S', 'r', 'l', '1', '6', 0,
     713             :   /* 64 */ 'S', 'e', 'l', 'e', 'c', 't', '1', '6', 0,
     714             :   /* 73 */ 'S', 'r', 'a', '8', 0,
     715             :   /* 78 */ 'S', 'h', 'l', '8', 0,
     716             :   /* 83 */ 'S', 'r', 'l', '8', 0,
     717             :   /* 88 */ 'M', 'O', 'V', 'Z', 'X', '1', '6', 'r', 'm', '8', 0,
     718             :   /* 99 */ 'M', 'O', 'V', 'Z', 'X', '1', '6', 'r', 'r', '8', 0,
     719             :   /* 110 */ 'S', 'e', 'l', 'e', 'c', 't', '8', 0,
     720             :   /* 118 */ 'G', '_', 'F', 'M', 'A', 0,
     721             :   /* 124 */ 'G', '_', 'F', 'S', 'U', 'B', 0,
     722             :   /* 131 */ 'G', '_', 'S', 'U', 'B', 0,
     723             :   /* 137 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'S', 'U', 'B', 0,
     724             :   /* 153 */ 'J', 'C', 'C', 0,
     725             :   /* 157 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', 0,
     726             :   /* 169 */ 'G', '_', 'F', 'P', 'T', 'R', 'U', 'N', 'C', 0,
     727             :   /* 179 */ 'G', '_', 'T', 'R', 'U', 'N', 'C', 0,
     728             :   /* 187 */ 'G', '_', 'S', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
     729             :   /* 198 */ 'G', '_', 'Z', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
     730             :   /* 209 */ 'G', '_', 'L', 'O', 'A', 'D', 0,
     731             :   /* 216 */ 'G', '_', 'F', 'A', 'D', 'D', 0,
     732             :   /* 223 */ 'G', '_', 'A', 'D', 'D', 0,
     733             :   /* 229 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'D', 'D', 0,
     734             :   /* 245 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'N', 'A', 'N', 'D', 0,
     735             :   /* 262 */ 'G', '_', 'A', 'N', 'D', 0,
     736             :   /* 268 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'N', 'D', 0,
     737             :   /* 284 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
     738             :   /* 297 */ 'G', '_', 'B', 'R', 'C', 'O', 'N', 'D', 0,
     739             :   /* 306 */ 'L', 'O', 'A', 'D', '_', 'S', 'T', 'A', 'C', 'K', '_', 'G', 'U', 'A', 'R', 'D', 0,
     740             :   /* 323 */ 'G', '_', 'U', 'S', 'U', 'B', 'E', 0,
     741             :   /* 331 */ 'R', 'E', 'G', '_', 'S', 'E', 'Q', 'U', 'E', 'N', 'C', 'E', 0,
     742             :   /* 344 */ 'G', '_', 'U', 'A', 'D', 'D', 'E', 0,
     743             :   /* 352 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
     744             :   /* 359 */ 'L', 'O', 'C', 'A', 'L', '_', 'E', 'S', 'C', 'A', 'P', 'E', 0,
     745             :   /* 372 */ 'G', '_', 'S', 'T', 'O', 'R', 'E', 0,
     746             :   /* 380 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
     747             :   /* 390 */ 'G', '_', 'G', 'L', 'O', 'B', 'A', 'L', '_', 'V', 'A', 'L', 'U', 'E', 0,
     748             :   /* 405 */ 'G', '_', 'I', 'M', 'P', 'L', 'I', 'C', 'I', 'T', '_', 'D', 'E', 'F', 0,
     749             :   /* 420 */ 'G', '_', 'F', 'N', 'E', 'G', 0,
     750             :   /* 427 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
     751             :   /* 442 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
     752             :   /* 456 */ 'S', 'U', 'B', 'R', 'E', 'G', '_', 'T', 'O', '_', 'R', 'E', 'G', 0,
     753             :   /* 470 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', 0,
     754             :   /* 487 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'C', 'H', 'G', 0,
     755             :   /* 504 */ 'G', '_', 'F', 'L', 'O', 'G', 0,
     756             :   /* 511 */ 'G', '_', 'V', 'A', 'A', 'R', 'G', 0,
     757             :   /* 519 */ 'G', '_', 'S', 'M', 'U', 'L', 'H', 0,
     758             :   /* 527 */ 'G', '_', 'U', 'M', 'U', 'L', 'H', 0,
     759             :   /* 535 */ 'G', '_', 'P', 'H', 'I', 0,
     760             :   /* 541 */ 'G', '_', 'F', 'P', 'T', 'O', 'S', 'I', 0,
     761             :   /* 550 */ 'R', 'E', 'T', 'I', 0,
     762             :   /* 555 */ 'G', '_', 'F', 'P', 'T', 'O', 'U', 'I', 0,
     763             :   /* 564 */ 'G', '_', 'P', 'T', 'R', '_', 'M', 'A', 'S', 'K', 0,
     764             :   /* 575 */ 'G', 'C', '_', 'L', 'A', 'B', 'E', 'L', 0,
     765             :   /* 584 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0,
     766             :   /* 594 */ 'E', 'H', '_', 'L', 'A', 'B', 'E', 'L', 0,
     767             :   /* 603 */ 'A', 'N', 'N', 'O', 'T', 'A', 'T', 'I', 'O', 'N', '_', 'L', 'A', 'B', 'E', 'L', 0,
     768             :   /* 620 */ 'I', 'C', 'A', 'L', 'L', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'F', 'U', 'N', 'N', 'E', 'L', 0,
     769             :   /* 640 */ 'G', '_', 'S', 'H', 'L', 0,
     770             :   /* 646 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'A', 'I', 'L', '_', 'C', 'A', 'L', 'L', 0,
     771             :   /* 666 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'Y', 'P', 'E', 'D', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
     772             :   /* 693 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
     773             :   /* 714 */ 'F', 'E', 'N', 'T', 'R', 'Y', '_', 'C', 'A', 'L', 'L', 0,
     774             :   /* 726 */ 'K', 'I', 'L', 'L', 0,
     775             :   /* 731 */ 'G', '_', 'F', 'M', 'U', 'L', 0,
     776             :   /* 738 */ 'G', '_', 'M', 'U', 'L', 0,
     777             :   /* 744 */ 'G', '_', 'F', 'R', 'E', 'M', 0,
     778             :   /* 751 */ 'G', '_', 'S', 'R', 'E', 'M', 0,
     779             :   /* 758 */ 'G', '_', 'U', 'R', 'E', 'M', 0,
     780             :   /* 765 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', 0,
     781             :   /* 775 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'I', 'N', 0,
     782             :   /* 792 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'I', 'N', 0,
     783             :   /* 808 */ 'C', 'F', 'I', '_', 'I', 'N', 'S', 'T', 'R', 'U', 'C', 'T', 'I', 'O', 'N', 0,
     784             :   /* 824 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 0,
     785             :   /* 841 */ 'G', '_', 'S', 'S', 'U', 'B', 'O', 0,
     786             :   /* 849 */ 'G', '_', 'S', 'A', 'D', 'D', 'O', 0,
     787             :   /* 857 */ 'G', '_', 'S', 'M', 'U', 'L', 'O', 0,
     788             :   /* 865 */ 'G', '_', 'U', 'M', 'U', 'L', 'O', 0,
     789             :   /* 873 */ 'S', 'T', 'A', 'C', 'K', 'M', 'A', 'P', 0,
     790             :   /* 882 */ 'G', '_', 'B', 'S', 'W', 'A', 'P', 0,
     791             :   /* 890 */ 'G', '_', 'G', 'E', 'P', 0,
     792             :   /* 896 */ 'G', '_', 'S', 'I', 'T', 'O', 'F', 'P', 0,
     793             :   /* 905 */ 'G', '_', 'U', 'I', 'T', 'O', 'F', 'P', 0,
     794             :   /* 914 */ 'G', '_', 'F', 'C', 'M', 'P', 0,
     795             :   /* 921 */ 'G', '_', 'I', 'C', 'M', 'P', 0,
     796             :   /* 928 */ 'J', 'M', 'P', 0,
     797             :   /* 932 */ 'N', 'O', 'P', 0,
     798             :   /* 936 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'O', 'P', 0,
     799             :   /* 949 */ 'F', 'A', 'U', 'L', 'T', 'I', 'N', 'G', '_', 'O', 'P', 0,
     800             :   /* 961 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 0,
     801             :   /* 976 */ 'G', '_', 'F', 'E', 'X', 'P', 0,
     802             :   /* 983 */ 'G', '_', 'B', 'R', 0,
     803             :   /* 988 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'N', 'T', 'E', 'R', 0,
     804             :   /* 1013 */ 'G', '_', 'A', 'S', 'H', 'R', 0,
     805             :   /* 1020 */ 'G', '_', 'L', 'S', 'H', 'R', 0,
     806             :   /* 1027 */ 'G', '_', 'S', 'H', 'U', 'F', 'F', 'L', 'E', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
     807             :   /* 1044 */ 'G', '_', 'X', 'O', 'R', 0,
     808             :   /* 1050 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'O', 'R', 0,
     809             :   /* 1066 */ 'G', '_', 'O', 'R', 0,
     810             :   /* 1071 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'O', 'R', 0,
     811             :   /* 1086 */ 'G', '_', 'I', 'N', 'T', 'T', 'O', 'P', 'T', 'R', 0,
     812             :   /* 1097 */ 'G', '_', 'F', 'A', 'B', 'S', 0,
     813             :   /* 1104 */ 'G', '_', 'U', 'N', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
     814             :   /* 1121 */ 'G', '_', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
     815             :   /* 1136 */ 'C', 'O', 'P', 'Y', '_', 'T', 'O', '_', 'R', 'E', 'G', 'C', 'L', 'A', 'S', 'S', 0,
     816             :   /* 1153 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'W', 'I', 'T', 'H', '_', 'S', 'U', 'C', 'C', 'E', 'S', 'S', 0,
     817             :   /* 1183 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'W', '_', 'S', 'I', 'D', 'E', '_', 'E', 'F', 'F', 'E', 'C', 'T', 'S', 0,
     818             :   /* 1210 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', 0,
     819             :   /* 1220 */ 'G', '_', 'S', 'E', 'L', 'E', 'C', 'T', 0,
     820             :   /* 1229 */ 'G', '_', 'B', 'R', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', 0,
     821             :   /* 1242 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'R', 'E', 'T', 0,
     822             :   /* 1256 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'X', 'I', 'T', 0,
     823             :   /* 1280 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
     824             :   /* 1301 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
     825             :   /* 1321 */ 'G', '_', 'F', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
     826             :   /* 1333 */ 'G', '_', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
     827             :   /* 1344 */ 'S', 'T', 'A', 'T', 'E', 'P', 'O', 'I', 'N', 'T', 0,
     828             :   /* 1355 */ 'P', 'A', 'T', 'C', 'H', 'P', 'O', 'I', 'N', 'T', 0,
     829             :   /* 1366 */ 'G', '_', 'P', 'T', 'R', 'T', 'O', 'I', 'N', 'T', 0,
     830             :   /* 1377 */ 'G', '_', 'V', 'A', 'S', 'T', 'A', 'R', 'T', 0,
     831             :   /* 1387 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
     832             :   /* 1402 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', 0,
     833             :   /* 1411 */ 'G', '_', 'B', 'I', 'T', 'C', 'A', 'S', 'T', 0,
     834             :   /* 1421 */ 'S', 'U', 'B', '1', '6', 'r', 'm', '_', 'P', 'O', 'S', 'T', 0,
     835             :   /* 1434 */ 'A', 'D', 'D', '1', '6', 'r', 'm', '_', 'P', 'O', 'S', 'T', 0,
     836             :   /* 1447 */ 'A', 'N', 'D', '1', '6', 'r', 'm', '_', 'P', 'O', 'S', 'T', 0,
     837             :   /* 1460 */ 'X', 'O', 'R', '1', '6', 'r', 'm', '_', 'P', 'O', 'S', 'T', 0,
     838             :   /* 1473 */ 'M', 'O', 'V', '1', '6', 'r', 'm', '_', 'P', 'O', 'S', 'T', 0,
     839             :   /* 1486 */ 'S', 'U', 'B', '8', 'r', 'm', '_', 'P', 'O', 'S', 'T', 0,
     840             :   /* 1498 */ 'A', 'D', 'D', '8', 'r', 'm', '_', 'P', 'O', 'S', 'T', 0,
     841             :   /* 1510 */ 'A', 'N', 'D', '8', 'r', 'm', '_', 'P', 'O', 'S', 'T', 0,
     842             :   /* 1522 */ 'X', 'O', 'R', '8', 'r', 'm', '_', 'P', 'O', 'S', 'T', 0,
     843             :   /* 1534 */ 'M', 'O', 'V', '8', 'r', 'm', '_', 'P', 'O', 'S', 'T', 0,
     844             :   /* 1546 */ 'G', '_', 'F', 'P', 'E', 'X', 'T', 0,
     845             :   /* 1554 */ 'G', '_', 'S', 'E', 'X', 'T', 0,
     846             :   /* 1561 */ 'G', '_', 'A', 'N', 'Y', 'E', 'X', 'T', 0,
     847             :   /* 1570 */ 'G', '_', 'Z', 'E', 'X', 'T', 0,
     848             :   /* 1577 */ 'G', '_', 'F', 'D', 'I', 'V', 0,
     849             :   /* 1584 */ 'G', '_', 'S', 'D', 'I', 'V', 0,
     850             :   /* 1591 */ 'G', '_', 'U', 'D', 'I', 'V', 0,
     851             :   /* 1598 */ 'G', '_', 'F', 'P', 'O', 'W', 0,
     852             :   /* 1605 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'A', 'X', 0,
     853             :   /* 1622 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'A', 'X', 0,
     854             :   /* 1638 */ 'G', '_', 'F', 'R', 'A', 'M', 'E', '_', 'I', 'N', 'D', 'E', 'X', 0,
     855             :   /* 1652 */ 'C', 'O', 'P', 'Y', 0,
     856             :   /* 1657 */ 'S', 'A', 'R', '1', '6', 'r', '1', 'c', 0,
     857             :   /* 1666 */ 'S', 'A', 'R', '8', 'r', '1', 'c', 0,
     858             :   /* 1674 */ 'A', 'D', 'D', 'f', 'r', 'a', 'm', 'e', 0,
     859             :   /* 1683 */ 'B', 'i', 0,
     860             :   /* 1686 */ 'C', 'A', 'L', 'L', 'i', 0,
     861             :   /* 1692 */ 'S', 'U', 'B', '1', '6', 'm', 'i', 0,
     862             :   /* 1700 */ 'S', 'B', 'C', '1', '6', 'm', 'i', 0,
     863             :   /* 1708 */ 'A', 'D', 'C', '1', '6', 'm', 'i', 0,
     864             :   /* 1716 */ 'A', 'D', 'D', '1', '6', 'm', 'i', 0,
     865             :   /* 1724 */ 'A', 'N', 'D', '1', '6', 'm', 'i', 0,
     866             :   /* 1732 */ 'C', 'M', 'P', '1', '6', 'm', 'i', 0,
     867             :   /* 1740 */ 'X', 'O', 'R', '1', '6', 'm', 'i', 0,
     868             :   /* 1748 */ 'B', 'I', 'T', '1', '6', 'm', 'i', 0,
     869             :   /* 1756 */ 'M', 'O', 'V', '1', '6', 'm', 'i', 0,
     870             :   /* 1764 */ 'S', 'U', 'B', '8', 'm', 'i', 0,
     871             :   /* 1771 */ 'S', 'B', 'C', '8', 'm', 'i', 0,
     872             :   /* 1778 */ 'A', 'D', 'C', '8', 'm', 'i', 0,
     873             :   /* 1785 */ 'A', 'D', 'D', '8', 'm', 'i', 0,
     874             :   /* 1792 */ 'A', 'N', 'D', '8', 'm', 'i', 0,
     875             :   /* 1799 */ 'C', 'M', 'P', '8', 'm', 'i', 0,
     876             :   /* 1806 */ 'X', 'O', 'R', '8', 'm', 'i', 0,
     877             :   /* 1813 */ 'B', 'I', 'T', '8', 'm', 'i', 0,
     878             :   /* 1820 */ 'M', 'O', 'V', '8', 'm', 'i', 0,
     879             :   /* 1827 */ 'S', 'U', 'B', '1', '6', 'r', 'i', 0,
     880             :   /* 1835 */ 'S', 'B', 'C', '1', '6', 'r', 'i', 0,
     881             :   /* 1843 */ 'A', 'D', 'C', '1', '6', 'r', 'i', 0,
     882             :   /* 1851 */ 'A', 'D', 'D', '1', '6', 'r', 'i', 0,
     883             :   /* 1859 */ 'A', 'N', 'D', '1', '6', 'r', 'i', 0,
     884             :   /* 1867 */ 'C', 'M', 'P', '1', '6', 'r', 'i', 0,
     885             :   /* 1875 */ 'X', 'O', 'R', '1', '6', 'r', 'i', 0,
     886             :   /* 1883 */ 'B', 'I', 'T', '1', '6', 'r', 'i', 0,
     887             :   /* 1891 */ 'M', 'O', 'V', '1', '6', 'r', 'i', 0,
     888             :   /* 1899 */ 'S', 'U', 'B', '8', 'r', 'i', 0,
     889             :   /* 1906 */ 'S', 'B', 'C', '8', 'r', 'i', 0,
     890             :   /* 1913 */ 'A', 'D', 'C', '8', 'r', 'i', 0,
     891             :   /* 1920 */ 'A', 'D', 'D', '8', 'r', 'i', 0,
     892             :   /* 1927 */ 'A', 'N', 'D', '8', 'r', 'i', 0,
     893             :   /* 1934 */ 'C', 'M', 'P', '8', 'r', 'i', 0,
     894             :   /* 1941 */ 'X', 'O', 'R', '8', 'r', 'i', 0,
     895             :   /* 1948 */ 'B', 'I', 'T', '8', 'r', 'i', 0,
     896             :   /* 1955 */ 'M', 'O', 'V', '8', 'r', 'i', 0,
     897             :   /* 1962 */ 'B', 'm', 0,
     898             :   /* 1965 */ 'C', 'A', 'L', 'L', 'm', 0,
     899             :   /* 1971 */ 'S', 'U', 'B', '1', '6', 'm', 'm', 0,
     900             :   /* 1979 */ 'S', 'B', 'C', '1', '6', 'm', 'm', 0,
     901             :   /* 1987 */ 'A', 'D', 'C', '1', '6', 'm', 'm', 0,
     902             :   /* 1995 */ 'B', 'I', 'C', '1', '6', 'm', 'm', 0,
     903             :   /* 2003 */ 'A', 'D', 'D', '1', '6', 'm', 'm', 0,
     904             :   /* 2011 */ 'A', 'N', 'D', '1', '6', 'm', 'm', 0,
     905             :   /* 2019 */ 'X', 'O', 'R', '1', '6', 'm', 'm', 0,
     906             :   /* 2027 */ 'B', 'I', 'T', '1', '6', 'm', 'm', 0,
     907             :   /* 2035 */ 'M', 'O', 'V', '1', '6', 'm', 'm', 0,
     908             :   /* 2043 */ 'S', 'U', 'B', '8', 'm', 'm', 0,
     909             :   /* 2050 */ 'S', 'B', 'C', '8', 'm', 'm', 0,
     910             :   /* 2057 */ 'A', 'D', 'C', '8', 'm', 'm', 0,
     911             :   /* 2064 */ 'B', 'I', 'C', '8', 'm', 'm', 0,
     912             :   /* 2071 */ 'A', 'D', 'D', '8', 'm', 'm', 0,
     913             :   /* 2078 */ 'A', 'N', 'D', '8', 'm', 'm', 0,
     914             :   /* 2085 */ 'X', 'O', 'R', '8', 'm', 'm', 0,
     915             :   /* 2092 */ 'B', 'I', 'T', '8', 'm', 'm', 0,
     916             :   /* 2099 */ 'M', 'O', 'V', '8', 'm', 'm', 0,
     917             :   /* 2106 */ 'S', 'U', 'B', '1', '6', 'r', 'm', 0,
     918             :   /* 2114 */ 'S', 'B', 'C', '1', '6', 'r', 'm', 0,
     919             :   /* 2122 */ 'A', 'D', 'C', '1', '6', 'r', 'm', 0,
     920             :   /* 2130 */ 'B', 'I', 'C', '1', '6', 'r', 'm', 0,
     921             :   /* 2138 */ 'A', 'D', 'D', '1', '6', 'r', 'm', 0,
     922             :   /* 2146 */ 'A', 'N', 'D', '1', '6', 'r', 'm', 0,
     923             :   /* 2154 */ 'C', 'M', 'P', '1', '6', 'r', 'm', 0,
     924             :   /* 2162 */ 'X', 'O', 'R', '1', '6', 'r', 'm', 0,
     925             :   /* 2170 */ 'B', 'I', 'T', '1', '6', 'r', 'm', 0,
     926             :   /* 2178 */ 'M', 'O', 'V', '1', '6', 'r', 'm', 0,
     927             :   /* 2186 */ 'S', 'U', 'B', '8', 'r', 'm', 0,
     928             :   /* 2193 */ 'S', 'B', 'C', '8', 'r', 'm', 0,
     929             :   /* 2200 */ 'A', 'D', 'C', '8', 'r', 'm', 0,
     930             :   /* 2207 */ 'B', 'I', 'C', '8', 'r', 'm', 0,
     931             :   /* 2214 */ 'A', 'D', 'D', '8', 'r', 'm', 0,
     932             :   /* 2221 */ 'A', 'N', 'D', '8', 'r', 'm', 0,
     933             :   /* 2228 */ 'C', 'M', 'P', '8', 'r', 'm', 0,
     934             :   /* 2235 */ 'X', 'O', 'R', '8', 'r', 'm', 0,
     935             :   /* 2242 */ 'B', 'I', 'T', '8', 'r', 'm', 0,
     936             :   /* 2249 */ 'M', 'O', 'V', '8', 'r', 'm', 0,
     937             :   /* 2256 */ 'S', 'W', 'P', 'B', '1', '6', 'r', 0,
     938             :   /* 2264 */ 'P', 'U', 'S', 'H', '1', '6', 'r', 0,
     939             :   /* 2272 */ 'P', 'O', 'P', '1', '6', 'r', 0,
     940             :   /* 2279 */ 'S', 'E', 'X', 'T', '1', '6', 'r', 0,
     941             :   /* 2287 */ 'Z', 'E', 'X', 'T', '1', '6', 'r', 0,
     942             :   /* 2295 */ 'B', 'r', 0,
     943             :   /* 2298 */ 'C', 'A', 'L', 'L', 'r', 0,
     944             :   /* 2304 */ 'S', 'U', 'B', '1', '6', 'm', 'r', 0,
     945             :   /* 2312 */ 'S', 'B', 'C', '1', '6', 'm', 'r', 0,
     946             :   /* 2320 */ 'A', 'D', 'C', '1', '6', 'm', 'r', 0,
     947             :   /* 2328 */ 'B', 'I', 'C', '1', '6', 'm', 'r', 0,
     948             :   /* 2336 */ 'A', 'D', 'D', '1', '6', 'm', 'r', 0,
     949             :   /* 2344 */ 'A', 'N', 'D', '1', '6', 'm', 'r', 0,
     950             :   /* 2352 */ 'C', 'M', 'P', '1', '6', 'm', 'r', 0,
     951             :   /* 2360 */ 'X', 'O', 'R', '1', '6', 'm', 'r', 0,
     952             :   /* 2368 */ 'B', 'I', 'T', '1', '6', 'm', 'r', 0,
     953             :   /* 2376 */ 'M', 'O', 'V', '1', '6', 'm', 'r', 0,
     954             :   /* 2384 */ 'S', 'U', 'B', '8', 'm', 'r', 0,
     955             :   /* 2391 */ 'S', 'B', 'C', '8', 'm', 'r', 0,
     956             :   /* 2398 */ 'A', 'D', 'C', '8', 'm', 'r', 0,
     957             :   /* 2405 */ 'B', 'I', 'C', '8', 'm', 'r', 0,
     958             :   /* 2412 */ 'A', 'D', 'D', '8', 'm', 'r', 0,
     959             :   /* 2419 */ 'A', 'N', 'D', '8', 'm', 'r', 0,
     960             :   /* 2426 */ 'C', 'M', 'P', '8', 'm', 'r', 0,
     961             :   /* 2433 */ 'X', 'O', 'R', '8', 'm', 'r', 0,
     962             :   /* 2440 */ 'B', 'I', 'T', '8', 'm', 'r', 0,
     963             :   /* 2447 */ 'M', 'O', 'V', '8', 'm', 'r', 0,
     964             :   /* 2454 */ 'S', 'U', 'B', '1', '6', 'r', 'r', 0,
     965             :   /* 2462 */ 'S', 'B', 'C', '1', '6', 'r', 'r', 0,
     966             :   /* 2470 */ 'A', 'D', 'C', '1', '6', 'r', 'r', 0,
     967             :   /* 2478 */ 'B', 'I', 'C', '1', '6', 'r', 'r', 0,
     968             :   /* 2486 */ 'A', 'D', 'D', '1', '6', 'r', 'r', 0,
     969             :   /* 2494 */ 'A', 'N', 'D', '1', '6', 'r', 'r', 0,
     970             :   /* 2502 */ 'C', 'M', 'P', '1', '6', 'r', 'r', 0,
     971             :   /* 2510 */ 'X', 'O', 'R', '1', '6', 'r', 'r', 0,
     972             :   /* 2518 */ 'B', 'I', 'T', '1', '6', 'r', 'r', 0,
     973             :   /* 2526 */ 'M', 'O', 'V', '1', '6', 'r', 'r', 0,
     974             :   /* 2534 */ 'S', 'U', 'B', '8', 'r', 'r', 0,
     975             :   /* 2541 */ 'S', 'B', 'C', '8', 'r', 'r', 0,
     976             :   /* 2548 */ 'A', 'D', 'C', '8', 'r', 'r', 0,
     977             :   /* 2555 */ 'B', 'I', 'C', '8', 'r', 'r', 0,
     978             :   /* 2562 */ 'A', 'D', 'D', '8', 'r', 'r', 0,
     979             :   /* 2569 */ 'A', 'N', 'D', '8', 'r', 'r', 0,
     980             :   /* 2576 */ 'C', 'M', 'P', '8', 'r', 'r', 0,
     981             :   /* 2583 */ 'X', 'O', 'R', '8', 'r', 'r', 0,
     982             :   /* 2590 */ 'B', 'I', 'T', '8', 'r', 'r', 0,
     983             :   /* 2597 */ 'M', 'O', 'V', '8', 'r', 'r', 0,
     984             : };
     985             : 
     986             : extern const unsigned MSP430InstrNameIndices[] = {
     987             :     537U, 765U, 808U, 594U, 575U, 603U, 726U, 427U, 
     988             :     442U, 407U, 456U, 1136U, 380U, 584U, 331U, 1652U, 
     989             :     352U, 1387U, 284U, 873U, 714U, 1355U, 306U, 1344U, 
     990             :     359U, 949U, 936U, 988U, 1242U, 1256U, 646U, 693U, 
     991             :     666U, 620U, 223U, 131U, 738U, 1584U, 1591U, 751U, 
     992             :     758U, 262U, 1066U, 1044U, 405U, 535U, 1638U, 390U, 
     993             :     1210U, 1104U, 1402U, 1121U, 1366U, 1086U, 1411U, 209U, 
     994             :     187U, 198U, 372U, 1153U, 470U, 487U, 229U, 137U, 
     995             :     268U, 245U, 1071U, 1050U, 1622U, 792U, 1605U, 775U, 
     996             :     297U, 1229U, 157U, 1183U, 1561U, 179U, 1333U, 1321U, 
     997             :     1377U, 511U, 1554U, 1570U, 640U, 1020U, 1013U, 921U, 
     998             :     914U, 1220U, 344U, 323U, 849U, 841U, 865U, 857U, 
     999             :     527U, 519U, 216U, 124U, 731U, 118U, 1577U, 744U, 
    1000             :     1598U, 976U, 38U, 504U, 30U, 420U, 1546U, 169U, 
    1001             :     541U, 555U, 896U, 905U, 1097U, 890U, 564U, 983U, 
    1002             :     1301U, 1280U, 1027U, 882U, 1708U, 1987U, 2320U, 1843U, 
    1003             :     2122U, 2470U, 1778U, 2057U, 2398U, 1913U, 2200U, 2548U, 
    1004             :     1716U, 2003U, 2336U, 1851U, 2138U, 1434U, 2486U, 1785U, 
    1005             :     2071U, 2412U, 1920U, 2214U, 1498U, 2562U, 1674U, 824U, 
    1006             :     961U, 1724U, 2011U, 2344U, 1859U, 2146U, 1447U, 2494U, 
    1007             :     1792U, 2078U, 2419U, 1927U, 2221U, 1510U, 2569U, 1995U, 
    1008             :     2328U, 2130U, 2478U, 2064U, 2405U, 2207U, 2555U, 1748U, 
    1009             :     2027U, 2368U, 1883U, 2170U, 2518U, 1813U, 2092U, 2440U, 
    1010             :     1948U, 2242U, 2590U, 1683U, 1962U, 2295U, 1686U, 1965U, 
    1011             :     2298U, 1732U, 2352U, 1867U, 2154U, 2502U, 1799U, 2426U, 
    1012             :     1934U, 2228U, 2576U, 153U, 928U, 1756U, 2035U, 2376U, 
    1013             :     1891U, 2178U, 1473U, 2526U, 1820U, 2099U, 2447U, 1955U, 
    1014             :     2249U, 1534U, 2597U, 88U, 99U, 932U, 1741U, 2020U, 
    1015             :     2361U, 1876U, 2163U, 1461U, 2511U, 1807U, 2086U, 2434U, 
    1016             :     1942U, 2236U, 1523U, 2584U, 2272U, 2264U, 1252U, 550U, 
    1017             :     8U, 1657U, 23U, 1666U, 1700U, 1979U, 2312U, 1835U, 
    1018             :     2114U, 2462U, 1771U, 2050U, 2391U, 1906U, 2193U, 2541U, 
    1019             :     2279U, 0U, 16U, 1692U, 1971U, 2304U, 1827U, 2106U, 
    1020             :     1421U, 2454U, 1764U, 2043U, 2384U, 1899U, 2186U, 1486U, 
    1021             :     2534U, 2256U, 64U, 110U, 52U, 78U, 46U, 73U, 
    1022             :     58U, 83U, 1740U, 2019U, 2360U, 1875U, 2162U, 1460U, 
    1023             :     2510U, 1806U, 2085U, 2433U, 1941U, 2235U, 1522U, 2583U, 
    1024             :     2287U, 
    1025             : };
    1026             : 
    1027             : static inline void InitMSP430MCInstrInfo(MCInstrInfo *II) {
    1028             :   II->InitMCInstrInfo(MSP430Insts, MSP430InstrNameIndices, MSP430InstrNameData, 297);
    1029             : }
    1030             : 
    1031             : } // end llvm namespace
    1032             : #endif // GET_INSTRINFO_MC_DESC
    1033             : 
    1034             : #ifdef GET_INSTRINFO_HEADER
    1035             : #undef GET_INSTRINFO_HEADER
    1036             : namespace llvm {
    1037             : struct MSP430GenInstrInfo : public TargetInstrInfo {
    1038             :   explicit MSP430GenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);
    1039          64 :   ~MSP430GenInstrInfo() override = default;
    1040             : 
    1041             : };
    1042             : } // end llvm namespace
    1043             : #endif // GET_INSTRINFO_HEADER
    1044             : 
    1045             : #ifdef GET_INSTRINFO_CTOR_DTOR
    1046             : #undef GET_INSTRINFO_CTOR_DTOR
    1047             : namespace llvm {
    1048             : extern const MCInstrDesc MSP430Insts[];
    1049             : extern const unsigned MSP430InstrNameIndices[];
    1050             : extern const char MSP430InstrNameData[];
    1051          64 : MSP430GenInstrInfo::MSP430GenInstrInfo(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode)
    1052         128 :   : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
    1053             :   InitMCInstrInfo(MSP430Insts, MSP430InstrNameIndices, MSP430InstrNameData, 297);
    1054          64 : }
    1055             : } // end llvm namespace
    1056             : #endif // GET_INSTRINFO_CTOR_DTOR
    1057             : 
    1058             : #ifdef GET_INSTRINFO_OPERAND_ENUM
    1059             : #undef GET_INSTRINFO_OPERAND_ENUM
    1060             : namespace llvm {
    1061             : namespace MSP430 {
    1062             : namespace OpName {
    1063             : enum {
    1064             : OPERAND_LAST
    1065             : };
    1066             : } // end namespace OpName
    1067             : } // end namespace MSP430
    1068             : } // end namespace llvm
    1069             : #endif //GET_INSTRINFO_OPERAND_ENUM
    1070             : 
    1071             : #ifdef GET_INSTRINFO_NAMED_OPS
    1072             : #undef GET_INSTRINFO_NAMED_OPS
    1073             : namespace llvm {
    1074             : namespace MSP430 {
    1075             : LLVM_READONLY
    1076             : int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
    1077             :   return -1;
    1078             : }
    1079             : } // end namespace MSP430
    1080             : } // end namespace llvm
    1081             : #endif //GET_INSTRINFO_NAMED_OPS
    1082             : 
    1083             : #ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
    1084             : #undef GET_INSTRINFO_OPERAND_TYPES_ENUM
    1085             : namespace llvm {
    1086             : namespace MSP430 {
    1087             : namespace OpTypes {
    1088             : enum OperandType {
    1089             :   cc = 0,
    1090             :   f32imm = 1,
    1091             :   f64imm = 2,
    1092             :   i16imm = 3,
    1093             :   i1imm = 4,
    1094             :   i32imm = 5,
    1095             :   i64imm = 6,
    1096             :   i8imm = 7,
    1097             :   jmptarget = 8,
    1098             :   memdst = 9,
    1099             :   memsrc = 10,
    1100             :   ptype0 = 11,
    1101             :   ptype1 = 12,
    1102             :   ptype2 = 13,
    1103             :   ptype3 = 14,
    1104             :   ptype4 = 15,
    1105             :   ptype5 = 16,
    1106             :   type0 = 17,
    1107             :   type1 = 18,
    1108             :   type2 = 19,
    1109             :   type3 = 20,
    1110             :   type4 = 21,
    1111             :   type5 = 22,
    1112             :   OPERAND_TYPE_LIST_END
    1113             : };
    1114             : } // end namespace OpTypes
    1115             : } // end namespace MSP430
    1116             : } // end namespace llvm
    1117             : #endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
    1118             : 

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