LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/Mips - MipsGenAsmMatcher.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 591 1168 50.6 %
Date: 2017-09-14 15:23:50 Functions: 8 10 80.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Assembly Matcher Source Fragment                                           *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : 
      10             : #ifdef GET_ASSEMBLER_HEADER
      11             : #undef GET_ASSEMBLER_HEADER
      12             :   // This should be included into the middle of the declaration of
      13             :   // your subclasses implementation of MCTargetAsmParser.
      14             :   uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;
      15             :   void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
      16             :                        const OperandVector &Operands);
      17             :   void convertToMapAndConstraints(unsigned Kind,
      18             :                            const OperandVector &Operands) override;
      19             :   unsigned MatchInstructionImpl(const OperandVector &Operands,
      20             :                                 MCInst &Inst,
      21             :                                 uint64_t &ErrorInfo, bool matchingInlineAsm,
      22             :                                 unsigned VariantID = 0);
      23             :   OperandMatchResultTy MatchOperandParserImpl(
      24             :     OperandVector &Operands,
      25             :     StringRef Mnemonic);
      26             :   OperandMatchResultTy tryCustomParseOperand(
      27             :     OperandVector &Operands,
      28             :     unsigned MCK);
      29             : 
      30             : #endif // GET_ASSEMBLER_HEADER_INFO
      31             : 
      32             : 
      33             : #ifdef GET_OPERAND_DIAGNOSTIC_TYPES
      34             : #undef GET_OPERAND_DIAGNOSTIC_TYPES
      35             : 
      36             :   Match_Immz,
      37             :   Match_MemSImm10,
      38             :   Match_MemSImm10Lsl1,
      39             :   Match_MemSImm10Lsl2,
      40             :   Match_MemSImm10Lsl3,
      41             :   Match_MemSImm11,
      42             :   Match_MemSImm12,
      43             :   Match_MemSImm16,
      44             :   Match_MemSImm9,
      45             :   Match_SImm10_0,
      46             :   Match_SImm10_Lsl1,
      47             :   Match_SImm10_Lsl2,
      48             :   Match_SImm10_Lsl3,
      49             :   Match_SImm11_0,
      50             :   Match_SImm16,
      51             :   Match_SImm16_Relaxed,
      52             :   Match_SImm19_Lsl2,
      53             :   Match_SImm32,
      54             :   Match_SImm32_Relaxed,
      55             :   Match_SImm4_0,
      56             :   Match_SImm5_0,
      57             :   Match_SImm6_0,
      58             :   Match_SImm7_Lsl2,
      59             :   Match_SImm9_0,
      60             :   Match_UImm10_0,
      61             :   Match_UImm16,
      62             :   Match_UImm16_AltRelaxed,
      63             :   Match_UImm16_Relaxed,
      64             :   Match_UImm1_0,
      65             :   Match_UImm20_0,
      66             :   Match_UImm26_0,
      67             :   Match_UImm2_0,
      68             :   Match_UImm2_1,
      69             :   Match_UImm32_Coerced,
      70             :   Match_UImm3_0,
      71             :   Match_UImm4_0,
      72             :   Match_UImm5_0,
      73             :   Match_UImm5_0_Report_UImm6,
      74             :   Match_UImm5_1,
      75             :   Match_UImm5_32,
      76             :   Match_UImm5_33,
      77             :   Match_UImm5_Lsl2,
      78             :   Match_UImm6_0,
      79             :   Match_UImm6_Lsl2,
      80             :   Match_UImm7_0,
      81             :   Match_UImm7_N1,
      82             :   Match_UImm8_0,
      83             :   Match_UImmRange2_64,
      84             :   END_OPERAND_DIAGNOSTIC_TYPES
      85             : #endif // GET_OPERAND_DIAGNOSTIC_TYPES
      86             : 
      87             : 
      88             : #ifdef GET_REGISTER_MATCHER
      89             : #undef GET_REGISTER_MATCHER
      90             : 
      91             : // Flags for subtarget features that participate in instruction matching.
      92             : enum SubtargetFeatureFlag : uint64_t {
      93             :   Feature_HasMips2 = (1ULL << 10),
      94             :   Feature_HasMips3_32 = (1ULL << 16),
      95             :   Feature_HasMips3_32r2 = (1ULL << 17),
      96             :   Feature_HasMips3 = (1ULL << 11),
      97             :   Feature_NotMips3 = (1ULL << 40),
      98             :   Feature_HasMips4_32 = (1ULL << 18),
      99             :   Feature_NotMips4_32 = (1ULL << 42),
     100             :   Feature_HasMips4_32r2 = (1ULL << 19),
     101             :   Feature_HasMips5_32r2 = (1ULL << 20),
     102             :   Feature_HasMips32 = (1ULL << 12),
     103             :   Feature_HasMips32r2 = (1ULL << 13),
     104             :   Feature_HasMips32r5 = (1ULL << 14),
     105             :   Feature_HasMips32r6 = (1ULL << 15),
     106             :   Feature_NotMips32r6 = (1ULL << 41),
     107             :   Feature_IsGP64bit = (1ULL << 29),
     108             :   Feature_IsGP32bit = (1ULL << 28),
     109             :   Feature_IsPTR64bit = (1ULL << 33),
     110             :   Feature_IsPTR32bit = (1ULL << 32),
     111             :   Feature_HasMips64 = (1ULL << 21),
     112             :   Feature_NotMips64 = (1ULL << 43),
     113             :   Feature_HasMips64r2 = (1ULL << 22),
     114             :   Feature_HasMips64r6 = (1ULL << 23),
     115             :   Feature_NotMips64r6 = (1ULL << 44),
     116             :   Feature_HasMicroMips32r6 = (1ULL << 8),
     117             :   Feature_HasMicroMips64r6 = (1ULL << 9),
     118             :   Feature_InMips16Mode = (1ULL << 26),
     119             :   Feature_HasCnMips = (1ULL << 0),
     120             :   Feature_NotCnMips = (1ULL << 37),
     121             :   Feature_IsSym32 = (1ULL << 35),
     122             :   Feature_IsSym64 = (1ULL << 36),
     123             :   Feature_HasStdEnc = (1ULL << 24),
     124             :   Feature_InMicroMips = (1ULL << 25),
     125             :   Feature_NotInMicroMips = (1ULL << 39),
     126             :   Feature_HasEVA = (1ULL << 4),
     127             :   Feature_HasMSA = (1ULL << 5),
     128             :   Feature_HasMadd4 = (1ULL << 7),
     129             :   Feature_HasMT = (1ULL << 6),
     130             :   Feature_IsFP64bit = (1ULL << 27),
     131             :   Feature_NotFP64bit = (1ULL << 38),
     132             :   Feature_IsSingleFloat = (1ULL << 34),
     133             :   Feature_IsNotSingleFloat = (1ULL << 30),
     134             :   Feature_IsNotSoftFloat = (1ULL << 31),
     135             :   Feature_HasDSP = (1ULL << 1),
     136             :   Feature_HasDSPR2 = (1ULL << 2),
     137             :   Feature_HasDSPR3 = (1ULL << 3),
     138             :   Feature_None = 0
     139             : };
     140             : 
     141             : #endif // GET_REGISTER_MATCHER
     142             : 
     143             : 
     144             : #ifdef GET_SUBTARGET_FEATURE_NAME
     145             : #undef GET_SUBTARGET_FEATURE_NAME
     146             : 
     147             : // User-level names for subtarget features that participate in
     148             : // instruction matching.
     149             : static const char *getSubtargetFeatureName(uint64_t Val) {
     150             :   switch(Val) {
     151             :   case Feature_HasMips2: return "";
     152             :   case Feature_HasMips3_32: return "";
     153             :   case Feature_HasMips3_32r2: return "";
     154             :   case Feature_HasMips3: return "";
     155             :   case Feature_NotMips3: return "";
     156             :   case Feature_HasMips4_32: return "";
     157             :   case Feature_NotMips4_32: return "";
     158             :   case Feature_HasMips4_32r2: return "";
     159             :   case Feature_HasMips5_32r2: return "";
     160             :   case Feature_HasMips32: return "";
     161             :   case Feature_HasMips32r2: return "";
     162             :   case Feature_HasMips32r5: return "";
     163             :   case Feature_HasMips32r6: return "";
     164             :   case Feature_NotMips32r6: return "";
     165             :   case Feature_IsGP64bit: return "";
     166             :   case Feature_IsGP32bit: return "";
     167             :   case Feature_IsPTR64bit: return "";
     168             :   case Feature_IsPTR32bit: return "";
     169             :   case Feature_HasMips64: return "";
     170             :   case Feature_NotMips64: return "";
     171             :   case Feature_HasMips64r2: return "";
     172             :   case Feature_HasMips64r6: return "";
     173             :   case Feature_NotMips64r6: return "";
     174             :   case Feature_HasMicroMips32r6: return "";
     175             :   case Feature_HasMicroMips64r6: return "";
     176             :   case Feature_InMips16Mode: return "";
     177             :   case Feature_HasCnMips: return "";
     178             :   case Feature_NotCnMips: return "";
     179             :   case Feature_IsSym32: return "";
     180             :   case Feature_IsSym64: return "";
     181             :   case Feature_HasStdEnc: return "";
     182             :   case Feature_InMicroMips: return "";
     183             :   case Feature_NotInMicroMips: return "";
     184             :   case Feature_HasEVA: return "";
     185             :   case Feature_HasMSA: return "";
     186             :   case Feature_HasMadd4: return "";
     187             :   case Feature_HasMT: return "";
     188             :   case Feature_IsFP64bit: return "";
     189             :   case Feature_NotFP64bit: return "";
     190             :   case Feature_IsSingleFloat: return "";
     191             :   case Feature_IsNotSingleFloat: return "";
     192             :   case Feature_IsNotSoftFloat: return "";
     193             :   case Feature_HasDSP: return "";
     194             :   case Feature_HasDSPR2: return "";
     195             :   case Feature_HasDSPR3: return "";
     196             :   default: return "(unknown)";
     197             :   }
     198             : }
     199             : 
     200             : #endif // GET_SUBTARGET_FEATURE_NAME
     201             : 
     202             : 
     203             : #ifdef GET_MATCHER_IMPLEMENTATION
     204             : #undef GET_MATCHER_IMPLEMENTATION
     205             : 
     206             : namespace {
     207             : enum OperatorConversionKind {
     208             :   CVT_Done,
     209             :   CVT_Reg,
     210             :   CVT_Tied,
     211             :   CVT_95_addGPR32AsmRegOperands,
     212             :   CVT_95_addAFGR64AsmRegOperands,
     213             :   CVT_95_addFGR64AsmRegOperands,
     214             :   CVT_95_addFGR32AsmRegOperands,
     215             :   CVT_95_addSImmOperands_LT_32_GT_,
     216             :   CVT_95_addMSA128AsmRegOperands,
     217             :   CVT_95_addSImmOperands_LT_16_GT_,
     218             :   CVT_95_Reg,
     219             :   CVT_95_addImmOperands,
     220             :   CVT_95_addGPRMM16AsmRegOperands,
     221             :   CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_,
     222             :   CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_,
     223             :   CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_,
     224             :   CVT_95_addUImmOperands_LT_16_GT_,
     225             :   CVT_95_addGPR64AsmRegOperands,
     226             :   CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_,
     227             :   CVT_regZERO,
     228             :   CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_,
     229             :   CVT_regFCC0,
     230             :   CVT_95_addFCCAsmRegOperands,
     231             :   CVT_95_addCOP2AsmRegOperands,
     232             :   CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_,
     233             :   CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_,
     234             :   CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_,
     235             :   CVT_imm_95_0,
     236             :   CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_,
     237             :   CVT_95_addMemOperands,
     238             :   CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_,
     239             :   CVT_95_addCCRAsmRegOperands,
     240             :   CVT_95_addMSACtrlAsmRegOperands,
     241             :   CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_,
     242             :   CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_,
     243             :   CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_,
     244             :   CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_,
     245             :   CVT_95_addGPR32NonZeroAsmRegOperands,
     246             :   CVT_95_addGPR32ZeroAsmRegOperands,
     247             :   CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_,
     248             :   CVT_95_addCOP0AsmRegOperands,
     249             :   CVT_regZERO_64,
     250             :   CVT_95_addACC64DSPAsmRegOperands,
     251             :   CVT_95_addConstantUImmOperands_LT_1_GT_,
     252             :   CVT_regRA,
     253             :   CVT_95_addMicroMipsMemOperands,
     254             :   CVT_95_addCOP3AsmRegOperands,
     255             :   CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_,
     256             :   CVT_95_addConstantUImmOperands_LT_32_GT_,
     257             :   CVT_95_addStrictlyAFGR64AsmRegOperands,
     258             :   CVT_95_addStrictlyFGR64AsmRegOperands,
     259             :   CVT_95_addStrictlyFGR32AsmRegOperands,
     260             :   CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_,
     261             :   CVT_95_addRegListOperands,
     262             :   CVT_95_addRegPairOperands,
     263             :   CVT_95_addMovePRegPairOperands,
     264             :   CVT_95_addGPRMM16AsmRegMovePOperands,
     265             :   CVT_95_addHI32DSPAsmRegOperands,
     266             :   CVT_95_addLO32DSPAsmRegOperands,
     267             :   CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_,
     268             :   CVT_95_addHWRegsAsmRegOperands,
     269             :   CVT_95_addGPRMM16AsmRegZeroOperands,
     270             :   CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_,
     271             :   CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_,
     272             :   CVT_imm_95_2,
     273             :   CVT_imm_95_6,
     274             :   CVT_imm_95_4,
     275             :   CVT_imm_95_5,
     276             :   CVT_imm_95_31,
     277             :   CVT_NUM_CONVERTERS
     278             : };
     279             : 
     280             : enum InstructionConversionKind {
     281             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_1,
     282             :   Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1,
     283             :   Convert__FGR64AsmReg1_0__FGR64AsmReg1_1,
     284             :   Convert__FGR32AsmReg1_0__FGR32AsmReg1_1,
     285             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1,
     286             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1,
     287             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
     288             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2,
     289             :   Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2,
     290             :   Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_2__AFGR64AsmReg1_1,
     291             :   Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
     292             :   Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1,
     293             :   Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,
     294             :   Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2,
     295             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1,
     296             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1,
     297             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2,
     298             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2,
     299             :   Convert__SImm161_1,
     300             :   Convert__Reg1_0__SImm161_1,
     301             :   Convert__Reg1_0__SImm161_2,
     302             :   Convert__Reg1_0__Reg1_1__SImm161_2,
     303             :   Convert__Reg1_0__Tie0__SImm161_1,
     304             :   Convert__GPR32AsmReg1_0__Simm19_Lsl21_1,
     305             :   Convert__GPRMM16AsmReg1_0__Imm1_1,
     306             :   Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1,
     307             :   Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2,
     308             :   Convert__GPR32AsmReg1_0__Tie0__ConstantSImm4_01_1,
     309             :   Convert__Imm1_0,
     310             :   Convert__Reg1_0__Reg1_1__Reg1_2,
     311             :   Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2,
     312             :   Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2,
     313             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3,
     314             :   Convert__GPR32AsmReg1_0__SImm161_1,
     315             :   Convert__Reg1_0__Tie0__Reg1_1,
     316             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1,
     317             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1,
     318             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2,
     319             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2,
     320             :   Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0,
     321             :   Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2,
     322             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0,
     323             :   Convert__JumpTarget1_0,
     324             :   Convert__regZERO__regZERO__JumpTarget1_0,
     325             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1,
     326             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2,
     327             :   Convert__regZERO__JumpTarget1_0,
     328             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0,
     329             :   Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2,
     330             :   Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2,
     331             :   Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2,
     332             :   Convert__FGR64AsmReg1_0__JumpTarget1_1,
     333             :   Convert__regFCC0__JumpTarget1_0,
     334             :   Convert__FCCAsmReg1_0__JumpTarget1_1,
     335             :   Convert__COP2AsmReg1_0__JumpTarget1_1,
     336             :   Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2,
     337             :   Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2,
     338             :   Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2,
     339             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2,
     340             :   Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2,
     341             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2,
     342             :   Convert__Reg1_0__JumpTarget1_1,
     343             :   Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1,
     344             :   Convert__GPRMM16AsmReg1_0__JumpTarget1_1,
     345             :   Convert__GPR32AsmReg1_0__JumpTarget1_1,
     346             :   Convert__GPR64AsmReg1_0__JumpTarget1_1,
     347             :   Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2,
     348             :   Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm3_01_2,
     349             :   Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm6_01_2,
     350             :   Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm4_01_2,
     351             :   Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm5_01_2,
     352             :   Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm8_01_2,
     353             :   Convert__MSA128AsmReg1_0__JumpTarget1_1,
     354             :   Convert__imm_95_0__imm_95_0,
     355             :   Convert_NoOperands,
     356             :   Convert__ConstantUImm10_01_0__imm_95_0,
     357             :   Convert__ConstantUImm10_01_0__ConstantUImm10_01_1,
     358             :   Convert__ConstantUImm4_01_0,
     359             :   Convert__SImm161_0,
     360             :   Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1,
     361             :   Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1,
     362             :   Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2,
     363             :   Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
     364             :   Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1,
     365             :   Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,
     366             :   Convert__MemOffsetSimm92_1__ConstantUImm5_01_0,
     367             :   Convert__Mem2_1__ConstantUImm5_01_0,
     368             :   Convert__FGR64AsmReg1_0__FGR32AsmReg1_1,
     369             :   Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1,
     370             :   Convert__FGR32AsmReg1_0__FGR64AsmReg1_1,
     371             :   Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2,
     372             :   Convert__GPR32AsmReg1_0__CCRAsmReg1_1,
     373             :   Convert__GPR32AsmReg1_0__COP2AsmReg1_1,
     374             :   Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1,
     375             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2,
     376             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2,
     377             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3,
     378             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3,
     379             :   Convert__Reg1_0__Reg1_1,
     380             :   Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
     381             :   Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3,
     382             :   Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3,
     383             :   Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3,
     384             :   Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3,
     385             :   Convert__CCRAsmReg1_1__GPR32AsmReg1_0,
     386             :   Convert__COP2AsmReg1_1__GPR32AsmReg1_0,
     387             :   Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1,
     388             :   Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1,
     389             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1,
     390             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2,
     391             :   Convert__GPR64AsmReg1_0__Tie0__UImm16_AltRelaxed1_2,
     392             :   Convert__GPR64AsmReg1_0__Tie0__UImm161_2,
     393             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3,
     394             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2,
     395             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_1,
     396             :   Convert__GPR64AsmReg1_1__GPR64AsmReg1_2,
     397             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_11_3,
     398             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3,
     399             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3,
     400             :   Convert__regZERO,
     401             :   Convert__GPR32AsmReg1_0,
     402             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0,
     403             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0,
     404             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0,
     405             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0,
     406             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1,
     407             :   Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1,
     408             :   Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1,
     409             :   Convert__Reg1_1__Reg1_2,
     410             :   Convert__GPR32AsmReg1_1__GPR32AsmReg1_2,
     411             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2,
     412             :   Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
     413             :   Convert__GPR64AsmReg1_0__Imm1_1,
     414             :   Convert__GPR64AsmReg1_0__Mem2_1,
     415             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3,
     416             :   Convert__GPR64AsmReg1_2__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm2_11_3,
     417             :   Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0,
     418             :   Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2,
     419             :   Convert__GPR64AsmReg1_0__FGR64AsmReg1_1,
     420             :   Convert__GPR64AsmReg1_0__COP2AsmReg1_1,
     421             :   Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0,
     422             :   Convert__GPR64AsmReg1_0__UImm161_1,
     423             :   Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2,
     424             :   Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0,
     425             :   Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2,
     426             :   Convert__FGR64AsmReg1_1__GPR64AsmReg1_0,
     427             :   Convert__COP2AsmReg1_1__GPR64AsmReg1_0,
     428             :   Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0,
     429             :   Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2,
     430             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2,
     431             :   Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0,
     432             :   Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1,
     433             :   Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0,
     434             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_0,
     435             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1,
     436             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2,
     437             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1,
     438             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2,
     439             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2,
     440             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1,
     441             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1,
     442             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2,
     443             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3,
     444             :   Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2,
     445             :   Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2,
     446             :   Convert__MSA128AsmReg1_0__MSA128AsmReg1_1,
     447             :   Convert__MSA128AsmReg1_0__GPR32AsmReg1_1,
     448             :   Convert__MSA128AsmReg1_0__GPR64AsmReg1_1,
     449             :   Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2,
     450             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0,
     451             :   Convert__MSA128AsmReg1_0__Tie0__GPR32AsmReg1_4__ConstantUImm4_01_2,
     452             :   Convert__MSA128AsmReg1_0__Tie0__GPR64AsmReg1_4__ConstantUImm1_01_2,
     453             :   Convert__MSA128AsmReg1_0__Tie0__GPR32AsmReg1_4__ConstantUImm3_01_2,
     454             :   Convert__MSA128AsmReg1_0__Tie0__GPR32AsmReg1_4__ConstantUImm2_01_2,
     455             :   Convert__GPR32AsmReg1_0__Tie0__GPR32AsmReg1_1,
     456             :   Convert__MSA128AsmReg1_0__Tie0__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
     457             :   Convert__MSA128AsmReg1_0__Tie0__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
     458             :   Convert__MSA128AsmReg1_0__Tie0__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
     459             :   Convert__MSA128AsmReg1_0__Tie0__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
     460             :   Convert__regRA__GPR32AsmReg1_0,
     461             :   Convert__Reg1_0,
     462             :   Convert__GPR32AsmReg1_0__imm_95_0,
     463             :   Convert__GPR64AsmReg1_0__imm_95_0,
     464             :   Convert__regZERO__GPR32AsmReg1_0,
     465             :   Convert__GPR64AsmReg1_0,
     466             :   Convert__regZERO_64__GPR64AsmReg1_0,
     467             :   Convert__UImm5Lsl21_0,
     468             :   Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1,
     469             :   Convert__FGR64AsmReg1_0__MemOffsetSimm162_1,
     470             :   Convert__FGR32AsmReg1_0__MemOffsetSimm162_1,
     471             :   Convert__GPR32AsmReg1_0__Imm1_1,
     472             :   Convert__GPR32AsmReg1_0__Mem2_1,
     473             :   Convert__GPR32AsmReg1_0__MemOffsetSimm162_1,
     474             :   Convert__GPR32AsmReg1_0__MemOffsetSimm92_1,
     475             :   Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1,
     476             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
     477             :   Convert__GPR64AsmReg1_0__MemOffsetSimm162_1,
     478             :   Convert__MSA128AsmReg1_0__MemOffsetSimm102_1,
     479             :   Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1,
     480             :   Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1,
     481             :   Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1,
     482             :   Convert__COP2AsmReg1_0__MemOffsetSimm112_1,
     483             :   Convert__COP2AsmReg1_0__MemOffsetSimm162_1,
     484             :   Convert__COP3AsmReg1_0__Mem2_1,
     485             :   Convert__MSA128AsmReg1_0__ConstantSImm10_01_1,
     486             :   Convert__GPR64AsmReg1_0__Mem2_1__Tie0,
     487             :   Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
     488             :   Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
     489             :   Convert__GPR32AsmReg1_0__UImm32_Coerced1_1,
     490             :   Convert__StrictlyAFGR64AsmReg1_0__Imm1_1,
     491             :   Convert__StrictlyFGR64AsmReg1_0__Imm1_1,
     492             :   Convert__StrictlyFGR32AsmReg1_0__Imm1_1,
     493             :   Convert__GPRMM16AsmReg1_0__UImm7_N11_1,
     494             :   Convert__GPR64AsmReg1_0__MemOffsetSimm122_1,
     495             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3,
     496             :   Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3,
     497             :   Convert__GPR32AsmReg1_0__UImm161_1,
     498             :   Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1,
     499             :   Convert__Reg1_0__Imm1_1__imm_95_0,
     500             :   Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1,
     501             :   Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1,
     502             :   Convert__GPR32AsmReg1_0__Mem2_1__Tie0,
     503             :   Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0,
     504             :   Convert__RegList1_0__Mem2_1,
     505             :   Convert__RegList161_0__MemOffsetUimm42_1,
     506             :   Convert__RegPair2_0__MemOffsetSimm122_1,
     507             :   Convert__GPR32AsmReg1_0__MemOffsetSimm122_1,
     508             :   Convert__GPR64AsmReg1_0__Simm19_Lsl21_1,
     509             :   Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
     510             :   Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3,
     511             :   Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3,
     512             :   Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3,
     513             :   Convert__FGR64AsmReg1_0__Tie0__FGR64AsmReg1_1__FGR64AsmReg1_2,
     514             :   Convert__FGR32AsmReg1_0__Tie0__FGR32AsmReg1_1__FGR32AsmReg1_2,
     515             :   Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0,
     516             :   Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2,
     517             :   Convert__GPR32AsmReg1_0__FGR32AsmReg1_1,
     518             :   Convert__GPR32AsmReg1_0__FGR64AsmReg1_1,
     519             :   Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0,
     520             :   Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2,
     521             :   Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1,
     522             :   Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1,
     523             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO,
     524             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64,
     525             :   Convert__MovePRegPair2_0__GPRMM16AsmRegMoveP1_1__GPRMM16AsmRegMoveP1_2,
     526             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0,
     527             :   Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0,
     528             :   Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0,
     529             :   Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0,
     530             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0,
     531             :   Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0,
     532             :   Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0,
     533             :   Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0,
     534             :   Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0,
     535             :   Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2,
     536             :   Convert__FGR32AsmReg1_1__GPR32AsmReg1_0,
     537             :   Convert__FGR64AsmReg1_1__GPR32AsmReg1_0,
     538             :   Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0,
     539             :   Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2,
     540             :   Convert__AFGR64AsmReg1_1__Tie0__GPR32AsmReg1_0,
     541             :   Convert__FGR64AsmReg1_1__Tie0__GPR32AsmReg1_0,
     542             :   Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0,
     543             :   Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0,
     544             :   Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0,
     545             :   Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
     546             :   Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0,
     547             :   Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1,
     548             :   Convert__regZERO__regZERO__imm_95_0,
     549             :   Convert__regZERO__regZERO,
     550             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO,
     551             :   Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1,
     552             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_0,
     553             :   Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0,
     554             :   Convert__GPR32AsmReg1_0__ConstantUImm7_01_1,
     555             :   Convert__GPR32AsmReg1_0__ConstantUImm10_01_1,
     556             :   Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1,
     557             :   Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0,
     558             :   Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2,
     559             :   Convert__GPR32AsmReg1_0__ConstantSImm10_01_1,
     560             :   Convert__GPR32AsmReg1_0__ConstantUImm8_01_1,
     561             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1,
     562             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2,
     563             :   Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1,
     564             :   Convert__GPR32AsmReg1_0__Tie0__MemOffsetSimm92_1,
     565             :   Convert__GPR32AsmReg1_0__Tie0__Mem2_1,
     566             :   Convert__GPR64AsmReg1_0__Tie0__MemOffsetSimm92_1,
     567             :   Convert__GPR64AsmReg1_0__Tie0__Mem2_1,
     568             :   Convert__imm_95_0,
     569             :   Convert__ConstantUImm10_01_0,
     570             :   Convert__ConstantUImm20_01_0,
     571             :   Convert__Reg1_0__Tie0,
     572             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1,
     573             :   Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2,
     574             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0,
     575             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1,
     576             :   Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0,
     577             :   Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0,
     578             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2,
     579             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2,
     580             :   Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__GPR32AsmReg1_3,
     581             :   Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm4_01_3,
     582             :   Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm1_01_3,
     583             :   Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm3_01_3,
     584             :   Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm2_01_3,
     585             :   Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2,
     586             :   Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3,
     587             :   Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3,
     588             :   Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3,
     589             :   Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3,
     590             :   Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3,
     591             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1,
     592             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2,
     593             :   Convert__ConstantUImm5_01_0,
     594             :   Convert__MemOffsetSimm162_0,
     595             :   Convert__imm_95_2,
     596             :   Convert__imm_95_6,
     597             :   Convert__imm_95_4,
     598             :   Convert__imm_95_5,
     599             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0,
     600             :   Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2,
     601             :   Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2,
     602             :   Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2,
     603             :   Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2,
     604             :   Convert__GPR32AsmReg1_0__imm_95_31,
     605             :   CVT_NUM_SIGNATURES
     606             : };
     607             : 
     608             : } // end anonymous namespace
     609             : 
     610             : static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][11] = {
     611             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1
     612             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
     613             :   // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1
     614             :   { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
     615             :   // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1
     616             :   { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
     617             :   // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1
     618             :   { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
     619             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1
     620             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
     621             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1
     622             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
     623             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
     624             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
     625             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2
     626             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
     627             :   // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2
     628             :   { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done },
     629             :   // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_2__AFGR64AsmReg1_1
     630             :   { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 3, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
     631             :   // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
     632             :   { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
     633             :   // Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1
     634             :   { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
     635             :   // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2
     636             :   { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
     637             :   // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2
     638             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done },
     639             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1
     640             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
     641             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1
     642             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
     643             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2
     644             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
     645             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2
     646             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
     647             :   // Convert__SImm161_1
     648             :   { CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
     649             :   // Convert__Reg1_0__SImm161_1
     650             :   { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
     651             :   // Convert__Reg1_0__SImm161_2
     652             :   { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
     653             :   // Convert__Reg1_0__Reg1_1__SImm161_2
     654             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
     655             :   // Convert__Reg1_0__Tie0__SImm161_1
     656             :   { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
     657             :   // Convert__GPR32AsmReg1_0__Simm19_Lsl21_1
     658             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
     659             :   // Convert__GPRMM16AsmReg1_0__Imm1_1
     660             :   { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
     661             :   // Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1
     662             :   { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
     663             :   // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2
     664             :   { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
     665             :   // Convert__GPR32AsmReg1_0__Tie0__ConstantSImm4_01_1
     666             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_, 2, CVT_Done },
     667             :   // Convert__Imm1_0
     668             :   { CVT_95_addImmOperands, 1, CVT_Done },
     669             :   // Convert__Reg1_0__Reg1_1__Reg1_2
     670             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
     671             :   // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2
     672             :   { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addGPRMM16AsmRegOperands, 3, CVT_Done },
     673             :   // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2
     674             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
     675             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3
     676             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
     677             :   // Convert__GPR32AsmReg1_0__SImm161_1
     678             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
     679             :   // Convert__Reg1_0__Tie0__Reg1_1
     680             :   { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 2, CVT_Done },
     681             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1
     682             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
     683             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1
     684             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
     685             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2
     686             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
     687             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2
     688             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
     689             :   // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0
     690             :   { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Tied, 0, CVT_Done },
     691             :   // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2
     692             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
     693             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0
     694             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Tied, 0, CVT_Done },
     695             :   // Convert__JumpTarget1_0
     696             :   { CVT_95_addImmOperands, 1, CVT_Done },
     697             :   // Convert__regZERO__regZERO__JumpTarget1_0
     698             :   { CVT_regZERO, 0, CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done },
     699             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1
     700             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
     701             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2
     702             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done },
     703             :   // Convert__regZERO__JumpTarget1_0
     704             :   { CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done },
     705             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0
     706             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Tied, 0, CVT_Done },
     707             :   // Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2
     708             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
     709             :   // Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2
     710             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
     711             :   // Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2
     712             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
     713             :   // Convert__FGR64AsmReg1_0__JumpTarget1_1
     714             :   { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
     715             :   // Convert__regFCC0__JumpTarget1_0
     716             :   { CVT_regFCC0, 0, CVT_95_addImmOperands, 1, CVT_Done },
     717             :   // Convert__FCCAsmReg1_0__JumpTarget1_1
     718             :   { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
     719             :   // Convert__COP2AsmReg1_0__JumpTarget1_1
     720             :   { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
     721             :   // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2
     722             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
     723             :   // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2
     724             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
     725             :   // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2
     726             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
     727             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2
     728             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
     729             :   // Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2
     730             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
     731             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2
     732             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
     733             :   // Convert__Reg1_0__JumpTarget1_1
     734             :   { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
     735             :   // Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1
     736             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addImmOperands, 2, CVT_Done },
     737             :   // Convert__GPRMM16AsmReg1_0__JumpTarget1_1
     738             :   { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
     739             :   // Convert__GPR32AsmReg1_0__JumpTarget1_1
     740             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
     741             :   // Convert__GPR64AsmReg1_0__JumpTarget1_1
     742             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
     743             :   // Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2
     744             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done },
     745             :   // Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm3_01_2
     746             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
     747             :   // Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm6_01_2
     748             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
     749             :   // Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm4_01_2
     750             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
     751             :   // Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm5_01_2
     752             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
     753             :   // Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm8_01_2
     754             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
     755             :   // Convert__MSA128AsmReg1_0__JumpTarget1_1
     756             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
     757             :   // Convert__imm_95_0__imm_95_0
     758             :   { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
     759             :   // Convert_NoOperands
     760             :   { CVT_Done },
     761             :   // Convert__ConstantUImm10_01_0__imm_95_0
     762             :   { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_imm_95_0, 0, CVT_Done },
     763             :   // Convert__ConstantUImm10_01_0__ConstantUImm10_01_1
     764             :   { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
     765             :   // Convert__ConstantUImm4_01_0
     766             :   { CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 1, CVT_Done },
     767             :   // Convert__SImm161_0
     768             :   { CVT_95_addSImmOperands_LT_16_GT_, 1, CVT_Done },
     769             :   // Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1
     770             :   { CVT_regFCC0, 0, CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
     771             :   // Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1
     772             :   { CVT_regFCC0, 0, CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
     773             :   // Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2
     774             :   { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done },
     775             :   // Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
     776             :   { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
     777             :   // Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1
     778             :   { CVT_regFCC0, 0, CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
     779             :   // Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2
     780             :   { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
     781             :   // Convert__MemOffsetSimm92_1__ConstantUImm5_01_0
     782             :   { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
     783             :   // Convert__Mem2_1__ConstantUImm5_01_0
     784             :   { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
     785             :   // Convert__FGR64AsmReg1_0__FGR32AsmReg1_1
     786             :   { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
     787             :   // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1
     788             :   { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
     789             :   // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1
     790             :   { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
     791             :   // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2
     792             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
     793             :   // Convert__GPR32AsmReg1_0__CCRAsmReg1_1
     794             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCCRAsmRegOperands, 2, CVT_Done },
     795             :   // Convert__GPR32AsmReg1_0__COP2AsmReg1_1
     796             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_Done },
     797             :   // Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1
     798             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSACtrlAsmRegOperands, 2, CVT_Done },
     799             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2
     800             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
     801             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2
     802             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
     803             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3
     804             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done },
     805             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3
     806             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done },
     807             :   // Convert__Reg1_0__Reg1_1
     808             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
     809             :   // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
     810             :   { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
     811             :   // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3
     812             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
     813             :   // Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3
     814             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
     815             :   // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3
     816             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
     817             :   // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3
     818             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
     819             :   // Convert__CCRAsmReg1_1__GPR32AsmReg1_0
     820             :   { CVT_95_addCCRAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
     821             :   // Convert__COP2AsmReg1_1__GPR32AsmReg1_0
     822             :   { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
     823             :   // Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1
     824             :   { CVT_95_addMSACtrlAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
     825             :   // Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1
     826             :   { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
     827             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1
     828             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
     829             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2
     830             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
     831             :   // Convert__GPR64AsmReg1_0__Tie0__UImm16_AltRelaxed1_2
     832             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
     833             :   // Convert__GPR64AsmReg1_0__Tie0__UImm161_2
     834             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
     835             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3
     836             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
     837             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2
     838             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
     839             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1
     840             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
     841             :   // Convert__GPR64AsmReg1_1__GPR64AsmReg1_2
     842             :   { CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done },
     843             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_11_3
     844             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
     845             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3
     846             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_, 4, CVT_Done },
     847             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3
     848             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
     849             :   // Convert__regZERO
     850             :   { CVT_regZERO, 0, CVT_Done },
     851             :   // Convert__GPR32AsmReg1_0
     852             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
     853             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0
     854             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, 0, CVT_Done },
     855             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0
     856             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, 0, CVT_Done },
     857             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0
     858             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addImmOperands, 4, CVT_Tied, 0, CVT_Done },
     859             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0
     860             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, 0, CVT_Done },
     861             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1
     862             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
     863             :   // Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1
     864             :   { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
     865             :   // Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1
     866             :   { CVT_95_addGPR32ZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
     867             :   // Convert__Reg1_1__Reg1_2
     868             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
     869             :   // Convert__GPR32AsmReg1_1__GPR32AsmReg1_2
     870             :   { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
     871             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2
     872             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
     873             :   // Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
     874             :   { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
     875             :   // Convert__GPR64AsmReg1_0__Imm1_1
     876             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
     877             :   // Convert__GPR64AsmReg1_0__Mem2_1
     878             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
     879             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3
     880             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
     881             :   // Convert__GPR64AsmReg1_2__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm2_11_3
     882             :   { CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
     883             :   // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0
     884             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
     885             :   // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2
     886             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
     887             :   // Convert__GPR64AsmReg1_0__FGR64AsmReg1_1
     888             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
     889             :   // Convert__GPR64AsmReg1_0__COP2AsmReg1_1
     890             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_Done },
     891             :   // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0
     892             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
     893             :   // Convert__GPR64AsmReg1_0__UImm161_1
     894             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
     895             :   // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2
     896             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
     897             :   // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0
     898             :   { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
     899             :   // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2
     900             :   { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
     901             :   // Convert__FGR64AsmReg1_1__GPR64AsmReg1_0
     902             :   { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
     903             :   // Convert__COP2AsmReg1_1__GPR64AsmReg1_0
     904             :   { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
     905             :   // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0
     906             :   { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
     907             :   // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2
     908             :   { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
     909             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2
     910             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
     911             :   // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0
     912             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
     913             :   // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1
     914             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
     915             :   // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0
     916             :   { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, 0, CVT_Done },
     917             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0
     918             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
     919             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1
     920             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 2, CVT_Done },
     921             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2
     922             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
     923             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1
     924             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done },
     925             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2
     926             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
     927             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2
     928             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
     929             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1
     930             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
     931             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1
     932             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
     933             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2
     934             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
     935             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3
     936             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
     937             :   // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2
     938             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
     939             :   // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2
     940             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
     941             :   // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1
     942             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_Done },
     943             :   // Convert__MSA128AsmReg1_0__GPR32AsmReg1_1
     944             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
     945             :   // Convert__MSA128AsmReg1_0__GPR64AsmReg1_1
     946             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
     947             :   // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2
     948             :   { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
     949             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0
     950             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, 0, CVT_Done },
     951             :   // Convert__MSA128AsmReg1_0__Tie0__GPR32AsmReg1_4__ConstantUImm4_01_2
     952             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
     953             :   // Convert__MSA128AsmReg1_0__Tie0__GPR64AsmReg1_4__ConstantUImm1_01_2
     954             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addGPR64AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_Done },
     955             :   // Convert__MSA128AsmReg1_0__Tie0__GPR32AsmReg1_4__ConstantUImm3_01_2
     956             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
     957             :   // Convert__MSA128AsmReg1_0__Tie0__GPR32AsmReg1_4__ConstantUImm2_01_2
     958             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Done },
     959             :   // Convert__GPR32AsmReg1_0__Tie0__GPR32AsmReg1_1
     960             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
     961             :   // Convert__MSA128AsmReg1_0__Tie0__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6
     962             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
     963             :   // Convert__MSA128AsmReg1_0__Tie0__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6
     964             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
     965             :   // Convert__MSA128AsmReg1_0__Tie0__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6
     966             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
     967             :   // Convert__MSA128AsmReg1_0__Tie0__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6
     968             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
     969             :   // Convert__regRA__GPR32AsmReg1_0
     970             :   { CVT_regRA, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
     971             :   // Convert__Reg1_0
     972             :   { CVT_95_Reg, 1, CVT_Done },
     973             :   // Convert__GPR32AsmReg1_0__imm_95_0
     974             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
     975             :   // Convert__GPR64AsmReg1_0__imm_95_0
     976             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
     977             :   // Convert__regZERO__GPR32AsmReg1_0
     978             :   { CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
     979             :   // Convert__GPR64AsmReg1_0
     980             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
     981             :   // Convert__regZERO_64__GPR64AsmReg1_0
     982             :   { CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
     983             :   // Convert__UImm5Lsl21_0
     984             :   { CVT_95_addImmOperands, 1, CVT_Done },
     985             :   // Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1
     986             :   { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
     987             :   // Convert__FGR64AsmReg1_0__MemOffsetSimm162_1
     988             :   { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
     989             :   // Convert__FGR32AsmReg1_0__MemOffsetSimm162_1
     990             :   { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
     991             :   // Convert__GPR32AsmReg1_0__Imm1_1
     992             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
     993             :   // Convert__GPR32AsmReg1_0__Mem2_1
     994             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
     995             :   // Convert__GPR32AsmReg1_0__MemOffsetSimm162_1
     996             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
     997             :   // Convert__GPR32AsmReg1_0__MemOffsetSimm92_1
     998             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
     999             :   // Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1
    1000             :   { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done },
    1001             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
    1002             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
    1003             :   // Convert__GPR64AsmReg1_0__MemOffsetSimm162_1
    1004             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
    1005             :   // Convert__MSA128AsmReg1_0__MemOffsetSimm102_1
    1006             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
    1007             :   // Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1
    1008             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
    1009             :   // Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1
    1010             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
    1011             :   // Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1
    1012             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
    1013             :   // Convert__COP2AsmReg1_0__MemOffsetSimm112_1
    1014             :   { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
    1015             :   // Convert__COP2AsmReg1_0__MemOffsetSimm162_1
    1016             :   { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
    1017             :   // Convert__COP3AsmReg1_0__Mem2_1
    1018             :   { CVT_95_addCOP3AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
    1019             :   // Convert__MSA128AsmReg1_0__ConstantSImm10_01_1
    1020             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
    1021             :   // Convert__GPR64AsmReg1_0__Mem2_1__Tie0
    1022             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, 0, CVT_Done },
    1023             :   // Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
    1024             :   { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
    1025             :   // Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
    1026             :   { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
    1027             :   // Convert__GPR32AsmReg1_0__UImm32_Coerced1_1
    1028             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_32_GT_, 2, CVT_Done },
    1029             :   // Convert__StrictlyAFGR64AsmReg1_0__Imm1_1
    1030             :   { CVT_95_addStrictlyAFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
    1031             :   // Convert__StrictlyFGR64AsmReg1_0__Imm1_1
    1032             :   { CVT_95_addStrictlyFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
    1033             :   // Convert__StrictlyFGR32AsmReg1_0__Imm1_1
    1034             :   { CVT_95_addStrictlyFGR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
    1035             :   // Convert__GPRMM16AsmReg1_0__UImm7_N11_1
    1036             :   { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_, 2, CVT_Done },
    1037             :   // Convert__GPR64AsmReg1_0__MemOffsetSimm122_1
    1038             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
    1039             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3
    1040             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
    1041             :   // Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3
    1042             :   { CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
    1043             :   // Convert__GPR32AsmReg1_0__UImm161_1
    1044             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
    1045             :   // Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1
    1046             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
    1047             :   // Convert__Reg1_0__Imm1_1__imm_95_0
    1048             :   { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
    1049             :   // Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1
    1050             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
    1051             :   // Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1
    1052             :   { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
    1053             :   // Convert__GPR32AsmReg1_0__Mem2_1__Tie0
    1054             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, 0, CVT_Done },
    1055             :   // Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0
    1056             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, 0, CVT_Done },
    1057             :   // Convert__RegList1_0__Mem2_1
    1058             :   { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
    1059             :   // Convert__RegList161_0__MemOffsetUimm42_1
    1060             :   { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
    1061             :   // Convert__RegPair2_0__MemOffsetSimm122_1
    1062             :   { CVT_95_addRegPairOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
    1063             :   // Convert__GPR32AsmReg1_0__MemOffsetSimm122_1
    1064             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
    1065             :   // Convert__GPR64AsmReg1_0__Simm19_Lsl21_1
    1066             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
    1067             :   // Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
    1068             :   { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
    1069             :   // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3
    1070             :   { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_95_addAFGR64AsmRegOperands, 4, CVT_Done },
    1071             :   // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3
    1072             :   { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_95_addFGR64AsmRegOperands, 4, CVT_Done },
    1073             :   // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3
    1074             :   { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 4, CVT_Done },
    1075             :   // Convert__FGR64AsmReg1_0__Tie0__FGR64AsmReg1_1__FGR64AsmReg1_2
    1076             :   { CVT_95_addFGR64AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
    1077             :   // Convert__FGR32AsmReg1_0__Tie0__FGR32AsmReg1_1__FGR32AsmReg1_2
    1078             :   { CVT_95_addFGR32AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
    1079             :   // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0
    1080             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
    1081             :   // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2
    1082             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
    1083             :   // Convert__GPR32AsmReg1_0__FGR32AsmReg1_1
    1084             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
    1085             :   // Convert__GPR32AsmReg1_0__FGR64AsmReg1_1
    1086             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
    1087             :   // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0
    1088             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
    1089             :   // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2
    1090             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
    1091             :   // Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1
    1092             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
    1093             :   // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1
    1094             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_Done },
    1095             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO
    1096             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_regZERO, 0, CVT_Done },
    1097             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64
    1098             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_regZERO_64, 0, CVT_Done },
    1099             :   // Convert__MovePRegPair2_0__GPRMM16AsmRegMoveP1_1__GPRMM16AsmRegMoveP1_2
    1100             :   { CVT_95_addMovePRegPairOperands, 1, CVT_95_addGPRMM16AsmRegMovePOperands, 2, CVT_95_addGPRMM16AsmRegMovePOperands, 3, CVT_Done },
    1101             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0
    1102             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, 0, CVT_Done },
    1103             :   // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0
    1104             :   { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, 0, CVT_Done },
    1105             :   // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0
    1106             :   { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, 0, CVT_Done },
    1107             :   // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0
    1108             :   { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, 0, CVT_Done },
    1109             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0
    1110             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, 0, CVT_Done },
    1111             :   // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0
    1112             :   { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, 0, CVT_Done },
    1113             :   // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0
    1114             :   { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, 0, CVT_Done },
    1115             :   // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0
    1116             :   { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, 0, CVT_Done },
    1117             :   // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0
    1118             :   { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
    1119             :   // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2
    1120             :   { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
    1121             :   // Convert__FGR32AsmReg1_1__GPR32AsmReg1_0
    1122             :   { CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
    1123             :   // Convert__FGR64AsmReg1_1__GPR32AsmReg1_0
    1124             :   { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
    1125             :   // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0
    1126             :   { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
    1127             :   // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2
    1128             :   { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
    1129             :   // Convert__AFGR64AsmReg1_1__Tie0__GPR32AsmReg1_0
    1130             :   { CVT_95_addAFGR64AsmRegOperands, 2, CVT_Tied, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
    1131             :   // Convert__FGR64AsmReg1_1__Tie0__GPR32AsmReg1_0
    1132             :   { CVT_95_addFGR64AsmRegOperands, 2, CVT_Tied, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
    1133             :   // Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0
    1134             :   { CVT_95_addHI32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
    1135             :   // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0
    1136             :   { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, 0, CVT_Done },
    1137             :   // Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0
    1138             :   { CVT_95_addLO32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
    1139             :   // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
    1140             :   { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
    1141             :   // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0
    1142             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
    1143             :   // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1
    1144             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
    1145             :   // Convert__regZERO__regZERO__imm_95_0
    1146             :   { CVT_regZERO, 0, CVT_regZERO, 0, CVT_imm_95_0, 0, CVT_Done },
    1147             :   // Convert__regZERO__regZERO
    1148             :   { CVT_regZERO, 0, CVT_regZERO, 0, CVT_Done },
    1149             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO
    1150             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_Done },
    1151             :   // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1
    1152             :   { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Done },
    1153             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0
    1154             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
    1155             :   // Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0
    1156             :   { CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
    1157             :   // Convert__GPR32AsmReg1_0__ConstantUImm7_01_1
    1158             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_, 2, CVT_Done },
    1159             :   // Convert__GPR32AsmReg1_0__ConstantUImm10_01_1
    1160             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
    1161             :   // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1
    1162             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_Done },
    1163             :   // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0
    1164             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
    1165             :   // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2
    1166             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
    1167             :   // Convert__GPR32AsmReg1_0__ConstantSImm10_01_1
    1168             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
    1169             :   // Convert__GPR32AsmReg1_0__ConstantUImm8_01_1
    1170             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 2, CVT_Done },
    1171             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1
    1172             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done },
    1173             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2
    1174             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
    1175             :   // Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1
    1176             :   { CVT_95_addGPRMM16AsmRegZeroOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done },
    1177             :   // Convert__GPR32AsmReg1_0__Tie0__MemOffsetSimm92_1
    1178             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_Done },
    1179             :   // Convert__GPR32AsmReg1_0__Tie0__Mem2_1
    1180             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_Done },
    1181             :   // Convert__GPR64AsmReg1_0__Tie0__MemOffsetSimm92_1
    1182             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_Done },
    1183             :   // Convert__GPR64AsmReg1_0__Tie0__Mem2_1
    1184             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_Done },
    1185             :   // Convert__imm_95_0
    1186             :   { CVT_imm_95_0, 0, CVT_Done },
    1187             :   // Convert__ConstantUImm10_01_0
    1188             :   { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_Done },
    1189             :   // Convert__ConstantUImm20_01_0
    1190             :   { CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_, 1, CVT_Done },
    1191             :   // Convert__Reg1_0__Tie0
    1192             :   { CVT_95_Reg, 1, CVT_Tied, 0, CVT_Done },
    1193             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1
    1194             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
    1195             :   // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2
    1196             :   { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done },
    1197             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0
    1198             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
    1199             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1
    1200             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
    1201             :   // Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0
    1202             :   { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_, 2, CVT_Tied, 0, CVT_Done },
    1203             :   // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0
    1204             :   { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Tied, 0, CVT_Done },
    1205             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2
    1206             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
    1207             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2
    1208             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
    1209             :   // Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__GPR32AsmReg1_3
    1210             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done },
    1211             :   // Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm4_01_3
    1212             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
    1213             :   // Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm1_01_3
    1214             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
    1215             :   // Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm3_01_3
    1216             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
    1217             :   // Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm2_01_3
    1218             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
    1219             :   // Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2
    1220             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
    1221             :   // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3
    1222             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done },
    1223             :   // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3
    1224             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
    1225             :   // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3
    1226             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
    1227             :   // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3
    1228             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
    1229             :   // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3
    1230             :   { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
    1231             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1
    1232             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
    1233             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2
    1234             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
    1235             :   // Convert__ConstantUImm5_01_0
    1236             :   { CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
    1237             :   // Convert__MemOffsetSimm162_0
    1238             :   { CVT_95_addMemOperands, 1, CVT_Done },
    1239             :   // Convert__imm_95_2
    1240             :   { CVT_imm_95_2, 0, CVT_Done },
    1241             :   // Convert__imm_95_6
    1242             :   { CVT_imm_95_6, 0, CVT_Done },
    1243             :   // Convert__imm_95_4
    1244             :   { CVT_imm_95_4, 0, CVT_Done },
    1245             :   // Convert__imm_95_5
    1246             :   { CVT_imm_95_5, 0, CVT_Done },
    1247             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0
    1248             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
    1249             :   // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2
    1250             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done },
    1251             :   // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2
    1252             :   { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
    1253             :   // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2
    1254             :   { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
    1255             :   // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2
    1256             :   { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
    1257             :   // Convert__GPR32AsmReg1_0__imm_95_31
    1258             :   { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_31, 0, CVT_Done },
    1259             : };
    1260             : 
    1261       15377 : void MipsAsmParser::
    1262             : convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
    1263             :                 const OperandVector &Operands) {
    1264             :   assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
    1265       15377 :   const uint8_t *Converter = ConversionTable[Kind];
    1266             :   unsigned OpIdx;
    1267       30754 :   Inst.setOpcode(Opcode);
    1268       52894 :   for (const uint8_t *p = Converter; *p; p+= 2) {
    1269       37517 :     OpIdx = *(p + 1);
    1270       37517 :     switch (*p) {
    1271           0 :     default: llvm_unreachable("invalid conversion entry!");
    1272           0 :     case CVT_Reg:
    1273           0 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
    1274             :       break;
    1275         640 :     case CVT_Tied:
    1276         640 :       Inst.addOperand(Inst.getOperand(OpIdx));
    1277             :       break;
    1278       13402 :     case CVT_95_addGPR32AsmRegOperands:
    1279       40206 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32AsmRegOperands(Inst, 1);
    1280             :       break;
    1281         861 :     case CVT_95_addAFGR64AsmRegOperands:
    1282        2583 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addAFGR64AsmRegOperands(Inst, 1);
    1283             :       break;
    1284        1241 :     case CVT_95_addFGR64AsmRegOperands:
    1285        3723 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addFGR64AsmRegOperands(Inst, 1);
    1286             :       break;
    1287        2532 :     case CVT_95_addFGR32AsmRegOperands:
    1288        7596 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addFGR32AsmRegOperands(Inst, 1);
    1289             :       break;
    1290         354 :     case CVT_95_addSImmOperands_LT_32_GT_:
    1291        1062 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addSImmOperands<32>(Inst, 1);
    1292             :       break;
    1293        1409 :     case CVT_95_addMSA128AsmRegOperands:
    1294        4227 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addMSA128AsmRegOperands(Inst, 1);
    1295             :       break;
    1296        1259 :     case CVT_95_addSImmOperands_LT_16_GT_:
    1297        3777 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addSImmOperands<16>(Inst, 1);
    1298             :       break;
    1299           0 :     case CVT_95_Reg:
    1300           0 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
    1301             :       break;
    1302        3688 :     case CVT_95_addImmOperands:
    1303       11064 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
    1304             :       break;
    1305         214 :     case CVT_95_addGPRMM16AsmRegOperands:
    1306         642 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegOperands(Inst, 1);
    1307             :       break;
    1308           5 :     case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_:
    1309          15 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<4, 0>(Inst, 1);
    1310             :       break;
    1311         445 :     case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_:
    1312        1335 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 0>(Inst, 1);
    1313             :       break;
    1314          10 :     case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_:
    1315          30 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<2, 0>(Inst, 1);
    1316             :       break;
    1317         209 :     case CVT_95_addUImmOperands_LT_16_GT_:
    1318         627 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addUImmOperands<16>(Inst, 1);
    1319             :       break;
    1320        3656 :     case CVT_95_addGPR64AsmRegOperands:
    1321       10968 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR64AsmRegOperands(Inst, 1);
    1322             :       break;
    1323          13 :     case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_:
    1324          39 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<8, 0>(Inst, 1);
    1325             :       break;
    1326        1458 :     case CVT_regZERO:
    1327        2916 :       Inst.addOperand(MCOperand::createReg(Mips::ZERO));
    1328             :       break;
    1329           6 :     case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_:
    1330          18 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 32, -32>(Inst, 1);
    1331             :       break;
    1332         218 :     case CVT_regFCC0:
    1333         436 :       Inst.addOperand(MCOperand::createReg(Mips::FCC0));
    1334             :       break;
    1335         734 :     case CVT_95_addFCCAsmRegOperands:
    1336        2202 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addFCCAsmRegOperands(Inst, 1);
    1337             :       break;
    1338         132 :     case CVT_95_addCOP2AsmRegOperands:
    1339         396 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP2AsmRegOperands(Inst, 1);
    1340             :       break;
    1341          90 :     case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_:
    1342         270 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<3, 0>(Inst, 1);
    1343             :       break;
    1344          73 :     case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_:
    1345         219 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<6, 0>(Inst, 1);
    1346             :       break;
    1347          70 :     case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_:
    1348         210 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<4, 0>(Inst, 1);
    1349             :       break;
    1350         789 :     case CVT_imm_95_0:
    1351        1578 :       Inst.addOperand(MCOperand::createImm(0));
    1352             :       break;
    1353         130 :     case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_:
    1354         390 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<10, 0>(Inst, 1);
    1355             :       break;
    1356        2616 :     case CVT_95_addMemOperands:
    1357        7848 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addMemOperands(Inst, 2);
    1358             :       break;
    1359          20 :     case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_:
    1360          60 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<5, 0>(Inst, 1);
    1361             :       break;
    1362          40 :     case CVT_95_addCCRAsmRegOperands:
    1363         120 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addCCRAsmRegOperands(Inst, 1);
    1364             :       break;
    1365          32 :     case CVT_95_addMSACtrlAsmRegOperands:
    1366          96 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addMSACtrlAsmRegOperands(Inst, 1);
    1367             :       break;
    1368           5 :     case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_:
    1369          15 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<1, 0>(Inst, 1);
    1370             :       break;
    1371          14 :     case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_:
    1372          42 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 1>(Inst, 1);
    1373             :       break;
    1374           2 :     case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_:
    1375           6 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 33>(Inst, 1);
    1376             :       break;
    1377           4 :     case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_:
    1378          12 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 32>(Inst, 1);
    1379             :       break;
    1380          50 :     case CVT_95_addGPR32NonZeroAsmRegOperands:
    1381         150 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32NonZeroAsmRegOperands(Inst, 1);
    1382             :       break;
    1383          16 :     case CVT_95_addGPR32ZeroAsmRegOperands:
    1384          48 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32ZeroAsmRegOperands(Inst, 1);
    1385             :       break;
    1386          13 :     case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_:
    1387          39 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<2, 1>(Inst, 1);
    1388             :       break;
    1389          72 :     case CVT_95_addCOP0AsmRegOperands:
    1390         216 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP0AsmRegOperands(Inst, 1);
    1391             :       break;
    1392          91 :     case CVT_regZERO_64:
    1393         182 :       Inst.addOperand(MCOperand::createReg(Mips::ZERO_64));
    1394             :       break;
    1395         156 :     case CVT_95_addACC64DSPAsmRegOperands:
    1396         468 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addACC64DSPAsmRegOperands(Inst, 1);
    1397             :       break;
    1398           4 :     case CVT_95_addConstantUImmOperands_LT_1_GT_:
    1399          12 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<1>(Inst, 1);
    1400             :       break;
    1401          41 :     case CVT_regRA:
    1402          82 :       Inst.addOperand(MCOperand::createReg(Mips::RA));
    1403             :       break;
    1404          67 :     case CVT_95_addMicroMipsMemOperands:
    1405         201 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addMicroMipsMemOperands(Inst, 2);
    1406             :       break;
    1407           6 :     case CVT_95_addCOP3AsmRegOperands:
    1408          18 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP3AsmRegOperands(Inst, 1);
    1409             :       break;
    1410          12 :     case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_:
    1411          36 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<10, 0>(Inst, 1);
    1412             :       break;
    1413         206 :     case CVT_95_addConstantUImmOperands_LT_32_GT_:
    1414         618 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<32>(Inst, 1);
    1415             :       break;
    1416          39 :     case CVT_95_addStrictlyAFGR64AsmRegOperands:
    1417         117 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyAFGR64AsmRegOperands(Inst, 1);
    1418             :       break;
    1419          52 :     case CVT_95_addStrictlyFGR64AsmRegOperands:
    1420         156 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyFGR64AsmRegOperands(Inst, 1);
    1421             :       break;
    1422          66 :     case CVT_95_addStrictlyFGR32AsmRegOperands:
    1423         198 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyFGR32AsmRegOperands(Inst, 1);
    1424             :       break;
    1425           8 :     case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_:
    1426          24 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<7, -1>(Inst, 1);
    1427             :       break;
    1428          81 :     case CVT_95_addRegListOperands:
    1429         243 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addRegListOperands(Inst, 1);
    1430             :       break;
    1431          15 :     case CVT_95_addRegPairOperands:
    1432          45 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addRegPairOperands(Inst, 2);
    1433             :       break;
    1434           5 :     case CVT_95_addMovePRegPairOperands:
    1435          15 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addMovePRegPairOperands(Inst, 2);
    1436             :       break;
    1437          10 :     case CVT_95_addGPRMM16AsmRegMovePOperands:
    1438          30 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegMovePOperands(Inst, 1);
    1439             :       break;
    1440           3 :     case CVT_95_addHI32DSPAsmRegOperands:
    1441           9 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addHI32DSPAsmRegOperands(Inst, 1);
    1442             :       break;
    1443           3 :     case CVT_95_addLO32DSPAsmRegOperands:
    1444           9 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addLO32DSPAsmRegOperands(Inst, 1);
    1445             :       break;
    1446           5 :     case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_:
    1447          15 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<7, 0>(Inst, 1);
    1448             :       break;
    1449          57 :     case CVT_95_addHWRegsAsmRegOperands:
    1450         171 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addHWRegsAsmRegOperands(Inst, 1);
    1451             :       break;
    1452          29 :     case CVT_95_addGPRMM16AsmRegZeroOperands:
    1453          87 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegZeroOperands(Inst, 1);
    1454             :       break;
    1455          25 :     case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_:
    1456          75 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<20, 0>(Inst, 1);
    1457             :       break;
    1458           6 :     case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_:
    1459          18 :       static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<6, 0>(Inst, 1);
    1460             :       break;
    1461           1 :     case CVT_imm_95_2:
    1462           2 :       Inst.addOperand(MCOperand::createImm(2));
    1463             :       break;
    1464           1 :     case CVT_imm_95_6:
    1465           2 :       Inst.addOperand(MCOperand::createImm(6));
    1466             :       break;
    1467           1 :     case CVT_imm_95_4:
    1468           2 :       Inst.addOperand(MCOperand::createImm(4));
    1469             :       break;
    1470           1 :     case CVT_imm_95_5:
    1471           2 :       Inst.addOperand(MCOperand::createImm(5));
    1472             :       break;
    1473           4 :     case CVT_imm_95_31:
    1474           8 :       Inst.addOperand(MCOperand::createImm(31));
    1475             :       break;
    1476             :     }
    1477             :   }
    1478       15377 : }
    1479             : 
    1480           0 : void MipsAsmParser::
    1481             : convertToMapAndConstraints(unsigned Kind,
    1482             :                            const OperandVector &Operands) {
    1483             :   assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
    1484           0 :   unsigned NumMCOperands = 0;
    1485           0 :   const uint8_t *Converter = ConversionTable[Kind];
    1486           0 :   for (const uint8_t *p = Converter; *p; p+= 2) {
    1487           0 :     switch (*p) {
    1488           0 :     default: llvm_unreachable("invalid conversion entry!");
    1489           0 :     case CVT_Reg:
    1490           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1491           0 :       Operands[*(p + 1)]->setConstraint("r");
    1492           0 :       ++NumMCOperands;
    1493           0 :       break;
    1494           0 :     case CVT_Tied:
    1495           0 :       ++NumMCOperands;
    1496           0 :       break;
    1497           0 :     case CVT_95_addGPR32AsmRegOperands:
    1498           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1499           0 :       Operands[*(p + 1)]->setConstraint("m");
    1500           0 :       NumMCOperands += 1;
    1501           0 :       break;
    1502           0 :     case CVT_95_addAFGR64AsmRegOperands:
    1503           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1504           0 :       Operands[*(p + 1)]->setConstraint("m");
    1505           0 :       NumMCOperands += 1;
    1506           0 :       break;
    1507           0 :     case CVT_95_addFGR64AsmRegOperands:
    1508           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1509           0 :       Operands[*(p + 1)]->setConstraint("m");
    1510           0 :       NumMCOperands += 1;
    1511           0 :       break;
    1512           0 :     case CVT_95_addFGR32AsmRegOperands:
    1513           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1514           0 :       Operands[*(p + 1)]->setConstraint("m");
    1515           0 :       NumMCOperands += 1;
    1516           0 :       break;
    1517           0 :     case CVT_95_addSImmOperands_LT_32_GT_:
    1518           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1519           0 :       Operands[*(p + 1)]->setConstraint("m");
    1520           0 :       NumMCOperands += 1;
    1521           0 :       break;
    1522           0 :     case CVT_95_addMSA128AsmRegOperands:
    1523           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1524           0 :       Operands[*(p + 1)]->setConstraint("m");
    1525           0 :       NumMCOperands += 1;
    1526           0 :       break;
    1527           0 :     case CVT_95_addSImmOperands_LT_16_GT_:
    1528           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1529           0 :       Operands[*(p + 1)]->setConstraint("m");
    1530           0 :       NumMCOperands += 1;
    1531           0 :       break;
    1532           0 :     case CVT_95_Reg:
    1533           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1534           0 :       Operands[*(p + 1)]->setConstraint("r");
    1535           0 :       NumMCOperands += 1;
    1536           0 :       break;
    1537           0 :     case CVT_95_addImmOperands:
    1538           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1539           0 :       Operands[*(p + 1)]->setConstraint("m");
    1540           0 :       NumMCOperands += 1;
    1541           0 :       break;
    1542           0 :     case CVT_95_addGPRMM16AsmRegOperands:
    1543           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1544           0 :       Operands[*(p + 1)]->setConstraint("m");
    1545           0 :       NumMCOperands += 1;
    1546           0 :       break;
    1547           0 :     case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_:
    1548           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1549           0 :       Operands[*(p + 1)]->setConstraint("m");
    1550           0 :       NumMCOperands += 1;
    1551           0 :       break;
    1552           0 :     case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_:
    1553           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1554           0 :       Operands[*(p + 1)]->setConstraint("m");
    1555           0 :       NumMCOperands += 1;
    1556           0 :       break;
    1557           0 :     case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_:
    1558           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1559           0 :       Operands[*(p + 1)]->setConstraint("m");
    1560           0 :       NumMCOperands += 1;
    1561           0 :       break;
    1562           0 :     case CVT_95_addUImmOperands_LT_16_GT_:
    1563           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1564           0 :       Operands[*(p + 1)]->setConstraint("m");
    1565           0 :       NumMCOperands += 1;
    1566           0 :       break;
    1567           0 :     case CVT_95_addGPR64AsmRegOperands:
    1568           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1569           0 :       Operands[*(p + 1)]->setConstraint("m");
    1570           0 :       NumMCOperands += 1;
    1571           0 :       break;
    1572           0 :     case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_:
    1573           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1574           0 :       Operands[*(p + 1)]->setConstraint("m");
    1575           0 :       NumMCOperands += 1;
    1576           0 :       break;
    1577           0 :     case CVT_regZERO:
    1578           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1579           0 :       Operands[*(p + 1)]->setConstraint("m");
    1580           0 :       ++NumMCOperands;
    1581           0 :       break;
    1582           0 :     case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_:
    1583           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1584           0 :       Operands[*(p + 1)]->setConstraint("m");
    1585           0 :       NumMCOperands += 1;
    1586           0 :       break;
    1587           0 :     case CVT_regFCC0:
    1588           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1589           0 :       Operands[*(p + 1)]->setConstraint("m");
    1590           0 :       ++NumMCOperands;
    1591           0 :       break;
    1592           0 :     case CVT_95_addFCCAsmRegOperands:
    1593           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1594           0 :       Operands[*(p + 1)]->setConstraint("m");
    1595           0 :       NumMCOperands += 1;
    1596           0 :       break;
    1597           0 :     case CVT_95_addCOP2AsmRegOperands:
    1598           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1599           0 :       Operands[*(p + 1)]->setConstraint("m");
    1600           0 :       NumMCOperands += 1;
    1601           0 :       break;
    1602           0 :     case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_:
    1603           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1604           0 :       Operands[*(p + 1)]->setConstraint("m");
    1605           0 :       NumMCOperands += 1;
    1606           0 :       break;
    1607           0 :     case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_:
    1608           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1609           0 :       Operands[*(p + 1)]->setConstraint("m");
    1610           0 :       NumMCOperands += 1;
    1611           0 :       break;
    1612           0 :     case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_:
    1613           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1614           0 :       Operands[*(p + 1)]->setConstraint("m");
    1615           0 :       NumMCOperands += 1;
    1616           0 :       break;
    1617           0 :     case CVT_imm_95_0:
    1618           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1619           0 :       Operands[*(p + 1)]->setConstraint("");
    1620           0 :       ++NumMCOperands;
    1621           0 :       break;
    1622           0 :     case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_:
    1623           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1624           0 :       Operands[*(p + 1)]->setConstraint("m");
    1625           0 :       NumMCOperands += 1;
    1626           0 :       break;
    1627           0 :     case CVT_95_addMemOperands:
    1628           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1629           0 :       Operands[*(p + 1)]->setConstraint("m");
    1630           0 :       NumMCOperands += 2;
    1631           0 :       break;
    1632           0 :     case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_:
    1633           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1634           0 :       Operands[*(p + 1)]->setConstraint("m");
    1635           0 :       NumMCOperands += 1;
    1636           0 :       break;
    1637           0 :     case CVT_95_addCCRAsmRegOperands:
    1638           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1639           0 :       Operands[*(p + 1)]->setConstraint("m");
    1640           0 :       NumMCOperands += 1;
    1641           0 :       break;
    1642           0 :     case CVT_95_addMSACtrlAsmRegOperands:
    1643           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1644           0 :       Operands[*(p + 1)]->setConstraint("m");
    1645           0 :       NumMCOperands += 1;
    1646           0 :       break;
    1647           0 :     case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_:
    1648           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1649           0 :       Operands[*(p + 1)]->setConstraint("m");
    1650           0 :       NumMCOperands += 1;
    1651           0 :       break;
    1652           0 :     case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_:
    1653           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1654           0 :       Operands[*(p + 1)]->setConstraint("m");
    1655           0 :       NumMCOperands += 1;
    1656           0 :       break;
    1657           0 :     case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_:
    1658           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1659           0 :       Operands[*(p + 1)]->setConstraint("m");
    1660           0 :       NumMCOperands += 1;
    1661           0 :       break;
    1662           0 :     case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_:
    1663           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1664           0 :       Operands[*(p + 1)]->setConstraint("m");
    1665           0 :       NumMCOperands += 1;
    1666           0 :       break;
    1667           0 :     case CVT_95_addGPR32NonZeroAsmRegOperands:
    1668           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1669           0 :       Operands[*(p + 1)]->setConstraint("m");
    1670           0 :       NumMCOperands += 1;
    1671           0 :       break;
    1672           0 :     case CVT_95_addGPR32ZeroAsmRegOperands:
    1673           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1674           0 :       Operands[*(p + 1)]->setConstraint("m");
    1675           0 :       NumMCOperands += 1;
    1676           0 :       break;
    1677           0 :     case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_:
    1678           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1679           0 :       Operands[*(p + 1)]->setConstraint("m");
    1680           0 :       NumMCOperands += 1;
    1681           0 :       break;
    1682           0 :     case CVT_95_addCOP0AsmRegOperands:
    1683           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1684           0 :       Operands[*(p + 1)]->setConstraint("m");
    1685           0 :       NumMCOperands += 1;
    1686           0 :       break;
    1687           0 :     case CVT_regZERO_64:
    1688           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1689           0 :       Operands[*(p + 1)]->setConstraint("m");
    1690           0 :       ++NumMCOperands;
    1691           0 :       break;
    1692           0 :     case CVT_95_addACC64DSPAsmRegOperands:
    1693           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1694           0 :       Operands[*(p + 1)]->setConstraint("m");
    1695           0 :       NumMCOperands += 1;
    1696           0 :       break;
    1697           0 :     case CVT_95_addConstantUImmOperands_LT_1_GT_:
    1698           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1699           0 :       Operands[*(p + 1)]->setConstraint("m");
    1700           0 :       NumMCOperands += 1;
    1701           0 :       break;
    1702           0 :     case CVT_regRA:
    1703           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1704           0 :       Operands[*(p + 1)]->setConstraint("m");
    1705           0 :       ++NumMCOperands;
    1706           0 :       break;
    1707           0 :     case CVT_95_addMicroMipsMemOperands:
    1708           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1709           0 :       Operands[*(p + 1)]->setConstraint("m");
    1710           0 :       NumMCOperands += 2;
    1711           0 :       break;
    1712           0 :     case CVT_95_addCOP3AsmRegOperands:
    1713           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1714           0 :       Operands[*(p + 1)]->setConstraint("m");
    1715           0 :       NumMCOperands += 1;
    1716           0 :       break;
    1717           0 :     case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_:
    1718           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1719           0 :       Operands[*(p + 1)]->setConstraint("m");
    1720           0 :       NumMCOperands += 1;
    1721           0 :       break;
    1722           0 :     case CVT_95_addConstantUImmOperands_LT_32_GT_:
    1723           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1724           0 :       Operands[*(p + 1)]->setConstraint("m");
    1725           0 :       NumMCOperands += 1;
    1726           0 :       break;
    1727           0 :     case CVT_95_addStrictlyAFGR64AsmRegOperands:
    1728           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1729           0 :       Operands[*(p + 1)]->setConstraint("m");
    1730           0 :       NumMCOperands += 1;
    1731           0 :       break;
    1732           0 :     case CVT_95_addStrictlyFGR64AsmRegOperands:
    1733           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1734           0 :       Operands[*(p + 1)]->setConstraint("m");
    1735           0 :       NumMCOperands += 1;
    1736           0 :       break;
    1737           0 :     case CVT_95_addStrictlyFGR32AsmRegOperands:
    1738           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1739           0 :       Operands[*(p + 1)]->setConstraint("m");
    1740           0 :       NumMCOperands += 1;
    1741           0 :       break;
    1742           0 :     case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_:
    1743           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1744           0 :       Operands[*(p + 1)]->setConstraint("m");
    1745           0 :       NumMCOperands += 1;
    1746           0 :       break;
    1747           0 :     case CVT_95_addRegListOperands:
    1748           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1749           0 :       Operands[*(p + 1)]->setConstraint("m");
    1750           0 :       NumMCOperands += 1;
    1751           0 :       break;
    1752           0 :     case CVT_95_addRegPairOperands:
    1753           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1754           0 :       Operands[*(p + 1)]->setConstraint("m");
    1755           0 :       NumMCOperands += 2;
    1756           0 :       break;
    1757           0 :     case CVT_95_addMovePRegPairOperands:
    1758           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1759           0 :       Operands[*(p + 1)]->setConstraint("m");
    1760           0 :       NumMCOperands += 2;
    1761           0 :       break;
    1762           0 :     case CVT_95_addGPRMM16AsmRegMovePOperands:
    1763           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1764           0 :       Operands[*(p + 1)]->setConstraint("m");
    1765           0 :       NumMCOperands += 1;
    1766           0 :       break;
    1767           0 :     case CVT_95_addHI32DSPAsmRegOperands:
    1768           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1769           0 :       Operands[*(p + 1)]->setConstraint("m");
    1770           0 :       NumMCOperands += 1;
    1771           0 :       break;
    1772           0 :     case CVT_95_addLO32DSPAsmRegOperands:
    1773           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1774           0 :       Operands[*(p + 1)]->setConstraint("m");
    1775           0 :       NumMCOperands += 1;
    1776           0 :       break;
    1777           0 :     case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_:
    1778           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1779           0 :       Operands[*(p + 1)]->setConstraint("m");
    1780           0 :       NumMCOperands += 1;
    1781           0 :       break;
    1782           0 :     case CVT_95_addHWRegsAsmRegOperands:
    1783           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1784           0 :       Operands[*(p + 1)]->setConstraint("m");
    1785           0 :       NumMCOperands += 1;
    1786           0 :       break;
    1787           0 :     case CVT_95_addGPRMM16AsmRegZeroOperands:
    1788           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1789           0 :       Operands[*(p + 1)]->setConstraint("m");
    1790           0 :       NumMCOperands += 1;
    1791           0 :       break;
    1792           0 :     case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_:
    1793           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1794           0 :       Operands[*(p + 1)]->setConstraint("m");
    1795           0 :       NumMCOperands += 1;
    1796           0 :       break;
    1797           0 :     case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_:
    1798           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1799           0 :       Operands[*(p + 1)]->setConstraint("m");
    1800           0 :       NumMCOperands += 1;
    1801           0 :       break;
    1802           0 :     case CVT_imm_95_2:
    1803           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1804           0 :       Operands[*(p + 1)]->setConstraint("");
    1805           0 :       ++NumMCOperands;
    1806           0 :       break;
    1807           0 :     case CVT_imm_95_6:
    1808           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1809           0 :       Operands[*(p + 1)]->setConstraint("");
    1810           0 :       ++NumMCOperands;
    1811           0 :       break;
    1812           0 :     case CVT_imm_95_4:
    1813           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1814           0 :       Operands[*(p + 1)]->setConstraint("");
    1815           0 :       ++NumMCOperands;
    1816           0 :       break;
    1817           0 :     case CVT_imm_95_5:
    1818           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1819           0 :       Operands[*(p + 1)]->setConstraint("");
    1820           0 :       ++NumMCOperands;
    1821           0 :       break;
    1822           0 :     case CVT_imm_95_31:
    1823           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    1824           0 :       Operands[*(p + 1)]->setConstraint("");
    1825           0 :       ++NumMCOperands;
    1826           0 :       break;
    1827             :     }
    1828             :   }
    1829           0 : }
    1830             : 
    1831             : namespace {
    1832             : 
    1833             : /// MatchClassKind - The kinds of classes which participate in
    1834             : /// instruction matching.
    1835             : enum MatchClassKind {
    1836             :   InvalidMatchClass = 0,
    1837             :   OptionalMatchClass = 1,
    1838             :   MCK__35_, // '#'
    1839             :   MCK__40_, // '('
    1840             :   MCK__41_, // ')'
    1841             :   MCK_0, // '0'
    1842             :   MCK_16, // '16'
    1843             :   MCK__91_, // '['
    1844             :   MCK__93_, // ']'
    1845             :   MCK_bit, // 'bit'
    1846             :   MCK_inst, // 'inst'
    1847             :   MCK_Reg15, // derived register class
    1848             :   MCK_Reg29, // derived register class
    1849             :   MCK_ACC128, // register class 'ACC128'
    1850             :   MCK_ACC64, // register class 'ACC64'
    1851             :   MCK_CPURAReg, // register class 'CPURAReg,RA'
    1852             :   MCK_CPUSPReg, // register class 'CPUSPReg,SP32,SP'
    1853             :   MCK_DSPCC, // register class 'DSPCC'
    1854             :   MCK_GP32, // register class 'GP32'
    1855             :   MCK_GP64, // register class 'GP64'
    1856             :   MCK_GPR32ZERO, // register class 'GPR32ZERO,ZERO'
    1857             :   MCK_HI32, // register class 'HI32'
    1858             :   MCK_HI64, // register class 'HI64'
    1859             :   MCK_LO32, // register class 'LO32'
    1860             :   MCK_LO64, // register class 'LO64'
    1861             :   MCK_PC, // register class 'PC'
    1862             :   MCK_SP64, // register class 'SP64'
    1863             :   MCK_Reg11, // derived register class
    1864             :   MCK_Reg26, // derived register class
    1865             :   MCK_OCTEON_MPL, // register class 'OCTEON_MPL'
    1866             :   MCK_OCTEON_P, // register class 'OCTEON_P'
    1867             :   MCK_Reg4, // derived register class
    1868             :   MCK_Reg9, // derived register class
    1869             :   MCK_Reg19, // derived register class
    1870             :   MCK_Reg24, // derived register class
    1871             :   MCK_ACC64DSP, // register class 'ACC64DSP'
    1872             :   MCK_HI32DSP, // register class 'HI32DSP'
    1873             :   MCK_LO32DSP, // register class 'LO32DSP'
    1874             :   MCK_Reg8, // derived register class
    1875             :   MCK_Reg10, // derived register class
    1876             :   MCK_Reg23, // derived register class
    1877             :   MCK_Reg25, // derived register class
    1878             :   MCK_Reg17, // derived register class
    1879             :   MCK_Reg18, // derived register class
    1880             :   MCK_Reg36, // derived register class
    1881             :   MCK_CPU16Regs, // register class 'CPU16Regs,GPRMM16'
    1882             :   MCK_FCC, // register class 'FCC'
    1883             :   MCK_GPRMM16MoveP, // register class 'GPRMM16MoveP'
    1884             :   MCK_GPRMM16Zero, // register class 'GPRMM16Zero'
    1885             :   MCK_GPRMM16_64, // register class 'GPRMM16_64'
    1886             :   MCK_MSACtrl, // register class 'MSACtrl'
    1887             :   MCK_Reg22, // derived register class
    1888             :   MCK_CPU16RegsPlusSP, // register class 'CPU16RegsPlusSP'
    1889             :   MCK_Reg31, // derived register class
    1890             :   MCK_Reg34, // derived register class
    1891             :   MCK_Reg39, // derived register class
    1892             :   MCK_Reg42, // derived register class
    1893             :   MCK_AFGR64, // register class 'AFGR64'
    1894             :   MCK_MSA128WEvens, // register class 'MSA128WEvens'
    1895             :   MCK_Reg37, // derived register class
    1896             :   MCK_Reg20, // derived register class
    1897             :   MCK_GPR32NONZERO, // register class 'GPR32NONZERO'
    1898             :   MCK_CCR, // register class 'CCR'
    1899             :   MCK_COP0, // register class 'COP0'
    1900             :   MCK_COP2, // register class 'COP2'
    1901             :   MCK_COP3, // register class 'COP3'
    1902             :   MCK_DSPR, // register class 'DSPR,GPR32'
    1903             :   MCK_FGR32, // register class 'FGR32,FGRCC'
    1904             :   MCK_FGR64, // register class 'FGR64'
    1905             :   MCK_FGRH32, // register class 'FGRH32'
    1906             :   MCK_GPR64, // register class 'GPR64'
    1907             :   MCK_HWRegs, // register class 'HWRegs'
    1908             :   MCK_MSA128F16, // register class 'MSA128F16,MSA128B,MSA128D,MSA128H,MSA128W'
    1909             :   MCK_OddSP, // register class 'OddSP'
    1910             :   MCK_ACC64DSPAsmReg, // user defined class 'ACC64DSPAsmOperand'
    1911             :   MCK_AFGR64AsmReg, // user defined class 'AFGR64AsmOperand'
    1912             :   MCK_CCRAsmReg, // user defined class 'CCRAsmOperand'
    1913             :   MCK_COP0AsmReg, // user defined class 'COP0AsmOperand'
    1914             :   MCK_COP2AsmReg, // user defined class 'COP2AsmOperand'
    1915             :   MCK_COP3AsmReg, // user defined class 'COP3AsmOperand'
    1916             :   MCK_FCCAsmReg, // user defined class 'FCCRegsAsmOperand'
    1917             :   MCK_FGR32AsmReg, // user defined class 'FGR32AsmOperand'
    1918             :   MCK_FGR64AsmReg, // user defined class 'FGR64AsmOperand'
    1919             :   MCK_FGRH32AsmReg, // user defined class 'FGRH32AsmOperand'
    1920             :   MCK_GPR32AsmReg, // user defined class 'GPR32AsmOperand'
    1921             :   MCK_GPR32NonZeroAsmReg, // user defined class 'GPR32NonZeroAsmOperand'
    1922             :   MCK_GPR32ZeroAsmReg, // user defined class 'GPR32ZeroAsmOperand'
    1923             :   MCK_GPR64AsmReg, // user defined class 'GPR64AsmOperand'
    1924             :   MCK_GPRMM16AsmReg, // user defined class 'GPRMM16AsmOperand'
    1925             :   MCK_GPRMM16AsmRegMoveP, // user defined class 'GPRMM16AsmOperandMoveP'
    1926             :   MCK_GPRMM16AsmRegZero, // user defined class 'GPRMM16AsmOperandZero'
    1927             :   MCK_HI32DSPAsmReg, // user defined class 'HI32DSPAsmOperand'
    1928             :   MCK_HWRegsAsmReg, // user defined class 'HWRegsAsmOperand'
    1929             :   MCK_Imm, // user defined class 'ImmAsmOperand'
    1930             :   MCK_LO32DSPAsmReg, // user defined class 'LO32DSPAsmOperand'
    1931             :   MCK_MSA128AsmReg, // user defined class 'MSA128AsmOperand'
    1932             :   MCK_MSACtrlAsmReg, // user defined class 'MSACtrlAsmOperand'
    1933             :   MCK_MicroMipsMemGP, // user defined class 'MicroMipsMemGPAsmOperand'
    1934             :   MCK_MicroMipsMem, // user defined class 'MicroMipsMemGPRMM16AsmOperand'
    1935             :   MCK_MicroMipsMemSP, // user defined class 'MicroMipsMemSPAsmOperand'
    1936             :   MCK_InvNum, // user defined class 'MipsInvertedImmoperand'
    1937             :   MCK_JumpTarget, // user defined class 'MipsJumpTargetAsmOperand'
    1938             :   MCK_MemOffsetSimm10, // user defined class 'MipsMemSimm10AsmOperand'
    1939             :   MCK_MemOffsetSimm10_1, // user defined class 'MipsMemSimm10Lsl1AsmOperand'
    1940             :   MCK_MemOffsetSimm10_2, // user defined class 'MipsMemSimm10Lsl2AsmOperand'
    1941             :   MCK_MemOffsetSimm10_3, // user defined class 'MipsMemSimm10Lsl3AsmOperand'
    1942             :   MCK_MemOffsetSimm11, // user defined class 'MipsMemSimm11AsmOperand'
    1943             :   MCK_MemOffsetSimm12, // user defined class 'MipsMemSimm12AsmOperand'
    1944             :   MCK_MemOffsetSimm16, // user defined class 'MipsMemSimm16AsmOperand'
    1945             :   MCK_MemOffsetSimm9, // user defined class 'MipsMemSimm9AsmOperand'
    1946             :   MCK_MemOffsetUimm4, // user defined class 'MipsMemUimm4AsmOperand'
    1947             :   MCK_Mem, // user defined class 'MipsMemAsmOperand'
    1948             :   MCK_MovePRegPair, // user defined class 'MovePRegPairAsmOperand'
    1949             :   MCK_RegList16, // user defined class 'RegList16AsmOperand'
    1950             :   MCK_RegList, // user defined class 'RegListAsmOperand'
    1951             :   MCK_RegPair, // user defined class 'RegPairAsmOperand'
    1952             :   MCK_Simm19_Lsl2, // user defined class 'Simm19Lsl2AsmOperand'
    1953             :   MCK_StrictlyAFGR64AsmReg, // user defined class 'StrictlyAFGR64AsmOperand'
    1954             :   MCK_StrictlyFGR32AsmReg, // user defined class 'StrictlyFGR32AsmOperand'
    1955             :   MCK_StrictlyFGR64AsmReg, // user defined class 'StrictlyFGR64AsmOperand'
    1956             :   MCK_ConstantImmz, // user defined class 'ConstantImmzAsmOperandClass'
    1957             :   MCK_ConstantUImm1_0, // user defined class 'ConstantUImm1AsmOperandClass'
    1958             :   MCK_ConstantUImm2_0, // user defined class 'ConstantUImm2AsmOperandClass'
    1959             :   MCK_ConstantUImm2_1, // user defined class 'ConstantUImm2Plus1AsmOperandClass'
    1960             :   MCK_ConstantUImm3_0, // user defined class 'ConstantUImm3AsmOperandClass'
    1961             :   MCK_ConstantSImm4_0, // user defined class 'ConstantSImm4AsmOperandClass'
    1962             :   MCK_ConstantUImm4_0, // user defined class 'ConstantUImm4AsmOperandClass'
    1963             :   MCK_ConstantSImm5_0, // user defined class 'ConstantSImm5AsmOperandClass'
    1964             :   MCK_ConstantUImm5_0, // user defined class 'ConstantUImm5AsmOperandClass'
    1965             :   MCK_ConstantUImm5_1, // user defined class 'ConstantUImm5Plus1AsmOperandClass'
    1966             :   MCK_ConstantUImm5_32_Norm, // user defined class 'ConstantUImm5Plus32NormalizeAsmOperandClass'
    1967             :   MCK_ConstantUImm5_32, // user defined class 'ConstantUImm5Plus32AsmOperandClass'
    1968             :   MCK_ConstantUImm5_0_Report_UImm6, // user defined class 'ConstantUImm5ReportUImm6AsmOperandClass'
    1969             :   MCK_ConstantUImm5_33, // user defined class 'ConstantUImm5Plus33AsmOperandClass'
    1970             :   MCK_ConstantUImmRange2_64, // user defined class 'ConstantUImm5_Range2_64AsmOperandClass'
    1971             :   MCK_UImm5Lsl2, // user defined class 'ConstantUImm5Lsl2AsmOperandClass'
    1972             :   MCK_ConstantSImm6_0, // user defined class 'ConstantSImm6AsmOperandClass'
    1973             :   MCK_ConstantUImm6_0, // user defined class 'ConstantUImm6AsmOperandClass'
    1974             :   MCK_UImm6Lsl2, // user defined class 'ConstantUImm6Lsl2AsmOperandClass'
    1975             :   MCK_ConstantUImm7_0, // user defined class 'ConstantUImm7AsmOperandClass'
    1976             :   MCK_UImm7_N1, // user defined class 'ConstantUImm7Sub1AsmOperandClass'
    1977             :   MCK_ConstantUImm8_0, // user defined class 'ConstantUImm8AsmOperandClass'
    1978             :   MCK_SImm7Lsl2, // user defined class 'ConstantSImm7Lsl2AsmOperandClass'
    1979             :   MCK_ConstantSImm9_0, // user defined class 'ConstantSImm9AsmOperandClass'
    1980             :   MCK_ConstantSImm10_0, // user defined class 'ConstantSImm10AsmOperandClass'
    1981             :   MCK_ConstantUImm10_0, // user defined class 'ConstantUImm10AsmOperandClass'
    1982             :   MCK_SImm10Lsl1, // user defined class 'ConstantSImm10Lsl1AsmOperandClass'
    1983             :   MCK_ConstantSImm11_0, // user defined class 'ConstantSImm11AsmOperandClass'
    1984             :   MCK_SImm10Lsl2, // user defined class 'ConstantSImm10Lsl2AsmOperandClass'
    1985             :   MCK_SImm10Lsl3, // user defined class 'ConstantSImm10Lsl3AsmOperandClass'
    1986             :   MCK_SImm16, // user defined class 'SImm16AsmOperandClass'
    1987             :   MCK_SImm16_Relaxed, // user defined class 'SImm16RelaxedAsmOperandClass'
    1988             :   MCK_UImm16_AltRelaxed, // user defined class 'UImm16AltRelaxedAsmOperandClass'
    1989             :   MCK_UImm16, // user defined class 'UImm16AsmOperandClass'
    1990             :   MCK_SImm19Lsl2, // user defined class 'ConstantSImm19Lsl2AsmOperandClass'
    1991             :   MCK_UImm16_Relaxed, // user defined class 'UImm16RelaxedAsmOperandClass'
    1992             :   MCK_ConstantUImm20_0, // user defined class 'ConstantUImm20AsmOperandClass'
    1993             :   MCK_ConstantUImm26_0, // user defined class 'ConstantUImm26AsmOperandClass'
    1994             :   MCK_SImm32, // user defined class 'SImm32AsmOperandClass'
    1995             :   MCK_SImm32_Relaxed, // user defined class 'SImm32RelaxedAsmOperandClass'
    1996             :   MCK_UImm32_Coerced, // user defined class 'UImm32CoercedAsmOperandClass'
    1997             :   NumMatchClassKinds
    1998             : };
    1999             : 
    2000             : }
    2001             : 
    2002         750 : static MatchClassKind matchTokenString(StringRef Name) {
    2003         750 :   switch (Name.size()) {
    2004             :   default: break;
    2005         750 :   case 1:        // 6 strings to match.
    2006        1500 :     switch (Name[0]) {
    2007             :     default: break;
    2008             :     case '#':    // 1 string to match.
    2009             :       return MCK__35_;   // "#"
    2010         298 :     case '(':    // 1 string to match.
    2011         298 :       return MCK__40_;   // "("
    2012         298 :     case ')':    // 1 string to match.
    2013         298 :       return MCK__41_;   // ")"
    2014           0 :     case '0':    // 1 string to match.
    2015           0 :       return MCK_0;      // "0"
    2016         112 :     case '[':    // 1 string to match.
    2017         112 :       return MCK__91_;   // "["
    2018          42 :     case ']':    // 1 string to match.
    2019          42 :       return MCK__93_;   // "]"
    2020             :     }
    2021             :     break;
    2022           0 :   case 2:        // 1 string to match.
    2023           0 :     if (memcmp(Name.data()+0, "16", 2) != 0)
    2024             :       break;
    2025             :     return MCK_16;       // "16"
    2026           0 :   case 3:        // 1 string to match.
    2027           0 :     if (memcmp(Name.data()+0, "bit", 3) != 0)
    2028             :       break;
    2029             :     return MCK_bit;      // "bit"
    2030           0 :   case 4:        // 1 string to match.
    2031           0 :     if (memcmp(Name.data()+0, "inst", 4) != 0)
    2032             :       break;
    2033             :     return MCK_inst;     // "inst"
    2034             :   }
    2035             :   return InvalidMatchClass;
    2036             : }
    2037             : 
    2038             : /// isSubclass - Compute whether \p A is a subclass of \p B.
    2039       18569 : static bool isSubclass(MatchClassKind A, MatchClassKind B) {
    2040       18569 :   if (A == B)
    2041             :     return true;
    2042             : 
    2043       17699 :   switch (A) {
    2044             :   default:
    2045             :     return false;
    2046             : 
    2047           0 :   case MCK_Reg15:
    2048           0 :     switch (B) {
    2049             :     default: return false;
    2050           0 :     case MCK_Reg19: return true;
    2051           0 :     case MCK_Reg17: return true;
    2052           0 :     case MCK_Reg18: return true;
    2053           0 :     case MCK_GPR64: return true;
    2054             :     }
    2055             : 
    2056           0 :   case MCK_Reg29:
    2057           0 :     switch (B) {
    2058             :     default: return false;
    2059           0 :     case MCK_Reg20: return true;
    2060           0 :     case MCK_GPR64: return true;
    2061             :     }
    2062             : 
    2063           0 :   case MCK_ACC64:
    2064           0 :     return B == MCK_ACC64DSP;
    2065             : 
    2066         131 :   case MCK_CPURAReg:
    2067         131 :     switch (B) {
    2068             :     default: return false;
    2069           0 :     case MCK_GPR32NONZERO: return true;
    2070           0 :     case MCK_DSPR: return true;
    2071             :     }
    2072             : 
    2073         527 :   case MCK_CPUSPReg:
    2074             :     switch (B) {
    2075             :     default: return false;
    2076             :     case MCK_CPU16RegsPlusSP: return true;
    2077             :     case MCK_GPR32NONZERO: return true;
    2078             :     case MCK_DSPR: return true;
    2079             :     }
    2080             : 
    2081           0 :   case MCK_GP32:
    2082           0 :     switch (B) {
    2083             :     default: return false;
    2084           0 :     case MCK_GPR32NONZERO: return true;
    2085           0 :     case MCK_DSPR: return true;
    2086             :     }
    2087             : 
    2088           0 :   case MCK_GP64:
    2089           0 :     switch (B) {
    2090             :     default: return false;
    2091           0 :     case MCK_Reg20: return true;
    2092           0 :     case MCK_GPR64: return true;
    2093             :     }
    2094             : 
    2095         359 :   case MCK_GPR32ZERO:
    2096         359 :     switch (B) {
    2097             :     default: return false;
    2098           0 :     case MCK_Reg4: return true;
    2099           0 :     case MCK_GPRMM16MoveP: return true;
    2100           0 :     case MCK_GPRMM16Zero: return true;
    2101           0 :     case MCK_DSPR: return true;
    2102             :     }
    2103             : 
    2104           0 :   case MCK_HI32:
    2105           0 :     return B == MCK_HI32DSP;
    2106             : 
    2107           0 :   case MCK_LO32:
    2108           0 :     return B == MCK_LO32DSP;
    2109             : 
    2110           0 :   case MCK_SP64:
    2111             :     switch (B) {
    2112             :     default: return false;
    2113             :     case MCK_Reg22: return true;
    2114             :     case MCK_Reg20: return true;
    2115             :     case MCK_GPR64: return true;
    2116             :     }
    2117             : 
    2118           0 :   case MCK_Reg11:
    2119             :     switch (B) {
    2120             :     default: return false;
    2121             :     case MCK_Reg4: return true;
    2122             :     case MCK_Reg9: return true;
    2123             :     case MCK_Reg8: return true;
    2124             :     case MCK_Reg10: return true;
    2125             :     case MCK_CPU16Regs: return true;
    2126             :     case MCK_GPRMM16MoveP: return true;
    2127             :     case MCK_GPRMM16Zero: return true;
    2128             :     case MCK_CPU16RegsPlusSP: return true;
    2129             :     case MCK_GPR32NONZERO: return true;
    2130             :     case MCK_DSPR: return true;
    2131             :     }
    2132             : 
    2133           0 :   case MCK_Reg26:
    2134             :     switch (B) {
    2135             :     default: return false;
    2136             :     case MCK_Reg19: return true;
    2137             :     case MCK_Reg24: return true;
    2138             :     case MCK_Reg23: return true;
    2139             :     case MCK_Reg25: return true;
    2140             :     case MCK_Reg17: return true;
    2141             :     case MCK_Reg18: return true;
    2142             :     case MCK_GPRMM16_64: return true;
    2143             :     case MCK_Reg22: return true;
    2144             :     case MCK_Reg20: return true;
    2145             :     case MCK_GPR64: return true;
    2146             :     }
    2147             : 
    2148           0 :   case MCK_Reg4:
    2149             :     switch (B) {
    2150             :     default: return false;
    2151             :     case MCK_GPRMM16MoveP: return true;
    2152             :     case MCK_GPRMM16Zero: return true;
    2153             :     case MCK_DSPR: return true;
    2154             :     }
    2155             : 
    2156           0 :   case MCK_Reg9:
    2157             :     switch (B) {
    2158             :     default: return false;
    2159             :     case MCK_Reg10: return true;
    2160             :     case MCK_CPU16Regs: return true;
    2161             :     case MCK_GPRMM16MoveP: return true;
    2162             :     case MCK_CPU16RegsPlusSP: return true;
    2163             :     case MCK_GPR32NONZERO: return true;
    2164             :     case MCK_DSPR: return true;
    2165             :     }
    2166             : 
    2167           0 :   case MCK_Reg19:
    2168           0 :     switch (B) {
    2169             :     default: return false;
    2170           0 :     case MCK_Reg17: return true;
    2171           0 :     case MCK_Reg18: return true;
    2172           0 :     case MCK_GPR64: return true;
    2173             :     }
    2174             : 
    2175           0 :   case MCK_Reg24:
    2176             :     switch (B) {
    2177             :     default: return false;
    2178             :     case MCK_Reg25: return true;
    2179             :     case MCK_Reg18: return true;
    2180             :     case MCK_GPRMM16_64: return true;
    2181             :     case MCK_Reg22: return true;
    2182             :     case MCK_Reg20: return true;
    2183             :     case MCK_GPR64: return true;
    2184             :     }
    2185             : 
    2186           0 :   case MCK_Reg8:
    2187             :     switch (B) {
    2188             :     default: return false;
    2189             :     case MCK_CPU16Regs: return true;
    2190             :     case MCK_GPRMM16Zero: return true;
    2191             :     case MCK_CPU16RegsPlusSP: return true;
    2192             :     case MCK_GPR32NONZERO: return true;
    2193             :     case MCK_DSPR: return true;
    2194             :     }
    2195             : 
    2196           0 :   case MCK_Reg10:
    2197             :     switch (B) {
    2198             :     default: return false;
    2199             :     case MCK_GPRMM16MoveP: return true;
    2200             :     case MCK_GPR32NONZERO: return true;
    2201             :     case MCK_DSPR: return true;
    2202             :     }
    2203             : 
    2204           0 :   case MCK_Reg23:
    2205             :     switch (B) {
    2206             :     default: return false;
    2207             :     case MCK_Reg17: return true;
    2208             :     case MCK_GPRMM16_64: return true;
    2209             :     case MCK_Reg22: return true;
    2210             :     case MCK_Reg20: return true;
    2211             :     case MCK_GPR64: return true;
    2212             :     }
    2213             : 
    2214           0 :   case MCK_Reg25:
    2215           0 :     switch (B) {
    2216             :     default: return false;
    2217           0 :     case MCK_Reg18: return true;
    2218           0 :     case MCK_Reg20: return true;
    2219           0 :     case MCK_GPR64: return true;
    2220             :     }
    2221             : 
    2222           0 :   case MCK_Reg17:
    2223           0 :     return B == MCK_GPR64;
    2224             : 
    2225           0 :   case MCK_Reg18:
    2226           0 :     return B == MCK_GPR64;
    2227             : 
    2228           0 :   case MCK_Reg36:
    2229             :     switch (B) {
    2230             :     default: return false;
    2231             :     case MCK_AFGR64: return true;
    2232             :     case MCK_Reg37: return true;
    2233             :     case MCK_OddSP: return true;
    2234             :     }
    2235             : 
    2236        3197 :   case MCK_CPU16Regs:
    2237             :     switch (B) {
    2238             :     default: return false;
    2239             :     case MCK_CPU16RegsPlusSP: return true;
    2240             :     case MCK_GPR32NONZERO: return true;
    2241             :     case MCK_DSPR: return true;
    2242             :     }
    2243             : 
    2244           0 :   case MCK_GPRMM16MoveP:
    2245           0 :     return B == MCK_DSPR;
    2246             : 
    2247           0 :   case MCK_GPRMM16Zero:
    2248           0 :     return B == MCK_DSPR;
    2249             : 
    2250           0 :   case MCK_GPRMM16_64:
    2251             :     switch (B) {
    2252             :     default: return false;
    2253             :     case MCK_Reg22: return true;
    2254             :     case MCK_Reg20: return true;
    2255             :     case MCK_GPR64: return true;
    2256             :     }
    2257             : 
    2258           0 :   case MCK_Reg22:
    2259           0 :     switch (B) {
    2260             :     default: return false;
    2261           0 :     case MCK_Reg20: return true;
    2262           0 :     case MCK_GPR64: return true;
    2263             :     }
    2264             : 
    2265           0 :   case MCK_CPU16RegsPlusSP:
    2266           0 :     switch (B) {
    2267             :     default: return false;
    2268           0 :     case MCK_GPR32NONZERO: return true;
    2269           0 :     case MCK_DSPR: return true;
    2270             :     }
    2271             : 
    2272           0 :   case MCK_Reg31:
    2273           0 :     switch (B) {
    2274             :     default: return false;
    2275           0 :     case MCK_FGR32: return true;
    2276           0 :     case MCK_OddSP: return true;
    2277             :     }
    2278             : 
    2279           0 :   case MCK_Reg34:
    2280           0 :     switch (B) {
    2281             :     default: return false;
    2282           0 :     case MCK_FGRH32: return true;
    2283           0 :     case MCK_OddSP: return true;
    2284             :     }
    2285             : 
    2286           0 :   case MCK_Reg39:
    2287             :     switch (B) {
    2288             :     default: return false;
    2289             :     case MCK_Reg37: return true;
    2290             :     case MCK_FGR64: return true;
    2291             :     case MCK_OddSP: return true;
    2292             :     }
    2293             : 
    2294           0 :   case MCK_Reg42:
    2295           0 :     return B == MCK_MSA128F16;
    2296             : 
    2297           0 :   case MCK_MSA128WEvens:
    2298           0 :     return B == MCK_MSA128F16;
    2299             : 
    2300           0 :   case MCK_Reg37:
    2301           0 :     return B == MCK_OddSP;
    2302             : 
    2303           0 :   case MCK_Reg20:
    2304           0 :     return B == MCK_GPR64;
    2305             : 
    2306           0 :   case MCK_GPR32NONZERO:
    2307           0 :     return B == MCK_DSPR;
    2308             : 
    2309           0 :   case MCK_MemOffsetSimm10:
    2310           0 :     return B == MCK_Mem;
    2311             : 
    2312           0 :   case MCK_MemOffsetSimm10_1:
    2313           0 :     return B == MCK_Mem;
    2314             : 
    2315           0 :   case MCK_MemOffsetSimm10_2:
    2316           0 :     return B == MCK_Mem;
    2317             : 
    2318           0 :   case MCK_MemOffsetSimm10_3:
    2319           0 :     return B == MCK_Mem;
    2320             : 
    2321           0 :   case MCK_MemOffsetSimm11:
    2322           0 :     return B == MCK_Mem;
    2323             : 
    2324           0 :   case MCK_MemOffsetSimm12:
    2325           0 :     return B == MCK_Mem;
    2326             : 
    2327           0 :   case MCK_MemOffsetSimm16:
    2328           0 :     return B == MCK_Mem;
    2329             : 
    2330           0 :   case MCK_MemOffsetSimm9:
    2331           0 :     return B == MCK_Mem;
    2332             : 
    2333          16 :   case MCK_MemOffsetUimm4:
    2334          16 :     return B == MCK_Mem;
    2335             : 
    2336           0 :   case MCK_ConstantImmz:
    2337             :     switch (B) {
    2338             :     default: return false;
    2339             :     case MCK_ConstantUImm1_0: return true;
    2340             :     case MCK_ConstantUImm2_0: return true;
    2341             :     case MCK_ConstantUImm3_0: return true;
    2342             :     case MCK_ConstantSImm4_0: return true;
    2343             :     case MCK_ConstantUImm4_0: return true;
    2344             :     case MCK_ConstantSImm5_0: return true;
    2345             :     case MCK_ConstantUImm5_0: return true;
    2346             :     case MCK_ConstantUImm5_1: return true;
    2347             :     case MCK_ConstantUImm5_32_Norm: return true;
    2348             :     case MCK_ConstantUImm5_32: return true;
    2349             :     case MCK_ConstantUImm5_0_Report_UImm6: return true;
    2350             :     case MCK_ConstantUImm5_33: return true;
    2351             :     case MCK_ConstantUImmRange2_64: return true;
    2352             :     case MCK_UImm5Lsl2: return true;
    2353             :     case MCK_ConstantSImm6_0: return true;
    2354             :     case MCK_ConstantUImm6_0: return true;
    2355             :     case MCK_UImm6Lsl2: return true;
    2356             :     case MCK_ConstantUImm7_0: return true;
    2357             :     case MCK_UImm7_N1: return true;
    2358             :     case MCK_ConstantUImm8_0: return true;
    2359             :     case MCK_SImm7Lsl2: return true;
    2360             :     case MCK_ConstantSImm9_0: return true;
    2361             :     case MCK_ConstantSImm10_0: return true;
    2362             :     case MCK_ConstantUImm10_0: return true;
    2363             :     case MCK_SImm10Lsl1: return true;
    2364             :     case MCK_ConstantSImm11_0: return true;
    2365             :     case MCK_SImm10Lsl2: return true;
    2366             :     case MCK_SImm10Lsl3: return true;
    2367             :     case MCK_SImm16: return true;
    2368             :     case MCK_SImm16_Relaxed: return true;
    2369             :     case MCK_UImm16_Relaxed: return true;
    2370             :     case MCK_ConstantUImm20_0: return true;
    2371             :     case MCK_ConstantUImm26_0: return true;
    2372             :     case MCK_SImm32: return true;
    2373             :     case MCK_SImm32_Relaxed: return true;
    2374             :     case MCK_UImm32_Coerced: return true;
    2375             :     }
    2376             : 
    2377           0 :   case MCK_ConstantUImm1_0:
    2378             :     switch (B) {
    2379             :     default: return false;
    2380             :     case MCK_ConstantUImm2_0: return true;
    2381             :     case MCK_ConstantUImm3_0: return true;
    2382             :     case MCK_ConstantSImm4_0: return true;
    2383             :     case MCK_ConstantUImm4_0: return true;
    2384             :     case MCK_ConstantSImm5_0: return true;
    2385             :     case MCK_ConstantUImm5_0: return true;
    2386             :     case MCK_ConstantUImm5_1: return true;
    2387             :     case MCK_ConstantUImm5_32_Norm: return true;
    2388             :     case MCK_ConstantUImm5_32: return true;
    2389             :     case MCK_ConstantUImm5_0_Report_UImm6: return true;
    2390             :     case MCK_ConstantUImm5_33: return true;
    2391             :     case MCK_ConstantUImmRange2_64: return true;
    2392             :     case MCK_UImm5Lsl2: return true;
    2393             :     case MCK_ConstantSImm6_0: return true;
    2394             :     case MCK_ConstantUImm6_0: return true;
    2395             :     case MCK_UImm6Lsl2: return true;
    2396             :     case MCK_ConstantUImm7_0: return true;
    2397             :     case MCK_UImm7_N1: return true;
    2398             :     case MCK_ConstantUImm8_0: return true;
    2399             :     case MCK_SImm7Lsl2: return true;
    2400             :     case MCK_ConstantSImm9_0: return true;
    2401             :     case MCK_ConstantSImm10_0: return true;
    2402             :     case MCK_ConstantUImm10_0: return true;
    2403             :     case MCK_SImm10Lsl1: return true;
    2404             :     case MCK_ConstantSImm11_0: return true;
    2405             :     case MCK_SImm10Lsl2: return true;
    2406             :     case MCK_SImm10Lsl3: return true;
    2407             :     case MCK_SImm16: return true;
    2408             :     case MCK_SImm16_Relaxed: return true;
    2409             :     case MCK_UImm16_Relaxed: return true;
    2410             :     case MCK_ConstantUImm20_0: return true;
    2411             :     case MCK_ConstantUImm26_0: return true;
    2412             :     case MCK_SImm32: return true;
    2413             :     case MCK_SImm32_Relaxed: return true;
    2414             :     case MCK_UImm32_Coerced: return true;
    2415             :     }
    2416             : 
    2417           0 :   case MCK_ConstantUImm2_0:
    2418             :     switch (B) {
    2419             :     default: return false;
    2420             :     case MCK_ConstantUImm3_0: return true;
    2421             :     case MCK_ConstantSImm4_0: return true;
    2422             :     case MCK_ConstantUImm4_0: return true;
    2423             :     case MCK_ConstantSImm5_0: return true;
    2424             :     case MCK_ConstantUImm5_0: return true;
    2425             :     case MCK_ConstantUImm5_1: return true;
    2426             :     case MCK_ConstantUImm5_32_Norm: return true;
    2427             :     case MCK_ConstantUImm5_32: return true;
    2428             :     case MCK_ConstantUImm5_0_Report_UImm6: return true;
    2429             :     case MCK_ConstantUImm5_33: return true;
    2430             :     case MCK_ConstantUImmRange2_64: return true;
    2431             :     case MCK_UImm5Lsl2: return true;
    2432             :     case MCK_ConstantSImm6_0: return true;
    2433             :     case MCK_ConstantUImm6_0: return true;
    2434             :     case MCK_UImm6Lsl2: return true;
    2435             :     case MCK_ConstantUImm7_0: return true;
    2436             :     case MCK_UImm7_N1: return true;
    2437             :     case MCK_ConstantUImm8_0: return true;
    2438             :     case MCK_SImm7Lsl2: return true;
    2439             :     case MCK_ConstantSImm9_0: return true;
    2440             :     case MCK_ConstantSImm10_0: return true;
    2441             :     case MCK_ConstantUImm10_0: return true;
    2442             :     case MCK_SImm10Lsl1: return true;
    2443             :     case MCK_ConstantSImm11_0: return true;
    2444             :     case MCK_SImm10Lsl2: return true;
    2445             :     case MCK_SImm10Lsl3: return true;
    2446             :     case MCK_SImm16: return true;
    2447             :     case MCK_SImm16_Relaxed: return true;
    2448             :     case MCK_UImm16_Relaxed: return true;
    2449             :     case MCK_ConstantUImm20_0: return true;
    2450             :     case MCK_ConstantUImm26_0: return true;
    2451             :     case MCK_SImm32: return true;
    2452             :     case MCK_SImm32_Relaxed: return true;
    2453             :     case MCK_UImm32_Coerced: return true;
    2454             :     }
    2455             : 
    2456           0 :   case MCK_ConstantUImm2_1:
    2457             :     switch (B) {
    2458             :     default: return false;
    2459             :     case MCK_ConstantUImm3_0: return true;
    2460             :     case MCK_ConstantSImm4_0: return true;
    2461             :     case MCK_ConstantUImm4_0: return true;
    2462             :     case MCK_ConstantSImm5_0: return true;
    2463             :     case MCK_ConstantUImm5_0: return true;
    2464             :     case MCK_ConstantUImm5_1: return true;
    2465             :     case MCK_ConstantUImm5_32_Norm: return true;
    2466             :     case MCK_ConstantUImm5_32: return true;
    2467             :     case MCK_ConstantUImm5_0_Report_UImm6: return true;
    2468             :     case MCK_ConstantUImm5_33: return true;
    2469             :     case MCK_ConstantUImmRange2_64: return true;
    2470             :     case MCK_UImm5Lsl2: return true;
    2471             :     case MCK_ConstantSImm6_0: return true;
    2472             :     case MCK_ConstantUImm6_0: return true;
    2473             :     case MCK_UImm6Lsl2: return true;
    2474             :     case MCK_ConstantUImm7_0: return true;
    2475             :     case MCK_UImm7_N1: return true;
    2476             :     case MCK_ConstantUImm8_0: return true;
    2477             :     case MCK_SImm7Lsl2: return true;
    2478             :     case MCK_ConstantSImm9_0: return true;
    2479             :     case MCK_ConstantSImm10_0: return true;
    2480             :     case MCK_ConstantUImm10_0: return true;
    2481             :     case MCK_SImm10Lsl1: return true;
    2482             :     case MCK_ConstantSImm11_0: return true;
    2483             :     case MCK_SImm10Lsl2: return true;
    2484             :     case MCK_SImm10Lsl3: return true;
    2485             :     case MCK_SImm16: return true;
    2486             :     case MCK_SImm16_Relaxed: return true;
    2487             :     case MCK_UImm16_Relaxed: return true;
    2488             :     case MCK_ConstantUImm20_0: return true;
    2489             :     case MCK_ConstantUImm26_0: return true;
    2490             :     case MCK_SImm32: return true;
    2491             :     case MCK_SImm32_Relaxed: return true;
    2492             :     case MCK_UImm32_Coerced: return true;
    2493             :     }
    2494             : 
    2495           0 :   case MCK_ConstantUImm3_0:
    2496             :     switch (B) {
    2497             :     default: return false;
    2498             :     case MCK_ConstantSImm4_0: return true;
    2499             :     case MCK_ConstantUImm4_0: return true;
    2500             :     case MCK_ConstantSImm5_0: return true;
    2501             :     case MCK_ConstantUImm5_0: return true;
    2502             :     case MCK_ConstantUImm5_1: return true;
    2503             :     case MCK_ConstantUImm5_32_Norm: return true;
    2504             :     case MCK_ConstantUImm5_32: return true;
    2505             :     case MCK_ConstantUImm5_0_Report_UImm6: return true;
    2506             :     case MCK_ConstantUImm5_33: return true;
    2507             :     case MCK_ConstantUImmRange2_64: return true;
    2508             :     case MCK_UImm5Lsl2: return true;
    2509             :     case MCK_ConstantSImm6_0: return true;
    2510             :     case MCK_ConstantUImm6_0: return true;
    2511             :     case MCK_UImm6Lsl2: return true;
    2512             :     case MCK_ConstantUImm7_0: return true;
    2513             :     case MCK_UImm7_N1: return true;
    2514             :     case MCK_ConstantUImm8_0: return true;
    2515             :     case MCK_SImm7Lsl2: return true;
    2516             :     case MCK_ConstantSImm9_0: return true;
    2517             :     case MCK_ConstantSImm10_0: return true;
    2518             :     case MCK_ConstantUImm10_0: return true;
    2519             :     case MCK_SImm10Lsl1: return true;
    2520             :     case MCK_ConstantSImm11_0: return true;
    2521             :     case MCK_SImm10Lsl2: return true;
    2522             :     case MCK_SImm10Lsl3: return true;
    2523             :     case MCK_SImm16: return true;
    2524             :     case MCK_SImm16_Relaxed: return true;
    2525             :     case MCK_UImm16_Relaxed: return true;
    2526             :     case MCK_ConstantUImm20_0: return true;
    2527             :     case MCK_ConstantUImm26_0: return true;
    2528             :     case MCK_SImm32: return true;
    2529             :     case MCK_SImm32_Relaxed: return true;
    2530             :     case MCK_UImm32_Coerced: return true;
    2531             :     }
    2532             : 
    2533           0 :   case MCK_ConstantSImm4_0:
    2534             :     switch (B) {
    2535             :     default: return false;
    2536             :     case MCK_ConstantUImm4_0: return true;
    2537             :     case MCK_ConstantSImm5_0: return true;
    2538             :     case MCK_ConstantUImm5_0: return true;
    2539             :     case MCK_ConstantUImm5_1: return true;
    2540             :     case MCK_ConstantUImm5_32_Norm: return true;
    2541             :     case MCK_ConstantUImm5_32: return true;
    2542             :     case MCK_ConstantUImm5_0_Report_UImm6: return true;
    2543             :     case MCK_ConstantUImm5_33: return true;
    2544             :     case MCK_ConstantUImmRange2_64: return true;
    2545             :     case MCK_UImm5Lsl2: return true;
    2546             :     case MCK_ConstantSImm6_0: return true;
    2547             :     case MCK_ConstantUImm6_0: return true;
    2548             :     case MCK_UImm6Lsl2: return true;
    2549             :     case MCK_ConstantUImm7_0: return true;
    2550             :     case MCK_UImm7_N1: return true;
    2551             :     case MCK_ConstantUImm8_0: return true;
    2552             :     case MCK_SImm7Lsl2: return true;
    2553             :     case MCK_ConstantSImm9_0: return true;
    2554             :     case MCK_ConstantSImm10_0: return true;
    2555             :     case MCK_ConstantUImm10_0: return true;
    2556             :     case MCK_SImm10Lsl1: return true;
    2557             :     case MCK_ConstantSImm11_0: return true;
    2558             :     case MCK_SImm10Lsl2: return true;
    2559             :     case MCK_SImm10Lsl3: return true;
    2560             :     case MCK_SImm16: return true;
    2561             :     case MCK_SImm16_Relaxed: return true;
    2562             :     case MCK_UImm16_Relaxed: return true;
    2563             :     case MCK_ConstantUImm20_0: return true;
    2564             :     case MCK_ConstantUImm26_0: return true;
    2565             :     case MCK_SImm32: return true;
    2566             :     case MCK_SImm32_Relaxed: return true;
    2567             :     case MCK_UImm32_Coerced: return true;
    2568             :     }
    2569             : 
    2570           6 :   case MCK_ConstantUImm4_0:
    2571             :     switch (B) {
    2572             :     default: return false;
    2573             :     case MCK_ConstantSImm5_0: return true;
    2574             :     case MCK_ConstantUImm5_0: return true;
    2575             :     case MCK_ConstantUImm5_1: return true;
    2576             :     case MCK_ConstantUImm5_32_Norm: return true;
    2577             :     case MCK_ConstantUImm5_32: return true;
    2578             :     case MCK_ConstantUImm5_0_Report_UImm6: return true;
    2579             :     case MCK_ConstantUImm5_33: return true;
    2580             :     case MCK_ConstantUImmRange2_64: return true;
    2581             :     case MCK_UImm5Lsl2: return true;
    2582             :     case MCK_ConstantSImm6_0: return true;
    2583             :     case MCK_ConstantUImm6_0: return true;
    2584             :     case MCK_UImm6Lsl2: return true;
    2585             :     case MCK_ConstantUImm7_0: return true;
    2586             :     case MCK_UImm7_N1: return true;
    2587             :     case MCK_ConstantUImm8_0: return true;
    2588             :     case MCK_SImm7Lsl2: return true;
    2589             :     case MCK_ConstantSImm9_0: return true;
    2590             :     case MCK_ConstantSImm10_0: return true;
    2591             :     case MCK_ConstantUImm10_0: return true;
    2592             :     case MCK_SImm10Lsl1: return true;
    2593             :     case MCK_ConstantSImm11_0: return true;
    2594             :     case MCK_SImm10Lsl2: return true;
    2595             :     case MCK_SImm10Lsl3: return true;
    2596             :     case MCK_SImm16: return true;
    2597             :     case MCK_SImm16_Relaxed: return true;
    2598             :     case MCK_UImm16_Relaxed: return true;
    2599             :     case MCK_ConstantUImm20_0: return true;
    2600             :     case MCK_ConstantUImm26_0: return true;
    2601             :     case MCK_SImm32: return true;
    2602             :     case MCK_SImm32_Relaxed: return true;
    2603             :     case MCK_UImm32_Coerced: return true;
    2604             :     }
    2605             : 
    2606           0 :   case MCK_ConstantSImm5_0:
    2607             :     switch (B) {
    2608             :     default: return false;
    2609             :     case MCK_ConstantUImm5_0: return true;
    2610             :     case MCK_ConstantUImm5_1: return true;
    2611             :     case MCK_ConstantUImm5_32_Norm: return true;
    2612             :     case MCK_ConstantUImm5_32: return true;
    2613             :     case MCK_ConstantUImm5_0_Report_UImm6: return true;
    2614             :     case MCK_ConstantUImm5_33: return true;
    2615             :     case MCK_ConstantUImmRange2_64: return true;
    2616             :     case MCK_UImm5Lsl2: return true;
    2617             :     case MCK_ConstantSImm6_0: return true;
    2618             :     case MCK_ConstantUImm6_0: return true;
    2619             :     case MCK_UImm6Lsl2: return true;
    2620             :     case MCK_ConstantUImm7_0: return true;
    2621             :     case MCK_UImm7_N1: return true;
    2622             :     case MCK_ConstantUImm8_0: return true;
    2623             :     case MCK_SImm7Lsl2: return true;
    2624             :     case MCK_ConstantSImm9_0: return true;
    2625             :     case MCK_ConstantSImm10_0: return true;
    2626             :     case MCK_ConstantUImm10_0: return true;
    2627             :     case MCK_SImm10Lsl1: return true;
    2628             :     case MCK_ConstantSImm11_0: return true;
    2629             :     case MCK_SImm10Lsl2: return true;
    2630             :     case MCK_SImm10Lsl3: return true;
    2631             :     case MCK_SImm16: return true;
    2632             :     case MCK_SImm16_Relaxed: return true;
    2633             :     case MCK_UImm16_Relaxed: return true;
    2634             :     case MCK_ConstantUImm20_0: return true;
    2635             :     case MCK_ConstantUImm26_0: return true;
    2636             :     case MCK_SImm32: return true;
    2637             :     case MCK_SImm32_Relaxed: return true;
    2638             :     case MCK_UImm32_Coerced: return true;
    2639             :     }
    2640             : 
    2641           3 :   case MCK_ConstantUImm5_0:
    2642             :     switch (B) {
    2643             :     default: return false;
    2644             :     case MCK_ConstantUImm5_1: return true;
    2645             :     case MCK_ConstantUImm5_32_Norm: return true;
    2646             :     case MCK_ConstantUImm5_32: return true;
    2647             :     case MCK_ConstantUImm5_0_Report_UImm6: return true;
    2648             :     case MCK_ConstantUImm5_33: return true;
    2649             :     case MCK_ConstantUImmRange2_64: return true;
    2650             :     case MCK_UImm5Lsl2: return true;
    2651             :     case MCK_ConstantSImm6_0: return true;
    2652             :     case MCK_ConstantUImm6_0: return true;
    2653             :     case MCK_UImm6Lsl2: return true;
    2654             :     case MCK_ConstantUImm7_0: return true;
    2655             :     case MCK_UImm7_N1: return true;
    2656             :     case MCK_ConstantUImm8_0: return true;
    2657             :     case MCK_SImm7Lsl2: return true;
    2658             :     case MCK_ConstantSImm9_0: return true;
    2659             :     case MCK_ConstantSImm10_0: return true;
    2660             :     case MCK_ConstantUImm10_0: return true;
    2661             :     case MCK_SImm10Lsl1: return true;
    2662             :     case MCK_ConstantSImm11_0: return true;
    2663             :     case MCK_SImm10Lsl2: return true;
    2664             :     case MCK_SImm10Lsl3: return true;
    2665             :     case MCK_SImm16: return true;
    2666             :     case MCK_SImm16_Relaxed: return true;
    2667             :     case MCK_UImm16_Relaxed: return true;
    2668             :     case MCK_ConstantUImm20_0: return true;
    2669             :     case MCK_ConstantUImm26_0: return true;
    2670             :     case MCK_SImm32: return true;
    2671             :     case MCK_SImm32_Relaxed: return true;
    2672             :     case MCK_UImm32_Coerced: return true;
    2673             :     }
    2674             : 
    2675           0 :   case MCK_ConstantUImm5_1:
    2676             :     switch (B) {
    2677             :     default: return false;
    2678             :     case MCK_ConstantUImm5_32_Norm: return true;
    2679             :     case MCK_ConstantUImm5_32: return true;
    2680             :     case MCK_ConstantUImm5_0_Report_UImm6: return true;
    2681             :     case MCK_ConstantUImm5_33: return true;
    2682             :     case MCK_ConstantUImmRange2_64: return true;
    2683             :     case MCK_UImm5Lsl2: return true;
    2684             :     case MCK_ConstantSImm6_0: return true;
    2685             :     case MCK_ConstantUImm6_0: return true;
    2686             :     case MCK_UImm6Lsl2: return true;
    2687             :     case MCK_ConstantUImm7_0: return true;
    2688             :     case MCK_UImm7_N1: return true;
    2689             :     case MCK_ConstantUImm8_0: return true;
    2690             :     case MCK_SImm7Lsl2: return true;
    2691             :     case MCK_ConstantSImm9_0: return true;
    2692             :     case MCK_ConstantSImm10_0: return true;
    2693             :     case MCK_ConstantUImm10_0: return true;
    2694             :     case MCK_SImm10Lsl1: return true;
    2695             :     case MCK_ConstantSImm11_0: return true;
    2696             :     case MCK_SImm10Lsl2: return true;
    2697             :     case MCK_SImm10Lsl3: return true;
    2698             :     case MCK_SImm16: return true;
    2699             :     case MCK_SImm16_Relaxed: return true;
    2700             :     case MCK_UImm16_Relaxed: return true;
    2701             :     case MCK_ConstantUImm20_0: return true;
    2702             :     case MCK_ConstantUImm26_0: return true;
    2703             :     case MCK_SImm32: return true;
    2704             :     case MCK_SImm32_Relaxed: return true;
    2705             :     case MCK_UImm32_Coerced: return true;
    2706             :     }
    2707             : 
    2708           0 :   case MCK_ConstantUImm5_32_Norm:
    2709             :     switch (B) {
    2710             :     default: return false;
    2711             :     case MCK_ConstantUImm5_32: return true;
    2712             :     case MCK_ConstantUImm5_0_Report_UImm6: return true;
    2713             :     case MCK_ConstantUImm5_33: return true;
    2714             :     case MCK_ConstantUImmRange2_64: return true;
    2715             :     case MCK_UImm5Lsl2: return true;
    2716             :     case MCK_ConstantSImm6_0: return true;
    2717             :     case MCK_ConstantUImm6_0: return true;
    2718             :     case MCK_UImm6Lsl2: return true;
    2719             :     case MCK_ConstantUImm7_0: return true;
    2720             :     case MCK_UImm7_N1: return true;
    2721             :     case MCK_ConstantUImm8_0: return true;
    2722             :     case MCK_SImm7Lsl2: return true;
    2723             :     case MCK_ConstantSImm9_0: return true;
    2724             :     case MCK_ConstantSImm10_0: return true;
    2725             :     case MCK_ConstantUImm10_0: return true;
    2726             :     case MCK_SImm10Lsl1: return true;
    2727             :     case MCK_ConstantSImm11_0: return true;
    2728             :     case MCK_SImm10Lsl2: return true;
    2729             :     case MCK_SImm10Lsl3: return true;
    2730             :     case MCK_SImm16: return true;
    2731             :     case MCK_SImm16_Relaxed: return true;
    2732             :     case MCK_UImm16_Relaxed: return true;
    2733             :     case MCK_ConstantUImm20_0: return true;
    2734             :     case MCK_ConstantUImm26_0: return true;
    2735             :     case MCK_SImm32: return true;
    2736             :     case MCK_SImm32_Relaxed: return true;
    2737             :     case MCK_UImm32_Coerced: return true;
    2738             :     }
    2739             : 
    2740           0 :   case MCK_ConstantUImm5_32:
    2741             :     switch (B) {
    2742             :     default: return false;
    2743             :     case MCK_ConstantUImm5_0_Report_UImm6: return true;
    2744             :     case MCK_ConstantUImm5_33: return true;
    2745             :     case MCK_ConstantUImmRange2_64: return true;
    2746             :     case MCK_UImm5Lsl2: return true;
    2747             :     case MCK_ConstantSImm6_0: return true;
    2748             :     case MCK_ConstantUImm6_0: return true;
    2749             :     case MCK_UImm6Lsl2: return true;
    2750             :     case MCK_ConstantUImm7_0: return true;
    2751             :     case MCK_UImm7_N1: return true;
    2752             :     case MCK_ConstantUImm8_0: return true;
    2753             :     case MCK_SImm7Lsl2: return true;
    2754             :     case MCK_ConstantSImm9_0: return true;
    2755             :     case MCK_ConstantSImm10_0: return true;
    2756             :     case MCK_ConstantUImm10_0: return true;
    2757             :     case MCK_SImm10Lsl1: return true;
    2758             :     case MCK_ConstantSImm11_0: return true;
    2759             :     case MCK_SImm10Lsl2: return true;
    2760             :     case MCK_SImm10Lsl3: return true;
    2761             :     case MCK_SImm16: return true;
    2762             :     case MCK_SImm16_Relaxed: return true;
    2763             :     case MCK_UImm16_Relaxed: return true;
    2764             :     case MCK_ConstantUImm20_0: return true;
    2765             :     case MCK_ConstantUImm26_0: return true;
    2766             :     case MCK_SImm32: return true;
    2767             :     case MCK_SImm32_Relaxed: return true;
    2768             :     case MCK_UImm32_Coerced: return true;
    2769             :     }
    2770             : 
    2771           0 :   case MCK_ConstantUImm5_0_Report_UImm6:
    2772             :     switch (B) {
    2773             :     default: return false;
    2774             :     case MCK_ConstantUImm5_33: return true;
    2775             :     case MCK_ConstantUImmRange2_64: return true;
    2776             :     case MCK_UImm5Lsl2: return true;
    2777             :     case MCK_ConstantSImm6_0: return true;
    2778             :     case MCK_ConstantUImm6_0: return true;
    2779             :     case MCK_UImm6Lsl2: return true;
    2780             :     case MCK_ConstantUImm7_0: return true;
    2781             :     case MCK_UImm7_N1: return true;
    2782             :     case MCK_ConstantUImm8_0: return true;
    2783             :     case MCK_SImm7Lsl2: return true;
    2784             :     case MCK_ConstantSImm9_0: return true;
    2785             :     case MCK_ConstantSImm10_0: return true;
    2786             :     case MCK_ConstantUImm10_0: return true;
    2787             :     case MCK_SImm10Lsl1: return true;
    2788             :     case MCK_ConstantSImm11_0: return true;
    2789             :     case MCK_SImm10Lsl2: return true;
    2790             :     case MCK_SImm10Lsl3: return true;
    2791             :     case MCK_SImm16: return true;
    2792             :     case MCK_SImm16_Relaxed: return true;
    2793             :     case MCK_UImm16_Relaxed: return true;
    2794             :     case MCK_ConstantUImm20_0: return true;
    2795             :     case MCK_ConstantUImm26_0: return true;
    2796             :     case MCK_SImm32: return true;
    2797             :     case MCK_SImm32_Relaxed: return true;
    2798             :     case MCK_UImm32_Coerced: return true;
    2799             :     }
    2800             : 
    2801           0 :   case MCK_ConstantUImm5_33:
    2802             :     switch (B) {
    2803             :     default: return false;
    2804             :     case MCK_ConstantUImmRange2_64: return true;
    2805             :     case MCK_UImm5Lsl2: return true;
    2806             :     case MCK_ConstantSImm6_0: return true;
    2807             :     case MCK_ConstantUImm6_0: return true;
    2808             :     case MCK_UImm6Lsl2: return true;
    2809             :     case MCK_ConstantUImm7_0: return true;
    2810             :     case MCK_UImm7_N1: return true;
    2811             :     case MCK_ConstantUImm8_0: return true;
    2812             :     case MCK_SImm7Lsl2: return true;
    2813             :     case MCK_ConstantSImm9_0: return true;
    2814             :     case MCK_ConstantSImm10_0: return true;
    2815             :     case MCK_ConstantUImm10_0: return true;
    2816             :     case MCK_SImm10Lsl1: return true;
    2817             :     case MCK_ConstantSImm11_0: return true;
    2818             :     case MCK_SImm10Lsl2: return true;
    2819             :     case MCK_SImm10Lsl3: return true;
    2820             :     case MCK_SImm16: return true;
    2821             :     case MCK_SImm16_Relaxed: return true;
    2822             :     case MCK_UImm16_Relaxed: return true;
    2823             :     case MCK_ConstantUImm20_0: return true;
    2824             :     case MCK_ConstantUImm26_0: return true;
    2825             :     case MCK_SImm32: return true;
    2826             :     case MCK_SImm32_Relaxed: return true;
    2827             :     case MCK_UImm32_Coerced: return true;
    2828             :     }
    2829             : 
    2830           0 :   case MCK_ConstantUImmRange2_64:
    2831             :     switch (B) {
    2832             :     default: return false;
    2833             :     case MCK_UImm5Lsl2: return true;
    2834             :     case MCK_ConstantSImm6_0: return true;
    2835             :     case MCK_ConstantUImm6_0: return true;
    2836             :     case MCK_UImm6Lsl2: return true;
    2837             :     case MCK_ConstantUImm7_0: return true;
    2838             :     case MCK_UImm7_N1: return true;
    2839             :     case MCK_ConstantUImm8_0: return true;
    2840             :     case MCK_SImm7Lsl2: return true;
    2841             :     case MCK_ConstantSImm9_0: return true;
    2842             :     case MCK_ConstantSImm10_0: return true;
    2843             :     case MCK_ConstantUImm10_0: return true;
    2844             :     case MCK_SImm10Lsl1: return true;
    2845             :     case MCK_ConstantSImm11_0: return true;
    2846             :     case MCK_SImm10Lsl2: return true;
    2847             :     case MCK_SImm10Lsl3: return true;
    2848             :     case MCK_SImm16: return true;
    2849             :     case MCK_SImm16_Relaxed: return true;
    2850             :     case MCK_UImm16_Relaxed: return true;
    2851             :     case MCK_ConstantUImm20_0: return true;
    2852             :     case MCK_ConstantUImm26_0: return true;
    2853             :     case MCK_SImm32: return true;
    2854             :     case MCK_SImm32_Relaxed: return true;
    2855             :     case MCK_UImm32_Coerced: return true;
    2856             :     }
    2857             : 
    2858           0 :   case MCK_UImm5Lsl2:
    2859             :     switch (B) {
    2860             :     default: return false;
    2861             :     case MCK_ConstantSImm6_0: return true;
    2862             :     case MCK_ConstantUImm6_0: return true;
    2863             :     case MCK_UImm6Lsl2: return true;
    2864             :     case MCK_ConstantUImm7_0: return true;
    2865             :     case MCK_UImm7_N1: return true;
    2866             :     case MCK_ConstantUImm8_0: return true;
    2867             :     case MCK_SImm7Lsl2: return true;
    2868             :     case MCK_ConstantSImm9_0: return true;
    2869             :     case MCK_ConstantSImm10_0: return true;
    2870             :     case MCK_ConstantUImm10_0: return true;
    2871             :     case MCK_SImm10Lsl1: return true;
    2872             :     case MCK_ConstantSImm11_0: return true;
    2873             :     case MCK_SImm10Lsl2: return true;
    2874             :     case MCK_SImm10Lsl3: return true;
    2875             :     case MCK_SImm16: return true;
    2876             :     case MCK_SImm16_Relaxed: return true;
    2877             :     case MCK_UImm16_Relaxed: return true;
    2878             :     case MCK_ConstantUImm20_0: return true;
    2879             :     case MCK_ConstantUImm26_0: return true;
    2880             :     case MCK_SImm32: return true;
    2881             :     case MCK_SImm32_Relaxed: return true;
    2882             :     case MCK_UImm32_Coerced: return true;
    2883             :     }
    2884             : 
    2885           0 :   case MCK_ConstantSImm6_0:
    2886             :     switch (B) {
    2887             :     default: return false;
    2888             :     case MCK_ConstantUImm6_0: return true;
    2889             :     case MCK_UImm6Lsl2: return true;
    2890             :     case MCK_ConstantUImm7_0: return true;
    2891             :     case MCK_UImm7_N1: return true;
    2892             :     case MCK_ConstantUImm8_0: return true;
    2893             :     case MCK_SImm7Lsl2: return true;
    2894             :     case MCK_ConstantSImm9_0: return true;
    2895             :     case MCK_ConstantSImm10_0: return true;
    2896             :     case MCK_ConstantUImm10_0: return true;
    2897             :     case MCK_SImm10Lsl1: return true;
    2898             :     case MCK_ConstantSImm11_0: return true;
    2899             :     case MCK_SImm10Lsl2: return true;
    2900             :     case MCK_SImm10Lsl3: return true;
    2901             :     case MCK_SImm16: return true;
    2902             :     case MCK_SImm16_Relaxed: return true;
    2903             :     case MCK_UImm16_Relaxed: return true;
    2904             :     case MCK_ConstantUImm20_0: return true;
    2905             :     case MCK_ConstantUImm26_0: return true;
    2906             :     case MCK_SImm32: return true;
    2907             :     case MCK_SImm32_Relaxed: return true;
    2908             :     case MCK_UImm32_Coerced: return true;
    2909             :     }
    2910             : 
    2911           0 :   case MCK_ConstantUImm6_0:
    2912             :     switch (B) {
    2913             :     default: return false;
    2914             :     case MCK_UImm6Lsl2: return true;
    2915             :     case MCK_ConstantUImm7_0: return true;
    2916             :     case MCK_UImm7_N1: return true;
    2917             :     case MCK_ConstantUImm8_0: return true;
    2918             :     case MCK_SImm7Lsl2: return true;
    2919             :     case MCK_ConstantSImm9_0: return true;
    2920             :     case MCK_ConstantSImm10_0: return true;
    2921             :     case MCK_ConstantUImm10_0: return true;
    2922             :     case MCK_SImm10Lsl1: return true;
    2923             :     case MCK_ConstantSImm11_0: return true;
    2924             :     case MCK_SImm10Lsl2: return true;
    2925             :     case MCK_SImm10Lsl3: return true;
    2926             :     case MCK_SImm16: return true;
    2927             :     case MCK_SImm16_Relaxed: return true;
    2928             :     case MCK_UImm16_Relaxed: return true;
    2929             :     case MCK_ConstantUImm20_0: return true;
    2930             :     case MCK_ConstantUImm26_0: return true;
    2931             :     case MCK_SImm32: return true;
    2932             :     case MCK_SImm32_Relaxed: return true;
    2933             :     case MCK_UImm32_Coerced: return true;
    2934             :     }
    2935             : 
    2936           0 :   case MCK_UImm6Lsl2:
    2937             :     switch (B) {
    2938             :     default: return false;
    2939             :     case MCK_ConstantUImm7_0: return true;
    2940             :     case MCK_UImm7_N1: return true;
    2941             :     case MCK_ConstantUImm8_0: return true;
    2942             :     case MCK_SImm7Lsl2: return true;
    2943             :     case MCK_ConstantSImm9_0: return true;
    2944             :     case MCK_ConstantSImm10_0: return true;
    2945             :     case MCK_ConstantUImm10_0: return true;
    2946             :     case MCK_SImm10Lsl1: return true;
    2947             :     case MCK_ConstantSImm11_0: return true;
    2948             :     case MCK_SImm10Lsl2: return true;
    2949             :     case MCK_SImm10Lsl3: return true;
    2950             :     case MCK_SImm16: return true;
    2951             :     case MCK_SImm16_Relaxed: return true;
    2952             :     case MCK_UImm16_Relaxed: return true;
    2953             :     case MCK_ConstantUImm20_0: return true;
    2954             :     case MCK_ConstantUImm26_0: return true;
    2955             :     case MCK_SImm32: return true;
    2956             :     case MCK_SImm32_Relaxed: return true;
    2957             :     case MCK_UImm32_Coerced: return true;
    2958             :     }
    2959             : 
    2960           0 :   case MCK_ConstantUImm7_0:
    2961             :     switch (B) {
    2962             :     default: return false;
    2963             :     case MCK_UImm7_N1: return true;
    2964             :     case MCK_ConstantUImm8_0: return true;
    2965             :     case MCK_SImm7Lsl2: return true;
    2966             :     case MCK_ConstantSImm9_0: return true;
    2967             :     case MCK_ConstantSImm10_0: return true;
    2968             :     case MCK_ConstantUImm10_0: return true;
    2969             :     case MCK_SImm10Lsl1: return true;
    2970             :     case MCK_ConstantSImm11_0: return true;
    2971             :     case MCK_SImm10Lsl2: return true;
    2972             :     case MCK_SImm10Lsl3: return true;
    2973             :     case MCK_SImm16: return true;
    2974             :     case MCK_SImm16_Relaxed: return true;
    2975             :     case MCK_UImm16_Relaxed: return true;
    2976             :     case MCK_ConstantUImm20_0: return true;
    2977             :     case MCK_ConstantUImm26_0: return true;
    2978             :     case MCK_SImm32: return true;
    2979             :     case MCK_SImm32_Relaxed: return true;
    2980             :     case MCK_UImm32_Coerced: return true;
    2981             :     }
    2982             : 
    2983           0 :   case MCK_UImm7_N1:
    2984             :     switch (B) {
    2985             :     default: return false;
    2986             :     case MCK_ConstantUImm8_0: return true;
    2987             :     case MCK_SImm7Lsl2: return true;
    2988             :     case MCK_ConstantSImm9_0: return true;
    2989             :     case MCK_ConstantSImm10_0: return true;
    2990             :     case MCK_ConstantUImm10_0: return true;
    2991             :     case MCK_SImm10Lsl1: return true;
    2992             :     case MCK_ConstantSImm11_0: return true;
    2993             :     case MCK_SImm10Lsl2: return true;
    2994             :     case MCK_SImm10Lsl3: return true;
    2995             :     case MCK_SImm16: return true;
    2996             :     case MCK_SImm16_Relaxed: return true;
    2997             :     case MCK_UImm16_Relaxed: return true;
    2998             :     case MCK_ConstantUImm20_0: return true;
    2999             :     case MCK_ConstantUImm26_0: return true;
    3000             :     case MCK_SImm32: return true;
    3001             :     case MCK_SImm32_Relaxed: return true;
    3002             :     case MCK_UImm32_Coerced: return true;
    3003             :     }
    3004             : 
    3005           0 :   case MCK_ConstantUImm8_0:
    3006             :     switch (B) {
    3007             :     default: return false;
    3008             :     case MCK_SImm7Lsl2: return true;
    3009             :     case MCK_ConstantSImm9_0: return true;
    3010             :     case MCK_ConstantSImm10_0: return true;
    3011             :     case MCK_ConstantUImm10_0: return true;
    3012             :     case MCK_SImm10Lsl1: return true;
    3013             :     case MCK_ConstantSImm11_0: return true;
    3014             :     case MCK_SImm10Lsl2: return true;
    3015             :     case MCK_SImm10Lsl3: return true;
    3016             :     case MCK_SImm16: return true;
    3017             :     case MCK_SImm16_Relaxed: return true;
    3018             :     case MCK_UImm16_Relaxed: return true;
    3019             :     case MCK_ConstantUImm20_0: return true;
    3020             :     case MCK_ConstantUImm26_0: return true;
    3021             :     case MCK_SImm32: return true;
    3022             :     case MCK_SImm32_Relaxed: return true;
    3023             :     case MCK_UImm32_Coerced: return true;
    3024             :     }
    3025             : 
    3026           0 :   case MCK_SImm7Lsl2:
    3027             :     switch (B) {
    3028             :     default: return false;
    3029             :     case MCK_ConstantSImm9_0: return true;
    3030             :     case MCK_ConstantSImm10_0: return true;
    3031             :     case MCK_ConstantUImm10_0: return true;
    3032             :     case MCK_SImm10Lsl1: return true;
    3033             :     case MCK_ConstantSImm11_0: return true;
    3034             :     case MCK_SImm10Lsl2: return true;
    3035             :     case MCK_SImm10Lsl3: return true;
    3036             :     case MCK_SImm16: return true;
    3037             :     case MCK_SImm16_Relaxed: return true;
    3038             :     case MCK_UImm16_Relaxed: return true;
    3039             :     case MCK_ConstantUImm20_0: return true;
    3040             :     case MCK_ConstantUImm26_0: return true;
    3041             :     case MCK_SImm32: return true;
    3042             :     case MCK_SImm32_Relaxed: return true;
    3043             :     case MCK_UImm32_Coerced: return true;
    3044             :     }
    3045             : 
    3046           0 :   case MCK_ConstantSImm9_0:
    3047             :     switch (B) {
    3048             :     default: return false;
    3049             :     case MCK_ConstantSImm10_0: return true;
    3050             :     case MCK_ConstantUImm10_0: return true;
    3051             :     case MCK_SImm10Lsl1: return true;
    3052             :     case MCK_ConstantSImm11_0: return true;
    3053             :     case MCK_SImm10Lsl2: return true;
    3054             :     case MCK_SImm10Lsl3: return true;
    3055             :     case MCK_SImm16: return true;
    3056             :     case MCK_SImm16_Relaxed: return true;
    3057             :     case MCK_UImm16_Relaxed: return true;
    3058             :     case MCK_ConstantUImm20_0: return true;
    3059             :     case MCK_ConstantUImm26_0: return true;
    3060             :     case MCK_SImm32: return true;
    3061             :     case MCK_SImm32_Relaxed: return true;
    3062             :     case MCK_UImm32_Coerced: return true;
    3063             :     }
    3064             : 
    3065           0 :   case MCK_ConstantSImm10_0:
    3066             :     switch (B) {
    3067             :     default: return false;
    3068             :     case MCK_ConstantUImm10_0: return true;
    3069             :     case MCK_SImm10Lsl1: return true;
    3070             :     case MCK_ConstantSImm11_0: return true;
    3071             :     case MCK_SImm10Lsl2: return true;
    3072             :     case MCK_SImm10Lsl3: return true;
    3073             :     case MCK_SImm16: return true;
    3074             :     case MCK_SImm16_Relaxed: return true;
    3075             :     case MCK_UImm16_Relaxed: return true;
    3076             :     case MCK_ConstantUImm20_0: return true;
    3077             :     case MCK_ConstantUImm26_0: return true;
    3078             :     case MCK_SImm32: return true;
    3079             :     case MCK_SImm32_Relaxed: return true;
    3080             :     case MCK_UImm32_Coerced: return true;
    3081             :     }
    3082             : 
    3083           6 :   case MCK_ConstantUImm10_0:
    3084             :     switch (B) {
    3085             :     default: return false;
    3086             :     case MCK_SImm10Lsl1: return true;
    3087             :     case MCK_ConstantSImm11_0: return true;
    3088             :     case MCK_SImm10Lsl2: return true;
    3089             :     case MCK_SImm10Lsl3: return true;
    3090             :     case MCK_SImm16: return true;
    3091             :     case MCK_SImm16_Relaxed: return true;
    3092             :     case MCK_UImm16_Relaxed: return true;
    3093             :     case MCK_ConstantUImm20_0: return true;
    3094             :     case MCK_ConstantUImm26_0: return true;
    3095             :     case MCK_SImm32: return true;
    3096             :     case MCK_SImm32_Relaxed: return true;
    3097             :     case MCK_UImm32_Coerced: return true;
    3098             :     }
    3099             : 
    3100           0 :   case MCK_SImm10Lsl1:
    3101             :     switch (B) {
    3102             :     default: return false;
    3103             :     case MCK_ConstantSImm11_0: return true;
    3104             :     case MCK_SImm10Lsl2: return true;
    3105             :     case MCK_SImm10Lsl3: return true;
    3106             :     case MCK_SImm16: return true;
    3107             :     case MCK_SImm16_Relaxed: return true;
    3108             :     case MCK_UImm16_Relaxed: return true;
    3109             :     case MCK_ConstantUImm20_0: return true;
    3110             :     case MCK_ConstantUImm26_0: return true;
    3111             :     case MCK_SImm32: return true;
    3112             :     case MCK_SImm32_Relaxed: return true;
    3113             :     case MCK_UImm32_Coerced: return true;
    3114             :     }
    3115             : 
    3116           0 :   case MCK_ConstantSImm11_0:
    3117             :     switch (B) {
    3118             :     default: return false;
    3119             :     case MCK_SImm10Lsl2: return true;
    3120             :     case MCK_SImm10Lsl3: return true;
    3121             :     case MCK_SImm16: return true;
    3122             :     case MCK_SImm16_Relaxed: return true;
    3123             :     case MCK_UImm16_Relaxed: return true;
    3124             :     case MCK_ConstantUImm20_0: return true;
    3125             :     case MCK_ConstantUImm26_0: return true;
    3126             :     case MCK_SImm32: return true;
    3127             :     case MCK_SImm32_Relaxed: return true;
    3128             :     case MCK_UImm32_Coerced: return true;
    3129             :     }
    3130             : 
    3131           0 :   case MCK_SImm10Lsl2:
    3132             :     switch (B) {
    3133             :     default: return false;
    3134             :     case MCK_SImm10Lsl3: return true;
    3135             :     case MCK_SImm16: return true;
    3136             :     case MCK_SImm16_Relaxed: return true;
    3137             :     case MCK_UImm16_Relaxed: return true;
    3138             :     case MCK_ConstantUImm20_0: return true;
    3139             :     case MCK_ConstantUImm26_0: return true;
    3140             :     case MCK_SImm32: return true;
    3141             :     case MCK_SImm32_Relaxed: return true;
    3142             :     case MCK_UImm32_Coerced: return true;
    3143             :     }
    3144             : 
    3145           0 :   case MCK_SImm10Lsl3:
    3146             :     switch (B) {
    3147             :     default: return false;
    3148             :     case MCK_SImm16: return true;
    3149             :     case MCK_SImm16_Relaxed: return true;
    3150             :     case MCK_UImm16_Relaxed: return true;
    3151             :     case MCK_ConstantUImm20_0: return true;
    3152             :     case MCK_ConstantUImm26_0: return true;
    3153             :     case MCK_SImm32: return true;
    3154             :     case MCK_SImm32_Relaxed: return true;
    3155             :     case MCK_UImm32_Coerced: return true;
    3156             :     }
    3157             : 
    3158          10 :   case MCK_SImm16:
    3159             :     switch (B) {
    3160             :     default: return false;
    3161             :     case MCK_SImm16_Relaxed: return true;
    3162             :     case MCK_UImm16_Relaxed: return true;
    3163             :     case MCK_ConstantUImm20_0: return true;
    3164             :     case MCK_ConstantUImm26_0: return true;
    3165             :     case MCK_SImm32: return true;
    3166             :     case MCK_SImm32_Relaxed: return true;
    3167             :     case MCK_UImm32_Coerced: return true;
    3168             :     }
    3169             : 
    3170           0 :   case MCK_SImm16_Relaxed:
    3171             :     switch (B) {
    3172             :     default: return false;
    3173             :     case MCK_UImm16_Relaxed: return true;
    3174             :     case MCK_ConstantUImm20_0: return true;
    3175             :     case MCK_ConstantUImm26_0: return true;
    3176             :     case MCK_SImm32: return true;
    3177             :     case MCK_SImm32_Relaxed: return true;
    3178             :     case MCK_UImm32_Coerced: return true;
    3179             :     }
    3180             : 
    3181           0 :   case MCK_UImm16_AltRelaxed:
    3182             :     switch (B) {
    3183             :     default: return false;
    3184             :     case MCK_UImm16_Relaxed: return true;
    3185             :     case MCK_ConstantUImm20_0: return true;
    3186             :     case MCK_ConstantUImm26_0: return true;
    3187             :     case MCK_SImm32: return true;
    3188             :     case MCK_SImm32_Relaxed: return true;
    3189             :     case MCK_UImm32_Coerced: return true;
    3190             :     }
    3191             : 
    3192           0 :   case MCK_UImm16:
    3193             :     switch (B) {
    3194             :     default: return false;
    3195             :     case MCK_UImm16_Relaxed: return true;
    3196             :     case MCK_ConstantUImm20_0: return true;
    3197             :     case MCK_ConstantUImm26_0: return true;
    3198             :     case MCK_SImm32: return true;
    3199             :     case MCK_SImm32_Relaxed: return true;
    3200             :     case MCK_UImm32_Coerced: return true;
    3201             :     }
    3202             : 
    3203           0 :   case MCK_SImm19Lsl2:
    3204             :     switch (B) {
    3205             :     default: return false;
    3206             :     case MCK_ConstantUImm20_0: return true;
    3207             :     case MCK_ConstantUImm26_0: return true;
    3208             :     case MCK_SImm32: return true;
    3209             :     case MCK_SImm32_Relaxed: return true;
    3210             :     case MCK_UImm32_Coerced: return true;
    3211             :     }
    3212             : 
    3213           0 :   case MCK_UImm16_Relaxed:
    3214             :     switch (B) {
    3215             :     default: return false;
    3216             :     case MCK_ConstantUImm20_0: return true;
    3217             :     case MCK_ConstantUImm26_0: return true;
    3218             :     case MCK_SImm32: return true;
    3219             :     case MCK_SImm32_Relaxed: return true;
    3220             :     case MCK_UImm32_Coerced: return true;
    3221             :     }
    3222             : 
    3223           0 :   case MCK_ConstantUImm20_0:
    3224             :     switch (B) {
    3225             :     default: return false;
    3226             :     case MCK_ConstantUImm26_0: return true;
    3227             :     case MCK_SImm32: return true;
    3228             :     case MCK_SImm32_Relaxed: return true;
    3229             :     case MCK_UImm32_Coerced: return true;
    3230             :     }
    3231             : 
    3232           0 :   case MCK_ConstantUImm26_0:
    3233             :     switch (B) {
    3234             :     default: return false;
    3235             :     case MCK_SImm32: return true;
    3236             :     case MCK_SImm32_Relaxed: return true;
    3237             :     case MCK_UImm32_Coerced: return true;
    3238             :     }
    3239             : 
    3240           0 :   case MCK_SImm32:
    3241           0 :     switch (B) {
    3242             :     default: return false;
    3243           0 :     case MCK_SImm32_Relaxed: return true;
    3244           0 :     case MCK_UImm32_Coerced: return true;
    3245             :     }
    3246             : 
    3247           0 :   case MCK_SImm32_Relaxed:
    3248           0 :     return B == MCK_UImm32_Coerced;
    3249             :   }
    3250             : }
    3251             : 
    3252      111402 : static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
    3253      111402 :   MipsOperand &Operand = (MipsOperand&)GOp;
    3254      111402 :   if (Kind == InvalidMatchClass)
    3255             :     return MCTargetAsmParser::Match_InvalidOperand;
    3256             : 
    3257      213942 :   if (Operand.isToken())
    3258        1500 :     return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
    3259             :              MCTargetAsmParser::Match_Success :
    3260             :              MCTargetAsmParser::Match_InvalidOperand;
    3261             : 
    3262      106221 :   switch (Kind) {
    3263             :   default: break;
    3264             :   // 'ACC64DSPAsmReg' class
    3265         533 :   case MCK_ACC64DSPAsmReg:
    3266             :     if (Operand.isACCAsmReg())
    3267             :       return MCTargetAsmParser::Match_Success;
    3268             :     break;
    3269             :   // 'AFGR64AsmReg' class
    3270        3981 :   case MCK_AFGR64AsmReg:
    3271             :     if (Operand.isFGRAsmReg())
    3272             :       return MCTargetAsmParser::Match_Success;
    3273             :     break;
    3274             :   // 'CCRAsmReg' class
    3275          50 :   case MCK_CCRAsmReg:
    3276             :     if (Operand.isCCRAsmReg())
    3277             :       return MCTargetAsmParser::Match_Success;
    3278             :     break;
    3279             :   // 'COP0AsmReg' class
    3280         416 :   case MCK_COP0AsmReg:
    3281             :     if (Operand.isCOP0AsmReg())
    3282             :       return MCTargetAsmParser::Match_Success;
    3283             :     break;
    3284             :   // 'COP2AsmReg' class
    3285         726 :   case MCK_COP2AsmReg:
    3286             :     if (Operand.isCOP2AsmReg())
    3287             :       return MCTargetAsmParser::Match_Success;
    3288             :     break;
    3289             :   // 'COP3AsmReg' class
    3290           8 :   case MCK_COP3AsmReg:
    3291             :     if (Operand.isCOP3AsmReg())
    3292             :       return MCTargetAsmParser::Match_Success;
    3293             :     break;
    3294             :   // 'FCCAsmReg' class
    3295        1935 :   case MCK_FCCAsmReg:
    3296        1517 :     if (Operand.isFCCAsmReg())
    3297             :       return MCTargetAsmParser::Match_Success;
    3298             :     break;
    3299             :   // 'FGR32AsmReg' class
    3300        6649 :   case MCK_FGR32AsmReg:
    3301             :     if (Operand.isFGRAsmReg())
    3302             :       return MCTargetAsmParser::Match_Success;
    3303             :     break;
    3304             :   // 'FGR64AsmReg' class
    3305        4144 :   case MCK_FGR64AsmReg:
    3306             :     if (Operand.isFGRAsmReg())
    3307             :       return MCTargetAsmParser::Match_Success;
    3308             :     break;
    3309             :   // 'FGRH32AsmReg' class
    3310           0 :   case MCK_FGRH32AsmReg:
    3311             :     if (Operand.isFGRAsmReg())
    3312             :       return MCTargetAsmParser::Match_Success;
    3313             :     break;
    3314             :   // 'GPR32AsmReg' class
    3315       44347 :   case MCK_GPR32AsmReg:
    3316             :     if (Operand.isGPRAsmReg())
    3317             :       return MCTargetAsmParser::Match_Success;
    3318             :     break;
    3319             :   // 'GPR32NonZeroAsmReg' class
    3320         130 :   case MCK_GPR32NonZeroAsmReg:
    3321             :     if (Operand.isGPRNonZeroAsmReg())
    3322             :       return MCTargetAsmParser::Match_Success;
    3323             :     break;
    3324             :   // 'GPR32ZeroAsmReg' class
    3325         100 :   case MCK_GPR32ZeroAsmReg:
    3326             :     if (Operand.isGPRZeroAsmReg())
    3327             :       return MCTargetAsmParser::Match_Success;
    3328             :     break;
    3329             :   // 'GPR64AsmReg' class
    3330       10205 :   case MCK_GPR64AsmReg:
    3331             :     if (Operand.isGPRAsmReg())
    3332             :       return MCTargetAsmParser::Match_Success;
    3333             :     break;
    3334             :   // 'GPRMM16AsmReg' class
    3335         330 :   case MCK_GPRMM16AsmReg:
    3336             :     if (Operand.isMM16AsmReg())
    3337             :       return MCTargetAsmParser::Match_Success;
    3338             :     break;
    3339             :   // 'GPRMM16AsmRegMoveP' class
    3340          19 :   case MCK_GPRMM16AsmRegMoveP:
    3341             :     if (Operand.isMM16AsmRegMoveP())
    3342             :       return MCTargetAsmParser::Match_Success;
    3343             :     break;
    3344             :   // 'GPRMM16AsmRegZero' class
    3345          83 :   case MCK_GPRMM16AsmRegZero:
    3346             :     if (Operand.isMM16AsmRegZero())
    3347             :       return MCTargetAsmParser::Match_Success;
    3348             :     break;
    3349             :   // 'HI32DSPAsmReg' class
    3350           9 :   case MCK_HI32DSPAsmReg:
    3351             :     if (Operand.isACCAsmReg())
    3352             :       return MCTargetAsmParser::Match_Success;
    3353             :     break;
    3354             :   // 'HWRegsAsmReg' class
    3355         117 :   case MCK_HWRegsAsmReg:
    3356             :     if (Operand.isHWRegsAsmReg())
    3357             :       return MCTargetAsmParser::Match_Success;
    3358             :     break;
    3359             :   // 'Imm' class
    3360        2962 :   case MCK_Imm:
    3361        2962 :     if (Operand.isImm())
    3362             :       return MCTargetAsmParser::Match_Success;
    3363             :     break;
    3364             :   // 'LO32DSPAsmReg' class
    3365           9 :   case MCK_LO32DSPAsmReg:
    3366             :     if (Operand.isACCAsmReg())
    3367             :       return MCTargetAsmParser::Match_Success;
    3368             :     break;
    3369             :   // 'MSA128AsmReg' class
    3370        2131 :   case MCK_MSA128AsmReg:
    3371             :     if (Operand.isMSA128AsmReg())
    3372             :       return MCTargetAsmParser::Match_Success;
    3373             :     break;
    3374             :   // 'MSACtrlAsmReg' class
    3375          38 :   case MCK_MSACtrlAsmReg:
    3376             :     if (Operand.isMSACtrlAsmReg())
    3377             :       return MCTargetAsmParser::Match_Success;
    3378             :     break;
    3379             :   // 'MicroMipsMemGP' class
    3380           0 :   case MCK_MicroMipsMemGP:
    3381           0 :     if (Operand.isMemWithSimmWordAlignedOffsetGP<9>())
    3382             :       return MCTargetAsmParser::Match_Success;
    3383             :     break;
    3384             :   // 'MicroMipsMem' class
    3385          94 :   case MCK_MicroMipsMem:
    3386          94 :     if (Operand.isMemWithGRPMM16Base())
    3387             :       return MCTargetAsmParser::Match_Success;
    3388             :     break;
    3389             :   // 'MicroMipsMemSP' class
    3390         442 :   case MCK_MicroMipsMemSP:
    3391         442 :     if (Operand.isMemWithUimmWordAlignedOffsetSP<7>())
    3392             :       return MCTargetAsmParser::Match_Success;
    3393             :     break;
    3394             :   // 'InvNum' class
    3395         272 :   case MCK_InvNum:
    3396         272 :     if (Operand.isInvNum())
    3397             :       return MCTargetAsmParser::Match_Success;
    3398             :     break;
    3399             :   // 'JumpTarget' class
    3400        2690 :   case MCK_JumpTarget:
    3401        2690 :     if (Operand.isImm())
    3402             :       return MCTargetAsmParser::Match_Success;
    3403             :     break;
    3404             :   // 'MemOffsetSimm10' class
    3405           7 :   case MCK_MemOffsetSimm10:
    3406           7 :     if (Operand.isMemWithSimmOffset<10>())
    3407             :       return MCTargetAsmParser::Match_Success;
    3408           4 :     return MipsAsmParser::Match_MemSImm10;
    3409             :   // 'MemOffsetSimm10_1' class
    3410           9 :   case MCK_MemOffsetSimm10_1:
    3411           9 :     if (Operand.isMemWithSimmOffset<10, 1>())
    3412             :       return MCTargetAsmParser::Match_Success;
    3413           4 :     return MipsAsmParser::Match_MemSImm10Lsl1;
    3414             :   // 'MemOffsetSimm10_2' class
    3415          10 :   case MCK_MemOffsetSimm10_2:
    3416          10 :     if (Operand.isMemWithSimmOffset<10, 2>())
    3417             :       return MCTargetAsmParser::Match_Success;
    3418           4 :     return MipsAsmParser::Match_MemSImm10Lsl2;
    3419             :   // 'MemOffsetSimm10_3' class
    3420          13 :   case MCK_MemOffsetSimm10_3:
    3421          13 :     if (Operand.isMemWithSimmOffset<10, 3>())
    3422             :       return MCTargetAsmParser::Match_Success;
    3423           4 :     return MipsAsmParser::Match_MemSImm10Lsl3;
    3424             :   // 'MemOffsetSimm11' class
    3425         368 :   case MCK_MemOffsetSimm11:
    3426         368 :     if (Operand.isMemWithSimmOffset<11>())
    3427             :       return MCTargetAsmParser::Match_Success;
    3428         302 :     return MipsAsmParser::Match_MemSImm11;
    3429             :   // 'MemOffsetSimm12' class
    3430         112 :   case MCK_MemOffsetSimm12:
    3431         112 :     if (Operand.isMemWithSimmOffset<12>())
    3432             :       return MCTargetAsmParser::Match_Success;
    3433          67 :     return MipsAsmParser::Match_MemSImm12;
    3434             :   // 'MemOffsetSimm16' class
    3435        1506 :   case MCK_MemOffsetSimm16:
    3436        1506 :     if (Operand.isMemWithSimmOffset<16>())
    3437             :       return MCTargetAsmParser::Match_Success;
    3438         560 :     return MipsAsmParser::Match_MemSImm16;
    3439             :   // 'MemOffsetSimm9' class
    3440        2330 :   case MCK_MemOffsetSimm9:
    3441        2330 :     if (Operand.isMemWithSimmOffset<9>())
    3442             :       return MCTargetAsmParser::Match_Success;
    3443        1715 :     return MipsAsmParser::Match_MemSImm9;
    3444             :   // 'MemOffsetUimm4' class
    3445          30 :   case MCK_MemOffsetUimm4:
    3446          30 :     if (Operand.isMemWithUimmOffsetSP<6>())
    3447             :       return MCTargetAsmParser::Match_Success;
    3448             :     break;
    3449             :   // 'Mem' class
    3450        1916 :   case MCK_Mem:
    3451        1916 :     if (Operand.isMem())
    3452             :       return MCTargetAsmParser::Match_Success;
    3453             :     break;
    3454             :   // 'MovePRegPair' class
    3455          17 :   case MCK_MovePRegPair:
    3456          17 :     if (Operand.isMovePRegPair())
    3457             :       return MCTargetAsmParser::Match_Success;
    3458             :     break;
    3459             :   // 'RegList16' class
    3460          60 :   case MCK_RegList16:
    3461          60 :     if (Operand.isRegList16())
    3462             :       return MCTargetAsmParser::Match_Success;
    3463             :     break;
    3464             :   // 'RegList' class
    3465          71 :   case MCK_RegList:
    3466          71 :     if (Operand.isRegList())
    3467             :       return MCTargetAsmParser::Match_Success;
    3468             :     break;
    3469             :   // 'RegPair' class
    3470          58 :   case MCK_RegPair:
    3471          58 :     if (Operand.isRegPair())
    3472             :       return MCTargetAsmParser::Match_Success;
    3473             :     break;
    3474             :   // 'Simm19_Lsl2' class
    3475         114 :   case MCK_Simm19_Lsl2:
    3476         114 :     if (Operand.isScaledSImm<19, 2>())
    3477             :       return MCTargetAsmParser::Match_Success;
    3478          52 :     return MipsAsmParser::Match_SImm19_Lsl2;
    3479             :   // 'StrictlyAFGR64AsmReg' class
    3480          91 :   case MCK_StrictlyAFGR64AsmReg:
    3481             :     if (Operand.isStrictlyFGRAsmReg())
    3482             :       return MCTargetAsmParser::Match_Success;
    3483             :     break;
    3484             :   // 'StrictlyFGR32AsmReg' class
    3485          66 :   case MCK_StrictlyFGR32AsmReg:
    3486             :     if (Operand.isStrictlyFGRAsmReg())
    3487             :       return MCTargetAsmParser::Match_Success;
    3488             :     break;
    3489             :   // 'StrictlyFGR64AsmReg' class
    3490          52 :   case MCK_StrictlyFGR64AsmReg:
    3491             :     if (Operand.isStrictlyFGRAsmReg())
    3492             :       return MCTargetAsmParser::Match_Success;
    3493             :     break;
    3494             :   // 'ConstantImmz' class
    3495          12 :   case MCK_ConstantImmz:
    3496          12 :     if (Operand.isConstantImmz())
    3497             :       return MCTargetAsmParser::Match_Success;
    3498           8 :     return MipsAsmParser::Match_Immz;
    3499             :   // 'ConstantUImm1_0' class
    3500          21 :   case MCK_ConstantUImm1_0:
    3501          21 :     if (Operand.isConstantUImm<1, 0>())
    3502             :       return MCTargetAsmParser::Match_Success;
    3503          14 :     return MipsAsmParser::Match_UImm1_0;
    3504             :   // 'ConstantUImm2_0' class
    3505          53 :   case MCK_ConstantUImm2_0:
    3506          53 :     if (Operand.isConstantUImm<2, 0>())
    3507             :       return MCTargetAsmParser::Match_Success;
    3508          40 :     return MipsAsmParser::Match_UImm2_0;
    3509             :   // 'ConstantUImm2_1' class
    3510          78 :   case MCK_ConstantUImm2_1:
    3511          78 :     if (Operand.isConstantUImm<2, 1>())
    3512             :       return MCTargetAsmParser::Match_Success;
    3513          57 :     return MipsAsmParser::Match_UImm2_1;
    3514             :   // 'ConstantUImm3_0' class
    3515         292 :   case MCK_ConstantUImm3_0:
    3516         292 :     if (Operand.isConstantUImm<3, 0>())
    3517             :       return MCTargetAsmParser::Match_Success;
    3518         154 :     return MipsAsmParser::Match_UImm3_0;
    3519             :   // 'ConstantSImm4_0' class
    3520          11 :   case MCK_ConstantSImm4_0:
    3521          11 :     if (Operand.isConstantSImm<4, 0>())
    3522             :       return MCTargetAsmParser::Match_Success;
    3523           6 :     return MipsAsmParser::Match_SImm4_0;
    3524             :   // 'ConstantUImm4_0' class
    3525         319 :   case MCK_ConstantUImm4_0:
    3526         319 :     if (Operand.isConstantUImm<4, 0>())
    3527             :       return MCTargetAsmParser::Match_Success;
    3528         228 :     return MipsAsmParser::Match_UImm4_0;
    3529             :   // 'ConstantSImm5_0' class
    3530          60 :   case MCK_ConstantSImm5_0:
    3531          60 :     if (Operand.isConstantSImm<5, 0>())
    3532             :       return MCTargetAsmParser::Match_Success;
    3533          40 :     return MipsAsmParser::Match_SImm5_0;
    3534             :   // 'ConstantUImm5_0' class
    3535        2325 :   case MCK_ConstantUImm5_0:
    3536        2325 :     if (Operand.isConstantUImm<5, 0>())
    3537             :       return MCTargetAsmParser::Match_Success;
    3538        1420 :     return MipsAsmParser::Match_UImm5_0;
    3539             :   // 'ConstantUImm5_1' class
    3540         103 :   case MCK_ConstantUImm5_1:
    3541         103 :     if (Operand.isConstantUImm<5, 1>())
    3542             :       return MCTargetAsmParser::Match_Success;
    3543          70 :     return MipsAsmParser::Match_UImm5_1;
    3544             :   // 'ConstantUImm5_32_Norm' class
    3545          16 :   case MCK_ConstantUImm5_32_Norm:
    3546          16 :     if (Operand.isConstantUImm<5, 32>())
    3547             :       return MCTargetAsmParser::Match_Success;
    3548          10 :     return MipsAsmParser::Match_UImm5_32;
    3549             :   // 'ConstantUImm5_32' class
    3550          46 :   case MCK_ConstantUImm5_32:
    3551          46 :     if (Operand.isConstantUImm<5, 32>())
    3552             :       return MCTargetAsmParser::Match_Success;
    3553          20 :     return MipsAsmParser::Match_UImm5_32;
    3554             :   // 'ConstantUImm5_0_Report_UImm6' class
    3555          27 :   case MCK_ConstantUImm5_0_Report_UImm6:
    3556          27 :     if (Operand.isConstantUImm<5, 0>())
    3557             :       return MCTargetAsmParser::Match_Success;
    3558          12 :     return MipsAsmParser::Match_UImm5_0_Report_UImm6;
    3559             :   // 'ConstantUImm5_33' class
    3560          13 :   case MCK_ConstantUImm5_33:
    3561          13 :     if (Operand.isConstantUImm<5, 33>())
    3562             :       return MCTargetAsmParser::Match_Success;
    3563           8 :     return MipsAsmParser::Match_UImm5_33;
    3564             :   // 'ConstantUImmRange2_64' class
    3565          15 :   case MCK_ConstantUImmRange2_64:
    3566          15 :     if (Operand.isConstantUImmRange<2, 64>())
    3567             :       return MCTargetAsmParser::Match_Success;
    3568           8 :     return MipsAsmParser::Match_UImmRange2_64;
    3569             :   // 'UImm5Lsl2' class
    3570          37 :   case MCK_UImm5Lsl2:
    3571          37 :     if (Operand.isScaledUImm<5, 2>())
    3572             :       return MCTargetAsmParser::Match_Success;
    3573          32 :     return MipsAsmParser::Match_UImm5_Lsl2;
    3574             :   // 'ConstantSImm6_0' class
    3575          22 :   case MCK_ConstantSImm6_0:
    3576          22 :     if (Operand.isConstantSImm<6, 0>())
    3577             :       return MCTargetAsmParser::Match_Success;
    3578           8 :     return MipsAsmParser::Match_SImm6_0;
    3579             :   // 'ConstantUImm6_0' class
    3580         524 :   case MCK_ConstantUImm6_0:
    3581         524 :     if (Operand.isConstantUImm<6, 0>())
    3582             :       return MCTargetAsmParser::Match_Success;
    3583         363 :     return MipsAsmParser::Match_UImm6_0;
    3584             :   // 'UImm6Lsl2' class
    3585          13 :   case MCK_UImm6Lsl2:
    3586          13 :     if (Operand.isScaledUImm<6, 2>())
    3587             :       return MCTargetAsmParser::Match_Success;
    3588           8 :     return MipsAsmParser::Match_UImm6_Lsl2;
    3589             :   // 'ConstantUImm7_0' class
    3590          19 :   case MCK_ConstantUImm7_0:
    3591          19 :     if (Operand.isConstantUImm<7, 0>())
    3592             :       return MCTargetAsmParser::Match_Success;
    3593           8 :     return MipsAsmParser::Match_UImm7_0;
    3594             :   // 'UImm7_N1' class
    3595          20 :   case MCK_UImm7_N1:
    3596          20 :     if (Operand.isConstantUImm<7, -1>())
    3597             :       return MCTargetAsmParser::Match_Success;
    3598          12 :     return MipsAsmParser::Match_UImm7_N1;
    3599             :   // 'ConstantUImm8_0' class
    3600          42 :   case MCK_ConstantUImm8_0:
    3601          42 :     if (Operand.isConstantUImm<8, 0>())
    3602             :       return MCTargetAsmParser::Match_Success;
    3603          27 :     return MipsAsmParser::Match_UImm8_0;
    3604             :   // 'SImm7Lsl2' class
    3605           0 :   case MCK_SImm7Lsl2:
    3606           0 :     if (Operand.isScaledSImm<7, 2>())
    3607             :       return MCTargetAsmParser::Match_Success;
    3608           0 :     return MipsAsmParser::Match_SImm7_Lsl2;
    3609             :   // 'ConstantSImm9_0' class
    3610           0 :   case MCK_ConstantSImm9_0:
    3611           0 :     if (Operand.isConstantSImm<9, 0>())
    3612             :       return MCTargetAsmParser::Match_Success;
    3613           0 :     return MipsAsmParser::Match_SImm9_0;
    3614             :   // 'ConstantSImm10_0' class
    3615          44 :   case MCK_ConstantSImm10_0:
    3616          44 :     if (Operand.isConstantSImm<10, 0>())
    3617             :       return MCTargetAsmParser::Match_Success;
    3618          26 :     return MipsAsmParser::Match_SImm10_0;
    3619             :   // 'ConstantUImm10_0' class
    3620         395 :   case MCK_ConstantUImm10_0:
    3621         395 :     if (Operand.isConstantUImm<10, 0>())
    3622             :       return MCTargetAsmParser::Match_Success;
    3623         164 :     return MipsAsmParser::Match_UImm10_0;
    3624             :   // 'SImm10Lsl1' class
    3625           0 :   case MCK_SImm10Lsl1:
    3626           0 :     if (Operand.isScaledSImm<10, 1>())
    3627             :       return MCTargetAsmParser::Match_Success;
    3628           0 :     return MipsAsmParser::Match_SImm10_Lsl1;
    3629             :   // 'ConstantSImm11_0' class
    3630           0 :   case MCK_ConstantSImm11_0:
    3631           0 :     if (Operand.isConstantSImm<11, 0>())
    3632             :       return MCTargetAsmParser::Match_Success;
    3633           0 :     return MipsAsmParser::Match_SImm11_0;
    3634             :   // 'SImm10Lsl2' class
    3635           0 :   case MCK_SImm10Lsl2:
    3636           0 :     if (Operand.isScaledSImm<10, 2>())
    3637             :       return MCTargetAsmParser::Match_Success;
    3638           0 :     return MipsAsmParser::Match_SImm10_Lsl2;
    3639             :   // 'SImm10Lsl3' class
    3640           0 :   case MCK_SImm10Lsl3:
    3641           0 :     if (Operand.isScaledSImm<10, 3>())
    3642             :       return MCTargetAsmParser::Match_Success;
    3643           0 :     return MipsAsmParser::Match_SImm10_Lsl3;
    3644             :   // 'SImm16' class
    3645        3825 :   case MCK_SImm16:
    3646        3825 :     if (Operand.isSImm<16>())
    3647             :       return MCTargetAsmParser::Match_Success;
    3648        1873 :     return MipsAsmParser::Match_SImm16;
    3649             :   // 'SImm16_Relaxed' class
    3650        1094 :   case MCK_SImm16_Relaxed:
    3651        1094 :     if (Operand.isAnyImm<16>())
    3652             :       return MCTargetAsmParser::Match_Success;
    3653         594 :     return MipsAsmParser::Match_SImm16_Relaxed;
    3654             :   // 'UImm16_AltRelaxed' class
    3655          21 :   case MCK_UImm16_AltRelaxed:
    3656          21 :     if (Operand.isUImm<16>())
    3657             :       return MCTargetAsmParser::Match_Success;
    3658          10 :     return MipsAsmParser::Match_UImm16_AltRelaxed;
    3659             :   // 'UImm16' class
    3660         916 :   case MCK_UImm16:
    3661         916 :     if (Operand.isUImm<16>())
    3662             :       return MCTargetAsmParser::Match_Success;
    3663         585 :     return MipsAsmParser::Match_UImm16;
    3664             :   // 'SImm19Lsl2' class
    3665           0 :   case MCK_SImm19Lsl2:
    3666           0 :     if (Operand.isScaledSImm<19, 2>())
    3667             :       return MCTargetAsmParser::Match_Success;
    3668           0 :     return MipsAsmParser::Match_SImm19_Lsl2;
    3669             :   // 'UImm16_Relaxed' class
    3670         158 :   case MCK_UImm16_Relaxed:
    3671         158 :     if (Operand.isAnyImm<16>())
    3672             :       return MCTargetAsmParser::Match_Success;
    3673           0 :     return MipsAsmParser::Match_UImm16_Relaxed;
    3674             :   // 'ConstantUImm20_0' class
    3675          50 :   case MCK_ConstantUImm20_0:
    3676          50 :     if (Operand.isConstantUImm<20, 0>())
    3677             :       return MCTargetAsmParser::Match_Success;
    3678          17 :     return MipsAsmParser::Match_UImm20_0;
    3679             :   // 'ConstantUImm26_0' class
    3680           0 :   case MCK_ConstantUImm26_0:
    3681           0 :     if (Operand.isConstantUImm<26, 0>())
    3682             :       return MCTargetAsmParser::Match_Success;
    3683           0 :     return MipsAsmParser::Match_UImm26_0;
    3684             :   // 'SImm32' class
    3685         198 :   case MCK_SImm32:
    3686         198 :     if (Operand.isSImm<32>())
    3687             :       return MCTargetAsmParser::Match_Success;
    3688         148 :     return MipsAsmParser::Match_SImm32;
    3689             :   // 'SImm32_Relaxed' class
    3690        1635 :   case MCK_SImm32_Relaxed:
    3691        1635 :     if (Operand.isAnyImm<33>())
    3692             :       return MCTargetAsmParser::Match_Success;
    3693         987 :     return MipsAsmParser::Match_SImm32_Relaxed;
    3694             :   // 'UImm32_Coerced' class
    3695         209 :   case MCK_UImm32_Coerced:
    3696         209 :     if (Operand.isSImm<33>())
    3697             :       return MCTargetAsmParser::Match_Success;
    3698           3 :     return MipsAsmParser::Match_UImm32_Coerced;
    3699             :   } // end switch (Kind)
    3700             : 
    3701       13236 :   if (Operand.isReg()) {
    3702             :     MatchClassKind OpKind;
    3703         502 :     switch (Operand.getReg()) {
    3704             :     default: OpKind = InvalidMatchClass; break;
    3705             :     case Mips::ZERO: OpKind = MCK_GPR32ZERO; break;
    3706             :     case Mips::AT: OpKind = MCK_GPR32NONZERO; break;
    3707             :     case Mips::V0: OpKind = MCK_Reg11; break;
    3708             :     case Mips::V1: OpKind = MCK_Reg11; break;
    3709             :     case Mips::A0: OpKind = MCK_Reg8; break;
    3710             :     case Mips::A1: OpKind = MCK_Reg8; break;
    3711             :     case Mips::A2: OpKind = MCK_Reg8; break;
    3712             :     case Mips::A3: OpKind = MCK_Reg8; break;
    3713             :     case Mips::T0: OpKind = MCK_GPR32NONZERO; break;
    3714             :     case Mips::T1: OpKind = MCK_GPR32NONZERO; break;
    3715             :     case Mips::T2: OpKind = MCK_GPR32NONZERO; break;
    3716             :     case Mips::T3: OpKind = MCK_GPR32NONZERO; break;
    3717             :     case Mips::T4: OpKind = MCK_GPR32NONZERO; break;
    3718             :     case Mips::T5: OpKind = MCK_GPR32NONZERO; break;
    3719             :     case Mips::T6: OpKind = MCK_GPR32NONZERO; break;
    3720             :     case Mips::T7: OpKind = MCK_GPR32NONZERO; break;
    3721             :     case Mips::S0: OpKind = MCK_Reg9; break;
    3722             :     case Mips::S1: OpKind = MCK_Reg11; break;
    3723             :     case Mips::S2: OpKind = MCK_Reg10; break;
    3724             :     case Mips::S3: OpKind = MCK_Reg10; break;
    3725             :     case Mips::S4: OpKind = MCK_Reg10; break;
    3726             :     case Mips::S5: OpKind = MCK_GPR32NONZERO; break;
    3727             :     case Mips::S6: OpKind = MCK_GPR32NONZERO; break;
    3728             :     case Mips::S7: OpKind = MCK_GPR32NONZERO; break;
    3729             :     case Mips::T8: OpKind = MCK_GPR32NONZERO; break;
    3730             :     case Mips::T9: OpKind = MCK_GPR32NONZERO; break;
    3731             :     case Mips::K0: OpKind = MCK_GPR32NONZERO; break;
    3732             :     case Mips::K1: OpKind = MCK_GPR32NONZERO; break;
    3733             :     case Mips::GP: OpKind = MCK_GP32; break;
    3734             :     case Mips::SP: OpKind = MCK_CPUSPReg; break;
    3735             :     case Mips::FP: OpKind = MCK_GPR32NONZERO; break;
    3736             :     case Mips::RA: OpKind = MCK_CPURAReg; break;
    3737             :     case Mips::ZERO_64: OpKind = MCK_Reg15; break;
    3738             :     case Mips::AT_64: OpKind = MCK_Reg20; break;
    3739             :     case Mips::V0_64: OpKind = MCK_Reg26; break;
    3740             :     case Mips::V1_64: OpKind = MCK_Reg26; break;
    3741             :     case Mips::A0_64: OpKind = MCK_Reg23; break;
    3742             :     case Mips::A1_64: OpKind = MCK_Reg23; break;
    3743             :     case Mips::A2_64: OpKind = MCK_Reg23; break;
    3744             :     case Mips::A3_64: OpKind = MCK_Reg23; break;
    3745             :     case Mips::T0_64: OpKind = MCK_Reg20; break;
    3746             :     case Mips::T1_64: OpKind = MCK_Reg20; break;
    3747             :     case Mips::T2_64: OpKind = MCK_Reg20; break;
    3748             :     case Mips::T3_64: OpKind = MCK_Reg20; break;
    3749             :     case Mips::T4_64: OpKind = MCK_Reg20; break;
    3750             :     case Mips::T5_64: OpKind = MCK_Reg20; break;
    3751             :     case Mips::T6_64: OpKind = MCK_Reg20; break;
    3752             :     case Mips::T7_64: OpKind = MCK_Reg20; break;
    3753             :     case Mips::S0_64: OpKind = MCK_Reg24; break;
    3754             :     case Mips::S1_64: OpKind = MCK_Reg26; break;
    3755             :     case Mips::S2_64: OpKind = MCK_Reg25; break;
    3756             :     case Mips::S3_64: OpKind = MCK_Reg25; break;
    3757             :     case Mips::S4_64: OpKind = MCK_Reg25; break;
    3758             :     case Mips::S5_64: OpKind = MCK_Reg20; break;
    3759             :     case Mips::S6_64: OpKind = MCK_Reg20; break;
    3760             :     case Mips::S7_64: OpKind = MCK_Reg20; break;
    3761             :     case Mips::T8_64: OpKind = MCK_Reg20; break;
    3762             :     case Mips::T9_64: OpKind = MCK_Reg20; break;
    3763             :     case Mips::K0_64: OpKind = MCK_Reg20; break;
    3764             :     case Mips::K1_64: OpKind = MCK_Reg20; break;
    3765             :     case Mips::GP_64: OpKind = MCK_GP64; break;
    3766             :     case Mips::SP_64: OpKind = MCK_SP64; break;
    3767             :     case Mips::FP_64: OpKind = MCK_Reg20; break;
    3768             :     case Mips::RA_64: OpKind = MCK_Reg29; break;
    3769             :     case Mips::F0: OpKind = MCK_FGR32; break;
    3770             :     case Mips::F1: OpKind = MCK_Reg31; break;
    3771             :     case Mips::F2: OpKind = MCK_FGR32; break;
    3772             :     case Mips::F3: OpKind = MCK_Reg31; break;
    3773             :     case Mips::F4: OpKind = MCK_FGR32; break;
    3774             :     case Mips::F5: OpKind = MCK_Reg31; break;
    3775             :     case Mips::F6: OpKind = MCK_FGR32; break;
    3776             :     case Mips::F7: OpKind = MCK_Reg31; break;
    3777             :     case Mips::F8: OpKind = MCK_FGR32; break;
    3778             :     case Mips::F9: OpKind = MCK_Reg31; break;
    3779             :     case Mips::F10: OpKind = MCK_FGR32; break;
    3780             :     case Mips::F11: OpKind = MCK_Reg31; break;
    3781             :     case Mips::F12: OpKind = MCK_FGR32; break;
    3782             :     case Mips::F13: OpKind = MCK_Reg31; break;
    3783             :     case Mips::F14: OpKind = MCK_FGR32; break;
    3784             :     case Mips::F15: OpKind = MCK_Reg31; break;
    3785             :     case Mips::F16: OpKind = MCK_FGR32; break;
    3786             :     case Mips::F17: OpKind = MCK_Reg31; break;
    3787             :     case Mips::F18: OpKind = MCK_FGR32; break;
    3788             :     case Mips::F19: OpKind = MCK_Reg31; break;
    3789             :     case Mips::F20: OpKind = MCK_FGR32; break;
    3790             :     case Mips::F21: OpKind = MCK_Reg31; break;
    3791             :     case Mips::F22: OpKind = MCK_FGR32; break;
    3792             :     case Mips::F23: OpKind = MCK_Reg31; break;
    3793             :     case Mips::F24: OpKind = MCK_FGR32; break;
    3794             :     case Mips::F25: OpKind = MCK_Reg31; break;
    3795             :     case Mips::F26: OpKind = MCK_FGR32; break;
    3796             :     case Mips::F27: OpKind = MCK_Reg31; break;
    3797             :     case Mips::F28: OpKind = MCK_FGR32; break;
    3798             :     case Mips::F29: OpKind = MCK_Reg31; break;
    3799             :     case Mips::F30: OpKind = MCK_FGR32; break;
    3800             :     case Mips::F31: OpKind = MCK_Reg31; break;
    3801             :     case Mips::F_HI0: OpKind = MCK_FGRH32; break;
    3802             :     case Mips::F_HI1: OpKind = MCK_Reg34; break;
    3803             :     case Mips::F_HI2: OpKind = MCK_FGRH32; break;
    3804             :     case Mips::F_HI3: OpKind = MCK_Reg34; break;
    3805             :     case Mips::F_HI4: OpKind = MCK_FGRH32; break;
    3806             :     case Mips::F_HI5: OpKind = MCK_Reg34; break;
    3807             :     case Mips::F_HI6: OpKind = MCK_FGRH32; break;
    3808             :     case Mips::F_HI7: OpKind = MCK_Reg34; break;
    3809             :     case Mips::F_HI8: OpKind = MCK_FGRH32; break;
    3810             :     case Mips::F_HI9: OpKind = MCK_Reg34; break;
    3811             :     case Mips::F_HI10: OpKind = MCK_FGRH32; break;
    3812             :     case Mips::F_HI11: OpKind = MCK_Reg34; break;
    3813             :     case Mips::F_HI12: OpKind = MCK_FGRH32; break;
    3814             :     case Mips::F_HI13: OpKind = MCK_Reg34; break;
    3815             :     case Mips::F_HI14: OpKind = MCK_FGRH32; break;
    3816             :     case Mips::F_HI15: OpKind = MCK_Reg34; break;
    3817             :     case Mips::F_HI16: OpKind = MCK_FGRH32; break;
    3818             :     case Mips::F_HI17: OpKind = MCK_Reg34; break;
    3819             :     case Mips::F_HI18: OpKind = MCK_FGRH32; break;
    3820             :     case Mips::F_HI19: OpKind = MCK_Reg34; break;
    3821             :     case Mips::F_HI20: OpKind = MCK_FGRH32; break;
    3822             :     case Mips::F_HI21: OpKind = MCK_Reg34; break;
    3823             :     case Mips::F_HI22: OpKind = MCK_FGRH32; break;
    3824             :     case Mips::F_HI23: OpKind = MCK_Reg34; break;
    3825             :     case Mips::F_HI24: OpKind = MCK_FGRH32; break;
    3826             :     case Mips::F_HI25: OpKind = MCK_Reg34; break;
    3827             :     case Mips::F_HI26: OpKind = MCK_FGRH32; break;
    3828             :     case Mips::F_HI27: OpKind = MCK_Reg34; break;
    3829             :     case Mips::F_HI28: OpKind = MCK_FGRH32; break;
    3830             :     case Mips::F_HI29: OpKind = MCK_Reg34; break;
    3831             :     case Mips::F_HI30: OpKind = MCK_FGRH32; break;
    3832             :     case Mips::F_HI31: OpKind = MCK_Reg34; break;
    3833             :     case Mips::D0: OpKind = MCK_AFGR64; break;
    3834             :     case Mips::D1: OpKind = MCK_Reg36; break;
    3835             :     case Mips::D2: OpKind = MCK_AFGR64; break;
    3836             :     case Mips::D3: OpKind = MCK_Reg36; break;
    3837             :     case Mips::D4: OpKind = MCK_AFGR64; break;
    3838             :     case Mips::D5: OpKind = MCK_Reg36; break;
    3839             :     case Mips::D6: OpKind = MCK_AFGR64; break;
    3840             :     case Mips::D7: OpKind = MCK_Reg36; break;
    3841             :     case Mips::D8: OpKind = MCK_AFGR64; break;
    3842             :     case Mips::D9: OpKind = MCK_Reg36; break;
    3843             :     case Mips::D10: OpKind = MCK_AFGR64; break;
    3844             :     case Mips::D11: OpKind = MCK_Reg36; break;
    3845             :     case Mips::D12: OpKind = MCK_AFGR64; break;
    3846             :     case Mips::D13: OpKind = MCK_Reg36; break;
    3847             :     case Mips::D14: OpKind = MCK_AFGR64; break;
    3848             :     case Mips::D15: OpKind = MCK_Reg36; break;
    3849             :     case Mips::D0_64: OpKind = MCK_FGR64; break;
    3850             :     case Mips::D1_64: OpKind = MCK_Reg39; break;
    3851             :     case Mips::D2_64: OpKind = MCK_FGR64; break;
    3852             :     case Mips::D3_64: OpKind = MCK_Reg39; break;
    3853             :     case Mips::D4_64: OpKind = MCK_FGR64; break;
    3854             :     case Mips::D5_64: OpKind = MCK_Reg39; break;
    3855             :     case Mips::D6_64: OpKind = MCK_FGR64; break;
    3856             :     case Mips::D7_64: OpKind = MCK_Reg39; break;
    3857             :     case Mips::D8_64: OpKind = MCK_FGR64; break;
    3858             :     case Mips::D9_64: OpKind = MCK_Reg39; break;
    3859             :     case Mips::D10_64: OpKind = MCK_FGR64; break;
    3860             :     case Mips::D11_64: OpKind = MCK_Reg39; break;
    3861             :     case Mips::D12_64: OpKind = MCK_FGR64; break;
    3862             :     case Mips::D13_64: OpKind = MCK_Reg39; break;
    3863             :     case Mips::D14_64: OpKind = MCK_FGR64; break;
    3864             :     case Mips::D15_64: OpKind = MCK_Reg39; break;
    3865             :     case Mips::D16_64: OpKind = MCK_FGR64; break;
    3866             :     case Mips::D17_64: OpKind = MCK_Reg39; break;
    3867             :     case Mips::D18_64: OpKind = MCK_FGR64; break;
    3868             :     case Mips::D19_64: OpKind = MCK_Reg39; break;
    3869             :     case Mips::D20_64: OpKind = MCK_FGR64; break;
    3870             :     case Mips::D21_64: OpKind = MCK_Reg39; break;
    3871             :     case Mips::D22_64: OpKind = MCK_FGR64; break;
    3872             :     case Mips::D23_64: OpKind = MCK_Reg39; break;
    3873             :     case Mips::D24_64: OpKind = MCK_FGR64; break;
    3874             :     case Mips::D25_64: OpKind = MCK_Reg39; break;
    3875             :     case Mips::D26_64: OpKind = MCK_FGR64; break;
    3876             :     case Mips::D27_64: OpKind = MCK_Reg39; break;
    3877             :     case Mips::D28_64: OpKind = MCK_FGR64; break;
    3878             :     case Mips::D29_64: OpKind = MCK_Reg39; break;
    3879             :     case Mips::D30_64: OpKind = MCK_FGR64; break;
    3880             :     case Mips::D31_64: OpKind = MCK_Reg39; break;
    3881             :     case Mips::W0: OpKind = MCK_MSA128WEvens; break;
    3882             :     case Mips::W1: OpKind = MCK_Reg42; break;
    3883             :     case Mips::W2: OpKind = MCK_MSA128WEvens; break;
    3884             :     case Mips::W3: OpKind = MCK_Reg42; break;
    3885             :     case Mips::W4: OpKind = MCK_MSA128WEvens; break;
    3886             :     case Mips::W5: OpKind = MCK_Reg42; break;
    3887             :     case Mips::W6: OpKind = MCK_MSA128WEvens; break;
    3888             :     case Mips::W7: OpKind = MCK_Reg42; break;
    3889             :     case Mips::W8: OpKind = MCK_MSA128WEvens; break;
    3890             :     case Mips::W9: OpKind = MCK_Reg42; break;
    3891             :     case Mips::W10: OpKind = MCK_MSA128WEvens; break;
    3892             :     case Mips::W11: OpKind = MCK_Reg42; break;
    3893             :     case Mips::W12: OpKind = MCK_MSA128WEvens; break;
    3894             :     case Mips::W13: OpKind = MCK_Reg42; break;
    3895             :     case Mips::W14: OpKind = MCK_MSA128WEvens; break;
    3896             :     case Mips::W15: OpKind = MCK_Reg42; break;
    3897             :     case Mips::W16: OpKind = MCK_MSA128WEvens; break;
    3898             :     case Mips::W17: OpKind = MCK_Reg42; break;
    3899             :     case Mips::W18: OpKind = MCK_MSA128WEvens; break;
    3900             :     case Mips::W19: OpKind = MCK_Reg42; break;
    3901             :     case Mips::W20: OpKind = MCK_MSA128WEvens; break;
    3902             :     case Mips::W21: OpKind = MCK_Reg42; break;
    3903             :     case Mips::W22: OpKind = MCK_MSA128WEvens; break;
    3904             :     case Mips::W23: OpKind = MCK_Reg42; break;
    3905             :     case Mips::W24: OpKind = MCK_MSA128WEvens; break;
    3906             :     case Mips::W25: OpKind = MCK_Reg42; break;
    3907             :     case Mips::W26: OpKind = MCK_MSA128WEvens; break;
    3908             :     case Mips::W27: OpKind = MCK_Reg42; break;
    3909             :     case Mips::W28: OpKind = MCK_MSA128WEvens; break;
    3910             :     case Mips::W29: OpKind = MCK_Reg42; break;
    3911             :     case Mips::W30: OpKind = MCK_MSA128WEvens; break;
    3912             :     case Mips::W31: OpKind = MCK_Reg42; break;
    3913             :     case Mips::HI0: OpKind = MCK_HI32; break;
    3914             :     case Mips::HI1: OpKind = MCK_HI32DSP; break;
    3915             :     case Mips::HI2: OpKind = MCK_HI32DSP; break;
    3916             :     case Mips::HI3: OpKind = MCK_HI32DSP; break;
    3917             :     case Mips::LO0: OpKind = MCK_LO32; break;
    3918             :     case Mips::LO1: OpKind = MCK_LO32DSP; break;
    3919             :     case Mips::LO2: OpKind = MCK_LO32DSP; break;
    3920             :     case Mips::LO3: OpKind = MCK_LO32DSP; break;
    3921             :     case Mips::HI0_64: OpKind = MCK_HI64; break;
    3922             :     case Mips::LO0_64: OpKind = MCK_LO64; break;
    3923             :     case Mips::FCR0: OpKind = MCK_CCR; break;
    3924             :     case Mips::FCR1: OpKind = MCK_CCR; break;
    3925             :     case Mips::FCR2: OpKind = MCK_CCR; break;
    3926             :     case Mips::FCR3: OpKind = MCK_CCR; break;
    3927             :     case Mips::FCR4: OpKind = MCK_CCR; break;
    3928             :     case Mips::FCR5: OpKind = MCK_CCR; break;
    3929             :     case Mips::FCR6: OpKind = MCK_CCR; break;
    3930             :     case Mips::FCR7: OpKind = MCK_CCR; break;
    3931             :     case Mips::FCR8: OpKind = MCK_CCR; break;
    3932             :     case Mips::FCR9: OpKind = MCK_CCR; break;
    3933             :     case Mips::FCR10: OpKind = MCK_CCR; break;
    3934             :     case Mips::FCR11: OpKind = MCK_CCR; break;
    3935             :     case Mips::FCR12: OpKind = MCK_CCR; break;
    3936             :     case Mips::FCR13: OpKind = MCK_CCR; break;
    3937             :     case Mips::FCR14: OpKind = MCK_CCR; break;
    3938             :     case Mips::FCR15: OpKind = MCK_CCR; break;
    3939             :     case Mips::FCR16: OpKind = MCK_CCR; break;
    3940             :     case Mips::FCR17: OpKind = MCK_CCR; break;
    3941             :     case Mips::FCR18: OpKind = MCK_CCR; break;
    3942             :     case Mips::FCR19: OpKind = MCK_CCR; break;
    3943             :     case Mips::FCR20: OpKind = MCK_CCR; break;
    3944             :     case Mips::FCR21: OpKind = MCK_CCR; break;
    3945             :     case Mips::FCR22: OpKind = MCK_CCR; break;
    3946             :     case Mips::FCR23: OpKind = MCK_CCR; break;
    3947             :     case Mips::FCR24: OpKind = MCK_CCR; break;
    3948             :     case Mips::FCR25: OpKind = MCK_CCR; break;
    3949             :     case Mips::FCR26: OpKind = MCK_CCR; break;
    3950             :     case Mips::FCR27: OpKind = MCK_CCR; break;
    3951             :     case Mips::FCR28: OpKind = MCK_CCR; break;
    3952             :     case Mips::FCR29: OpKind = MCK_CCR; break;
    3953             :     case Mips::FCR30: OpKind = MCK_CCR; break;
    3954             :     case Mips::FCR31: OpKind = MCK_CCR; break;
    3955             :     case Mips::FCC0: OpKind = MCK_FCC; break;
    3956             :     case Mips::FCC1: OpKind = MCK_FCC; break;
    3957             :     case Mips::FCC2: OpKind = MCK_FCC; break;
    3958             :     case Mips::FCC3: OpKind = MCK_FCC; break;
    3959             :     case Mips::FCC4: OpKind = MCK_FCC; break;
    3960             :     case Mips::FCC5: OpKind = MCK_FCC; break;
    3961             :     case Mips::FCC6: OpKind = MCK_FCC; break;
    3962             :     case Mips::FCC7: OpKind = MCK_FCC; break;
    3963             :     case Mips::COP00: OpKind = MCK_COP0; break;
    3964             :     case Mips::COP01: OpKind = MCK_COP0; break;
    3965             :     case Mips::COP02: OpKind = MCK_COP0; break;
    3966             :     case Mips::COP03: OpKind = MCK_COP0; break;
    3967             :     case Mips::COP04: OpKind = MCK_COP0; break;
    3968             :     case Mips::COP05: OpKind = MCK_COP0; break;
    3969             :     case Mips::COP06: OpKind = MCK_COP0; break;
    3970             :     case Mips::COP07: OpKind = MCK_COP0; break;
    3971             :     case Mips::COP08: OpKind = MCK_COP0; break;
    3972             :     case Mips::COP09: OpKind = MCK_COP0; break;
    3973             :     case Mips::COP010: OpKind = MCK_COP0; break;
    3974             :     case Mips::COP011: OpKind = MCK_COP0; break;
    3975             :     case Mips::COP012: OpKind = MCK_COP0; break;
    3976             :     case Mips::COP013: OpKind = MCK_COP0; break;
    3977             :     case Mips::COP014: OpKind = MCK_COP0; break;
    3978             :     case Mips::COP015: OpKind = MCK_COP0; break;
    3979             :     case Mips::COP016: OpKind = MCK_COP0; break;
    3980             :     case Mips::COP017: OpKind = MCK_COP0; break;
    3981             :     case Mips::COP018: OpKind = MCK_COP0; break;
    3982             :     case Mips::COP019: OpKind = MCK_COP0; break;
    3983             :     case Mips::COP020: OpKind = MCK_COP0; break;
    3984             :     case Mips::COP021: OpKind = MCK_COP0; break;
    3985             :     case Mips::COP022: OpKind = MCK_COP0; break;
    3986             :     case Mips::COP023: OpKind = MCK_COP0; break;
    3987             :     case Mips::COP024: OpKind = MCK_COP0; break;
    3988             :     case Mips::COP025: OpKind = MCK_COP0; break;
    3989             :     case Mips::COP026: OpKind = MCK_COP0; break;
    3990             :     case Mips::COP027: OpKind = MCK_COP0; break;
    3991             :     case Mips::COP028: OpKind = MCK_COP0; break;
    3992             :     case Mips::COP029: OpKind = MCK_COP0; break;
    3993             :     case Mips::COP030: OpKind = MCK_COP0; break;
    3994             :     case Mips::COP031: OpKind = MCK_COP0; break;
    3995             :     case Mips::COP20: OpKind = MCK_COP2; break;
    3996             :     case Mips::COP21: OpKind = MCK_COP2; break;
    3997             :     case Mips::COP22: OpKind = MCK_COP2; break;
    3998             :     case Mips::COP23: OpKind = MCK_COP2; break;
    3999             :     case Mips::COP24: OpKind = MCK_COP2; break;
    4000             :     case Mips::COP25: OpKind = MCK_COP2; break;
    4001             :     case Mips::COP26: OpKind = MCK_COP2; break;
    4002             :     case Mips::COP27: OpKind = MCK_COP2; break;
    4003             :     case Mips::COP28: OpKind = MCK_COP2; break;
    4004             :     case Mips::COP29: OpKind = MCK_COP2; break;
    4005             :     case Mips::COP210: OpKind = MCK_COP2; break;
    4006             :     case Mips::COP211: OpKind = MCK_COP2; break;
    4007             :     case Mips::COP212: OpKind = MCK_COP2; break;
    4008             :     case Mips::COP213: OpKind = MCK_COP2; break;
    4009             :     case Mips::COP214: OpKind = MCK_COP2; break;
    4010             :     case Mips::COP215: OpKind = MCK_COP2; break;
    4011             :     case Mips::COP216: OpKind = MCK_COP2; break;
    4012             :     case Mips::COP217: OpKind = MCK_COP2; break;
    4013             :     case Mips::COP218: OpKind = MCK_COP2; break;
    4014             :     case Mips::COP219: OpKind = MCK_COP2; break;
    4015             :     case Mips::COP220: OpKind = MCK_COP2; break;
    4016             :     case Mips::COP221: OpKind = MCK_COP2; break;
    4017             :     case Mips::COP222: OpKind = MCK_COP2; break;
    4018             :     case Mips::COP223: OpKind = MCK_COP2; break;
    4019             :     case Mips::COP224: OpKind = MCK_COP2; break;
    4020             :     case Mips::COP225: OpKind = MCK_COP2; break;
    4021             :     case Mips::COP226: OpKind = MCK_COP2; break;
    4022             :     case Mips::COP227: OpKind = MCK_COP2; break;
    4023             :     case Mips::COP228: OpKind = MCK_COP2; break;
    4024             :     case Mips::COP229: OpKind = MCK_COP2; break;
    4025             :     case Mips::COP230: OpKind = MCK_COP2; break;
    4026             :     case Mips::COP231: OpKind = MCK_COP2; break;
    4027             :     case Mips::COP30: OpKind = MCK_COP3; break;
    4028             :     case Mips::COP31: OpKind = MCK_COP3; break;
    4029             :     case Mips::COP32: OpKind = MCK_COP3; break;
    4030             :     case Mips::COP33: OpKind = MCK_COP3; break;
    4031             :     case Mips::COP34: OpKind = MCK_COP3; break;
    4032             :     case Mips::COP35: OpKind = MCK_COP3; break;
    4033             :     case Mips::COP36: OpKind = MCK_COP3; break;
    4034             :     case Mips::COP37: OpKind = MCK_COP3; break;
    4035             :     case Mips::COP38: OpKind = MCK_COP3; break;
    4036             :     case Mips::COP39: OpKind = MCK_COP3; break;
    4037             :     case Mips::COP310: OpKind = MCK_COP3; break;
    4038             :     case Mips::COP311: OpKind = MCK_COP3; break;
    4039             :     case Mips::COP312: OpKind = MCK_COP3; break;
    4040             :     case Mips::COP313: OpKind = MCK_COP3; break;
    4041             :     case Mips::COP314: OpKind = MCK_COP3; break;
    4042             :     case Mips::COP315: OpKind = MCK_COP3; break;
    4043             :     case Mips::COP316: OpKind = MCK_COP3; break;
    4044             :     case Mips::COP317: OpKind = MCK_COP3; break;
    4045             :     case Mips::COP318: OpKind = MCK_COP3; break;
    4046             :     case Mips::COP319: OpKind = MCK_COP3; break;
    4047             :     case Mips::COP320: OpKind = MCK_COP3; break;
    4048             :     case Mips::COP321: OpKind = MCK_COP3; break;
    4049             :     case Mips::COP322: OpKind = MCK_COP3; break;
    4050             :     case Mips::COP323: OpKind = MCK_COP3; break;
    4051             :     case Mips::COP324: OpKind = MCK_COP3; break;
    4052             :     case Mips::COP325: OpKind = MCK_COP3; break;
    4053             :     case Mips::COP326: OpKind = MCK_COP3; break;
    4054             :     case Mips::COP327: OpKind = MCK_COP3; break;
    4055             :     case Mips::COP328: OpKind = MCK_COP3; break;
    4056             :     case Mips::COP329: OpKind = MCK_COP3; break;
    4057             :     case Mips::COP330: OpKind = MCK_COP3; break;
    4058             :     case Mips::COP331: OpKind = MCK_COP3; break;
    4059             :     case Mips::PC: OpKind = MCK_PC; break;
    4060             :     case Mips::HWR0: OpKind = MCK_HWRegs; break;
    4061             :     case Mips::HWR1: OpKind = MCK_HWRegs; break;
    4062             :     case Mips::HWR2: OpKind = MCK_HWRegs; break;
    4063             :     case Mips::HWR3: OpKind = MCK_HWRegs; break;
    4064             :     case Mips::HWR4: OpKind = MCK_HWRegs; break;
    4065             :     case Mips::HWR5: OpKind = MCK_HWRegs; break;
    4066             :     case Mips::HWR6: OpKind = MCK_HWRegs; break;
    4067             :     case Mips::HWR7: OpKind = MCK_HWRegs; break;
    4068             :     case Mips::HWR8: OpKind = MCK_HWRegs; break;
    4069             :     case Mips::HWR9: OpKind = MCK_HWRegs; break;
    4070             :     case Mips::HWR10: OpKind = MCK_HWRegs; break;
    4071             :     case Mips::HWR11: OpKind = MCK_HWRegs; break;
    4072             :     case Mips::HWR12: OpKind = MCK_HWRegs; break;
    4073             :     case Mips::HWR13: OpKind = MCK_HWRegs; break;
    4074             :     case Mips::HWR14: OpKind = MCK_HWRegs; break;
    4075             :     case Mips::HWR15: OpKind = MCK_HWRegs; break;
    4076             :     case Mips::HWR16: OpKind = MCK_HWRegs; break;
    4077             :     case Mips::HWR17: OpKind = MCK_HWRegs; break;
    4078             :     case Mips::HWR18: OpKind = MCK_HWRegs; break;
    4079             :     case Mips::HWR19: OpKind = MCK_HWRegs; break;
    4080             :     case Mips::HWR20: OpKind = MCK_HWRegs; break;
    4081             :     case Mips::HWR21: OpKind = MCK_HWRegs; break;
    4082             :     case Mips::HWR22: OpKind = MCK_HWRegs; break;
    4083             :     case Mips::HWR23: OpKind = MCK_HWRegs; break;
    4084             :     case Mips::HWR24: OpKind = MCK_HWRegs; break;
    4085             :     case Mips::HWR25: OpKind = MCK_HWRegs; break;
    4086             :     case Mips::HWR26: OpKind = MCK_HWRegs; break;
    4087             :     case Mips::HWR27: OpKind = MCK_HWRegs; break;
    4088             :     case Mips::HWR28: OpKind = MCK_HWRegs; break;
    4089             :     case Mips::HWR29: OpKind = MCK_HWRegs; break;
    4090             :     case Mips::HWR30: OpKind = MCK_HWRegs; break;
    4091             :     case Mips::HWR31: OpKind = MCK_HWRegs; break;
    4092             :     case Mips::AC0: OpKind = MCK_ACC64; break;
    4093             :     case Mips::AC1: OpKind = MCK_ACC64DSP; break;
    4094             :     case Mips::AC2: OpKind = MCK_ACC64DSP; break;
    4095             :     case Mips::AC3: OpKind = MCK_ACC64DSP; break;
    4096             :     case Mips::AC0_64: OpKind = MCK_ACC128; break;
    4097             :     case Mips::DSPCCond: OpKind = MCK_DSPCC; break;
    4098             :     case Mips::MSAIR: OpKind = MCK_MSACtrl; break;
    4099             :     case Mips::MSACSR: OpKind = MCK_MSACtrl; break;
    4100             :     case Mips::MSAAccess: OpKind = MCK_MSACtrl; break;
    4101             :     case Mips::MSASave: OpKind = MCK_MSACtrl; break;
    4102             :     case Mips::MSAModify: OpKind = MCK_MSACtrl; break;
    4103             :     case Mips::MSARequest: OpKind = MCK_MSACtrl; break;
    4104             :     case Mips::MSAMap: OpKind = MCK_MSACtrl; break;
    4105             :     case Mips::MSAUnmap: OpKind = MCK_MSACtrl; break;
    4106             :     case Mips::MPL0: OpKind = MCK_OCTEON_MPL; break;
    4107             :     case Mips::MPL1: OpKind = MCK_OCTEON_MPL; break;
    4108             :     case Mips::MPL2: OpKind = MCK_OCTEON_MPL; break;
    4109             :     case Mips::P0: OpKind = MCK_OCTEON_P; break;
    4110             :     case Mips::P1: OpKind = MCK_OCTEON_P; break;
    4111             :     case Mips::P2: OpKind = MCK_OCTEON_P; break;
    4112             :     }
    4113         251 :     return isSubclass(OpKind, Kind) ? MCTargetAsmParser::Match_Success :
    4114             :                                       MCTargetAsmParser::Match_InvalidOperand;
    4115             :   }
    4116             : 
    4117             :   return MCTargetAsmParser::Match_InvalidOperand;
    4118             : }
    4119             : 
    4120        1325 : uint64_t MipsAsmParser::
    4121             : ComputeAvailableFeatures(const FeatureBitset& FB) const {
    4122        1325 :   uint64_t Features = 0;
    4123        2650 :   if ((FB[Mips::FeatureMips2]))
    4124        1304 :     Features |= Feature_HasMips2;
    4125        2650 :   if ((FB[Mips::FeatureMips3_32]))
    4126        1288 :     Features |= Feature_HasMips3_32;
    4127        2650 :   if ((FB[Mips::FeatureMips3_32r2]))
    4128         688 :     Features |= Feature_HasMips3_32r2;
    4129        2650 :   if ((FB[Mips::FeatureMips3]))
    4130         380 :     Features |= Feature_HasMips3;
    4131        2650 :   if ((!FB[Mips::FeatureMips3]))
    4132         945 :     Features |= Feature_NotMips3;
    4133        2650 :   if ((FB[Mips::FeatureMips4_32]))
    4134        1268 :     Features |= Feature_HasMips4_32;
    4135        2650 :   if ((!FB[Mips::FeatureMips4_32]))
    4136          57 :     Features |= Feature_NotMips4_32;
    4137        2650 :   if ((FB[Mips::FeatureMips4_32r2]))
    4138         668 :     Features |= Feature_HasMips4_32r2;
    4139        2650 :   if ((FB[Mips::FeatureMips5_32r2]))
    4140         648 :     Features |= Feature_HasMips5_32r2;
    4141        2650 :   if ((FB[Mips::FeatureMips32]))
    4142        1233 :     Features |= Feature_HasMips32;
    4143        2650 :   if ((FB[Mips::FeatureMips32r2]))
    4144         482 :     Features |= Feature_HasMips32r2;
    4145        2650 :   if ((FB[Mips::FeatureMips32r5]))
    4146         196 :     Features |= Feature_HasMips32r5;
    4147        2650 :   if ((FB[Mips::FeatureMips32r6]))
    4148         155 :     Features |= Feature_HasMips32r6;
    4149        2650 :   if ((!FB[Mips::FeatureMips32r6]))
    4150        1170 :     Features |= Feature_NotMips32r6;
    4151        2650 :   if ((FB[Mips::FeatureGP64Bit]))
    4152         386 :     Features |= Feature_IsGP64bit;
    4153        2650 :   if ((!FB[Mips::FeatureGP64Bit]))
    4154         939 :     Features |= Feature_IsGP32bit;
    4155        2650 :   if ((FB[Mips::FeaturePTR64Bit]))
    4156           0 :     Features |= Feature_IsPTR64bit;
    4157        2650 :   if ((!FB[Mips::FeaturePTR64Bit]))
    4158        1325 :     Features |= Feature_IsPTR32bit;
    4159        2650 :   if ((FB[Mips::FeatureMips64]))
    4160         328 :     Features |= Feature_HasMips64;
    4161        2650 :   if ((!FB[Mips::FeatureMips64]))
    4162         997 :     Features |= Feature_NotMips64;
    4163        2650 :   if ((FB[Mips::FeatureMips64r2]))
    4164         178 :     Features |= Feature_HasMips64r2;
    4165        2650 :   if ((FB[Mips::FeatureMips64r6]))
    4166          56 :     Features |= Feature_HasMips64r6;
    4167        2650 :   if ((!FB[Mips::FeatureMips64r6]))
    4168        1269 :     Features |= Feature_NotMips64r6;
    4169        2766 :   if ((FB[Mips::FeatureMicroMips]) && (FB[Mips::FeatureMips32r6]))
    4170          21 :     Features |= Feature_HasMicroMips32r6;
    4171        2766 :   if ((FB[Mips::FeatureMicroMips]) && (FB[Mips::FeatureMips64r6]))
    4172           5 :     Features |= Feature_HasMicroMips64r6;
    4173        2650 :   if ((FB[Mips::FeatureMips16]))
    4174          44 :     Features |= Feature_InMips16Mode;
    4175        2650 :   if ((FB[Mips::FeatureCnMips]))
    4176           9 :     Features |= Feature_HasCnMips;
    4177        2650 :   if ((!FB[Mips::FeatureCnMips]))
    4178        1316 :     Features |= Feature_NotCnMips;
    4179        2650 :   if ((FB[Mips::FeatureSym32]))
    4180           0 :     Features |= Feature_IsSym32;
    4181        2650 :   if ((!FB[Mips::FeatureSym32]))
    4182        1325 :     Features |= Feature_IsSym64;
    4183        2650 :   if ((!FB[Mips::FeatureMips16]))
    4184        1281 :     Features |= Feature_HasStdEnc;
    4185        2650 :   if ((FB[Mips::FeatureMicroMips]))
    4186         116 :     Features |= Feature_InMicroMips;
    4187        2650 :   if ((!FB[Mips::FeatureMicroMips]))
    4188        1209 :     Features |= Feature_NotInMicroMips;
    4189        2660 :   if ((FB[Mips::FeatureEVA]) && (FB[Mips::FeatureMips32r2]))
    4190          10 :     Features |= Feature_HasEVA;
    4191        2650 :   if ((FB[Mips::FeatureMSA]))
    4192          44 :     Features |= Feature_HasMSA;
    4193        2650 :   if ((!FB[Mips::FeatureMadd4]))
    4194        1325 :     Features |= Feature_HasMadd4;
    4195        2650 :   if ((FB[Mips::FeatureMT]))
    4196           7 :     Features |= Feature_HasMT;
    4197        2650 :   if ((FB[Mips::FeatureFP64Bit]))
    4198         512 :     Features |= Feature_IsFP64bit;
    4199        2650 :   if ((!FB[Mips::FeatureFP64Bit]))
    4200         813 :     Features |= Feature_NotFP64bit;
    4201        2650 :   if ((FB[Mips::FeatureSingleFloat]))
    4202           0 :     Features |= Feature_IsSingleFloat;
    4203        2650 :   if ((!FB[Mips::FeatureSingleFloat]))
    4204        1325 :     Features |= Feature_IsNotSingleFloat;
    4205        2650 :   if ((!FB[Mips::FeatureSoftFloat]))
    4206        1273 :     Features |= Feature_IsNotSoftFloat;
    4207        2650 :   if ((FB[Mips::FeatureDSP]))
    4208          18 :     Features |= Feature_HasDSP;
    4209        2650 :   if ((FB[Mips::FeatureDSPR2]))
    4210           5 :     Features |= Feature_HasDSPR2;
    4211        2650 :   if ((FB[Mips::FeatureDSPR3]))
    4212           1 :     Features |= Feature_HasDSPR3;
    4213        1325 :   return Features;
    4214             : }
    4215             : 
    4216             : static const char *const MnemonicTable =
    4217             :     "\003abs\005abs.d\005abs.s\tabsq_s.ph\tabsq_s.qb\010absq_s.w\003add\005a"
    4218             :     "dd.d\005add.s\007add_a.b\007add_a.d\007add_a.h\007add_a.w\004addi\005ad"
    4219             :     "diu\007addiupc\taddiur1sp\007addiur2\007addius5\007addiusp\007addq.ph\t"
    4220             :     "addq_s.ph\010addq_s.w\010addqh.ph\007addqh.w\naddqh_r.ph\taddqh_r.w\010"
    4221             :     "adds_a.b\010adds_a.d\010adds_a.h\010adds_a.w\010adds_s.b\010adds_s.d\010"
    4222             :     "adds_s.h\010adds_s.w\010adds_u.b\010adds_u.d\010adds_u.h\010adds_u.w\005"
    4223             :     "addsc\004addu\007addu.ph\007addu.qb\006addu16\taddu_s.ph\taddu_s.qb\010"
    4224             :     "adduh.qb\nadduh_r.qb\006addv.b\006addv.d\006addv.h\006addv.w\007addvi.b"
    4225             :     "\007addvi.d\007addvi.h\007addvi.w\005addwc\005align\006aluipc\003and\005"
    4226             :     "and.v\005and16\004andi\006andi.b\006andi16\006append\010asub_s.b\010asu"
    4227             :     "b_s.d\010asub_s.h\010asub_s.w\010asub_u.b\010asub_u.d\010asub_u.h\010as"
    4228             :     "ub_u.w\003aui\005auipc\007ave_s.b\007ave_s.d\007ave_s.h\007ave_s.w\007a"
    4229             :     "ve_u.b\007ave_u.d\007ave_u.h\007ave_u.w\010aver_s.b\010aver_s.d\010aver"
    4230             :     "_s.h\010aver_s.w\010aver_u.b\010aver_u.d\010aver_u.h\010aver_u.w\001b\003"
    4231             :     "b16\005baddu\003bal\004balc\006balign\005bbit0\007bbit032\005bbit1\007b"
    4232             :     "bit132\002bc\004bc16\006bc1eqz\007bc1eqzc\004bc1f\005bc1fl\006bc1nez\007"
    4233             :     "bc1nezc\004bc1t\005bc1tl\006bc2eqz\007bc2eqzc\006bc2nez\007bc2nezc\006b"
    4234             :     "clr.b\006bclr.d\006bclr.h\006bclr.w\007bclri.b\007bclri.d\007bclri.h\007"
    4235             :     "bclri.w\003beq\004beqc\004beql\004beqz\006beqz16\007beqzalc\005beqzc\007"
    4236             :     "beqzc16\005beqzl\003bge\004bgec\004bgel\004bgeu\005bgeuc\005bgeul\004bg"
    4237             :     "ez\006bgezal\007bgezalc\007bgezall\007bgezals\005bgezc\005bgezl\003bgt\004"
    4238             :     "bgtl\004bgtu\005bgtul\004bgtz\007bgtzalc\005bgtzc\005bgtzl\007binsl.b\007"
    4239             :     "binsl.d\007binsl.h\007binsl.w\010binsli.b\010binsli.d\010binsli.h\010bi"
    4240             :     "nsli.w\007binsr.b\007binsr.d\007binsr.h\007binsr.w\010binsri.b\010binsr"
    4241             :     "i.d\010binsri.h\010binsri.w\006bitrev\007bitswap\003ble\004blel\004bleu"
    4242             :     "\005bleul\004blez\007blezalc\005blezc\005blezl\003blt\004bltc\004bltl\004"
    4243             :     "bltu\005bltuc\005bltul\004bltz\006bltzal\007bltzalc\007bltzall\007bltza"
    4244             :     "ls\005bltzc\005bltzl\006bmnz.v\007bmnzi.b\005bmz.v\006bmzi.b\003bne\004"
    4245             :     "bnec\006bneg.b\006bneg.d\006bneg.h\006bneg.w\007bnegi.b\007bnegi.d\007b"
    4246             :     "negi.h\007bnegi.w\004bnel\004bnez\006bnez16\007bnezalc\005bnezc\007bnez"
    4247             :     "c16\005bnezl\004bnvc\005bnz.b\005bnz.d\005bnz.h\005bnz.v\005bnz.w\004bo"
    4248             :     "vc\010bposge32\tbposge32c\005break\007break16\006bsel.v\007bseli.b\006b"
    4249             :     "set.b\006bset.d\006bset.h\006bset.w\007bseti.b\007bseti.d\007bseti.h\007"
    4250             :     "bseti.w\005bteqz\005btnez\004bz.b\004bz.d\004bz.h\004bz.v\004bz.w\006c."
    4251             :     "eq.d\006c.eq.s\005c.f.d\005c.f.s\006c.le.d\006c.le.s\006c.lt.d\006c.lt."
    4252             :     "s\007c.nge.d\007c.nge.s\007c.ngl.d\007c.ngl.s\010c.ngle.d\010c.ngle.s\007"
    4253             :     "c.ngt.d\007c.ngt.s\007c.ole.d\007c.ole.s\007c.olt.d\007c.olt.s\007c.seq"
    4254             :     ".d\007c.seq.s\006c.sf.d\006c.sf.s\007c.ueq.d\007c.ueq.s\007c.ule.d\007c"
    4255             :     ".ule.s\007c.ult.d\007c.ult.s\006c.un.d\006c.un.s\005cache\006cachee\010"
    4256             :     "ceil.l.d\010ceil.l.s\010ceil.w.d\010ceil.w.s\005ceq.b\005ceq.d\005ceq.h"
    4257             :     "\005ceq.w\006ceqi.b\006ceqi.d\006ceqi.h\006ceqi.w\004cfc1\004cfc2\006cf"
    4258             :     "cmsa\004cins\006cins32\007class.d\007class.s\007cle_s.b\007cle_s.d\007c"
    4259             :     "le_s.h\007cle_s.w\007cle_u.b\007cle_u.d\007cle_u.h\007cle_u.w\010clei_s"
    4260             :     ".b\010clei_s.d\010clei_s.h\010clei_s.w\010clei_u.b\010clei_u.d\010clei_"
    4261             :     "u.h\010clei_u.w\003clo\007clt_s.b\007clt_s.d\007clt_s.h\007clt_s.w\007c"
    4262             :     "lt_u.b\007clt_u.d\007clt_u.h\007clt_u.w\010clti_s.b\010clti_s.d\010clti"
    4263             :     "_s.h\010clti_s.w\010clti_u.b\010clti_u.d\010clti_u.h\010clti_u.w\003clz"
    4264             :     "\003cmp\010cmp.af.d\010cmp.af.s\010cmp.eq.d\tcmp.eq.ph\010cmp.eq.s\010c"
    4265             :     "mp.le.d\tcmp.le.ph\010cmp.le.s\010cmp.lt.d\tcmp.lt.ph\010cmp.lt.s\tcmp."
    4266             :     "saf.d\tcmp.saf.s\tcmp.seq.d\tcmp.seq.s\tcmp.sle.d\tcmp.sle.s\tcmp.slt.d"
    4267             :     "\tcmp.slt.s\ncmp.sueq.d\ncmp.sueq.s\ncmp.sule.d\ncmp.sule.s\ncmp.sult.d"
    4268             :     "\ncmp.sult.s\tcmp.sun.d\tcmp.sun.s\tcmp.ueq.d\tcmp.ueq.s\tcmp.ule.d\tcm"
    4269             :     "p.ule.s\tcmp.ult.d\tcmp.ult.s\010cmp.un.d\010cmp.un.s\014cmpgdu.eq.qb\014"
    4270             :     "cmpgdu.le.qb\014cmpgdu.lt.qb\013cmpgu.eq.qb\013cmpgu.le.qb\013cmpgu.lt."
    4271             :     "qb\004cmpi\ncmpu.eq.qb\ncmpu.le.qb\ncmpu.lt.qb\010copy_s.b\010copy_s.d\010"
    4272             :     "copy_s.h\010copy_s.w\010copy_u.b\010copy_u.h\010copy_u.w\004ctc1\004ctc"
    4273             :     "2\006ctcmsa\007cvt.d.l\007cvt.d.s\007cvt.d.w\007cvt.l.d\007cvt.l.s\007c"
    4274             :     "vt.s.d\007cvt.s.l\007cvt.s.w\007cvt.w.d\007cvt.w.s\004dadd\005daddi\006"
    4275             :     "daddiu\005daddu\004dahi\006dalign\004dati\004daui\010dbitswap\004dclo\004"
    4276             :     "dclz\004ddiv\005ddivu\005deret\004dext\005dextm\005dextu\002di\004dins\005"
    4277             :     "dinsm\005dinsu\003div\005div.d\005div.s\007div_s.b\007div_s.d\007div_s."
    4278             :     "h\007div_s.w\007div_u.b\007div_u.d\007div_u.h\007div_u.w\004divu\003dla"
    4279             :     "\003dli\004dlsa\005dmfc0\005dmfc1\005dmfc2\004dmod\005dmodu\003dmt\005d"
    4280             :     "mtc0\005dmtc1\005dmtc2\004dmuh\005dmuhu\004dmul\005dmulo\006dmulou\005d"
    4281             :     "mult\006dmultu\005dmulu\004dneg\005dnegu\010dotp_s.d\010dotp_s.h\010dot"
    4282             :     "p_s.w\010dotp_u.d\010dotp_u.h\010dotp_u.w\010dpa.w.ph\tdpadd_s.d\tdpadd"
    4283             :     "_s.h\tdpadd_s.w\tdpadd_u.d\tdpadd_u.h\tdpadd_u.w\013dpaq_s.w.ph\013dpaq"
    4284             :     "_sa.l.w\014dpaqx_s.w.ph\015dpaqx_sa.w.ph\ndpau.h.qbl\ndpau.h.qbr\tdpax."
    4285             :     "w.ph\004dpop\010dps.w.ph\013dpsq_s.w.ph\013dpsq_sa.l.w\014dpsqx_s.w.ph\015"
    4286             :     "dpsqx_sa.w.ph\ndpsu.h.qbl\ndpsu.h.qbr\tdpsub_s.d\tdpsub_s.h\tdpsub_s.w\t"
    4287             :     "dpsub_u.d\tdpsub_u.h\tdpsub_u.w\tdpsx.w.ph\004drol\004dror\005drotr\007"
    4288             :     "drotr32\006drotrv\004dsbh\004dshd\004dsll\006dsll32\005dsllv\004dsra\006"
    4289             :     "dsra32\005dsrav\004dsrl\006dsrl32\005dsrlv\004dsub\005dsubi\005dsubu\003"
    4290             :     "dvp\004dvpe\003ehb\002ei\003emt\004eret\006eretnc\003evp\004evpe\003ext"
    4291             :     "\004extp\006extpdp\007extpdpv\005extpv\006extr.w\010extr_r.w\textr_rs.w"
    4292             :     "\010extr_s.h\007extrv.w\textrv_r.w\nextrv_rs.w\textrv_s.h\004exts\006ex"
    4293             :     "ts32\006fadd.d\006fadd.w\006fcaf.d\006fcaf.w\006fceq.d\006fceq.w\010fcl"
    4294             :     "ass.d\010fclass.w\006fcle.d\006fcle.w\006fclt.d\006fclt.w\006fcne.d\006"
    4295             :     "fcne.w\006fcor.d\006fcor.w\007fcueq.d\007fcueq.w\007fcule.d\007fcule.w\007"
    4296             :     "fcult.d\007fcult.w\006fcun.d\006fcun.w\007fcune.d\007fcune.w\006fdiv.d\006"
    4297             :     "fdiv.w\007fexdo.h\007fexdo.w\007fexp2.d\007fexp2.w\010fexupl.d\010fexup"
    4298             :     "l.w\010fexupr.d\010fexupr.w\tffint_s.d\tffint_s.w\tffint_u.d\tffint_u.w"
    4299             :     "\006ffql.d\006ffql.w\006ffqr.d\006ffqr.w\006fill.b\006fill.d\006fill.h\006"
    4300             :     "fill.w\007flog2.d\007flog2.w\tfloor.l.d\tfloor.l.s\tfloor.w.d\tfloor.w."
    4301             :     "s\007fmadd.d\007fmadd.w\006fmax.d\006fmax.w\010fmax_a.d\010fmax_a.w\006"
    4302             :     "fmin.d\006fmin.w\010fmin_a.d\010fmin_a.w\007fmsub.d\007fmsub.w\006fmul."
    4303             :     "d\006fmul.w\004fork\006frcp.d\006frcp.w\007frint.d\007frint.w\010frsqrt"
    4304             :     ".d\010frsqrt.w\006fsaf.d\006fsaf.w\006fseq.d\006fseq.w\006fsle.d\006fsl"
    4305             :     "e.w\006fslt.d\006fslt.w\006fsne.d\006fsne.w\006fsor.d\006fsor.w\007fsqr"
    4306             :     "t.d\007fsqrt.w\006fsub.d\006fsub.w\007fsueq.d\007fsueq.w\007fsule.d\007"
    4307             :     "fsule.w\007fsult.d\007fsult.w\006fsun.d\006fsun.w\007fsune.d\007fsune.w"
    4308             :     "\tftint_s.d\tftint_s.w\tftint_u.d\tftint_u.w\005ftq.h\005ftq.w\nftrunc_"
    4309             :     "s.d\nftrunc_s.w\nftrunc_u.d\nftrunc_u.w\010hadd_s.d\010hadd_s.h\010hadd"
    4310             :     "_s.w\010hadd_u.d\010hadd_u.h\010hadd_u.w\010hsub_s.d\010hsub_s.h\010hsu"
    4311             :     "b_s.w\010hsub_u.d\010hsub_u.h\010hsub_u.w\007ilvev.b\007ilvev.d\007ilve"
    4312             :     "v.h\007ilvev.w\006ilvl.b\006ilvl.d\006ilvl.h\006ilvl.w\007ilvod.b\007il"
    4313             :     "vod.d\007ilvod.h\007ilvod.w\006ilvr.b\006ilvr.d\006ilvr.h\006ilvr.w\003"
    4314             :     "ins\010insert.b\010insert.d\010insert.h\010insert.w\004insv\007insve.b\007"
    4315             :     "insve.d\007insve.h\007insve.w\001j\003jal\004jalr\007jalr.hb\005jalrc\010"
    4316             :     "jalrc.hb\005jalrs\007jalrs16\004jals\004jalx\005jialc\003jic\002jr\005j"
    4317             :     "r.hb\004jr16\tjraddiusp\003jrc\005jrc16\njrcaddiusp\003l.d\003l.s\002la"
    4318             :     "\004lapc\002lb\003lbe\003lbu\005lbu16\004lbue\004lbux\002ld\004ld.b\004"
    4319             :     "ld.d\004ld.h\004ld.w\004ldc1\004ldc2\004ldc3\005ldi.b\005ldi.d\005ldi.h"
    4320             :     "\005ldi.w\003ldl\004ldpc\003ldr\005ldxc1\002lh\003lhe\003lhu\005lhu16\004"
    4321             :     "lhue\003lhx\002li\004li.d\004li.s\004li16\002ll\003lld\003lle\003lsa\003"
    4322             :     "lui\005luxc1\002lw\004lw16\004lwc1\004lwc2\004lwc3\003lwe\003lwl\004lwl"
    4323             :     "e\003lwm\005lwm16\005lwm32\003lwp\004lwpc\003lwr\004lwre\003lwu\005lwup"
    4324             :     "c\003lwx\005lwxc1\004lwxs\004madd\006madd.d\006madd.s\010madd_q.h\010ma"
    4325             :     "dd_q.w\007maddf.d\007maddf.s\tmaddr_q.h\tmaddr_q.w\005maddu\007maddv.b\007"
    4326             :     "maddv.d\007maddv.h\007maddv.w\013maq_s.w.phl\013maq_s.w.phr\014maq_sa.w"
    4327             :     ".phl\014maq_sa.w.phr\005max.d\005max.s\007max_a.b\007max_a.d\007max_a.h"
    4328             :     "\007max_a.w\007max_s.b\007max_s.d\007max_s.h\007max_s.w\007max_u.b\007m"
    4329             :     "ax_u.d\007max_u.h\007max_u.w\006maxa.d\006maxa.s\010maxi_s.b\010maxi_s."
    4330             :     "d\010maxi_s.h\010maxi_s.w\010maxi_u.b\010maxi_u.d\010maxi_u.h\010maxi_u"
    4331             :     ".w\004mfc0\004mfc1\004mfc2\005mfhc0\005mfhc1\005mfhc2\004mfhi\004mflo\005"
    4332             :     "min.d\005min.s\007min_a.b\007min_a.d\007min_a.h\007min_a.w\007min_s.b\007"
    4333             :     "min_s.d\007min_s.h\007min_s.w\007min_u.b\007min_u.d\007min_u.h\007min_u"
    4334             :     ".w\006mina.d\006mina.s\010mini_s.b\010mini_s.d\010mini_s.h\010mini_s.w\010"
    4335             :     "mini_u.b\010mini_u.d\010mini_u.h\010mini_u.w\003mod\007mod_s.b\007mod_s"
    4336             :     ".d\007mod_s.h\007mod_s.w\007mod_u.b\007mod_u.d\007mod_u.h\007mod_u.w\006"
    4337             :     "modsub\004modu\005mov.d\005mov.s\004move\006move.v\006move16\005movep\004"
    4338             :     "movf\006movf.d\006movf.s\004movn\006movn.d\006movn.s\004movt\006movt.d\006"
    4339             :     "movt.s\004movz\006movz.d\006movz.s\004msub\006msub.d\006msub.s\010msub_"
    4340             :     "q.h\010msub_q.w\007msubf.d\007msubf.s\tmsubr_q.h\tmsubr_q.w\005msubu\007"
    4341             :     "msubv.b\007msubv.d\007msubv.h\007msubv.w\004mtc0\004mtc1\004mtc2\005mth"
    4342             :     "c0\005mthc1\005mthc2\004mthi\006mthlip\004mtlo\004mtm0\004mtm1\004mtm2\004"
    4343             :     "mtp0\004mtp1\004mtp2\003muh\004muhu\003mul\005mul.d\006mul.ph\005mul.s\007"
    4344             :     "mul_q.h\007mul_q.w\010mul_s.ph\015muleq_s.w.phl\015muleq_s.w.phr\016mul"
    4345             :     "eu_s.ph.qbl\016muleu_s.ph.qbr\004mulo\005mulou\nmulq_rs.ph\tmulq_rs.w\t"
    4346             :     "mulq_s.ph\010mulq_s.w\010mulr_q.h\010mulr_q.w\nmulsa.w.ph\015mulsaq_s.w"
    4347             :     ".ph\004mult\005multu\004mulu\006mulv.b\006mulv.d\006mulv.h\006mulv.w\003"
    4348             :     "neg\005neg.d\005neg.s\004negu\006nloc.b\006nloc.d\006nloc.h\006nloc.w\006"
    4349             :     "nlzc.b\006nlzc.d\006nlzc.h\006nlzc.w\007nmadd.d\007nmadd.s\007nmsub.d\007"
    4350             :     "nmsub.s\003nop\003nor\005nor.v\006nori.b\003not\005not16\002or\004or.v\004"
    4351             :     "or16\003ori\005ori.b\tpackrl.ph\005pause\007pckev.b\007pckev.d\007pckev"
    4352             :     ".h\007pckev.w\007pckod.b\007pckod.d\007pckod.h\007pckod.w\006pcnt.b\006"
    4353             :     "pcnt.d\006pcnt.h\006pcnt.w\007pick.ph\007pick.qb\003pop\014preceq.w.phl"
    4354             :     "\014preceq.w.phr\016precequ.ph.qbl\017precequ.ph.qbla\016precequ.ph.qbr"
    4355             :     "\017precequ.ph.qbra\015preceu.ph.qbl\016preceu.ph.qbla\015preceu.ph.qbr"
    4356             :     "\016preceu.ph.qbra\013precr.qb.ph\016precr_sra.ph.w\020precr_sra_r.ph.w"
    4357             :     "\013precrq.ph.w\014precrq.qb.ph\016precrq_rs.ph.w\017precrqu_s.qb.ph\004"
    4358             :     "pref\005prefe\005prefx\007prepend\nraddu.w.qb\005rddsp\005rdhwr\006rdpg"
    4359             :     "pr\007recip.d\007recip.s\007repl.ph\007repl.qb\010replv.ph\010replv.qb\006"
    4360             :     "rint.d\006rint.s\003rol\003ror\004rotr\005rotrv\tround.l.d\tround.l.s\t"
    4361             :     "round.w.d\tround.w.s\007rsqrt.d\007rsqrt.s\003s.d\003s.s\007sat_s.b\007"
    4362             :     "sat_s.d\007sat_s.h\007sat_s.w\007sat_u.b\007sat_u.d\007sat_u.h\007sat_u"
    4363             :     ".w\002sb\004sb16\003sbe\002sc\003scd\003sce\002sd\005sdbbp\007sdbbp16\004"
    4364             :     "sdc1\004sdc2\004sdc3\003sdl\003sdr\005sdxc1\003seb\003seh\005sel.d\005s"
    4365             :     "el.s\006seleqz\010seleqz.d\010seleqz.s\006selnez\010selnez.d\010selnez."
    4366             :     "s\003seq\004seqi\003sgt\004sgtu\002sh\004sh16\003she\005shf.b\005shf.h\005"
    4367             :     "shf.w\005shilo\006shilov\007shll.ph\007shll.qb\tshll_s.ph\010shll_s.w\010"
    4368             :     "shllv.ph\010shllv.qb\nshllv_s.ph\tshllv_s.w\007shra.ph\007shra.qb\tshra"
    4369             :     "_r.ph\tshra_r.qb\010shra_r.w\010shrav.ph\010shrav.qb\nshrav_r.ph\nshrav"
    4370             :     "_r.qb\tshrav_r.w\007shrl.ph\007shrl.qb\010shrlv.ph\010shrlv.qb\005sld.b"
    4371             :     "\005sld.d\005sld.h\005sld.w\006sldi.b\006sldi.d\006sldi.h\006sldi.w\003"
    4372             :     "sll\005sll.b\005sll.d\005sll.h\005sll.w\005sll16\006slli.b\006slli.d\006"
    4373             :     "slli.h\006slli.w\004sllv\003slt\004slti\005sltiu\004sltu\003sne\004snei"
    4374             :     "\007splat.b\007splat.d\007splat.h\007splat.w\010splati.b\010splati.d\010"
    4375             :     "splati.h\010splati.w\006sqrt.d\006sqrt.s\003sra\005sra.b\005sra.d\005sr"
    4376             :     "a.h\005sra.w\006srai.b\006srai.d\006srai.h\006srai.w\006srar.b\006srar."
    4377             :     "d\006srar.h\006srar.w\007srari.b\007srari.d\007srari.h\007srari.w\004sr"
    4378             :     "av\003srl\005srl.b\005srl.d\005srl.h\005srl.w\005srl16\006srli.b\006srl"
    4379             :     "i.d\006srli.h\006srli.w\006srlr.b\006srlr.d\006srlr.h\006srlr.w\007srlr"
    4380             :     "i.b\007srlri.d\007srlri.h\007srlri.w\004srlv\005ssnop\004st.b\004st.d\004"
    4381             :     "st.h\004st.w\003sub\005sub.d\005sub.s\007subq.ph\tsubq_s.ph\010subq_s.w"
    4382             :     "\010subqh.ph\007subqh.w\nsubqh_r.ph\tsubqh_r.w\010subs_s.b\010subs_s.d\010"
    4383             :     "subs_s.h\010subs_s.w\010subs_u.b\010subs_u.d\010subs_u.h\010subs_u.w\ns"
    4384             :     "ubsus_u.b\nsubsus_u.d\nsubsus_u.h\nsubsus_u.w\nsubsuu_s.b\nsubsuu_s.d\n"
    4385             :     "subsuu_s.h\nsubsuu_s.w\004subu\007subu.ph\007subu.qb\006subu16\tsubu_s."
    4386             :     "ph\tsubu_s.qb\010subuh.qb\nsubuh_r.qb\006subv.b\006subv.d\006subv.h\006"
    4387             :     "subv.w\007subvi.b\007subvi.d\007subvi.h\007subvi.w\005suxc1\002sw\004sw"
    4388             :     "16\004swc1\004swc2\004swc3\003swe\003swl\004swle\003swm\005swm16\005swm"
    4389             :     "32\003swp\003swr\004swre\005swxc1\004sync\005synci\nsynciobdma\005syncs"
    4390             :     "\005syncw\006syncws\007syscall\003teq\004teqi\003tge\004tgei\005tgeiu\004"
    4391             :     "tgeu\006tlbinv\007tlbinvf\004tlbp\004tlbr\005tlbwi\005tlbwr\003tlt\004t"
    4392             :     "lti\005tltiu\004tltu\003tne\004tnei\ttrunc.l.d\ttrunc.l.s\ttrunc.w.d\tt"
    4393             :     "runc.w.s\003ulh\004ulhu\003ulw\003ush\003usw\006v3mulu\004vmm0\005vmulu"
    4394             :     "\006vshf.b\006vshf.d\006vshf.h\006vshf.w\004wait\005wrdsp\006wrpgpr\004"
    4395             :     "wsbh\003xor\005xor.v\005xor16\004xori\006xori.b\005yield";
    4396             : 
    4397             : namespace {
    4398             :   struct MatchEntry {
    4399             :     uint16_t Mnemonic;
    4400             :     uint16_t Opcode;
    4401             :     uint16_t ConvertFn;
    4402             :     uint64_t RequiredFeatures;
    4403             :     uint8_t Classes[8];
    4404             :     StringRef getMnemonic() const {
    4405      764224 :       return StringRef(MnemonicTable + Mnemonic + 1,
    4406      764224 :                        MnemonicTable[Mnemonic]);
    4407             :     }
    4408             :   };
    4409             : 
    4410             :   // Predicate for searching for an opcode.
    4411             :   struct LessOpcode {
    4412             :     bool operator()(const MatchEntry &LHS, StringRef RHS) {
    4413      922960 :       return LHS.getMnemonic() < RHS;
    4414             :     }
    4415             :     bool operator()(StringRef LHS, const MatchEntry &RHS) {
    4416      605488 :       return LHS < RHS.getMnemonic();
    4417             :     }
    4418             :     bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
    4419             :       return LHS.getMnemonic() < RHS.getMnemonic();
    4420             :     }
    4421             :   };
    4422             : } // end anonymous namespace.
    4423             : 
    4424             : static const MatchEntry MatchTable0[] = {
    4425             :   { 0 /* abs */, Mips::ABSMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4426             :   { 4 /* abs.d */, Mips::ABS_D_MMR6, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4427             :   { 4 /* abs.d */, Mips::FABS_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4428             :   { 4 /* abs.d */, Mips::FABS_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4429             :   { 10 /* abs.s */, Mips::ABS_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4430             :   { 10 /* abs.s */, Mips::FABS_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4431             :   { 16 /* absq_s.ph */, Mips::ABSQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4432             :   { 16 /* absq_s.ph */, Mips::ABSQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4433             :   { 26 /* absq_s.qb */, Mips::ABSQ_S_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4434             :   { 26 /* absq_s.qb */, Mips::ABSQ_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4435             :   { 36 /* absq_s.w */, Mips::ABSQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4436             :   { 36 /* absq_s.w */, Mips::ABSQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4437             :   { 45 /* add */, Mips::ADD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4438             :   { 45 /* add */, Mips::ADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4439             :   { 45 /* add */, Mips::ADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4440             :   { 45 /* add */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
    4441             :   { 45 /* add */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
    4442             :   { 45 /* add */, Mips::ADD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4443             :   { 45 /* add */, Mips::ADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4444             :   { 45 /* add */, Mips::ADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4445             :   { 45 /* add */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
    4446             :   { 45 /* add */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
    4447             :   { 49 /* add.d */, Mips::FADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4448             :   { 49 /* add.d */, Mips::FADD_D_MMR6, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_2__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4449             :   { 49 /* add.d */, Mips::FADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4450             :   { 55 /* add.s */, Mips::FADD_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4451             :   { 55 /* add.s */, Mips::FADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4452             :   { 61 /* add_a.b */, Mips::ADD_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4453             :   { 69 /* add_a.d */, Mips::ADD_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4454             :   { 77 /* add_a.h */, Mips::ADD_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4455             :   { 85 /* add_a.w */, Mips::ADD_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4456             :   { 93 /* addi */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
    4457             :   { 93 /* addi */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, },
    4458             :   { 93 /* addi */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
    4459             :   { 93 /* addi */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, },
    4460             :   { 98 /* addiu */, Mips::AddiuSpImmX16, Convert__SImm161_1, Feature_InMips16Mode, { MCK_CPUSPReg, MCK_SImm16 }, },
    4461             :   { 98 /* addiu */, Mips::AddiuRxImmX16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
    4462             :   { 98 /* addiu */, Mips::ADDIU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
    4463             :   { 98 /* addiu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
    4464             :   { 98 /* addiu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, },
    4465             :   { 98 /* addiu */, Mips::AddiuRxPcImmX16, Convert__Reg1_0__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_PC, MCK_SImm16 }, },
    4466             :   { 98 /* addiu */, Mips::AddiuRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, },
    4467             :   { 98 /* addiu */, Mips::ADDIU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
    4468             :   { 98 /* addiu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
    4469             :   { 98 /* addiu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, },
    4470             :   { 98 /* addiu */, Mips::AddiuSpImm16, Convert__SImm161_1, Feature_InMips16Mode, { MCK_CPUSPReg, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
    4471             :   { 98 /* addiu */, Mips::AddiuRxRxImm16, Convert__Reg1_0__Tie0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
    4472             :   { 104 /* addiupc */, Mips::ADDIUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
    4473             :   { 104 /* addiupc */, Mips::ADDIUPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
    4474             :   { 104 /* addiupc */, Mips::ADDIUPC_MM, Convert__GPRMM16AsmReg1_0__Imm1_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_Imm }, },
    4475             :   { 112 /* addiur1sp */, Mips::ADDIUR1SP_MM, Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_UImm6Lsl2 }, },
    4476             :   { 122 /* addiur2 */, Mips::ADDIUR2_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
    4477             :   { 130 /* addius5 */, Mips::ADDIUS5_MM, Convert__GPR32AsmReg1_0__Tie0__ConstantSImm4_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantSImm4_0 }, },
    4478             :   { 138 /* addiusp */, Mips::ADDIUSP_MM, Convert__Imm1_0, Feature_InMicroMips, { MCK_Imm }, },
    4479             :   { 146 /* addq.ph */, Mips::ADDQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4480             :   { 146 /* addq.ph */, Mips::ADDQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4481             :   { 154 /* addq_s.ph */, Mips::ADDQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4482             :   { 154 /* addq_s.ph */, Mips::ADDQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4483             :   { 164 /* addq_s.w */, Mips::ADDQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4484             :   { 164 /* addq_s.w */, Mips::ADDQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4485             :   { 173 /* addqh.ph */, Mips::ADDQH_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4486             :   { 173 /* addqh.ph */, Mips::ADDQH_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4487             :   { 182 /* addqh.w */, Mips::ADDQH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4488             :   { 182 /* addqh.w */, Mips::ADDQH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4489             :   { 190 /* addqh_r.ph */, Mips::ADDQH_R_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4490             :   { 190 /* addqh_r.ph */, Mips::ADDQH_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4491             :   { 201 /* addqh_r.w */, Mips::ADDQH_R_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4492             :   { 201 /* addqh_r.w */, Mips::ADDQH_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4493             :   { 211 /* adds_a.b */, Mips::ADDS_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4494             :   { 220 /* adds_a.d */, Mips::ADDS_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4495             :   { 229 /* adds_a.h */, Mips::ADDS_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4496             :   { 238 /* adds_a.w */, Mips::ADDS_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4497             :   { 247 /* adds_s.b */, Mips::ADDS_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4498             :   { 256 /* adds_s.d */, Mips::ADDS_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4499             :   { 265 /* adds_s.h */, Mips::ADDS_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4500             :   { 274 /* adds_s.w */, Mips::ADDS_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4501             :   { 283 /* adds_u.b */, Mips::ADDS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4502             :   { 292 /* adds_u.d */, Mips::ADDS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4503             :   { 301 /* adds_u.h */, Mips::ADDS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4504             :   { 310 /* adds_u.w */, Mips::ADDS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4505             :   { 319 /* addsc */, Mips::ADDSC_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4506             :   { 319 /* addsc */, Mips::ADDSC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4507             :   { 325 /* addu */, Mips::ADDU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4508             :   { 325 /* addu */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4509             :   { 325 /* addu */, Mips::ADDu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4510             :   { 325 /* addu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
    4511             :   { 325 /* addu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
    4512             :   { 325 /* addu */, Mips::AdduRxRyRz16, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_CPU16Regs }, },
    4513             :   { 325 /* addu */, Mips::ADDU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4514             :   { 325 /* addu */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4515             :   { 325 /* addu */, Mips::ADDu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4516             :   { 325 /* addu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
    4517             :   { 325 /* addu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
    4518             :   { 330 /* addu.ph */, Mips::ADDU_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4519             :   { 330 /* addu.ph */, Mips::ADDU_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4520             :   { 338 /* addu.qb */, Mips::ADDU_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4521             :   { 338 /* addu.qb */, Mips::ADDU_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4522             :   { 346 /* addu16 */, Mips::ADDU16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
    4523             :   { 346 /* addu16 */, Mips::ADDU16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, Feature_HasMicroMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
    4524             :   { 353 /* addu_s.ph */, Mips::ADDU_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4525             :   { 353 /* addu_s.ph */, Mips::ADDU_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4526             :   { 363 /* addu_s.qb */, Mips::ADDU_S_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4527             :   { 363 /* addu_s.qb */, Mips::ADDU_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4528             :   { 373 /* adduh.qb */, Mips::ADDUH_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4529             :   { 373 /* adduh.qb */, Mips::ADDUH_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4530             :   { 382 /* adduh_r.qb */, Mips::ADDUH_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4531             :   { 382 /* adduh_r.qb */, Mips::ADDUH_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4532             :   { 393 /* addv.b */, Mips::ADDV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4533             :   { 400 /* addv.d */, Mips::ADDV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4534             :   { 407 /* addv.h */, Mips::ADDV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4535             :   { 414 /* addv.w */, Mips::ADDV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4536             :   { 421 /* addvi.b */, Mips::ADDVI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    4537             :   { 429 /* addvi.d */, Mips::ADDVI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    4538             :   { 437 /* addvi.h */, Mips::ADDVI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    4539             :   { 445 /* addvi.w */, Mips::ADDVI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    4540             :   { 453 /* addwc */, Mips::ADDWC_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4541             :   { 453 /* addwc */, Mips::ADDWC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4542             :   { 459 /* align */, Mips::ALIGN, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
    4543             :   { 459 /* align */, Mips::ALIGN_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
    4544             :   { 465 /* aluipc */, Mips::ALUIPC, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
    4545             :   { 465 /* aluipc */, Mips::ALUIPC_MMR6, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
    4546             :   { 472 /* and */, Mips::AndRxRxRy16, Convert__Reg1_0__Tie0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
    4547             :   { 472 /* and */, Mips::AND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4548             :   { 472 /* and */, Mips::AND_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4549             :   { 472 /* and */, Mips::AND_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4550             :   { 472 /* and */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
    4551             :   { 472 /* and */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
    4552             :   { 472 /* and */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
    4553             :   { 472 /* and */, Mips::ANDi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_IsGP64bit|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
    4554             :   { 472 /* and */, Mips::AND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4555             :   { 472 /* and */, Mips::AND_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4556             :   { 472 /* and */, Mips::AND_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4557             :   { 472 /* and */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
    4558             :   { 472 /* and */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
    4559             :   { 472 /* and */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
    4560             :   { 472 /* and */, Mips::ANDi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_IsGP64bit|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
    4561             :   { 476 /* and.v */, Mips::AND_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4562             :   { 482 /* and16 */, Mips::AND16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0, Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
    4563             :   { 482 /* and16 */, Mips::AND16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0, Feature_HasMicroMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
    4564             :   { 488 /* andi */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
    4565             :   { 488 /* andi */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, },
    4566             :   { 488 /* andi */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, },
    4567             :   { 488 /* andi */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
    4568             :   { 488 /* andi */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
    4569             :   { 488 /* andi */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
    4570             :   { 493 /* andi.b */, Mips::ANDI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
    4571             :   { 500 /* andi16 */, Mips::ANDI16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
    4572             :   { 500 /* andi16 */, Mips::ANDI16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_HasMicroMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
    4573             :   { 507 /* append */, Mips::APPEND_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    4574             :   { 507 /* append */, Mips::APPEND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    4575             :   { 514 /* asub_s.b */, Mips::ASUB_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4576             :   { 523 /* asub_s.d */, Mips::ASUB_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4577             :   { 532 /* asub_s.h */, Mips::ASUB_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4578             :   { 541 /* asub_s.w */, Mips::ASUB_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4579             :   { 550 /* asub_u.b */, Mips::ASUB_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4580             :   { 559 /* asub_u.d */, Mips::ASUB_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4581             :   { 568 /* asub_u.h */, Mips::ASUB_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4582             :   { 577 /* asub_u.w */, Mips::ASUB_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4583             :   { 586 /* aui */, Mips::AUI, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
    4584             :   { 586 /* aui */, Mips::AUI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
    4585             :   { 590 /* auipc */, Mips::AUIPC, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
    4586             :   { 590 /* auipc */, Mips::AUIPC_MMR6, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
    4587             :   { 596 /* ave_s.b */, Mips::AVE_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4588             :   { 604 /* ave_s.d */, Mips::AVE_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4589             :   { 612 /* ave_s.h */, Mips::AVE_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4590             :   { 620 /* ave_s.w */, Mips::AVE_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4591             :   { 628 /* ave_u.b */, Mips::AVE_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4592             :   { 636 /* ave_u.d */, Mips::AVE_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4593             :   { 644 /* ave_u.h */, Mips::AVE_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4594             :   { 652 /* ave_u.w */, Mips::AVE_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4595             :   { 660 /* aver_s.b */, Mips::AVER_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4596             :   { 669 /* aver_s.d */, Mips::AVER_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4597             :   { 678 /* aver_s.h */, Mips::AVER_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4598             :   { 687 /* aver_s.w */, Mips::AVER_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4599             :   { 696 /* aver_u.b */, Mips::AVER_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4600             :   { 705 /* aver_u.d */, Mips::AVER_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4601             :   { 714 /* aver_u.h */, Mips::AVER_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4602             :   { 723 /* aver_u.w */, Mips::AVER_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4603             :   { 732 /* b */, Mips::B_MM_Pseudo, Convert__JumpTarget1_0, Feature_InMicroMips, { MCK_JumpTarget }, },
    4604             :   { 732 /* b */, Mips::BimmX16, Convert__JumpTarget1_0, Feature_InMips16Mode, { MCK_JumpTarget }, },
    4605             :   { 732 /* b */, Mips::BEQ, Convert__regZERO__regZERO__JumpTarget1_0, Feature_NotInMicroMips, { MCK_JumpTarget }, },
    4606             :   { 732 /* b */, Mips::B_MMR6_Pseudo, Convert__JumpTarget1_0, 0, { MCK_JumpTarget }, },
    4607             :   { 732 /* b */, Mips::Bimm16, Convert__JumpTarget1_0, Feature_InMips16Mode, { MCK_JumpTarget, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
    4608             :   { 734 /* b16 */, Mips::B16_MM, Convert__JumpTarget1_0, Feature_InMicroMips, { MCK_JumpTarget }, },
    4609             :   { 738 /* baddu */, Mips::BADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    4610             :   { 738 /* baddu */, Mips::BADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    4611             :   { 744 /* bal */, Mips::BAL, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_JumpTarget }, },
    4612             :   { 744 /* bal */, Mips::BGEZAL, Convert__regZERO__JumpTarget1_0, Feature_NotMips32r6|Feature_NotMips64r6, { MCK_JumpTarget }, },
    4613             :   { 748 /* balc */, Mips::BALC, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_JumpTarget }, },
    4614             :   { 748 /* balc */, Mips::BALC_MMR6, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_JumpTarget }, },
    4615             :   { 753 /* balign */, Mips::BALIGN_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
    4616             :   { 753 /* balign */, Mips::BALIGN, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
    4617             :   { 760 /* bbit0 */, Mips::BBIT032, Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_JumpTarget }, },
    4618             :   { 760 /* bbit0 */, Mips::BBIT0, Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_JumpTarget }, },
    4619             :   { 766 /* bbit032 */, Mips::BBIT032, Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_JumpTarget }, },
    4620             :   { 774 /* bbit1 */, Mips::BBIT132, Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_JumpTarget }, },
    4621             :   { 774 /* bbit1 */, Mips::BBIT1, Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_JumpTarget }, },
    4622             :   { 780 /* bbit132 */, Mips::BBIT132, Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_JumpTarget }, },
    4623             :   { 788 /* bc */, Mips::BC, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_JumpTarget }, },
    4624             :   { 788 /* bc */, Mips::BC_MMR6, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_JumpTarget }, },
    4625             :   { 791 /* bc16 */, Mips::BC16_MMR6, Convert__JumpTarget1_0, Feature_HasMicroMips32r6, { MCK_JumpTarget }, },
    4626             :   { 796 /* bc1eqz */, Mips::BC1EQZ, Convert__FGR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_JumpTarget }, },
    4627             :   { 803 /* bc1eqzc */, Mips::BC1EQZC_MMR6, Convert__FGR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_JumpTarget }, },
    4628             :   { 811 /* bc1f */, Mips::BC1F, Convert__regFCC0__JumpTarget1_0, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_JumpTarget }, },
    4629             :   { 811 /* bc1f */, Mips::BC1F_MM, Convert__regFCC0__JumpTarget1_0, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_JumpTarget }, },
    4630             :   { 811 /* bc1f */, Mips::BC1F, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_JumpTarget }, },
    4631             :   { 816 /* bc1fl */, Mips::BC1FL, Convert__regFCC0__JumpTarget1_0, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_JumpTarget }, },
    4632             :   { 816 /* bc1fl */, Mips::BC1FL, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_JumpTarget }, },
    4633             :   { 822 /* bc1nez */, Mips::BC1NEZ, Convert__FGR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_JumpTarget }, },
    4634             :   { 829 /* bc1nezc */, Mips::BC1NEZC_MMR6, Convert__FGR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_JumpTarget }, },
    4635             :   { 837 /* bc1t */, Mips::BC1T, Convert__regFCC0__JumpTarget1_0, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_JumpTarget }, },
    4636             :   { 837 /* bc1t */, Mips::BC1T_MM, Convert__regFCC0__JumpTarget1_0, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_JumpTarget }, },
    4637             :   { 837 /* bc1t */, Mips::BC1T, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_JumpTarget }, },
    4638             :   { 842 /* bc1tl */, Mips::BC1TL, Convert__regFCC0__JumpTarget1_0, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_JumpTarget }, },
    4639             :   { 842 /* bc1tl */, Mips::BC1TL, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_JumpTarget }, },
    4640             :   { 848 /* bc2eqz */, Mips::BC2EQZ, Convert__COP2AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_JumpTarget }, },
    4641             :   { 855 /* bc2eqzc */, Mips::BC2EQZC_MMR6, Convert__COP2AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_COP2AsmReg, MCK_JumpTarget }, },
    4642             :   { 863 /* bc2nez */, Mips::BC2NEZ, Convert__COP2AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_JumpTarget }, },
    4643             :   { 870 /* bc2nezc */, Mips::BC2NEZC_MMR6, Convert__COP2AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_COP2AsmReg, MCK_JumpTarget }, },
    4644             :   { 878 /* bclr.b */, Mips::BCLR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4645             :   { 885 /* bclr.d */, Mips::BCLR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4646             :   { 892 /* bclr.h */, Mips::BCLR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4647             :   { 899 /* bclr.w */, Mips::BCLR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4648             :   { 906 /* bclri.b */, Mips::BCLRI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
    4649             :   { 914 /* bclri.d */, Mips::BCLRI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
    4650             :   { 922 /* bclri.h */, Mips::BCLRI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
    4651             :   { 930 /* bclri.w */, Mips::BCLRI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    4652             :   { 938 /* beq */, Mips::BEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4653             :   { 938 /* beq */, Mips::BEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4654             :   { 938 /* beq */, Mips::BeqImm, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
    4655             :   { 942 /* beqc */, Mips::BEQC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4656             :   { 942 /* beqc */, Mips::BEQC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4657             :   { 942 /* beqc */, Mips::BEQC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
    4658             :   { 947 /* beql */, Mips::BEQL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4659             :   { 947 /* beql */, Mips::BEQLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
    4660             :   { 952 /* beqz */, Mips::BeqzRxImmX16, Convert__Reg1_0__JumpTarget1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget }, },
    4661             :   { 952 /* beqz */, Mips::BEQ_MM, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4662             :   { 952 /* beqz */, Mips::BEQ, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, 0, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4663             :   { 952 /* beqz */, Mips::BeqzRxImm16, Convert__Reg1_0__JumpTarget1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
    4664             :   { 957 /* beqz16 */, Mips::BEQZ16_MM, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
    4665             :   { 964 /* beqzalc */, Mips::BEQZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4666             :   { 964 /* beqzalc */, Mips::BEQZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4667             :   { 972 /* beqzc */, Mips::BEQZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4668             :   { 972 /* beqzc */, Mips::BEQZC_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4669             :   { 972 /* beqzc */, Mips::BEQZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4670             :   { 972 /* beqzc */, Mips::BEQZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
    4671             :   { 978 /* beqzc16 */, Mips::BEQZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_HasMicroMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
    4672             :   { 986 /* beqzl */, Mips::BEQL, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, 0, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4673             :   { 992 /* bge */, Mips::BGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4674             :   { 992 /* bge */, Mips::BGEImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
    4675             :   { 996 /* bgec */, Mips::BGEC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4676             :   { 996 /* bgec */, Mips::BGEC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4677             :   { 996 /* bgec */, Mips::BGEC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
    4678             :   { 1001 /* bgel */, Mips::BGEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4679             :   { 1001 /* bgel */, Mips::BGELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
    4680             :   { 1006 /* bgeu */, Mips::BGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4681             :   { 1006 /* bgeu */, Mips::BGEUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
    4682             :   { 1011 /* bgeuc */, Mips::BGEUC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4683             :   { 1011 /* bgeuc */, Mips::BGEUC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4684             :   { 1011 /* bgeuc */, Mips::BGEUC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
    4685             :   { 1017 /* bgeul */, Mips::BGEUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4686             :   { 1017 /* bgeul */, Mips::BGEULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
    4687             :   { 1023 /* bgez */, Mips::BGEZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4688             :   { 1023 /* bgez */, Mips::BGEZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4689             :   { 1028 /* bgezal */, Mips::BGEZAL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4690             :   { 1028 /* bgezal */, Mips::BGEZAL_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4691             :   { 1035 /* bgezalc */, Mips::BGEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4692             :   { 1035 /* bgezalc */, Mips::BGEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4693             :   { 1043 /* bgezall */, Mips::BGEZALL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4694             :   { 1051 /* bgezals */, Mips::BGEZALS_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4695             :   { 1059 /* bgezc */, Mips::BGEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4696             :   { 1059 /* bgezc */, Mips::BGEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4697             :   { 1059 /* bgezc */, Mips::BGEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
    4698             :   { 1065 /* bgezl */, Mips::BGEZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4699             :   { 1071 /* bgt */, Mips::BGT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4700             :   { 1071 /* bgt */, Mips::BGTImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
    4701             :   { 1075 /* bgtl */, Mips::BGTL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4702             :   { 1075 /* bgtl */, Mips::BGTLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
    4703             :   { 1080 /* bgtu */, Mips::BGTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4704             :   { 1080 /* bgtu */, Mips::BGTUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
    4705             :   { 1085 /* bgtul */, Mips::BGTUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4706             :   { 1085 /* bgtul */, Mips::BGTULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
    4707             :   { 1091 /* bgtz */, Mips::BGTZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4708             :   { 1091 /* bgtz */, Mips::BGTZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4709             :   { 1096 /* bgtzalc */, Mips::BGTZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4710             :   { 1096 /* bgtzalc */, Mips::BGTZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4711             :   { 1104 /* bgtzc */, Mips::BGTZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4712             :   { 1104 /* bgtzc */, Mips::BGTZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4713             :   { 1104 /* bgtzc */, Mips::BGTZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
    4714             :   { 1110 /* bgtzl */, Mips::BGTZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4715             :   { 1116 /* binsl.b */, Mips::BINSL_B, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4716             :   { 1124 /* binsl.d */, Mips::BINSL_D, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4717             :   { 1132 /* binsl.h */, Mips::BINSL_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4718             :   { 1140 /* binsl.w */, Mips::BINSL_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4719             :   { 1148 /* binsli.b */, Mips::BINSLI_B, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
    4720             :   { 1157 /* binsli.d */, Mips::BINSLI_D, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
    4721             :   { 1166 /* binsli.h */, Mips::BINSLI_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
    4722             :   { 1175 /* binsli.w */, Mips::BINSLI_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    4723             :   { 1184 /* binsr.b */, Mips::BINSR_B, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4724             :   { 1192 /* binsr.d */, Mips::BINSR_D, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4725             :   { 1200 /* binsr.h */, Mips::BINSR_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4726             :   { 1208 /* binsr.w */, Mips::BINSR_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4727             :   { 1216 /* binsri.b */, Mips::BINSRI_B, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
    4728             :   { 1225 /* binsri.d */, Mips::BINSRI_D, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
    4729             :   { 1234 /* binsri.h */, Mips::BINSRI_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
    4730             :   { 1243 /* binsri.w */, Mips::BINSRI_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    4731             :   { 1252 /* bitrev */, Mips::BITREV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4732             :   { 1252 /* bitrev */, Mips::BITREV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4733             :   { 1259 /* bitswap */, Mips::BITSWAP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4734             :   { 1259 /* bitswap */, Mips::BITSWAP_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    4735             :   { 1267 /* ble */, Mips::BLE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4736             :   { 1267 /* ble */, Mips::BLEImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
    4737             :   { 1271 /* blel */, Mips::BLEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4738             :   { 1271 /* blel */, Mips::BLELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
    4739             :   { 1276 /* bleu */, Mips::BLEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4740             :   { 1276 /* bleu */, Mips::BLEUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
    4741             :   { 1281 /* bleul */, Mips::BLEUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4742             :   { 1281 /* bleul */, Mips::BLEULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
    4743             :   { 1287 /* blez */, Mips::BLEZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4744             :   { 1287 /* blez */, Mips::BLEZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4745             :   { 1292 /* blezalc */, Mips::BLEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4746             :   { 1292 /* blezalc */, Mips::BLEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4747             :   { 1300 /* blezc */, Mips::BLEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4748             :   { 1300 /* blezc */, Mips::BLEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4749             :   { 1300 /* blezc */, Mips::BLEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
    4750             :   { 1306 /* blezl */, Mips::BLEZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4751             :   { 1312 /* blt */, Mips::BLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4752             :   { 1312 /* blt */, Mips::BLTImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
    4753             :   { 1316 /* bltc */, Mips::BLTC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4754             :   { 1316 /* bltc */, Mips::BLTC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4755             :   { 1316 /* bltc */, Mips::BLTC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
    4756             :   { 1321 /* bltl */, Mips::BLTL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4757             :   { 1321 /* bltl */, Mips::BLTLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
    4758             :   { 1326 /* bltu */, Mips::BLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4759             :   { 1326 /* bltu */, Mips::BLTUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
    4760             :   { 1331 /* bltuc */, Mips::BLTUC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4761             :   { 1331 /* bltuc */, Mips::BLTUC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4762             :   { 1331 /* bltuc */, Mips::BLTUC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
    4763             :   { 1337 /* bltul */, Mips::BLTUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4764             :   { 1337 /* bltul */, Mips::BLTULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
    4765             :   { 1343 /* bltz */, Mips::BLTZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4766             :   { 1343 /* bltz */, Mips::BLTZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4767             :   { 1348 /* bltzal */, Mips::BLTZAL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4768             :   { 1348 /* bltzal */, Mips::BLTZAL_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4769             :   { 1355 /* bltzalc */, Mips::BLTZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4770             :   { 1355 /* bltzalc */, Mips::BLTZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4771             :   { 1363 /* bltzall */, Mips::BLTZALL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4772             :   { 1371 /* bltzals */, Mips::BLTZALS_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4773             :   { 1379 /* bltzc */, Mips::BLTZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4774             :   { 1379 /* bltzc */, Mips::BLTZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4775             :   { 1379 /* bltzc */, Mips::BLTZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
    4776             :   { 1385 /* bltzl */, Mips::BLTZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4777             :   { 1391 /* bmnz.v */, Mips::BMNZ_V, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4778             :   { 1398 /* bmnzi.b */, Mips::BMNZI_B, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
    4779             :   { 1406 /* bmz.v */, Mips::BMZ_V, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4780             :   { 1412 /* bmzi.b */, Mips::BMZI_B, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
    4781             :   { 1419 /* bne */, Mips::BNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4782             :   { 1419 /* bne */, Mips::BNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4783             :   { 1419 /* bne */, Mips::BneImm, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
    4784             :   { 1423 /* bnec */, Mips::BNEC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4785             :   { 1423 /* bnec */, Mips::BNEC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4786             :   { 1423 /* bnec */, Mips::BNEC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
    4787             :   { 1428 /* bneg.b */, Mips::BNEG_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4788             :   { 1435 /* bneg.d */, Mips::BNEG_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4789             :   { 1442 /* bneg.h */, Mips::BNEG_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4790             :   { 1449 /* bneg.w */, Mips::BNEG_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4791             :   { 1456 /* bnegi.b */, Mips::BNEGI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
    4792             :   { 1464 /* bnegi.d */, Mips::BNEGI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
    4793             :   { 1472 /* bnegi.h */, Mips::BNEGI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
    4794             :   { 1480 /* bnegi.w */, Mips::BNEGI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    4795             :   { 1488 /* bnel */, Mips::BNEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4796             :   { 1488 /* bnel */, Mips::BNELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
    4797             :   { 1493 /* bnez */, Mips::BnezRxImmX16, Convert__Reg1_0__JumpTarget1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget }, },
    4798             :   { 1493 /* bnez */, Mips::BNE_MM, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4799             :   { 1493 /* bnez */, Mips::BNE, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, 0, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4800             :   { 1493 /* bnez */, Mips::BnezRxImm16, Convert__Reg1_0__JumpTarget1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
    4801             :   { 1498 /* bnez16 */, Mips::BNEZ16_MM, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
    4802             :   { 1505 /* bnezalc */, Mips::BNEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4803             :   { 1505 /* bnezalc */, Mips::BNEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4804             :   { 1513 /* bnezc */, Mips::BNEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4805             :   { 1513 /* bnezc */, Mips::BNEZC_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4806             :   { 1513 /* bnezc */, Mips::BNEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4807             :   { 1513 /* bnezc */, Mips::BNEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
    4808             :   { 1519 /* bnezc16 */, Mips::BNEZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_HasMicroMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
    4809             :   { 1527 /* bnezl */, Mips::BNEL, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, 0, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4810             :   { 1533 /* bnvc */, Mips::BNVC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4811             :   { 1533 /* bnvc */, Mips::BNVC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4812             :   { 1538 /* bnz.b */, Mips::BNZ_B, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
    4813             :   { 1544 /* bnz.d */, Mips::BNZ_D, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
    4814             :   { 1550 /* bnz.h */, Mips::BNZ_H, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
    4815             :   { 1556 /* bnz.v */, Mips::BNZ_V, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
    4816             :   { 1562 /* bnz.w */, Mips::BNZ_W, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
    4817             :   { 1568 /* bovc */, Mips::BOVC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4818             :   { 1568 /* bovc */, Mips::BOVC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
    4819             :   { 1573 /* bposge32 */, Mips::BPOSGE32_MM, Convert__JumpTarget1_0, Feature_NotMips32r6|Feature_NotMips64r6|Feature_InMicroMips, { MCK_JumpTarget }, },
    4820             :   { 1573 /* bposge32 */, Mips::BPOSGE32, Convert__JumpTarget1_0, Feature_HasDSP|Feature_NotInMicroMips, { MCK_JumpTarget }, },
    4821             :   { 1582 /* bposge32c */, Mips::BPOSGE32C_MMR3, Convert__JumpTarget1_0, Feature_HasDSPR3|Feature_InMicroMips, { MCK_JumpTarget }, },
    4822             :   { 1592 /* break */, Mips::BREAK, Convert__imm_95_0__imm_95_0, 0, {  }, },
    4823             :   { 1592 /* break */, Mips::Break16, Convert_NoOperands, Feature_InMips16Mode, { MCK_0 }, },
    4824             :   { 1592 /* break */, Mips::BREAK, Convert__ConstantUImm10_01_0__imm_95_0, 0, { MCK_ConstantUImm10_0 }, },
    4825             :   { 1592 /* break */, Mips::BREAK, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, },
    4826             :   { 1592 /* break */, Mips::BREAK_MMR6, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, },
    4827             :   { 1592 /* break */, Mips::BREAK_MM, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, Feature_InMicroMips, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, },
    4828             :   { 1598 /* break16 */, Mips::BREAK16_MM, Convert__ConstantUImm4_01_0, Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_ConstantUImm4_0 }, },
    4829             :   { 1598 /* break16 */, Mips::BREAK16_MMR6, Convert__ConstantUImm4_01_0, Feature_HasMicroMips32r6, { MCK_ConstantUImm4_0 }, },
    4830             :   { 1606 /* bsel.v */, Mips::BSEL_V, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4831             :   { 1613 /* bseli.b */, Mips::BSELI_B, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
    4832             :   { 1621 /* bset.b */, Mips::BSET_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4833             :   { 1628 /* bset.d */, Mips::BSET_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4834             :   { 1635 /* bset.h */, Mips::BSET_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4835             :   { 1642 /* bset.w */, Mips::BSET_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    4836             :   { 1649 /* bseti.b */, Mips::BSETI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
    4837             :   { 1657 /* bseti.d */, Mips::BSETI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
    4838             :   { 1665 /* bseti.h */, Mips::BSETI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
    4839             :   { 1673 /* bseti.w */, Mips::BSETI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    4840             :   { 1681 /* bteqz */, Mips::BteqzX16, Convert__SImm161_0, Feature_InMips16Mode, { MCK_SImm16 }, },
    4841             :   { 1681 /* bteqz */, Mips::Bteqz16, Convert__SImm161_0, Feature_InMips16Mode, { MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
    4842             :   { 1687 /* btnez */, Mips::BtnezX16, Convert__SImm161_0, Feature_InMips16Mode, { MCK_SImm16 }, },
    4843             :   { 1687 /* btnez */, Mips::Btnez16, Convert__SImm161_0, Feature_InMips16Mode, { MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
    4844             :   { 1693 /* bz.b */, Mips::BZ_B, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
    4845             :   { 1698 /* bz.d */, Mips::BZ_D, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
    4846             :   { 1703 /* bz.h */, Mips::BZ_H, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
    4847             :   { 1708 /* bz.v */, Mips::BZ_V, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
    4848             :   { 1713 /* bz.w */, Mips::BZ_W, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
    4849             :   { 1718 /* c.eq.d */, Mips::C_EQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4850             :   { 1718 /* c.eq.d */, Mips::C_EQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4851             :   { 1718 /* c.eq.d */, Mips::C_EQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4852             :   { 1718 /* c.eq.d */, Mips::C_EQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4853             :   { 1718 /* c.eq.d */, Mips::C_EQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4854             :   { 1718 /* c.eq.d */, Mips::C_EQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4855             :   { 1718 /* c.eq.d */, Mips::C_EQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4856             :   { 1718 /* c.eq.d */, Mips::C_EQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4857             :   { 1725 /* c.eq.s */, Mips::C_EQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4858             :   { 1725 /* c.eq.s */, Mips::C_EQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4859             :   { 1725 /* c.eq.s */, Mips::C_EQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4860             :   { 1725 /* c.eq.s */, Mips::C_EQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4861             :   { 1732 /* c.f.d */, Mips::C_F_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4862             :   { 1732 /* c.f.d */, Mips::C_F_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4863             :   { 1732 /* c.f.d */, Mips::C_F_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4864             :   { 1732 /* c.f.d */, Mips::C_F_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4865             :   { 1732 /* c.f.d */, Mips::C_F_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4866             :   { 1732 /* c.f.d */, Mips::C_F_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4867             :   { 1732 /* c.f.d */, Mips::C_F_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4868             :   { 1732 /* c.f.d */, Mips::C_F_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4869             :   { 1738 /* c.f.s */, Mips::C_F_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4870             :   { 1738 /* c.f.s */, Mips::C_F_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4871             :   { 1738 /* c.f.s */, Mips::C_F_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4872             :   { 1738 /* c.f.s */, Mips::C_F_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4873             :   { 1744 /* c.le.d */, Mips::C_LE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4874             :   { 1744 /* c.le.d */, Mips::C_LE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4875             :   { 1744 /* c.le.d */, Mips::C_LE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4876             :   { 1744 /* c.le.d */, Mips::C_LE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4877             :   { 1744 /* c.le.d */, Mips::C_LE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4878             :   { 1744 /* c.le.d */, Mips::C_LE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4879             :   { 1744 /* c.le.d */, Mips::C_LE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4880             :   { 1744 /* c.le.d */, Mips::C_LE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4881             :   { 1751 /* c.le.s */, Mips::C_LE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4882             :   { 1751 /* c.le.s */, Mips::C_LE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4883             :   { 1751 /* c.le.s */, Mips::C_LE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4884             :   { 1751 /* c.le.s */, Mips::C_LE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4885             :   { 1758 /* c.lt.d */, Mips::C_LT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4886             :   { 1758 /* c.lt.d */, Mips::C_LT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4887             :   { 1758 /* c.lt.d */, Mips::C_LT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4888             :   { 1758 /* c.lt.d */, Mips::C_LT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4889             :   { 1758 /* c.lt.d */, Mips::C_LT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4890             :   { 1758 /* c.lt.d */, Mips::C_LT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4891             :   { 1758 /* c.lt.d */, Mips::C_LT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4892             :   { 1758 /* c.lt.d */, Mips::C_LT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4893             :   { 1765 /* c.lt.s */, Mips::C_LT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4894             :   { 1765 /* c.lt.s */, Mips::C_LT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4895             :   { 1765 /* c.lt.s */, Mips::C_LT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4896             :   { 1765 /* c.lt.s */, Mips::C_LT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4897             :   { 1772 /* c.nge.d */, Mips::C_NGE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4898             :   { 1772 /* c.nge.d */, Mips::C_NGE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4899             :   { 1772 /* c.nge.d */, Mips::C_NGE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4900             :   { 1772 /* c.nge.d */, Mips::C_NGE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4901             :   { 1772 /* c.nge.d */, Mips::C_NGE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4902             :   { 1772 /* c.nge.d */, Mips::C_NGE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4903             :   { 1772 /* c.nge.d */, Mips::C_NGE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4904             :   { 1772 /* c.nge.d */, Mips::C_NGE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4905             :   { 1780 /* c.nge.s */, Mips::C_NGE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4906             :   { 1780 /* c.nge.s */, Mips::C_NGE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4907             :   { 1780 /* c.nge.s */, Mips::C_NGE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4908             :   { 1780 /* c.nge.s */, Mips::C_NGE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4909             :   { 1788 /* c.ngl.d */, Mips::C_NGL_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4910             :   { 1788 /* c.ngl.d */, Mips::C_NGL_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4911             :   { 1788 /* c.ngl.d */, Mips::C_NGL_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4912             :   { 1788 /* c.ngl.d */, Mips::C_NGL_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4913             :   { 1788 /* c.ngl.d */, Mips::C_NGL_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4914             :   { 1788 /* c.ngl.d */, Mips::C_NGL_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4915             :   { 1788 /* c.ngl.d */, Mips::C_NGL_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4916             :   { 1788 /* c.ngl.d */, Mips::C_NGL_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4917             :   { 1796 /* c.ngl.s */, Mips::C_NGL_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4918             :   { 1796 /* c.ngl.s */, Mips::C_NGL_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4919             :   { 1796 /* c.ngl.s */, Mips::C_NGL_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4920             :   { 1796 /* c.ngl.s */, Mips::C_NGL_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4921             :   { 1804 /* c.ngle.d */, Mips::C_NGLE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4922             :   { 1804 /* c.ngle.d */, Mips::C_NGLE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4923             :   { 1804 /* c.ngle.d */, Mips::C_NGLE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4924             :   { 1804 /* c.ngle.d */, Mips::C_NGLE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4925             :   { 1804 /* c.ngle.d */, Mips::C_NGLE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4926             :   { 1804 /* c.ngle.d */, Mips::C_NGLE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4927             :   { 1804 /* c.ngle.d */, Mips::C_NGLE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4928             :   { 1804 /* c.ngle.d */, Mips::C_NGLE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4929             :   { 1813 /* c.ngle.s */, Mips::C_NGLE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4930             :   { 1813 /* c.ngle.s */, Mips::C_NGLE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4931             :   { 1813 /* c.ngle.s */, Mips::C_NGLE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4932             :   { 1813 /* c.ngle.s */, Mips::C_NGLE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4933             :   { 1822 /* c.ngt.d */, Mips::C_NGT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4934             :   { 1822 /* c.ngt.d */, Mips::C_NGT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4935             :   { 1822 /* c.ngt.d */, Mips::C_NGT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4936             :   { 1822 /* c.ngt.d */, Mips::C_NGT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4937             :   { 1822 /* c.ngt.d */, Mips::C_NGT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4938             :   { 1822 /* c.ngt.d */, Mips::C_NGT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4939             :   { 1822 /* c.ngt.d */, Mips::C_NGT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4940             :   { 1822 /* c.ngt.d */, Mips::C_NGT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4941             :   { 1830 /* c.ngt.s */, Mips::C_NGT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4942             :   { 1830 /* c.ngt.s */, Mips::C_NGT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4943             :   { 1830 /* c.ngt.s */, Mips::C_NGT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4944             :   { 1830 /* c.ngt.s */, Mips::C_NGT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4945             :   { 1838 /* c.ole.d */, Mips::C_OLE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4946             :   { 1838 /* c.ole.d */, Mips::C_OLE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4947             :   { 1838 /* c.ole.d */, Mips::C_OLE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4948             :   { 1838 /* c.ole.d */, Mips::C_OLE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4949             :   { 1838 /* c.ole.d */, Mips::C_OLE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4950             :   { 1838 /* c.ole.d */, Mips::C_OLE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4951             :   { 1838 /* c.ole.d */, Mips::C_OLE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4952             :   { 1838 /* c.ole.d */, Mips::C_OLE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4953             :   { 1846 /* c.ole.s */, Mips::C_OLE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4954             :   { 1846 /* c.ole.s */, Mips::C_OLE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4955             :   { 1846 /* c.ole.s */, Mips::C_OLE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4956             :   { 1846 /* c.ole.s */, Mips::C_OLE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4957             :   { 1854 /* c.olt.d */, Mips::C_OLT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4958             :   { 1854 /* c.olt.d */, Mips::C_OLT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4959             :   { 1854 /* c.olt.d */, Mips::C_OLT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4960             :   { 1854 /* c.olt.d */, Mips::C_OLT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4961             :   { 1854 /* c.olt.d */, Mips::C_OLT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4962             :   { 1854 /* c.olt.d */, Mips::C_OLT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4963             :   { 1854 /* c.olt.d */, Mips::C_OLT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4964             :   { 1854 /* c.olt.d */, Mips::C_OLT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4965             :   { 1862 /* c.olt.s */, Mips::C_OLT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4966             :   { 1862 /* c.olt.s */, Mips::C_OLT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4967             :   { 1862 /* c.olt.s */, Mips::C_OLT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4968             :   { 1862 /* c.olt.s */, Mips::C_OLT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4969             :   { 1870 /* c.seq.d */, Mips::C_SEQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4970             :   { 1870 /* c.seq.d */, Mips::C_SEQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4971             :   { 1870 /* c.seq.d */, Mips::C_SEQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4972             :   { 1870 /* c.seq.d */, Mips::C_SEQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4973             :   { 1870 /* c.seq.d */, Mips::C_SEQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4974             :   { 1870 /* c.seq.d */, Mips::C_SEQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4975             :   { 1870 /* c.seq.d */, Mips::C_SEQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4976             :   { 1870 /* c.seq.d */, Mips::C_SEQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4977             :   { 1878 /* c.seq.s */, Mips::C_SEQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4978             :   { 1878 /* c.seq.s */, Mips::C_SEQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4979             :   { 1878 /* c.seq.s */, Mips::C_SEQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4980             :   { 1878 /* c.seq.s */, Mips::C_SEQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4981             :   { 1886 /* c.sf.d */, Mips::C_SF_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4982             :   { 1886 /* c.sf.d */, Mips::C_SF_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4983             :   { 1886 /* c.sf.d */, Mips::C_SF_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4984             :   { 1886 /* c.sf.d */, Mips::C_SF_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4985             :   { 1886 /* c.sf.d */, Mips::C_SF_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4986             :   { 1886 /* c.sf.d */, Mips::C_SF_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4987             :   { 1886 /* c.sf.d */, Mips::C_SF_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4988             :   { 1886 /* c.sf.d */, Mips::C_SF_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4989             :   { 1893 /* c.sf.s */, Mips::C_SF_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4990             :   { 1893 /* c.sf.s */, Mips::C_SF_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4991             :   { 1893 /* c.sf.s */, Mips::C_SF_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4992             :   { 1893 /* c.sf.s */, Mips::C_SF_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    4993             :   { 1900 /* c.ueq.d */, Mips::C_UEQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4994             :   { 1900 /* c.ueq.d */, Mips::C_UEQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4995             :   { 1900 /* c.ueq.d */, Mips::C_UEQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4996             :   { 1900 /* c.ueq.d */, Mips::C_UEQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    4997             :   { 1900 /* c.ueq.d */, Mips::C_UEQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4998             :   { 1900 /* c.ueq.d */, Mips::C_UEQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    4999             :   { 1900 /* c.ueq.d */, Mips::C_UEQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5000             :   { 1900 /* c.ueq.d */, Mips::C_UEQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5001             :   { 1908 /* c.ueq.s */, Mips::C_UEQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5002             :   { 1908 /* c.ueq.s */, Mips::C_UEQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5003             :   { 1908 /* c.ueq.s */, Mips::C_UEQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5004             :   { 1908 /* c.ueq.s */, Mips::C_UEQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5005             :   { 1916 /* c.ule.d */, Mips::C_ULE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    5006             :   { 1916 /* c.ule.d */, Mips::C_ULE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    5007             :   { 1916 /* c.ule.d */, Mips::C_ULE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5008             :   { 1916 /* c.ule.d */, Mips::C_ULE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5009             :   { 1916 /* c.ule.d */, Mips::C_ULE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    5010             :   { 1916 /* c.ule.d */, Mips::C_ULE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    5011             :   { 1916 /* c.ule.d */, Mips::C_ULE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5012             :   { 1916 /* c.ule.d */, Mips::C_ULE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5013             :   { 1924 /* c.ule.s */, Mips::C_ULE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5014             :   { 1924 /* c.ule.s */, Mips::C_ULE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5015             :   { 1924 /* c.ule.s */, Mips::C_ULE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5016             :   { 1924 /* c.ule.s */, Mips::C_ULE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5017             :   { 1932 /* c.ult.d */, Mips::C_ULT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    5018             :   { 1932 /* c.ult.d */, Mips::C_ULT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    5019             :   { 1932 /* c.ult.d */, Mips::C_ULT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5020             :   { 1932 /* c.ult.d */, Mips::C_ULT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5021             :   { 1932 /* c.ult.d */, Mips::C_ULT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    5022             :   { 1932 /* c.ult.d */, Mips::C_ULT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    5023             :   { 1932 /* c.ult.d */, Mips::C_ULT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5024             :   { 1932 /* c.ult.d */, Mips::C_ULT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5025             :   { 1940 /* c.ult.s */, Mips::C_ULT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5026             :   { 1940 /* c.ult.s */, Mips::C_ULT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5027             :   { 1940 /* c.ult.s */, Mips::C_ULT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5028             :   { 1940 /* c.ult.s */, Mips::C_ULT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5029             :   { 1948 /* c.un.d */, Mips::C_UN_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    5030             :   { 1948 /* c.un.d */, Mips::C_UN_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    5031             :   { 1948 /* c.un.d */, Mips::C_UN_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5032             :   { 1948 /* c.un.d */, Mips::C_UN_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5033             :   { 1948 /* c.un.d */, Mips::C_UN_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    5034             :   { 1948 /* c.un.d */, Mips::C_UN_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    5035             :   { 1948 /* c.un.d */, Mips::C_UN_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5036             :   { 1948 /* c.un.d */, Mips::C_UN_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5037             :   { 1955 /* c.un.s */, Mips::C_UN_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5038             :   { 1955 /* c.un.s */, Mips::C_UN_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5039             :   { 1955 /* c.un.s */, Mips::C_UN_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5040             :   { 1955 /* c.un.s */, Mips::C_UN_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5041             :   { 1962 /* cache */, Mips::CACHE_R6, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
    5042             :   { 1962 /* cache */, Mips::CACHE, Convert__Mem2_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
    5043             :   { 1962 /* cache */, Mips::CACHE_MMR6, Convert__Mem2_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
    5044             :   { 1962 /* cache */, Mips::CACHE_MM, Convert__Mem2_1__ConstantUImm5_01_0, Feature_InMicroMips, { MCK_ConstantUImm5_0, MCK_Mem }, },
    5045             :   { 1968 /* cachee */, Mips::CACHEE, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasEVA, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
    5046             :   { 1968 /* cachee */, Mips::CACHEE_MMR6, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
    5047             :   { 1968 /* cachee */, Mips::CACHEE_MM, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_InMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
    5048             :   { 1975 /* ceil.l.d */, Mips::CEIL_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5049             :   { 1975 /* ceil.l.d */, Mips::CEIL_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5050             :   { 1984 /* ceil.l.s */, Mips::CEIL_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
    5051             :   { 1984 /* ceil.l.s */, Mips::CEIL_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
    5052             :   { 1993 /* ceil.w.d */, Mips::CEIL_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
    5053             :   { 1993 /* ceil.w.d */, Mips::CEIL_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
    5054             :   { 1993 /* ceil.w.d */, Mips::CEIL_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
    5055             :   { 2002 /* ceil.w.s */, Mips::CEIL_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5056             :   { 2002 /* ceil.w.s */, Mips::CEIL_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5057             :   { 2002 /* ceil.w.s */, Mips::CEIL_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5058             :   { 2011 /* ceq.b */, Mips::CEQ_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5059             :   { 2017 /* ceq.d */, Mips::CEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5060             :   { 2023 /* ceq.h */, Mips::CEQ_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5061             :   { 2029 /* ceq.w */, Mips::CEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5062             :   { 2035 /* ceqi.b */, Mips::CEQI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
    5063             :   { 2042 /* ceqi.d */, Mips::CEQI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
    5064             :   { 2049 /* ceqi.h */, Mips::CEQI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
    5065             :   { 2056 /* ceqi.w */, Mips::CEQI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
    5066             :   { 2063 /* cfc1 */, Mips::CFC1, Convert__GPR32AsmReg1_0__CCRAsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, },
    5067             :   { 2063 /* cfc1 */, Mips::CFC1_MM, Convert__GPR32AsmReg1_0__CCRAsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, },
    5068             :   { 2068 /* cfc2 */, Mips::CFC2_MM, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, Feature_HasStdEnc|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
    5069             :   { 2073 /* cfcmsa */, Mips::CFCMSA, Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSACtrlAsmReg }, },
    5070             :   { 2080 /* cins */, Mips::CINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
    5071             :   { 2080 /* cins */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2, Feature_HasMips64|Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
    5072             :   { 2080 /* cins */, Mips::CINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
    5073             :   { 2080 /* cins */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3, Feature_HasMips64|Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
    5074             :   { 2085 /* cins32 */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
    5075             :   { 2085 /* cins32 */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
    5076             :   { 2092 /* class.d */, Mips::CLASS_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5077             :   { 2092 /* class.d */, Mips::CLASS_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5078             :   { 2100 /* class.s */, Mips::CLASS_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5079             :   { 2100 /* class.s */, Mips::CLASS_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5080             :   { 2108 /* cle_s.b */, Mips::CLE_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5081             :   { 2116 /* cle_s.d */, Mips::CLE_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5082             :   { 2124 /* cle_s.h */, Mips::CLE_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5083             :   { 2132 /* cle_s.w */, Mips::CLE_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5084             :   { 2140 /* cle_u.b */, Mips::CLE_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5085             :   { 2148 /* cle_u.d */, Mips::CLE_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5086             :   { 2156 /* cle_u.h */, Mips::CLE_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5087             :   { 2164 /* cle_u.w */, Mips::CLE_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5088             :   { 2172 /* clei_s.b */, Mips::CLEI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
    5089             :   { 2181 /* clei_s.d */, Mips::CLEI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
    5090             :   { 2190 /* clei_s.h */, Mips::CLEI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
    5091             :   { 2199 /* clei_s.w */, Mips::CLEI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
    5092             :   { 2208 /* clei_u.b */, Mips::CLEI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    5093             :   { 2217 /* clei_u.d */, Mips::CLEI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    5094             :   { 2226 /* clei_u.h */, Mips::CLEI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    5095             :   { 2235 /* clei_u.w */, Mips::CLEI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    5096             :   { 2244 /* clo */, Mips::CLO, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5097             :   { 2244 /* clo */, Mips::CLO_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5098             :   { 2244 /* clo */, Mips::CLO_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5099             :   { 2244 /* clo */, Mips::CLO_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5100             :   { 2248 /* clt_s.b */, Mips::CLT_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5101             :   { 2256 /* clt_s.d */, Mips::CLT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5102             :   { 2264 /* clt_s.h */, Mips::CLT_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5103             :   { 2272 /* clt_s.w */, Mips::CLT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5104             :   { 2280 /* clt_u.b */, Mips::CLT_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5105             :   { 2288 /* clt_u.d */, Mips::CLT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5106             :   { 2296 /* clt_u.h */, Mips::CLT_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5107             :   { 2304 /* clt_u.w */, Mips::CLT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5108             :   { 2312 /* clti_s.b */, Mips::CLTI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
    5109             :   { 2321 /* clti_s.d */, Mips::CLTI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
    5110             :   { 2330 /* clti_s.h */, Mips::CLTI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
    5111             :   { 2339 /* clti_s.w */, Mips::CLTI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
    5112             :   { 2348 /* clti_u.b */, Mips::CLTI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    5113             :   { 2357 /* clti_u.d */, Mips::CLTI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    5114             :   { 2366 /* clti_u.h */, Mips::CLTI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    5115             :   { 2375 /* clti_u.w */, Mips::CLTI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    5116             :   { 2384 /* clz */, Mips::CLZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5117             :   { 2384 /* clz */, Mips::CLZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5118             :   { 2384 /* clz */, Mips::CLZ_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5119             :   { 2384 /* clz */, Mips::CLZ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5120             :   { 2388 /* cmp */, Mips::CmpRxRy16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
    5121             :   { 2392 /* cmp.af.d */, Mips::CMP_F_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5122             :   { 2392 /* cmp.af.d */, Mips::CMP_AF_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5123             :   { 2401 /* cmp.af.s */, Mips::CMP_F_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5124             :   { 2401 /* cmp.af.s */, Mips::CMP_AF_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5125             :   { 2410 /* cmp.eq.d */, Mips::CMP_EQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5126             :   { 2410 /* cmp.eq.d */, Mips::CMP_EQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5127             :   { 2419 /* cmp.eq.ph */, Mips::CMP_EQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5128             :   { 2419 /* cmp.eq.ph */, Mips::CMP_EQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5129             :   { 2429 /* cmp.eq.s */, Mips::CMP_EQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5130             :   { 2429 /* cmp.eq.s */, Mips::CMP_EQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5131             :   { 2438 /* cmp.le.d */, Mips::CMP_LE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5132             :   { 2438 /* cmp.le.d */, Mips::CMP_LE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5133             :   { 2447 /* cmp.le.ph */, Mips::CMP_LE_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5134             :   { 2447 /* cmp.le.ph */, Mips::CMP_LE_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5135             :   { 2457 /* cmp.le.s */, Mips::CMP_LE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5136             :   { 2457 /* cmp.le.s */, Mips::CMP_LE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5137             :   { 2466 /* cmp.lt.d */, Mips::CMP_LT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5138             :   { 2466 /* cmp.lt.d */, Mips::CMP_LT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5139             :   { 2475 /* cmp.lt.ph */, Mips::CMP_LT_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5140             :   { 2475 /* cmp.lt.ph */, Mips::CMP_LT_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5141             :   { 2485 /* cmp.lt.s */, Mips::CMP_LT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5142             :   { 2485 /* cmp.lt.s */, Mips::CMP_LT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5143             :   { 2494 /* cmp.saf.d */, Mips::CMP_SAF_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5144             :   { 2494 /* cmp.saf.d */, Mips::CMP_SAF_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5145             :   { 2504 /* cmp.saf.s */, Mips::CMP_SAF_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5146             :   { 2504 /* cmp.saf.s */, Mips::CMP_SAF_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5147             :   { 2514 /* cmp.seq.d */, Mips::CMP_SEQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5148             :   { 2514 /* cmp.seq.d */, Mips::CMP_SEQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5149             :   { 2524 /* cmp.seq.s */, Mips::CMP_SEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5150             :   { 2524 /* cmp.seq.s */, Mips::CMP_SEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5151             :   { 2534 /* cmp.sle.d */, Mips::CMP_SLE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5152             :   { 2534 /* cmp.sle.d */, Mips::CMP_SLE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5153             :   { 2544 /* cmp.sle.s */, Mips::CMP_SLE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5154             :   { 2544 /* cmp.sle.s */, Mips::CMP_SLE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5155             :   { 2554 /* cmp.slt.d */, Mips::CMP_SLT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5156             :   { 2554 /* cmp.slt.d */, Mips::CMP_SLT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5157             :   { 2564 /* cmp.slt.s */, Mips::CMP_SLT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5158             :   { 2564 /* cmp.slt.s */, Mips::CMP_SLT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5159             :   { 2574 /* cmp.sueq.d */, Mips::CMP_SUEQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5160             :   { 2574 /* cmp.sueq.d */, Mips::CMP_SUEQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5161             :   { 2585 /* cmp.sueq.s */, Mips::CMP_SUEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5162             :   { 2585 /* cmp.sueq.s */, Mips::CMP_SUEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5163             :   { 2596 /* cmp.sule.d */, Mips::CMP_SULE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5164             :   { 2596 /* cmp.sule.d */, Mips::CMP_SULE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5165             :   { 2607 /* cmp.sule.s */, Mips::CMP_SULE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5166             :   { 2607 /* cmp.sule.s */, Mips::CMP_SULE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5167             :   { 2618 /* cmp.sult.d */, Mips::CMP_SULT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5168             :   { 2618 /* cmp.sult.d */, Mips::CMP_SULT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5169             :   { 2629 /* cmp.sult.s */, Mips::CMP_SULT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5170             :   { 2629 /* cmp.sult.s */, Mips::CMP_SULT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5171             :   { 2640 /* cmp.sun.d */, Mips::CMP_SUN_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5172             :   { 2640 /* cmp.sun.d */, Mips::CMP_SUN_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5173             :   { 2650 /* cmp.sun.s */, Mips::CMP_SUN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5174             :   { 2650 /* cmp.sun.s */, Mips::CMP_SUN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5175             :   { 2660 /* cmp.ueq.d */, Mips::CMP_UEQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5176             :   { 2660 /* cmp.ueq.d */, Mips::CMP_UEQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5177             :   { 2670 /* cmp.ueq.s */, Mips::CMP_UEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5178             :   { 2670 /* cmp.ueq.s */, Mips::CMP_UEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5179             :   { 2680 /* cmp.ule.d */, Mips::CMP_ULE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5180             :   { 2680 /* cmp.ule.d */, Mips::CMP_ULE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5181             :   { 2690 /* cmp.ule.s */, Mips::CMP_ULE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5182             :   { 2690 /* cmp.ule.s */, Mips::CMP_ULE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5183             :   { 2700 /* cmp.ult.d */, Mips::CMP_ULT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5184             :   { 2700 /* cmp.ult.d */, Mips::CMP_ULT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5185             :   { 2710 /* cmp.ult.s */, Mips::CMP_ULT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5186             :   { 2710 /* cmp.ult.s */, Mips::CMP_ULT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5187             :   { 2720 /* cmp.un.d */, Mips::CMP_UN_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5188             :   { 2720 /* cmp.un.d */, Mips::CMP_UN_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5189             :   { 2729 /* cmp.un.s */, Mips::CMP_UN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5190             :   { 2729 /* cmp.un.s */, Mips::CMP_UN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5191             :   { 2738 /* cmpgdu.eq.qb */, Mips::CMPGDU_EQ_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5192             :   { 2738 /* cmpgdu.eq.qb */, Mips::CMPGDU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5193             :   { 2751 /* cmpgdu.le.qb */, Mips::CMPGDU_LE_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5194             :   { 2751 /* cmpgdu.le.qb */, Mips::CMPGDU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5195             :   { 2764 /* cmpgdu.lt.qb */, Mips::CMPGDU_LT_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5196             :   { 2764 /* cmpgdu.lt.qb */, Mips::CMPGDU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5197             :   { 2777 /* cmpgu.eq.qb */, Mips::CMPGU_EQ_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5198             :   { 2777 /* cmpgu.eq.qb */, Mips::CMPGU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5199             :   { 2789 /* cmpgu.le.qb */, Mips::CMPGU_LE_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5200             :   { 2789 /* cmpgu.le.qb */, Mips::CMPGU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5201             :   { 2801 /* cmpgu.lt.qb */, Mips::CMPGU_LT_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5202             :   { 2801 /* cmpgu.lt.qb */, Mips::CMPGU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5203             :   { 2813 /* cmpi */, Mips::CmpiRxImmX16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
    5204             :   { 2813 /* cmpi */, Mips::CmpiRxImm16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
    5205             :   { 2818 /* cmpu.eq.qb */, Mips::CMPU_EQ_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5206             :   { 2818 /* cmpu.eq.qb */, Mips::CMPU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5207             :   { 2829 /* cmpu.le.qb */, Mips::CMPU_LE_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5208             :   { 2829 /* cmpu.le.qb */, Mips::CMPU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5209             :   { 2840 /* cmpu.lt.qb */, Mips::CMPU_LT_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5210             :   { 2840 /* cmpu.lt.qb */, Mips::CMPU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5211             :   { 2851 /* copy_s.b */, Mips::COPY_S_B, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, },
    5212             :   { 2860 /* copy_s.d */, Mips::COPY_S_D, Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, { MCK_GPR64AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, },
    5213             :   { 2869 /* copy_s.h */, Mips::COPY_S_H, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, },
    5214             :   { 2878 /* copy_s.w */, Mips::COPY_S_W, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, },
    5215             :   { 2887 /* copy_u.b */, Mips::COPY_U_B, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, },
    5216             :   { 2896 /* copy_u.h */, Mips::COPY_U_H, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, },
    5217             :   { 2905 /* copy_u.w */, Mips::COPY_U_W, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, },
    5218             :   { 2914 /* ctc1 */, Mips::CTC1, Convert__CCRAsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, },
    5219             :   { 2914 /* ctc1 */, Mips::CTC1_MM, Convert__CCRAsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, },
    5220             :   { 2919 /* ctc2 */, Mips::CTC2_MM, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
    5221             :   { 2924 /* ctcmsa */, Mips::CTCMSA, Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSACtrlAsmReg, MCK_GPR32AsmReg }, },
    5222             :   { 2931 /* cvt.d.l */, Mips::CVT_D_L_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5223             :   { 2931 /* cvt.d.l */, Mips::CVT_D64_L, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5224             :   { 2939 /* cvt.d.s */, Mips::CVT_D32_S, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, },
    5225             :   { 2939 /* cvt.d.s */, Mips::CVT_D_S_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
    5226             :   { 2939 /* cvt.d.s */, Mips::CVT_D64_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
    5227             :   { 2947 /* cvt.d.w */, Mips::CVT_D32_W, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, },
    5228             :   { 2947 /* cvt.d.w */, Mips::CVT_D_W_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
    5229             :   { 2947 /* cvt.d.w */, Mips::CVT_D64_W, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
    5230             :   { 2955 /* cvt.l.d */, Mips::CVT_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5231             :   { 2955 /* cvt.l.d */, Mips::CVT_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5232             :   { 2963 /* cvt.l.s */, Mips::CVT_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
    5233             :   { 2963 /* cvt.l.s */, Mips::CVT_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
    5234             :   { 2971 /* cvt.s.d */, Mips::CVT_S_D_MMR6, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, },
    5235             :   { 2971 /* cvt.s.d */, Mips::CVT_S_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
    5236             :   { 2971 /* cvt.s.d */, Mips::CVT_S_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
    5237             :   { 2979 /* cvt.s.l */, Mips::CVT_S_L, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
    5238             :   { 2979 /* cvt.s.l */, Mips::CVT_S_L_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
    5239             :   { 2987 /* cvt.s.w */, Mips::CVT_S_W_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5240             :   { 2987 /* cvt.s.w */, Mips::CVT_S_W, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5241             :   { 2995 /* cvt.w.d */, Mips::CVT_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
    5242             :   { 2995 /* cvt.w.d */, Mips::CVT_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
    5243             :   { 2995 /* cvt.w.d */, Mips::CVT_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
    5244             :   { 3003 /* cvt.w.s */, Mips::CVT_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5245             :   { 3003 /* cvt.w.s */, Mips::CVT_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5246             :   { 3011 /* dadd */, Mips::DADD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5247             :   { 3011 /* dadd */, Mips::DADD_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5248             :   { 3011 /* dadd */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, },
    5249             :   { 3011 /* dadd */, Mips::DADD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5250             :   { 3011 /* dadd */, Mips::DADD_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5251             :   { 3011 /* dadd */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, },
    5252             :   { 3016 /* daddi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_SImm16 }, },
    5253             :   { 3016 /* daddi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, },
    5254             :   { 3022 /* daddiu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, },
    5255             :   { 3022 /* daddiu */, Mips::DADDIU_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_SImm16 }, },
    5256             :   { 3022 /* daddiu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, },
    5257             :   { 3022 /* daddiu */, Mips::DADDIU_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, },
    5258             :   { 3029 /* daddu */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5259             :   { 3029 /* daddu */, Mips::DADDU_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5260             :   { 3029 /* daddu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, },
    5261             :   { 3029 /* daddu */, Mips::DADDIU_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_SImm16 }, },
    5262             :   { 3029 /* daddu */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5263             :   { 3029 /* daddu */, Mips::DADDU_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5264             :   { 3029 /* daddu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, },
    5265             :   { 3029 /* daddu */, Mips::DADDIU_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, },
    5266             :   { 3035 /* dahi */, Mips::DAHI, Convert__GPR64AsmReg1_0__Tie0__UImm16_AltRelaxed1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16_AltRelaxed }, },
    5267             :   { 3035 /* dahi */, Mips::DAHI_MM64R6, Convert__GPR64AsmReg1_0__Tie0__UImm161_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16 }, },
    5268             :   { 3040 /* dalign */, Mips::DALIGN, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm3_0 }, },
    5269             :   { 3040 /* dalign */, Mips::DALIGN_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm3_0 }, },
    5270             :   { 3047 /* dati */, Mips::DATI, Convert__GPR64AsmReg1_0__Tie0__UImm16_AltRelaxed1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16_AltRelaxed }, },
    5271             :   { 3047 /* dati */, Mips::DATI_MM64R6, Convert__GPR64AsmReg1_0__Tie0__UImm161_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16 }, },
    5272             :   { 3052 /* daui */, Mips::DAUI, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16 }, },
    5273             :   { 3052 /* daui */, Mips::DAUI_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16 }, },
    5274             :   { 3057 /* dbitswap */, Mips::DBITSWAP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5275             :   { 3057 /* dbitswap */, Mips::DBITSWAP_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5276             :   { 3066 /* dclo */, Mips::DCLO, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5277             :   { 3066 /* dclo */, Mips::DCLO_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5278             :   { 3066 /* dclo */, Mips::DCLO_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5279             :   { 3071 /* dclz */, Mips::DCLZ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5280             :   { 3071 /* dclz */, Mips::DCLZ_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5281             :   { 3071 /* dclz */, Mips::DCLZ_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5282             :   { 3076 /* ddiv */, Mips::DSDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5283             :   { 3076 /* ddiv */, Mips::DSDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
    5284             :   { 3076 /* ddiv */, Mips::DSDIV, Convert__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5285             :   { 3076 /* ddiv */, Mips::DSDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5286             :   { 3076 /* ddiv */, Mips::DDIV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5287             :   { 3076 /* ddiv */, Mips::DDIV_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5288             :   { 3076 /* ddiv */, Mips::DSDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
    5289             :   { 3081 /* ddivu */, Mips::DUDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5290             :   { 3081 /* ddivu */, Mips::DUDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
    5291             :   { 3081 /* ddivu */, Mips::DUDIV, Convert__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5292             :   { 3081 /* ddivu */, Mips::DUDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5293             :   { 3081 /* ddivu */, Mips::DDIVU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5294             :   { 3081 /* ddivu */, Mips::DDIVU_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5295             :   { 3081 /* ddivu */, Mips::DUDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
    5296             :   { 3087 /* deret */, Mips::DERET, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32|Feature_NotInMicroMips, {  }, },
    5297             :   { 3087 /* deret */, Mips::DERET_MMR6, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMicroMips32r6, {  }, },
    5298             :   { 3087 /* deret */, Mips::DERET_MM, Convert_NoOperands, Feature_InMicroMips, {  }, },
    5299             :   { 3093 /* dext */, Mips::DEXT, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_11_3, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_ConstantUImm5_1 }, },
    5300             :   { 3093 /* dext */, Mips::DEXT_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_11_3, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_ConstantUImm5_1 }, },
    5301             :   { 3098 /* dextm */, Mips::DEXTM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_33 }, },
    5302             :   { 3098 /* dextm */, Mips::DEXTM_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_33 }, },
    5303             :   { 3104 /* dextu */, Mips::DEXTU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, },
    5304             :   { 3104 /* dextu */, Mips::DEXTU_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, },
    5305             :   { 3110 /* di */, Mips::DI, Convert__regZERO, Feature_HasMips32r2|Feature_NotInMicroMips, {  }, },
    5306             :   { 3110 /* di */, Mips::DI_MM, Convert__regZERO, Feature_InMicroMips, {  }, },
    5307             :   { 3110 /* di */, Mips::DI_MMR6, Convert__regZERO, Feature_HasMicroMips32r6, {  }, },
    5308             :   { 3110 /* di */, Mips::DI, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
    5309             :   { 3110 /* di */, Mips::DI_MMR6, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg }, },
    5310             :   { 3110 /* di */, Mips::DI_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
    5311             :   { 3113 /* dins */, Mips::DINS_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
    5312             :   { 3113 /* dins */, Mips::DINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0, MCK_ConstantUImm5_1 }, },
    5313             :   { 3118 /* dinsm */, Mips::DINSM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImmRange2_64 }, },
    5314             :   { 3118 /* dinsm */, Mips::DINSM_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImmRange2_64 }, },
    5315             :   { 3124 /* dinsu */, Mips::DINSU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, },
    5316             :   { 3124 /* dinsu */, Mips::DINSU_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, },
    5317             :   { 3130 /* div */, Mips::DIV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5318             :   { 3130 /* div */, Mips::SDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32 }, },
    5319             :   { 3130 /* div */, Mips::SDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg }, },
    5320             :   { 3130 /* div */, Mips::SDIV, Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32ZeroAsmReg, MCK_GPR32AsmReg }, },
    5321             :   { 3130 /* div */, Mips::DivRxRy16, Convert__Reg1_1__Reg1_2, Feature_InMips16Mode, { MCK_GPR32ZERO, MCK_CPU16Regs, MCK_CPU16Regs }, },
    5322             :   { 3130 /* div */, Mips::SDIV, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5323             :   { 3130 /* div */, Mips::SDIV_MM, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5324             :   { 3130 /* div */, Mips::DIV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5325             :   { 3130 /* div */, Mips::DIV_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5326             :   { 3130 /* div */, Mips::SDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, },
    5327             :   { 3130 /* div */, Mips::SDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5328             :   { 3134 /* div.d */, Mips::FDIV_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    5329             :   { 3134 /* div.d */, Mips::FDIV_D_MMR6, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_2__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    5330             :   { 3134 /* div.d */, Mips::FDIV_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5331             :   { 3140 /* div.s */, Mips::FDIV_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5332             :   { 3140 /* div.s */, Mips::FDIV_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5333             :   { 3146 /* div_s.b */, Mips::DIV_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5334             :   { 3154 /* div_s.d */, Mips::DIV_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5335             :   { 3162 /* div_s.h */, Mips::DIV_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5336             :   { 3170 /* div_s.w */, Mips::DIV_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5337             :   { 3178 /* div_u.b */, Mips::DIV_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5338             :   { 3186 /* div_u.d */, Mips::DIV_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5339             :   { 3194 /* div_u.h */, Mips::DIV_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5340             :   { 3202 /* div_u.w */, Mips::DIV_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5341             :   { 3210 /* divu */, Mips::DIVU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5342             :   { 3210 /* divu */, Mips::UDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32 }, },
    5343             :   { 3210 /* divu */, Mips::UDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg }, },
    5344             :   { 3210 /* divu */, Mips::UDIV, Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32ZeroAsmReg, MCK_GPR32AsmReg }, },
    5345             :   { 3210 /* divu */, Mips::DivuRxRy16, Convert__Reg1_1__Reg1_2, Feature_InMips16Mode, { MCK_GPR32ZERO, MCK_CPU16Regs, MCK_CPU16Regs }, },
    5346             :   { 3210 /* divu */, Mips::UDIV, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5347             :   { 3210 /* divu */, Mips::UDIV_MM, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5348             :   { 3210 /* divu */, Mips::DIVU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5349             :   { 3210 /* divu */, Mips::DIVU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5350             :   { 3210 /* divu */, Mips::UDivMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5351             :   { 3210 /* divu */, Mips::UDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, },
    5352             :   { 3215 /* dla */, Mips::LoadAddrImm64, Convert__GPR64AsmReg1_0__Imm1_1, 0, { MCK_GPR64AsmReg, MCK_Imm }, },
    5353             :   { 3215 /* dla */, Mips::LoadAddrReg64, Convert__GPR64AsmReg1_0__Mem2_1, 0, { MCK_GPR64AsmReg, MCK_Mem }, },
    5354             :   { 3219 /* dli */, Mips::LoadImm64, Convert__GPR64AsmReg1_0__Imm1_1, 0, { MCK_GPR64AsmReg, MCK_Imm }, },
    5355             :   { 3223 /* dlsa */, Mips::DLSA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3, Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm2_1 }, },
    5356             :   { 3223 /* dlsa */, Mips::DLSA_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm2_1 }, },
    5357             :   { 3223 /* dlsa */, Mips::DLSA_MM64R6, Convert__GPR64AsmReg1_2__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm2_11_3, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm2_1 }, },
    5358             :   { 3228 /* dmfc0 */, Mips::DMFC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
    5359             :   { 3228 /* dmfc0 */, Mips::DMFC0_MM64R6, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
    5360             :   { 3228 /* dmfc0 */, Mips::DMFC0_MM64R6, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
    5361             :   { 3228 /* dmfc0 */, Mips::DMFC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_HasMips64, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
    5362             :   { 3234 /* dmfc1 */, Mips::DMFC1, Convert__GPR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_FGR64AsmReg }, },
    5363             :   { 3234 /* dmfc1 */, Mips::DMFC1_MM64R6, Convert__GPR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_FGR64AsmReg }, },
    5364             :   { 3240 /* dmfc2 */, Mips::DMFC2_MM64R6, Convert__GPR64AsmReg1_0__COP2AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_COP2AsmReg }, },
    5365             :   { 3240 /* dmfc2 */, Mips::DMFC2, Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0, 0, { MCK_GPR64AsmReg, MCK_COP2AsmReg }, },
    5366             :   { 3240 /* dmfc2 */, Mips::DMFC2_OCTEON, Convert__GPR64AsmReg1_0__UImm161_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_UImm16 }, },
    5367             :   { 3240 /* dmfc2 */, Mips::DMFC2, Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, Feature_HasMips64, { MCK_GPR64AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, },
    5368             :   { 3246 /* dmod */, Mips::DMOD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5369             :   { 3246 /* dmod */, Mips::DMOD_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5370             :   { 3251 /* dmodu */, Mips::DMODU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5371             :   { 3251 /* dmodu */, Mips::DMODU_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5372             :   { 3257 /* dmt */, Mips::DMT, Convert__regZERO, Feature_HasMT|Feature_NotInMicroMips, {  }, },
    5373             :   { 3257 /* dmt */, Mips::DMT, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
    5374             :   { 3261 /* dmtc0 */, Mips::DMTC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0, Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
    5375             :   { 3261 /* dmtc0 */, Mips::DMTC0_MM64R6, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0, 0, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
    5376             :   { 3261 /* dmtc0 */, Mips::DMTC0_MM64R6, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
    5377             :   { 3261 /* dmtc0 */, Mips::DMTC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, Feature_HasMips64, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
    5378             :   { 3267 /* dmtc1 */, Mips::DMTC1, Convert__FGR64AsmReg1_1__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_FGR64AsmReg }, },
    5379             :   { 3267 /* dmtc1 */, Mips::DMTC1_MM64R6, Convert__FGR64AsmReg1_1__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_FGR64AsmReg }, },
    5380             :   { 3273 /* dmtc2 */, Mips::DMTC2_MM64R6, Convert__COP2AsmReg1_1__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_COP2AsmReg }, },
    5381             :   { 3273 /* dmtc2 */, Mips::DMTC2, Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0, 0, { MCK_GPR64AsmReg, MCK_COP2AsmReg }, },
    5382             :   { 3273 /* dmtc2 */, Mips::DMTC2_OCTEON, Convert__GPR64AsmReg1_0__UImm161_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_UImm16 }, },
    5383             :   { 3273 /* dmtc2 */, Mips::DMTC2, Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, Feature_HasMips64, { MCK_GPR64AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, },
    5384             :   { 3279 /* dmuh */, Mips::DMUH, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5385             :   { 3279 /* dmuh */, Mips::DMUH_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5386             :   { 3284 /* dmuhu */, Mips::DMUHU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5387             :   { 3284 /* dmuhu */, Mips::DMUHU_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5388             :   { 3290 /* dmul */, Mips::DMUL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5389             :   { 3290 /* dmul */, Mips::DMULMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasMips3|Feature_NotMips64r6|Feature_NotCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5390             :   { 3290 /* dmul */, Mips::DMUL_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5391             :   { 3290 /* dmul */, Mips::DMUL_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5392             :   { 3290 /* dmul */, Mips::DMUL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5393             :   { 3290 /* dmul */, Mips::DMULImmMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
    5394             :   { 3295 /* dmulo */, Mips::DMULOMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5395             :   { 3301 /* dmulou */, Mips::DMULOUMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5396             :   { 3308 /* dmult */, Mips::DMULT, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5397             :   { 3314 /* dmultu */, Mips::DMULTu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5398             :   { 3321 /* dmulu */, Mips::DMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5399             :   { 3321 /* dmulu */, Mips::DMULU_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5400             :   { 3327 /* dneg */, Mips::DSUB, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0, Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg }, },
    5401             :   { 3327 /* dneg */, Mips::DSUB_MM64R6, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0, Feature_HasMicroMips64r6, { MCK_GPR64AsmReg }, },
    5402             :   { 3327 /* dneg */, Mips::DSUB, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1, Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5403             :   { 3327 /* dneg */, Mips::DSUB_MM64R6, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1, Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5404             :   { 3332 /* dnegu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0, Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg }, },
    5405             :   { 3332 /* dnegu */, Mips::DSUBU_MM64R6, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0, Feature_HasMicroMips64r6, { MCK_GPR64AsmReg }, },
    5406             :   { 3332 /* dnegu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1, Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5407             :   { 3332 /* dnegu */, Mips::DSUBU_MM64R6, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1, Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5408             :   { 3338 /* dotp_s.d */, Mips::DOTP_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5409             :   { 3347 /* dotp_s.h */, Mips::DOTP_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5410             :   { 3356 /* dotp_s.w */, Mips::DOTP_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5411             :   { 3365 /* dotp_u.d */, Mips::DOTP_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5412             :   { 3374 /* dotp_u.h */, Mips::DOTP_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5413             :   { 3383 /* dotp_u.w */, Mips::DOTP_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5414             :   { 3392 /* dpa.w.ph */, Mips::DPA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5415             :   { 3392 /* dpa.w.ph */, Mips::DPA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5416             :   { 3401 /* dpadd_s.d */, Mips::DPADD_S_D, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5417             :   { 3411 /* dpadd_s.h */, Mips::DPADD_S_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5418             :   { 3421 /* dpadd_s.w */, Mips::DPADD_S_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5419             :   { 3431 /* dpadd_u.d */, Mips::DPADD_U_D, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5420             :   { 3441 /* dpadd_u.h */, Mips::DPADD_U_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5421             :   { 3451 /* dpadd_u.w */, Mips::DPADD_U_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5422             :   { 3461 /* dpaq_s.w.ph */, Mips::DPAQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5423             :   { 3461 /* dpaq_s.w.ph */, Mips::DPAQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5424             :   { 3473 /* dpaq_sa.l.w */, Mips::DPAQ_SA_L_W_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5425             :   { 3473 /* dpaq_sa.l.w */, Mips::DPAQ_SA_L_W, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5426             :   { 3485 /* dpaqx_s.w.ph */, Mips::DPAQX_S_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5427             :   { 3485 /* dpaqx_s.w.ph */, Mips::DPAQX_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5428             :   { 3498 /* dpaqx_sa.w.ph */, Mips::DPAQX_SA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5429             :   { 3498 /* dpaqx_sa.w.ph */, Mips::DPAQX_SA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5430             :   { 3512 /* dpau.h.qbl */, Mips::DPAU_H_QBL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5431             :   { 3512 /* dpau.h.qbl */, Mips::DPAU_H_QBL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5432             :   { 3523 /* dpau.h.qbr */, Mips::DPAU_H_QBR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5433             :   { 3523 /* dpau.h.qbr */, Mips::DPAU_H_QBR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5434             :   { 3534 /* dpax.w.ph */, Mips::DPAX_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5435             :   { 3534 /* dpax.w.ph */, Mips::DPAX_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5436             :   { 3544 /* dpop */, Mips::DPOP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
    5437             :   { 3544 /* dpop */, Mips::DPOP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5438             :   { 3549 /* dps.w.ph */, Mips::DPS_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5439             :   { 3549 /* dps.w.ph */, Mips::DPS_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5440             :   { 3558 /* dpsq_s.w.ph */, Mips::DPSQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5441             :   { 3558 /* dpsq_s.w.ph */, Mips::DPSQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5442             :   { 3570 /* dpsq_sa.l.w */, Mips::DPSQ_SA_L_W_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5443             :   { 3570 /* dpsq_sa.l.w */, Mips::DPSQ_SA_L_W, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5444             :   { 3582 /* dpsqx_s.w.ph */, Mips::DPSQX_S_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5445             :   { 3582 /* dpsqx_s.w.ph */, Mips::DPSQX_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5446             :   { 3595 /* dpsqx_sa.w.ph */, Mips::DPSQX_SA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5447             :   { 3595 /* dpsqx_sa.w.ph */, Mips::DPSQX_SA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5448             :   { 3609 /* dpsu.h.qbl */, Mips::DPSU_H_QBL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5449             :   { 3609 /* dpsu.h.qbl */, Mips::DPSU_H_QBL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5450             :   { 3620 /* dpsu.h.qbr */, Mips::DPSU_H_QBR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5451             :   { 3620 /* dpsu.h.qbr */, Mips::DPSU_H_QBR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5452             :   { 3631 /* dpsub_s.d */, Mips::DPSUB_S_D, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5453             :   { 3641 /* dpsub_s.h */, Mips::DPSUB_S_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5454             :   { 3651 /* dpsub_s.w */, Mips::DPSUB_S_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5455             :   { 3661 /* dpsub_u.d */, Mips::DPSUB_U_D, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5456             :   { 3671 /* dpsub_u.h */, Mips::DPSUB_U_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5457             :   { 3681 /* dpsub_u.w */, Mips::DPSUB_U_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5458             :   { 3691 /* dpsx.w.ph */, Mips::DPSX_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5459             :   { 3691 /* dpsx.w.ph */, Mips::DPSX_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5460             :   { 3701 /* drol */, Mips::DROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5461             :   { 3701 /* drol */, Mips::DROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, Feature_HasMips64, { MCK_GPR32AsmReg, MCK_SImm16 }, },
    5462             :   { 3701 /* drol */, Mips::DROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5463             :   { 3701 /* drol */, Mips::DROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
    5464             :   { 3706 /* dror */, Mips::DROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5465             :   { 3706 /* dror */, Mips::DRORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, Feature_HasMips64, { MCK_GPR32AsmReg, MCK_SImm16 }, },
    5466             :   { 3706 /* dror */, Mips::DROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5467             :   { 3706 /* dror */, Mips::DRORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
    5468             :   { 3711 /* drotr */, Mips::DROTR, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
    5469             :   { 3711 /* drotr */, Mips::DROTR_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
    5470             :   { 3711 /* drotr */, Mips::DROTR, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
    5471             :   { 3711 /* drotr */, Mips::DROTR_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
    5472             :   { 3717 /* drotr32 */, Mips::DROTR32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
    5473             :   { 3717 /* drotr32 */, Mips::DROTR32_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
    5474             :   { 3717 /* drotr32 */, Mips::DROTR32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
    5475             :   { 3717 /* drotr32 */, Mips::DROTR32_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
    5476             :   { 3725 /* drotrv */, Mips::DROTRV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
    5477             :   { 3725 /* drotrv */, Mips::DROTRV_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
    5478             :   { 3732 /* dsbh */, Mips::DSBH, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5479             :   { 3732 /* dsbh */, Mips::DSBH_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5480             :   { 3737 /* dshd */, Mips::DSHD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5481             :   { 3737 /* dshd */, Mips::DSHD_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5482             :   { 3742 /* dsll */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
    5483             :   { 3742 /* dsll */, Mips::DSLLV_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
    5484             :   { 3742 /* dsll */, Mips::DSLL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
    5485             :   { 3742 /* dsll */, Mips::DSLL_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
    5486             :   { 3742 /* dsll */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
    5487             :   { 3742 /* dsll */, Mips::DSLLV_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
    5488             :   { 3742 /* dsll */, Mips::DSLL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
    5489             :   { 3742 /* dsll */, Mips::DSLL_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
    5490             :   { 3747 /* dsll32 */, Mips::DSLL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
    5491             :   { 3747 /* dsll32 */, Mips::DSLL32_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
    5492             :   { 3747 /* dsll32 */, Mips::DSLL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
    5493             :   { 3747 /* dsll32 */, Mips::DSLL32_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
    5494             :   { 3754 /* dsllv */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
    5495             :   { 3754 /* dsllv */, Mips::DSLLV_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
    5496             :   { 3760 /* dsra */, Mips::DSRA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
    5497             :   { 3760 /* dsra */, Mips::DSRA_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
    5498             :   { 3760 /* dsra */, Mips::DSRAV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
    5499             :   { 3760 /* dsra */, Mips::DSRA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
    5500             :   { 3760 /* dsra */, Mips::DSRA_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
    5501             :   { 3765 /* dsra32 */, Mips::DSRA32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
    5502             :   { 3765 /* dsra32 */, Mips::DSRA32_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
    5503             :   { 3765 /* dsra32 */, Mips::DSRA32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
    5504             :   { 3765 /* dsra32 */, Mips::DSRA32_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
    5505             :   { 3772 /* dsrav */, Mips::DSRAV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
    5506             :   { 3772 /* dsrav */, Mips::DSRAV_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
    5507             :   { 3778 /* dsrl */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
    5508             :   { 3778 /* dsrl */, Mips::DSRLV_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
    5509             :   { 3778 /* dsrl */, Mips::DSRL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
    5510             :   { 3778 /* dsrl */, Mips::DSRL_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
    5511             :   { 3778 /* dsrl */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
    5512             :   { 3778 /* dsrl */, Mips::DSRLV_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
    5513             :   { 3778 /* dsrl */, Mips::DSRL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
    5514             :   { 3778 /* dsrl */, Mips::DSRL_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
    5515             :   { 3783 /* dsrl32 */, Mips::DSRL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
    5516             :   { 3783 /* dsrl32 */, Mips::DSRL32_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
    5517             :   { 3783 /* dsrl32 */, Mips::DSRL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
    5518             :   { 3783 /* dsrl32 */, Mips::DSRL32_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
    5519             :   { 3790 /* dsrlv */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
    5520             :   { 3790 /* dsrlv */, Mips::DSRLV_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
    5521             :   { 3796 /* dsub */, Mips::DSUB, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5522             :   { 3796 /* dsub */, Mips::DSUB_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5523             :   { 3796 /* dsub */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_InvNum }, },
    5524             :   { 3796 /* dsub */, Mips::DSUB, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5525             :   { 3796 /* dsub */, Mips::DSUB_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5526             :   { 3796 /* dsub */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, },
    5527             :   { 3801 /* dsubi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_InvNum }, },
    5528             :   { 3801 /* dsubi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, },
    5529             :   { 3807 /* dsubu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5530             :   { 3807 /* dsubu */, Mips::DSUBU_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5531             :   { 3807 /* dsubu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_InvNum }, },
    5532             :   { 3807 /* dsubu */, Mips::DADDIU_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_InvNum }, },
    5533             :   { 3807 /* dsubu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5534             :   { 3807 /* dsubu */, Mips::DSUBU_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5535             :   { 3807 /* dsubu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, },
    5536             :   { 3807 /* dsubu */, Mips::DADDIU_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, },
    5537             :   { 3813 /* dvp */, Mips::DVP, Convert__regZERO, Feature_HasMips32r6, {  }, },
    5538             :   { 3813 /* dvp */, Mips::DVP_MMR6, Convert__regZERO, Feature_HasMicroMips32r6, {  }, },
    5539             :   { 3813 /* dvp */, Mips::DVP, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
    5540             :   { 3813 /* dvp */, Mips::DVP_MMR6, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg }, },
    5541             :   { 3817 /* dvpe */, Mips::DVPE, Convert__regZERO, Feature_HasMT|Feature_NotInMicroMips, {  }, },
    5542             :   { 3817 /* dvpe */, Mips::DVPE, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
    5543             :   { 3822 /* ehb */, Mips::EHB_MMR6, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMicroMips32r6, {  }, },
    5544             :   { 3822 /* ehb */, Mips::EHB, Convert_NoOperands, Feature_HasStdEnc, {  }, },
    5545             :   { 3822 /* ehb */, Mips::EHB_MM, Convert_NoOperands, Feature_InMicroMips, {  }, },
    5546             :   { 3826 /* ei */, Mips::EI, Convert__regZERO, Feature_HasMips32r2|Feature_NotInMicroMips, {  }, },
    5547             :   { 3826 /* ei */, Mips::EI_MM, Convert__regZERO, Feature_InMicroMips, {  }, },
    5548             :   { 3826 /* ei */, Mips::EI_MMR6, Convert__regZERO, Feature_HasMicroMips32r6, {  }, },
    5549             :   { 3826 /* ei */, Mips::EI, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
    5550             :   { 3826 /* ei */, Mips::EI_MMR6, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg }, },
    5551             :   { 3826 /* ei */, Mips::EI_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
    5552             :   { 3829 /* emt */, Mips::EMT, Convert__regZERO, Feature_HasMT|Feature_NotInMicroMips, {  }, },
    5553             :   { 3829 /* emt */, Mips::EMT, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
    5554             :   { 3833 /* eret */, Mips::ERET, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotInMicroMips, {  }, },
    5555             :   { 3833 /* eret */, Mips::ERET_MMR6, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMicroMips32r6, {  }, },
    5556             :   { 3833 /* eret */, Mips::ERET_MM, Convert_NoOperands, Feature_InMicroMips, {  }, },
    5557             :   { 3838 /* eretnc */, Mips::ERETNC, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r5|Feature_NotInMicroMips, {  }, },
    5558             :   { 3838 /* eretnc */, Mips::ERETNC_MMR6, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMicroMips32r6, {  }, },
    5559             :   { 3845 /* evp */, Mips::EVP, Convert__regZERO, Feature_HasMips32r6, {  }, },
    5560             :   { 3845 /* evp */, Mips::EVP_MMR6, Convert__regZERO, Feature_HasMicroMips32r6, {  }, },
    5561             :   { 3845 /* evp */, Mips::EVP, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
    5562             :   { 3845 /* evp */, Mips::EVP_MMR6, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg }, },
    5563             :   { 3849 /* evpe */, Mips::EVPE, Convert__regZERO, Feature_HasMT|Feature_NotInMicroMips, {  }, },
    5564             :   { 3849 /* evpe */, Mips::EVPE, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
    5565             :   { 3854 /* ext */, Mips::EXT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
    5566             :   { 3854 /* ext */, Mips::EXT_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
    5567             :   { 3854 /* ext */, Mips::EXT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
    5568             :   { 3858 /* extp */, Mips::EXTP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
    5569             :   { 3858 /* extp */, Mips::EXTP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
    5570             :   { 3863 /* extpdp */, Mips::EXTPDP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
    5571             :   { 3863 /* extpdp */, Mips::EXTPDP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
    5572             :   { 3870 /* extpdpv */, Mips::EXTPDPV_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
    5573             :   { 3870 /* extpdpv */, Mips::EXTPDPV, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
    5574             :   { 3878 /* extpv */, Mips::EXTPV_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
    5575             :   { 3878 /* extpv */, Mips::EXTPV, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
    5576             :   { 3884 /* extr.w */, Mips::EXTR_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
    5577             :   { 3884 /* extr.w */, Mips::EXTR_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
    5578             :   { 3891 /* extr_r.w */, Mips::EXTR_R_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
    5579             :   { 3891 /* extr_r.w */, Mips::EXTR_R_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
    5580             :   { 3900 /* extr_rs.w */, Mips::EXTR_RS_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
    5581             :   { 3900 /* extr_rs.w */, Mips::EXTR_RS_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
    5582             :   { 3910 /* extr_s.h */, Mips::EXTR_S_H_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
    5583             :   { 3910 /* extr_s.h */, Mips::EXTR_S_H, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
    5584             :   { 3919 /* extrv.w */, Mips::EXTRV_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
    5585             :   { 3919 /* extrv.w */, Mips::EXTRV_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
    5586             :   { 3927 /* extrv_r.w */, Mips::EXTRV_R_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
    5587             :   { 3927 /* extrv_r.w */, Mips::EXTRV_R_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
    5588             :   { 3937 /* extrv_rs.w */, Mips::EXTRV_RS_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
    5589             :   { 3937 /* extrv_rs.w */, Mips::EXTRV_RS_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
    5590             :   { 3948 /* extrv_s.h */, Mips::EXTRV_S_H_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
    5591             :   { 3948 /* extrv_s.h */, Mips::EXTRV_S_H, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
    5592             :   { 3958 /* exts */, Mips::EXTS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
    5593             :   { 3958 /* exts */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2, Feature_HasMips64|Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
    5594             :   { 3958 /* exts */, Mips::EXTS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
    5595             :   { 3958 /* exts */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3, Feature_HasMips64|Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
    5596             :   { 3963 /* exts32 */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
    5597             :   { 3963 /* exts32 */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
    5598             :   { 3970 /* fadd.d */, Mips::FADD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5599             :   { 3977 /* fadd.w */, Mips::FADD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5600             :   { 3984 /* fcaf.d */, Mips::FCAF_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5601             :   { 3991 /* fcaf.w */, Mips::FCAF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5602             :   { 3998 /* fceq.d */, Mips::FCEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5603             :   { 4005 /* fceq.w */, Mips::FCEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5604             :   { 4012 /* fclass.d */, Mips::FCLASS_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5605             :   { 4021 /* fclass.w */, Mips::FCLASS_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5606             :   { 4030 /* fcle.d */, Mips::FCLE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5607             :   { 4037 /* fcle.w */, Mips::FCLE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5608             :   { 4044 /* fclt.d */, Mips::FCLT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5609             :   { 4051 /* fclt.w */, Mips::FCLT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5610             :   { 4058 /* fcne.d */, Mips::FCNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5611             :   { 4065 /* fcne.w */, Mips::FCNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5612             :   { 4072 /* fcor.d */, Mips::FCOR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5613             :   { 4079 /* fcor.w */, Mips::FCOR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5614             :   { 4086 /* fcueq.d */, Mips::FCUEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5615             :   { 4094 /* fcueq.w */, Mips::FCUEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5616             :   { 4102 /* fcule.d */, Mips::FCULE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5617             :   { 4110 /* fcule.w */, Mips::FCULE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5618             :   { 4118 /* fcult.d */, Mips::FCULT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5619             :   { 4126 /* fcult.w */, Mips::FCULT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5620             :   { 4134 /* fcun.d */, Mips::FCUN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5621             :   { 4141 /* fcun.w */, Mips::FCUN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5622             :   { 4148 /* fcune.d */, Mips::FCUNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5623             :   { 4156 /* fcune.w */, Mips::FCUNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5624             :   { 4164 /* fdiv.d */, Mips::FDIV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5625             :   { 4171 /* fdiv.w */, Mips::FDIV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5626             :   { 4178 /* fexdo.h */, Mips::FEXDO_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5627             :   { 4186 /* fexdo.w */, Mips::FEXDO_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5628             :   { 4194 /* fexp2.d */, Mips::FEXP2_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5629             :   { 4202 /* fexp2.w */, Mips::FEXP2_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5630             :   { 4210 /* fexupl.d */, Mips::FEXUPL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5631             :   { 4219 /* fexupl.w */, Mips::FEXUPL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5632             :   { 4228 /* fexupr.d */, Mips::FEXUPR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5633             :   { 4237 /* fexupr.w */, Mips::FEXUPR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5634             :   { 4246 /* ffint_s.d */, Mips::FFINT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5635             :   { 4256 /* ffint_s.w */, Mips::FFINT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5636             :   { 4266 /* ffint_u.d */, Mips::FFINT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5637             :   { 4276 /* ffint_u.w */, Mips::FFINT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5638             :   { 4286 /* ffql.d */, Mips::FFQL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5639             :   { 4293 /* ffql.w */, Mips::FFQL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5640             :   { 4300 /* ffqr.d */, Mips::FFQR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5641             :   { 4307 /* ffqr.w */, Mips::FFQR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5642             :   { 4314 /* fill.b */, Mips::FILL_B, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, },
    5643             :   { 4321 /* fill.d */, Mips::FILL_D, Convert__MSA128AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, { MCK_MSA128AsmReg, MCK_GPR64AsmReg }, },
    5644             :   { 4328 /* fill.h */, Mips::FILL_H, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, },
    5645             :   { 4335 /* fill.w */, Mips::FILL_W, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, },
    5646             :   { 4342 /* flog2.d */, Mips::FLOG2_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5647             :   { 4350 /* flog2.w */, Mips::FLOG2_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5648             :   { 4358 /* floor.l.d */, Mips::FLOOR_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5649             :   { 4358 /* floor.l.d */, Mips::FLOOR_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5650             :   { 4368 /* floor.l.s */, Mips::FLOOR_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
    5651             :   { 4368 /* floor.l.s */, Mips::FLOOR_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
    5652             :   { 4378 /* floor.w.d */, Mips::FLOOR_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
    5653             :   { 4378 /* floor.w.d */, Mips::FLOOR_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
    5654             :   { 4378 /* floor.w.d */, Mips::FLOOR_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
    5655             :   { 4388 /* floor.w.s */, Mips::FLOOR_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5656             :   { 4388 /* floor.w.s */, Mips::FLOOR_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5657             :   { 4388 /* floor.w.s */, Mips::FLOOR_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5658             :   { 4398 /* fmadd.d */, Mips::FMADD_D, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5659             :   { 4406 /* fmadd.w */, Mips::FMADD_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5660             :   { 4414 /* fmax.d */, Mips::FMAX_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5661             :   { 4421 /* fmax.w */, Mips::FMAX_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5662             :   { 4428 /* fmax_a.d */, Mips::FMAX_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5663             :   { 4437 /* fmax_a.w */, Mips::FMAX_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5664             :   { 4446 /* fmin.d */, Mips::FMIN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5665             :   { 4453 /* fmin.w */, Mips::FMIN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5666             :   { 4460 /* fmin_a.d */, Mips::FMIN_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5667             :   { 4469 /* fmin_a.w */, Mips::FMIN_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5668             :   { 4478 /* fmsub.d */, Mips::FMSUB_D, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5669             :   { 4486 /* fmsub.w */, Mips::FMSUB_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5670             :   { 4494 /* fmul.d */, Mips::FMUL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5671             :   { 4501 /* fmul.w */, Mips::FMUL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5672             :   { 4508 /* fork */, Mips::FORK, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5673             :   { 4513 /* frcp.d */, Mips::FRCP_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5674             :   { 4520 /* frcp.w */, Mips::FRCP_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5675             :   { 4527 /* frint.d */, Mips::FRINT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5676             :   { 4535 /* frint.w */, Mips::FRINT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5677             :   { 4543 /* frsqrt.d */, Mips::FRSQRT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5678             :   { 4552 /* frsqrt.w */, Mips::FRSQRT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5679             :   { 4561 /* fsaf.d */, Mips::FSAF_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5680             :   { 4568 /* fsaf.w */, Mips::FSAF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5681             :   { 4575 /* fseq.d */, Mips::FSEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5682             :   { 4582 /* fseq.w */, Mips::FSEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5683             :   { 4589 /* fsle.d */, Mips::FSLE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5684             :   { 4596 /* fsle.w */, Mips::FSLE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5685             :   { 4603 /* fslt.d */, Mips::FSLT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5686             :   { 4610 /* fslt.w */, Mips::FSLT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5687             :   { 4617 /* fsne.d */, Mips::FSNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5688             :   { 4624 /* fsne.w */, Mips::FSNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5689             :   { 4631 /* fsor.d */, Mips::FSOR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5690             :   { 4638 /* fsor.w */, Mips::FSOR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5691             :   { 4645 /* fsqrt.d */, Mips::FSQRT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5692             :   { 4653 /* fsqrt.w */, Mips::FSQRT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5693             :   { 4661 /* fsub.d */, Mips::FSUB_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5694             :   { 4668 /* fsub.w */, Mips::FSUB_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5695             :   { 4675 /* fsueq.d */, Mips::FSUEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5696             :   { 4683 /* fsueq.w */, Mips::FSUEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5697             :   { 4691 /* fsule.d */, Mips::FSULE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5698             :   { 4699 /* fsule.w */, Mips::FSULE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5699             :   { 4707 /* fsult.d */, Mips::FSULT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5700             :   { 4715 /* fsult.w */, Mips::FSULT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5701             :   { 4723 /* fsun.d */, Mips::FSUN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5702             :   { 4730 /* fsun.w */, Mips::FSUN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5703             :   { 4737 /* fsune.d */, Mips::FSUNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5704             :   { 4745 /* fsune.w */, Mips::FSUNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5705             :   { 4753 /* ftint_s.d */, Mips::FTINT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5706             :   { 4763 /* ftint_s.w */, Mips::FTINT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5707             :   { 4773 /* ftint_u.d */, Mips::FTINT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5708             :   { 4783 /* ftint_u.w */, Mips::FTINT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5709             :   { 4793 /* ftq.h */, Mips::FTQ_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5710             :   { 4799 /* ftq.w */, Mips::FTQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5711             :   { 4805 /* ftrunc_s.d */, Mips::FTRUNC_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5712             :   { 4816 /* ftrunc_s.w */, Mips::FTRUNC_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5713             :   { 4827 /* ftrunc_u.d */, Mips::FTRUNC_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5714             :   { 4838 /* ftrunc_u.w */, Mips::FTRUNC_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5715             :   { 4849 /* hadd_s.d */, Mips::HADD_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5716             :   { 4858 /* hadd_s.h */, Mips::HADD_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5717             :   { 4867 /* hadd_s.w */, Mips::HADD_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5718             :   { 4876 /* hadd_u.d */, Mips::HADD_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5719             :   { 4885 /* hadd_u.h */, Mips::HADD_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5720             :   { 4894 /* hadd_u.w */, Mips::HADD_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5721             :   { 4903 /* hsub_s.d */, Mips::HSUB_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5722             :   { 4912 /* hsub_s.h */, Mips::HSUB_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5723             :   { 4921 /* hsub_s.w */, Mips::HSUB_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5724             :   { 4930 /* hsub_u.d */, Mips::HSUB_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5725             :   { 4939 /* hsub_u.h */, Mips::HSUB_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5726             :   { 4948 /* hsub_u.w */, Mips::HSUB_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5727             :   { 4957 /* ilvev.b */, Mips::ILVEV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5728             :   { 4965 /* ilvev.d */, Mips::ILVEV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5729             :   { 4973 /* ilvev.h */, Mips::ILVEV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5730             :   { 4981 /* ilvev.w */, Mips::ILVEV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5731             :   { 4989 /* ilvl.b */, Mips::ILVL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5732             :   { 4996 /* ilvl.d */, Mips::ILVL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5733             :   { 5003 /* ilvl.h */, Mips::ILVL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5734             :   { 5010 /* ilvl.w */, Mips::ILVL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5735             :   { 5017 /* ilvod.b */, Mips::ILVOD_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5736             :   { 5025 /* ilvod.d */, Mips::ILVOD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5737             :   { 5033 /* ilvod.h */, Mips::ILVOD_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5738             :   { 5041 /* ilvod.w */, Mips::ILVOD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5739             :   { 5049 /* ilvr.b */, Mips::ILVR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5740             :   { 5056 /* ilvr.d */, Mips::ILVR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5741             :   { 5063 /* ilvr.h */, Mips::ILVR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5742             :   { 5070 /* ilvr.w */, Mips::ILVR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5743             :   { 5077 /* ins */, Mips::INS, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
    5744             :   { 5077 /* ins */, Mips::INS_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
    5745             :   { 5077 /* ins */, Mips::INS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
    5746             :   { 5081 /* insert.b */, Mips::INSERT_B, Convert__MSA128AsmReg1_0__Tie0__GPR32AsmReg1_4__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_, MCK_GPR32AsmReg }, },
    5747             :   { 5090 /* insert.d */, Mips::INSERT_D, Convert__MSA128AsmReg1_0__Tie0__GPR64AsmReg1_4__ConstantUImm1_01_2, Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_, MCK_GPR64AsmReg }, },
    5748             :   { 5099 /* insert.h */, Mips::INSERT_H, Convert__MSA128AsmReg1_0__Tie0__GPR32AsmReg1_4__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_, MCK_GPR32AsmReg }, },
    5749             :   { 5108 /* insert.w */, Mips::INSERT_W, Convert__MSA128AsmReg1_0__Tie0__GPR32AsmReg1_4__ConstantUImm2_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_, MCK_GPR32AsmReg }, },
    5750             :   { 5117 /* insv */, Mips::INSV_MM, Convert__GPR32AsmReg1_0__Tie0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5751             :   { 5117 /* insv */, Mips::INSV, Convert__GPR32AsmReg1_0__Tie0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5752             :   { 5122 /* insve.b */, Mips::INSVE_B, Convert__MSA128AsmReg1_0__Tie0__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
    5753             :   { 5130 /* insve.d */, Mips::INSVE_D, Convert__MSA128AsmReg1_0__Tie0__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
    5754             :   { 5138 /* insve.h */, Mips::INSVE_H, Convert__MSA128AsmReg1_0__Tie0__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
    5755             :   { 5146 /* insve.w */, Mips::INSVE_W, Convert__MSA128AsmReg1_0__Tie0__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
    5756             :   { 5154 /* j */, Mips::JR, Convert__GPR32AsmReg1_0, 0, { MCK_GPR32AsmReg }, },
    5757             :   { 5154 /* j */, Mips::J_MM, Convert__Imm1_0, Feature_InMicroMips, { MCK_Imm }, },
    5758             :   { 5154 /* j */, Mips::J, Convert__JumpTarget1_0, Feature_HasStdEnc, { MCK_JumpTarget }, },
    5759             :   { 5156 /* jal */, Mips::JalOneReg, Convert__GPR32AsmReg1_0, 0, { MCK_GPR32AsmReg }, },
    5760             :   { 5156 /* jal */, Mips::JAL_MM, Convert__Imm1_0, Feature_InMicroMips, { MCK_Imm }, },
    5761             :   { 5156 /* jal */, Mips::JAL, Convert__JumpTarget1_0, Feature_HasStdEnc, { MCK_JumpTarget }, },
    5762             :   { 5156 /* jal */, Mips::JalTwoReg, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5763             :   { 5160 /* jalr */, Mips::JALR16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
    5764             :   { 5160 /* jalr */, Mips::JALRC16_MMR6, Convert__GPR32AsmReg1_0, Feature_HasMicroMips32r6, { MCK_GPR32AsmReg }, },
    5765             :   { 5160 /* jalr */, Mips::JALR, Convert__regRA__GPR32AsmReg1_0, Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
    5766             :   { 5160 /* jalr */, Mips::JALR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5767             :   { 5160 /* jalr */, Mips::JALR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5768             :   { 5160 /* jalr */, Mips::JALR64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    5769             :   { 5165 /* jalr.hb */, Mips::JALR_HB, Convert__regRA__GPR32AsmReg1_0, Feature_HasMips32, { MCK_GPR32AsmReg }, },
    5770             :   { 5165 /* jalr.hb */, Mips::JALR_HB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5771             :   { 5173 /* jalrc */, Mips::JumpLinkReg16, Convert__Reg1_0, Feature_InMips16Mode, { MCK_CPU16Regs }, },
    5772             :   { 5173 /* jalrc */, Mips::JIALC, Convert__GPR32AsmReg1_0__imm_95_0, Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
    5773             :   { 5173 /* jalrc */, Mips::JALRC_MMR6, Convert__regRA__GPR32AsmReg1_0, Feature_HasMicroMips32r6, { MCK_GPR32AsmReg }, },
    5774             :   { 5173 /* jalrc */, Mips::JIALC64, Convert__GPR64AsmReg1_0__imm_95_0, Feature_HasMips64r6, { MCK_GPR64AsmReg }, },
    5775             :   { 5173 /* jalrc */, Mips::JALRC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5776             :   { 5179 /* jalrc.hb */, Mips::JALRC_HB_MMR6, Convert__regRA__GPR32AsmReg1_0, Feature_HasMicroMips32r6, { MCK_GPR32AsmReg }, },
    5777             :   { 5179 /* jalrc.hb */, Mips::JALRC_HB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5778             :   { 5188 /* jalrs */, Mips::JALRS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5779             :   { 5194 /* jalrs16 */, Mips::JALRS16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
    5780             :   { 5202 /* jals */, Mips::JALS_MM, Convert__Imm1_0, Feature_InMicroMips, { MCK_Imm }, },
    5781             :   { 5207 /* jalx */, Mips::JALX, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_JumpTarget }, },
    5782             :   { 5207 /* jalx */, Mips::JALX_MM, Convert__JumpTarget1_0, Feature_InMicroMips, { MCK_JumpTarget }, },
    5783             :   { 5212 /* jialc */, Mips::JIALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    5784             :   { 5212 /* jialc */, Mips::JIALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    5785             :   { 5212 /* jialc */, Mips::JIALC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
    5786             :   { 5218 /* jic */, Mips::JIC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    5787             :   { 5218 /* jic */, Mips::JIC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
    5788             :   { 5218 /* jic */, Mips::JIC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
    5789             :   { 5222 /* jr */, Mips::JrRa16, Convert_NoOperands, Feature_InMips16Mode, { MCK_CPURAReg }, },
    5790             :   { 5222 /* jr */, Mips::JR, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg }, },
    5791             :   { 5222 /* jr */, Mips::JALR, Convert__regZERO__GPR32AsmReg1_0, Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
    5792             :   { 5222 /* jr */, Mips::JR_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
    5793             :   { 5222 /* jr */, Mips::JR64, Convert__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_IsPTR64bit|Feature_NotInMicroMips, { MCK_GPR64AsmReg }, },
    5794             :   { 5222 /* jr */, Mips::JALR64, Convert__regZERO_64__GPR64AsmReg1_0, Feature_HasMips64r6, { MCK_GPR64AsmReg }, },
    5795             :   { 5225 /* jr.hb */, Mips::JR_HB, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg }, },
    5796             :   { 5225 /* jr.hb */, Mips::JR_HB_R6, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
    5797             :   { 5231 /* jr16 */, Mips::JR16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
    5798             :   { 5236 /* jraddiusp */, Mips::JRADDIUSP, Convert__UImm5Lsl21_0, Feature_InMicroMips, { MCK_UImm5Lsl2 }, },
    5799             :   { 5246 /* jrc */, Mips::JrcRa16, Convert_NoOperands, Feature_InMips16Mode, { MCK_CPURAReg }, },
    5800             :   { 5246 /* jrc */, Mips::JrcRx16, Convert__Reg1_0, Feature_InMips16Mode, { MCK_CPU16Regs }, },
    5801             :   { 5246 /* jrc */, Mips::JIC, Convert__GPR32AsmReg1_0__imm_95_0, Feature_IsGP32bit|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
    5802             :   { 5246 /* jrc */, Mips::JRC16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
    5803             :   { 5246 /* jrc */, Mips::JIC64, Convert__GPR64AsmReg1_0__imm_95_0, Feature_HasMips64r6, { MCK_GPR64AsmReg }, },
    5804             :   { 5250 /* jrc16 */, Mips::JRC16_MMR6, Convert__GPR32AsmReg1_0, Feature_HasMicroMips32r6, { MCK_GPR32AsmReg }, },
    5805             :   { 5256 /* jrcaddiusp */, Mips::JRCADDIUSP_MMR6, Convert__UImm5Lsl21_0, Feature_HasMicroMips32r6, { MCK_UImm5Lsl2 }, },
    5806             :   { 5267 /* l.d */, Mips::LDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, },
    5807             :   { 5267 /* l.d */, Mips::LDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, },
    5808             :   { 5271 /* l.s */, Mips::LWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, },
    5809             :   { 5275 /* la */, Mips::LoadAddrImm32, Convert__GPR32AsmReg1_0__Imm1_1, 0, { MCK_GPR32AsmReg, MCK_Imm }, },
    5810             :   { 5275 /* la */, Mips::LoadAddrReg32, Convert__GPR32AsmReg1_0__Mem2_1, 0, { MCK_GPR32AsmReg, MCK_Mem }, },
    5811             :   { 5278 /* lapc */, Mips::ADDIUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
    5812             :   { 5278 /* lapc */, Mips::ADDIUPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
    5813             :   { 5283 /* lb */, Mips::LB_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
    5814             :   { 5283 /* lb */, Mips::LB, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
    5815             :   { 5283 /* lb */, Mips::LB_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
    5816             :   { 5286 /* lbe */, Mips::LBE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    5817             :   { 5286 /* lbe */, Mips::LBE_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    5818             :   { 5286 /* lbe */, Mips::LBE_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
    5819             :   { 5290 /* lbu */, Mips::LBU_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
    5820             :   { 5290 /* lbu */, Mips::LBu, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
    5821             :   { 5290 /* lbu */, Mips::LBu_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
    5822             :   { 5294 /* lbu16 */, Mips::LBU16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, },
    5823             :   { 5300 /* lbue */, Mips::LBUE_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    5824             :   { 5300 /* lbue */, Mips::LBuE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    5825             :   { 5300 /* lbue */, Mips::LBuE_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
    5826             :   { 5305 /* lbux */, Mips::LBUX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
    5827             :   { 5305 /* lbux */, Mips::LBUX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
    5828             :   { 5310 /* ld */, Mips::LDMacro, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_NotMips3, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
    5829             :   { 5310 /* ld */, Mips::LD, Convert__GPR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimm16 }, },
    5830             :   { 5310 /* ld */, Mips::LD_MM64R6, Convert__GPR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_MemOffsetSimm16 }, },
    5831             :   { 5313 /* ld.b */, Mips::LD_B, Convert__MSA128AsmReg1_0__MemOffsetSimm102_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10 }, },
    5832             :   { 5318 /* ld.d */, Mips::LD_D, Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_3 }, },
    5833             :   { 5323 /* ld.h */, Mips::LD_H, Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_1 }, },
    5834             :   { 5328 /* ld.w */, Mips::LD_W, Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_2 }, },
    5835             :   { 5333 /* ldc1 */, Mips::LDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, },
    5836             :   { 5333 /* ldc1 */, Mips::LDC1_MM, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, },
    5837             :   { 5333 /* ldc1 */, Mips::LDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, },
    5838             :   { 5333 /* ldc1 */, Mips::LDC1_D64_MMR6, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, },
    5839             :   { 5338 /* ldc2 */, Mips::LDC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
    5840             :   { 5338 /* ldc2 */, Mips::LDC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
    5841             :   { 5338 /* ldc2 */, Mips::LDC2, Convert__COP2AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16 }, },
    5842             :   { 5343 /* ldc3 */, Mips::LDC3, Convert__COP3AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
    5843             :   { 5348 /* ldi.b */, Mips::LDI_B, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, },
    5844             :   { 5354 /* ldi.d */, Mips::LDI_D, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, },
    5845             :   { 5360 /* ldi.h */, Mips::LDI_H, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, },
    5846             :   { 5366 /* ldi.w */, Mips::LDI_W, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, },
    5847             :   { 5372 /* ldl */, Mips::LDL, Convert__GPR64AsmReg1_0__Mem2_1__Tie0, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
    5848             :   { 5376 /* ldpc */, Mips::LDPC, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
    5849             :   { 5376 /* ldpc */, Mips::LDPC_MM64R6, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
    5850             :   { 5381 /* ldr */, Mips::LDR, Convert__GPR64AsmReg1_0__Mem2_1__Tie0, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
    5851             :   { 5385 /* ldxc1 */, Mips::LDXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
    5852             :   { 5385 /* ldxc1 */, Mips::LDXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
    5853             :   { 5391 /* lh */, Mips::LH, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
    5854             :   { 5391 /* lh */, Mips::LH_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
    5855             :   { 5394 /* lhe */, Mips::LHE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    5856             :   { 5394 /* lhe */, Mips::LHE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    5857             :   { 5398 /* lhu */, Mips::LHu, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
    5858             :   { 5398 /* lhu */, Mips::LHu_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
    5859             :   { 5402 /* lhu16 */, Mips::LHU16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, },
    5860             :   { 5408 /* lhue */, Mips::LHuE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    5861             :   { 5408 /* lhue */, Mips::LHuE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    5862             :   { 5413 /* lhx */, Mips::LHX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
    5863             :   { 5413 /* lhx */, Mips::LHX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
    5864             :   { 5417 /* li */, Mips::LiRxImmX16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
    5865             :   { 5417 /* li */, Mips::LoadImm32, Convert__GPR32AsmReg1_0__UImm32_Coerced1_1, 0, { MCK_GPR32AsmReg, MCK_UImm32_Coerced }, },
    5866             :   { 5417 /* li */, Mips::LiRxImm16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
    5867             :   { 5420 /* li.d */, Mips::LoadImmDoubleGPR, Convert__GPR32AsmReg1_0__Imm1_1, 0, { MCK_GPR32AsmReg, MCK_Imm }, },
    5868             :   { 5420 /* li.d */, Mips::LoadImmDoubleFGR_32, Convert__StrictlyAFGR64AsmReg1_0__Imm1_1, Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_StrictlyAFGR64AsmReg, MCK_Imm }, },
    5869             :   { 5420 /* li.d */, Mips::LoadImmDoubleFGR, Convert__StrictlyFGR64AsmReg1_0__Imm1_1, Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_StrictlyFGR64AsmReg, MCK_Imm }, },
    5870             :   { 5425 /* li.s */, Mips::LoadImmSingleGPR, Convert__GPR32AsmReg1_0__Imm1_1, 0, { MCK_GPR32AsmReg, MCK_Imm }, },
    5871             :   { 5425 /* li.s */, Mips::LoadImmSingleFGR, Convert__StrictlyFGR32AsmReg1_0__Imm1_1, Feature_IsNotSoftFloat, { MCK_StrictlyFGR32AsmReg, MCK_Imm }, },
    5872             :   { 5430 /* li16 */, Mips::LI16_MM, Convert__GPRMM16AsmReg1_0__UImm7_N11_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_UImm7_N1 }, },
    5873             :   { 5430 /* li16 */, Mips::LI16_MMR6, Convert__GPRMM16AsmReg1_0__UImm7_N11_1, Feature_HasMicroMips32r6, { MCK_GPRMM16AsmReg, MCK_UImm7_N1 }, },
    5874             :   { 5435 /* ll */, Mips::LL64_R6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    5875             :   { 5435 /* ll */, Mips::LL_R6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    5876             :   { 5435 /* ll */, Mips::LL, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
    5877             :   { 5435 /* ll */, Mips::LL64, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
    5878             :   { 5435 /* ll */, Mips::LL_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
    5879             :   { 5438 /* lld */, Mips::LLD_MM64R6, Convert__GPR64AsmReg1_0__MemOffsetSimm122_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_MemOffsetSimm12 }, },
    5880             :   { 5438 /* lld */, Mips::LLD, Convert__GPR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimm16 }, },
    5881             :   { 5438 /* lld */, Mips::LLD_R6, Convert__GPR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimm16 }, },
    5882             :   { 5442 /* lle */, Mips::LLE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    5883             :   { 5442 /* lle */, Mips::LLE_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    5884             :   { 5442 /* lle */, Mips::LLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    5885             :   { 5446 /* lsa */, Mips::LSA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, },
    5886             :   { 5446 /* lsa */, Mips::LSA_MMR6, Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, },
    5887             :   { 5446 /* lsa */, Mips::LSA_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, },
    5888             :   { 5450 /* lui */, Mips::LUI_MMR6, Convert__GPR32AsmReg1_0__UImm161_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
    5889             :   { 5450 /* lui */, Mips::LUi, Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_UImm16_Relaxed }, },
    5890             :   { 5450 /* lui */, Mips::LUi_MM, Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_UImm16_Relaxed }, },
    5891             :   { 5454 /* luxc1 */, Mips::LUXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
    5892             :   { 5454 /* luxc1 */, Mips::LUXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
    5893             :   { 5460 /* lw */, Mips::LwRxPcTcpX16, Convert__Reg1_0__Imm1_1__imm_95_0, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_Imm }, },
    5894             :   { 5460 /* lw */, Mips::LWSP_MM, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, },
    5895             :   { 5460 /* lw */, Mips::LW, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
    5896             :   { 5460 /* lw */, Mips::LW_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
    5897             :   { 5460 /* lw */, Mips::LW_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
    5898             :   { 5460 /* lw */, Mips::LWGP_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMemGP }, },
    5899             :   { 5460 /* lw */, Mips::LwRxSpImmX16, Convert__Reg1_0__Reg1_1__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, },
    5900             :   { 5460 /* lw */, Mips::LwRxPcTcp16, Convert__Reg1_0__Imm1_1__imm_95_0, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_Imm, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
    5901             :   { 5463 /* lw16 */, Mips::LW16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, },
    5902             :   { 5468 /* lwc1 */, Mips::LWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, },
    5903             :   { 5468 /* lwc1 */, Mips::LWC1_MM, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, },
    5904             :   { 5473 /* lwc2 */, Mips::LWC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
    5905             :   { 5473 /* lwc2 */, Mips::LWC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
    5906             :   { 5473 /* lwc2 */, Mips::LWC2, Convert__COP2AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16 }, },
    5907             :   { 5478 /* lwc3 */, Mips::LWC3, Convert__COP3AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
    5908             :   { 5483 /* lwe */, Mips::LWE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    5909             :   { 5483 /* lwe */, Mips::LWE_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    5910             :   { 5483 /* lwe */, Mips::LWE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    5911             :   { 5487 /* lwl */, Mips::LWL, Convert__GPR32AsmReg1_0__Mem2_1__Tie0, Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
    5912             :   { 5487 /* lwl */, Mips::LWL_MM, Convert__GPR32AsmReg1_0__Mem2_1__Tie0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
    5913             :   { 5491 /* lwle */, Mips::LWLE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    5914             :   { 5491 /* lwle */, Mips::LWLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    5915             :   { 5496 /* lwm */, Mips::LWM_MM, Convert__RegList1_0__Mem2_1, Feature_InMicroMips, { MCK_RegList, MCK_Mem }, },
    5916             :   { 5500 /* lwm16 */, Mips::LWM16_MM, Convert__RegList161_0__MemOffsetUimm42_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, },
    5917             :   { 5500 /* lwm16 */, Mips::LWM16_MMR6, Convert__RegList161_0__MemOffsetUimm42_1, Feature_HasMicroMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, },
    5918             :   { 5506 /* lwm32 */, Mips::LWM32_MM, Convert__RegList1_0__Mem2_1, Feature_InMicroMips, { MCK_RegList, MCK_Mem }, },
    5919             :   { 5512 /* lwp */, Mips::LWP_MMR6, Convert__RegPair2_0__MemOffsetSimm122_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_RegPair, MCK_MemOffsetSimm12 }, },
    5920             :   { 5512 /* lwp */, Mips::LWP_MM, Convert__RegPair2_0__MemOffsetSimm122_1, Feature_InMicroMips, { MCK_RegPair, MCK_MemOffsetSimm12 }, },
    5921             :   { 5516 /* lwpc */, Mips::LWPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
    5922             :   { 5516 /* lwpc */, Mips::LWPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
    5923             :   { 5521 /* lwr */, Mips::LWR, Convert__GPR32AsmReg1_0__Mem2_1__Tie0, Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
    5924             :   { 5521 /* lwr */, Mips::LWR_MM, Convert__GPR32AsmReg1_0__Mem2_1__Tie0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
    5925             :   { 5525 /* lwre */, Mips::LWRE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    5926             :   { 5525 /* lwre */, Mips::LWRE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    5927             :   { 5530 /* lwu */, Mips::LWU_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm122_1, Feature_HasStdEnc|Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm12 }, },
    5928             :   { 5530 /* lwu */, Mips::LWU_MM64R6, Convert__GPR64AsmReg1_0__MemOffsetSimm122_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_MemOffsetSimm12 }, },
    5929             :   { 5530 /* lwu */, Mips::LWu, Convert__GPR64AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Mem }, },
    5930             :   { 5534 /* lwupc */, Mips::LWUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
    5931             :   { 5534 /* lwupc */, Mips::LWUPC_MM64R6, Convert__GPR64AsmReg1_0__Simm19_Lsl21_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_Simm19_Lsl2 }, },
    5932             :   { 5540 /* lwx */, Mips::LWX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
    5933             :   { 5540 /* lwx */, Mips::LWX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
    5934             :   { 5544 /* lwxc1 */, Mips::LWXC1, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
    5935             :   { 5550 /* lwxs */, Mips::LWXS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
    5936             :   { 5555 /* madd */, Mips::MADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5937             :   { 5555 /* madd */, Mips::MADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5938             :   { 5555 /* madd */, Mips::MADD_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5939             :   { 5555 /* madd */, Mips::MADD_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5940             :   { 5560 /* madd.d */, Mips::MADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    5941             :   { 5560 /* madd.d */, Mips::MADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5942             :   { 5567 /* madd.s */, Mips::MADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5943             :   { 5574 /* madd_q.h */, Mips::MADD_Q_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5944             :   { 5583 /* madd_q.w */, Mips::MADD_Q_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5945             :   { 5592 /* maddf.d */, Mips::MADDF_D, Convert__FGR64AsmReg1_0__Tie0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5946             :   { 5592 /* maddf.d */, Mips::MADDF_D_MMR6, Convert__FGR64AsmReg1_0__Tie0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5947             :   { 5600 /* maddf.s */, Mips::MADDF_S, Convert__FGR32AsmReg1_0__Tie0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5948             :   { 5600 /* maddf.s */, Mips::MADDF_S_MMR6, Convert__FGR32AsmReg1_0__Tie0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5949             :   { 5608 /* maddr_q.h */, Mips::MADDR_Q_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5950             :   { 5618 /* maddr_q.w */, Mips::MADDR_Q_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5951             :   { 5628 /* maddu */, Mips::MADDU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5952             :   { 5628 /* maddu */, Mips::MADDU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5953             :   { 5628 /* maddu */, Mips::MADDU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5954             :   { 5628 /* maddu */, Mips::MADDU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5955             :   { 5634 /* maddv.b */, Mips::MADDV_B, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5956             :   { 5642 /* maddv.d */, Mips::MADDV_D, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5957             :   { 5650 /* maddv.h */, Mips::MADDV_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5958             :   { 5658 /* maddv.w */, Mips::MADDV_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5959             :   { 5666 /* maq_s.w.phl */, Mips::MAQ_S_W_PHL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5960             :   { 5666 /* maq_s.w.phl */, Mips::MAQ_S_W_PHL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5961             :   { 5678 /* maq_s.w.phr */, Mips::MAQ_S_W_PHR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5962             :   { 5678 /* maq_s.w.phr */, Mips::MAQ_S_W_PHR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5963             :   { 5690 /* maq_sa.w.phl */, Mips::MAQ_SA_W_PHL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5964             :   { 5690 /* maq_sa.w.phl */, Mips::MAQ_SA_W_PHL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5965             :   { 5703 /* maq_sa.w.phr */, Mips::MAQ_SA_W_PHR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5966             :   { 5703 /* maq_sa.w.phr */, Mips::MAQ_SA_W_PHR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    5967             :   { 5716 /* max.d */, Mips::MAX_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5968             :   { 5716 /* max.d */, Mips::MAX_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5969             :   { 5722 /* max.s */, Mips::MAX_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5970             :   { 5722 /* max.s */, Mips::MAX_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5971             :   { 5728 /* max_a.b */, Mips::MAX_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5972             :   { 5736 /* max_a.d */, Mips::MAX_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5973             :   { 5744 /* max_a.h */, Mips::MAX_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5974             :   { 5752 /* max_a.w */, Mips::MAX_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5975             :   { 5760 /* max_s.b */, Mips::MAX_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5976             :   { 5768 /* max_s.d */, Mips::MAX_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5977             :   { 5776 /* max_s.h */, Mips::MAX_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5978             :   { 5784 /* max_s.w */, Mips::MAX_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5979             :   { 5792 /* max_u.b */, Mips::MAX_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5980             :   { 5800 /* max_u.d */, Mips::MAX_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5981             :   { 5808 /* max_u.h */, Mips::MAX_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5982             :   { 5816 /* max_u.w */, Mips::MAX_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    5983             :   { 5824 /* maxa.d */, Mips::MAXA_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5984             :   { 5824 /* maxa.d */, Mips::MAXA_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    5985             :   { 5831 /* maxa.s */, Mips::MAXA_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5986             :   { 5831 /* maxa.s */, Mips::MAXA_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    5987             :   { 5838 /* maxi_s.b */, Mips::MAXI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
    5988             :   { 5847 /* maxi_s.d */, Mips::MAXI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
    5989             :   { 5856 /* maxi_s.h */, Mips::MAXI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
    5990             :   { 5865 /* maxi_s.w */, Mips::MAXI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
    5991             :   { 5874 /* maxi_u.b */, Mips::MAXI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    5992             :   { 5883 /* maxi_u.d */, Mips::MAXI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    5993             :   { 5892 /* maxi_u.h */, Mips::MAXI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    5994             :   { 5901 /* maxi_u.w */, Mips::MAXI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    5995             :   { 5910 /* mfc0 */, Mips::MFC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
    5996             :   { 5910 /* mfc0 */, Mips::MFC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, 0, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
    5997             :   { 5910 /* mfc0 */, Mips::MFC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMips32|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
    5998             :   { 5910 /* mfc0 */, Mips::MFC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
    5999             :   { 5915 /* mfc1 */, Mips::MFC1_MMR6, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
    6000             :   { 5915 /* mfc1 */, Mips::MFC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
    6001             :   { 5915 /* mfc1 */, Mips::MFC1_D64, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
    6002             :   { 5920 /* mfc2 */, Mips::MFC2_MMR6, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
    6003             :   { 5920 /* mfc2 */, Mips::MFC2, Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0, 0, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
    6004             :   { 5920 /* mfc2 */, Mips::MFC2, Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, },
    6005             :   { 5925 /* mfhc0 */, Mips::MFHC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
    6006             :   { 5925 /* mfhc0 */, Mips::MFHC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
    6007             :   { 5931 /* mfhc1 */, Mips::MFHC1_D32, Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
    6008             :   { 5931 /* mfhc1 */, Mips::MFHC1_MM, Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
    6009             :   { 5931 /* mfhc1 */, Mips::MFHC1_D32_MMR6, Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
    6010             :   { 5931 /* mfhc1 */, Mips::MFHC1_D64, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
    6011             :   { 5931 /* mfhc1 */, Mips::MFHC1_D64_MMR6, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
    6012             :   { 5937 /* mfhc2 */, Mips::MFHC2_MMR6, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
    6013             :   { 5943 /* mfhi */, Mips::Mfhi16, Convert__Reg1_0, Feature_InMips16Mode, { MCK_CPU16Regs }, },
    6014             :   { 5943 /* mfhi */, Mips::MFHI, Convert__GPR32AsmReg1_0, Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
    6015             :   { 5943 /* mfhi */, Mips::MFHI16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
    6016             :   { 5943 /* mfhi */, Mips::MFHI_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
    6017             :   { 5943 /* mfhi */, Mips::MFHI_DSP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
    6018             :   { 5943 /* mfhi */, Mips::MFHI_DSP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
    6019             :   { 5948 /* mflo */, Mips::Mflo16, Convert__Reg1_0, Feature_InMips16Mode, { MCK_CPU16Regs }, },
    6020             :   { 5948 /* mflo */, Mips::MFLO, Convert__GPR32AsmReg1_0, Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
    6021             :   { 5948 /* mflo */, Mips::MFLO16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
    6022             :   { 5948 /* mflo */, Mips::MFLO_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
    6023             :   { 5948 /* mflo */, Mips::MFLO_DSP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
    6024             :   { 5948 /* mflo */, Mips::MFLO_DSP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
    6025             :   { 5953 /* min.d */, Mips::MIN_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    6026             :   { 5953 /* min.d */, Mips::MIN_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    6027             :   { 5959 /* min.s */, Mips::MIN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6028             :   { 5959 /* min.s */, Mips::MIN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6029             :   { 5965 /* min_a.b */, Mips::MIN_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6030             :   { 5973 /* min_a.d */, Mips::MIN_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6031             :   { 5981 /* min_a.h */, Mips::MIN_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6032             :   { 5989 /* min_a.w */, Mips::MIN_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6033             :   { 5997 /* min_s.b */, Mips::MIN_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6034             :   { 6005 /* min_s.d */, Mips::MIN_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6035             :   { 6013 /* min_s.h */, Mips::MIN_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6036             :   { 6021 /* min_s.w */, Mips::MIN_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6037             :   { 6029 /* min_u.b */, Mips::MIN_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6038             :   { 6037 /* min_u.d */, Mips::MIN_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6039             :   { 6045 /* min_u.h */, Mips::MIN_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6040             :   { 6053 /* min_u.w */, Mips::MIN_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6041             :   { 6061 /* mina.d */, Mips::MINA_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    6042             :   { 6061 /* mina.d */, Mips::MINA_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    6043             :   { 6068 /* mina.s */, Mips::MINA_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6044             :   { 6068 /* mina.s */, Mips::MINA_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6045             :   { 6075 /* mini_s.b */, Mips::MINI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
    6046             :   { 6084 /* mini_s.d */, Mips::MINI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
    6047             :   { 6093 /* mini_s.h */, Mips::MINI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
    6048             :   { 6102 /* mini_s.w */, Mips::MINI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
    6049             :   { 6111 /* mini_u.b */, Mips::MINI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    6050             :   { 6120 /* mini_u.d */, Mips::MINI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    6051             :   { 6129 /* mini_u.h */, Mips::MINI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    6052             :   { 6138 /* mini_u.w */, Mips::MINI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    6053             :   { 6147 /* mod */, Mips::MOD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6054             :   { 6147 /* mod */, Mips::MOD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6055             :   { 6151 /* mod_s.b */, Mips::MOD_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6056             :   { 6159 /* mod_s.d */, Mips::MOD_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6057             :   { 6167 /* mod_s.h */, Mips::MOD_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6058             :   { 6175 /* mod_s.w */, Mips::MOD_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6059             :   { 6183 /* mod_u.b */, Mips::MOD_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6060             :   { 6191 /* mod_u.d */, Mips::MOD_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6061             :   { 6199 /* mod_u.h */, Mips::MOD_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6062             :   { 6207 /* mod_u.w */, Mips::MOD_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6063             :   { 6215 /* modsub */, Mips::MODSUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6064             :   { 6215 /* modsub */, Mips::MODSUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6065             :   { 6222 /* modu */, Mips::MODU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6066             :   { 6222 /* modu */, Mips::MODU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6067             :   { 6227 /* mov.d */, Mips::FMOV_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    6068             :   { 6227 /* mov.d */, Mips::FMOV_D_MMR6, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    6069             :   { 6227 /* mov.d */, Mips::FMOV_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    6070             :   { 6233 /* mov.s */, Mips::FMOV_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6071             :   { 6233 /* mov.s */, Mips::FMOV_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6072             :   { 6239 /* move */, Mips::MoveR3216, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_DSPR }, },
    6073             :   { 6239 /* move */, Mips::Move32R16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_DSPR, MCK_CPU16Regs }, },
    6074             :   { 6239 /* move */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6075             :   { 6239 /* move */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6076             :   { 6239 /* move */, Mips::MOVE16_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6077             :   { 6239 /* move */, Mips::OR64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64, Feature_IsGP64bit|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    6078             :   { 6239 /* move */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64, Feature_IsGP64bit|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    6079             :   { 6244 /* move.v */, Mips::MOVE_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6080             :   { 6251 /* move16 */, Mips::MOVE16_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6081             :   { 6258 /* movep */, Mips::MOVEP_MM, Convert__MovePRegPair2_0__GPRMM16AsmRegMoveP1_1__GPRMM16AsmRegMoveP1_2, Feature_InMicroMips, { MCK_MovePRegPair, MCK_GPRMM16AsmRegMoveP, MCK_GPRMM16AsmRegMoveP }, },
    6082             :   { 6264 /* movf */, Mips::MOVF_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
    6083             :   { 6264 /* movf */, Mips::MOVF_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
    6084             :   { 6269 /* movf.d */, Mips::MOVF_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, },
    6085             :   { 6269 /* movf.d */, Mips::MOVF_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FCCAsmReg }, },
    6086             :   { 6276 /* movf.s */, Mips::MOVF_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, },
    6087             :   { 6283 /* movn */, Mips::MOVN_I_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6088             :   { 6283 /* movn */, Mips::MOVN_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6089             :   { 6288 /* movn.d */, Mips::MOVN_I_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
    6090             :   { 6288 /* movn.d */, Mips::MOVN_I_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, },
    6091             :   { 6295 /* movn.s */, Mips::MOVN_I_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
    6092             :   { 6302 /* movt */, Mips::MOVT_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
    6093             :   { 6302 /* movt */, Mips::MOVT_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
    6094             :   { 6307 /* movt.d */, Mips::MOVT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, },
    6095             :   { 6307 /* movt.d */, Mips::MOVT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FCCAsmReg }, },
    6096             :   { 6314 /* movt.s */, Mips::MOVT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, },
    6097             :   { 6321 /* movz */, Mips::MOVZ_I_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6098             :   { 6321 /* movz */, Mips::MOVZ_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6099             :   { 6326 /* movz.d */, Mips::MOVZ_I_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
    6100             :   { 6326 /* movz.d */, Mips::MOVZ_I_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, },
    6101             :   { 6333 /* movz.s */, Mips::MOVZ_I_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
    6102             :   { 6340 /* msub */, Mips::MSUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6103             :   { 6340 /* msub */, Mips::MSUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6104             :   { 6340 /* msub */, Mips::MSUB_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6105             :   { 6340 /* msub */, Mips::MSUB_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6106             :   { 6345 /* msub.d */, Mips::MSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    6107             :   { 6345 /* msub.d */, Mips::MSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    6108             :   { 6352 /* msub.s */, Mips::MSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6109             :   { 6359 /* msub_q.h */, Mips::MSUB_Q_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6110             :   { 6368 /* msub_q.w */, Mips::MSUB_Q_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6111             :   { 6377 /* msubf.d */, Mips::MSUBF_D, Convert__FGR64AsmReg1_0__Tie0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    6112             :   { 6377 /* msubf.d */, Mips::MSUBF_D_MMR6, Convert__FGR64AsmReg1_0__Tie0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    6113             :   { 6385 /* msubf.s */, Mips::MSUBF_S, Convert__FGR32AsmReg1_0__Tie0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6114             :   { 6385 /* msubf.s */, Mips::MSUBF_S_MMR6, Convert__FGR32AsmReg1_0__Tie0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6115             :   { 6393 /* msubr_q.h */, Mips::MSUBR_Q_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6116             :   { 6403 /* msubr_q.w */, Mips::MSUBR_Q_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6117             :   { 6413 /* msubu */, Mips::MSUBU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6118             :   { 6413 /* msubu */, Mips::MSUBU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6119             :   { 6413 /* msubu */, Mips::MSUBU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6120             :   { 6413 /* msubu */, Mips::MSUBU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6121             :   { 6419 /* msubv.b */, Mips::MSUBV_B, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6122             :   { 6427 /* msubv.d */, Mips::MSUBV_D, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6123             :   { 6435 /* msubv.h */, Mips::MSUBV_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6124             :   { 6443 /* msubv.w */, Mips::MSUBV_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6125             :   { 6451 /* mtc0 */, Mips::MTC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
    6126             :   { 6451 /* mtc0 */, Mips::MTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, 0, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
    6127             :   { 6451 /* mtc0 */, Mips::MTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMips32|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
    6128             :   { 6451 /* mtc0 */, Mips::MTC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
    6129             :   { 6456 /* mtc1 */, Mips::MTC1_MMR6, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
    6130             :   { 6456 /* mtc1 */, Mips::MTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
    6131             :   { 6456 /* mtc1 */, Mips::MTC1_D64, Convert__FGR64AsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
    6132             :   { 6461 /* mtc2 */, Mips::MTC2_MMR6, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
    6133             :   { 6461 /* mtc2 */, Mips::MTC2, Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0, 0, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
    6134             :   { 6461 /* mtc2 */, Mips::MTC2, Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, },
    6135             :   { 6466 /* mthc0 */, Mips::MTHC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
    6136             :   { 6466 /* mthc0 */, Mips::MTHC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
    6137             :   { 6472 /* mthc1 */, Mips::MTHC1_D32, Convert__AFGR64AsmReg1_1__Tie0__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
    6138             :   { 6472 /* mthc1 */, Mips::MTHC1_MM, Convert__AFGR64AsmReg1_1__Tie0__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
    6139             :   { 6472 /* mthc1 */, Mips::MTHC1_D32_MMR6, Convert__AFGR64AsmReg1_1__Tie0__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
    6140             :   { 6472 /* mthc1 */, Mips::MTHC1_D64, Convert__FGR64AsmReg1_1__Tie0__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
    6141             :   { 6472 /* mthc1 */, Mips::MTHC1_D64_MMR6, Convert__FGR64AsmReg1_1__Tie0__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
    6142             :   { 6478 /* mthc2 */, Mips::MTHC2_MMR6, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
    6143             :   { 6484 /* mthi */, Mips::MTHI, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg }, },
    6144             :   { 6484 /* mthi */, Mips::MTHI_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
    6145             :   { 6484 /* mthi */, Mips::MTHI_DSP_MM, Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_HI32DSPAsmReg }, },
    6146             :   { 6484 /* mthi */, Mips::MTHI_DSP, Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_HI32DSPAsmReg }, },
    6147             :   { 6489 /* mthlip */, Mips::MTHLIP_MM, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
    6148             :   { 6489 /* mthlip */, Mips::MTHLIP, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
    6149             :   { 6496 /* mtlo */, Mips::MTLO, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg }, },
    6150             :   { 6496 /* mtlo */, Mips::MTLO_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
    6151             :   { 6496 /* mtlo */, Mips::MTLO_DSP_MM, Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_LO32DSPAsmReg }, },
    6152             :   { 6496 /* mtlo */, Mips::MTLO_DSP, Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_LO32DSPAsmReg }, },
    6153             :   { 6501 /* mtm0 */, Mips::MTM0, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
    6154             :   { 6506 /* mtm1 */, Mips::MTM1, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
    6155             :   { 6511 /* mtm2 */, Mips::MTM2, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
    6156             :   { 6516 /* mtp0 */, Mips::MTP0, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
    6157             :   { 6521 /* mtp1 */, Mips::MTP1, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
    6158             :   { 6526 /* mtp2 */, Mips::MTP2, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
    6159             :   { 6531 /* muh */, Mips::MUH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6160             :   { 6531 /* muh */, Mips::MUH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6161             :   { 6531 /* muh */, Mips::MUH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6162             :   { 6535 /* muhu */, Mips::MUHU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6163             :   { 6535 /* muhu */, Mips::MUHU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6164             :   { 6535 /* muhu */, Mips::MUHU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6165             :   { 6540 /* mul */, Mips::MUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6166             :   { 6540 /* mul */, Mips::MUL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6167             :   { 6540 /* mul */, Mips::MUL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6168             :   { 6540 /* mul */, Mips::MUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6169             :   { 6540 /* mul */, Mips::MUL_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6170             :   { 6540 /* mul */, Mips::MUL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6171             :   { 6540 /* mul */, Mips::MUL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6172             :   { 6540 /* mul */, Mips::MULImmMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
    6173             :   { 6544 /* mul.d */, Mips::FMUL_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    6174             :   { 6544 /* mul.d */, Mips::FMUL_D_MMR6, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_2__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    6175             :   { 6544 /* mul.d */, Mips::FMUL_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    6176             :   { 6550 /* mul.ph */, Mips::MUL_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6177             :   { 6550 /* mul.ph */, Mips::MUL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6178             :   { 6557 /* mul.s */, Mips::FMUL_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6179             :   { 6557 /* mul.s */, Mips::FMUL_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6180             :   { 6563 /* mul_q.h */, Mips::MUL_Q_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6181             :   { 6571 /* mul_q.w */, Mips::MUL_Q_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6182             :   { 6579 /* mul_s.ph */, Mips::MUL_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6183             :   { 6579 /* mul_s.ph */, Mips::MUL_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6184             :   { 6588 /* muleq_s.w.phl */, Mips::MULEQ_S_W_PHL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6185             :   { 6588 /* muleq_s.w.phl */, Mips::MULEQ_S_W_PHL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6186             :   { 6602 /* muleq_s.w.phr */, Mips::MULEQ_S_W_PHR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6187             :   { 6602 /* muleq_s.w.phr */, Mips::MULEQ_S_W_PHR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6188             :   { 6616 /* muleu_s.ph.qbl */, Mips::MULEU_S_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6189             :   { 6616 /* muleu_s.ph.qbl */, Mips::MULEU_S_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6190             :   { 6631 /* muleu_s.ph.qbr */, Mips::MULEU_S_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6191             :   { 6631 /* muleu_s.ph.qbr */, Mips::MULEU_S_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6192             :   { 6646 /* mulo */, Mips::MULOMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6193             :   { 6646 /* mulo */, Mips::MULOMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6194             :   { 6651 /* mulou */, Mips::MULOUMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6195             :   { 6651 /* mulou */, Mips::MULOUMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6196             :   { 6657 /* mulq_rs.ph */, Mips::MULQ_RS_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6197             :   { 6657 /* mulq_rs.ph */, Mips::MULQ_RS_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6198             :   { 6668 /* mulq_rs.w */, Mips::MULQ_RS_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6199             :   { 6668 /* mulq_rs.w */, Mips::MULQ_RS_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6200             :   { 6678 /* mulq_s.ph */, Mips::MULQ_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6201             :   { 6678 /* mulq_s.ph */, Mips::MULQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6202             :   { 6688 /* mulq_s.w */, Mips::MULQ_S_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6203             :   { 6688 /* mulq_s.w */, Mips::MULQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6204             :   { 6697 /* mulr_q.h */, Mips::MULR_Q_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6205             :   { 6706 /* mulr_q.w */, Mips::MULR_Q_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6206             :   { 6715 /* mulsa.w.ph */, Mips::MULSA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6207             :   { 6715 /* mulsa.w.ph */, Mips::MULSA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6208             :   { 6726 /* mulsaq_s.w.ph */, Mips::MULSAQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6209             :   { 6726 /* mulsaq_s.w.ph */, Mips::MULSAQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6210             :   { 6740 /* mult */, Mips::MULT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6211             :   { 6740 /* mult */, Mips::MULT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6212             :   { 6740 /* mult */, Mips::MULT_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6213             :   { 6740 /* mult */, Mips::MULT_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6214             :   { 6745 /* multu */, Mips::MULTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6215             :   { 6745 /* multu */, Mips::MULTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6216             :   { 6745 /* multu */, Mips::MULTU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6217             :   { 6745 /* multu */, Mips::MULTU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6218             :   { 6751 /* mulu */, Mips::MULU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6219             :   { 6751 /* mulu */, Mips::MULU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6220             :   { 6751 /* mulu */, Mips::MULU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6221             :   { 6756 /* mulv.b */, Mips::MULV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6222             :   { 6763 /* mulv.d */, Mips::MULV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6223             :   { 6770 /* mulv.h */, Mips::MULV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6224             :   { 6777 /* mulv.w */, Mips::MULV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6225             :   { 6784 /* neg */, Mips::SUB, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, 0, { MCK_GPR32AsmReg }, },
    6226             :   { 6784 /* neg */, Mips::NegRxRy16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
    6227             :   { 6784 /* neg */, Mips::SUB, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6228             :   { 6788 /* neg.d */, Mips::FNEG_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    6229             :   { 6788 /* neg.d */, Mips::FNEG_D_MMR6, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    6230             :   { 6788 /* neg.d */, Mips::FNEG_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    6231             :   { 6794 /* neg.s */, Mips::FNEG_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6232             :   { 6794 /* neg.s */, Mips::FNEG_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6233             :   { 6800 /* negu */, Mips::SUBu, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, 0, { MCK_GPR32AsmReg }, },
    6234             :   { 6800 /* negu */, Mips::SUBu, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6235             :   { 6805 /* nloc.b */, Mips::NLOC_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6236             :   { 6812 /* nloc.d */, Mips::NLOC_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6237             :   { 6819 /* nloc.h */, Mips::NLOC_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6238             :   { 6826 /* nloc.w */, Mips::NLOC_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6239             :   { 6833 /* nlzc.b */, Mips::NLZC_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6240             :   { 6840 /* nlzc.d */, Mips::NLZC_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6241             :   { 6847 /* nlzc.h */, Mips::NLZC_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6242             :   { 6854 /* nlzc.w */, Mips::NLZC_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6243             :   { 6861 /* nmadd.d */, Mips::NMADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    6244             :   { 6861 /* nmadd.d */, Mips::NMADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    6245             :   { 6869 /* nmadd.s */, Mips::NMADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6246             :   { 6877 /* nmsub.d */, Mips::NMSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    6247             :   { 6877 /* nmsub.d */, Mips::NMSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    6248             :   { 6885 /* nmsub.s */, Mips::NMSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6249             :   { 6893 /* nop */, Mips::SLL, Convert__regZERO__regZERO__imm_95_0, Feature_NotInMicroMips, {  }, },
    6250             :   { 6893 /* nop */, Mips::SLL_MM, Convert__regZERO__regZERO__imm_95_0, Feature_InMicroMips, {  }, },
    6251             :   { 6893 /* nop */, Mips::MOVE16_MM, Convert__regZERO__regZERO, Feature_InMicroMips, {  }, },
    6252             :   { 6893 /* nop */, Mips::SLL_MMR6, Convert__regZERO__regZERO__imm_95_0, Feature_HasMicroMips32r6, {  }, },
    6253             :   { 6897 /* nor */, Mips::NORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_IsGP32bit, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
    6254             :   { 6897 /* nor */, Mips::NORImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
    6255             :   { 6897 /* nor */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6256             :   { 6897 /* nor */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6257             :   { 6897 /* nor */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6258             :   { 6897 /* nor */, Mips::NORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_IsGP32bit, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
    6259             :   { 6897 /* nor */, Mips::NORImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
    6260             :   { 6901 /* nor.v */, Mips::NOR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6261             :   { 6907 /* nori.b */, Mips::NORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
    6262             :   { 6914 /* not */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
    6263             :   { 6914 /* not */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
    6264             :   { 6914 /* not */, Mips::NotRxRy16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
    6265             :   { 6914 /* not */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6266             :   { 6914 /* not */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6267             :   { 6914 /* not */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6268             :   { 6918 /* not16 */, Mips::NOT16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
    6269             :   { 6918 /* not16 */, Mips::NOT16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1, Feature_HasMicroMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
    6270             :   { 6924 /* or */, Mips::OrRxRxRy16, Convert__Reg1_0__Tie0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
    6271             :   { 6924 /* or */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6272             :   { 6924 /* or */, Mips::OR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6273             :   { 6924 /* or */, Mips::OR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6274             :   { 6924 /* or */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
    6275             :   { 6924 /* or */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
    6276             :   { 6924 /* or */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
    6277             :   { 6924 /* or */, Mips::ORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_IsGP64bit|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
    6278             :   { 6924 /* or */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6279             :   { 6924 /* or */, Mips::OR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6280             :   { 6924 /* or */, Mips::OR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6281             :   { 6924 /* or */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
    6282             :   { 6924 /* or */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
    6283             :   { 6924 /* or */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
    6284             :   { 6924 /* or */, Mips::ORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_IsGP64bit|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
    6285             :   { 6927 /* or.v */, Mips::OR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6286             :   { 6932 /* or16 */, Mips::OR16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0, Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
    6287             :   { 6932 /* or16 */, Mips::OR16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0, Feature_HasMicroMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
    6288             :   { 6937 /* ori */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
    6289             :   { 6937 /* ori */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, },
    6290             :   { 6937 /* ori */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, },
    6291             :   { 6937 /* ori */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
    6292             :   { 6937 /* ori */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
    6293             :   { 6937 /* ori */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
    6294             :   { 6941 /* ori.b */, Mips::ORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
    6295             :   { 6947 /* packrl.ph */, Mips::PACKRL_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6296             :   { 6947 /* packrl.ph */, Mips::PACKRL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6297             :   { 6957 /* pause */, Mips::PAUSE, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r2, {  }, },
    6298             :   { 6957 /* pause */, Mips::PAUSE_MMR6, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMicroMips32r6, {  }, },
    6299             :   { 6957 /* pause */, Mips::PAUSE_MM, Convert_NoOperands, Feature_InMicroMips, {  }, },
    6300             :   { 6963 /* pckev.b */, Mips::PCKEV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6301             :   { 6971 /* pckev.d */, Mips::PCKEV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6302             :   { 6979 /* pckev.h */, Mips::PCKEV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6303             :   { 6987 /* pckev.w */, Mips::PCKEV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6304             :   { 6995 /* pckod.b */, Mips::PCKOD_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6305             :   { 7003 /* pckod.d */, Mips::PCKOD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6306             :   { 7011 /* pckod.h */, Mips::PCKOD_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6307             :   { 7019 /* pckod.w */, Mips::PCKOD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6308             :   { 7027 /* pcnt.b */, Mips::PCNT_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6309             :   { 7034 /* pcnt.d */, Mips::PCNT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6310             :   { 7041 /* pcnt.h */, Mips::PCNT_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6311             :   { 7048 /* pcnt.w */, Mips::PCNT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6312             :   { 7055 /* pick.ph */, Mips::PICK_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6313             :   { 7055 /* pick.ph */, Mips::PICK_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6314             :   { 7063 /* pick.qb */, Mips::PICK_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6315             :   { 7063 /* pick.qb */, Mips::PICK_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6316             :   { 7071 /* pop */, Mips::POP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, Feature_HasCnMips, { MCK_GPR32AsmReg }, },
    6317             :   { 7071 /* pop */, Mips::POP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6318             :   { 7075 /* preceq.w.phl */, Mips::PRECEQ_W_PHL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6319             :   { 7075 /* preceq.w.phl */, Mips::PRECEQ_W_PHL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6320             :   { 7088 /* preceq.w.phr */, Mips::PRECEQ_W_PHR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6321             :   { 7088 /* preceq.w.phr */, Mips::PRECEQ_W_PHR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6322             :   { 7101 /* precequ.ph.qbl */, Mips::PRECEQU_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6323             :   { 7101 /* precequ.ph.qbl */, Mips::PRECEQU_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6324             :   { 7116 /* precequ.ph.qbla */, Mips::PRECEQU_PH_QBLA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6325             :   { 7116 /* precequ.ph.qbla */, Mips::PRECEQU_PH_QBLA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6326             :   { 7132 /* precequ.ph.qbr */, Mips::PRECEQU_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6327             :   { 7132 /* precequ.ph.qbr */, Mips::PRECEQU_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6328             :   { 7147 /* precequ.ph.qbra */, Mips::PRECEQU_PH_QBRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6329             :   { 7147 /* precequ.ph.qbra */, Mips::PRECEQU_PH_QBRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6330             :   { 7163 /* preceu.ph.qbl */, Mips::PRECEU_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6331             :   { 7163 /* preceu.ph.qbl */, Mips::PRECEU_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6332             :   { 7177 /* preceu.ph.qbla */, Mips::PRECEU_PH_QBLA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6333             :   { 7177 /* preceu.ph.qbla */, Mips::PRECEU_PH_QBLA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6334             :   { 7192 /* preceu.ph.qbr */, Mips::PRECEU_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6335             :   { 7192 /* preceu.ph.qbr */, Mips::PRECEU_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6336             :   { 7206 /* preceu.ph.qbra */, Mips::PRECEU_PH_QBRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6337             :   { 7206 /* preceu.ph.qbra */, Mips::PRECEU_PH_QBRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6338             :   { 7221 /* precr.qb.ph */, Mips::PRECR_QB_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6339             :   { 7221 /* precr.qb.ph */, Mips::PRECR_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6340             :   { 7233 /* precr_sra.ph.w */, Mips::PRECR_SRA_PH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6341             :   { 7233 /* precr_sra.ph.w */, Mips::PRECR_SRA_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6342             :   { 7248 /* precr_sra_r.ph.w */, Mips::PRECR_SRA_R_PH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6343             :   { 7248 /* precr_sra_r.ph.w */, Mips::PRECR_SRA_R_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6344             :   { 7265 /* precrq.ph.w */, Mips::PRECRQ_PH_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6345             :   { 7265 /* precrq.ph.w */, Mips::PRECRQ_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6346             :   { 7277 /* precrq.qb.ph */, Mips::PRECRQ_QB_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6347             :   { 7277 /* precrq.qb.ph */, Mips::PRECRQ_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6348             :   { 7290 /* precrq_rs.ph.w */, Mips::PRECRQ_RS_PH_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6349             :   { 7290 /* precrq_rs.ph.w */, Mips::PRECRQ_RS_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6350             :   { 7305 /* precrqu_s.qb.ph */, Mips::PRECRQU_S_QB_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6351             :   { 7305 /* precrqu_s.qb.ph */, Mips::PRECRQU_S_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6352             :   { 7321 /* pref */, Mips::PREF_R6, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
    6353             :   { 7321 /* pref */, Mips::PREF, Convert__Mem2_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
    6354             :   { 7321 /* pref */, Mips::PREF_MMR6, Convert__Mem2_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
    6355             :   { 7321 /* pref */, Mips::PREF_MM, Convert__Mem2_1__ConstantUImm5_01_0, Feature_InMicroMips, { MCK_ConstantUImm5_0, MCK_Mem }, },
    6356             :   { 7326 /* prefe */, Mips::PREFE, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasEVA, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
    6357             :   { 7326 /* prefe */, Mips::PREFE_MMR6, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
    6358             :   { 7326 /* prefe */, Mips::PREFE_MM, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_InMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
    6359             :   { 7332 /* prefx */, Mips::PREFX_MM, Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0, Feature_InMicroMips, { MCK_ConstantUImm5_0, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
    6360             :   { 7338 /* prepend */, Mips::PREPEND_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6361             :   { 7338 /* prepend */, Mips::PREPEND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6362             :   { 7346 /* raddu.w.qb */, Mips::RADDU_W_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6363             :   { 7346 /* raddu.w.qb */, Mips::RADDU_W_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6364             :   { 7357 /* rddsp */, Mips::RDDSP_MM, Convert__GPR32AsmReg1_0__ConstantUImm7_01_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm7_0 }, },
    6365             :   { 7357 /* rddsp */, Mips::RDDSP, Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
    6366             :   { 7363 /* rdhwr */, Mips::RDHWR_MM, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1, Feature_HasStdEnc|Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, },
    6367             :   { 7363 /* rdhwr */, Mips::RDHWR, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, },
    6368             :   { 7363 /* rdhwr */, Mips::RDHWR_MMR6, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, },
    6369             :   { 7363 /* rdhwr */, Mips::RDHWR_MMR6, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm3_0 }, },
    6370             :   { 7369 /* rdpgpr */, Mips::RDPGPR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6371             :   { 7376 /* recip.d */, Mips::RECIP_D_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    6372             :   { 7376 /* recip.d */, Mips::RECIP_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    6373             :   { 7384 /* recip.s */, Mips::RECIP_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6374             :   { 7384 /* recip.s */, Mips::RECIP_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6375             :   { 7392 /* repl.ph */, Mips::REPL_PH_MM, Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantSImm10_0 }, },
    6376             :   { 7392 /* repl.ph */, Mips::REPL_PH, Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantSImm10_0 }, },
    6377             :   { 7400 /* repl.qb */, Mips::REPL_QB_MM, Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm8_0 }, },
    6378             :   { 7400 /* repl.qb */, Mips::REPL_QB, Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm8_0 }, },
    6379             :   { 7408 /* replv.ph */, Mips::REPLV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6380             :   { 7408 /* replv.ph */, Mips::REPLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6381             :   { 7417 /* replv.qb */, Mips::REPLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6382             :   { 7417 /* replv.qb */, Mips::REPLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6383             :   { 7426 /* rint.d */, Mips::RINT_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    6384             :   { 7426 /* rint.d */, Mips::RINT_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    6385             :   { 7433 /* rint.s */, Mips::RINT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6386             :   { 7433 /* rint.s */, Mips::RINT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6387             :   { 7440 /* rol */, Mips::ROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6388             :   { 7440 /* rol */, Mips::ROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, 0, { MCK_GPR32AsmReg, MCK_SImm16 }, },
    6389             :   { 7440 /* rol */, Mips::ROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6390             :   { 7440 /* rol */, Mips::ROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
    6391             :   { 7444 /* ror */, Mips::ROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6392             :   { 7444 /* ror */, Mips::RORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, 0, { MCK_GPR32AsmReg, MCK_SImm16 }, },
    6393             :   { 7444 /* ror */, Mips::ROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6394             :   { 7444 /* ror */, Mips::RORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
    6395             :   { 7448 /* rotr */, Mips::ROTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6396             :   { 7448 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6397             :   { 7448 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6398             :   { 7448 /* rotr */, Mips::ROTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6399             :   { 7448 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6400             :   { 7453 /* rotrv */, Mips::ROTRV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6401             :   { 7453 /* rotrv */, Mips::ROTRV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6402             :   { 7459 /* round.l.d */, Mips::ROUND_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    6403             :   { 7459 /* round.l.d */, Mips::ROUND_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    6404             :   { 7469 /* round.l.s */, Mips::ROUND_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
    6405             :   { 7469 /* round.l.s */, Mips::ROUND_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
    6406             :   { 7479 /* round.w.d */, Mips::ROUND_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
    6407             :   { 7479 /* round.w.d */, Mips::ROUND_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
    6408             :   { 7479 /* round.w.d */, Mips::ROUND_W_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    6409             :   { 7489 /* round.w.s */, Mips::ROUND_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6410             :   { 7489 /* round.w.s */, Mips::ROUND_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6411             :   { 7499 /* rsqrt.d */, Mips::RSQRT_D_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    6412             :   { 7499 /* rsqrt.d */, Mips::RSQRT_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    6413             :   { 7507 /* rsqrt.s */, Mips::RSQRT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6414             :   { 7507 /* rsqrt.s */, Mips::RSQRT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6415             :   { 7515 /* s.d */, Mips::SDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, },
    6416             :   { 7515 /* s.d */, Mips::SDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, },
    6417             :   { 7519 /* s.s */, Mips::SWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, },
    6418             :   { 7523 /* sat_s.b */, Mips::SAT_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
    6419             :   { 7531 /* sat_s.d */, Mips::SAT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
    6420             :   { 7539 /* sat_s.h */, Mips::SAT_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
    6421             :   { 7547 /* sat_s.w */, Mips::SAT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    6422             :   { 7555 /* sat_u.b */, Mips::SAT_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
    6423             :   { 7563 /* sat_u.d */, Mips::SAT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
    6424             :   { 7571 /* sat_u.h */, Mips::SAT_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
    6425             :   { 7579 /* sat_u.w */, Mips::SAT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    6426             :   { 7587 /* sb */, Mips::SB_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
    6427             :   { 7587 /* sb */, Mips::SB, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_Mem }, },
    6428             :   { 7587 /* sb */, Mips::SB_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
    6429             :   { 7587 /* sb */, Mips::SbRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_SImm16 }, },
    6430             :   { 7590 /* sb16 */, Mips::SB16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_InMicroMips, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
    6431             :   { 7590 /* sb16 */, Mips::SB16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_HasMicroMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
    6432             :   { 7595 /* sbe */, Mips::SBE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    6433             :   { 7595 /* sbe */, Mips::SBE_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    6434             :   { 7595 /* sbe */, Mips::SBE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    6435             :   { 7599 /* sc */, Mips::SC64_R6, Convert__GPR32AsmReg1_0__Tie0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    6436             :   { 7599 /* sc */, Mips::SC_R6, Convert__GPR32AsmReg1_0__Tie0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    6437             :   { 7599 /* sc */, Mips::SC, Convert__GPR32AsmReg1_0__Tie0__Mem2_1, Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
    6438             :   { 7599 /* sc */, Mips::SC64, Convert__GPR32AsmReg1_0__Tie0__Mem2_1, Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
    6439             :   { 7599 /* sc */, Mips::SC_MM, Convert__GPR32AsmReg1_0__Tie0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
    6440             :   { 7602 /* scd */, Mips::SCD_R6, Convert__GPR64AsmReg1_0__Tie0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR64AsmReg, MCK_MemOffsetSimm9 }, },
    6441             :   { 7602 /* scd */, Mips::SCD, Convert__GPR64AsmReg1_0__Tie0__Mem2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
    6442             :   { 7606 /* sce */, Mips::SCE, Convert__GPR32AsmReg1_0__Tie0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    6443             :   { 7606 /* sce */, Mips::SCE_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    6444             :   { 7606 /* sce */, Mips::SCE_MM, Convert__GPR32AsmReg1_0__Tie0__MemOffsetSimm92_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    6445             :   { 7610 /* sd */, Mips::SDMacro, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_NotMips3, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
    6446             :   { 7610 /* sd */, Mips::SD, Convert__GPR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimm16 }, },
    6447             :   { 7610 /* sd */, Mips::SD_MM64R6, Convert__GPR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_MemOffsetSimm16 }, },
    6448             :   { 7613 /* sdbbp */, Mips::SDBBP, Convert__imm_95_0, Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, {  }, },
    6449             :   { 7613 /* sdbbp */, Mips::SDBBP_R6, Convert__imm_95_0, Feature_HasMips32r6|Feature_NotInMicroMips, {  }, },
    6450             :   { 7613 /* sdbbp */, Mips::SDBBP_MMR6, Convert__imm_95_0, Feature_HasMicroMips32r6, {  }, },
    6451             :   { 7613 /* sdbbp */, Mips::SDBBP_MM, Convert__ConstantUImm10_01_0, Feature_InMicroMips, { MCK_ConstantUImm10_0 }, },
    6452             :   { 7613 /* sdbbp */, Mips::SDBBP, Convert__ConstantUImm20_01_0, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_ConstantUImm20_0 }, },
    6453             :   { 7613 /* sdbbp */, Mips::SDBBP_R6, Convert__ConstantUImm20_01_0, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_ConstantUImm20_0 }, },
    6454             :   { 7613 /* sdbbp */, Mips::SDBBP_MMR6, Convert__ConstantUImm20_01_0, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_ConstantUImm20_0 }, },
    6455             :   { 7619 /* sdbbp16 */, Mips::SDBBP16_MM, Convert__ConstantUImm4_01_0, Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_ConstantUImm4_0 }, },
    6456             :   { 7619 /* sdbbp16 */, Mips::SDBBP16_MMR6, Convert__ConstantUImm4_01_0, Feature_HasMicroMips32r6, { MCK_ConstantUImm4_0 }, },
    6457             :   { 7627 /* sdc1 */, Mips::SDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, },
    6458             :   { 7627 /* sdc1 */, Mips::SDC1_MM, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, },
    6459             :   { 7627 /* sdc1 */, Mips::SDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, },
    6460             :   { 7627 /* sdc1 */, Mips::SDC1_D64_MMR6, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, },
    6461             :   { 7632 /* sdc2 */, Mips::SDC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
    6462             :   { 7632 /* sdc2 */, Mips::SDC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
    6463             :   { 7632 /* sdc2 */, Mips::SDC2, Convert__COP2AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16 }, },
    6464             :   { 7637 /* sdc3 */, Mips::SDC3, Convert__COP3AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
    6465             :   { 7642 /* sdl */, Mips::SDL, Convert__GPR64AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
    6466             :   { 7646 /* sdr */, Mips::SDR, Convert__GPR64AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
    6467             :   { 7650 /* sdxc1 */, Mips::SDXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
    6468             :   { 7650 /* sdxc1 */, Mips::SDXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
    6469             :   { 7656 /* seb */, Mips::SebRx16, Convert__Reg1_0__Tie0, Feature_InMips16Mode, { MCK_CPU16Regs }, },
    6470             :   { 7656 /* seb */, Mips::SEB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
    6471             :   { 7656 /* seb */, Mips::SEB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
    6472             :   { 7656 /* seb */, Mips::SEB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, Feature_HasMicroMips32r6, { MCK_GPR32AsmReg }, },
    6473             :   { 7656 /* seb */, Mips::SEB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6474             :   { 7656 /* seb */, Mips::SEB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6475             :   { 7656 /* seb */, Mips::SEB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6476             :   { 7660 /* seh */, Mips::SehRx16, Convert__Reg1_0__Tie0, Feature_InMips16Mode, { MCK_CPU16Regs }, },
    6477             :   { 7660 /* seh */, Mips::SEH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
    6478             :   { 7660 /* seh */, Mips::SEH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
    6479             :   { 7660 /* seh */, Mips::SEH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, Feature_HasMicroMips32r6, { MCK_GPR32AsmReg }, },
    6480             :   { 7660 /* seh */, Mips::SEH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6481             :   { 7660 /* seh */, Mips::SEH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6482             :   { 7660 /* seh */, Mips::SEH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6483             :   { 7664 /* sel.d */, Mips::SEL_D, Convert__FGR64AsmReg1_0__Tie0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    6484             :   { 7664 /* sel.d */, Mips::SEL_D_MMR6, Convert__FGR64AsmReg1_0__Tie0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    6485             :   { 7670 /* sel.s */, Mips::SEL_S, Convert__FGR32AsmReg1_0__Tie0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6486             :   { 7670 /* sel.s */, Mips::SEL_S_MMR6, Convert__FGR32AsmReg1_0__Tie0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6487             :   { 7676 /* seleqz */, Mips::SELEQZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6488             :   { 7676 /* seleqz */, Mips::SELEQZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6489             :   { 7676 /* seleqz */, Mips::SELEQZ64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips32r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    6490             :   { 7683 /* seleqz.d */, Mips::SELEQZ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    6491             :   { 7683 /* seleqz.d */, Mips::SELEQZ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    6492             :   { 7692 /* seleqz.s */, Mips::SELEQZ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6493             :   { 7692 /* seleqz.s */, Mips::SELEQZ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6494             :   { 7701 /* selnez */, Mips::SELNEZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6495             :   { 7701 /* selnez */, Mips::SELNEZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6496             :   { 7701 /* selnez */, Mips::SELNEZ64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips32r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    6497             :   { 7708 /* selnez.d */, Mips::SELNEZ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    6498             :   { 7708 /* selnez.d */, Mips::SELNEZ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    6499             :   { 7717 /* selnez.s */, Mips::SELNEZ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6500             :   { 7717 /* selnez.s */, Mips::SELNEZ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6501             :   { 7726 /* seq */, Mips::SEQMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6502             :   { 7726 /* seq */, Mips::SEQIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, Feature_NotCnMips, { MCK_GPR32AsmReg, MCK_SImm32 }, },
    6503             :   { 7726 /* seq */, Mips::SEQ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    6504             :   { 7726 /* seq */, Mips::SEQMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6505             :   { 7726 /* seq */, Mips::SEQIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
    6506             :   { 7726 /* seq */, Mips::SEQ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    6507             :   { 7730 /* seqi */, Mips::SEQi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, },
    6508             :   { 7730 /* seqi */, Mips::SEQi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, },
    6509             :   { 7735 /* sgt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6510             :   { 7735 /* sgt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6511             :   { 7735 /* sgt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6512             :   { 7735 /* sgt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6513             :   { 7739 /* sgtu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6514             :   { 7739 /* sgtu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6515             :   { 7739 /* sgtu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6516             :   { 7739 /* sgtu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6517             :   { 7744 /* sh */, Mips::SH_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
    6518             :   { 7744 /* sh */, Mips::SH, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_Mem }, },
    6519             :   { 7744 /* sh */, Mips::SH_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
    6520             :   { 7744 /* sh */, Mips::ShRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_SImm16 }, },
    6521             :   { 7747 /* sh16 */, Mips::SH16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_InMicroMips, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
    6522             :   { 7747 /* sh16 */, Mips::SH16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_HasMicroMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
    6523             :   { 7752 /* she */, Mips::SHE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    6524             :   { 7752 /* she */, Mips::SHE_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    6525             :   { 7752 /* she */, Mips::SHE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    6526             :   { 7756 /* shf.b */, Mips::SHF_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
    6527             :   { 7762 /* shf.h */, Mips::SHF_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
    6528             :   { 7768 /* shf.w */, Mips::SHF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
    6529             :   { 7774 /* shilo */, Mips::SHILO_MM, Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_ConstantSImm6_0 }, },
    6530             :   { 7774 /* shilo */, Mips::SHILO, Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_ConstantSImm6_0 }, },
    6531             :   { 7780 /* shilov */, Mips::SHILOV_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
    6532             :   { 7780 /* shilov */, Mips::SHILOV, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
    6533             :   { 7787 /* shll.ph */, Mips::SHLL_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
    6534             :   { 7787 /* shll.ph */, Mips::SHLL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
    6535             :   { 7795 /* shll.qb */, Mips::SHLL_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
    6536             :   { 7795 /* shll.qb */, Mips::SHLL_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
    6537             :   { 7803 /* shll_s.ph */, Mips::SHLL_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
    6538             :   { 7803 /* shll_s.ph */, Mips::SHLL_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
    6539             :   { 7813 /* shll_s.w */, Mips::SHLL_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6540             :   { 7813 /* shll_s.w */, Mips::SHLL_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6541             :   { 7822 /* shllv.ph */, Mips::SHLLV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6542             :   { 7822 /* shllv.ph */, Mips::SHLLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6543             :   { 7831 /* shllv.qb */, Mips::SHLLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6544             :   { 7831 /* shllv.qb */, Mips::SHLLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6545             :   { 7840 /* shllv_s.ph */, Mips::SHLLV_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6546             :   { 7840 /* shllv_s.ph */, Mips::SHLLV_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6547             :   { 7851 /* shllv_s.w */, Mips::SHLLV_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6548             :   { 7851 /* shllv_s.w */, Mips::SHLLV_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6549             :   { 7861 /* shra.ph */, Mips::SHRA_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
    6550             :   { 7861 /* shra.ph */, Mips::SHRA_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
    6551             :   { 7869 /* shra.qb */, Mips::SHRA_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
    6552             :   { 7869 /* shra.qb */, Mips::SHRA_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
    6553             :   { 7877 /* shra_r.ph */, Mips::SHRA_R_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
    6554             :   { 7877 /* shra_r.ph */, Mips::SHRA_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
    6555             :   { 7887 /* shra_r.qb */, Mips::SHRA_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
    6556             :   { 7887 /* shra_r.qb */, Mips::SHRA_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
    6557             :   { 7897 /* shra_r.w */, Mips::SHRA_R_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6558             :   { 7897 /* shra_r.w */, Mips::SHRA_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6559             :   { 7906 /* shrav.ph */, Mips::SHRAV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6560             :   { 7906 /* shrav.ph */, Mips::SHRAV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6561             :   { 7915 /* shrav.qb */, Mips::SHRAV_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6562             :   { 7915 /* shrav.qb */, Mips::SHRAV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6563             :   { 7924 /* shrav_r.ph */, Mips::SHRAV_R_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6564             :   { 7924 /* shrav_r.ph */, Mips::SHRAV_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6565             :   { 7935 /* shrav_r.qb */, Mips::SHRAV_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6566             :   { 7935 /* shrav_r.qb */, Mips::SHRAV_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6567             :   { 7946 /* shrav_r.w */, Mips::SHRAV_R_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6568             :   { 7946 /* shrav_r.w */, Mips::SHRAV_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6569             :   { 7956 /* shrl.ph */, Mips::SHRL_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
    6570             :   { 7956 /* shrl.ph */, Mips::SHRL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
    6571             :   { 7964 /* shrl.qb */, Mips::SHRL_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
    6572             :   { 7964 /* shrl.qb */, Mips::SHRL_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
    6573             :   { 7972 /* shrlv.ph */, Mips::SHRLV_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6574             :   { 7972 /* shrlv.ph */, Mips::SHRLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6575             :   { 7981 /* shrlv.qb */, Mips::SHRLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6576             :   { 7981 /* shrlv.qb */, Mips::SHRLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6577             :   { 7990 /* sld.b */, Mips::SLD_B, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
    6578             :   { 7996 /* sld.d */, Mips::SLD_D, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
    6579             :   { 8002 /* sld.h */, Mips::SLD_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
    6580             :   { 8008 /* sld.w */, Mips::SLD_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
    6581             :   { 8014 /* sldi.b */, Mips::SLDI_B, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm4_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, },
    6582             :   { 8021 /* sldi.d */, Mips::SLDI_D, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm1_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, },
    6583             :   { 8028 /* sldi.h */, Mips::SLDI_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm3_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, },
    6584             :   { 8035 /* sldi.w */, Mips::SLDI_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm2_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, },
    6585             :   { 8042 /* sll */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6586             :   { 8042 /* sll */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6587             :   { 8042 /* sll */, Mips::SLL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6588             :   { 8042 /* sll */, Mips::SLL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6589             :   { 8042 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6590             :   { 8042 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6591             :   { 8042 /* sll */, Mips::SllX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, },
    6592             :   { 8042 /* sll */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6593             :   { 8042 /* sll */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6594             :   { 8042 /* sll */, Mips::SLL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6595             :   { 8042 /* sll */, Mips::SLL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6596             :   { 8042 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6597             :   { 8046 /* sll.b */, Mips::SLL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6598             :   { 8052 /* sll.d */, Mips::SLL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6599             :   { 8058 /* sll.h */, Mips::SLL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6600             :   { 8064 /* sll.w */, Mips::SLL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6601             :   { 8070 /* sll16 */, Mips::SLL16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
    6602             :   { 8070 /* sll16 */, Mips::SLL16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_HasMicroMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
    6603             :   { 8076 /* slli.b */, Mips::SLLI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
    6604             :   { 8083 /* slli.d */, Mips::SLLI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
    6605             :   { 8090 /* slli.h */, Mips::SLLI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
    6606             :   { 8097 /* slli.w */, Mips::SLLI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    6607             :   { 8104 /* sllv */, Mips::SllvRxRy16, Convert__Reg1_0__Tie0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
    6608             :   { 8104 /* sllv */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6609             :   { 8104 /* sllv */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6610             :   { 8109 /* slt */, Mips::SltRxRy16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
    6611             :   { 8109 /* slt */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
    6612             :   { 8109 /* slt */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
    6613             :   { 8109 /* slt */, Mips::SLTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
    6614             :   { 8109 /* slt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6615             :   { 8109 /* slt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6616             :   { 8109 /* slt */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
    6617             :   { 8109 /* slt */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
    6618             :   { 8109 /* slt */, Mips::SLTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
    6619             :   { 8113 /* slti */, Mips::SltiRxImmX16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
    6620             :   { 8113 /* slti */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
    6621             :   { 8113 /* slti */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
    6622             :   { 8113 /* slti */, Mips::SltiRxImm16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
    6623             :   { 8118 /* sltiu */, Mips::SltiuRxImmX16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
    6624             :   { 8118 /* sltiu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
    6625             :   { 8118 /* sltiu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
    6626             :   { 8118 /* sltiu */, Mips::SltiuRxImm16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
    6627             :   { 8124 /* sltu */, Mips::SltuRxRy16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
    6628             :   { 8124 /* sltu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
    6629             :   { 8124 /* sltu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
    6630             :   { 8124 /* sltu */, Mips::SLTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
    6631             :   { 8124 /* sltu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6632             :   { 8124 /* sltu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6633             :   { 8124 /* sltu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
    6634             :   { 8124 /* sltu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
    6635             :   { 8124 /* sltu */, Mips::SLTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
    6636             :   { 8129 /* sne */, Mips::SNE, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    6637             :   { 8129 /* sne */, Mips::SNE, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
    6638             :   { 8133 /* snei */, Mips::SNEi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, },
    6639             :   { 8133 /* snei */, Mips::SNEi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, },
    6640             :   { 8138 /* splat.b */, Mips::SPLAT_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
    6641             :   { 8146 /* splat.d */, Mips::SPLAT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
    6642             :   { 8154 /* splat.h */, Mips::SPLAT_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
    6643             :   { 8162 /* splat.w */, Mips::SPLAT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
    6644             :   { 8170 /* splati.b */, Mips::SPLATI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, },
    6645             :   { 8179 /* splati.d */, Mips::SPLATI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, },
    6646             :   { 8188 /* splati.h */, Mips::SPLATI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, },
    6647             :   { 8197 /* splati.w */, Mips::SPLATI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, },
    6648             :   { 8206 /* sqrt.d */, Mips::FSQRT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    6649             :   { 8206 /* sqrt.d */, Mips::SQRT_D_MMR6, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    6650             :   { 8206 /* sqrt.d */, Mips::FSQRT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    6651             :   { 8213 /* sqrt.s */, Mips::FSQRT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6652             :   { 8213 /* sqrt.s */, Mips::FSQRT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6653             :   { 8213 /* sqrt.s */, Mips::SQRT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6654             :   { 8220 /* sra */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6655             :   { 8220 /* sra */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6656             :   { 8220 /* sra */, Mips::SRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6657             :   { 8220 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6658             :   { 8220 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6659             :   { 8220 /* sra */, Mips::SraX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, },
    6660             :   { 8220 /* sra */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6661             :   { 8220 /* sra */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6662             :   { 8220 /* sra */, Mips::SRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6663             :   { 8220 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6664             :   { 8224 /* sra.b */, Mips::SRA_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6665             :   { 8230 /* sra.d */, Mips::SRA_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6666             :   { 8236 /* sra.h */, Mips::SRA_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6667             :   { 8242 /* sra.w */, Mips::SRA_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6668             :   { 8248 /* srai.b */, Mips::SRAI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
    6669             :   { 8255 /* srai.d */, Mips::SRAI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
    6670             :   { 8262 /* srai.h */, Mips::SRAI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
    6671             :   { 8269 /* srai.w */, Mips::SRAI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    6672             :   { 8276 /* srar.b */, Mips::SRAR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6673             :   { 8283 /* srar.d */, Mips::SRAR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6674             :   { 8290 /* srar.h */, Mips::SRAR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6675             :   { 8297 /* srar.w */, Mips::SRAR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6676             :   { 8304 /* srari.b */, Mips::SRARI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
    6677             :   { 8312 /* srari.d */, Mips::SRARI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
    6678             :   { 8320 /* srari.h */, Mips::SRARI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
    6679             :   { 8328 /* srari.w */, Mips::SRARI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    6680             :   { 8336 /* srav */, Mips::SravRxRy16, Convert__Reg1_0__Tie0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
    6681             :   { 8336 /* srav */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6682             :   { 8336 /* srav */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6683             :   { 8341 /* srl */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6684             :   { 8341 /* srl */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6685             :   { 8341 /* srl */, Mips::SRL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6686             :   { 8341 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6687             :   { 8341 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6688             :   { 8341 /* srl */, Mips::SrlX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, },
    6689             :   { 8341 /* srl */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6690             :   { 8341 /* srl */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6691             :   { 8341 /* srl */, Mips::SRL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6692             :   { 8341 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
    6693             :   { 8345 /* srl.b */, Mips::SRL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6694             :   { 8351 /* srl.d */, Mips::SRL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6695             :   { 8357 /* srl.h */, Mips::SRL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6696             :   { 8363 /* srl.w */, Mips::SRL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6697             :   { 8369 /* srl16 */, Mips::SRL16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
    6698             :   { 8369 /* srl16 */, Mips::SRL16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_HasMicroMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
    6699             :   { 8375 /* srli.b */, Mips::SRLI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
    6700             :   { 8382 /* srli.d */, Mips::SRLI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
    6701             :   { 8389 /* srli.h */, Mips::SRLI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
    6702             :   { 8396 /* srli.w */, Mips::SRLI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    6703             :   { 8403 /* srlr.b */, Mips::SRLR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6704             :   { 8410 /* srlr.d */, Mips::SRLR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6705             :   { 8417 /* srlr.h */, Mips::SRLR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6706             :   { 8424 /* srlr.w */, Mips::SRLR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6707             :   { 8431 /* srlri.b */, Mips::SRLRI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
    6708             :   { 8439 /* srlri.d */, Mips::SRLRI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
    6709             :   { 8447 /* srlri.h */, Mips::SRLRI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
    6710             :   { 8455 /* srlri.w */, Mips::SRLRI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    6711             :   { 8463 /* srlv */, Mips::SrlvRxRy16, Convert__Reg1_0__Tie0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
    6712             :   { 8463 /* srlv */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6713             :   { 8463 /* srlv */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6714             :   { 8468 /* ssnop */, Mips::SSNOP_MMR6, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMicroMips32r6, {  }, },
    6715             :   { 8468 /* ssnop */, Mips::SSNOP, Convert_NoOperands, Feature_HasStdEnc, {  }, },
    6716             :   { 8468 /* ssnop */, Mips::SSNOP_MM, Convert_NoOperands, Feature_InMicroMips, {  }, },
    6717             :   { 8474 /* st.b */, Mips::ST_B, Convert__MSA128AsmReg1_0__MemOffsetSimm102_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10 }, },
    6718             :   { 8479 /* st.d */, Mips::ST_D, Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_3 }, },
    6719             :   { 8484 /* st.h */, Mips::ST_H, Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_1 }, },
    6720             :   { 8489 /* st.w */, Mips::ST_W, Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_2 }, },
    6721             :   { 8494 /* sub */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6722             :   { 8494 /* sub */, Mips::SUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6723             :   { 8494 /* sub */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6724             :   { 8494 /* sub */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1, Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_InvNum }, },
    6725             :   { 8494 /* sub */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6726             :   { 8494 /* sub */, Mips::SUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6727             :   { 8494 /* sub */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6728             :   { 8494 /* sub */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2, Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_InvNum }, },
    6729             :   { 8498 /* sub.d */, Mips::FSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    6730             :   { 8498 /* sub.d */, Mips::FSUB_D_MMR6, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_2__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
    6731             :   { 8498 /* sub.d */, Mips::FSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
    6732             :   { 8504 /* sub.s */, Mips::FSUB_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6733             :   { 8504 /* sub.s */, Mips::FSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
    6734             :   { 8510 /* subq.ph */, Mips::SUBQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6735             :   { 8510 /* subq.ph */, Mips::SUBQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6736             :   { 8518 /* subq_s.ph */, Mips::SUBQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6737             :   { 8518 /* subq_s.ph */, Mips::SUBQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6738             :   { 8528 /* subq_s.w */, Mips::SUBQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6739             :   { 8528 /* subq_s.w */, Mips::SUBQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6740             :   { 8537 /* subqh.ph */, Mips::SUBQH_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6741             :   { 8537 /* subqh.ph */, Mips::SUBQH_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6742             :   { 8546 /* subqh.w */, Mips::SUBQH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6743             :   { 8546 /* subqh.w */, Mips::SUBQH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6744             :   { 8554 /* subqh_r.ph */, Mips::SUBQH_R_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6745             :   { 8554 /* subqh_r.ph */, Mips::SUBQH_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6746             :   { 8565 /* subqh_r.w */, Mips::SUBQH_R_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6747             :   { 8565 /* subqh_r.w */, Mips::SUBQH_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6748             :   { 8575 /* subs_s.b */, Mips::SUBS_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6749             :   { 8584 /* subs_s.d */, Mips::SUBS_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6750             :   { 8593 /* subs_s.h */, Mips::SUBS_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6751             :   { 8602 /* subs_s.w */, Mips::SUBS_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6752             :   { 8611 /* subs_u.b */, Mips::SUBS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6753             :   { 8620 /* subs_u.d */, Mips::SUBS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6754             :   { 8629 /* subs_u.h */, Mips::SUBS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6755             :   { 8638 /* subs_u.w */, Mips::SUBS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6756             :   { 8647 /* subsus_u.b */, Mips::SUBSUS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6757             :   { 8658 /* subsus_u.d */, Mips::SUBSUS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6758             :   { 8669 /* subsus_u.h */, Mips::SUBSUS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6759             :   { 8680 /* subsus_u.w */, Mips::SUBSUS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6760             :   { 8691 /* subsuu_s.b */, Mips::SUBSUU_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6761             :   { 8702 /* subsuu_s.d */, Mips::SUBSUU_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6762             :   { 8713 /* subsuu_s.h */, Mips::SUBSUU_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6763             :   { 8724 /* subsuu_s.w */, Mips::SUBSUU_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6764             :   { 8735 /* subu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6765             :   { 8735 /* subu */, Mips::SUBu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6766             :   { 8735 /* subu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6767             :   { 8735 /* subu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1, 0, { MCK_GPR32AsmReg, MCK_InvNum }, },
    6768             :   { 8735 /* subu */, Mips::SubuRxRyRz16, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_CPU16Regs }, },
    6769             :   { 8735 /* subu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6770             :   { 8735 /* subu */, Mips::SUBu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6771             :   { 8735 /* subu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6772             :   { 8735 /* subu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_InvNum }, },
    6773             :   { 8740 /* subu.ph */, Mips::SUBU_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6774             :   { 8740 /* subu.ph */, Mips::SUBU_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6775             :   { 8748 /* subu.qb */, Mips::SUBU_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6776             :   { 8748 /* subu.qb */, Mips::SUBU_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6777             :   { 8756 /* subu16 */, Mips::SUBU16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
    6778             :   { 8756 /* subu16 */, Mips::SUBU16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, Feature_HasMicroMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
    6779             :   { 8763 /* subu_s.ph */, Mips::SUBU_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6780             :   { 8763 /* subu_s.ph */, Mips::SUBU_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6781             :   { 8773 /* subu_s.qb */, Mips::SUBU_S_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6782             :   { 8773 /* subu_s.qb */, Mips::SUBU_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6783             :   { 8783 /* subuh.qb */, Mips::SUBUH_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6784             :   { 8783 /* subuh.qb */, Mips::SUBUH_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6785             :   { 8792 /* subuh_r.qb */, Mips::SUBUH_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6786             :   { 8792 /* subuh_r.qb */, Mips::SUBUH_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
    6787             :   { 8803 /* subv.b */, Mips::SUBV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6788             :   { 8810 /* subv.d */, Mips::SUBV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6789             :   { 8817 /* subv.h */, Mips::SUBV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6790             :   { 8824 /* subv.w */, Mips::SUBV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
    6791             :   { 8831 /* subvi.b */, Mips::SUBVI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    6792             :   { 8839 /* subvi.d */, Mips::SUBVI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    6793             :   { 8847 /* subvi.h */, Mips::SUBVI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    6794             :   { 8855 /* subvi.w */, Mips::SUBVI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
    6795             :   { 8863 /* suxc1 */, Mips::SUXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
    6796             :   { 8863 /* suxc1 */, Mips::SUXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
    6797             :   { 8869 /* sw */, Mips::SWSP_MM, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, },
    6798             :   { 8869 /* sw */, Mips::SWSP_MMR6, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, },
    6799             :   { 8869 /* sw */, Mips::SW, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
    6800             :   { 8869 /* sw */, Mips::SW_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
    6801             :   { 8869 /* sw */, Mips::SW_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
    6802             :   { 8869 /* sw */, Mips::SwRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_SImm16 }, },
    6803             :   { 8869 /* sw */, Mips::SwRxSpImmX16, Convert__Reg1_0__Reg1_1__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, },
    6804             :   { 8872 /* sw16 */, Mips::SW16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_InMicroMips, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
    6805             :   { 8872 /* sw16 */, Mips::SW16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_HasMicroMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
    6806             :   { 8877 /* swc1 */, Mips::SWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, },
    6807             :   { 8877 /* swc1 */, Mips::SWC1_MM, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, },
    6808             :   { 8882 /* swc2 */, Mips::SWC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
    6809             :   { 8882 /* swc2 */, Mips::SWC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
    6810             :   { 8882 /* swc2 */, Mips::SWC2, Convert__COP2AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16 }, },
    6811             :   { 8887 /* swc3 */, Mips::SWC3, Convert__COP3AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
    6812             :   { 8892 /* swe */, Mips::SWE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    6813             :   { 8892 /* swe */, Mips::SWE_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    6814             :   { 8892 /* swe */, Mips::SWE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    6815             :   { 8896 /* swl */, Mips::SWL, Convert__GPR32AsmReg1_0__Mem2_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
    6816             :   { 8896 /* swl */, Mips::SWL_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
    6817             :   { 8900 /* swle */, Mips::SWLE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    6818             :   { 8900 /* swle */, Mips::SWLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    6819             :   { 8905 /* swm */, Mips::SWM_MM, Convert__RegList1_0__Mem2_1, Feature_InMicroMips, { MCK_RegList, MCK_Mem }, },
    6820             :   { 8909 /* swm16 */, Mips::SWM16_MM, Convert__RegList161_0__MemOffsetUimm42_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, },
    6821             :   { 8909 /* swm16 */, Mips::SWM16_MMR6, Convert__RegList161_0__MemOffsetUimm42_1, Feature_HasMicroMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, },
    6822             :   { 8915 /* swm32 */, Mips::SWM32_MM, Convert__RegList1_0__Mem2_1, Feature_InMicroMips, { MCK_RegList, MCK_Mem }, },
    6823             :   { 8921 /* swp */, Mips::SWP_MMR6, Convert__RegPair2_0__MemOffsetSimm122_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_RegPair, MCK_MemOffsetSimm12 }, },
    6824             :   { 8921 /* swp */, Mips::SWP_MM, Convert__RegPair2_0__MemOffsetSimm122_1, Feature_InMicroMips, { MCK_RegPair, MCK_MemOffsetSimm12 }, },
    6825             :   { 8925 /* swr */, Mips::SWR, Convert__GPR32AsmReg1_0__Mem2_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
    6826             :   { 8925 /* swr */, Mips::SWR_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
    6827             :   { 8929 /* swre */, Mips::SWRE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    6828             :   { 8929 /* swre */, Mips::SWRE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
    6829             :   { 8934 /* swxc1 */, Mips::SWXC1, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
    6830             :   { 8940 /* sync */, Mips::SYNC, Convert__imm_95_0, Feature_HasMips2, {  }, },
    6831             :   { 8940 /