LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/Mips - MipsGenFastISel.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 144 1764 8.2 %
Date: 2018-05-20 00:06:23 Functions: 31 291 10.7 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* "Fast" Instruction Selector for the Mips target                            *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : 
      10             : // FastEmit Immediate Predicate functions.
      11             : static bool Predicate_immZExt5(int64_t Imm) {
      12           7 : return Imm == (Imm & 0x1f);
      13             : }
      14             : static bool Predicate_immZExt6(int64_t Imm) {
      15           7 : return Imm == (Imm & 0x3f);
      16             : }
      17             : static bool Predicate_immSExt6(int64_t Imm) {
      18             : return isInt<6>(Imm);
      19             : }
      20             : static bool Predicate_immZExt4Ptr(int64_t Imm) {
      21             : return isUInt<4>(Imm);
      22             : }
      23             : static bool Predicate_immZExt3Ptr(int64_t Imm) {
      24             : return isUInt<3>(Imm);
      25             : }
      26             : static bool Predicate_immZExt2Ptr(int64_t Imm) {
      27             : return isUInt<2>(Imm);
      28             : }
      29             : static bool Predicate_immZExt1Ptr(int64_t Imm) {
      30             : return isUInt<1>(Imm);
      31             : }
      32             : static bool Predicate_immZExt4(int64_t Imm) {
      33             : return isUInt<4>(Imm);
      34             : }
      35             : static bool Predicate_immZExt3(int64_t Imm) {
      36             : return isUInt<3>(Imm);
      37             : }
      38             : static bool Predicate_immZExt2(int64_t Imm) {
      39             : return isUInt<2>(Imm);
      40             : }
      41             : static bool Predicate_immZExt1(int64_t Imm) {
      42             : return isUInt<1>(Imm);
      43             : }
      44             : static bool Predicate_immZExt8(int64_t Imm) {
      45             : return isUInt<8>(Imm);
      46             : }
      47             : static bool Predicate_immSExtAddiur2(int64_t Imm) {
      48          13 : return Imm == 1 || Imm == -1 ||
      49           6 :                                            ((Imm % 4 == 0) &&
      50           6 :                                             Imm < 28 && Imm > 0);
      51             : }
      52             : static bool Predicate_immSExtAddius5(int64_t Imm) {
      53           7 : return Imm >= -8 && Imm <= 7;
      54             : }
      55           7 : static bool Predicate_immZExtAndi16(int64_t Imm) {
      56          13 : return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
      57           6 :             Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
      58          13 :             Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
      59             : }
      60             : static bool Predicate_immZExt2Shift(int64_t Imm) {
      61           7 : return Imm >= 1 && Imm <= 8;
      62             : }
      63             : 
      64             : 
      65             : // FastEmit functions for ISD::BITCAST.
      66             : 
      67           0 : unsigned fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      68           0 :   if (RetVT.SimpleTy != MVT::f32)
      69             :     return 0;
      70           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
      71           0 :     return fastEmitInst_r(Mips::MTC1_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill);
      72             :   }
      73           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
      74           0 :     return fastEmitInst_r(Mips::MTC1_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
      75             :   }
      76           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
      77           0 :     return fastEmitInst_r(Mips::MTC1, &Mips::FGR32RegClass, Op0, Op0IsKill);
      78             :   }
      79             :   return 0;
      80             : }
      81             : 
      82           0 : unsigned fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      83           0 :   if (RetVT.SimpleTy != MVT::f64)
      84             :     return 0;
      85           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
      86           0 :     return fastEmitInst_r(Mips::DMTC1, &Mips::FGR64RegClass, Op0, Op0IsKill);
      87             :   }
      88             :   return 0;
      89             : }
      90             : 
      91           0 : unsigned fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      92           0 :   if (RetVT.SimpleTy != MVT::i32)
      93             :     return 0;
      94           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
      95           0 :     return fastEmitInst_r(Mips::MFC1_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
      96             :   }
      97           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
      98           0 :     return fastEmitInst_r(Mips::MFC1_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
      99             :   }
     100           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
     101           0 :     return fastEmitInst_r(Mips::MFC1, &Mips::GPR32RegClass, Op0, Op0IsKill);
     102             :   }
     103             :   return 0;
     104             : }
     105             : 
     106           0 : unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     107           0 :   if (RetVT.SimpleTy != MVT::i64)
     108             :     return 0;
     109           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
     110           0 :     return fastEmitInst_r(Mips::DMFC1, &Mips::GPR64RegClass, Op0, Op0IsKill);
     111             :   }
     112             :   return 0;
     113             : }
     114             : 
     115           0 : unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     116           0 :   switch (VT.SimpleTy) {
     117           0 :   case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0, Op0IsKill);
     118           0 :   case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0, Op0IsKill);
     119           0 :   case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0, Op0IsKill);
     120           0 :   case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0, Op0IsKill);
     121             :   default: return 0;
     122             :   }
     123             : }
     124             : 
     125             : // FastEmit functions for ISD::BRIND.
     126             : 
     127           0 : unsigned fastEmit_ISD_BRIND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     128           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     129             :     return 0;
     130           0 :   if ((Subtarget->inMips16Mode())) {
     131           0 :     return fastEmitInst_r(Mips::JrcRx16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill);
     132             :   }
     133           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
     134           0 :     return fastEmitInst_r(Mips::PseudoIndirectBranch_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
     135             :   }
     136           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
     137           0 :     return fastEmitInst_r(Mips::PseudoIndirectBranch_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
     138             :   }
     139           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
     140           0 :     return fastEmitInst_r(Mips::PseudoIndrectHazardBranchR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
     141             :   }
     142           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
     143           0 :     return fastEmitInst_r(Mips::PseudoIndirectBranchR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
     144             :   }
     145           0 :   if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
     146           0 :     return fastEmitInst_r(Mips::PseudoIndirectHazardBranch, &Mips::GPR32RegClass, Op0, Op0IsKill);
     147             :   }
     148           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
     149           0 :     return fastEmitInst_r(Mips::PseudoIndirectBranch, &Mips::GPR32RegClass, Op0, Op0IsKill);
     150             :   }
     151             :   return 0;
     152             : }
     153             : 
     154           0 : unsigned fastEmit_ISD_BRIND_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     155           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     156             :     return 0;
     157           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
     158           0 :     return fastEmitInst_r(Mips::PseudoIndrectHazardBranch64R6, &Mips::GPR64RegClass, Op0, Op0IsKill);
     159             :   }
     160           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
     161           0 :     return fastEmitInst_r(Mips::PseudoIndirectBranch64R6, &Mips::GPR64RegClass, Op0, Op0IsKill);
     162             :   }
     163           0 :   if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
     164           0 :     return fastEmitInst_r(Mips::PseudoIndirectHazardBranch64, &Mips::GPR64RegClass, Op0, Op0IsKill);
     165             :   }
     166           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
     167           0 :     return fastEmitInst_r(Mips::PseudoIndirectBranch64, &Mips::GPR64RegClass, Op0, Op0IsKill);
     168             :   }
     169             :   return 0;
     170             : }
     171             : 
     172           0 : unsigned fastEmit_ISD_BRIND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     173           0 :   switch (VT.SimpleTy) {
     174           0 :   case MVT::i32: return fastEmit_ISD_BRIND_MVT_i32_r(RetVT, Op0, Op0IsKill);
     175           0 :   case MVT::i64: return fastEmit_ISD_BRIND_MVT_i64_r(RetVT, Op0, Op0IsKill);
     176             :   default: return 0;
     177             :   }
     178             : }
     179             : 
     180             : // FastEmit functions for ISD::CTLZ.
     181             : 
     182           0 : unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     183           0 :   if (RetVT.SimpleTy != MVT::i32)
     184             :     return 0;
     185           0 :   if ((Subtarget->inMicroMipsMode())) {
     186           0 :     return fastEmitInst_r(Mips::CLZ_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
     187             :   }
     188           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding())) {
     189           0 :     return fastEmitInst_r(Mips::CLZ_R6, &Mips::GPR32RegClass, Op0, Op0IsKill);
     190             :   }
     191           0 :   if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
     192           0 :     return fastEmitInst_r(Mips::CLZ, &Mips::GPR32RegClass, Op0, Op0IsKill);
     193             :   }
     194             :   return 0;
     195             : }
     196             : 
     197           0 : unsigned fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     198           0 :   if (RetVT.SimpleTy != MVT::i64)
     199             :     return 0;
     200           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
     201           0 :     return fastEmitInst_r(Mips::DCLZ_R6, &Mips::GPR64RegClass, Op0, Op0IsKill);
     202             :   }
     203           0 :   if ((Subtarget->hasMips64()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips64r6())) {
     204           0 :     return fastEmitInst_r(Mips::DCLZ, &Mips::GPR64RegClass, Op0, Op0IsKill);
     205             :   }
     206             :   return 0;
     207             : }
     208             : 
     209           0 : unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     210           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     211             :     return 0;
     212           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     213           0 :     return fastEmitInst_r(Mips::NLZC_B, &Mips::MSA128BRegClass, Op0, Op0IsKill);
     214             :   }
     215             :   return 0;
     216             : }
     217             : 
     218           0 : unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     219           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     220             :     return 0;
     221           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     222           0 :     return fastEmitInst_r(Mips::NLZC_H, &Mips::MSA128HRegClass, Op0, Op0IsKill);
     223             :   }
     224             :   return 0;
     225             : }
     226             : 
     227           0 : unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     228           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     229             :     return 0;
     230           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     231           0 :     return fastEmitInst_r(Mips::NLZC_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     232             :   }
     233             :   return 0;
     234             : }
     235             : 
     236           0 : unsigned fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     237           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     238             :     return 0;
     239           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     240           0 :     return fastEmitInst_r(Mips::NLZC_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     241             :   }
     242             :   return 0;
     243             : }
     244             : 
     245           0 : unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     246           0 :   switch (VT.SimpleTy) {
     247           0 :   case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
     248           0 :   case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0, Op0IsKill);
     249           0 :   case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     250           0 :   case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     251           0 :   case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     252           0 :   case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     253             :   default: return 0;
     254             :   }
     255             : }
     256             : 
     257             : // FastEmit functions for ISD::CTPOP.
     258             : 
     259             : unsigned fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     260           0 :   if (RetVT.SimpleTy != MVT::i32)
     261             :     return 0;
     262           0 :   if ((Subtarget->hasCnMips())) {
     263           0 :     return fastEmitInst_r(Mips::POP, &Mips::GPR32RegClass, Op0, Op0IsKill);
     264             :   }
     265             :   return 0;
     266             : }
     267             : 
     268             : unsigned fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     269           0 :   if (RetVT.SimpleTy != MVT::i64)
     270             :     return 0;
     271           0 :   if ((Subtarget->hasCnMips())) {
     272           0 :     return fastEmitInst_r(Mips::DPOP, &Mips::GPR64RegClass, Op0, Op0IsKill);
     273             :   }
     274             :   return 0;
     275             : }
     276             : 
     277           0 : unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     278           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     279             :     return 0;
     280           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     281           0 :     return fastEmitInst_r(Mips::PCNT_B, &Mips::MSA128BRegClass, Op0, Op0IsKill);
     282             :   }
     283             :   return 0;
     284             : }
     285             : 
     286           0 : unsigned fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     287           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     288             :     return 0;
     289           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     290           0 :     return fastEmitInst_r(Mips::PCNT_H, &Mips::MSA128HRegClass, Op0, Op0IsKill);
     291             :   }
     292             :   return 0;
     293             : }
     294             : 
     295           0 : unsigned fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     296           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     297             :     return 0;
     298           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     299           0 :     return fastEmitInst_r(Mips::PCNT_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     300             :   }
     301             :   return 0;
     302             : }
     303             : 
     304           0 : unsigned fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     305           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     306             :     return 0;
     307           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     308           0 :     return fastEmitInst_r(Mips::PCNT_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     309             :   }
     310             :   return 0;
     311             : }
     312             : 
     313           0 : unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     314           0 :   switch (VT.SimpleTy) {
     315           0 :   case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0, Op0IsKill);
     316           0 :   case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0, Op0IsKill);
     317           0 :   case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     318           0 :   case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     319           0 :   case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     320           0 :   case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     321             :   default: return 0;
     322             :   }
     323             : }
     324             : 
     325             : // FastEmit functions for ISD::FABS.
     326             : 
     327           0 : unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     328           0 :   if (RetVT.SimpleTy != MVT::f32)
     329             :     return 0;
     330           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
     331           0 :     return fastEmitInst_r(Mips::FABS_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
     332             :   }
     333           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
     334           0 :     return fastEmitInst_r(Mips::FABS_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
     335             :   }
     336             :   return 0;
     337             : }
     338             : 
     339           0 : unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     340           0 :   if (RetVT.SimpleTy != MVT::f64)
     341             :     return 0;
     342           0 :   if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
     343           0 :     return fastEmitInst_r(Mips::FABS_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill);
     344             :   }
     345           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
     346           0 :     return fastEmitInst_r(Mips::FABS_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     347             :   }
     348           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
     349           0 :     return fastEmitInst_r(Mips::FABS_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
     350             :   }
     351           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
     352           0 :     return fastEmitInst_r(Mips::FABS_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     353             :   }
     354             :   return 0;
     355             : }
     356             : 
     357             : unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     358           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     359             :     return 0;
     360           0 :   if ((Subtarget->hasMSA())) {
     361           0 :     return fastEmitInst_r(Mips::FABS_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     362             :   }
     363             :   return 0;
     364             : }
     365             : 
     366             : unsigned fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     367           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     368             :     return 0;
     369           0 :   if ((Subtarget->hasMSA())) {
     370           0 :     return fastEmitInst_r(Mips::FABS_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     371             :   }
     372             :   return 0;
     373             : }
     374             : 
     375           0 : unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     376           0 :   switch (VT.SimpleTy) {
     377           0 :   case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill);
     378           0 :   case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0, Op0IsKill);
     379           0 :   case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     380           0 :   case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     381             :   default: return 0;
     382             :   }
     383             : }
     384             : 
     385             : // FastEmit functions for ISD::FEXP2.
     386             : 
     387             : unsigned fastEmit_ISD_FEXP2_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     388           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     389             :     return 0;
     390           0 :   if ((Subtarget->hasMSA())) {
     391           0 :     return fastEmitInst_r(Mips::FEXP2_W_1_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     392             :   }
     393             :   return 0;
     394             : }
     395             : 
     396             : unsigned fastEmit_ISD_FEXP2_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     397           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     398             :     return 0;
     399           0 :   if ((Subtarget->hasMSA())) {
     400           0 :     return fastEmitInst_r(Mips::FEXP2_D_1_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     401             :   }
     402             :   return 0;
     403             : }
     404             : 
     405           0 : unsigned fastEmit_ISD_FEXP2_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     406           0 :   switch (VT.SimpleTy) {
     407           0 :   case MVT::v4f32: return fastEmit_ISD_FEXP2_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     408           0 :   case MVT::v2f64: return fastEmit_ISD_FEXP2_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     409             :   default: return 0;
     410             :   }
     411             : }
     412             : 
     413             : // FastEmit functions for ISD::FLOG2.
     414             : 
     415           0 : unsigned fastEmit_ISD_FLOG2_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     416           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     417             :     return 0;
     418           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     419           0 :     return fastEmitInst_r(Mips::FLOG2_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     420             :   }
     421             :   return 0;
     422             : }
     423             : 
     424           0 : unsigned fastEmit_ISD_FLOG2_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     425           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     426             :     return 0;
     427           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     428           0 :     return fastEmitInst_r(Mips::FLOG2_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     429             :   }
     430             :   return 0;
     431             : }
     432             : 
     433           0 : unsigned fastEmit_ISD_FLOG2_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     434           0 :   switch (VT.SimpleTy) {
     435           0 :   case MVT::v4f32: return fastEmit_ISD_FLOG2_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     436           0 :   case MVT::v2f64: return fastEmit_ISD_FLOG2_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     437             :   default: return 0;
     438             :   }
     439             : }
     440             : 
     441             : // FastEmit functions for ISD::FNEG.
     442             : 
     443           0 : unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     444           0 :   if (RetVT.SimpleTy != MVT::f32)
     445             :     return 0;
     446           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
     447           0 :     return fastEmitInst_r(Mips::FNEG_S_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill);
     448             :   }
     449           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
     450           0 :     return fastEmitInst_r(Mips::FNEG_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
     451             :   }
     452           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
     453           0 :     return fastEmitInst_r(Mips::FNEG_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
     454             :   }
     455             :   return 0;
     456             : }
     457             : 
     458           0 : unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     459           0 :   if (RetVT.SimpleTy != MVT::f64)
     460             :     return 0;
     461           0 :   if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
     462           0 :     return fastEmitInst_r(Mips::FNEG_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill);
     463             :   }
     464           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
     465           0 :     return fastEmitInst_r(Mips::FNEG_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     466             :   }
     467           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
     468           0 :     return fastEmitInst_r(Mips::FNEG_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
     469             :   }
     470           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
     471           0 :     return fastEmitInst_r(Mips::FNEG_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     472             :   }
     473             :   return 0;
     474             : }
     475             : 
     476           0 : unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     477           0 :   switch (VT.SimpleTy) {
     478           0 :   case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill);
     479           0 :   case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0, Op0IsKill);
     480             :   default: return 0;
     481             :   }
     482             : }
     483             : 
     484             : // FastEmit functions for ISD::FP_EXTEND.
     485             : 
     486             : unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
     487           0 :   if ((Subtarget->hasMSA())) {
     488           0 :     return fastEmitInst_r(Mips::MSA_FP_EXTEND_W_PSEUDO, &Mips::FGR32RegClass, Op0, Op0IsKill);
     489             :   }
     490             :   return 0;
     491             : }
     492             : 
     493             : unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
     494           0 :   if ((Subtarget->hasMSA())) {
     495           0 :     return fastEmitInst_r(Mips::MSA_FP_EXTEND_D_PSEUDO, &Mips::FGR64RegClass, Op0, Op0IsKill);
     496             :   }
     497             :   return 0;
     498             : }
     499             : 
     500           0 : unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     501           0 : switch (RetVT.SimpleTy) {
     502           0 :   case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(Op0, Op0IsKill);
     503           0 :   case MVT::f64: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(Op0, Op0IsKill);
     504             :   default: return 0;
     505             : }
     506             : }
     507             : 
     508           0 : unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     509           0 :   if (RetVT.SimpleTy != MVT::f64)
     510             :     return 0;
     511           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit())) {
     512           0 :     return fastEmitInst_r(Mips::CVT_D32_S_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     513             :   }
     514           0 :   if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())) {
     515           0 :     return fastEmitInst_r(Mips::CVT_D64_S_MM, &Mips::FGR64RegClass, Op0, Op0IsKill);
     516             :   }
     517           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
     518           0 :     return fastEmitInst_r(Mips::CVT_D64_S, &Mips::FGR64RegClass, Op0, Op0IsKill);
     519             :   }
     520           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
     521           0 :     return fastEmitInst_r(Mips::CVT_D32_S, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     522             :   }
     523             :   return 0;
     524             : }
     525             : 
     526           0 : unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     527           0 :   switch (VT.SimpleTy) {
     528           0 :   case MVT::f16: return fastEmit_ISD_FP_EXTEND_MVT_f16_r(RetVT, Op0, Op0IsKill);
     529           0 :   case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0, Op0IsKill);
     530             :   default: return 0;
     531             :   }
     532             : }
     533             : 
     534             : // FastEmit functions for ISD::FP_ROUND.
     535             : 
     536             : unsigned fastEmit_ISD_FP_ROUND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     537           0 :   if (RetVT.SimpleTy != MVT::f16)
     538             :     return 0;
     539           0 :   if ((Subtarget->hasMSA())) {
     540           0 :     return fastEmitInst_r(Mips::MSA_FP_ROUND_W_PSEUDO, &Mips::MSA128F16RegClass, Op0, Op0IsKill);
     541             :   }
     542             :   return 0;
     543             : }
     544             : 
     545             : unsigned fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(unsigned Op0, bool Op0IsKill) {
     546           0 :   if ((Subtarget->hasMSA())) {
     547           0 :     return fastEmitInst_r(Mips::MSA_FP_ROUND_D_PSEUDO, &Mips::MSA128F16RegClass, Op0, Op0IsKill);
     548             :   }
     549             :   return 0;
     550             : }
     551             : 
     552           0 : unsigned fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
     553           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit())) {
     554           0 :     return fastEmitInst_r(Mips::CVT_S_D32_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
     555             :   }
     556           0 :   if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())) {
     557           0 :     return fastEmitInst_r(Mips::CVT_S_D64_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
     558             :   }
     559           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
     560           0 :     return fastEmitInst_r(Mips::CVT_S_D64, &Mips::FGR32RegClass, Op0, Op0IsKill);
     561             :   }
     562           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
     563           0 :     return fastEmitInst_r(Mips::CVT_S_D32, &Mips::FGR32RegClass, Op0, Op0IsKill);
     564             :   }
     565             :   return 0;
     566             : }
     567             : 
     568           0 : unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     569           0 : switch (RetVT.SimpleTy) {
     570           0 :   case MVT::f16: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(Op0, Op0IsKill);
     571           0 :   case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(Op0, Op0IsKill);
     572             :   default: return 0;
     573             : }
     574             : }
     575             : 
     576           0 : unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     577           0 :   switch (VT.SimpleTy) {
     578           0 :   case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f32_r(RetVT, Op0, Op0IsKill);
     579           0 :   case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
     580             :   default: return 0;
     581             :   }
     582             : }
     583             : 
     584             : // FastEmit functions for ISD::FP_TO_SINT.
     585             : 
     586           0 : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     587           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     588             :     return 0;
     589           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     590           0 :     return fastEmitInst_r(Mips::FTRUNC_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     591             :   }
     592             :   return 0;
     593             : }
     594             : 
     595           0 : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     596           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     597             :     return 0;
     598           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     599           0 :     return fastEmitInst_r(Mips::FTRUNC_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     600             :   }
     601             :   return 0;
     602             : }
     603             : 
     604           4 : unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     605           4 :   switch (VT.SimpleTy) {
     606           0 :   case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     607           0 :   case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     608             :   default: return 0;
     609             :   }
     610             : }
     611             : 
     612             : // FastEmit functions for ISD::FP_TO_UINT.
     613             : 
     614           0 : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     615           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     616             :     return 0;
     617           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     618           0 :     return fastEmitInst_r(Mips::FTRUNC_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     619             :   }
     620             :   return 0;
     621             : }
     622             : 
     623           0 : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     624           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     625             :     return 0;
     626           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     627           0 :     return fastEmitInst_r(Mips::FTRUNC_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     628             :   }
     629             :   return 0;
     630             : }
     631             : 
     632           0 : unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     633           0 :   switch (VT.SimpleTy) {
     634           0 :   case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     635           0 :   case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     636             :   default: return 0;
     637             :   }
     638             : }
     639             : 
     640             : // FastEmit functions for ISD::FRINT.
     641             : 
     642           0 : unsigned fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     643           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     644             :     return 0;
     645           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     646           0 :     return fastEmitInst_r(Mips::FRINT_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     647             :   }
     648             :   return 0;
     649             : }
     650             : 
     651           0 : unsigned fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     652           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     653             :     return 0;
     654           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     655           0 :     return fastEmitInst_r(Mips::FRINT_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     656             :   }
     657             :   return 0;
     658             : }
     659             : 
     660           0 : unsigned fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     661           0 :   switch (VT.SimpleTy) {
     662           0 :   case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     663           0 :   case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     664             :   default: return 0;
     665             :   }
     666             : }
     667             : 
     668             : // FastEmit functions for ISD::FSQRT.
     669             : 
     670           0 : unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     671           0 :   if (RetVT.SimpleTy != MVT::f32)
     672             :     return 0;
     673           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
     674           0 :     return fastEmitInst_r(Mips::FSQRT_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
     675             :   }
     676           0 :   if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
     677           0 :     return fastEmitInst_r(Mips::FSQRT_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
     678             :   }
     679             :   return 0;
     680             : }
     681             : 
     682           0 : unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     683           0 :   if (RetVT.SimpleTy != MVT::f64)
     684             :     return 0;
     685           0 :   if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
     686           0 :     return fastEmitInst_r(Mips::FSQRT_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill);
     687             :   }
     688           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
     689           0 :     return fastEmitInst_r(Mips::FSQRT_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     690             :   }
     691           0 :   if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
     692           0 :     return fastEmitInst_r(Mips::FSQRT_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
     693             :   }
     694           0 :   if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
     695           0 :     return fastEmitInst_r(Mips::FSQRT_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     696             :   }
     697             :   return 0;
     698             : }
     699             : 
     700           0 : unsigned fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     701           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     702             :     return 0;
     703           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     704           0 :     return fastEmitInst_r(Mips::FSQRT_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     705             :   }
     706             :   return 0;
     707             : }
     708             : 
     709           0 : unsigned fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     710           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     711             :     return 0;
     712           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     713           0 :     return fastEmitInst_r(Mips::FSQRT_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     714             :   }
     715             :   return 0;
     716             : }
     717             : 
     718           0 : unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     719           0 :   switch (VT.SimpleTy) {
     720           0 :   case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill);
     721           0 :   case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0, Op0IsKill);
     722           0 :   case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     723           0 :   case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     724             :   default: return 0;
     725             :   }
     726             : }
     727             : 
     728             : // FastEmit functions for ISD::SIGN_EXTEND.
     729             : 
     730             : unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     731           0 :   if (RetVT.SimpleTy != MVT::i64)
     732             :     return 0;
     733           0 :   if ((Subtarget->hasStandardEncoding())) {
     734           0 :     return fastEmitInst_r(Mips::SLL64_32, &Mips::GPR64RegClass, Op0, Op0IsKill);
     735             :   }
     736             :   return 0;
     737             : }
     738             : 
     739           0 : unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     740           0 :   switch (VT.SimpleTy) {
     741           0 :   case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0, Op0IsKill);
     742             :   default: return 0;
     743             :   }
     744             : }
     745             : 
     746             : // FastEmit functions for ISD::SINT_TO_FP.
     747             : 
     748             : unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
     749           0 :   if ((Subtarget->hasStandardEncoding())) {
     750           0 :     return fastEmitInst_r(Mips::PseudoCVT_S_W, &Mips::FGR32RegClass, Op0, Op0IsKill);
     751             :   }
     752             :   return 0;
     753             : }
     754             : 
     755           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
     756           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
     757           0 :     return fastEmitInst_r(Mips::PseudoCVT_D64_W, &Mips::FGR64RegClass, Op0, Op0IsKill);
     758             :   }
     759           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit())) {
     760           0 :     return fastEmitInst_r(Mips::PseudoCVT_D32_W, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     761             :   }
     762             :   return 0;
     763             : }
     764             : 
     765           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     766           0 : switch (RetVT.SimpleTy) {
     767           0 :   case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0, Op0IsKill);
     768           0 :   case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0, Op0IsKill);
     769             :   default: return 0;
     770             : }
     771             : }
     772             : 
     773           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     774           0 :   if (RetVT.SimpleTy != MVT::f64)
     775             :     return 0;
     776           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
     777           0 :     return fastEmitInst_r(Mips::PseudoCVT_D64_L, &Mips::FGR64RegClass, Op0, Op0IsKill);
     778             :   }
     779             :   return 0;
     780             : }
     781             : 
     782           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     783           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     784             :     return 0;
     785           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     786           0 :     return fastEmitInst_r(Mips::FFINT_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     787             :   }
     788             :   return 0;
     789             : }
     790             : 
     791           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     792           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     793             :     return 0;
     794           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     795           0 :     return fastEmitInst_r(Mips::FFINT_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     796             :   }
     797             :   return 0;
     798             : }
     799             : 
     800           0 : unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     801           0 :   switch (VT.SimpleTy) {
     802           0 :   case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0, Op0IsKill);
     803           0 :   case MVT::i64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_r(RetVT, Op0, Op0IsKill);
     804           0 :   case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     805           0 :   case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     806             :   default: return 0;
     807             :   }
     808             : }
     809             : 
     810             : // FastEmit functions for ISD::UINT_TO_FP.
     811             : 
     812           0 : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     813           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     814             :     return 0;
     815           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     816           0 :     return fastEmitInst_r(Mips::FFINT_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     817             :   }
     818             :   return 0;
     819             : }
     820             : 
     821           0 : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     822           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     823             :     return 0;
     824           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     825           0 :     return fastEmitInst_r(Mips::FFINT_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     826             :   }
     827             :   return 0;
     828             : }
     829             : 
     830           0 : unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     831           0 :   switch (VT.SimpleTy) {
     832           0 :   case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     833           0 :   case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     834             :   default: return 0;
     835             :   }
     836             : }
     837             : 
     838             : // FastEmit functions for MipsISD::JmpLink.
     839             : 
     840           0 : unsigned fastEmit_MipsISD_JmpLink_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     841           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     842             :     return 0;
     843           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
     844           0 :     return fastEmitInst_r(Mips::JALRC16_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
     845             :   }
     846           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
     847           0 :     return fastEmitInst_r(Mips::JALR16_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
     848             :   }
     849           0 :   if ((Subtarget->inMips16Mode())) {
     850           0 :     return fastEmitInst_r(Mips::JumpLinkReg16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill);
     851             :   }
     852           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (Subtarget->useIndirectJumpsHazard())) {
     853           0 :     return fastEmitInst_r(Mips::JALRHBPseudo, &Mips::GPR32RegClass, Op0, Op0IsKill);
     854             :   }
     855           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode())) {
     856           0 :     return fastEmitInst_r(Mips::JALRPseudo, &Mips::GPR32RegClass, Op0, Op0IsKill);
     857             :   }
     858             :   return 0;
     859             : }
     860             : 
     861           0 : unsigned fastEmit_MipsISD_JmpLink_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     862           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     863             :     return 0;
     864           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->useIndirectJumpsHazard())) {
     865           0 :     return fastEmitInst_r(Mips::JALRHB64Pseudo, &Mips::GPR64RegClass, Op0, Op0IsKill);
     866             :   }
     867           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard())) {
     868           0 :     return fastEmitInst_r(Mips::JALR64Pseudo, &Mips::GPR64RegClass, Op0, Op0IsKill);
     869             :   }
     870             :   return 0;
     871             : }
     872             : 
     873           0 : unsigned fastEmit_MipsISD_JmpLink_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     874           0 :   switch (VT.SimpleTy) {
     875           0 :   case MVT::i32: return fastEmit_MipsISD_JmpLink_MVT_i32_r(RetVT, Op0, Op0IsKill);
     876           0 :   case MVT::i64: return fastEmit_MipsISD_JmpLink_MVT_i64_r(RetVT, Op0, Op0IsKill);
     877             :   default: return 0;
     878             :   }
     879             : }
     880             : 
     881             : // FastEmit functions for MipsISD::MFHI.
     882             : 
     883           0 : unsigned fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(unsigned Op0, bool Op0IsKill) {
     884           0 :   if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
     885           0 :     return fastEmitInst_r(Mips::MFHI_DSP_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
     886             :   }
     887           0 :   if ((Subtarget->hasDSP())) {
     888           0 :     return fastEmitInst_r(Mips::MFHI_DSP, &Mips::GPR32RegClass, Op0, Op0IsKill);
     889             :   }
     890           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
     891           0 :     return fastEmitInst_r(Mips::PseudoMFHI, &Mips::GPR32RegClass, Op0, Op0IsKill);
     892             :   }
     893             :   return 0;
     894             : }
     895             : 
     896           0 : unsigned fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(unsigned Op0, bool Op0IsKill) {
     897           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
     898           0 :     return fastEmitInst_r(Mips::PseudoMFHI64, &Mips::GPR64RegClass, Op0, Op0IsKill);
     899             :   }
     900             :   return 0;
     901             : }
     902             : 
     903           0 : unsigned fastEmit_MipsISD_MFHI_MVT_Untyped_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     904           0 : switch (RetVT.SimpleTy) {
     905           0 :   case MVT::i32: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(Op0, Op0IsKill);
     906           0 :   case MVT::i64: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(Op0, Op0IsKill);
     907             :   default: return 0;
     908             : }
     909             : }
     910             : 
     911             : unsigned fastEmit_MipsISD_MFHI_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     912           0 :   switch (VT.SimpleTy) {
     913           0 :   case MVT::Untyped: return fastEmit_MipsISD_MFHI_MVT_Untyped_r(RetVT, Op0, Op0IsKill);
     914             :   default: return 0;
     915             :   }
     916             : }
     917             : 
     918             : // FastEmit functions for MipsISD::MFLO.
     919             : 
     920           0 : unsigned fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(unsigned Op0, bool Op0IsKill) {
     921           0 :   if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
     922           0 :     return fastEmitInst_r(Mips::MFLO_DSP_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
     923             :   }
     924           0 :   if ((Subtarget->hasDSP())) {
     925           0 :     return fastEmitInst_r(Mips::MFLO_DSP, &Mips::GPR32RegClass, Op0, Op0IsKill);
     926             :   }
     927           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
     928           0 :     return fastEmitInst_r(Mips::PseudoMFLO, &Mips::GPR32RegClass, Op0, Op0IsKill);
     929             :   }
     930             :   return 0;
     931             : }
     932             : 
     933           0 : unsigned fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(unsigned Op0, bool Op0IsKill) {
     934           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
     935           0 :     return fastEmitInst_r(Mips::PseudoMFLO64, &Mips::GPR64RegClass, Op0, Op0IsKill);
     936             :   }
     937             :   return 0;
     938             : }
     939             : 
     940           0 : unsigned fastEmit_MipsISD_MFLO_MVT_Untyped_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     941           0 : switch (RetVT.SimpleTy) {
     942           0 :   case MVT::i32: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(Op0, Op0IsKill);
     943           0 :   case MVT::i64: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(Op0, Op0IsKill);
     944             :   default: return 0;
     945             : }
     946             : }
     947             : 
     948             : unsigned fastEmit_MipsISD_MFLO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     949           0 :   switch (VT.SimpleTy) {
     950           0 :   case MVT::Untyped: return fastEmit_MipsISD_MFLO_MVT_Untyped_r(RetVT, Op0, Op0IsKill);
     951             :   default: return 0;
     952             :   }
     953             : }
     954             : 
     955             : // FastEmit functions for MipsISD::MTC1_D64.
     956             : 
     957           0 : unsigned fastEmit_MipsISD_MTC1_D64_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     958           0 :   if (RetVT.SimpleTy != MVT::f64)
     959             :     return 0;
     960           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
     961           0 :     return fastEmitInst_r(Mips::MTC1_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
     962             :   }
     963             :   return 0;
     964             : }
     965             : 
     966             : unsigned fastEmit_MipsISD_MTC1_D64_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     967           0 :   switch (VT.SimpleTy) {
     968           0 :   case MVT::i32: return fastEmit_MipsISD_MTC1_D64_MVT_i32_r(RetVT, Op0, Op0IsKill);
     969             :   default: return 0;
     970             :   }
     971             : }
     972             : 
     973             : // FastEmit functions for MipsISD::TailCall.
     974             : 
     975           0 : unsigned fastEmit_MipsISD_TailCall_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     976           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     977             :     return 0;
     978           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
     979           0 :     return fastEmitInst_r(Mips::TAILCALLREG_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
     980             :   }
     981           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
     982           0 :     return fastEmitInst_r(Mips::TAILCALLREG_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
     983             :   }
     984           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
     985           0 :     return fastEmitInst_r(Mips::TAILCALLHBR6REG, &Mips::GPR32RegClass, Op0, Op0IsKill);
     986             :   }
     987           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
     988           0 :     return fastEmitInst_r(Mips::TAILCALLR6REG, &Mips::GPR32RegClass, Op0, Op0IsKill);
     989             :   }
     990           0 :   if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
     991           0 :     return fastEmitInst_r(Mips::TAILCALLREGHB, &Mips::GPR32RegClass, Op0, Op0IsKill);
     992             :   }
     993           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
     994           0 :     return fastEmitInst_r(Mips::TAILCALLREG, &Mips::GPR32RegClass, Op0, Op0IsKill);
     995             :   }
     996             :   return 0;
     997             : }
     998             : 
     999           0 : unsigned fastEmit_MipsISD_TailCall_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1000           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    1001             :     return 0;
    1002           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
    1003           0 :     return fastEmitInst_r(Mips::TAILCALLHB64R6REG, &Mips::GPR64RegClass, Op0, Op0IsKill);
    1004             :   }
    1005           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
    1006           0 :     return fastEmitInst_r(Mips::TAILCALL64R6REG, &Mips::GPR64RegClass, Op0, Op0IsKill);
    1007             :   }
    1008           0 :   if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
    1009           0 :     return fastEmitInst_r(Mips::TAILCALLREGHB64, &Mips::GPR64RegClass, Op0, Op0IsKill);
    1010             :   }
    1011           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    1012           0 :     return fastEmitInst_r(Mips::TAILCALLREG64, &Mips::GPR64RegClass, Op0, Op0IsKill);
    1013             :   }
    1014             :   return 0;
    1015             : }
    1016             : 
    1017           0 : unsigned fastEmit_MipsISD_TailCall_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1018           0 :   switch (VT.SimpleTy) {
    1019           0 :   case MVT::i32: return fastEmit_MipsISD_TailCall_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1020           0 :   case MVT::i64: return fastEmit_MipsISD_TailCall_MVT_i64_r(RetVT, Op0, Op0IsKill);
    1021             :   default: return 0;
    1022             :   }
    1023             : }
    1024             : 
    1025             : // FastEmit functions for MipsISD::TruncIntFP.
    1026             : 
    1027             : unsigned fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
    1028           0 :   if ((Subtarget->hasStandardEncoding())) {
    1029           0 :     return fastEmitInst_r(Mips::TRUNC_W_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
    1030             :   }
    1031             :   return 0;
    1032             : }
    1033             : 
    1034           0 : unsigned fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
    1035           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
    1036           0 :     return fastEmitInst_r(Mips::TRUNC_L_S, &Mips::FGR64RegClass, Op0, Op0IsKill);
    1037             :   }
    1038             :   return 0;
    1039             : }
    1040             : 
    1041           0 : unsigned fastEmit_MipsISD_TruncIntFP_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1042           0 : switch (RetVT.SimpleTy) {
    1043           0 :   case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(Op0, Op0IsKill);
    1044           0 :   case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(Op0, Op0IsKill);
    1045             :   default: return 0;
    1046             : }
    1047             : }
    1048             : 
    1049           0 : unsigned fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
    1050           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
    1051           0 :     return fastEmitInst_r(Mips::TRUNC_W_D64, &Mips::FGR32RegClass, Op0, Op0IsKill);
    1052             :   }
    1053           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit())) {
    1054           0 :     return fastEmitInst_r(Mips::TRUNC_W_D32, &Mips::FGR32RegClass, Op0, Op0IsKill);
    1055             :   }
    1056             :   return 0;
    1057             : }
    1058             : 
    1059           0 : unsigned fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
    1060           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
    1061           0 :     return fastEmitInst_r(Mips::TRUNC_L_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
    1062             :   }
    1063             :   return 0;
    1064             : }
    1065             : 
    1066           0 : unsigned fastEmit_MipsISD_TruncIntFP_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1067           0 : switch (RetVT.SimpleTy) {
    1068           0 :   case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(Op0, Op0IsKill);
    1069           0 :   case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(Op0, Op0IsKill);
    1070             :   default: return 0;
    1071             : }
    1072             : }
    1073             : 
    1074           0 : unsigned fastEmit_MipsISD_TruncIntFP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1075           0 :   switch (VT.SimpleTy) {
    1076           0 :   case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1077           0 :   case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1078             :   default: return 0;
    1079             :   }
    1080             : }
    1081             : 
    1082             : // FastEmit functions for MipsISD::VALL_NONZERO.
    1083             : 
    1084             : unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1085           0 :   if (RetVT.SimpleTy != MVT::i32)
    1086             :     return 0;
    1087           0 :   return fastEmitInst_r(Mips::SNZ_B_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1088             : }
    1089             : 
    1090             : unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1091           0 :   if (RetVT.SimpleTy != MVT::i32)
    1092             :     return 0;
    1093           0 :   return fastEmitInst_r(Mips::SNZ_H_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1094             : }
    1095             : 
    1096             : unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1097           0 :   if (RetVT.SimpleTy != MVT::i32)
    1098             :     return 0;
    1099           0 :   return fastEmitInst_r(Mips::SNZ_W_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1100             : }
    1101             : 
    1102             : unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1103           0 :   if (RetVT.SimpleTy != MVT::i32)
    1104             :     return 0;
    1105           0 :   return fastEmitInst_r(Mips::SNZ_D_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1106             : }
    1107             : 
    1108           0 : unsigned fastEmit_MipsISD_VALL_NONZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1109           0 :   switch (VT.SimpleTy) {
    1110           0 :   case MVT::v16i8: return fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1111           0 :   case MVT::v8i16: return fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    1112           0 :   case MVT::v4i32: return fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    1113           0 :   case MVT::v2i64: return fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
    1114             :   default: return 0;
    1115             :   }
    1116             : }
    1117             : 
    1118             : // FastEmit functions for MipsISD::VALL_ZERO.
    1119             : 
    1120             : unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1121           0 :   if (RetVT.SimpleTy != MVT::i32)
    1122             :     return 0;
    1123           0 :   return fastEmitInst_r(Mips::SZ_B_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1124             : }
    1125             : 
    1126             : unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1127           0 :   if (RetVT.SimpleTy != MVT::i32)
    1128             :     return 0;
    1129           0 :   return fastEmitInst_r(Mips::SZ_H_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1130             : }
    1131             : 
    1132             : unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1133           0 :   if (RetVT.SimpleTy != MVT::i32)
    1134             :     return 0;
    1135           0 :   return fastEmitInst_r(Mips::SZ_W_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1136             : }
    1137             : 
    1138             : unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1139           0 :   if (RetVT.SimpleTy != MVT::i32)
    1140             :     return 0;
    1141           0 :   return fastEmitInst_r(Mips::SZ_D_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1142             : }
    1143             : 
    1144           0 : unsigned fastEmit_MipsISD_VALL_ZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1145           0 :   switch (VT.SimpleTy) {
    1146           0 :   case MVT::v16i8: return fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1147           0 :   case MVT::v8i16: return fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    1148           0 :   case MVT::v4i32: return fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    1149           0 :   case MVT::v2i64: return fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
    1150             :   default: return 0;
    1151             :   }
    1152             : }
    1153             : 
    1154             : // FastEmit functions for MipsISD::VANY_NONZERO.
    1155             : 
    1156             : unsigned fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1157           0 :   if (RetVT.SimpleTy != MVT::i32)
    1158             :     return 0;
    1159           0 :   return fastEmitInst_r(Mips::SNZ_V_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1160             : }
    1161             : 
    1162             : unsigned fastEmit_MipsISD_VANY_NONZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1163           0 :   switch (VT.SimpleTy) {
    1164           0 :   case MVT::v16i8: return fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1165             :   default: return 0;
    1166             :   }
    1167             : }
    1168             : 
    1169             : // FastEmit functions for MipsISD::VANY_ZERO.
    1170             : 
    1171             : unsigned fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1172           0 :   if (RetVT.SimpleTy != MVT::i32)
    1173             :     return 0;
    1174           0 :   return fastEmitInst_r(Mips::SZ_V_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1175             : }
    1176             : 
    1177             : unsigned fastEmit_MipsISD_VANY_ZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1178           0 :   switch (VT.SimpleTy) {
    1179           0 :   case MVT::v16i8: return fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1180             :   default: return 0;
    1181             :   }
    1182             : }
    1183             : 
    1184             : // Top-level FastEmit function.
    1185             : 
    1186           4 : unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill) override {
    1187           4 :   switch (Opcode) {
    1188           0 :   case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0, Op0IsKill);
    1189           0 :   case ISD::BRIND: return fastEmit_ISD_BRIND_r(VT, RetVT, Op0, Op0IsKill);
    1190           0 :   case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill);
    1191           0 :   case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill);
    1192           0 :   case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill);
    1193           0 :   case ISD::FEXP2: return fastEmit_ISD_FEXP2_r(VT, RetVT, Op0, Op0IsKill);
    1194           0 :   case ISD::FLOG2: return fastEmit_ISD_FLOG2_r(VT, RetVT, Op0, Op0IsKill);
    1195           0 :   case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill);
    1196           0 :   case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
    1197           0 :   case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill);
    1198           4 :   case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill);
    1199           0 :   case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill);
    1200           0 :   case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0, Op0IsKill);
    1201           0 :   case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill);
    1202           0 :   case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
    1203           0 :   case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill);
    1204           0 :   case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill);
    1205           0 :   case MipsISD::JmpLink: return fastEmit_MipsISD_JmpLink_r(VT, RetVT, Op0, Op0IsKill);
    1206           0 :   case MipsISD::MFHI: return fastEmit_MipsISD_MFHI_r(VT, RetVT, Op0, Op0IsKill);
    1207           0 :   case MipsISD::MFLO: return fastEmit_MipsISD_MFLO_r(VT, RetVT, Op0, Op0IsKill);
    1208           0 :   case MipsISD::MTC1_D64: return fastEmit_MipsISD_MTC1_D64_r(VT, RetVT, Op0, Op0IsKill);
    1209           0 :   case MipsISD::TailCall: return fastEmit_MipsISD_TailCall_r(VT, RetVT, Op0, Op0IsKill);
    1210           0 :   case MipsISD::TruncIntFP: return fastEmit_MipsISD_TruncIntFP_r(VT, RetVT, Op0, Op0IsKill);
    1211           0 :   case MipsISD::VALL_NONZERO: return fastEmit_MipsISD_VALL_NONZERO_r(VT, RetVT, Op0, Op0IsKill);
    1212           0 :   case MipsISD::VALL_ZERO: return fastEmit_MipsISD_VALL_ZERO_r(VT, RetVT, Op0, Op0IsKill);
    1213           0 :   case MipsISD::VANY_NONZERO: return fastEmit_MipsISD_VANY_NONZERO_r(VT, RetVT, Op0, Op0IsKill);
    1214           0 :   case MipsISD::VANY_ZERO: return fastEmit_MipsISD_VANY_ZERO_r(VT, RetVT, Op0, Op0IsKill);
    1215             :   default: return 0;
    1216             :   }
    1217             : }
    1218             : 
    1219             : // FastEmit functions for ISD::ADD.
    1220             : 
    1221           6 : unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1222           6 :   if (RetVT.SimpleTy != MVT::i32)
    1223             :     return 0;
    1224           6 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
    1225           0 :     return fastEmitInst_rr(Mips::ADDU16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1226             :   }
    1227           6 :   if ((Subtarget->inMips16Mode())) {
    1228           0 :     return fastEmitInst_rr(Mips::AdduRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1229             :   }
    1230           6 :   if ((Subtarget->inMicroMipsMode())) {
    1231           0 :     return fastEmitInst_rr(Mips::ADDu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1232             :   }
    1233             :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
    1234             :     return fastEmitInst_rr(Mips::ADDU16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1235             :   }
    1236             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1237          12 :     return fastEmitInst_rr(Mips::ADDu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1238             :   }
    1239             :   return 0;
    1240             : }
    1241             : 
    1242           0 : unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1243           0 :   if (RetVT.SimpleTy != MVT::i64)
    1244             :     return 0;
    1245           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1246           0 :     return fastEmitInst_rr(Mips::DADDu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1247             :   }
    1248             :   return 0;
    1249             : }
    1250             : 
    1251             : unsigned fastEmit_ISD_ADD_MVT_v4i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1252           0 :   if (RetVT.SimpleTy != MVT::v4i8)
    1253             :     return 0;
    1254           0 :   if ((Subtarget->hasDSP())) {
    1255             :     return fastEmitInst_rr(Mips::ADDU_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1256             :   }
    1257             :   return 0;
    1258             : }
    1259             : 
    1260           0 : unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1261           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1262             :     return 0;
    1263           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1264           0 :     return fastEmitInst_rr(Mips::ADDV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1265             :   }
    1266             :   return 0;
    1267             : }
    1268             : 
    1269             : unsigned fastEmit_ISD_ADD_MVT_v2i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1270           0 :   if (RetVT.SimpleTy != MVT::v2i16)
    1271             :     return 0;
    1272           0 :   if ((Subtarget->hasDSP())) {
    1273             :     return fastEmitInst_rr(Mips::ADDQ_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1274             :   }
    1275             :   return 0;
    1276             : }
    1277             : 
    1278           0 : unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1279           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1280             :     return 0;
    1281           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1282           0 :     return fastEmitInst_rr(Mips::ADDV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1283             :   }
    1284             :   return 0;
    1285             : }
    1286             : 
    1287           0 : unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1288           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1289             :     return 0;
    1290           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1291           0 :     return fastEmitInst_rr(Mips::ADDV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1292             :   }
    1293             :   return 0;
    1294             : }
    1295             : 
    1296           0 : unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1297           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1298             :     return 0;
    1299           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1300           0 :     return fastEmitInst_rr(Mips::ADDV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1301             :   }
    1302             :   return 0;
    1303             : }
    1304             : 
    1305           6 : unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1306           6 :   switch (VT.SimpleTy) {
    1307           6 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1308           0 :   case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1309           0 :   case MVT::v4i8: return fastEmit_ISD_ADD_MVT_v4i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1310           0 :   case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1311           0 :   case MVT::v2i16: return fastEmit_ISD_ADD_MVT_v2i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1312           0 :   case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1313           0 :   case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1314           0 :   case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1315             :   default: return 0;
    1316             :   }
    1317             : }
    1318             : 
    1319             : // FastEmit functions for ISD::ADDC.
    1320             : 
    1321           0 : unsigned fastEmit_ISD_ADDC_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1322           0 :   if (RetVT.SimpleTy != MVT::i32)
    1323             :     return 0;
    1324           0 :   if ((Subtarget->hasDSP())) {
    1325           0 :     return fastEmitInst_rr(Mips::ADDSC, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1326             :   }
    1327           0 :   if ((Subtarget->inMips16Mode())) {
    1328           0 :     return fastEmitInst_rr(Mips::AdduRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1329             :   }
    1330             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP())) {
    1331           0 :     return fastEmitInst_rr(Mips::ADDu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1332             :   }
    1333             :   return 0;
    1334             : }
    1335             : 
    1336           0 : unsigned fastEmit_ISD_ADDC_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1337           0 :   if (RetVT.SimpleTy != MVT::i64)
    1338             :     return 0;
    1339           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->inMicroMipsMode())) {
    1340           0 :     return fastEmitInst_rr(Mips::DADDu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1341             :   }
    1342             :   return 0;
    1343             : }
    1344             : 
    1345           0 : unsigned fastEmit_ISD_ADDC_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1346           0 :   switch (VT.SimpleTy) {
    1347           0 :   case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1348           0 :   case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1349             :   default: return 0;
    1350             :   }
    1351             : }
    1352             : 
    1353             : // FastEmit functions for ISD::ADDE.
    1354             : 
    1355             : unsigned fastEmit_ISD_ADDE_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1356           0 :   if (RetVT.SimpleTy != MVT::i32)
    1357             :     return 0;
    1358           0 :   if ((Subtarget->hasDSP())) {
    1359             :     return fastEmitInst_rr(Mips::ADDWC, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1360             :   }
    1361             :   return 0;
    1362             : }
    1363             : 
    1364           0 : unsigned fastEmit_ISD_ADDE_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1365           0 :   switch (VT.SimpleTy) {
    1366           0 :   case MVT::i32: return fastEmit_ISD_ADDE_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1367             :   default: return 0;
    1368             :   }
    1369             : }
    1370             : 
    1371             : // FastEmit functions for ISD::AND.
    1372             : 
    1373           5 : unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1374           5 :   if (RetVT.SimpleTy != MVT::i32)
    1375             :     return 0;
    1376           5 :   if ((Subtarget->inMips16Mode())) {
    1377           0 :     return fastEmitInst_rr(Mips::AndRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1378             :   }
    1379           5 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
    1380           0 :     return fastEmitInst_rr(Mips::AND_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1381             :   }
    1382           5 :   if ((Subtarget->inMicroMipsMode())) {
    1383           0 :     return fastEmitInst_rr(Mips::AND_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1384             :   }
    1385             :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
    1386             :     return fastEmitInst_rr(Mips::AND16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1387             :   }
    1388             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1389          10 :     return fastEmitInst_rr(Mips::AND, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1390             :   }
    1391             :   return 0;
    1392             : }
    1393             : 
    1394             : unsigned fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1395           0 :   if (RetVT.SimpleTy != MVT::i64)
    1396             :     return 0;
    1397           0 :   if ((Subtarget->hasStandardEncoding())) {
    1398             :     return fastEmitInst_rr(Mips::AND64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1399             :   }
    1400             :   return 0;
    1401             : }
    1402             : 
    1403           0 : unsigned fastEmit_ISD_AND_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1404           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1405             :     return 0;
    1406           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1407           0 :     return fastEmitInst_rr(Mips::AND_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1408             :   }
    1409             :   return 0;
    1410             : }
    1411             : 
    1412             : unsigned fastEmit_ISD_AND_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1413           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1414             :     return 0;
    1415           0 :   if ((Subtarget->hasMSA())) {
    1416             :     return fastEmitInst_rr(Mips::AND_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1417             :   }
    1418             :   return 0;
    1419             : }
    1420             : 
    1421             : unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1422           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1423             :     return 0;
    1424           0 :   if ((Subtarget->hasMSA())) {
    1425             :     return fastEmitInst_rr(Mips::AND_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1426             :   }
    1427             :   return 0;
    1428             : }
    1429             : 
    1430             : unsigned fastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1431           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1432             :     return 0;
    1433           0 :   if ((Subtarget->hasMSA())) {
    1434             :     return fastEmitInst_rr(Mips::AND_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1435             :   }
    1436             :   return 0;
    1437             : }
    1438             : 
    1439           5 : unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1440           5 :   switch (VT.SimpleTy) {
    1441           5 :   case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1442           0 :   case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1443           0 :   case MVT::v16i8: return fastEmit_ISD_AND_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1444           0 :   case MVT::v8i16: return fastEmit_ISD_AND_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1445           0 :   case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1446           0 :   case MVT::v2i64: return fastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1447             :   default: return 0;
    1448             :   }
    1449             : }
    1450             : 
    1451             : // FastEmit functions for ISD::FADD.
    1452             : 
    1453           0 : unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1454           0 :   if (RetVT.SimpleTy != MVT::f32)
    1455             :     return 0;
    1456           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
    1457           0 :     return fastEmitInst_rr(Mips::FADD_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1458             :   }
    1459           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
    1460           0 :     return fastEmitInst_rr(Mips::FADD_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1461             :   }
    1462             :   return 0;
    1463             : }
    1464             : 
    1465           0 : unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1466           0 :   if (RetVT.SimpleTy != MVT::f64)
    1467             :     return 0;
    1468           0 :   if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
    1469           0 :     return fastEmitInst_rr(Mips::FADD_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1470             :   }
    1471           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
    1472           0 :     return fastEmitInst_rr(Mips::FADD_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1473             :   }
    1474           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
    1475           0 :     return fastEmitInst_rr(Mips::FADD_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1476             :   }
    1477           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
    1478           0 :     return fastEmitInst_rr(Mips::FADD_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1479             :   }
    1480             :   return 0;
    1481             : }
    1482             : 
    1483           0 : unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1484           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1485             :     return 0;
    1486           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1487           0 :     return fastEmitInst_rr(Mips::FADD_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1488             :   }
    1489             :   return 0;
    1490             : }
    1491             : 
    1492           0 : unsigned fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1493           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1494             :     return 0;
    1495           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1496           0 :     return fastEmitInst_rr(Mips::FADD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1497             :   }
    1498             :   return 0;
    1499             : }
    1500             : 
    1501           0 : unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1502           0 :   switch (VT.SimpleTy) {
    1503           0 :   case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1504           0 :   case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1505           0 :   case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1506           0 :   case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1507             :   default: return 0;
    1508             :   }
    1509             : }
    1510             : 
    1511             : // FastEmit functions for ISD::FDIV.
    1512             : 
    1513           0 : unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1514           0 :   if (RetVT.SimpleTy != MVT::f32)
    1515             :     return 0;
    1516           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
    1517           0 :     return fastEmitInst_rr(Mips::FDIV_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1518             :   }
    1519           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
    1520           0 :     return fastEmitInst_rr(Mips::FDIV_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1521             :   }
    1522             :   return 0;
    1523             : }
    1524             : 
    1525           0 : unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1526           0 :   if (RetVT.SimpleTy != MVT::f64)
    1527             :     return 0;
    1528           0 :   if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
    1529           0 :     return fastEmitInst_rr(Mips::FDIV_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1530             :   }
    1531           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
    1532           0 :     return fastEmitInst_rr(Mips::FDIV_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1533             :   }
    1534           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
    1535           0 :     return fastEmitInst_rr(Mips::FDIV_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1536             :   }
    1537           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
    1538           0 :     return fastEmitInst_rr(Mips::FDIV_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1539             :   }
    1540             :   return 0;
    1541             : }
    1542             : 
    1543           0 : unsigned fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1544           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1545             :     return 0;
    1546           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1547           0 :     return fastEmitInst_rr(Mips::FDIV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1548             :   }
    1549             :   return 0;
    1550             : }
    1551             : 
    1552           0 : unsigned fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1553           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1554             :     return 0;
    1555           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1556           0 :     return fastEmitInst_rr(Mips::FDIV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1557             :   }
    1558             :   return 0;
    1559             : }
    1560             : 
    1561           0 : unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1562           0 :   switch (VT.SimpleTy) {
    1563           0 :   case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1564           0 :   case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1565           0 :   case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1566           0 :   case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1567             :   default: return 0;
    1568             :   }
    1569             : }
    1570             : 
    1571             : // FastEmit functions for ISD::FMUL.
    1572             : 
    1573           0 : unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1574           0 :   if (RetVT.SimpleTy != MVT::f32)
    1575             :     return 0;
    1576           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
    1577           0 :     return fastEmitInst_rr(Mips::FMUL_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1578             :   }
    1579           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
    1580           0 :     return fastEmitInst_rr(Mips::FMUL_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1581             :   }
    1582             :   return 0;
    1583             : }
    1584             : 
    1585           0 : unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1586           0 :   if (RetVT.SimpleTy != MVT::f64)
    1587             :     return 0;
    1588           0 :   if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
    1589           0 :     return fastEmitInst_rr(Mips::FMUL_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1590             :   }
    1591           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
    1592           0 :     return fastEmitInst_rr(Mips::FMUL_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1593             :   }
    1594           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
    1595           0 :     return fastEmitInst_rr(Mips::FMUL_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1596             :   }
    1597           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
    1598           0 :     return fastEmitInst_rr(Mips::FMUL_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1599             :   }
    1600             :   return 0;
    1601             : }
    1602             : 
    1603           0 : unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1604           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1605             :     return 0;
    1606           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1607           0 :     return fastEmitInst_rr(Mips::FMUL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1608             :   }
    1609             :   return 0;
    1610             : }
    1611             : 
    1612           0 : unsigned fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1613           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1614             :     return 0;
    1615           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1616           0 :     return fastEmitInst_rr(Mips::FMUL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1617             :   }
    1618             :   return 0;
    1619             : }
    1620             : 
    1621           0 : unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1622           0 :   switch (VT.SimpleTy) {
    1623           0 :   case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1624           0 :   case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1625           0 :   case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1626           0 :   case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1627             :   default: return 0;
    1628             :   }
    1629             : }
    1630             : 
    1631             : // FastEmit functions for ISD::FSUB.
    1632             : 
    1633           0 : unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1634           0 :   if (RetVT.SimpleTy != MVT::f32)
    1635             :     return 0;
    1636           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
    1637           0 :     return fastEmitInst_rr(Mips::FSUB_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1638             :   }
    1639           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
    1640           0 :     return fastEmitInst_rr(Mips::FSUB_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1641             :   }
    1642             :   return 0;
    1643             : }
    1644             : 
    1645           0 : unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1646           0 :   if (RetVT.SimpleTy != MVT::f64)
    1647             :     return 0;
    1648           0 :   if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
    1649           0 :     return fastEmitInst_rr(Mips::FSUB_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1650             :   }
    1651           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
    1652           0 :     return fastEmitInst_rr(Mips::FSUB_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1653             :   }
    1654           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
    1655           0 :     return fastEmitInst_rr(Mips::FSUB_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1656             :   }
    1657           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
    1658           0 :     return fastEmitInst_rr(Mips::FSUB_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1659             :   }
    1660             :   return 0;
    1661             : }
    1662             : 
    1663           0 : unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1664           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1665             :     return 0;
    1666           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1667           0 :     return fastEmitInst_rr(Mips::FSUB_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1668             :   }
    1669             :   return 0;
    1670             : }
    1671             : 
    1672           0 : unsigned fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1673           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1674             :     return 0;
    1675           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1676           0 :     return fastEmitInst_rr(Mips::FSUB_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1677             :   }
    1678             :   return 0;
    1679             : }
    1680             : 
    1681           0 : unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1682           0 :   switch (VT.SimpleTy) {
    1683           0 :   case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1684           0 :   case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1685           0 :   case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1686           0 :   case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1687             :   default: return 0;
    1688             :   }
    1689             : }
    1690             : 
    1691             : // FastEmit functions for ISD::MUL.
    1692             : 
    1693           2 : unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1694           2 :   if (RetVT.SimpleTy != MVT::i32)
    1695             :     return 0;
    1696           2 :   if ((Subtarget->inMips16Mode())) {
    1697           0 :     return fastEmitInst_rr(Mips::MultRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1698             :   }
    1699           2 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
    1700           0 :     return fastEmitInst_rr(Mips::MUL_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1701             :   }
    1702           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1703           0 :     return fastEmitInst_rr(Mips::MUL_R6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1704             :   }
    1705             :   if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    1706           2 :     return fastEmitInst_rr(Mips::MUL, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1707             :   }
    1708             :   return 0;
    1709             : }
    1710             : 
    1711           0 : unsigned fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1712           0 :   if (RetVT.SimpleTy != MVT::i64)
    1713             :     return 0;
    1714           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1715           0 :     return fastEmitInst_rr(Mips::DMUL_R6, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1716             :   }
    1717           0 :   if ((Subtarget->hasCnMips())) {
    1718           0 :     return fastEmitInst_rr(Mips::DMUL, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1719             :   }
    1720             :   return 0;
    1721             : }
    1722             : 
    1723           0 : unsigned fastEmit_ISD_MUL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1724           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1725             :     return 0;
    1726           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1727           0 :     return fastEmitInst_rr(Mips::MULV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1728             :   }
    1729             :   return 0;
    1730             : }
    1731             : 
    1732             : unsigned fastEmit_ISD_MUL_MVT_v2i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1733           0 :   if (RetVT.SimpleTy != MVT::v2i16)
    1734             :     return 0;
    1735           0 :   if ((Subtarget->hasDSPR2())) {
    1736             :     return fastEmitInst_rr(Mips::MUL_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1737             :   }
    1738             :   return 0;
    1739             : }
    1740             : 
    1741           0 : unsigned fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1742           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1743             :     return 0;
    1744           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1745           0 :     return fastEmitInst_rr(Mips::MULV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1746             :   }
    1747             :   return 0;
    1748             : }
    1749             : 
    1750           0 : unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1751           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1752             :     return 0;
    1753           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1754           0 :     return fastEmitInst_rr(Mips::MULV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1755             :   }
    1756             :   return 0;
    1757             : }
    1758             : 
    1759           0 : unsigned fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1760           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1761             :     return 0;
    1762           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1763           0 :     return fastEmitInst_rr(Mips::MULV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1764             :   }
    1765             :   return 0;
    1766             : }
    1767             : 
    1768           2 : unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1769           2 :   switch (VT.SimpleTy) {
    1770           2 :   case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1771           0 :   case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1772           0 :   case MVT::v16i8: return fastEmit_ISD_MUL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1773           0 :   case MVT::v2i16: return fastEmit_ISD_MUL_MVT_v2i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1774           0 :   case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1775           0 :   case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1776           0 :   case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1777             :   default: return 0;
    1778             :   }
    1779             : }
    1780             : 
    1781             : // FastEmit functions for ISD::MULHS.
    1782             : 
    1783           0 : unsigned fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1784           0 :   if (RetVT.SimpleTy != MVT::i32)
    1785             :     return 0;
    1786           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
    1787           0 :     return fastEmitInst_rr(Mips::MUH_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1788             :   }
    1789           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1790           0 :     return fastEmitInst_rr(Mips::MUH, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1791             :   }
    1792             :   return 0;
    1793             : }
    1794             : 
    1795           0 : unsigned fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1796           0 :   if (RetVT.SimpleTy != MVT::i64)
    1797             :     return 0;
    1798           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1799           0 :     return fastEmitInst_rr(Mips::DMUH, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1800             :   }
    1801             :   return 0;
    1802             : }
    1803             : 
    1804           0 : unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1805           0 :   switch (VT.SimpleTy) {
    1806           0 :   case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1807           0 :   case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1808             :   default: return 0;
    1809             :   }
    1810             : }
    1811             : 
    1812             : // FastEmit functions for ISD::MULHU.
    1813             : 
    1814           0 : unsigned fastEmit_ISD_MULHU_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1815           0 :   if (RetVT.SimpleTy != MVT::i32)
    1816             :     return 0;
    1817           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
    1818           0 :     return fastEmitInst_rr(Mips::MUHU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1819             :   }
    1820           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1821           0 :     return fastEmitInst_rr(Mips::MUHU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1822             :   }
    1823             :   return 0;
    1824             : }
    1825             : 
    1826           0 : unsigned fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1827           0 :   if (RetVT.SimpleTy != MVT::i64)
    1828             :     return 0;
    1829           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1830           0 :     return fastEmitInst_rr(Mips::DMUHU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1831             :   }
    1832             :   return 0;
    1833             : }
    1834             : 
    1835           0 : unsigned fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1836           0 :   switch (VT.SimpleTy) {
    1837           0 :   case MVT::i32: return fastEmit_ISD_MULHU_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1838           0 :   case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1839             :   default: return 0;
    1840             :   }
    1841             : }
    1842             : 
    1843             : // FastEmit functions for ISD::OR.
    1844             : 
    1845           4 : unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1846           4 :   if (RetVT.SimpleTy != MVT::i32)
    1847             :     return 0;
    1848           4 :   if ((Subtarget->inMips16Mode())) {
    1849           0 :     return fastEmitInst_rr(Mips::OrRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1850             :   }
    1851           4 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
    1852           0 :     return fastEmitInst_rr(Mips::OR_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1853             :   }
    1854           4 :   if ((Subtarget->inMicroMipsMode())) {
    1855           0 :     return fastEmitInst_rr(Mips::OR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1856             :   }
    1857             :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
    1858             :     return fastEmitInst_rr(Mips::OR16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1859             :   }
    1860             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1861           8 :     return fastEmitInst_rr(Mips::OR, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1862             :   }
    1863             :   return 0;
    1864             : }
    1865             : 
    1866             : unsigned fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1867           0 :   if (RetVT.SimpleTy != MVT::i64)
    1868             :     return 0;
    1869           0 :   if ((Subtarget->hasStandardEncoding())) {
    1870             :     return fastEmitInst_rr(Mips::OR64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1871             :   }
    1872             :   return 0;
    1873             : }
    1874             : 
    1875           0 : unsigned fastEmit_ISD_OR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1876           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1877             :     return 0;
    1878           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1879           0 :     return fastEmitInst_rr(Mips::OR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1880             :   }
    1881             :   return 0;
    1882             : }
    1883             : 
    1884             : unsigned fastEmit_ISD_OR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1885           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1886             :     return 0;
    1887           0 :   if ((Subtarget->hasMSA())) {
    1888             :     return fastEmitInst_rr(Mips::OR_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1889             :   }
    1890             :   return 0;
    1891             : }
    1892             : 
    1893             : unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1894           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1895             :     return 0;
    1896           0 :   if ((Subtarget->hasMSA())) {
    1897             :     return fastEmitInst_rr(Mips::OR_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1898             :   }
    1899             :   return 0;
    1900             : }
    1901             : 
    1902             : unsigned fastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1903           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1904             :     return 0;
    1905           0 :   if ((Subtarget->hasMSA())) {
    1906             :     return fastEmitInst_rr(Mips::OR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1907             :   }
    1908             :   return 0;
    1909             : }
    1910             : 
    1911           4 : unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1912           4 :   switch (VT.SimpleTy) {
    1913           4 :   case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1914           0 :   case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1915           0 :   case MVT::v16i8: return fastEmit_ISD_OR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1916           0 :   case MVT::v8i16: return fastEmit_ISD_OR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1917           0 :   case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1918           0 :   case MVT::v2i64: return fastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1919             :   default: return 0;
    1920             :   }
    1921             : }
    1922             : 
    1923             : // FastEmit functions for ISD::ROTR.
    1924             : 
    1925           0 : unsigned fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1926           0 :   if (RetVT.SimpleTy != MVT::i32)
    1927             :     return 0;
    1928           0 :   if ((Subtarget->inMicroMipsMode())) {
    1929           0 :     return fastEmitInst_rr(Mips::ROTRV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1930             :   }
    1931           0 :   if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1932           0 :     return fastEmitInst_rr(Mips::ROTRV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1933             :   }
    1934             :   return 0;
    1935             : }
    1936             : 
    1937             : unsigned fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1938           0 :   switch (VT.SimpleTy) {
    1939           0 :   case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1940             :   default: return 0;
    1941             :   }
    1942             : }
    1943             : 
    1944             : // FastEmit functions for ISD::SDIV.
    1945             : 
    1946           4 : unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1947           4 :   if (RetVT.SimpleTy != MVT::i32)
    1948             :     return 0;
    1949           4 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
    1950           0 :     return fastEmitInst_rr(Mips::DIV_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1951             :   }
    1952           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1953           0 :     return fastEmitInst_rr(Mips::DIV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1954             :   }
    1955             :   return 0;
    1956             : }
    1957             : 
    1958           0 : unsigned fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1959           0 :   if (RetVT.SimpleTy != MVT::i64)
    1960             :     return 0;
    1961           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1962           0 :     return fastEmitInst_rr(Mips::DDIV, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1963             :   }
    1964             :   return 0;
    1965             : }
    1966             : 
    1967           0 : unsigned fastEmit_ISD_SDIV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1968           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1969             :     return 0;
    1970           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1971           0 :     return fastEmitInst_rr(Mips::DIV_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1972             :   }
    1973             :   return 0;
    1974             : }
    1975             : 
    1976           0 : unsigned fastEmit_ISD_SDIV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1977           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1978             :     return 0;
    1979           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1980           0 :     return fastEmitInst_rr(Mips::DIV_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1981             :   }
    1982             :   return 0;
    1983             : }
    1984             : 
    1985           0 : unsigned fastEmit_ISD_SDIV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1986           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1987             :     return 0;
    1988           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1989           0 :     return fastEmitInst_rr(Mips::DIV_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1990             :   }
    1991             :   return 0;
    1992             : }
    1993             : 
    1994           0 : unsigned fastEmit_ISD_SDIV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1995           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1996             :     return 0;
    1997           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1998           0 :     return fastEmitInst_rr(Mips::DIV_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1999             :   }
    2000             :   return 0;
    2001             : }
    2002             : 
    2003           4 : unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2004           4 :   switch (VT.SimpleTy) {
    2005           4 :   case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2006           0 :   case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2007           0 :   case MVT::v16i8: return fastEmit_ISD_SDIV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2008           0 :   case MVT::v8i16: return fastEmit_ISD_SDIV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2009           0 :   case MVT::v4i32: return fastEmit_ISD_SDIV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2010           0 :   case MVT::v2i64: return fastEmit_ISD_SDIV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2011             :   default: return 0;
    2012             :   }
    2013             : }
    2014             : 
    2015             : // FastEmit functions for ISD::SHL.
    2016             : 
    2017           0 : unsigned fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2018           0 :   if (RetVT.SimpleTy != MVT::i32)
    2019             :     return 0;
    2020           0 :   if ((Subtarget->inMicroMipsMode())) {
    2021           0 :     return fastEmitInst_rr(Mips::SLLV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2022             :   }
    2023           0 :   if ((Subtarget->inMips16Mode())) {
    2024           0 :     return fastEmitInst_rr(Mips::SllvRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2025             :   }
    2026             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2027           0 :     return fastEmitInst_rr(Mips::SLLV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2028             :   }
    2029             :   return 0;
    2030             : }
    2031             : 
    2032           0 : unsigned fastEmit_ISD_SHL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2033           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2034             :     return 0;
    2035           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2036           0 :     return fastEmitInst_rr(Mips::SLL_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2037             :   }
    2038             :   return 0;
    2039             : }
    2040             : 
    2041           0 : unsigned fastEmit_ISD_SHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2042           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2043             :     return 0;
    2044           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2045           0 :     return fastEmitInst_rr(Mips::SLL_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2046             :   }
    2047             :   return 0;
    2048             : }
    2049             : 
    2050           0 : unsigned fastEmit_ISD_SHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2051           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2052             :     return 0;
    2053           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2054           0 :     return fastEmitInst_rr(Mips::SLL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2055             :   }
    2056             :   return 0;
    2057             : }
    2058             : 
    2059           0 : unsigned fastEmit_ISD_SHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2060           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2061             :     return 0;
    2062           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2063           0 :     return fastEmitInst_rr(Mips::SLL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2064             :   }
    2065             :   return 0;
    2066             : }
    2067             : 
    2068           0 : unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2069           0 :   switch (VT.SimpleTy) {
    2070           0 :   case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2071           0 :   case MVT::v16i8: return fastEmit_ISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2072           0 :   case MVT::v8i16: return fastEmit_ISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2073           0 :   case MVT::v4i32: return fastEmit_ISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2074           0 :   case MVT::v2i64: return fastEmit_ISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2075             :   default: return 0;
    2076             :   }
    2077             : }
    2078             : 
    2079             : // FastEmit functions for ISD::SMAX.
    2080             : 
    2081           0 : unsigned fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2082           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2083             :     return 0;
    2084           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2085           0 :     return fastEmitInst_rr(Mips::MAX_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2086             :   }
    2087             :   return 0;
    2088             : }
    2089             : 
    2090           0 : unsigned fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2091           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2092             :     return 0;
    2093           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2094           0 :     return fastEmitInst_rr(Mips::MAX_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2095             :   }
    2096             :   return 0;
    2097             : }
    2098             : 
    2099           0 : unsigned fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2100           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2101             :     return 0;
    2102           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2103           0 :     return fastEmitInst_rr(Mips::MAX_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2104             :   }
    2105             :   return 0;
    2106             : }
    2107             : 
    2108           0 : unsigned fastEmit_ISD_SMAX_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2109           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2110             :     return 0;
    2111           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2112           0 :     return fastEmitInst_rr(Mips::MAX_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2113             :   }
    2114             :   return 0;
    2115             : }
    2116             : 
    2117           0 : unsigned fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2118           0 :   switch (VT.SimpleTy) {
    2119           0 :   case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2120           0 :   case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2121           0 :   case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2122           0 :   case MVT::v2i64: return fastEmit_ISD_SMAX_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2123             :   default: return 0;
    2124             :   }
    2125             : }
    2126             : 
    2127             : // FastEmit functions for ISD::SMIN.
    2128             : 
    2129           0 : unsigned fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2130           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2131             :     return 0;
    2132           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2133           0 :     return fastEmitInst_rr(Mips::MIN_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2134             :   }
    2135             :   return 0;
    2136             : }
    2137             : 
    2138           0 : unsigned fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2139           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2140             :     return 0;
    2141           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2142           0 :     return fastEmitInst_rr(Mips::MIN_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2143             :   }
    2144             :   return 0;
    2145             : }
    2146             : 
    2147           0 : unsigned fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2148           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2149             :     return 0;
    2150           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2151           0 :     return fastEmitInst_rr(Mips::MIN_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2152             :   }
    2153             :   return 0;
    2154             : }
    2155             : 
    2156           0 : unsigned fastEmit_ISD_SMIN_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2157           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2158             :     return 0;
    2159           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2160           0 :     return fastEmitInst_rr(Mips::MIN_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2161             :   }
    2162             :   return 0;
    2163             : }
    2164             : 
    2165           0 : unsigned fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2166           0 :   switch (VT.SimpleTy) {
    2167           0 :   case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2168           0 :   case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2169           0 :   case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2170           0 :   case MVT::v2i64: return fastEmit_ISD_SMIN_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2171             :   default: return 0;
    2172             :   }
    2173             : }
    2174             : 
    2175             : // FastEmit functions for ISD::SRA.
    2176             : 
    2177           0 : unsigned fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2178           0 :   if (RetVT.SimpleTy != MVT::i32)
    2179             :     return 0;
    2180           0 :   if ((Subtarget->inMicroMipsMode())) {
    2181           0 :     return fastEmitInst_rr(Mips::SRAV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2182             :   }
    2183           0 :   if ((Subtarget->inMips16Mode())) {
    2184           0 :     return fastEmitInst_rr(Mips::SravRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2185             :   }
    2186             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2187           0 :     return fastEmitInst_rr(Mips::SRAV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2188             :   }
    2189             :   return 0;
    2190             : }
    2191             : 
    2192           0 : unsigned fastEmit_ISD_SRA_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2193           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2194             :     return 0;
    2195           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2196           0 :     return fastEmitInst_rr(Mips::SRA_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2197             :   }
    2198             :   return 0;
    2199             : }
    2200             : 
    2201           0 : unsigned fastEmit_ISD_SRA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2202           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2203             :     return 0;
    2204           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2205           0 :     return fastEmitInst_rr(Mips::SRA_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2206             :   }
    2207             :   return 0;
    2208             : }
    2209             : 
    2210           0 : unsigned fastEmit_ISD_SRA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2211           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2212             :     return 0;
    2213           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2214           0 :     return fastEmitInst_rr(Mips::SRA_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2215             :   }
    2216             :   return 0;
    2217             : }
    2218             : 
    2219           0 : unsigned fastEmit_ISD_SRA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2220           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2221             :     return 0;
    2222           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2223           0 :     return fastEmitInst_rr(Mips::SRA_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2224             :   }
    2225             :   return 0;
    2226             : }
    2227             : 
    2228           0 : unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2229           0 :   switch (VT.SimpleTy) {
    2230           0 :   case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2231           0 :   case MVT::v16i8: return fastEmit_ISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2232           0 :   case MVT::v8i16: return fastEmit_ISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2233           0 :   case MVT::v4i32: return fastEmit_ISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2234           0 :   case MVT::v2i64: return fastEmit_ISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2235             :   default: return 0;
    2236             :   }
    2237             : }
    2238             : 
    2239             : // FastEmit functions for ISD::SREM.
    2240             : 
    2241           4 : unsigned fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2242           4 :   if (RetVT.SimpleTy != MVT::i32)
    2243             :     return 0;
    2244           4 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
    2245           0 :     return fastEmitInst_rr(Mips::MOD_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2246             :   }
    2247           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2248           0 :     return fastEmitInst_rr(Mips::MOD, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2249             :   }
    2250             :   return 0;
    2251             : }
    2252             : 
    2253           0 : unsigned fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2254           0 :   if (RetVT.SimpleTy != MVT::i64)
    2255             :     return 0;
    2256           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2257           0 :     return fastEmitInst_rr(Mips::DMOD, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2258             :   }
    2259             :   return 0;
    2260             : }
    2261             : 
    2262           0 : unsigned fastEmit_ISD_SREM_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2263           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2264             :     return 0;
    2265           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2266           0 :     return fastEmitInst_rr(Mips::MOD_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2267             :   }
    2268             :   return 0;
    2269             : }
    2270             : 
    2271           0 : unsigned fastEmit_ISD_SREM_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2272           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2273             :     return 0;
    2274           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2275           0 :     return fastEmitInst_rr(Mips::MOD_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2276             :   }
    2277             :   return 0;
    2278             : }
    2279             : 
    2280           0 : unsigned fastEmit_ISD_SREM_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2281           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2282             :     return 0;
    2283           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2284           0 :     return fastEmitInst_rr(Mips::MOD_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2285             :   }
    2286             :   return 0;
    2287             : }
    2288             : 
    2289           0 : unsigned fastEmit_ISD_SREM_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2290           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2291             :     return 0;
    2292           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2293           0 :     return fastEmitInst_rr(Mips::MOD_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2294             :   }
    2295             :   return 0;
    2296             : }
    2297             : 
    2298           4 : unsigned fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2299           4 :   switch (VT.SimpleTy) {
    2300           4 :   case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2301           0 :   case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2302           0 :   case MVT::v16i8: return fastEmit_ISD_SREM_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2303           0 :   case MVT::v8i16: return fastEmit_ISD_SREM_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2304           0 :   case MVT::v4i32: return fastEmit_ISD_SREM_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2305           0 :   case MVT::v2i64: return fastEmit_ISD_SREM_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2306             :   default: return 0;
    2307             :   }
    2308             : }
    2309             : 
    2310             : // FastEmit functions for ISD::SRL.
    2311             : 
    2312           0 : unsigned fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2313           0 :   if (RetVT.SimpleTy != MVT::i32)
    2314             :     return 0;
    2315           0 :   if ((Subtarget->inMicroMipsMode())) {
    2316           0 :     return fastEmitInst_rr(Mips::SRLV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2317             :   }
    2318           0 :   if ((Subtarget->inMips16Mode())) {
    2319           0 :     return fastEmitInst_rr(Mips::SrlvRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2320             :   }
    2321             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2322           0 :     return fastEmitInst_rr(Mips::SRLV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2323             :   }
    2324             :   return 0;
    2325             : }
    2326             : 
    2327           0 : unsigned fastEmit_ISD_SRL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2328           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2329             :     return 0;
    2330           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2331           0 :     return fastEmitInst_rr(Mips::SRL_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2332             :   }
    2333             :   return 0;
    2334             : }
    2335             : 
    2336           0 : unsigned fastEmit_ISD_SRL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2337           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2338             :     return 0;
    2339           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2340           0 :     return fastEmitInst_rr(Mips::SRL_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2341             :   }
    2342             :   return 0;
    2343             : }
    2344             : 
    2345           0 : unsigned fastEmit_ISD_SRL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2346           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2347             :     return 0;
    2348           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2349           0 :     return fastEmitInst_rr(Mips::SRL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2350             :   }
    2351             :   return 0;
    2352             : }
    2353             : 
    2354           0 : unsigned fastEmit_ISD_SRL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2355           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2356             :     return 0;
    2357           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2358           0 :     return fastEmitInst_rr(Mips::SRL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2359             :   }
    2360             :   return 0;
    2361             : }
    2362             : 
    2363           0 : unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2364           0 :   switch (VT.SimpleTy) {
    2365           0 :   case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2366           0 :   case MVT::v16i8: return fastEmit_ISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2367           0 :   case MVT::v8i16: return fastEmit_ISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2368           0 :   case MVT::v4i32: return fastEmit_ISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2369           0 :   case MVT::v2i64: return fastEmit_ISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2370             :   default: return 0;
    2371             :   }
    2372             : }
    2373             : 
    2374             : // FastEmit functions for ISD::SUB.
    2375             : 
    2376           0 : unsigned fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2377           0 :   if (RetVT.SimpleTy != MVT::i32)
    2378             :     return 0;
    2379           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
    2380           0 :     return fastEmitInst_rr(Mips::SUBU16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2381             :   }
    2382           0 :   if ((Subtarget->inMips16Mode())) {
    2383           0 :     return fastEmitInst_rr(Mips::SubuRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2384             :   }
    2385           0 :   if ((Subtarget->inMicroMipsMode())) {
    2386           0 :     return fastEmitInst_rr(Mips::SUBu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2387             :   }
    2388             :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
    2389             :     return fastEmitInst_rr(Mips::SUBU16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2390             :   }
    2391             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2392           0 :     return fastEmitInst_rr(Mips::SUBu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2393             :   }
    2394             :   return 0;
    2395             : }
    2396             : 
    2397           0 : unsigned fastEmit_ISD_SUB_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2398           0 :   if (RetVT.SimpleTy != MVT::i64)
    2399             :     return 0;
    2400           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2401           0 :     return fastEmitInst_rr(Mips::DSUBu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2402             :   }
    2403             :   return 0;
    2404             : }
    2405             : 
    2406             : unsigned fastEmit_ISD_SUB_MVT_v4i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2407           0 :   if (RetVT.SimpleTy != MVT::v4i8)
    2408             :     return 0;
    2409           0 :   if ((Subtarget->hasDSP())) {
    2410             :     return fastEmitInst_rr(Mips::SUBU_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2411             :   }
    2412             :   return 0;
    2413             : }
    2414             : 
    2415           0 : unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2416           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2417             :     return 0;
    2418           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2419           0 :     return fastEmitInst_rr(Mips::SUBV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2420             :   }
    2421             :   return 0;
    2422             : }
    2423             : 
    2424             : unsigned fastEmit_ISD_SUB_MVT_v2i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2425           0 :   if (RetVT.SimpleTy != MVT::v2i16)
    2426             :     return 0;
    2427           0 :   if ((Subtarget->hasDSP())) {
    2428             :     return fastEmitInst_rr(Mips::SUBQ_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2429             :   }
    2430             :   return 0;
    2431             : }
    2432             : 
    2433           0 : unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2434           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2435             :     return 0;
    2436           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2437           0 :     return fastEmitInst_rr(Mips::SUBV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2438             :   }
    2439             :   return 0;
    2440             : }
    2441             : 
    2442           0 : unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2443           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2444             :     return 0;
    2445           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2446           0 :     return fastEmitInst_rr(Mips::SUBV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2447             :   }
    2448             :   return 0;
    2449             : }
    2450             : 
    2451           0 : unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2452           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2453             :     return 0;
    2454           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2455           0 :     return fastEmitInst_rr(Mips::SUBV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2456             :   }
    2457             :   return 0;
    2458             : }
    2459             : 
    2460           0 : unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2461           0 :   switch (VT.SimpleTy) {
    2462           0 :   case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2463           0 :   case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2464           0 :   case MVT::v4i8: return fastEmit_ISD_SUB_MVT_v4i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2465           0 :   case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2466           0 :   case MVT::v2i16: return fastEmit_ISD_SUB_MVT_v2i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2467           0 :   case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2468           0 :   case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2469           0 :   case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2470             :   default: return 0;
    2471             :   }
    2472             : }
    2473             : 
    2474             : // FastEmit functions for ISD::SUBC.
    2475             : 
    2476           0 : unsigned fastEmit_ISD_SUBC_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2477           0 :   if (RetVT.SimpleTy != MVT::i32)
    2478             :     return 0;
    2479           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
    2480           0 :     return fastEmitInst_rr(Mips::SUBU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2481             :   }
    2482           0 :   if ((Subtarget->inMicroMipsMode())) {
    2483           0 :     return fastEmitInst_rr(Mips::SUBu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2484             :   }
    2485           0 :   if ((Subtarget->inMips16Mode())) {
    2486           0 :     return fastEmitInst_rr(Mips::SubuRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2487             :   }
    2488             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2489           0 :     return fastEmitInst_rr(Mips::SUBu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2490             :   }
    2491             :   return 0;
    2492             : }
    2493             : 
    2494           0 : unsigned fastEmit_ISD_SUBC_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2495           0 :   if (RetVT.SimpleTy != MVT::i64)
    2496             :     return 0;
    2497           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2498           0 :     return fastEmitInst_rr(Mips::DSUBu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2499             :   }
    2500             :   return 0;
    2501             : }
    2502             : 
    2503           0 : unsigned fastEmit_ISD_SUBC_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2504           0 :   switch (VT.SimpleTy) {
    2505           0 :   case MVT::i32: return fastEmit_ISD_SUBC_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2506           0 :   case MVT::i64: return fastEmit_ISD_SUBC_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2507             :   default: return 0;
    2508             :   }
    2509             : }
    2510             : 
    2511             : // FastEmit functions for ISD::UDIV.
    2512             : 
    2513           4 : unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2514           4 :   if (RetVT.SimpleTy != MVT::i32)
    2515             :     return 0;
    2516           4 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
    2517           0 :     return fastEmitInst_rr(Mips::DIVU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2518             :   }
    2519           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2520           0 :     return fastEmitInst_rr(Mips::DIVU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2521             :   }
    2522             :   return 0;
    2523             : }
    2524             : 
    2525           0 : unsigned fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2526           0 :   if (RetVT.SimpleTy != MVT::i64)
    2527             :     return 0;
    2528           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2529           0 :     return fastEmitInst_rr(Mips::DDIVU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2530             :   }
    2531             :   return 0;
    2532             : }
    2533             : 
    2534           0 : unsigned fastEmit_ISD_UDIV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2535           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2536             :     return 0;
    2537           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2538           0 :     return fastEmitInst_rr(Mips::DIV_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2539             :   }
    2540             :   return 0;
    2541             : }
    2542             : 
    2543           0 : unsigned fastEmit_ISD_UDIV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2544           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2545             :     return 0;
    2546           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2547           0 :     return fastEmitInst_rr(Mips::DIV_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2548             :   }
    2549             :   return 0;
    2550             : }
    2551             : 
    2552           0 : unsigned fastEmit_ISD_UDIV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2553           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2554             :     return 0;
    2555           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2556           0 :     return fastEmitInst_rr(Mips::DIV_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2557             :   }
    2558             :   return 0;
    2559             : }
    2560             : 
    2561           0 : unsigned fastEmit_ISD_UDIV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2562           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2563             :     return 0;
    2564           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2565           0 :     return fastEmitInst_rr(Mips::DIV_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2566             :   }
    2567             :   return 0;
    2568             : }
    2569             : 
    2570           4 : unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2571           4 :   switch (VT.SimpleTy) {
    2572           4 :   case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2573           0 :   case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2574           0 :   case MVT::v16i8: return fastEmit_ISD_UDIV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2575           0 :   case MVT::v8i16: return fastEmit_ISD_UDIV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2576           0 :   case MVT::v4i32: return fastEmit_ISD_UDIV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2577           0 :   case MVT::v2i64: return fastEmit_ISD_UDIV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2578             :   default: return 0;
    2579             :   }
    2580             : }
    2581             : 
    2582             : // FastEmit functions for ISD::UMAX.
    2583             : 
    2584           0 : unsigned fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2585           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2586             :     return 0;
    2587           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2588           0 :     return fastEmitInst_rr(Mips::MAX_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2589             :   }
    2590             :   return 0;
    2591             : }
    2592             : 
    2593           0 : unsigned fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2594           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2595             :     return 0;
    2596           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2597           0 :     return fastEmitInst_rr(Mips::MAX_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2598             :   }
    2599             :   return 0;
    2600             : }
    2601             : 
    2602           0 : unsigned fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2603           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2604             :     return 0;
    2605           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2606           0 :     return fastEmitInst_rr(Mips::MAX_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2607             :   }
    2608             :   return 0;
    2609             : }
    2610             : 
    2611           0 : unsigned fastEmit_ISD_UMAX_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2612           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2613             :     return 0;
    2614           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2615           0 :     return fastEmitInst_rr(Mips::MAX_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2616             :   }
    2617             :   return 0;
    2618             : }
    2619             : 
    2620           0 : unsigned fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2621           0 :   switch (VT.SimpleTy) {
    2622           0 :   case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2623           0 :   case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2624           0 :   case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2625           0 :   case MVT::v2i64: return fastEmit_ISD_UMAX_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2626             :   default: return 0;
    2627             :   }
    2628             : }
    2629             : 
    2630             : // FastEmit functions for ISD::UMIN.
    2631             : 
    2632           0 : unsigned fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2633           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2634             :     return 0;
    2635           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2636           0 :     return fastEmitInst_rr(Mips::MIN_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2637             :   }
    2638             :   return 0;
    2639             : }
    2640             : 
    2641           0 : unsigned fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2642           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2643             :     return 0;
    2644           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2645           0 :     return fastEmitInst_rr(Mips::MIN_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2646             :   }
    2647             :   return 0;
    2648             : }
    2649             : 
    2650           0 : unsigned fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2651           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2652             :     return 0;
    2653           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2654           0 :     return fastEmitInst_rr(Mips::MIN_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2655             :   }
    2656             :   return 0;
    2657             : }
    2658             : 
    2659           0 : unsigned fastEmit_ISD_UMIN_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2660           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2661             :     return 0;
    2662           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2663           0 :     return fastEmitInst_rr(Mips::MIN_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2664             :   }
    2665             :   return 0;
    2666             : }
    2667             : 
    2668           0 : unsigned fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2669           0 :   switch (VT.SimpleTy) {
    2670           0 :   case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2671           0 :   case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2672           0 :   case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2673           0 :   case MVT::v2i64: return fastEmit_ISD_UMIN_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2674             :   default: return 0;
    2675             :   }
    2676             : }
    2677             : 
    2678             : // FastEmit functions for ISD::UREM.
    2679             : 
    2680           4 : unsigned fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2681           4 :   if (RetVT.SimpleTy != MVT::i32)
    2682             :     return 0;
    2683           4 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
    2684           0 :     return fastEmitInst_rr(Mips::MODU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2685             :   }
    2686           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2687           0 :     return fastEmitInst_rr(Mips::MODU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2688             :   }
    2689             :   return 0;
    2690             : }
    2691             : 
    2692           0 : unsigned fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2693           0 :   if (RetVT.SimpleTy != MVT::i64)
    2694             :     return 0;
    2695           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2696           0 :     return fastEmitInst_rr(Mips::DMODU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2697             :   }
    2698             :   return 0;
    2699             : }
    2700             : 
    2701           0 : unsigned fastEmit_ISD_UREM_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2702           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2703             :     return 0;
    2704           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2705           0 :     return fastEmitInst_rr(Mips::MOD_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2706             :   }
    2707             :   return 0;
    2708             : }
    2709             : 
    2710           0 : unsigned fastEmit_ISD_UREM_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2711           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2712             :     return 0;
    2713           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2714           0 :     return fastEmitInst_rr(Mips::MOD_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2715             :   }
    2716             :   return 0;
    2717             : }
    2718             : 
    2719           0 : unsigned fastEmit_ISD_UREM_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2720           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2721             :     return 0;
    2722           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2723           0 :     return fastEmitInst_rr(Mips::MOD_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2724             :   }
    2725             :   return 0;
    2726             : }
    2727             : 
    2728           0 : unsigned fastEmit_ISD_UREM_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2729           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2730             :     return 0;
    2731           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2732           0 :     return fastEmitInst_rr(Mips::MOD_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2733             :   }
    2734             :   return 0;
    2735             : }
    2736             : 
    2737           4 : unsigned fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2738           4 :   switch (VT.SimpleTy) {
    2739           4 :   case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2740           0 :   case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2741           0 :   case MVT::v16i8: return fastEmit_ISD_UREM_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2742           0 :   case MVT::v8i16: return fastEmit_ISD_UREM_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2743           0 :   case MVT::v4i32: return fastEmit_ISD_UREM_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2744           0 :   case MVT::v2i64: return fastEmit_ISD_UREM_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2745             :   default: return 0;
    2746             :   }
    2747             : }
    2748             : 
    2749             : // FastEmit functions for ISD::XOR.
    2750             : 
    2751           4 : unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2752           4 :   if (RetVT.SimpleTy != MVT::i32)
    2753             :     return 0;
    2754           4 :   if ((Subtarget->inMips16Mode())) {
    2755           0 :     return fastEmitInst_rr(Mips::XorRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2756             :   }
    2757           4 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
    2758           0 :     return fastEmitInst_rr(Mips::XOR_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2759             :   }
    2760           4 :   if ((Subtarget->inMicroMipsMode())) {
    2761           0 :     return fastEmitInst_rr(Mips::XOR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2762             :   }
    2763             :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
    2764             :     return fastEmitInst_rr(Mips::XOR16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2765             :   }
    2766             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2767           8 :     return fastEmitInst_rr(Mips::XOR, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2768             :   }
    2769             :   return 0;
    2770             : }
    2771             : 
    2772             : unsigned fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2773           0 :   if (RetVT.SimpleTy != MVT::i64)
    2774             :     return 0;
    2775           0 :   if ((Subtarget->hasStandardEncoding())) {
    2776             :     return fastEmitInst_rr(Mips::XOR64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2777             :   }
    2778             :   return 0;
    2779             : }
    2780             : 
    2781           0 : unsigned fastEmit_ISD_XOR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2782           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2783             :     return 0;
    2784           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2785           0 :     return fastEmitInst_rr(Mips::XOR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2786             :   }
    2787             :   return 0;
    2788             : }
    2789             : 
    2790             : unsigned fastEmit_ISD_XOR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2791           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2792             :     return 0;
    2793           0 :   if ((Subtarget->hasMSA())) {
    2794             :     return fastEmitInst_rr(Mips::XOR_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2795             :   }
    2796             :   return 0;
    2797             : }
    2798             : 
    2799             : unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2800           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2801             :     return 0;
    2802           0 :   if ((Subtarget->hasMSA())) {
    2803             :     return fastEmitInst_rr(Mips::XOR_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2804             :   }
    2805             :   return 0;
    2806             : }
    2807             : 
    2808             : unsigned fastEmit_ISD_XOR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2809           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2810             :     return 0;
    2811           0 :   if ((Subtarget->hasMSA())) {
    2812             :     return fastEmitInst_rr(Mips::XOR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2813             :   }
    2814             :   return 0;
    2815             : }
    2816             : 
    2817           4 : unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2818           4 :   switch (VT.SimpleTy) {
    2819           4 :   case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2820           0 :   case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2821           0 :   case MVT::v16i8: return fastEmit_ISD_XOR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2822           0 :   case MVT::v8i16: return fastEmit_ISD_XOR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2823           0 :   case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2824           0 :   case MVT::v2i64: return fastEmit_ISD_XOR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2825             :   default: return 0;
    2826             :   }
    2827             : }
    2828             : 
    2829             : // FastEmit functions for MipsISD::BuildPairF64.
    2830             : 
    2831           0 : unsigned fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2832           0 :   if (RetVT.SimpleTy != MVT::f64)
    2833             :     return 0;
    2834           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
    2835           0 :     return fastEmitInst_rr(Mips::BuildPairF64_64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2836             :   }
    2837           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
    2838           0 :     return fastEmitInst_rr(Mips::BuildPairF64, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2839             :   }
    2840             :   return 0;
    2841             : }
    2842             : 
    2843             : unsigned fastEmit_MipsISD_BuildPairF64_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2844           0 :   switch (VT.SimpleTy) {
    2845           0 :   case MVT::i32: return fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2846             :   default: return 0;
    2847             :   }
    2848             : }
    2849             : 
    2850             : // FastEmit functions for MipsISD::DivRem.
    2851             : 
    2852           0 : unsigned fastEmit_MipsISD_DivRem_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2853           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    2854             :     return 0;
    2855           0 :   if ((Subtarget->inMicroMipsMode())) {
    2856           0 :     return fastEmitInst_rr(Mips::SDIV_MM_Pseudo, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2857             :   }
    2858           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    2859           0 :     return fastEmitInst_rr(Mips::PseudoSDIV, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2860             :   }
    2861             :   return 0;
    2862             : }
    2863             : 
    2864           0 : unsigned fastEmit_MipsISD_DivRem_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2865           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    2866             :     return 0;
    2867           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    2868           0 :     return fastEmitInst_rr(Mips::PseudoDSDIV, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2869             :   }
    2870             :   return 0;
    2871             : }
    2872             : 
    2873           0 : unsigned fastEmit_MipsISD_DivRem_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2874           0 :   switch (VT.SimpleTy) {
    2875           0 :   case MVT::i32: return fastEmit_MipsISD_DivRem_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2876           0 :   case MVT::i64: return fastEmit_MipsISD_DivRem_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2877             :   default: return 0;
    2878             :   }
    2879             : }
    2880             : 
    2881             : // FastEmit functions for MipsISD::DivRem16.
    2882             : 
    2883             : unsigned fastEmit_MipsISD_DivRem16_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2884           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2885             :     return 0;
    2886           0 :   if ((Subtarget->inMips16Mode())) {
    2887             :     return fastEmitInst_rr(Mips::DivRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2888             :   }
    2889             :   return 0;
    2890             : }
    2891             : 
    2892           0 : unsigned fastEmit_MipsISD_DivRem16_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2893           0 :   switch (VT.SimpleTy) {
    2894           0 :   case MVT::i32: return fastEmit_MipsISD_DivRem16_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2895             :   default: return 0;
    2896             :   }
    2897             : }
    2898             : 
    2899             : // FastEmit functions for MipsISD::DivRemU.
    2900             : 
    2901           0 : unsigned fastEmit_MipsISD_DivRemU_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2902           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    2903             :     return 0;
    2904           0 :   if ((Subtarget->inMicroMipsMode())) {
    2905           0 :     return fastEmitInst_rr(Mips::UDIV_MM_Pseudo, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2906             :   }
    2907           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    2908           0 :     return fastEmitInst_rr(Mips::PseudoUDIV, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2909             :   }
    2910             :   return 0;
    2911             : }
    2912             : 
    2913           0 : unsigned fastEmit_MipsISD_DivRemU_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2914           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    2915             :     return 0;
    2916           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    2917           0 :     return fastEmitInst_rr(Mips::PseudoDUDIV, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2918             :   }
    2919             :   return 0;
    2920             : }
    2921             : 
    2922           0 : unsigned fastEmit_MipsISD_DivRemU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2923           0 :   switch (VT.SimpleTy) {
    2924           0 :   case MVT::i32: return fastEmit_MipsISD_DivRemU_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2925           0 :   case MVT::i64: return fastEmit_MipsISD_DivRemU_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2926             :   default: return 0;
    2927             :   }
    2928             : }
    2929             : 
    2930             : // FastEmit functions for MipsISD::DivRemU16.
    2931             : 
    2932             : unsigned fastEmit_MipsISD_DivRemU16_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2933           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2934             :     return 0;
    2935           0 :   if ((Subtarget->inMips16Mode())) {
    2936             :     return fastEmitInst_rr(Mips::DivuRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2937             :   }
    2938             :   return 0;
    2939             : }
    2940             : 
    2941           0 : unsigned fastEmit_MipsISD_DivRemU16_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2942           0 :   switch (VT.SimpleTy) {
    2943           0 :   case MVT::i32: return fastEmit_MipsISD_DivRemU16_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2944             :   default: return 0;
    2945             :   }
    2946             : }
    2947             : 
    2948             : // FastEmit functions for MipsISD::EH_RETURN.
    2949             : 
    2950             : unsigned fastEmit_MipsISD_EH_RETURN_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2951           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2952             :     return 0;
    2953             :   return fastEmitInst_rr(Mips::MIPSeh_return32, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2954             : }
    2955             : 
    2956             : unsigned fastEmit_MipsISD_EH_RETURN_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2957           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2958             :     return 0;
    2959             :   return fastEmitInst_rr(Mips::MIPSeh_return64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2960             : }
    2961             : 
    2962           0 : unsigned fastEmit_MipsISD_EH_RETURN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2963           0 :   switch (VT.SimpleTy) {
    2964           0 :   case MVT::i32: return fastEmit_MipsISD_EH_RETURN_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2965           0 :   case MVT::i64: return fastEmit_MipsISD_EH_RETURN_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2966             :   default: return 0;
    2967             :   }
    2968             : }
    2969             : 
    2970             : // FastEmit functions for MipsISD::ILVEV.
    2971             : 
    2972           0 : unsigned fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2973           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2974             :     return 0;
    2975           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2976           0 :     return fastEmitInst_rr(Mips::ILVEV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2977             :   }
    2978             :   return 0;
    2979             : }
    2980             : 
    2981           0 : unsigned fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2982           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2983             :     return 0;
    2984           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2985           0 :     return fastEmitInst_rr(Mips::ILVEV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2986             :   }
    2987             :   return 0;
    2988             : }
    2989             : 
    2990           0 : unsigned fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2991           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2992             :     return 0;
    2993           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2994           0 :     return fastEmitInst_rr(Mips::ILVEV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2995             :   }
    2996             :   return 0;
    2997             : }
    2998             : 
    2999           0 : unsigned fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3000           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3001             :     return 0;
    3002           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3003           0 :     return fastEmitInst_rr(Mips::ILVEV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3004             :   }
    3005             :   return 0;
    3006             : }
    3007             : 
    3008           0 : unsigned fastEmit_MipsISD_ILVEV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3009           0 :   switch (VT.SimpleTy) {
    3010           0 :   case MVT::v16i8: return fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3011           0 :   case MVT::v8i16: return fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3012           0 :   case MVT::v4i32: return fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3013           0 :   case MVT::v2i64: return fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3014             :   default: return 0;
    3015             :   }
    3016             : }
    3017             : 
    3018             : // FastEmit functions for MipsISD::ILVL.
    3019             : 
    3020           0 : unsigned fastEmit_MipsISD_ILVL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3021           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3022             :     return 0;
    3023           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3024           0 :     return fastEmitInst_rr(Mips::ILVL_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3025             :   }
    3026             :   return 0;
    3027             : }
    3028             : 
    3029           0 : unsigned fastEmit_MipsISD_ILVL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3030           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3031             :     return 0;
    3032           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3033           0 :     return fastEmitInst_rr(Mips::ILVL_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3034             :   }
    3035             :   return 0;
    3036             : }
    3037             : 
    3038           0 : unsigned fastEmit_MipsISD_ILVL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3039           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3040             :     return 0;
    3041           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3042           0 :     return fastEmitInst_rr(Mips::ILVL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3043             :   }
    3044             :   return 0;
    3045             : }
    3046             : 
    3047           0 : unsigned fastEmit_MipsISD_ILVL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3048           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3049             :     return 0;
    3050           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3051           0 :     return fastEmitInst_rr(Mips::ILVL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3052             :   }
    3053             :   return 0;
    3054             : }
    3055             : 
    3056           0 : unsigned fastEmit_MipsISD_ILVL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3057           0 :   switch (VT.SimpleTy) {
    3058           0 :   case MVT::v16i8: return fastEmit_MipsISD_ILVL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3059           0 :   case MVT::v8i16: return fastEmit_MipsISD_ILVL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3060           0 :   case MVT::v4i32: return fastEmit_MipsISD_ILVL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3061           0 :   case MVT::v2i64: return fastEmit_MipsISD_ILVL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3062             :   default: return 0;
    3063             :   }
    3064             : }
    3065             : 
    3066             : // FastEmit functions for MipsISD::ILVOD.
    3067             : 
    3068           0 : unsigned fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3069           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3070             :     return 0;
    3071           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3072           0 :     return fastEmitInst_rr(Mips::ILVOD_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3073             :   }
    3074             :   return 0;
    3075             : }
    3076             : 
    3077           0 : unsigned fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3078           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3079             :     return 0;
    3080           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3081           0 :     return fastEmitInst_rr(Mips::ILVOD_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3082             :   }
    3083             :   return 0;
    3084             : }
    3085             : 
    3086           0 : unsigned fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3087           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3088             :     return 0;
    3089           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3090           0 :     return fastEmitInst_rr(Mips::ILVOD_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3091             :   }
    3092             :   return 0;
    3093             : }
    3094             : 
    3095           0 : unsigned fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3096           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3097             :     return 0;
    3098           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3099           0 :     return fastEmitInst_rr(Mips::ILVOD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3100             :   }
    3101             :   return 0;
    3102             : }
    3103             : 
    3104           0 : unsigned fastEmit_MipsISD_ILVOD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3105           0 :   switch (VT.SimpleTy) {
    3106           0 :   case MVT::v16i8: return fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3107           0 :   case MVT::v8i16: return fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3108           0 :   case MVT::v4i32: return fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3109           0 :   case MVT::v2i64: return fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3110             :   default: return 0;
    3111             :   }
    3112             : }
    3113             : 
    3114             : // FastEmit functions for MipsISD::ILVR.
    3115             : 
    3116           0 : unsigned fastEmit_MipsISD_ILVR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3117           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3118             :     return 0;
    3119           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3120           0 :     return fastEmitInst_rr(Mips::ILVR_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3121             :   }
    3122             :   return 0;
    3123             : }
    3124             : 
    3125           0 : unsigned fastEmit_MipsISD_ILVR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3126           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3127             :     return 0;
    3128           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3129           0 :     return fastEmitInst_rr(Mips::ILVR_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3130             :   }
    3131             :   return 0;
    3132             : }
    3133             : 
    3134           0 : unsigned fastEmit_MipsISD_ILVR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3135           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3136             :     return 0;
    3137           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3138           0 :     return fastEmitInst_rr(Mips::ILVR_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3139             :   }
    3140             :   return 0;
    3141             : }
    3142             : 
    3143           0 : unsigned fastEmit_MipsISD_ILVR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3144           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3145             :     return 0;
    3146           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3147           0 :     return fastEmitInst_rr(Mips::ILVR_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3148             :   }
    3149             :   return 0;
    3150             : }
    3151             : 
    3152           0 : unsigned fastEmit_MipsISD_ILVR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3153           0 :   switch (VT.SimpleTy) {
    3154           0 :   case MVT::v16i8: return fastEmit_MipsISD_ILVR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3155           0 :   case MVT::v8i16: return fastEmit_MipsISD_ILVR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3156           0 :   case MVT::v4i32: return fastEmit_MipsISD_ILVR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3157           0 :   case MVT::v2i64: return fastEmit_MipsISD_ILVR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3158             :   default: return 0;
    3159             :   }
    3160             : }
    3161             : 
    3162             : // FastEmit functions for MipsISD::MTLOHI.
    3163             : 
    3164             : unsigned fastEmit_MipsISD_MTLOHI_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3165           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    3166             :     return 0;
    3167           0 :   if ((Subtarget->hasStandardEncoding())) {
    3168             :     return fastEmitInst_rr(Mips::PseudoMTLOHI_DSP, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3169             :   }
    3170             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    3171             :     return fastEmitInst_rr(Mips::PseudoMTLOHI, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3172             :   }
    3173             :   return 0;
    3174             : }
    3175             : 
    3176           0 : unsigned fastEmit_MipsISD_MTLOHI_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3177           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    3178             :     return 0;
    3179           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    3180           0 :     return fastEmitInst_rr(Mips::PseudoMTLOHI64, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3181             :   }
    3182             :   return 0;
    3183             : }
    3184             : 
    3185           0 : unsigned fastEmit_MipsISD_MTLOHI_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3186           0 :   switch (VT.SimpleTy) {
    3187           0 :   case MVT::i32: return fastEmit_MipsISD_MTLOHI_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3188           0 :   case MVT::i64: return fastEmit_MipsISD_MTLOHI_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3189             :   default: return 0;
    3190             :   }
    3191             : }
    3192             : 
    3193             : // FastEmit functions for MipsISD::Mult.
    3194             : 
    3195           0 : unsigned fastEmit_MipsISD_Mult_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3196           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    3197             :     return 0;
    3198           0 :   if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
    3199           0 :     return fastEmitInst_rr(Mips::MULT_DSP_MM, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3200             :   }
    3201           0 :   if ((Subtarget->hasDSP())) {
    3202           0 :     return fastEmitInst_rr(Mips::MULT_DSP, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3203             :   }
    3204           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    3205           0 :     return fastEmitInst_rr(Mips::PseudoMULT, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3206             :   }
    3207             :   return 0;
    3208             : }
    3209             : 
    3210           0 : unsigned fastEmit_MipsISD_Mult_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3211           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    3212             :     return 0;
    3213           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    3214           0 :     return fastEmitInst_rr(Mips::PseudoDMULT, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3215             :   }
    3216             :   return 0;
    3217             : }
    3218             : 
    3219           0 : unsigned fastEmit_MipsISD_Mult_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3220           0 :   switch (VT.SimpleTy) {
    3221           0 :   case MVT::i32: return fastEmit_MipsISD_Mult_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3222           0 :   case MVT::i64: return fastEmit_MipsISD_Mult_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3223             :   default: return 0;
    3224             :   }
    3225             : }
    3226             : 
    3227             : // FastEmit functions for MipsISD::Multu.
    3228             : 
    3229           0 : unsigned fastEmit_MipsISD_Multu_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3230           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    3231             :     return 0;
    3232           0 :   if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
    3233           0 :     return fastEmitInst_rr(Mips::MULTU_DSP_MM, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3234             :   }
    3235           0 :   if ((Subtarget->hasDSP())) {
    3236           0 :     return fastEmitInst_rr(Mips::MULTU_DSP, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3237             :   }
    3238           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    3239           0 :     return fastEmitInst_rr(Mips::PseudoMULTu, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3240             :   }
    3241             :   return 0;
    3242             : }
    3243             : 
    3244           0 : unsigned fastEmit_MipsISD_Multu_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3245           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    3246             :     return 0;
    3247           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    3248           0 :     return fastEmitInst_rr(Mips::PseudoDMULTu, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3249             :   }
    3250             :   return 0;
    3251             : }
    3252             : 
    3253           0 : unsigned fastEmit_MipsISD_Multu_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3254           0 :   switch (VT.SimpleTy) {
    3255           0 :   case MVT::i32: return fastEmit_MipsISD_Multu_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3256           0 :   case MVT::i64: return fastEmit_MipsISD_Multu_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3257             :   default: return 0;
    3258             :   }
    3259             : }
    3260             : 
    3261             : // FastEmit functions for MipsISD::PCKEV.
    3262             : 
    3263           0 : unsigned fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3264           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3265             :     return 0;
    3266           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3267           0 :     return fastEmitInst_rr(Mips::PCKEV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3268             :   }
    3269             :   return 0;
    3270             : }
    3271             : 
    3272           0 : unsigned fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3273           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3274             :     return 0;
    3275           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3276           0 :     return fastEmitInst_rr(Mips::PCKEV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3277             :   }
    3278             :   return 0;
    3279             : }
    3280             : 
    3281           0 : unsigned fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3282           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3283             :     return 0;
    3284           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3285           0 :     return fastEmitInst_rr(Mips::PCKEV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3286             :   }
    3287             :   return 0;
    3288             : }
    3289             : 
    3290           0 : unsigned fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3291           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3292             :     return 0;
    3293           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3294           0 :     return fastEmitInst_rr(Mips::PCKEV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3295             :   }
    3296             :   return 0;
    3297             : }
    3298             : 
    3299           0 : unsigned fastEmit_MipsISD_PCKEV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3300           0 :   switch (VT.SimpleTy) {
    3301           0 :   case MVT::v16i8: return fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3302           0 :   case MVT::v8i16: return fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3303           0 :   case MVT::v4i32: return fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3304           0 :   case MVT::v2i64: return fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3305             :   default: return 0;
    3306             :   }
    3307             : }
    3308             : 
    3309             : // FastEmit functions for MipsISD::PCKOD.
    3310             : 
    3311           0 : unsigned fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3312           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3313             :     return 0;
    3314           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3315           0 :     return fastEmitInst_rr(Mips::PCKOD_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3316             :   }
    3317             :   return 0;
    3318             : }
    3319             : 
    3320           0 : unsigned fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3321           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3322             :     return 0;
    3323           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3324           0 :     return fastEmitInst_rr(Mips::PCKOD_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3325             :   }
    3326             :   return 0;
    3327             : }
    3328             : 
    3329           0 : unsigned fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3330           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3331             :     return 0;
    3332           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3333           0 :     return fastEmitInst_rr(Mips::PCKOD_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3334             :   }
    3335             :   return 0;
    3336             : }
    3337             : 
    3338           0 : unsigned fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3339           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3340             :     return 0;
    3341           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3342           0 :     return fastEmitInst_rr(Mips::PCKOD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3343             :   }
    3344             :   return 0;
    3345             : }
    3346             : 
    3347           0 : unsigned fastEmit_MipsISD_PCKOD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3348           0 :   switch (VT.SimpleTy) {
    3349           0 :   case MVT::v16i8: return fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3350           0 :   case MVT::v8i16: return fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3351           0 :   case MVT::v4i32: return fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3352           0 :   case MVT::v2i64: return fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3353             :   default: return 0;
    3354             :   }
    3355             : }
    3356             : 
    3357             : // FastEmit functions for MipsISD::VNOR.
    3358             : 
    3359           0 : unsigned fastEmit_MipsISD_VNOR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3360           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3361             :     return 0;
    3362           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3363           0 :     return fastEmitInst_rr(Mips::NOR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3364             :   }
    3365             :   return 0;
    3366             : }
    3367             : 
    3368             : unsigned fastEmit_MipsISD_VNOR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3369           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3370             :     return 0;
    3371           0 :   if ((Subtarget->hasMSA())) {
    3372             :     return fastEmitInst_rr(Mips::NOR_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3373             :   }
    3374             :   return 0;
    3375             : }
    3376             : 
    3377             : unsigned fastEmit_MipsISD_VNOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3378           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3379             :     return 0;
    3380           0 :   if ((Subtarget->hasMSA())) {
    3381             :     return fastEmitInst_rr(Mips::NOR_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3382             :   }
    3383             :   return 0;
    3384             : }
    3385             : 
    3386             : unsigned fastEmit_MipsISD_VNOR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3387           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3388             :     return 0;
    3389           0 :   if ((Subtarget->hasMSA())) {
    3390             :     return fastEmitInst_rr(Mips::NOR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3391             :   }
    3392             :   return 0;
    3393             : }
    3394             : 
    3395           0 : unsigned fastEmit_MipsISD_VNOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3396           0 :   switch (VT.SimpleTy) {
    3397           0 :   case MVT::v16i8: return fastEmit_MipsISD_VNOR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3398           0 :   case MVT::v8i16: return fastEmit_MipsISD_VNOR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3399           0 :   case MVT::v4i32: return fastEmit_MipsISD_VNOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3400           0 :   case MVT::v2i64: return fastEmit_MipsISD_VNOR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3401             :   default: return 0;
    3402             :   }
    3403             : }
    3404             : 
    3405             : // Top-level FastEmit function.
    3406             : 
    3407          37 : unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) override {
    3408          37 :   switch (Opcode) {
    3409           6 :   case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3410           0 :   case ISD::ADDC: return fastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3411           0 :   case ISD::ADDE: return fastEmit_ISD_ADDE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3412           5 :   case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3413           0 :   case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3414           0 :   case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3415           0 :   case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3416           0 :   case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3417           2 :   case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3418           0 :   case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3419           0 :   case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3420           4 :   case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3421           0 :   case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3422           4 :   case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3423           0 :   case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3424           0 :   case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3425           0 :   case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3426           0 :   case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3427           4 :   case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3428           0 :   case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3429           0 :   case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3430           0 :   case ISD::SUBC: return fastEmit_ISD_SUBC_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3431           4 :   case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3432           0 :   case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3433           0 :   case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3434           4 :   case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3435           4 :   case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3436           0 :   case MipsISD::BuildPairF64: return fastEmit_MipsISD_BuildPairF64_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3437           0 :   case MipsISD::DivRem: return fastEmit_MipsISD_DivRem_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3438           0 :   case MipsISD::DivRem16: return fastEmit_MipsISD_DivRem16_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3439           0 :   case MipsISD::DivRemU: return fastEmit_MipsISD_DivRemU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3440           0 :   case MipsISD::DivRemU16: return fastEmit_MipsISD_DivRemU16_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3441           0 :   case MipsISD::EH_RETURN: return fastEmit_MipsISD_EH_RETURN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3442           0 :   case MipsISD::ILVEV: return fastEmit_MipsISD_ILVEV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3443           0 :   case MipsISD::ILVL: return fastEmit_MipsISD_ILVL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3444           0 :   case MipsISD::ILVOD: return fastEmit_MipsISD_ILVOD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3445           0 :   case MipsISD::ILVR: return fastEmit_MipsISD_ILVR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3446           0 :   case MipsISD::MTLOHI: return fastEmit_MipsISD_MTLOHI_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3447           0 :   case MipsISD::Mult: return fastEmit_MipsISD_Mult_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3448           0 :   case MipsISD::Multu: return fastEmit_MipsISD_Multu_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3449           0 :   case MipsISD::PCKEV: return fastEmit_MipsISD_PCKEV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3450           0 :   case MipsISD::PCKOD: return fastEmit_MipsISD_PCKOD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3451           0 :   case MipsISD::VNOR: return fastEmit_MipsISD_VNOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3452             :   default: return 0;
    3453             :   }
    3454             : }
    3455             : 
    3456             : // FastEmit functions for MipsISD::ExtractElementF64.
    3457             : 
    3458           0 : unsigned fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3459           0 :   if (RetVT.SimpleTy != MVT::i32)
    3460             :     return 0;
    3461           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
    3462           0 :     return fastEmitInst_ri(Mips::ExtractElementF64_64, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3463             :   }
    3464           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
    3465           0 :     return fastEmitInst_ri(Mips::ExtractElementF64, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3466             :   }
    3467             :   return 0;
    3468             : }
    3469             : 
    3470             : unsigned fastEmit_MipsISD_ExtractElementF64_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3471           0 :   switch (VT.SimpleTy) {
    3472           0 :   case MVT::f64: return fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(RetVT, Op0, Op0IsKill, imm1);
    3473             :   default: return 0;
    3474             :   }
    3475             : }
    3476             : 
    3477             : // FastEmit functions for MipsISD::SHLL_DSP.
    3478             : 
    3479             : unsigned fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3480           0 :   if (RetVT.SimpleTy != MVT::v4i8)
    3481             :     return 0;
    3482           0 :   if ((Subtarget->hasDSP())) {
    3483           0 :     return fastEmitInst_ri(Mips::SHLL_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
    3484             :   }
    3485             :   return 0;
    3486             : }
    3487             : 
    3488             : unsigned fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3489           0 :   if (RetVT.SimpleTy != MVT::v2i16)
    3490             :     return 0;
    3491           0 :   if ((Subtarget->hasDSP())) {
    3492           0 :     return fastEmitInst_ri(Mips::SHLL_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
    3493             :   }
    3494             :   return 0;
    3495             : }
    3496             : 
    3497           0 : unsigned fastEmit_MipsISD_SHLL_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3498           0 :   switch (VT.SimpleTy) {
    3499           0 :   case MVT::v4i8: return fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(RetVT, Op0, Op0IsKill, imm1);
    3500           0 :   case MVT::v2i16: return fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(RetVT, Op0, Op0IsKill, imm1);
    3501             :   default: return 0;
    3502             :   }
    3503             : }
    3504             : 
    3505             : // FastEmit functions for MipsISD::SHRA_DSP.
    3506             : 
    3507             : unsigned fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3508           0 :   if (RetVT.SimpleTy != MVT::v4i8)
    3509             :     return 0;
    3510           0 :   if ((Subtarget->hasDSPR2())) {
    3511           0 :     return fastEmitInst_ri(Mips::SHRA_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
    3512             :   }
    3513             :   return 0;
    3514             : }
    3515             : 
    3516             : unsigned fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3517           0 :   if (RetVT.SimpleTy != MVT::v2i16)
    3518             :     return 0;
    3519           0 :   if ((Subtarget->hasDSP())) {
    3520           0 :     return fastEmitInst_ri(Mips::SHRA_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
    3521             :   }
    3522             :   return 0;
    3523             : }
    3524             : 
    3525           0 : unsigned fastEmit_MipsISD_SHRA_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3526           0 :   switch (VT.SimpleTy) {
    3527           0 :   case MVT::v4i8: return fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(RetVT, Op0, Op0IsKill, imm1);
    3528           0 :   case MVT::v2i16: return fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(RetVT, Op0, Op0IsKill, imm1);
    3529             :   default: return 0;
    3530             :   }
    3531             : }
    3532             : 
    3533             : // FastEmit functions for MipsISD::SHRL_DSP.
    3534             : 
    3535             : unsigned fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3536           0 :   if (RetVT.SimpleTy != MVT::v4i8)
    3537             :     return 0;
    3538           0 :   if ((Subtarget->hasDSP())) {
    3539           0 :     return fastEmitInst_ri(Mips::SHRL_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
    3540             :   }
    3541             :   return 0;
    3542             : }
    3543             : 
    3544             : unsigned fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3545           0 :   if (RetVT.SimpleTy != MVT::v2i16)
    3546             :     return 0;
    3547           0 :   if ((Subtarget->hasDSPR2())) {
    3548           0 :     return fastEmitInst_ri(Mips::SHRL_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
    3549             :   }
    3550             :   return 0;
    3551             : }
    3552             : 
    3553           0 : unsigned fastEmit_MipsISD_SHRL_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3554           0 :   switch (VT.SimpleTy) {
    3555           0 :   case MVT::v4i8: return fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(RetVT, Op0, Op0IsKill, imm1);
    3556           0 :   case MVT::v2i16: return fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(RetVT, Op0, Op0IsKill, imm1);
    3557             :   default: return 0;
    3558             :   }
    3559             : }
    3560             : 
    3561             : // Top-level FastEmit function.
    3562             : 
    3563           7 : unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) override {
    3564          14 :   if (VT == MVT::i32 && Predicate_immZExt5(imm1))
    3565           7 :     if (unsigned Reg = fastEmit_ri_Predicate_immZExt5(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3566             :       return Reg;
    3567             : 
    3568          14 :   if (VT == MVT::i32 && Predicate_immZExt6(imm1))
    3569           7 :     if (unsigned Reg = fastEmit_ri_Predicate_immZExt6(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3570             :       return Reg;
    3571             : 
    3572           7 :   if (VT == MVT::iPTR && Predicate_immZExt2Ptr(imm1))
    3573           0 :     if (unsigned Reg = fastEmit_ri_Predicate_immZExt2Ptr(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3574             :       return Reg;
    3575             : 
    3576           7 :   if (VT == MVT::iPTR && Predicate_immZExt1Ptr(imm1))
    3577           0 :     if (unsigned Reg = fastEmit_ri_Predicate_immZExt1Ptr(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3578             :       return Reg;
    3579             : 
    3580           7 :   if (VT == MVT::i32 && Predicate_immZExt4(imm1))
    3581           7 :     if (unsigned Reg = fastEmit_ri_Predicate_immZExt4(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3582             :       return Reg;
    3583             : 
    3584           7 :   if (VT == MVT::i32 && Predicate_immSExtAddiur2(imm1))
    3585           2 :     if (unsigned Reg = fastEmit_ri_Predicate_immSExtAddiur2(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3586             :       return Reg;
    3587             : 
    3588          14 :   if (VT == MVT::i32 && Predicate_immSExtAddius5(imm1))
    3589           8 :     if (unsigned Reg = fastEmit_ri_Predicate_immSExtAddius5(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3590             :       return Reg;
    3591             : 
    3592           7 :   if (VT == MVT::i32 && Predicate_immZExtAndi16(imm1))
    3593           1 :     if (unsigned Reg = fastEmit_ri_Predicate_immZExtAndi16(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3594             :       return Reg;
    3595             : 
    3596          14 :   if (VT == MVT::i32 && Predicate_immZExt2Shift(imm1))
    3597           1 :     if (unsigned Reg = fastEmit_ri_Predicate_immZExt2Shift(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3598             :       return Reg;
    3599             : 
    3600           7 :   switch (Opcode) {
    3601           0 :   case MipsISD::ExtractElementF64: return fastEmit_MipsISD_ExtractElementF64_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    3602           0 :   case MipsISD::SHLL_DSP: return fastEmit_MipsISD_SHLL_DSP_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    3603           0 :   case MipsISD::SHRA_DSP: return fastEmit_MipsISD_SHRA_DSP_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    3604           0 :   case MipsISD::SHRL_DSP: return fastEmit_MipsISD_SHRL_DSP_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    3605             :   default: return 0;
    3606             :   }
    3607             : }
    3608             : 
    3609             : // FastEmit functions for ISD::ROTR.
    3610             : 
    3611           0 : unsigned fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3612           0 :   if (RetVT.SimpleTy != MVT::i32)
    3613             :     return 0;
    3614           0 :   if ((Subtarget->inMicroMipsMode())) {
    3615           0 :     return fastEmitInst_ri(Mips::ROTR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3616             :   }
    3617           0 :   if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3618           0 :     return fastEmitInst_ri(Mips::ROTR, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3619             :   }
    3620             :   return 0;
    3621             : }
    3622             : 
    3623             : unsigned fastEmit_ISD_ROTR_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3624           0 :   switch (VT.SimpleTy) {
    3625           0 :   case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1);
    3626             :   default: return 0;
    3627             :   }
    3628             : }
    3629             : 
    3630             : // FastEmit functions for ISD::SHL.
    3631             : 
    3632           0 : unsigned fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3633           0 :   if (RetVT.SimpleTy != MVT::i32)
    3634             :     return 0;
    3635           0 :   if ((Subtarget->inMicroMipsMode())) {
    3636           0 :     return fastEmitInst_ri(Mips::SLL_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3637             :   }
    3638           0 :   if ((Subtarget->inMips16Mode())) {
    3639           0 :     return fastEmitInst_ri(Mips::SllX16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, imm1);
    3640             :   }
    3641             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3642           0 :     return fastEmitInst_ri(Mips::SLL, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3643             :   }
    3644             :   return 0;
    3645             : }
    3646             : 
    3647             : unsigned fastEmit_ISD_SHL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3648           0 :   switch (VT.SimpleTy) {
    3649           0 :   case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1);
    3650             :   default: return 0;
    3651             :   }
    3652             : }
    3653             : 
    3654             : // FastEmit functions for ISD::SRA.
    3655             : 
    3656           0 : unsigned fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3657           0 :   if (RetVT.SimpleTy != MVT::i32)
    3658             :     return 0;
    3659           0 :   if ((Subtarget->inMicroMipsMode())) {
    3660           0 :     return fastEmitInst_ri(Mips::SRA_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3661             :   }
    3662           0 :   if ((Subtarget->inMips16Mode())) {
    3663           0 :     return fastEmitInst_ri(Mips::SraX16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, imm1);
    3664             :   }
    3665             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3666           0 :     return fastEmitInst_ri(Mips::SRA, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3667             :   }
    3668             :   return 0;
    3669             : }
    3670             : 
    3671             : unsigned fastEmit_ISD_SRA_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3672           0 :   switch (VT.SimpleTy) {
    3673           0 :   case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1);
    3674             :   default: return 0;
    3675             :   }
    3676             : }
    3677             : 
    3678             : // FastEmit functions for ISD::SRL.
    3679             : 
    3680           0 : unsigned fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3681           0 :   if (RetVT.SimpleTy != MVT::i32)
    3682             :     return 0;
    3683           0 :   if ((Subtarget->inMicroMipsMode())) {
    3684           0 :     return fastEmitInst_ri(Mips::SRL_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3685             :   }
    3686           0 :   if ((Subtarget->inMips16Mode())) {
    3687           0 :     return fastEmitInst_ri(Mips::SrlX16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, imm1);
    3688             :   }
    3689             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3690           0 :     return fastEmitInst_ri(Mips::SRL, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3691             :   }
    3692             :   return 0;
    3693             : }
    3694             : 
    3695             : unsigned fastEmit_ISD_SRL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3696           0 :   switch (VT.SimpleTy) {
    3697           0 :   case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1);
    3698             :   default: return 0;
    3699             :   }
    3700             : }
    3701             : 
    3702             : // Top-level FastEmit function.
    3703             : 
    3704           7 : unsigned fastEmit_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3705           7 :   switch (Opcode) {
    3706           0 :   case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1);
    3707           0 :   case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1);
    3708           0 :   case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1);
    3709           0 :   case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1);
    3710             :   default: return 0;
    3711             :   }
    3712             : }
    3713             : 
    3714             : // FastEmit functions for ISD::ROTR.
    3715             : 
    3716           0 : unsigned fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3717           0 :   if (RetVT.SimpleTy != MVT::i64)
    3718             :     return 0;
    3719           0 :   if ((Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3720           0 :     return fastEmitInst_ri(Mips::DROTR, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
    3721             :   }
    3722             :   return 0;
    3723             : }
    3724             : 
    3725             : unsigned fastEmit_ISD_ROTR_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3726           0 :   switch (VT.SimpleTy) {
    3727           0 :   case MVT::i64: return fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1);
    3728             :   default: return 0;
    3729             :   }
    3730             : }
    3731             : 
    3732             : // FastEmit functions for ISD::SHL.
    3733             : 
    3734           0 : unsigned fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3735           0 :   if (RetVT.SimpleTy != MVT::i64)
    3736             :     return 0;
    3737           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3738           0 :     return fastEmitInst_ri(Mips::DSLL, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
    3739             :   }
    3740             :   return 0;
    3741             : }
    3742             : 
    3743             : unsigned fastEmit_ISD_SHL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3744           0 :   switch (VT.SimpleTy) {
    3745           0 :   case MVT::i64: return fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1);
    3746             :   default: return 0;
    3747             :   }
    3748             : }
    3749             : 
    3750             : // FastEmit functions for ISD::SRA.
    3751             : 
    3752           0 : unsigned fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3753           0 :   if (RetVT.SimpleTy != MVT::i64)
    3754             :     return 0;
    3755           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3756           0 :     return fastEmitInst_ri(Mips::DSRA, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
    3757             :   }
    3758             :   return 0;
    3759             : }
    3760             : 
    3761             : unsigned fastEmit_ISD_SRA_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3762           0 :   switch (VT.SimpleTy) {
    3763           0 :   case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1);
    3764             :   default: return 0;
    3765             :   }
    3766             : }
    3767             : 
    3768             : // FastEmit functions for ISD::SRL.
    3769             : 
    3770           0 : unsigned fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3771           0 :   if (RetVT.SimpleTy != MVT::i64)
    3772             :     return 0;
    3773           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3774           0 :     return fastEmitInst_ri(Mips::DSRL, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
    3775             :   }
    3776             :   return 0;
    3777             : }
    3778             : 
    3779             : unsigned fastEmit_ISD_SRL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3780           0 :   switch (VT.SimpleTy) {
    3781           0 :   case MVT::i64: return fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1);
    3782             :   default: return 0;
    3783             :   }
    3784             : }
    3785             : 
    3786             : // Top-level FastEmit function.
    3787             : 
    3788           7 : unsigned fastEmit_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3789           7 :   switch (Opcode) {
    3790           0 :   case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1);
    3791           0 :   case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1);
    3792           0 :   case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1);
    3793           0 :   case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1);
    3794             :   default: return 0;
    3795             :   }
    3796             : }
    3797             : 
    3798             : // FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
    3799             : 
    3800             : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3801           0 :   if (RetVT.SimpleTy != MVT::f32)
    3802             :     return 0;
    3803           0 :   if ((Subtarget->hasMSA())) {
    3804           0 :     return fastEmitInst_ri(Mips::COPY_FW_PSEUDO, &Mips::FGR32RegClass, Op0, Op0IsKill, imm1);
    3805             :   }
    3806             :   return 0;
    3807             : }
    3808             : 
    3809           0 : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3810           0 :   switch (VT.SimpleTy) {
    3811           0 :   case MVT::v4f32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(RetVT, Op0, Op0IsKill, imm1);
    3812             :   default: return 0;
    3813             :   }
    3814             : }
    3815             : 
    3816             : // Top-level FastEmit function.
    3817             : 
    3818             : unsigned fastEmit_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3819           0 :   switch (Opcode) {
    3820           0 :   case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(VT, RetVT, Op0, Op0IsKill, imm1);
    3821             :   default: return 0;
    3822             :   }
    3823             : }
    3824             : 
    3825             : // FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
    3826             : 
    3827             : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3828           0 :   if (RetVT.SimpleTy != MVT::f64)
    3829             :     return 0;
    3830           0 :   if ((Subtarget->hasMSA())) {
    3831           0 :     return fastEmitInst_ri(Mips::COPY_FD_PSEUDO, &Mips::FGR64RegClass, Op0, Op0IsKill, imm1);
    3832             :   }
    3833             :   return 0;
    3834             : }
    3835             : 
    3836           0 : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3837           0 :   switch (VT.SimpleTy) {
    3838           0 :   case MVT::v2f64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(RetVT, Op0, Op0IsKill, imm1);
    3839             :   default: return 0;
    3840             :   }
    3841             : }
    3842             : 
    3843             : // Top-level FastEmit function.
    3844             : 
    3845             : unsigned fastEmit_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3846           0 :   switch (Opcode) {
    3847           0 :   case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(VT, RetVT, Op0, Op0IsKill, imm1);
    3848             :   default: return 0;
    3849             :   }
    3850             : }
    3851             : 
    3852             : // FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
    3853             : 
    3854             : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3855           0 :   if (RetVT.SimpleTy != MVT::i32)
    3856             :     return 0;
    3857           0 :   if ((Subtarget->hasMSA())) {
    3858           0 :     return fastEmitInst_ri(Mips::COPY_S_W, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3859             :   }
    3860             :   return 0;
    3861             : }
    3862             : 
    3863           0 : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3864           0 :   switch (VT.SimpleTy) {
    3865           0 :   case MVT::v4i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(RetVT, Op0, Op0IsKill, imm1);
    3866             :   default: return 0;
    3867             :   }
    3868             : }
    3869             : 
    3870             : // Top-level FastEmit function.
    3871             : 
    3872             : unsigned fastEmit_ri_Predicate_immZExt4(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3873           7 :   switch (Opcode) {
    3874           0 :   case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(VT, RetVT, Op0, Op0IsKill, imm1);
    3875             :   default: return 0;
    3876             :   }
    3877             : }
    3878             : 
    3879             : // FastEmit functions for ISD::ADD.
    3880             : 
    3881             : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3882           1 :   if (RetVT.SimpleTy != MVT::i32)
    3883             :     return 0;
    3884           1 :   if ((Subtarget->inMicroMipsMode())) {
    3885           0 :     return fastEmitInst_ri(Mips::ADDIUR2_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
    3886             :   }
    3887             :   return 0;
    3888             : }
    3889             : 
    3890           1 : unsigned fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3891           1 :   switch (VT.SimpleTy) {
    3892           1 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(RetVT, Op0, Op0IsKill, imm1);
    3893             :   default: return 0;
    3894             :   }
    3895             : }
    3896             : 
    3897             : // Top-level FastEmit function.
    3898             : 
    3899             : unsigned fastEmit_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3900           1 :   switch (Opcode) {
    3901           1 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(VT, RetVT, Op0, Op0IsKill, imm1);
    3902             :   default: return 0;
    3903             :   }
    3904             : }
    3905             : 
    3906             : // FastEmit functions for ISD::ADD.
    3907             : 
    3908             : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3909           1 :   if (RetVT.SimpleTy != MVT::i32)
    3910             :     return 0;
    3911           1 :   if ((Subtarget->inMicroMipsMode())) {
    3912           0 :     return fastEmitInst_ri(Mips::ADDIUS5_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3913             :   }
    3914             :   return 0;
    3915             : }
    3916             : 
    3917           1 : unsigned fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3918           1 :   switch (VT.SimpleTy) {
    3919           1 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(RetVT, Op0, Op0IsKill, imm1);
    3920             :   default: return 0;
    3921             :   }
    3922             : }
    3923             : 
    3924             : // Top-level FastEmit function.
    3925             : 
    3926             : unsigned fastEmit_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3927           7 :   switch (Opcode) {
    3928           1 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(VT, RetVT, Op0, Op0IsKill, imm1);
    3929             :   default: return 0;
    3930             :   }
    3931             : }
    3932             : 
    3933             : // FastEmit functions for ISD::AND.
    3934             : 
    3935           0 : unsigned fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3936           0 :   if (RetVT.SimpleTy != MVT::i32)
    3937             :     return 0;
    3938           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
    3939           0 :     return fastEmitInst_ri(Mips::ANDI16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
    3940             :   }
    3941           0 :   if ((Subtarget->inMicroMipsMode())) {
    3942           0 :     return fastEmitInst_ri(Mips::ANDI16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
    3943             :   }
    3944             :   return 0;
    3945             : }
    3946             : 
    3947             : unsigned fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3948           0 :   switch (VT.SimpleTy) {
    3949           0 :   case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(RetVT, Op0, Op0IsKill, imm1);
    3950             :   default: return 0;
    3951             :   }
    3952             : }
    3953             : 
    3954             : // Top-level FastEmit function.
    3955             : 
    3956           1 : unsigned fastEmit_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3957           1 :   switch (Opcode) {
    3958           0 :   case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(VT, RetVT, Op0, Op0IsKill, imm1);
    3959             :   default: return 0;
    3960             :   }
    3961             : }
    3962             : 
    3963             : // FastEmit functions for ISD::SHL.
    3964             : 
    3965             : unsigned fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3966           0 :   if (RetVT.SimpleTy != MVT::i32)
    3967             :     return 0;
    3968           0 :   if ((Subtarget->inMicroMipsMode())) {
    3969           0 :     return fastEmitInst_ri(Mips::SLL16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
    3970             :   }
    3971             :   return 0;
    3972             : }
    3973             : 
    3974           0 : unsigned fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3975           0 :   switch (VT.SimpleTy) {
    3976           0 :   case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, Op0IsKill, imm1);
    3977             :   default: return 0;
    3978             :   }
    3979             : }
    3980             : 
    3981             : // FastEmit functions for ISD::SRL.
    3982             : 
    3983             : unsigned fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3984           0 :   if (RetVT.SimpleTy != MVT::i32)
    3985             :     return 0;
    3986           0 :   if ((Subtarget->inMicroMipsMode())) {
    3987           0 :     return fastEmitInst_ri(Mips::SRL16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
    3988             :   }
    3989             :   return 0;
    3990             : }
    3991             : 
    3992           0 : unsigned fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3993           0 :   switch (VT.SimpleTy) {
    3994           0 :   case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, Op0IsKill, imm1);
    3995             :   default: return 0;
    3996             :   }
    3997             : }
    3998             : 
    3999             : // Top-level FastEmit function.
    4000             : 
    4001           1 : unsigned fastEmit_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    4002           1 :   switch (Opcode) {
    4003           0 :   case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, Op0IsKill, imm1);
    4004           0 :   case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, Op0IsKill, imm1);
    4005             :   default: return 0;
    4006             :   }
    4007             : }
    4008             : 
    4009             : // FastEmit functions for ISD::Constant.
    4010             : 
    4011             : unsigned fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) {
    4012           7 :   if (RetVT.SimpleTy != MVT::i32)
    4013             :     return 0;
    4014           7 :   if ((Subtarget->inMips16Mode())) {
    4015           0 :     return fastEmitInst_i(Mips::LwConstant32, &Mips::CPU16RegsRegClass, imm0);
    4016             :   }
    4017             :   return 0;
    4018             : }
    4019             : 
    4020           7 : unsigned fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) {
    4021           7 :   switch (VT.SimpleTy) {
    4022           7 :   case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0);
    4023             :   default: return 0;
    4024             :   }
    4025             : }
    4026             : 
    4027             : // Top-level FastEmit function.
    4028             : 
    4029           7 : unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override {
    4030           7 :   switch (Opcode) {
    4031           7 :   case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0);
    4032             :   default: return 0;
    4033             :   }
    4034             : }
    4035             : 

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