LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/Mips - MipsGenFastISel.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 162 1782 9.1 %
Date: 2017-09-14 15:23:50 Functions: 31 287 10.8 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* "Fast" Instruction Selector for the Mips target                            *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : 
      10             : // FastEmit Immediate Predicate functions.
      11             : static bool Predicate_immZExt5(int64_t Imm) {
      12           7 : return Imm == (Imm & 0x1f);
      13             : }
      14             : static bool Predicate_immZExt6(int64_t Imm) {
      15           7 : return Imm == (Imm & 0x3f);
      16             : }
      17             : static bool Predicate_immSExt6(int64_t Imm) {
      18             : return isInt<6>(Imm);
      19             : }
      20             : static bool Predicate_immZExt4Ptr(int64_t Imm) {
      21             : return isUInt<4>(Imm);
      22             : }
      23             : static bool Predicate_immZExt3Ptr(int64_t Imm) {
      24             : return isUInt<3>(Imm);
      25             : }
      26             : static bool Predicate_immZExt2Ptr(int64_t Imm) {
      27           0 : return isUInt<2>(Imm);
      28             : }
      29             : static bool Predicate_immZExt1Ptr(int64_t Imm) {
      30           0 : return isUInt<1>(Imm);
      31             : }
      32             : static bool Predicate_immZExt4(int64_t Imm) {
      33           7 : return isUInt<4>(Imm);
      34             : }
      35             : static bool Predicate_immZExt3(int64_t Imm) {
      36             : return isUInt<3>(Imm);
      37             : }
      38             : static bool Predicate_immZExt2(int64_t Imm) {
      39             : return isUInt<2>(Imm);
      40             : }
      41             : static bool Predicate_immZExt1(int64_t Imm) {
      42             : return isUInt<1>(Imm);
      43             : }
      44             : static bool Predicate_immZExt8(int64_t Imm) {
      45             : return isUInt<8>(Imm);
      46             : }
      47             : static bool Predicate_immSExtAddiur2(int64_t Imm) {
      48          13 : return Imm == 1 || Imm == -1 ||
      49           6 :                                            ((Imm % 4 == 0) &&
      50           6 :                                             Imm < 28 && Imm > 0);
      51             : }
      52             : static bool Predicate_immSExtAddius5(int64_t Imm) {
      53           7 : return Imm >= -8 && Imm <= 7;
      54             : }
      55           7 : static bool Predicate_immZExtAndi16(int64_t Imm) {
      56          13 : return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
      57           6 :             Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
      58          13 :             Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
      59             : }
      60             : static bool Predicate_immZExt2Shift(int64_t Imm) {
      61           7 : return Imm >= 1 && Imm <= 8;
      62             : }
      63             : 
      64             : 
      65             : // FastEmit functions for ISD::BITCAST.
      66             : 
      67           0 : unsigned fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      68           0 :   if (RetVT.SimpleTy != MVT::f32)
      69             :     return 0;
      70           0 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
      71           0 :     return fastEmitInst_r(Mips::MTC1_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill);
      72             :   }
      73           0 :   if ((Subtarget->inMicroMipsMode())) {
      74           0 :     return fastEmitInst_r(Mips::MTC1_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
      75             :   }
      76           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
      77           0 :     return fastEmitInst_r(Mips::MTC1, &Mips::FGR32RegClass, Op0, Op0IsKill);
      78             :   }
      79             :   return 0;
      80             : }
      81             : 
      82           0 : unsigned fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      83           0 :   if (RetVT.SimpleTy != MVT::f64)
      84             :     return 0;
      85           0 :   if ((Subtarget->inMicroMips64r6Mode()) && (Subtarget->hasStandardEncoding())) {
      86           0 :     return fastEmitInst_r(Mips::DMTC1_MM64R6, &Mips::FGR64RegClass, Op0, Op0IsKill);
      87             :   }
      88           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
      89           0 :     return fastEmitInst_r(Mips::DMTC1, &Mips::FGR64RegClass, Op0, Op0IsKill);
      90             :   }
      91             :   return 0;
      92             : }
      93             : 
      94           0 : unsigned fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      95           0 :   if (RetVT.SimpleTy != MVT::i32)
      96             :     return 0;
      97           0 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
      98           0 :     return fastEmitInst_r(Mips::MFC1_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
      99             :   }
     100           0 :   if ((Subtarget->inMicroMipsMode())) {
     101           0 :     return fastEmitInst_r(Mips::MFC1_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
     102             :   }
     103           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
     104           0 :     return fastEmitInst_r(Mips::MFC1, &Mips::GPR32RegClass, Op0, Op0IsKill);
     105             :   }
     106             :   return 0;
     107             : }
     108             : 
     109           0 : unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     110           0 :   if (RetVT.SimpleTy != MVT::i64)
     111             :     return 0;
     112           0 :   if ((Subtarget->inMicroMips64r6Mode()) && (Subtarget->hasStandardEncoding())) {
     113           0 :     return fastEmitInst_r(Mips::DMFC1_MM64R6, &Mips::GPR64RegClass, Op0, Op0IsKill);
     114             :   }
     115           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
     116           0 :     return fastEmitInst_r(Mips::DMFC1, &Mips::GPR64RegClass, Op0, Op0IsKill);
     117             :   }
     118             :   return 0;
     119             : }
     120             : 
     121           0 : unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     122           0 :   switch (VT.SimpleTy) {
     123           0 :   case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0, Op0IsKill);
     124           0 :   case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0, Op0IsKill);
     125           0 :   case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0, Op0IsKill);
     126           0 :   case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0, Op0IsKill);
     127             :   default: return 0;
     128             :   }
     129             : }
     130             : 
     131             : // FastEmit functions for ISD::BRIND.
     132             : 
     133           0 : unsigned fastEmit_ISD_BRIND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     134           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     135             :     return 0;
     136           0 :   if ((Subtarget->inMips16Mode())) {
     137           0 :     return fastEmitInst_r(Mips::JrcRx16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill);
     138             :   }
     139           0 :   return fastEmitInst_r(Mips::PseudoIndirectBranch, &Mips::GPR32RegClass, Op0, Op0IsKill);
     140             : }
     141             : 
     142             : unsigned fastEmit_ISD_BRIND_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     143           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     144             :     return 0;
     145           0 :   return fastEmitInst_r(Mips::PseudoIndirectBranch64, &Mips::GPR64RegClass, Op0, Op0IsKill);
     146             : }
     147             : 
     148           0 : unsigned fastEmit_ISD_BRIND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     149           0 :   switch (VT.SimpleTy) {
     150           0 :   case MVT::i32: return fastEmit_ISD_BRIND_MVT_i32_r(RetVT, Op0, Op0IsKill);
     151           0 :   case MVT::i64: return fastEmit_ISD_BRIND_MVT_i64_r(RetVT, Op0, Op0IsKill);
     152             :   default: return 0;
     153             :   }
     154             : }
     155             : 
     156             : // FastEmit functions for ISD::CTLZ.
     157             : 
     158           0 : unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     159           0 :   if (RetVT.SimpleTy != MVT::i32)
     160             :     return 0;
     161           0 :   if ((Subtarget->inMicroMipsMode())) {
     162           0 :     return fastEmitInst_r(Mips::CLZ_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
     163             :   }
     164           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding())) {
     165           0 :     return fastEmitInst_r(Mips::CLZ_R6, &Mips::GPR32RegClass, Op0, Op0IsKill);
     166             :   }
     167           0 :   if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
     168           0 :     return fastEmitInst_r(Mips::CLZ, &Mips::GPR32RegClass, Op0, Op0IsKill);
     169             :   }
     170             :   return 0;
     171             : }
     172             : 
     173           0 : unsigned fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     174           0 :   if (RetVT.SimpleTy != MVT::i64)
     175             :     return 0;
     176           0 :   if ((Subtarget->inMicroMips64r6Mode()) && (Subtarget->hasStandardEncoding())) {
     177           0 :     return fastEmitInst_r(Mips::DCLZ_MM64R6, &Mips::GPR64RegClass, Op0, Op0IsKill);
     178             :   }
     179           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
     180           0 :     return fastEmitInst_r(Mips::DCLZ_R6, &Mips::GPR64RegClass, Op0, Op0IsKill);
     181             :   }
     182           0 :   if ((Subtarget->hasMips64()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips64r6())) {
     183           0 :     return fastEmitInst_r(Mips::DCLZ, &Mips::GPR64RegClass, Op0, Op0IsKill);
     184             :   }
     185             :   return 0;
     186             : }
     187             : 
     188           0 : unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     189           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     190             :     return 0;
     191           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     192           0 :     return fastEmitInst_r(Mips::NLZC_B, &Mips::MSA128BRegClass, Op0, Op0IsKill);
     193             :   }
     194             :   return 0;
     195             : }
     196             : 
     197           0 : unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     198           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     199             :     return 0;
     200           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     201           0 :     return fastEmitInst_r(Mips::NLZC_H, &Mips::MSA128HRegClass, Op0, Op0IsKill);
     202             :   }
     203             :   return 0;
     204             : }
     205             : 
     206           0 : unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     207           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     208             :     return 0;
     209           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     210           0 :     return fastEmitInst_r(Mips::NLZC_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     211             :   }
     212             :   return 0;
     213             : }
     214             : 
     215           0 : unsigned fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     216           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     217             :     return 0;
     218           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     219           0 :     return fastEmitInst_r(Mips::NLZC_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     220             :   }
     221             :   return 0;
     222             : }
     223             : 
     224           0 : unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     225           0 :   switch (VT.SimpleTy) {
     226           0 :   case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
     227           0 :   case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0, Op0IsKill);
     228           0 :   case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     229           0 :   case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     230           0 :   case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     231           0 :   case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     232             :   default: return 0;
     233             :   }
     234             : }
     235             : 
     236             : // FastEmit functions for ISD::CTPOP.
     237             : 
     238             : unsigned fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     239           0 :   if (RetVT.SimpleTy != MVT::i32)
     240             :     return 0;
     241           0 :   if ((Subtarget->hasCnMips())) {
     242           0 :     return fastEmitInst_r(Mips::POP, &Mips::GPR32RegClass, Op0, Op0IsKill);
     243             :   }
     244             :   return 0;
     245             : }
     246             : 
     247             : unsigned fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     248           0 :   if (RetVT.SimpleTy != MVT::i64)
     249             :     return 0;
     250           0 :   if ((Subtarget->hasCnMips())) {
     251           0 :     return fastEmitInst_r(Mips::DPOP, &Mips::GPR64RegClass, Op0, Op0IsKill);
     252             :   }
     253             :   return 0;
     254             : }
     255             : 
     256           0 : unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     257           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     258             :     return 0;
     259           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     260           0 :     return fastEmitInst_r(Mips::PCNT_B, &Mips::MSA128BRegClass, Op0, Op0IsKill);
     261             :   }
     262             :   return 0;
     263             : }
     264             : 
     265           0 : unsigned fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     266           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     267             :     return 0;
     268           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     269           0 :     return fastEmitInst_r(Mips::PCNT_H, &Mips::MSA128HRegClass, Op0, Op0IsKill);
     270             :   }
     271             :   return 0;
     272             : }
     273             : 
     274           0 : unsigned fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     275           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     276             :     return 0;
     277           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     278           0 :     return fastEmitInst_r(Mips::PCNT_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     279             :   }
     280             :   return 0;
     281             : }
     282             : 
     283           0 : unsigned fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     284           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     285             :     return 0;
     286           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     287           0 :     return fastEmitInst_r(Mips::PCNT_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     288             :   }
     289             :   return 0;
     290             : }
     291             : 
     292           0 : unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     293           0 :   switch (VT.SimpleTy) {
     294           0 :   case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0, Op0IsKill);
     295           0 :   case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0, Op0IsKill);
     296           0 :   case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     297           0 :   case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     298           0 :   case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     299           0 :   case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     300             :   default: return 0;
     301             :   }
     302             : }
     303             : 
     304             : // FastEmit functions for ISD::FABS.
     305             : 
     306           0 : unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     307           0 :   if (RetVT.SimpleTy != MVT::f32)
     308             :     return 0;
     309           0 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
     310           0 :     return fastEmitInst_r(Mips::ABS_S_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill);
     311             :   }
     312           0 :   if ((Subtarget->inMicroMipsMode())) {
     313           0 :     return fastEmitInst_r(Mips::FABS_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
     314             :   }
     315           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
     316           0 :     return fastEmitInst_r(Mips::FABS_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
     317             :   }
     318             :   return 0;
     319             : }
     320             : 
     321           0 : unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     322           0 :   if (RetVT.SimpleTy != MVT::f64)
     323             :     return 0;
     324           0 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
     325           0 :     return fastEmitInst_r(Mips::ABS_D_MMR6, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     326             :   }
     327           0 :   if ((Subtarget->inMicroMipsMode())) {
     328           0 :     return fastEmitInst_r(Mips::FABS_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     329             :   }
     330           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
     331           0 :     return fastEmitInst_r(Mips::FABS_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
     332             :   }
     333           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
     334           0 :     return fastEmitInst_r(Mips::FABS_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     335             :   }
     336             :   return 0;
     337             : }
     338             : 
     339             : unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     340           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     341             :     return 0;
     342           0 :   if ((Subtarget->hasMSA())) {
     343           0 :     return fastEmitInst_r(Mips::FABS_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     344             :   }
     345             :   return 0;
     346             : }
     347             : 
     348             : unsigned fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     349           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     350             :     return 0;
     351           0 :   if ((Subtarget->hasMSA())) {
     352           0 :     return fastEmitInst_r(Mips::FABS_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     353             :   }
     354             :   return 0;
     355             : }
     356             : 
     357           0 : unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     358           0 :   switch (VT.SimpleTy) {
     359           0 :   case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill);
     360           0 :   case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0, Op0IsKill);
     361           0 :   case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     362           0 :   case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     363             :   default: return 0;
     364             :   }
     365             : }
     366             : 
     367             : // FastEmit functions for ISD::FEXP2.
     368             : 
     369             : unsigned fastEmit_ISD_FEXP2_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     370           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     371             :     return 0;
     372           0 :   if ((Subtarget->hasMSA())) {
     373           0 :     return fastEmitInst_r(Mips::FEXP2_W_1_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     374             :   }
     375             :   return 0;
     376             : }
     377             : 
     378             : unsigned fastEmit_ISD_FEXP2_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     379           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     380             :     return 0;
     381           0 :   if ((Subtarget->hasMSA())) {
     382           0 :     return fastEmitInst_r(Mips::FEXP2_D_1_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     383             :   }
     384             :   return 0;
     385             : }
     386             : 
     387           0 : unsigned fastEmit_ISD_FEXP2_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     388           0 :   switch (VT.SimpleTy) {
     389           0 :   case MVT::v4f32: return fastEmit_ISD_FEXP2_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     390           0 :   case MVT::v2f64: return fastEmit_ISD_FEXP2_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     391             :   default: return 0;
     392             :   }
     393             : }
     394             : 
     395             : // FastEmit functions for ISD::FLOG2.
     396             : 
     397           0 : unsigned fastEmit_ISD_FLOG2_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     398           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     399             :     return 0;
     400           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     401           0 :     return fastEmitInst_r(Mips::FLOG2_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     402             :   }
     403             :   return 0;
     404             : }
     405             : 
     406           0 : unsigned fastEmit_ISD_FLOG2_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     407           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     408             :     return 0;
     409           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     410           0 :     return fastEmitInst_r(Mips::FLOG2_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     411             :   }
     412             :   return 0;
     413             : }
     414             : 
     415           0 : unsigned fastEmit_ISD_FLOG2_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     416           0 :   switch (VT.SimpleTy) {
     417           0 :   case MVT::v4f32: return fastEmit_ISD_FLOG2_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     418           0 :   case MVT::v2f64: return fastEmit_ISD_FLOG2_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     419             :   default: return 0;
     420             :   }
     421             : }
     422             : 
     423             : // FastEmit functions for ISD::FNEG.
     424             : 
     425           0 : unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     426           0 :   if (RetVT.SimpleTy != MVT::f32)
     427             :     return 0;
     428           0 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
     429           0 :     return fastEmitInst_r(Mips::FNEG_S_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill);
     430             :   }
     431           0 :   if ((Subtarget->inMicroMipsMode())) {
     432           0 :     return fastEmitInst_r(Mips::FNEG_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
     433             :   }
     434           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
     435           0 :     return fastEmitInst_r(Mips::FNEG_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
     436             :   }
     437             :   return 0;
     438             : }
     439             : 
     440           0 : unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     441           0 :   if (RetVT.SimpleTy != MVT::f64)
     442             :     return 0;
     443           0 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
     444           0 :     return fastEmitInst_r(Mips::FNEG_D_MMR6, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     445             :   }
     446           0 :   if ((Subtarget->inMicroMipsMode())) {
     447           0 :     return fastEmitInst_r(Mips::FNEG_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     448             :   }
     449           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
     450           0 :     return fastEmitInst_r(Mips::FNEG_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
     451             :   }
     452           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
     453           0 :     return fastEmitInst_r(Mips::FNEG_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     454             :   }
     455             :   return 0;
     456             : }
     457             : 
     458           0 : unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     459           0 :   switch (VT.SimpleTy) {
     460           0 :   case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill);
     461           0 :   case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0, Op0IsKill);
     462             :   default: return 0;
     463             :   }
     464             : }
     465             : 
     466             : // FastEmit functions for ISD::FP_EXTEND.
     467             : 
     468             : unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
     469           0 :   if ((Subtarget->hasMSA())) {
     470           0 :     return fastEmitInst_r(Mips::MSA_FP_EXTEND_W_PSEUDO, &Mips::FGR32RegClass, Op0, Op0IsKill);
     471             :   }
     472             :   return 0;
     473             : }
     474             : 
     475             : unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
     476           0 :   if ((Subtarget->hasMSA())) {
     477           0 :     return fastEmitInst_r(Mips::MSA_FP_EXTEND_D_PSEUDO, &Mips::FGR64RegClass, Op0, Op0IsKill);
     478             :   }
     479             :   return 0;
     480             : }
     481             : 
     482           0 : unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     483           0 : switch (RetVT.SimpleTy) {
     484           0 :   case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(Op0, Op0IsKill);
     485           0 :   case MVT::f64: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(Op0, Op0IsKill);
     486             :   default: return 0;
     487             : }
     488             : }
     489             : 
     490           0 : unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     491           0 :   if (RetVT.SimpleTy != MVT::f64)
     492             :     return 0;
     493           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
     494           0 :     return fastEmitInst_r(Mips::CVT_D64_S, &Mips::FGR64RegClass, Op0, Op0IsKill);
     495             :   }
     496           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit())) {
     497           0 :     return fastEmitInst_r(Mips::CVT_D32_S, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     498             :   }
     499             :   return 0;
     500             : }
     501             : 
     502           0 : unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     503           0 :   switch (VT.SimpleTy) {
     504           0 :   case MVT::f16: return fastEmit_ISD_FP_EXTEND_MVT_f16_r(RetVT, Op0, Op0IsKill);
     505           0 :   case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0, Op0IsKill);
     506             :   default: return 0;
     507             :   }
     508             : }
     509             : 
     510             : // FastEmit functions for ISD::FP_ROUND.
     511             : 
     512             : unsigned fastEmit_ISD_FP_ROUND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     513           0 :   if (RetVT.SimpleTy != MVT::f16)
     514             :     return 0;
     515           0 :   if ((Subtarget->hasMSA())) {
     516           0 :     return fastEmitInst_r(Mips::MSA_FP_ROUND_W_PSEUDO, &Mips::MSA128F16RegClass, Op0, Op0IsKill);
     517             :   }
     518             :   return 0;
     519             : }
     520             : 
     521             : unsigned fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(unsigned Op0, bool Op0IsKill) {
     522           0 :   if ((Subtarget->hasMSA())) {
     523           0 :     return fastEmitInst_r(Mips::MSA_FP_ROUND_D_PSEUDO, &Mips::MSA128F16RegClass, Op0, Op0IsKill);
     524             :   }
     525             :   return 0;
     526             : }
     527             : 
     528           0 : unsigned fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
     529           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
     530           0 :     return fastEmitInst_r(Mips::CVT_S_D64, &Mips::FGR32RegClass, Op0, Op0IsKill);
     531             :   }
     532           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit())) {
     533           0 :     return fastEmitInst_r(Mips::CVT_S_D32, &Mips::FGR32RegClass, Op0, Op0IsKill);
     534             :   }
     535             :   return 0;
     536             : }
     537             : 
     538           0 : unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     539           0 : switch (RetVT.SimpleTy) {
     540           0 :   case MVT::f16: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(Op0, Op0IsKill);
     541           0 :   case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(Op0, Op0IsKill);
     542             :   default: return 0;
     543             : }
     544             : }
     545             : 
     546           0 : unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     547           0 :   switch (VT.SimpleTy) {
     548           0 :   case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f32_r(RetVT, Op0, Op0IsKill);
     549           0 :   case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
     550             :   default: return 0;
     551             :   }
     552             : }
     553             : 
     554             : // FastEmit functions for ISD::FP_TO_SINT.
     555             : 
     556           0 : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     557           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     558             :     return 0;
     559           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     560           0 :     return fastEmitInst_r(Mips::FTRUNC_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     561             :   }
     562             :   return 0;
     563             : }
     564             : 
     565           0 : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     566           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     567             :     return 0;
     568           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     569           0 :     return fastEmitInst_r(Mips::FTRUNC_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     570             :   }
     571             :   return 0;
     572             : }
     573             : 
     574           4 : unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     575           4 :   switch (VT.SimpleTy) {
     576           0 :   case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     577           0 :   case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     578             :   default: return 0;
     579             :   }
     580             : }
     581             : 
     582             : // FastEmit functions for ISD::FP_TO_UINT.
     583             : 
     584           0 : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     585           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     586             :     return 0;
     587           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     588           0 :     return fastEmitInst_r(Mips::FTRUNC_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     589             :   }
     590             :   return 0;
     591             : }
     592             : 
     593           0 : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     594           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     595             :     return 0;
     596           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     597           0 :     return fastEmitInst_r(Mips::FTRUNC_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     598             :   }
     599             :   return 0;
     600             : }
     601             : 
     602           0 : unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     603           0 :   switch (VT.SimpleTy) {
     604           0 :   case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     605           0 :   case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     606             :   default: return 0;
     607             :   }
     608             : }
     609             : 
     610             : // FastEmit functions for ISD::FRINT.
     611             : 
     612           0 : unsigned fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     613           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     614             :     return 0;
     615           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     616           0 :     return fastEmitInst_r(Mips::FRINT_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     617             :   }
     618             :   return 0;
     619             : }
     620             : 
     621           0 : unsigned fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     622           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     623             :     return 0;
     624           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     625           0 :     return fastEmitInst_r(Mips::FRINT_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     626             :   }
     627             :   return 0;
     628             : }
     629             : 
     630           0 : unsigned fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     631           0 :   switch (VT.SimpleTy) {
     632           0 :   case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     633           0 :   case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     634             :   default: return 0;
     635             :   }
     636             : }
     637             : 
     638             : // FastEmit functions for ISD::FSQRT.
     639             : 
     640           0 : unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     641           0 :   if (RetVT.SimpleTy != MVT::f32)
     642             :     return 0;
     643           0 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
     644           0 :     return fastEmitInst_r(Mips::SQRT_S_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill);
     645             :   }
     646           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
     647           0 :     return fastEmitInst_r(Mips::FSQRT_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
     648             :   }
     649           0 :   if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
     650           0 :     return fastEmitInst_r(Mips::FSQRT_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
     651             :   }
     652             :   return 0;
     653             : }
     654             : 
     655           0 : unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     656           0 :   if (RetVT.SimpleTy != MVT::f64)
     657             :     return 0;
     658           0 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
     659           0 :     return fastEmitInst_r(Mips::SQRT_D_MMR6, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     660             :   }
     661           0 :   if ((Subtarget->inMicroMipsMode())) {
     662           0 :     return fastEmitInst_r(Mips::FSQRT_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     663             :   }
     664           0 :   if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
     665           0 :     return fastEmitInst_r(Mips::FSQRT_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
     666             :   }
     667           0 :   if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
     668           0 :     return fastEmitInst_r(Mips::FSQRT_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     669             :   }
     670             :   return 0;
     671             : }
     672             : 
     673           0 : unsigned fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     674           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     675             :     return 0;
     676           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     677           0 :     return fastEmitInst_r(Mips::FSQRT_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     678             :   }
     679             :   return 0;
     680             : }
     681             : 
     682           0 : unsigned fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     683           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     684             :     return 0;
     685           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     686           0 :     return fastEmitInst_r(Mips::FSQRT_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     687             :   }
     688             :   return 0;
     689             : }
     690             : 
     691           0 : unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     692           0 :   switch (VT.SimpleTy) {
     693           0 :   case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill);
     694           0 :   case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0, Op0IsKill);
     695           0 :   case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     696           0 :   case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     697             :   default: return 0;
     698             :   }
     699             : }
     700             : 
     701             : // FastEmit functions for ISD::SIGN_EXTEND.
     702             : 
     703             : unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     704           0 :   if (RetVT.SimpleTy != MVT::i64)
     705             :     return 0;
     706           0 :   if ((Subtarget->hasStandardEncoding())) {
     707           0 :     return fastEmitInst_r(Mips::SLL64_32, &Mips::GPR64RegClass, Op0, Op0IsKill);
     708             :   }
     709             :   return 0;
     710             : }
     711             : 
     712           0 : unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     713           0 :   switch (VT.SimpleTy) {
     714           0 :   case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0, Op0IsKill);
     715             :   default: return 0;
     716             :   }
     717             : }
     718             : 
     719             : // FastEmit functions for ISD::SINT_TO_FP.
     720             : 
     721             : unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
     722           0 :   if ((Subtarget->hasStandardEncoding())) {
     723           0 :     return fastEmitInst_r(Mips::PseudoCVT_S_W, &Mips::FGR32RegClass, Op0, Op0IsKill);
     724             :   }
     725             :   return 0;
     726             : }
     727             : 
     728           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
     729           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
     730           0 :     return fastEmitInst_r(Mips::PseudoCVT_D64_W, &Mips::FGR64RegClass, Op0, Op0IsKill);
     731             :   }
     732           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit())) {
     733           0 :     return fastEmitInst_r(Mips::PseudoCVT_D32_W, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     734             :   }
     735             :   return 0;
     736             : }
     737             : 
     738           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     739           0 : switch (RetVT.SimpleTy) {
     740           0 :   case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0, Op0IsKill);
     741           0 :   case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0, Op0IsKill);
     742             :   default: return 0;
     743             : }
     744             : }
     745             : 
     746           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     747           0 :   if (RetVT.SimpleTy != MVT::f64)
     748             :     return 0;
     749           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
     750           0 :     return fastEmitInst_r(Mips::PseudoCVT_D64_L, &Mips::FGR64RegClass, Op0, Op0IsKill);
     751             :   }
     752             :   return 0;
     753             : }
     754             : 
     755           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     756           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     757             :     return 0;
     758           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     759           0 :     return fastEmitInst_r(Mips::FFINT_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     760             :   }
     761             :   return 0;
     762             : }
     763             : 
     764           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     765           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     766             :     return 0;
     767           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     768           0 :     return fastEmitInst_r(Mips::FFINT_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     769             :   }
     770             :   return 0;
     771             : }
     772             : 
     773           0 : unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     774           0 :   switch (VT.SimpleTy) {
     775           0 :   case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0, Op0IsKill);
     776           0 :   case MVT::i64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_r(RetVT, Op0, Op0IsKill);
     777           0 :   case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     778           0 :   case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     779             :   default: return 0;
     780             :   }
     781             : }
     782             : 
     783             : // FastEmit functions for ISD::UINT_TO_FP.
     784             : 
     785           0 : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     786           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     787             :     return 0;
     788           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     789           0 :     return fastEmitInst_r(Mips::FFINT_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     790             :   }
     791             :   return 0;
     792             : }
     793             : 
     794           0 : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     795           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     796             :     return 0;
     797           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     798           0 :     return fastEmitInst_r(Mips::FFINT_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     799             :   }
     800             :   return 0;
     801             : }
     802             : 
     803           0 : unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     804           0 :   switch (VT.SimpleTy) {
     805           0 :   case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     806           0 :   case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     807             :   default: return 0;
     808             :   }
     809             : }
     810             : 
     811             : // FastEmit functions for MipsISD::JmpLink.
     812             : 
     813           0 : unsigned fastEmit_MipsISD_JmpLink_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     814           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     815             :     return 0;
     816           0 :   if ((Subtarget->inMicroMips32r6Mode())) {
     817           0 :     return fastEmitInst_r(Mips::JALRC16_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
     818             :   }
     819           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
     820           0 :     return fastEmitInst_r(Mips::JALR16_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
     821             :   }
     822           0 :   if ((Subtarget->inMips16Mode())) {
     823           0 :     return fastEmitInst_r(Mips::JumpLinkReg16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill);
     824             :   }
     825           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
     826           0 :     return fastEmitInst_r(Mips::JALRPseudo, &Mips::GPR32RegClass, Op0, Op0IsKill);
     827             :   }
     828             :   return 0;
     829             : }
     830             : 
     831             : unsigned fastEmit_MipsISD_JmpLink_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     832           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     833             :     return 0;
     834           0 :   if ((Subtarget->hasStandardEncoding())) {
     835           0 :     return fastEmitInst_r(Mips::JALR64Pseudo, &Mips::GPR64RegClass, Op0, Op0IsKill);
     836             :   }
     837             :   return 0;
     838             : }
     839             : 
     840           0 : unsigned fastEmit_MipsISD_JmpLink_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     841           0 :   switch (VT.SimpleTy) {
     842           0 :   case MVT::i32: return fastEmit_MipsISD_JmpLink_MVT_i32_r(RetVT, Op0, Op0IsKill);
     843           0 :   case MVT::i64: return fastEmit_MipsISD_JmpLink_MVT_i64_r(RetVT, Op0, Op0IsKill);
     844             :   default: return 0;
     845             :   }
     846             : }
     847             : 
     848             : // FastEmit functions for MipsISD::MFHI.
     849             : 
     850           0 : unsigned fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(unsigned Op0, bool Op0IsKill) {
     851           0 :   if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
     852           0 :     return fastEmitInst_r(Mips::MFHI_DSP_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
     853             :   }
     854           0 :   if ((Subtarget->hasDSP())) {
     855           0 :     return fastEmitInst_r(Mips::MFHI_DSP, &Mips::GPR32RegClass, Op0, Op0IsKill);
     856             :   }
     857           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
     858           0 :     return fastEmitInst_r(Mips::PseudoMFHI, &Mips::GPR32RegClass, Op0, Op0IsKill);
     859             :   }
     860             :   return 0;
     861             : }
     862             : 
     863           0 : unsigned fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(unsigned Op0, bool Op0IsKill) {
     864           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
     865           0 :     return fastEmitInst_r(Mips::PseudoMFHI64, &Mips::GPR64RegClass, Op0, Op0IsKill);
     866             :   }
     867             :   return 0;
     868             : }
     869             : 
     870           0 : unsigned fastEmit_MipsISD_MFHI_MVT_Untyped_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     871           0 : switch (RetVT.SimpleTy) {
     872           0 :   case MVT::i32: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(Op0, Op0IsKill);
     873           0 :   case MVT::i64: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(Op0, Op0IsKill);
     874             :   default: return 0;
     875             : }
     876             : }
     877             : 
     878             : unsigned fastEmit_MipsISD_MFHI_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     879           0 :   switch (VT.SimpleTy) {
     880           0 :   case MVT::Untyped: return fastEmit_MipsISD_MFHI_MVT_Untyped_r(RetVT, Op0, Op0IsKill);
     881             :   default: return 0;
     882             :   }
     883             : }
     884             : 
     885             : // FastEmit functions for MipsISD::MFLO.
     886             : 
     887           0 : unsigned fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(unsigned Op0, bool Op0IsKill) {
     888           0 :   if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
     889           0 :     return fastEmitInst_r(Mips::MFLO_DSP_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
     890             :   }
     891           0 :   if ((Subtarget->hasDSP())) {
     892           0 :     return fastEmitInst_r(Mips::MFLO_DSP, &Mips::GPR32RegClass, Op0, Op0IsKill);
     893             :   }
     894           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
     895           0 :     return fastEmitInst_r(Mips::PseudoMFLO, &Mips::GPR32RegClass, Op0, Op0IsKill);
     896             :   }
     897             :   return 0;
     898             : }
     899             : 
     900           0 : unsigned fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(unsigned Op0, bool Op0IsKill) {
     901           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
     902           0 :     return fastEmitInst_r(Mips::PseudoMFLO64, &Mips::GPR64RegClass, Op0, Op0IsKill);
     903             :   }
     904             :   return 0;
     905             : }
     906             : 
     907           0 : unsigned fastEmit_MipsISD_MFLO_MVT_Untyped_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     908           0 : switch (RetVT.SimpleTy) {
     909           0 :   case MVT::i32: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(Op0, Op0IsKill);
     910           0 :   case MVT::i64: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(Op0, Op0IsKill);
     911             :   default: return 0;
     912             : }
     913             : }
     914             : 
     915             : unsigned fastEmit_MipsISD_MFLO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     916           0 :   switch (VT.SimpleTy) {
     917           0 :   case MVT::Untyped: return fastEmit_MipsISD_MFLO_MVT_Untyped_r(RetVT, Op0, Op0IsKill);
     918             :   default: return 0;
     919             :   }
     920             : }
     921             : 
     922             : // FastEmit functions for MipsISD::MTC1_D64.
     923             : 
     924           0 : unsigned fastEmit_MipsISD_MTC1_D64_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     925           0 :   if (RetVT.SimpleTy != MVT::f64)
     926             :     return 0;
     927           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
     928           0 :     return fastEmitInst_r(Mips::MTC1_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
     929             :   }
     930             :   return 0;
     931             : }
     932             : 
     933             : unsigned fastEmit_MipsISD_MTC1_D64_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     934           0 :   switch (VT.SimpleTy) {
     935           0 :   case MVT::i32: return fastEmit_MipsISD_MTC1_D64_MVT_i32_r(RetVT, Op0, Op0IsKill);
     936             :   default: return 0;
     937             :   }
     938             : }
     939             : 
     940             : // FastEmit functions for MipsISD::TailCall.
     941             : 
     942             : unsigned fastEmit_MipsISD_TailCall_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     943           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     944             :     return 0;
     945           0 :   return fastEmitInst_r(Mips::TAILCALLREG, &Mips::GPR32RegClass, Op0, Op0IsKill);
     946             : }
     947             : 
     948             : unsigned fastEmit_MipsISD_TailCall_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     949           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     950             :     return 0;
     951           0 :   return fastEmitInst_r(Mips::TAILCALLREG64, &Mips::GPR64RegClass, Op0, Op0IsKill);
     952             : }
     953             : 
     954           0 : unsigned fastEmit_MipsISD_TailCall_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     955           0 :   switch (VT.SimpleTy) {
     956           0 :   case MVT::i32: return fastEmit_MipsISD_TailCall_MVT_i32_r(RetVT, Op0, Op0IsKill);
     957           0 :   case MVT::i64: return fastEmit_MipsISD_TailCall_MVT_i64_r(RetVT, Op0, Op0IsKill);
     958             :   default: return 0;
     959             :   }
     960             : }
     961             : 
     962             : // FastEmit functions for MipsISD::TruncIntFP.
     963             : 
     964             : unsigned fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
     965           0 :   if ((Subtarget->hasStandardEncoding())) {
     966           0 :     return fastEmitInst_r(Mips::TRUNC_W_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
     967             :   }
     968             :   return 0;
     969             : }
     970             : 
     971           0 : unsigned fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
     972           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
     973           0 :     return fastEmitInst_r(Mips::TRUNC_L_S, &Mips::FGR64RegClass, Op0, Op0IsKill);
     974             :   }
     975             :   return 0;
     976             : }
     977             : 
     978           0 : unsigned fastEmit_MipsISD_TruncIntFP_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     979           0 : switch (RetVT.SimpleTy) {
     980           0 :   case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(Op0, Op0IsKill);
     981           0 :   case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(Op0, Op0IsKill);
     982             :   default: return 0;
     983             : }
     984             : }
     985             : 
     986           0 : unsigned fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
     987           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
     988           0 :     return fastEmitInst_r(Mips::TRUNC_W_D64, &Mips::FGR32RegClass, Op0, Op0IsKill);
     989             :   }
     990           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit())) {
     991           0 :     return fastEmitInst_r(Mips::TRUNC_W_D32, &Mips::FGR32RegClass, Op0, Op0IsKill);
     992             :   }
     993             :   return 0;
     994             : }
     995             : 
     996           0 : unsigned fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
     997           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
     998           0 :     return fastEmitInst_r(Mips::TRUNC_L_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
     999             :   }
    1000             :   return 0;
    1001             : }
    1002             : 
    1003           0 : unsigned fastEmit_MipsISD_TruncIntFP_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1004           0 : switch (RetVT.SimpleTy) {
    1005           0 :   case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(Op0, Op0IsKill);
    1006           0 :   case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(Op0, Op0IsKill);
    1007             :   default: return 0;
    1008             : }
    1009             : }
    1010             : 
    1011           0 : unsigned fastEmit_MipsISD_TruncIntFP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1012           0 :   switch (VT.SimpleTy) {
    1013           0 :   case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1014           0 :   case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1015             :   default: return 0;
    1016             :   }
    1017             : }
    1018             : 
    1019             : // FastEmit functions for MipsISD::VALL_NONZERO.
    1020             : 
    1021             : unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1022           0 :   if (RetVT.SimpleTy != MVT::i32)
    1023             :     return 0;
    1024           0 :   return fastEmitInst_r(Mips::SNZ_B_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1025             : }
    1026             : 
    1027             : unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1028           0 :   if (RetVT.SimpleTy != MVT::i32)
    1029             :     return 0;
    1030           0 :   return fastEmitInst_r(Mips::SNZ_H_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1031             : }
    1032             : 
    1033             : unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1034           0 :   if (RetVT.SimpleTy != MVT::i32)
    1035             :     return 0;
    1036           0 :   return fastEmitInst_r(Mips::SNZ_W_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1037             : }
    1038             : 
    1039             : unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1040           0 :   if (RetVT.SimpleTy != MVT::i32)
    1041             :     return 0;
    1042           0 :   return fastEmitInst_r(Mips::SNZ_D_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1043             : }
    1044             : 
    1045           0 : unsigned fastEmit_MipsISD_VALL_NONZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1046           0 :   switch (VT.SimpleTy) {
    1047           0 :   case MVT::v16i8: return fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1048           0 :   case MVT::v8i16: return fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    1049           0 :   case MVT::v4i32: return fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    1050           0 :   case MVT::v2i64: return fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
    1051             :   default: return 0;
    1052             :   }
    1053             : }
    1054             : 
    1055             : // FastEmit functions for MipsISD::VALL_ZERO.
    1056             : 
    1057             : unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1058           0 :   if (RetVT.SimpleTy != MVT::i32)
    1059             :     return 0;
    1060           0 :   return fastEmitInst_r(Mips::SZ_B_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1061             : }
    1062             : 
    1063             : unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1064           0 :   if (RetVT.SimpleTy != MVT::i32)
    1065             :     return 0;
    1066           0 :   return fastEmitInst_r(Mips::SZ_H_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1067             : }
    1068             : 
    1069             : unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1070           0 :   if (RetVT.SimpleTy != MVT::i32)
    1071             :     return 0;
    1072           0 :   return fastEmitInst_r(Mips::SZ_W_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1073             : }
    1074             : 
    1075             : unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1076           0 :   if (RetVT.SimpleTy != MVT::i32)
    1077             :     return 0;
    1078           0 :   return fastEmitInst_r(Mips::SZ_D_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1079             : }
    1080             : 
    1081           0 : unsigned fastEmit_MipsISD_VALL_ZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1082           0 :   switch (VT.SimpleTy) {
    1083           0 :   case MVT::v16i8: return fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1084           0 :   case MVT::v8i16: return fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    1085           0 :   case MVT::v4i32: return fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    1086           0 :   case MVT::v2i64: return fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
    1087             :   default: return 0;
    1088             :   }
    1089             : }
    1090             : 
    1091             : // FastEmit functions for MipsISD::VANY_NONZERO.
    1092             : 
    1093             : unsigned fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1094           0 :   if (RetVT.SimpleTy != MVT::i32)
    1095             :     return 0;
    1096           0 :   return fastEmitInst_r(Mips::SNZ_V_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1097             : }
    1098             : 
    1099             : unsigned fastEmit_MipsISD_VANY_NONZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1100           0 :   switch (VT.SimpleTy) {
    1101           0 :   case MVT::v16i8: return fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1102             :   default: return 0;
    1103             :   }
    1104             : }
    1105             : 
    1106             : // FastEmit functions for MipsISD::VANY_ZERO.
    1107             : 
    1108             : unsigned fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1109           0 :   if (RetVT.SimpleTy != MVT::i32)
    1110             :     return 0;
    1111           0 :   return fastEmitInst_r(Mips::SZ_V_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1112             : }
    1113             : 
    1114             : unsigned fastEmit_MipsISD_VANY_ZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1115           0 :   switch (VT.SimpleTy) {
    1116           0 :   case MVT::v16i8: return fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1117             :   default: return 0;
    1118             :   }
    1119             : }
    1120             : 
    1121             : // Top-level FastEmit function.
    1122             : 
    1123           4 : unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill) override {
    1124           4 :   switch (Opcode) {
    1125           0 :   case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0, Op0IsKill);
    1126           0 :   case ISD::BRIND: return fastEmit_ISD_BRIND_r(VT, RetVT, Op0, Op0IsKill);
    1127           0 :   case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill);
    1128           0 :   case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill);
    1129           0 :   case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill);
    1130           0 :   case ISD::FEXP2: return fastEmit_ISD_FEXP2_r(VT, RetVT, Op0, Op0IsKill);
    1131           0 :   case ISD::FLOG2: return fastEmit_ISD_FLOG2_r(VT, RetVT, Op0, Op0IsKill);
    1132           0 :   case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill);
    1133           0 :   case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
    1134           0 :   case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill);
    1135           4 :   case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill);
    1136           0 :   case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill);
    1137           0 :   case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0, Op0IsKill);
    1138           0 :   case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill);
    1139           0 :   case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
    1140           0 :   case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill);
    1141           0 :   case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill);
    1142           0 :   case MipsISD::JmpLink: return fastEmit_MipsISD_JmpLink_r(VT, RetVT, Op0, Op0IsKill);
    1143           0 :   case MipsISD::MFHI: return fastEmit_MipsISD_MFHI_r(VT, RetVT, Op0, Op0IsKill);
    1144           0 :   case MipsISD::MFLO: return fastEmit_MipsISD_MFLO_r(VT, RetVT, Op0, Op0IsKill);
    1145           0 :   case MipsISD::MTC1_D64: return fastEmit_MipsISD_MTC1_D64_r(VT, RetVT, Op0, Op0IsKill);
    1146           0 :   case MipsISD::TailCall: return fastEmit_MipsISD_TailCall_r(VT, RetVT, Op0, Op0IsKill);
    1147           0 :   case MipsISD::TruncIntFP: return fastEmit_MipsISD_TruncIntFP_r(VT, RetVT, Op0, Op0IsKill);
    1148           0 :   case MipsISD::VALL_NONZERO: return fastEmit_MipsISD_VALL_NONZERO_r(VT, RetVT, Op0, Op0IsKill);
    1149           0 :   case MipsISD::VALL_ZERO: return fastEmit_MipsISD_VALL_ZERO_r(VT, RetVT, Op0, Op0IsKill);
    1150           0 :   case MipsISD::VANY_NONZERO: return fastEmit_MipsISD_VANY_NONZERO_r(VT, RetVT, Op0, Op0IsKill);
    1151           0 :   case MipsISD::VANY_ZERO: return fastEmit_MipsISD_VANY_ZERO_r(VT, RetVT, Op0, Op0IsKill);
    1152             :   default: return 0;
    1153             :   }
    1154             : }
    1155             : 
    1156             : // FastEmit functions for ISD::ADD.
    1157             : 
    1158           6 : unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1159           6 :   if (RetVT.SimpleTy != MVT::i32)
    1160             :     return 0;
    1161           6 :   if ((Subtarget->inMicroMips32r6Mode())) {
    1162           0 :     return fastEmitInst_rr(Mips::ADDU16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1163             :   }
    1164           6 :   if ((Subtarget->inMips16Mode())) {
    1165           0 :     return fastEmitInst_rr(Mips::AdduRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1166             :   }
    1167           6 :   if ((Subtarget->inMicroMipsMode())) {
    1168           0 :     return fastEmitInst_rr(Mips::ADDu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1169             :   }
    1170           6 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    1171             :     return fastEmitInst_rr(Mips::ADDU16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1172             :   }
    1173          12 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1174          12 :     return fastEmitInst_rr(Mips::ADDu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1175             :   }
    1176             :   return 0;
    1177             : }
    1178             : 
    1179           0 : unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1180           0 :   if (RetVT.SimpleTy != MVT::i64)
    1181             :     return 0;
    1182           0 :   if ((Subtarget->inMicroMips64r6Mode()) && (Subtarget->hasStandardEncoding())) {
    1183           0 :     return fastEmitInst_rr(Mips::DADDU_MM64R6, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1184             :   }
    1185           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1186           0 :     return fastEmitInst_rr(Mips::DADDu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1187             :   }
    1188             :   return 0;
    1189             : }
    1190             : 
    1191             : unsigned fastEmit_ISD_ADD_MVT_v4i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1192           0 :   if (RetVT.SimpleTy != MVT::v4i8)
    1193             :     return 0;
    1194           0 :   if ((Subtarget->hasDSP())) {
    1195           0 :     return fastEmitInst_rr(Mips::ADDU_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1196             :   }
    1197             :   return 0;
    1198             : }
    1199             : 
    1200           0 : unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1201           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1202             :     return 0;
    1203           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1204           0 :     return fastEmitInst_rr(Mips::ADDV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1205             :   }
    1206             :   return 0;
    1207             : }
    1208             : 
    1209             : unsigned fastEmit_ISD_ADD_MVT_v2i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1210           0 :   if (RetVT.SimpleTy != MVT::v2i16)
    1211             :     return 0;
    1212           0 :   if ((Subtarget->hasDSP())) {
    1213           0 :     return fastEmitInst_rr(Mips::ADDQ_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1214             :   }
    1215             :   return 0;
    1216             : }
    1217             : 
    1218           0 : unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1219           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1220             :     return 0;
    1221           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1222           0 :     return fastEmitInst_rr(Mips::ADDV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1223             :   }
    1224             :   return 0;
    1225             : }
    1226             : 
    1227           0 : unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1228           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1229             :     return 0;
    1230           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1231           0 :     return fastEmitInst_rr(Mips::ADDV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1232             :   }
    1233             :   return 0;
    1234             : }
    1235             : 
    1236           0 : unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1237           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1238             :     return 0;
    1239           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1240           0 :     return fastEmitInst_rr(Mips::ADDV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1241             :   }
    1242             :   return 0;
    1243             : }
    1244             : 
    1245           6 : unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1246           6 :   switch (VT.SimpleTy) {
    1247           6 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1248           0 :   case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1249           0 :   case MVT::v4i8: return fastEmit_ISD_ADD_MVT_v4i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1250           0 :   case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1251           0 :   case MVT::v2i16: return fastEmit_ISD_ADD_MVT_v2i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1252           0 :   case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1253           0 :   case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1254           0 :   case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1255             :   default: return 0;
    1256             :   }
    1257             : }
    1258             : 
    1259             : // FastEmit functions for ISD::ADDC.
    1260             : 
    1261           0 : unsigned fastEmit_ISD_ADDC_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1262           0 :   if (RetVT.SimpleTy != MVT::i32)
    1263             :     return 0;
    1264           0 :   if ((Subtarget->hasDSP())) {
    1265           0 :     return fastEmitInst_rr(Mips::ADDSC, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1266             :   }
    1267           0 :   if ((Subtarget->inMips16Mode())) {
    1268           0 :     return fastEmitInst_rr(Mips::AdduRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1269             :   }
    1270           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP())) {
    1271           0 :     return fastEmitInst_rr(Mips::ADDu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1272             :   }
    1273             :   return 0;
    1274             : }
    1275             : 
    1276           0 : unsigned fastEmit_ISD_ADDC_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1277           0 :   if (RetVT.SimpleTy != MVT::i64)
    1278             :     return 0;
    1279           0 :   if ((Subtarget->inMicroMips64r6Mode()) && (Subtarget->hasStandardEncoding())) {
    1280           0 :     return fastEmitInst_rr(Mips::DADDU_MM64R6, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1281             :   }
    1282           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->inMicroMipsMode())) {
    1283           0 :     return fastEmitInst_rr(Mips::DADDu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1284             :   }
    1285             :   return 0;
    1286             : }
    1287             : 
    1288           0 : unsigned fastEmit_ISD_ADDC_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1289           0 :   switch (VT.SimpleTy) {
    1290           0 :   case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1291           0 :   case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1292             :   default: return 0;
    1293             :   }
    1294             : }
    1295             : 
    1296             : // FastEmit functions for ISD::ADDE.
    1297             : 
    1298             : unsigned fastEmit_ISD_ADDE_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1299           0 :   if (RetVT.SimpleTy != MVT::i32)
    1300             :     return 0;
    1301           0 :   if ((Subtarget->hasDSP())) {
    1302           0 :     return fastEmitInst_rr(Mips::ADDWC, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1303             :   }
    1304             :   return 0;
    1305             : }
    1306             : 
    1307           0 : unsigned fastEmit_ISD_ADDE_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1308           0 :   switch (VT.SimpleTy) {
    1309           0 :   case MVT::i32: return fastEmit_ISD_ADDE_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1310             :   default: return 0;
    1311             :   }
    1312             : }
    1313             : 
    1314             : // FastEmit functions for ISD::AND.
    1315             : 
    1316           5 : unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1317           5 :   if (RetVT.SimpleTy != MVT::i32)
    1318             :     return 0;
    1319           5 :   if ((Subtarget->inMicroMips32r6Mode())) {
    1320           0 :     return fastEmitInst_rr(Mips::AND16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1321             :   }
    1322           5 :   if ((Subtarget->inMips16Mode())) {
    1323           0 :     return fastEmitInst_rr(Mips::AndRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1324             :   }
    1325           5 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding())) {
    1326           0 :     return fastEmitInst_rr(Mips::AND_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1327             :   }
    1328           5 :   if ((Subtarget->inMicroMipsMode())) {
    1329           0 :     return fastEmitInst_rr(Mips::AND_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1330             :   }
    1331           5 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    1332             :     return fastEmitInst_rr(Mips::AND16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1333             :   }
    1334          10 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1335          10 :     return fastEmitInst_rr(Mips::AND, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1336             :   }
    1337             :   return 0;
    1338             : }
    1339             : 
    1340             : unsigned fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1341           0 :   if (RetVT.SimpleTy != MVT::i64)
    1342             :     return 0;
    1343           0 :   if ((Subtarget->hasStandardEncoding())) {
    1344           0 :     return fastEmitInst_rr(Mips::AND64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1345             :   }
    1346             :   return 0;
    1347             : }
    1348             : 
    1349           0 : unsigned fastEmit_ISD_AND_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1350           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1351             :     return 0;
    1352           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1353           0 :     return fastEmitInst_rr(Mips::AND_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1354             :   }
    1355             :   return 0;
    1356             : }
    1357             : 
    1358             : unsigned fastEmit_ISD_AND_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1359           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1360             :     return 0;
    1361           0 :   if ((Subtarget->hasMSA())) {
    1362           0 :     return fastEmitInst_rr(Mips::AND_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1363             :   }
    1364             :   return 0;
    1365             : }
    1366             : 
    1367             : unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1368           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1369             :     return 0;
    1370           0 :   if ((Subtarget->hasMSA())) {
    1371           0 :     return fastEmitInst_rr(Mips::AND_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1372             :   }
    1373             :   return 0;
    1374             : }
    1375             : 
    1376             : unsigned fastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1377           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1378             :     return 0;
    1379           0 :   if ((Subtarget->hasMSA())) {
    1380           0 :     return fastEmitInst_rr(Mips::AND_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1381             :   }
    1382             :   return 0;
    1383             : }
    1384             : 
    1385           5 : unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1386           5 :   switch (VT.SimpleTy) {
    1387           5 :   case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1388           0 :   case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1389           0 :   case MVT::v16i8: return fastEmit_ISD_AND_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1390           0 :   case MVT::v8i16: return fastEmit_ISD_AND_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1391           0 :   case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1392           0 :   case MVT::v2i64: return fastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1393             :   default: return 0;
    1394             :   }
    1395             : }
    1396             : 
    1397             : // FastEmit functions for ISD::FADD.
    1398             : 
    1399           0 : unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1400           0 :   if (RetVT.SimpleTy != MVT::f32)
    1401             :     return 0;
    1402           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
    1403           0 :     return fastEmitInst_rr(Mips::FADD_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1404             :   }
    1405             :   return 0;
    1406             : }
    1407             : 
    1408           0 : unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1409           0 :   if (RetVT.SimpleTy != MVT::f64)
    1410             :     return 0;
    1411           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
    1412           0 :     return fastEmitInst_rr(Mips::FADD_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1413             :   }
    1414           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
    1415           0 :     return fastEmitInst_rr(Mips::FADD_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1416             :   }
    1417             :   return 0;
    1418             : }
    1419             : 
    1420           0 : unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1421           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1422             :     return 0;
    1423           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1424           0 :     return fastEmitInst_rr(Mips::FADD_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1425             :   }
    1426             :   return 0;
    1427             : }
    1428             : 
    1429           0 : unsigned fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1430           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1431             :     return 0;
    1432           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1433           0 :     return fastEmitInst_rr(Mips::FADD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1434             :   }
    1435             :   return 0;
    1436             : }
    1437             : 
    1438           0 : unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1439           0 :   switch (VT.SimpleTy) {
    1440           0 :   case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1441           0 :   case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1442           0 :   case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1443           0 :   case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1444             :   default: return 0;
    1445             :   }
    1446             : }
    1447             : 
    1448             : // FastEmit functions for ISD::FDIV.
    1449             : 
    1450           0 : unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1451           0 :   if (RetVT.SimpleTy != MVT::f32)
    1452             :     return 0;
    1453           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
    1454           0 :     return fastEmitInst_rr(Mips::FDIV_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1455             :   }
    1456             :   return 0;
    1457             : }
    1458             : 
    1459           0 : unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1460           0 :   if (RetVT.SimpleTy != MVT::f64)
    1461             :     return 0;
    1462           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
    1463           0 :     return fastEmitInst_rr(Mips::FDIV_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1464             :   }
    1465           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
    1466           0 :     return fastEmitInst_rr(Mips::FDIV_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1467             :   }
    1468             :   return 0;
    1469             : }
    1470             : 
    1471           0 : unsigned fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1472           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1473             :     return 0;
    1474           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1475           0 :     return fastEmitInst_rr(Mips::FDIV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1476             :   }
    1477             :   return 0;
    1478             : }
    1479             : 
    1480           0 : unsigned fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1481           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1482             :     return 0;
    1483           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1484           0 :     return fastEmitInst_rr(Mips::FDIV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1485             :   }
    1486             :   return 0;
    1487             : }
    1488             : 
    1489           0 : unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1490           0 :   switch (VT.SimpleTy) {
    1491           0 :   case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1492           0 :   case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1493           0 :   case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1494           0 :   case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1495             :   default: return 0;
    1496             :   }
    1497             : }
    1498             : 
    1499             : // FastEmit functions for ISD::FMUL.
    1500             : 
    1501           0 : unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1502           0 :   if (RetVT.SimpleTy != MVT::f32)
    1503             :     return 0;
    1504           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
    1505           0 :     return fastEmitInst_rr(Mips::FMUL_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1506             :   }
    1507             :   return 0;
    1508             : }
    1509             : 
    1510           0 : unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1511           0 :   if (RetVT.SimpleTy != MVT::f64)
    1512             :     return 0;
    1513           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
    1514           0 :     return fastEmitInst_rr(Mips::FMUL_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1515             :   }
    1516           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
    1517           0 :     return fastEmitInst_rr(Mips::FMUL_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1518             :   }
    1519             :   return 0;
    1520             : }
    1521             : 
    1522           0 : unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1523           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1524             :     return 0;
    1525           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1526           0 :     return fastEmitInst_rr(Mips::FMUL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1527             :   }
    1528             :   return 0;
    1529             : }
    1530             : 
    1531           0 : unsigned fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1532           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1533             :     return 0;
    1534           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1535           0 :     return fastEmitInst_rr(Mips::FMUL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1536             :   }
    1537             :   return 0;
    1538             : }
    1539             : 
    1540           0 : unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1541           0 :   switch (VT.SimpleTy) {
    1542           0 :   case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1543           0 :   case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1544           0 :   case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1545           0 :   case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1546             :   default: return 0;
    1547             :   }
    1548             : }
    1549             : 
    1550             : // FastEmit functions for ISD::FSUB.
    1551             : 
    1552           0 : unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1553           0 :   if (RetVT.SimpleTy != MVT::f32)
    1554             :     return 0;
    1555           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
    1556           0 :     return fastEmitInst_rr(Mips::FSUB_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1557             :   }
    1558             :   return 0;
    1559             : }
    1560             : 
    1561           0 : unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1562           0 :   if (RetVT.SimpleTy != MVT::f64)
    1563             :     return 0;
    1564           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
    1565           0 :     return fastEmitInst_rr(Mips::FSUB_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1566             :   }
    1567           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
    1568           0 :     return fastEmitInst_rr(Mips::FSUB_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1569             :   }
    1570             :   return 0;
    1571             : }
    1572             : 
    1573           0 : unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1574           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1575             :     return 0;
    1576           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1577           0 :     return fastEmitInst_rr(Mips::FSUB_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1578             :   }
    1579             :   return 0;
    1580             : }
    1581             : 
    1582           0 : unsigned fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1583           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1584             :     return 0;
    1585           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1586           0 :     return fastEmitInst_rr(Mips::FSUB_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1587             :   }
    1588             :   return 0;
    1589             : }
    1590             : 
    1591           0 : unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1592           0 :   switch (VT.SimpleTy) {
    1593           0 :   case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1594           0 :   case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1595           0 :   case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1596           0 :   case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1597             :   default: return 0;
    1598             :   }
    1599             : }
    1600             : 
    1601             : // FastEmit functions for ISD::MUL.
    1602             : 
    1603           2 : unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1604           2 :   if (RetVT.SimpleTy != MVT::i32)
    1605             :     return 0;
    1606           2 :   if ((Subtarget->inMips16Mode())) {
    1607           0 :     return fastEmitInst_rr(Mips::MultRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1608             :   }
    1609           2 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding())) {
    1610           0 :     return fastEmitInst_rr(Mips::MUL_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1611             :   }
    1612           2 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1613           0 :     return fastEmitInst_rr(Mips::MUL_R6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1614             :   }
    1615           8 :   if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    1616           2 :     return fastEmitInst_rr(Mips::MUL, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1617             :   }
    1618             :   return 0;
    1619             : }
    1620             : 
    1621           0 : unsigned fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1622           0 :   if (RetVT.SimpleTy != MVT::i64)
    1623             :     return 0;
    1624           0 :   if ((Subtarget->inMicroMips64r6Mode()) && (Subtarget->hasStandardEncoding())) {
    1625           0 :     return fastEmitInst_rr(Mips::DMUL_MM64R6, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1626             :   }
    1627           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1628           0 :     return fastEmitInst_rr(Mips::DMUL_R6, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1629             :   }
    1630           0 :   if ((Subtarget->hasCnMips())) {
    1631           0 :     return fastEmitInst_rr(Mips::DMUL, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1632             :   }
    1633             :   return 0;
    1634             : }
    1635             : 
    1636           0 : unsigned fastEmit_ISD_MUL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1637           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1638             :     return 0;
    1639           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1640           0 :     return fastEmitInst_rr(Mips::MULV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1641             :   }
    1642             :   return 0;
    1643             : }
    1644             : 
    1645             : unsigned fastEmit_ISD_MUL_MVT_v2i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1646           0 :   if (RetVT.SimpleTy != MVT::v2i16)
    1647             :     return 0;
    1648           0 :   if ((Subtarget->hasDSPR2())) {
    1649           0 :     return fastEmitInst_rr(Mips::MUL_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1650             :   }
    1651             :   return 0;
    1652             : }
    1653             : 
    1654           0 : unsigned fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1655           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1656             :     return 0;
    1657           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1658           0 :     return fastEmitInst_rr(Mips::MULV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1659             :   }
    1660             :   return 0;
    1661             : }
    1662             : 
    1663           0 : unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1664           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1665             :     return 0;
    1666           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1667           0 :     return fastEmitInst_rr(Mips::MULV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1668             :   }
    1669             :   return 0;
    1670             : }
    1671             : 
    1672           0 : unsigned fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1673           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1674             :     return 0;
    1675           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1676           0 :     return fastEmitInst_rr(Mips::MULV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1677             :   }
    1678             :   return 0;
    1679             : }
    1680             : 
    1681           2 : unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1682           2 :   switch (VT.SimpleTy) {
    1683           2 :   case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1684           0 :   case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1685           0 :   case MVT::v16i8: return fastEmit_ISD_MUL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1686           0 :   case MVT::v2i16: return fastEmit_ISD_MUL_MVT_v2i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1687           0 :   case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1688           0 :   case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1689           0 :   case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1690             :   default: return 0;
    1691             :   }
    1692             : }
    1693             : 
    1694             : // FastEmit functions for ISD::MULHS.
    1695             : 
    1696           0 : unsigned fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1697           0 :   if (RetVT.SimpleTy != MVT::i32)
    1698             :     return 0;
    1699           0 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding())) {
    1700           0 :     return fastEmitInst_rr(Mips::MUH_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1701             :   }
    1702           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1703           0 :     return fastEmitInst_rr(Mips::MUH, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1704             :   }
    1705             :   return 0;
    1706             : }
    1707             : 
    1708           0 : unsigned fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1709           0 :   if (RetVT.SimpleTy != MVT::i64)
    1710             :     return 0;
    1711           0 :   if ((Subtarget->inMicroMips64r6Mode()) && (Subtarget->hasStandardEncoding())) {
    1712           0 :     return fastEmitInst_rr(Mips::DMUH_MM64R6, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1713             :   }
    1714           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1715           0 :     return fastEmitInst_rr(Mips::DMUH, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1716             :   }
    1717             :   return 0;
    1718             : }
    1719             : 
    1720           0 : unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1721           0 :   switch (VT.SimpleTy) {
    1722           0 :   case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1723           0 :   case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1724             :   default: return 0;
    1725             :   }
    1726             : }
    1727             : 
    1728             : // FastEmit functions for ISD::MULHU.
    1729             : 
    1730           0 : unsigned fastEmit_ISD_MULHU_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1731           0 :   if (RetVT.SimpleTy != MVT::i32)
    1732             :     return 0;
    1733           0 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding())) {
    1734           0 :     return fastEmitInst_rr(Mips::MUHU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1735             :   }
    1736           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1737           0 :     return fastEmitInst_rr(Mips::MUHU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1738             :   }
    1739             :   return 0;
    1740             : }
    1741             : 
    1742           0 : unsigned fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1743           0 :   if (RetVT.SimpleTy != MVT::i64)
    1744             :     return 0;
    1745           0 :   if ((Subtarget->inMicroMips64r6Mode()) && (Subtarget->hasStandardEncoding())) {
    1746           0 :     return fastEmitInst_rr(Mips::DMUHU_MM64R6, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1747             :   }
    1748           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1749           0 :     return fastEmitInst_rr(Mips::DMUHU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1750             :   }
    1751             :   return 0;
    1752             : }
    1753             : 
    1754           0 : unsigned fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1755           0 :   switch (VT.SimpleTy) {
    1756           0 :   case MVT::i32: return fastEmit_ISD_MULHU_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1757           0 :   case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1758             :   default: return 0;
    1759             :   }
    1760             : }
    1761             : 
    1762             : // FastEmit functions for ISD::OR.
    1763             : 
    1764           4 : unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1765           4 :   if (RetVT.SimpleTy != MVT::i32)
    1766             :     return 0;
    1767           4 :   if ((Subtarget->inMicroMips32r6Mode())) {
    1768           0 :     return fastEmitInst_rr(Mips::OR16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1769             :   }
    1770           4 :   if ((Subtarget->inMips16Mode())) {
    1771           0 :     return fastEmitInst_rr(Mips::OrRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1772             :   }
    1773           4 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding())) {
    1774           0 :     return fastEmitInst_rr(Mips::OR_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1775             :   }
    1776           4 :   if ((Subtarget->inMicroMipsMode())) {
    1777           0 :     return fastEmitInst_rr(Mips::OR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1778             :   }
    1779           4 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    1780             :     return fastEmitInst_rr(Mips::OR16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1781             :   }
    1782           8 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1783           8 :     return fastEmitInst_rr(Mips::OR, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1784             :   }
    1785             :   return 0;
    1786             : }
    1787             : 
    1788             : unsigned fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1789           0 :   if (RetVT.SimpleTy != MVT::i64)
    1790             :     return 0;
    1791           0 :   if ((Subtarget->hasStandardEncoding())) {
    1792           0 :     return fastEmitInst_rr(Mips::OR64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1793             :   }
    1794             :   return 0;
    1795             : }
    1796             : 
    1797           0 : unsigned fastEmit_ISD_OR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1798           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1799             :     return 0;
    1800           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1801           0 :     return fastEmitInst_rr(Mips::OR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1802             :   }
    1803             :   return 0;
    1804             : }
    1805             : 
    1806             : unsigned fastEmit_ISD_OR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1807           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1808             :     return 0;
    1809           0 :   if ((Subtarget->hasMSA())) {
    1810           0 :     return fastEmitInst_rr(Mips::OR_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1811             :   }
    1812             :   return 0;
    1813             : }
    1814             : 
    1815             : unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1816           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1817             :     return 0;
    1818           0 :   if ((Subtarget->hasMSA())) {
    1819           0 :     return fastEmitInst_rr(Mips::OR_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1820             :   }
    1821             :   return 0;
    1822             : }
    1823             : 
    1824             : unsigned fastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1825           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1826             :     return 0;
    1827           0 :   if ((Subtarget->hasMSA())) {
    1828           0 :     return fastEmitInst_rr(Mips::OR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1829             :   }
    1830             :   return 0;
    1831             : }
    1832             : 
    1833           4 : unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1834           4 :   switch (VT.SimpleTy) {
    1835           4 :   case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1836           0 :   case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1837           0 :   case MVT::v16i8: return fastEmit_ISD_OR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1838           0 :   case MVT::v8i16: return fastEmit_ISD_OR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1839           0 :   case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1840           0 :   case MVT::v2i64: return fastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1841             :   default: return 0;
    1842             :   }
    1843             : }
    1844             : 
    1845             : // FastEmit functions for ISD::ROTR.
    1846             : 
    1847           0 : unsigned fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1848           0 :   if (RetVT.SimpleTy != MVT::i32)
    1849             :     return 0;
    1850           0 :   if ((Subtarget->inMicroMipsMode())) {
    1851           0 :     return fastEmitInst_rr(Mips::ROTRV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1852             :   }
    1853           0 :   if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1854           0 :     return fastEmitInst_rr(Mips::ROTRV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1855             :   }
    1856             :   return 0;
    1857             : }
    1858             : 
    1859             : unsigned fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1860           0 :   switch (VT.SimpleTy) {
    1861           0 :   case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1862             :   default: return 0;
    1863             :   }
    1864             : }
    1865             : 
    1866             : // FastEmit functions for ISD::SDIV.
    1867             : 
    1868           4 : unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1869           4 :   if (RetVT.SimpleTy != MVT::i32)
    1870             :     return 0;
    1871           4 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding())) {
    1872           0 :     return fastEmitInst_rr(Mips::DIV_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1873             :   }
    1874           4 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1875           0 :     return fastEmitInst_rr(Mips::DIV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1876             :   }
    1877             :   return 0;
    1878             : }
    1879             : 
    1880           0 : unsigned fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1881           0 :   if (RetVT.SimpleTy != MVT::i64)
    1882             :     return 0;
    1883           0 :   if ((Subtarget->inMicroMips64r6Mode()) && (Subtarget->hasStandardEncoding())) {
    1884           0 :     return fastEmitInst_rr(Mips::DDIV_MM64R6, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1885             :   }
    1886           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1887           0 :     return fastEmitInst_rr(Mips::DDIV, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1888             :   }
    1889             :   return 0;
    1890             : }
    1891             : 
    1892           0 : unsigned fastEmit_ISD_SDIV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1893           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1894             :     return 0;
    1895           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1896           0 :     return fastEmitInst_rr(Mips::DIV_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1897             :   }
    1898             :   return 0;
    1899             : }
    1900             : 
    1901           0 : unsigned fastEmit_ISD_SDIV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1902           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1903             :     return 0;
    1904           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1905           0 :     return fastEmitInst_rr(Mips::DIV_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1906             :   }
    1907             :   return 0;
    1908             : }
    1909             : 
    1910           0 : unsigned fastEmit_ISD_SDIV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1911           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1912             :     return 0;
    1913           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1914           0 :     return fastEmitInst_rr(Mips::DIV_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1915             :   }
    1916             :   return 0;
    1917             : }
    1918             : 
    1919           0 : unsigned fastEmit_ISD_SDIV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1920           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1921             :     return 0;
    1922           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1923           0 :     return fastEmitInst_rr(Mips::DIV_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1924             :   }
    1925             :   return 0;
    1926             : }
    1927             : 
    1928           4 : unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1929           4 :   switch (VT.SimpleTy) {
    1930           4 :   case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1931           0 :   case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1932           0 :   case MVT::v16i8: return fastEmit_ISD_SDIV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1933           0 :   case MVT::v8i16: return fastEmit_ISD_SDIV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1934           0 :   case MVT::v4i32: return fastEmit_ISD_SDIV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1935           0 :   case MVT::v2i64: return fastEmit_ISD_SDIV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1936             :   default: return 0;
    1937             :   }
    1938             : }
    1939             : 
    1940             : // FastEmit functions for ISD::SHL.
    1941             : 
    1942           0 : unsigned fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1943           0 :   if (RetVT.SimpleTy != MVT::i32)
    1944             :     return 0;
    1945           0 :   if ((Subtarget->inMicroMipsMode())) {
    1946           0 :     return fastEmitInst_rr(Mips::SLLV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1947             :   }
    1948           0 :   if ((Subtarget->inMips16Mode())) {
    1949           0 :     return fastEmitInst_rr(Mips::SllvRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1950             :   }
    1951           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1952           0 :     return fastEmitInst_rr(Mips::SLLV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1953             :   }
    1954             :   return 0;
    1955             : }
    1956             : 
    1957           0 : unsigned fastEmit_ISD_SHL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1958           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1959             :     return 0;
    1960           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1961           0 :     return fastEmitInst_rr(Mips::SLL_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1962             :   }
    1963             :   return 0;
    1964             : }
    1965             : 
    1966           0 : unsigned fastEmit_ISD_SHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1967           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1968             :     return 0;
    1969           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1970           0 :     return fastEmitInst_rr(Mips::SLL_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1971             :   }
    1972             :   return 0;
    1973             : }
    1974             : 
    1975           0 : unsigned fastEmit_ISD_SHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1976           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1977             :     return 0;
    1978           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1979           0 :     return fastEmitInst_rr(Mips::SLL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1980             :   }
    1981             :   return 0;
    1982             : }
    1983             : 
    1984           0 : unsigned fastEmit_ISD_SHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1985           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1986             :     return 0;
    1987           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1988           0 :     return fastEmitInst_rr(Mips::SLL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1989             :   }
    1990             :   return 0;
    1991             : }
    1992             : 
    1993           0 : unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1994           0 :   switch (VT.SimpleTy) {
    1995           0 :   case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1996           0 :   case MVT::v16i8: return fastEmit_ISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1997           0 :   case MVT::v8i16: return fastEmit_ISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1998           0 :   case MVT::v4i32: return fastEmit_ISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1999           0 :   case MVT::v2i64: return fastEmit_ISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2000             :   default: return 0;
    2001             :   }
    2002             : }
    2003             : 
    2004             : // FastEmit functions for ISD::SRA.
    2005             : 
    2006           0 : unsigned fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2007           0 :   if (RetVT.SimpleTy != MVT::i32)
    2008             :     return 0;
    2009           0 :   if ((Subtarget->inMicroMipsMode())) {
    2010           0 :     return fastEmitInst_rr(Mips::SRAV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2011             :   }
    2012           0 :   if ((Subtarget->inMips16Mode())) {
    2013           0 :     return fastEmitInst_rr(Mips::SravRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2014             :   }
    2015           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2016           0 :     return fastEmitInst_rr(Mips::SRAV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2017             :   }
    2018             :   return 0;
    2019             : }
    2020             : 
    2021           0 : unsigned fastEmit_ISD_SRA_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2022           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2023             :     return 0;
    2024           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2025           0 :     return fastEmitInst_rr(Mips::SRA_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2026             :   }
    2027             :   return 0;
    2028             : }
    2029             : 
    2030           0 : unsigned fastEmit_ISD_SRA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2031           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2032             :     return 0;
    2033           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2034           0 :     return fastEmitInst_rr(Mips::SRA_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2035             :   }
    2036             :   return 0;
    2037             : }
    2038             : 
    2039           0 : unsigned fastEmit_ISD_SRA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2040           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2041             :     return 0;
    2042           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2043           0 :     return fastEmitInst_rr(Mips::SRA_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2044             :   }
    2045             :   return 0;
    2046             : }
    2047             : 
    2048           0 : unsigned fastEmit_ISD_SRA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2049           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2050             :     return 0;
    2051           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2052           0 :     return fastEmitInst_rr(Mips::SRA_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2053             :   }
    2054             :   return 0;
    2055             : }
    2056             : 
    2057           0 : unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2058           0 :   switch (VT.SimpleTy) {
    2059           0 :   case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2060           0 :   case MVT::v16i8: return fastEmit_ISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2061           0 :   case MVT::v8i16: return fastEmit_ISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2062           0 :   case MVT::v4i32: return fastEmit_ISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2063           0 :   case MVT::v2i64: return fastEmit_ISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2064             :   default: return 0;
    2065             :   }
    2066             : }
    2067             : 
    2068             : // FastEmit functions for ISD::SREM.
    2069             : 
    2070           4 : unsigned fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2071           4 :   if (RetVT.SimpleTy != MVT::i32)
    2072             :     return 0;
    2073           4 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding())) {
    2074           0 :     return fastEmitInst_rr(Mips::MOD_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2075             :   }
    2076           4 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2077           0 :     return fastEmitInst_rr(Mips::MOD, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2078             :   }
    2079             :   return 0;
    2080             : }
    2081             : 
    2082           0 : unsigned fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2083           0 :   if (RetVT.SimpleTy != MVT::i64)
    2084             :     return 0;
    2085           0 :   if ((Subtarget->inMicroMips64r6Mode()) && (Subtarget->hasStandardEncoding())) {
    2086           0 :     return fastEmitInst_rr(Mips::DMOD_MM64R6, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2087             :   }
    2088           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2089           0 :     return fastEmitInst_rr(Mips::DMOD, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2090             :   }
    2091             :   return 0;
    2092             : }
    2093             : 
    2094           0 : unsigned fastEmit_ISD_SREM_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2095           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2096             :     return 0;
    2097           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2098           0 :     return fastEmitInst_rr(Mips::MOD_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2099             :   }
    2100             :   return 0;
    2101             : }
    2102             : 
    2103           0 : unsigned fastEmit_ISD_SREM_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2104           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2105             :     return 0;
    2106           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2107           0 :     return fastEmitInst_rr(Mips::MOD_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2108             :   }
    2109             :   return 0;
    2110             : }
    2111             : 
    2112           0 : unsigned fastEmit_ISD_SREM_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2113           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2114             :     return 0;
    2115           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2116           0 :     return fastEmitInst_rr(Mips::MOD_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2117             :   }
    2118             :   return 0;
    2119             : }
    2120             : 
    2121           0 : unsigned fastEmit_ISD_SREM_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2122           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2123             :     return 0;
    2124           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2125           0 :     return fastEmitInst_rr(Mips::MOD_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2126             :   }
    2127             :   return 0;
    2128             : }
    2129             : 
    2130           4 : unsigned fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2131           4 :   switch (VT.SimpleTy) {
    2132           4 :   case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2133           0 :   case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2134           0 :   case MVT::v16i8: return fastEmit_ISD_SREM_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2135           0 :   case MVT::v8i16: return fastEmit_ISD_SREM_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2136           0 :   case MVT::v4i32: return fastEmit_ISD_SREM_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2137           0 :   case MVT::v2i64: return fastEmit_ISD_SREM_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2138             :   default: return 0;
    2139             :   }
    2140             : }
    2141             : 
    2142             : // FastEmit functions for ISD::SRL.
    2143             : 
    2144           0 : unsigned fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2145           0 :   if (RetVT.SimpleTy != MVT::i32)
    2146             :     return 0;
    2147           0 :   if ((Subtarget->inMicroMipsMode())) {
    2148           0 :     return fastEmitInst_rr(Mips::SRLV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2149             :   }
    2150           0 :   if ((Subtarget->inMips16Mode())) {
    2151           0 :     return fastEmitInst_rr(Mips::SrlvRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2152             :   }
    2153           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2154           0 :     return fastEmitInst_rr(Mips::SRLV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2155             :   }
    2156             :   return 0;
    2157             : }
    2158             : 
    2159           0 : unsigned fastEmit_ISD_SRL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2160           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2161             :     return 0;
    2162           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2163           0 :     return fastEmitInst_rr(Mips::SRL_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2164             :   }
    2165             :   return 0;
    2166             : }
    2167             : 
    2168           0 : unsigned fastEmit_ISD_SRL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2169           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2170             :     return 0;
    2171           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2172           0 :     return fastEmitInst_rr(Mips::SRL_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2173             :   }
    2174             :   return 0;
    2175             : }
    2176             : 
    2177           0 : unsigned fastEmit_ISD_SRL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2178           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2179             :     return 0;
    2180           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2181           0 :     return fastEmitInst_rr(Mips::SRL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2182             :   }
    2183             :   return 0;
    2184             : }
    2185             : 
    2186           0 : unsigned fastEmit_ISD_SRL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2187           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2188             :     return 0;
    2189           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2190           0 :     return fastEmitInst_rr(Mips::SRL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2191             :   }
    2192             :   return 0;
    2193             : }
    2194             : 
    2195           0 : unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2196           0 :   switch (VT.SimpleTy) {
    2197           0 :   case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2198           0 :   case MVT::v16i8: return fastEmit_ISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2199           0 :   case MVT::v8i16: return fastEmit_ISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2200           0 :   case MVT::v4i32: return fastEmit_ISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2201           0 :   case MVT::v2i64: return fastEmit_ISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2202             :   default: return 0;
    2203             :   }
    2204             : }
    2205             : 
    2206             : // FastEmit functions for ISD::SUB.
    2207             : 
    2208           0 : unsigned fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2209           0 :   if (RetVT.SimpleTy != MVT::i32)
    2210             :     return 0;
    2211           0 :   if ((Subtarget->inMicroMips32r6Mode())) {
    2212           0 :     return fastEmitInst_rr(Mips::SUBU16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2213             :   }
    2214           0 :   if ((Subtarget->inMips16Mode())) {
    2215           0 :     return fastEmitInst_rr(Mips::SubuRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2216             :   }
    2217           0 :   if ((Subtarget->inMicroMipsMode())) {
    2218           0 :     return fastEmitInst_rr(Mips::SUBu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2219             :   }
    2220           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    2221             :     return fastEmitInst_rr(Mips::SUBU16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2222             :   }
    2223           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2224           0 :     return fastEmitInst_rr(Mips::SUBu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2225             :   }
    2226             :   return 0;
    2227             : }
    2228             : 
    2229           0 : unsigned fastEmit_ISD_SUB_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2230           0 :   if (RetVT.SimpleTy != MVT::i64)
    2231             :     return 0;
    2232           0 :   if ((Subtarget->inMicroMips64r6Mode()) && (Subtarget->hasStandardEncoding())) {
    2233           0 :     return fastEmitInst_rr(Mips::DSUBU_MM64R6, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2234             :   }
    2235           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2236           0 :     return fastEmitInst_rr(Mips::DSUBu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2237             :   }
    2238             :   return 0;
    2239             : }
    2240             : 
    2241             : unsigned fastEmit_ISD_SUB_MVT_v4i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2242           0 :   if (RetVT.SimpleTy != MVT::v4i8)
    2243             :     return 0;
    2244           0 :   if ((Subtarget->hasDSP())) {
    2245           0 :     return fastEmitInst_rr(Mips::SUBU_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2246             :   }
    2247             :   return 0;
    2248             : }
    2249             : 
    2250           0 : unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2251           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2252             :     return 0;
    2253           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2254           0 :     return fastEmitInst_rr(Mips::SUBV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2255             :   }
    2256             :   return 0;
    2257             : }
    2258             : 
    2259             : unsigned fastEmit_ISD_SUB_MVT_v2i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2260           0 :   if (RetVT.SimpleTy != MVT::v2i16)
    2261             :     return 0;
    2262           0 :   if ((Subtarget->hasDSP())) {
    2263           0 :     return fastEmitInst_rr(Mips::SUBQ_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2264             :   }
    2265             :   return 0;
    2266             : }
    2267             : 
    2268           0 : unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2269           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2270             :     return 0;
    2271           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2272           0 :     return fastEmitInst_rr(Mips::SUBV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2273             :   }
    2274             :   return 0;
    2275             : }
    2276             : 
    2277           0 : unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2278           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2279             :     return 0;
    2280           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2281           0 :     return fastEmitInst_rr(Mips::SUBV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2282             :   }
    2283             :   return 0;
    2284             : }
    2285             : 
    2286           0 : unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2287           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2288             :     return 0;
    2289           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2290           0 :     return fastEmitInst_rr(Mips::SUBV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2291             :   }
    2292             :   return 0;
    2293             : }
    2294             : 
    2295           0 : unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2296           0 :   switch (VT.SimpleTy) {
    2297           0 :   case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2298           0 :   case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2299           0 :   case MVT::v4i8: return fastEmit_ISD_SUB_MVT_v4i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2300           0 :   case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2301           0 :   case MVT::v2i16: return fastEmit_ISD_SUB_MVT_v2i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2302           0 :   case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2303           0 :   case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2304           0 :   case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2305             :   default: return 0;
    2306             :   }
    2307             : }
    2308             : 
    2309             : // FastEmit functions for ISD::SUBC.
    2310             : 
    2311           0 : unsigned fastEmit_ISD_SUBC_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2312           0 :   if (RetVT.SimpleTy != MVT::i32)
    2313             :     return 0;
    2314           0 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding())) {
    2315           0 :     return fastEmitInst_rr(Mips::SUBU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2316             :   }
    2317           0 :   if ((Subtarget->inMicroMipsMode())) {
    2318           0 :     return fastEmitInst_rr(Mips::SUBu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2319             :   }
    2320           0 :   if ((Subtarget->inMips16Mode())) {
    2321           0 :     return fastEmitInst_rr(Mips::SubuRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2322             :   }
    2323           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2324           0 :     return fastEmitInst_rr(Mips::SUBu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2325             :   }
    2326             :   return 0;
    2327             : }
    2328             : 
    2329           0 : unsigned fastEmit_ISD_SUBC_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2330           0 :   if (RetVT.SimpleTy != MVT::i64)
    2331             :     return 0;
    2332           0 :   if ((Subtarget->inMicroMips64r6Mode()) && (Subtarget->hasStandardEncoding())) {
    2333           0 :     return fastEmitInst_rr(Mips::DSUBU_MM64R6, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2334             :   }
    2335           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2336           0 :     return fastEmitInst_rr(Mips::DSUBu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2337             :   }
    2338             :   return 0;
    2339             : }
    2340             : 
    2341           0 : unsigned fastEmit_ISD_SUBC_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2342           0 :   switch (VT.SimpleTy) {
    2343           0 :   case MVT::i32: return fastEmit_ISD_SUBC_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2344           0 :   case MVT::i64: return fastEmit_ISD_SUBC_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2345             :   default: return 0;
    2346             :   }
    2347             : }
    2348             : 
    2349             : // FastEmit functions for ISD::UDIV.
    2350             : 
    2351           4 : unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2352           4 :   if (RetVT.SimpleTy != MVT::i32)
    2353             :     return 0;
    2354           4 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding())) {
    2355           0 :     return fastEmitInst_rr(Mips::DIVU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2356             :   }
    2357           4 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2358           0 :     return fastEmitInst_rr(Mips::DIVU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2359             :   }
    2360             :   return 0;
    2361             : }
    2362             : 
    2363           0 : unsigned fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2364           0 :   if (RetVT.SimpleTy != MVT::i64)
    2365             :     return 0;
    2366           0 :   if ((Subtarget->inMicroMips64r6Mode()) && (Subtarget->hasStandardEncoding())) {
    2367           0 :     return fastEmitInst_rr(Mips::DDIVU_MM64R6, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2368             :   }
    2369           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2370           0 :     return fastEmitInst_rr(Mips::DDIVU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2371             :   }
    2372             :   return 0;
    2373             : }
    2374             : 
    2375           0 : unsigned fastEmit_ISD_UDIV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2376           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2377             :     return 0;
    2378           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2379           0 :     return fastEmitInst_rr(Mips::DIV_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2380             :   }
    2381             :   return 0;
    2382             : }
    2383             : 
    2384           0 : unsigned fastEmit_ISD_UDIV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2385           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2386             :     return 0;
    2387           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2388           0 :     return fastEmitInst_rr(Mips::DIV_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2389             :   }
    2390             :   return 0;
    2391             : }
    2392             : 
    2393           0 : unsigned fastEmit_ISD_UDIV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2394           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2395             :     return 0;
    2396           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2397           0 :     return fastEmitInst_rr(Mips::DIV_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2398             :   }
    2399             :   return 0;
    2400             : }
    2401             : 
    2402           0 : unsigned fastEmit_ISD_UDIV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2403           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2404             :     return 0;
    2405           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2406           0 :     return fastEmitInst_rr(Mips::DIV_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2407             :   }
    2408             :   return 0;
    2409             : }
    2410             : 
    2411           4 : unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2412           4 :   switch (VT.SimpleTy) {
    2413           4 :   case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2414           0 :   case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2415           0 :   case MVT::v16i8: return fastEmit_ISD_UDIV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2416           0 :   case MVT::v8i16: return fastEmit_ISD_UDIV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2417           0 :   case MVT::v4i32: return fastEmit_ISD_UDIV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2418           0 :   case MVT::v2i64: return fastEmit_ISD_UDIV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2419             :   default: return 0;
    2420             :   }
    2421             : }
    2422             : 
    2423             : // FastEmit functions for ISD::UREM.
    2424             : 
    2425           4 : unsigned fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2426           4 :   if (RetVT.SimpleTy != MVT::i32)
    2427             :     return 0;
    2428           4 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding())) {
    2429           0 :     return fastEmitInst_rr(Mips::MODU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2430             :   }
    2431           4 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2432           0 :     return fastEmitInst_rr(Mips::MODU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2433             :   }
    2434             :   return 0;
    2435             : }
    2436             : 
    2437           0 : unsigned fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2438           0 :   if (RetVT.SimpleTy != MVT::i64)
    2439             :     return 0;
    2440           0 :   if ((Subtarget->inMicroMips64r6Mode()) && (Subtarget->hasStandardEncoding())) {
    2441           0 :     return fastEmitInst_rr(Mips::DMODU_MM64R6, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2442             :   }
    2443           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2444           0 :     return fastEmitInst_rr(Mips::DMODU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2445             :   }
    2446             :   return 0;
    2447             : }
    2448             : 
    2449           0 : unsigned fastEmit_ISD_UREM_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2450           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2451             :     return 0;
    2452           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2453           0 :     return fastEmitInst_rr(Mips::MOD_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2454             :   }
    2455             :   return 0;
    2456             : }
    2457             : 
    2458           0 : unsigned fastEmit_ISD_UREM_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2459           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2460             :     return 0;
    2461           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2462           0 :     return fastEmitInst_rr(Mips::MOD_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2463             :   }
    2464             :   return 0;
    2465             : }
    2466             : 
    2467           0 : unsigned fastEmit_ISD_UREM_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2468           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2469             :     return 0;
    2470           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2471           0 :     return fastEmitInst_rr(Mips::MOD_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2472             :   }
    2473             :   return 0;
    2474             : }
    2475             : 
    2476           0 : unsigned fastEmit_ISD_UREM_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2477           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2478             :     return 0;
    2479           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2480           0 :     return fastEmitInst_rr(Mips::MOD_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2481             :   }
    2482             :   return 0;
    2483             : }
    2484             : 
    2485           4 : unsigned fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2486           4 :   switch (VT.SimpleTy) {
    2487           4 :   case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2488           0 :   case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2489           0 :   case MVT::v16i8: return fastEmit_ISD_UREM_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2490           0 :   case MVT::v8i16: return fastEmit_ISD_UREM_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2491           0 :   case MVT::v4i32: return fastEmit_ISD_UREM_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2492           0 :   case MVT::v2i64: return fastEmit_ISD_UREM_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2493             :   default: return 0;
    2494             :   }
    2495             : }
    2496             : 
    2497             : // FastEmit functions for ISD::XOR.
    2498             : 
    2499           4 : unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2500           4 :   if (RetVT.SimpleTy != MVT::i32)
    2501             :     return 0;
    2502           4 :   if ((Subtarget->inMicroMips32r6Mode())) {
    2503           0 :     return fastEmitInst_rr(Mips::XOR16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2504             :   }
    2505           4 :   if ((Subtarget->inMips16Mode())) {
    2506           0 :     return fastEmitInst_rr(Mips::XorRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2507             :   }
    2508           4 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding())) {
    2509           0 :     return fastEmitInst_rr(Mips::XOR_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2510             :   }
    2511           4 :   if ((Subtarget->inMicroMipsMode())) {
    2512           0 :     return fastEmitInst_rr(Mips::XOR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2513             :   }
    2514           4 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    2515             :     return fastEmitInst_rr(Mips::XOR16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2516             :   }
    2517           8 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2518           8 :     return fastEmitInst_rr(Mips::XOR, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2519             :   }
    2520             :   return 0;
    2521             : }
    2522             : 
    2523             : unsigned fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2524           0 :   if (RetVT.SimpleTy != MVT::i64)
    2525             :     return 0;
    2526           0 :   if ((Subtarget->hasStandardEncoding())) {
    2527           0 :     return fastEmitInst_rr(Mips::XOR64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2528             :   }
    2529             :   return 0;
    2530             : }
    2531             : 
    2532           0 : unsigned fastEmit_ISD_XOR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2533           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2534             :     return 0;
    2535           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2536           0 :     return fastEmitInst_rr(Mips::XOR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2537             :   }
    2538             :   return 0;
    2539             : }
    2540             : 
    2541             : unsigned fastEmit_ISD_XOR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2542           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2543             :     return 0;
    2544           0 :   if ((Subtarget->hasMSA())) {
    2545           0 :     return fastEmitInst_rr(Mips::XOR_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2546             :   }
    2547             :   return 0;
    2548             : }
    2549             : 
    2550             : unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2551           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2552             :     return 0;
    2553           0 :   if ((Subtarget->hasMSA())) {
    2554           0 :     return fastEmitInst_rr(Mips::XOR_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2555             :   }
    2556             :   return 0;
    2557             : }
    2558             : 
    2559             : unsigned fastEmit_ISD_XOR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2560           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2561             :     return 0;
    2562           0 :   if ((Subtarget->hasMSA())) {
    2563           0 :     return fastEmitInst_rr(Mips::XOR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2564             :   }
    2565             :   return 0;
    2566             : }
    2567             : 
    2568           4 : unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2569           4 :   switch (VT.SimpleTy) {
    2570           4 :   case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2571           0 :   case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2572           0 :   case MVT::v16i8: return fastEmit_ISD_XOR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2573           0 :   case MVT::v8i16: return fastEmit_ISD_XOR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2574           0 :   case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2575           0 :   case MVT::v2i64: return fastEmit_ISD_XOR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2576             :   default: return 0;
    2577             :   }
    2578             : }
    2579             : 
    2580             : // FastEmit functions for MipsISD::BuildPairF64.
    2581             : 
    2582           0 : unsigned fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2583           0 :   if (RetVT.SimpleTy != MVT::f64)
    2584             :     return 0;
    2585           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
    2586           0 :     return fastEmitInst_rr(Mips::BuildPairF64_64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2587             :   }
    2588           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
    2589           0 :     return fastEmitInst_rr(Mips::BuildPairF64, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2590             :   }
    2591             :   return 0;
    2592             : }
    2593             : 
    2594             : unsigned fastEmit_MipsISD_BuildPairF64_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2595           0 :   switch (VT.SimpleTy) {
    2596           0 :   case MVT::i32: return fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2597             :   default: return 0;
    2598             :   }
    2599             : }
    2600             : 
    2601             : // FastEmit functions for MipsISD::DivRem.
    2602             : 
    2603           0 : unsigned fastEmit_MipsISD_DivRem_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2604           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    2605             :     return 0;
    2606           0 :   if ((Subtarget->inMicroMipsMode())) {
    2607           0 :     return fastEmitInst_rr(Mips::SDIV_MM_Pseudo, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2608             :   }
    2609           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    2610           0 :     return fastEmitInst_rr(Mips::PseudoSDIV, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2611             :   }
    2612             :   return 0;
    2613             : }
    2614             : 
    2615           0 : unsigned fastEmit_MipsISD_DivRem_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2616           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    2617             :     return 0;
    2618           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    2619           0 :     return fastEmitInst_rr(Mips::PseudoDSDIV, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2620             :   }
    2621             :   return 0;
    2622             : }
    2623             : 
    2624           0 : unsigned fastEmit_MipsISD_DivRem_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2625           0 :   switch (VT.SimpleTy) {
    2626           0 :   case MVT::i32: return fastEmit_MipsISD_DivRem_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2627           0 :   case MVT::i64: return fastEmit_MipsISD_DivRem_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2628             :   default: return 0;
    2629             :   }
    2630             : }
    2631             : 
    2632             : // FastEmit functions for MipsISD::DivRem16.
    2633             : 
    2634             : unsigned fastEmit_MipsISD_DivRem16_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2635           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2636             :     return 0;
    2637           0 :   if ((Subtarget->inMips16Mode())) {
    2638           0 :     return fastEmitInst_rr(Mips::DivRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2639             :   }
    2640             :   return 0;
    2641             : }
    2642             : 
    2643           0 : unsigned fastEmit_MipsISD_DivRem16_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2644           0 :   switch (VT.SimpleTy) {
    2645           0 :   case MVT::i32: return fastEmit_MipsISD_DivRem16_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2646             :   default: return 0;
    2647             :   }
    2648             : }
    2649             : 
    2650             : // FastEmit functions for MipsISD::DivRemU.
    2651             : 
    2652           0 : unsigned fastEmit_MipsISD_DivRemU_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2653           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    2654             :     return 0;
    2655           0 :   if ((Subtarget->inMicroMipsMode())) {
    2656           0 :     return fastEmitInst_rr(Mips::UDIV_MM_Pseudo, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2657             :   }
    2658           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    2659           0 :     return fastEmitInst_rr(Mips::PseudoUDIV, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2660             :   }
    2661             :   return 0;
    2662             : }
    2663             : 
    2664           0 : unsigned fastEmit_MipsISD_DivRemU_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2665           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    2666             :     return 0;
    2667           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    2668           0 :     return fastEmitInst_rr(Mips::PseudoDUDIV, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2669             :   }
    2670             :   return 0;
    2671             : }
    2672             : 
    2673           0 : unsigned fastEmit_MipsISD_DivRemU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2674           0 :   switch (VT.SimpleTy) {
    2675           0 :   case MVT::i32: return fastEmit_MipsISD_DivRemU_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2676           0 :   case MVT::i64: return fastEmit_MipsISD_DivRemU_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2677             :   default: return 0;
    2678             :   }
    2679             : }
    2680             : 
    2681             : // FastEmit functions for MipsISD::DivRemU16.
    2682             : 
    2683             : unsigned fastEmit_MipsISD_DivRemU16_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2684           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2685             :     return 0;
    2686           0 :   if ((Subtarget->inMips16Mode())) {
    2687           0 :     return fastEmitInst_rr(Mips::DivuRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2688             :   }
    2689             :   return 0;
    2690             : }
    2691             : 
    2692           0 : unsigned fastEmit_MipsISD_DivRemU16_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2693           0 :   switch (VT.SimpleTy) {
    2694           0 :   case MVT::i32: return fastEmit_MipsISD_DivRemU16_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2695             :   default: return 0;
    2696             :   }
    2697             : }
    2698             : 
    2699             : // FastEmit functions for MipsISD::EH_RETURN.
    2700             : 
    2701             : unsigned fastEmit_MipsISD_EH_RETURN_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2702           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2703             :     return 0;
    2704           0 :   return fastEmitInst_rr(Mips::MIPSeh_return32, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2705             : }
    2706             : 
    2707             : unsigned fastEmit_MipsISD_EH_RETURN_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2708           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2709             :     return 0;
    2710           0 :   return fastEmitInst_rr(Mips::MIPSeh_return64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2711             : }
    2712             : 
    2713           0 : unsigned fastEmit_MipsISD_EH_RETURN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2714           0 :   switch (VT.SimpleTy) {
    2715           0 :   case MVT::i32: return fastEmit_MipsISD_EH_RETURN_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2716           0 :   case MVT::i64: return fastEmit_MipsISD_EH_RETURN_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2717             :   default: return 0;
    2718             :   }
    2719             : }
    2720             : 
    2721             : // FastEmit functions for MipsISD::ILVEV.
    2722             : 
    2723           0 : unsigned fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2724           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2725             :     return 0;
    2726           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2727           0 :     return fastEmitInst_rr(Mips::ILVEV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2728             :   }
    2729             :   return 0;
    2730             : }
    2731             : 
    2732           0 : unsigned fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2733           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2734             :     return 0;
    2735           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2736           0 :     return fastEmitInst_rr(Mips::ILVEV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2737             :   }
    2738             :   return 0;
    2739             : }
    2740             : 
    2741           0 : unsigned fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2742           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2743             :     return 0;
    2744           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2745           0 :     return fastEmitInst_rr(Mips::ILVEV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2746             :   }
    2747             :   return 0;
    2748             : }
    2749             : 
    2750           0 : unsigned fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2751           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2752             :     return 0;
    2753           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2754           0 :     return fastEmitInst_rr(Mips::ILVEV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2755             :   }
    2756             :   return 0;
    2757             : }
    2758             : 
    2759           0 : unsigned fastEmit_MipsISD_ILVEV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2760           0 :   switch (VT.SimpleTy) {
    2761           0 :   case MVT::v16i8: return fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2762           0 :   case MVT::v8i16: return fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2763           0 :   case MVT::v4i32: return fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2764           0 :   case MVT::v2i64: return fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2765             :   default: return 0;
    2766             :   }
    2767             : }
    2768             : 
    2769             : // FastEmit functions for MipsISD::ILVL.
    2770             : 
    2771           0 : unsigned fastEmit_MipsISD_ILVL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2772           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2773             :     return 0;
    2774           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2775           0 :     return fastEmitInst_rr(Mips::ILVL_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2776             :   }
    2777             :   return 0;
    2778             : }
    2779             : 
    2780           0 : unsigned fastEmit_MipsISD_ILVL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2781           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2782             :     return 0;
    2783           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2784           0 :     return fastEmitInst_rr(Mips::ILVL_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2785             :   }
    2786             :   return 0;
    2787             : }
    2788             : 
    2789           0 : unsigned fastEmit_MipsISD_ILVL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2790           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2791             :     return 0;
    2792           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2793           0 :     return fastEmitInst_rr(Mips::ILVL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2794             :   }
    2795             :   return 0;
    2796             : }
    2797             : 
    2798           0 : unsigned fastEmit_MipsISD_ILVL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2799           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2800             :     return 0;
    2801           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2802           0 :     return fastEmitInst_rr(Mips::ILVL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2803             :   }
    2804             :   return 0;
    2805             : }
    2806             : 
    2807           0 : unsigned fastEmit_MipsISD_ILVL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2808           0 :   switch (VT.SimpleTy) {
    2809           0 :   case MVT::v16i8: return fastEmit_MipsISD_ILVL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2810           0 :   case MVT::v8i16: return fastEmit_MipsISD_ILVL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2811           0 :   case MVT::v4i32: return fastEmit_MipsISD_ILVL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2812           0 :   case MVT::v2i64: return fastEmit_MipsISD_ILVL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2813             :   default: return 0;
    2814             :   }
    2815             : }
    2816             : 
    2817             : // FastEmit functions for MipsISD::ILVOD.
    2818             : 
    2819           0 : unsigned fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2820           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2821             :     return 0;
    2822           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2823           0 :     return fastEmitInst_rr(Mips::ILVOD_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2824             :   }
    2825             :   return 0;
    2826             : }
    2827             : 
    2828           0 : unsigned fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2829           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2830             :     return 0;
    2831           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2832           0 :     return fastEmitInst_rr(Mips::ILVOD_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2833             :   }
    2834             :   return 0;
    2835             : }
    2836             : 
    2837           0 : unsigned fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2838           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2839             :     return 0;
    2840           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2841           0 :     return fastEmitInst_rr(Mips::ILVOD_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2842             :   }
    2843             :   return 0;
    2844             : }
    2845             : 
    2846           0 : unsigned fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2847           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2848             :     return 0;
    2849           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2850           0 :     return fastEmitInst_rr(Mips::ILVOD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2851             :   }
    2852             :   return 0;
    2853             : }
    2854             : 
    2855           0 : unsigned fastEmit_MipsISD_ILVOD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2856           0 :   switch (VT.SimpleTy) {
    2857           0 :   case MVT::v16i8: return fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2858           0 :   case MVT::v8i16: return fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2859           0 :   case MVT::v4i32: return fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2860           0 :   case MVT::v2i64: return fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2861             :   default: return 0;
    2862             :   }
    2863             : }
    2864             : 
    2865             : // FastEmit functions for MipsISD::ILVR.
    2866             : 
    2867           0 : unsigned fastEmit_MipsISD_ILVR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2868           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2869             :     return 0;
    2870           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2871           0 :     return fastEmitInst_rr(Mips::ILVR_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2872             :   }
    2873             :   return 0;
    2874             : }
    2875             : 
    2876           0 : unsigned fastEmit_MipsISD_ILVR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2877           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2878             :     return 0;
    2879           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2880           0 :     return fastEmitInst_rr(Mips::ILVR_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2881             :   }
    2882             :   return 0;
    2883             : }
    2884             : 
    2885           0 : unsigned fastEmit_MipsISD_ILVR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2886           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2887             :     return 0;
    2888           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2889           0 :     return fastEmitInst_rr(Mips::ILVR_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2890             :   }
    2891             :   return 0;
    2892             : }
    2893             : 
    2894           0 : unsigned fastEmit_MipsISD_ILVR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2895           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2896             :     return 0;
    2897           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2898           0 :     return fastEmitInst_rr(Mips::ILVR_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2899             :   }
    2900             :   return 0;
    2901             : }
    2902             : 
    2903           0 : unsigned fastEmit_MipsISD_ILVR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2904           0 :   switch (VT.SimpleTy) {
    2905           0 :   case MVT::v16i8: return fastEmit_MipsISD_ILVR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2906           0 :   case MVT::v8i16: return fastEmit_MipsISD_ILVR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2907           0 :   case MVT::v4i32: return fastEmit_MipsISD_ILVR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2908           0 :   case MVT::v2i64: return fastEmit_MipsISD_ILVR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2909             :   default: return 0;
    2910             :   }
    2911             : }
    2912             : 
    2913             : // FastEmit functions for MipsISD::MTLOHI.
    2914             : 
    2915             : unsigned fastEmit_MipsISD_MTLOHI_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2916           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    2917             :     return 0;
    2918           0 :   if ((Subtarget->hasStandardEncoding())) {
    2919           0 :     return fastEmitInst_rr(Mips::PseudoMTLOHI_DSP, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2920             :   }
    2921             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    2922             :     return fastEmitInst_rr(Mips::PseudoMTLOHI, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2923             :   }
    2924             :   return 0;
    2925             : }
    2926             : 
    2927           0 : unsigned fastEmit_MipsISD_MTLOHI_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2928           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    2929             :     return 0;
    2930           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    2931           0 :     return fastEmitInst_rr(Mips::PseudoMTLOHI64, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2932             :   }
    2933             :   return 0;
    2934             : }
    2935             : 
    2936           0 : unsigned fastEmit_MipsISD_MTLOHI_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2937           0 :   switch (VT.SimpleTy) {
    2938           0 :   case MVT::i32: return fastEmit_MipsISD_MTLOHI_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2939           0 :   case MVT::i64: return fastEmit_MipsISD_MTLOHI_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2940             :   default: return 0;
    2941             :   }
    2942             : }
    2943             : 
    2944             : // FastEmit functions for MipsISD::Mult.
    2945             : 
    2946           0 : unsigned fastEmit_MipsISD_Mult_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2947           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    2948             :     return 0;
    2949           0 :   if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
    2950           0 :     return fastEmitInst_rr(Mips::MULT_DSP_MM, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2951             :   }
    2952           0 :   if ((Subtarget->hasDSP())) {
    2953           0 :     return fastEmitInst_rr(Mips::MULT_DSP, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2954             :   }
    2955           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    2956           0 :     return fastEmitInst_rr(Mips::PseudoMULT, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2957             :   }
    2958             :   return 0;
    2959             : }
    2960             : 
    2961           0 : unsigned fastEmit_MipsISD_Mult_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2962           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    2963             :     return 0;
    2964           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    2965           0 :     return fastEmitInst_rr(Mips::PseudoDMULT, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2966             :   }
    2967             :   return 0;
    2968             : }
    2969             : 
    2970           0 : unsigned fastEmit_MipsISD_Mult_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2971           0 :   switch (VT.SimpleTy) {
    2972           0 :   case MVT::i32: return fastEmit_MipsISD_Mult_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2973           0 :   case MVT::i64: return fastEmit_MipsISD_Mult_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2974             :   default: return 0;
    2975             :   }
    2976             : }
    2977             : 
    2978             : // FastEmit functions for MipsISD::Multu.
    2979             : 
    2980           0 : unsigned fastEmit_MipsISD_Multu_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2981           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    2982             :     return 0;
    2983           0 :   if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
    2984           0 :     return fastEmitInst_rr(Mips::MULTU_DSP_MM, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2985             :   }
    2986           0 :   if ((Subtarget->hasDSP())) {
    2987           0 :     return fastEmitInst_rr(Mips::MULTU_DSP, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2988             :   }
    2989           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    2990           0 :     return fastEmitInst_rr(Mips::PseudoMULTu, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2991             :   }
    2992             :   return 0;
    2993             : }
    2994             : 
    2995           0 : unsigned fastEmit_MipsISD_Multu_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2996           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    2997             :     return 0;
    2998           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    2999           0 :     return fastEmitInst_rr(Mips::PseudoDMULTu, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3000             :   }
    3001             :   return 0;
    3002             : }
    3003             : 
    3004           0 : unsigned fastEmit_MipsISD_Multu_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3005           0 :   switch (VT.SimpleTy) {
    3006           0 :   case MVT::i32: return fastEmit_MipsISD_Multu_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3007           0 :   case MVT::i64: return fastEmit_MipsISD_Multu_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3008             :   default: return 0;
    3009             :   }
    3010             : }
    3011             : 
    3012             : // FastEmit functions for MipsISD::PCKEV.
    3013             : 
    3014           0 : unsigned fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3015           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3016             :     return 0;
    3017           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3018           0 :     return fastEmitInst_rr(Mips::PCKEV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3019             :   }
    3020             :   return 0;
    3021             : }
    3022             : 
    3023           0 : unsigned fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3024           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3025             :     return 0;
    3026           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3027           0 :     return fastEmitInst_rr(Mips::PCKEV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3028             :   }
    3029             :   return 0;
    3030             : }
    3031             : 
    3032           0 : unsigned fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3033           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3034             :     return 0;
    3035           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3036           0 :     return fastEmitInst_rr(Mips::PCKEV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3037             :   }
    3038             :   return 0;
    3039             : }
    3040             : 
    3041           0 : unsigned fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3042           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3043             :     return 0;
    3044           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3045           0 :     return fastEmitInst_rr(Mips::PCKEV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3046             :   }
    3047             :   return 0;
    3048             : }
    3049             : 
    3050           0 : unsigned fastEmit_MipsISD_PCKEV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3051           0 :   switch (VT.SimpleTy) {
    3052           0 :   case MVT::v16i8: return fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3053           0 :   case MVT::v8i16: return fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3054           0 :   case MVT::v4i32: return fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3055           0 :   case MVT::v2i64: return fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3056             :   default: return 0;
    3057             :   }
    3058             : }
    3059             : 
    3060             : // FastEmit functions for MipsISD::PCKOD.
    3061             : 
    3062           0 : unsigned fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3063           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3064             :     return 0;
    3065           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3066           0 :     return fastEmitInst_rr(Mips::PCKOD_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3067             :   }
    3068             :   return 0;
    3069             : }
    3070             : 
    3071           0 : unsigned fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3072           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3073             :     return 0;
    3074           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3075           0 :     return fastEmitInst_rr(Mips::PCKOD_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3076             :   }
    3077             :   return 0;
    3078             : }
    3079             : 
    3080           0 : unsigned fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3081           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3082             :     return 0;
    3083           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3084           0 :     return fastEmitInst_rr(Mips::PCKOD_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3085             :   }
    3086             :   return 0;
    3087             : }
    3088             : 
    3089           0 : unsigned fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3090           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3091             :     return 0;
    3092           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3093           0 :     return fastEmitInst_rr(Mips::PCKOD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3094             :   }
    3095             :   return 0;
    3096             : }
    3097             : 
    3098           0 : unsigned fastEmit_MipsISD_PCKOD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3099           0 :   switch (VT.SimpleTy) {
    3100           0 :   case MVT::v16i8: return fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3101           0 :   case MVT::v8i16: return fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3102           0 :   case MVT::v4i32: return fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3103           0 :   case MVT::v2i64: return fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3104             :   default: return 0;
    3105             :   }
    3106             : }
    3107             : 
    3108             : // FastEmit functions for MipsISD::VNOR.
    3109             : 
    3110           0 : unsigned fastEmit_MipsISD_VNOR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3111           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3112             :     return 0;
    3113           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3114           0 :     return fastEmitInst_rr(Mips::NOR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3115             :   }
    3116             :   return 0;
    3117             : }
    3118             : 
    3119             : unsigned fastEmit_MipsISD_VNOR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3120           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3121             :     return 0;
    3122           0 :   if ((Subtarget->hasMSA())) {
    3123           0 :     return fastEmitInst_rr(Mips::NOR_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3124             :   }
    3125             :   return 0;
    3126             : }
    3127             : 
    3128             : unsigned fastEmit_MipsISD_VNOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3129           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3130             :     return 0;
    3131           0 :   if ((Subtarget->hasMSA())) {
    3132           0 :     return fastEmitInst_rr(Mips::NOR_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3133             :   }
    3134             :   return 0;
    3135             : }
    3136             : 
    3137             : unsigned fastEmit_MipsISD_VNOR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3138           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3139             :     return 0;
    3140           0 :   if ((Subtarget->hasMSA())) {
    3141           0 :     return fastEmitInst_rr(Mips::NOR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3142             :   }
    3143             :   return 0;
    3144             : }
    3145             : 
    3146           0 : unsigned fastEmit_MipsISD_VNOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3147           0 :   switch (VT.SimpleTy) {
    3148           0 :   case MVT::v16i8: return fastEmit_MipsISD_VNOR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3149           0 :   case MVT::v8i16: return fastEmit_MipsISD_VNOR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3150           0 :   case MVT::v4i32: return fastEmit_MipsISD_VNOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3151           0 :   case MVT::v2i64: return fastEmit_MipsISD_VNOR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3152             :   default: return 0;
    3153             :   }
    3154             : }
    3155             : 
    3156             : // FastEmit functions for MipsISD::VSMAX.
    3157             : 
    3158           0 : unsigned fastEmit_MipsISD_VSMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3159           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3160             :     return 0;
    3161           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3162           0 :     return fastEmitInst_rr(Mips::MAX_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3163             :   }
    3164             :   return 0;
    3165             : }
    3166             : 
    3167           0 : unsigned fastEmit_MipsISD_VSMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3168           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3169             :     return 0;
    3170           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3171           0 :     return fastEmitInst_rr(Mips::MAX_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3172             :   }
    3173             :   return 0;
    3174             : }
    3175             : 
    3176           0 : unsigned fastEmit_MipsISD_VSMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3177           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3178             :     return 0;
    3179           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3180           0 :     return fastEmitInst_rr(Mips::MAX_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3181             :   }
    3182             :   return 0;
    3183             : }
    3184             : 
    3185           0 : unsigned fastEmit_MipsISD_VSMAX_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3186           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3187             :     return 0;
    3188           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3189           0 :     return fastEmitInst_rr(Mips::MAX_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3190             :   }
    3191             :   return 0;
    3192             : }
    3193             : 
    3194           0 : unsigned fastEmit_MipsISD_VSMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3195           0 :   switch (VT.SimpleTy) {
    3196           0 :   case MVT::v16i8: return fastEmit_MipsISD_VSMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3197           0 :   case MVT::v8i16: return fastEmit_MipsISD_VSMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3198           0 :   case MVT::v4i32: return fastEmit_MipsISD_VSMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3199           0 :   case MVT::v2i64: return fastEmit_MipsISD_VSMAX_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3200             :   default: return 0;
    3201             :   }
    3202             : }
    3203             : 
    3204             : // FastEmit functions for MipsISD::VSMIN.
    3205             : 
    3206           0 : unsigned fastEmit_MipsISD_VSMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3207           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3208             :     return 0;
    3209           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3210           0 :     return fastEmitInst_rr(Mips::MIN_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3211             :   }
    3212             :   return 0;
    3213             : }
    3214             : 
    3215           0 : unsigned fastEmit_MipsISD_VSMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3216           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3217             :     return 0;
    3218           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3219           0 :     return fastEmitInst_rr(Mips::MIN_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3220             :   }
    3221             :   return 0;
    3222             : }
    3223             : 
    3224           0 : unsigned fastEmit_MipsISD_VSMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3225           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3226             :     return 0;
    3227           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3228           0 :     return fastEmitInst_rr(Mips::MIN_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3229             :   }
    3230             :   return 0;
    3231             : }
    3232             : 
    3233           0 : unsigned fastEmit_MipsISD_VSMIN_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3234           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3235             :     return 0;
    3236           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3237           0 :     return fastEmitInst_rr(Mips::MIN_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3238             :   }
    3239             :   return 0;
    3240             : }
    3241             : 
    3242           0 : unsigned fastEmit_MipsISD_VSMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3243           0 :   switch (VT.SimpleTy) {
    3244           0 :   case MVT::v16i8: return fastEmit_MipsISD_VSMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3245           0 :   case MVT::v8i16: return fastEmit_MipsISD_VSMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3246           0 :   case MVT::v4i32: return fastEmit_MipsISD_VSMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3247           0 :   case MVT::v2i64: return fastEmit_MipsISD_VSMIN_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3248             :   default: return 0;
    3249             :   }
    3250             : }
    3251             : 
    3252             : // FastEmit functions for MipsISD::VUMAX.
    3253             : 
    3254           0 : unsigned fastEmit_MipsISD_VUMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3255           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3256             :     return 0;
    3257           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3258           0 :     return fastEmitInst_rr(Mips::MAX_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3259             :   }
    3260             :   return 0;
    3261             : }
    3262             : 
    3263           0 : unsigned fastEmit_MipsISD_VUMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3264           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3265             :     return 0;
    3266           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3267           0 :     return fastEmitInst_rr(Mips::MAX_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3268             :   }
    3269             :   return 0;
    3270             : }
    3271             : 
    3272           0 : unsigned fastEmit_MipsISD_VUMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3273           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3274             :     return 0;
    3275           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3276           0 :     return fastEmitInst_rr(Mips::MAX_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3277             :   }
    3278             :   return 0;
    3279             : }
    3280             : 
    3281           0 : unsigned fastEmit_MipsISD_VUMAX_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3282           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3283             :     return 0;
    3284           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3285           0 :     return fastEmitInst_rr(Mips::MAX_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3286             :   }
    3287             :   return 0;
    3288             : }
    3289             : 
    3290           0 : unsigned fastEmit_MipsISD_VUMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3291           0 :   switch (VT.SimpleTy) {
    3292           0 :   case MVT::v16i8: return fastEmit_MipsISD_VUMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3293           0 :   case MVT::v8i16: return fastEmit_MipsISD_VUMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3294           0 :   case MVT::v4i32: return fastEmit_MipsISD_VUMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3295           0 :   case MVT::v2i64: return fastEmit_MipsISD_VUMAX_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3296             :   default: return 0;
    3297             :   }
    3298             : }
    3299             : 
    3300             : // FastEmit functions for MipsISD::VUMIN.
    3301             : 
    3302           0 : unsigned fastEmit_MipsISD_VUMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3303           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3304             :     return 0;
    3305           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3306           0 :     return fastEmitInst_rr(Mips::MIN_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3307             :   }
    3308             :   return 0;
    3309             : }
    3310             : 
    3311           0 : unsigned fastEmit_MipsISD_VUMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3312           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3313             :     return 0;
    3314           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3315           0 :     return fastEmitInst_rr(Mips::MIN_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3316             :   }
    3317             :   return 0;
    3318             : }
    3319             : 
    3320           0 : unsigned fastEmit_MipsISD_VUMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3321           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3322             :     return 0;
    3323           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3324           0 :     return fastEmitInst_rr(Mips::MIN_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3325             :   }
    3326             :   return 0;
    3327             : }
    3328             : 
    3329           0 : unsigned fastEmit_MipsISD_VUMIN_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3330           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3331             :     return 0;
    3332           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3333           0 :     return fastEmitInst_rr(Mips::MIN_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3334             :   }
    3335             :   return 0;
    3336             : }
    3337             : 
    3338           0 : unsigned fastEmit_MipsISD_VUMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3339           0 :   switch (VT.SimpleTy) {
    3340           0 :   case MVT::v16i8: return fastEmit_MipsISD_VUMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3341           0 :   case MVT::v8i16: return fastEmit_MipsISD_VUMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3342           0 :   case MVT::v4i32: return fastEmit_MipsISD_VUMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3343           0 :   case MVT::v2i64: return fastEmit_MipsISD_VUMIN_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3344             :   default: return 0;
    3345             :   }
    3346             : }
    3347             : 
    3348             : // Top-level FastEmit function.
    3349             : 
    3350          37 : unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) override {
    3351          37 :   switch (Opcode) {
    3352           6 :   case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3353           0 :   case ISD::ADDC: return fastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3354           0 :   case ISD::ADDE: return fastEmit_ISD_ADDE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3355           5 :   case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3356           0 :   case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3357           0 :   case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3358           0 :   case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3359           0 :   case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3360           2 :   case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3361           0 :   case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3362           0 :   case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3363           4 :   case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3364           0 :   case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3365           4 :   case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3366           0 :   case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3367           0 :   case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3368           4 :   case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3369           0 :   case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3370           0 :   case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3371           0 :   case ISD::SUBC: return fastEmit_ISD_SUBC_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3372           4 :   case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3373           4 :   case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3374           4 :   case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3375           0 :   case MipsISD::BuildPairF64: return fastEmit_MipsISD_BuildPairF64_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3376           0 :   case MipsISD::DivRem: return fastEmit_MipsISD_DivRem_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3377           0 :   case MipsISD::DivRem16: return fastEmit_MipsISD_DivRem16_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3378           0 :   case MipsISD::DivRemU: return fastEmit_MipsISD_DivRemU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3379           0 :   case MipsISD::DivRemU16: return fastEmit_MipsISD_DivRemU16_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3380           0 :   case MipsISD::EH_RETURN: return fastEmit_MipsISD_EH_RETURN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3381           0 :   case MipsISD::ILVEV: return fastEmit_MipsISD_ILVEV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3382           0 :   case MipsISD::ILVL: return fastEmit_MipsISD_ILVL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3383           0 :   case MipsISD::ILVOD: return fastEmit_MipsISD_ILVOD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3384           0 :   case MipsISD::ILVR: return fastEmit_MipsISD_ILVR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3385           0 :   case MipsISD::MTLOHI: return fastEmit_MipsISD_MTLOHI_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3386           0 :   case MipsISD::Mult: return fastEmit_MipsISD_Mult_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3387           0 :   case MipsISD::Multu: return fastEmit_MipsISD_Multu_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3388           0 :   case MipsISD::PCKEV: return fastEmit_MipsISD_PCKEV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3389           0 :   case MipsISD::PCKOD: return fastEmit_MipsISD_PCKOD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3390           0 :   case MipsISD::VNOR: return fastEmit_MipsISD_VNOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3391           0 :   case MipsISD::VSMAX: return fastEmit_MipsISD_VSMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3392           0 :   case MipsISD::VSMIN: return fastEmit_MipsISD_VSMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3393           0 :   case MipsISD::VUMAX: return fastEmit_MipsISD_VUMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3394           0 :   case MipsISD::VUMIN: return fastEmit_MipsISD_VUMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3395             :   default: return 0;
    3396             :   }
    3397             : }
    3398             : 
    3399             : // FastEmit functions for MipsISD::ExtractElementF64.
    3400             : 
    3401           0 : unsigned fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3402           0 :   if (RetVT.SimpleTy != MVT::i32)
    3403             :     return 0;
    3404           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
    3405           0 :     return fastEmitInst_ri(Mips::ExtractElementF64_64, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3406             :   }
    3407           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
    3408           0 :     return fastEmitInst_ri(Mips::ExtractElementF64, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3409             :   }
    3410             :   return 0;
    3411             : }
    3412             : 
    3413             : unsigned fastEmit_MipsISD_ExtractElementF64_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3414           0 :   switch (VT.SimpleTy) {
    3415           0 :   case MVT::f64: return fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(RetVT, Op0, Op0IsKill, imm1);
    3416             :   default: return 0;
    3417             :   }
    3418             : }
    3419             : 
    3420             : // FastEmit functions for MipsISD::SHLL_DSP.
    3421             : 
    3422             : unsigned fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3423           0 :   if (RetVT.SimpleTy != MVT::v4i8)
    3424             :     return 0;
    3425           0 :   if ((Subtarget->hasDSP())) {
    3426           0 :     return fastEmitInst_ri(Mips::SHLL_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
    3427             :   }
    3428             :   return 0;
    3429             : }
    3430             : 
    3431             : unsigned fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3432           0 :   if (RetVT.SimpleTy != MVT::v2i16)
    3433             :     return 0;
    3434           0 :   if ((Subtarget->hasDSP())) {
    3435           0 :     return fastEmitInst_ri(Mips::SHLL_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
    3436             :   }
    3437             :   return 0;
    3438             : }
    3439             : 
    3440           0 : unsigned fastEmit_MipsISD_SHLL_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3441           0 :   switch (VT.SimpleTy) {
    3442           0 :   case MVT::v4i8: return fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(RetVT, Op0, Op0IsKill, imm1);
    3443           0 :   case MVT::v2i16: return fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(RetVT, Op0, Op0IsKill, imm1);
    3444             :   default: return 0;
    3445             :   }
    3446             : }
    3447             : 
    3448             : // FastEmit functions for MipsISD::SHRA_DSP.
    3449             : 
    3450             : unsigned fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3451           0 :   if (RetVT.SimpleTy != MVT::v4i8)
    3452             :     return 0;
    3453           0 :   if ((Subtarget->hasDSPR2())) {
    3454           0 :     return fastEmitInst_ri(Mips::SHRA_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
    3455             :   }
    3456             :   return 0;
    3457             : }
    3458             : 
    3459             : unsigned fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3460           0 :   if (RetVT.SimpleTy != MVT::v2i16)
    3461             :     return 0;
    3462           0 :   if ((Subtarget->hasDSP())) {
    3463           0 :     return fastEmitInst_ri(Mips::SHRA_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
    3464             :   }
    3465             :   return 0;
    3466             : }
    3467             : 
    3468           0 : unsigned fastEmit_MipsISD_SHRA_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3469           0 :   switch (VT.SimpleTy) {
    3470           0 :   case MVT::v4i8: return fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(RetVT, Op0, Op0IsKill, imm1);
    3471           0 :   case MVT::v2i16: return fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(RetVT, Op0, Op0IsKill, imm1);
    3472             :   default: return 0;
    3473             :   }
    3474             : }
    3475             : 
    3476             : // FastEmit functions for MipsISD::SHRL_DSP.
    3477             : 
    3478             : unsigned fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3479           0 :   if (RetVT.SimpleTy != MVT::v4i8)
    3480             :     return 0;
    3481           0 :   if ((Subtarget->hasDSP())) {
    3482           0 :     return fastEmitInst_ri(Mips::SHRL_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
    3483             :   }
    3484             :   return 0;
    3485             : }
    3486             : 
    3487             : unsigned fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3488           0 :   if (RetVT.SimpleTy != MVT::v2i16)
    3489             :     return 0;
    3490           0 :   if ((Subtarget->hasDSPR2())) {
    3491           0 :     return fastEmitInst_ri(Mips::SHRL_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
    3492             :   }
    3493             :   return 0;
    3494             : }
    3495             : 
    3496           0 : unsigned fastEmit_MipsISD_SHRL_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3497           0 :   switch (VT.SimpleTy) {
    3498           0 :   case MVT::v4i8: return fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(RetVT, Op0, Op0IsKill, imm1);
    3499           0 :   case MVT::v2i16: return fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(RetVT, Op0, Op0IsKill, imm1);
    3500             :   default: return 0;
    3501             :   }
    3502             : }
    3503             : 
    3504             : // Top-level FastEmit function.
    3505             : 
    3506           7 : unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) override {
    3507          14 :   if (VT == MVT::i32 && Predicate_immZExt5(imm1))
    3508           7 :     if (unsigned Reg = fastEmit_ri_Predicate_immZExt5(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3509             :       return Reg;
    3510             : 
    3511          14 :   if (VT == MVT::i32 && Predicate_immZExt6(imm1))
    3512           7 :     if (unsigned Reg = fastEmit_ri_Predicate_immZExt6(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3513             :       return Reg;
    3514             : 
    3515           7 :   if (VT == MVT::iPTR && Predicate_immZExt2Ptr(imm1))
    3516           0 :     if (unsigned Reg = fastEmit_ri_Predicate_immZExt2Ptr(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3517             :       return Reg;
    3518             : 
    3519           7 :   if (VT == MVT::iPTR && Predicate_immZExt1Ptr(imm1))
    3520           0 :     if (unsigned Reg = fastEmit_ri_Predicate_immZExt1Ptr(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3521             :       return Reg;
    3522             : 
    3523          14 :   if (VT == MVT::i32 && Predicate_immZExt4(imm1))
    3524           7 :     if (unsigned Reg = fastEmit_ri_Predicate_immZExt4(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3525             :       return Reg;
    3526             : 
    3527           7 :   if (VT == MVT::i32 && Predicate_immSExtAddiur2(imm1))
    3528           2 :     if (unsigned Reg = fastEmit_ri_Predicate_immSExtAddiur2(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3529             :       return Reg;
    3530             : 
    3531          14 :   if (VT == MVT::i32 && Predicate_immSExtAddius5(imm1))
    3532           8 :     if (unsigned Reg = fastEmit_ri_Predicate_immSExtAddius5(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3533             :       return Reg;
    3534             : 
    3535           7 :   if (VT == MVT::i32 && Predicate_immZExtAndi16(imm1))
    3536           1 :     if (unsigned Reg = fastEmit_ri_Predicate_immZExtAndi16(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3537             :       return Reg;
    3538             : 
    3539          14 :   if (VT == MVT::i32 && Predicate_immZExt2Shift(imm1))
    3540           1 :     if (unsigned Reg = fastEmit_ri_Predicate_immZExt2Shift(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3541             :       return Reg;
    3542             : 
    3543           7 :   switch (Opcode) {
    3544           0 :   case MipsISD::ExtractElementF64: return fastEmit_MipsISD_ExtractElementF64_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    3545           0 :   case MipsISD::SHLL_DSP: return fastEmit_MipsISD_SHLL_DSP_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    3546           0 :   case MipsISD::SHRA_DSP: return fastEmit_MipsISD_SHRA_DSP_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    3547           0 :   case MipsISD::SHRL_DSP: return fastEmit_MipsISD_SHRL_DSP_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    3548             :   default: return 0;
    3549             :   }
    3550             : }
    3551             : 
    3552             : // FastEmit functions for ISD::ROTR.
    3553             : 
    3554           0 : unsigned fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3555           0 :   if (RetVT.SimpleTy != MVT::i32)
    3556             :     return 0;
    3557           0 :   if ((Subtarget->inMicroMipsMode())) {
    3558           0 :     return fastEmitInst_ri(Mips::ROTR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3559             :   }
    3560           0 :   if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3561           0 :     return fastEmitInst_ri(Mips::ROTR, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3562             :   }
    3563             :   return 0;
    3564             : }
    3565             : 
    3566             : unsigned fastEmit_ISD_ROTR_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3567           0 :   switch (VT.SimpleTy) {
    3568           0 :   case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1);
    3569             :   default: return 0;
    3570             :   }
    3571             : }
    3572             : 
    3573             : // FastEmit functions for ISD::SHL.
    3574             : 
    3575           0 : unsigned fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3576           0 :   if (RetVT.SimpleTy != MVT::i32)
    3577             :     return 0;
    3578           0 :   if ((Subtarget->inMicroMipsMode())) {
    3579           0 :     return fastEmitInst_ri(Mips::SLL_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3580             :   }
    3581           0 :   if ((Subtarget->inMips16Mode())) {
    3582           0 :     return fastEmitInst_ri(Mips::SllX16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, imm1);
    3583             :   }
    3584           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3585           0 :     return fastEmitInst_ri(Mips::SLL, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3586             :   }
    3587             :   return 0;
    3588             : }
    3589             : 
    3590             : unsigned fastEmit_ISD_SHL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3591           0 :   switch (VT.SimpleTy) {
    3592           0 :   case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1);
    3593             :   default: return 0;
    3594             :   }
    3595             : }
    3596             : 
    3597             : // FastEmit functions for ISD::SRA.
    3598             : 
    3599           0 : unsigned fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3600           0 :   if (RetVT.SimpleTy != MVT::i32)
    3601             :     return 0;
    3602           0 :   if ((Subtarget->inMicroMipsMode())) {
    3603           0 :     return fastEmitInst_ri(Mips::SRA_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3604             :   }
    3605           0 :   if ((Subtarget->inMips16Mode())) {
    3606           0 :     return fastEmitInst_ri(Mips::SraX16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, imm1);
    3607             :   }
    3608           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3609           0 :     return fastEmitInst_ri(Mips::SRA, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3610             :   }
    3611             :   return 0;
    3612             : }
    3613             : 
    3614             : unsigned fastEmit_ISD_SRA_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3615           0 :   switch (VT.SimpleTy) {
    3616           0 :   case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1);
    3617             :   default: return 0;
    3618             :   }
    3619             : }
    3620             : 
    3621             : // FastEmit functions for ISD::SRL.
    3622             : 
    3623           0 : unsigned fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3624           0 :   if (RetVT.SimpleTy != MVT::i32)
    3625             :     return 0;
    3626           0 :   if ((Subtarget->inMicroMipsMode())) {
    3627           0 :     return fastEmitInst_ri(Mips::SRL_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3628             :   }
    3629           0 :   if ((Subtarget->inMips16Mode())) {
    3630           0 :     return fastEmitInst_ri(Mips::SrlX16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, imm1);
    3631             :   }
    3632           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3633           0 :     return fastEmitInst_ri(Mips::SRL, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3634             :   }
    3635             :   return 0;
    3636             : }
    3637             : 
    3638             : unsigned fastEmit_ISD_SRL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3639           0 :   switch (VT.SimpleTy) {
    3640           0 :   case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1);
    3641             :   default: return 0;
    3642             :   }
    3643             : }
    3644             : 
    3645             : // Top-level FastEmit function.
    3646             : 
    3647           7 : unsigned fastEmit_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3648           7 :   switch (Opcode) {
    3649           0 :   case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1);
    3650           0 :   case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1);
    3651           0 :   case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1);
    3652           0 :   case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1);
    3653             :   default: return 0;
    3654             :   }
    3655             : }
    3656             : 
    3657             : // FastEmit functions for ISD::ROTR.
    3658             : 
    3659           0 : unsigned fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3660           0 :   if (RetVT.SimpleTy != MVT::i64)
    3661             :     return 0;
    3662           0 :   if ((Subtarget->inMicroMips64r6Mode()) && (Subtarget->hasStandardEncoding())) {
    3663           0 :     return fastEmitInst_ri(Mips::DROTR_MM64R6, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
    3664             :   }
    3665           0 :   if ((Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3666           0 :     return fastEmitInst_ri(Mips::DROTR, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
    3667             :   }
    3668             :   return 0;
    3669             : }
    3670             : 
    3671             : unsigned fastEmit_ISD_ROTR_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3672           0 :   switch (VT.SimpleTy) {
    3673           0 :   case MVT::i64: return fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1);
    3674             :   default: return 0;
    3675             :   }
    3676             : }
    3677             : 
    3678             : // FastEmit functions for ISD::SHL.
    3679             : 
    3680           0 : unsigned fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3681           0 :   if (RetVT.SimpleTy != MVT::i64)
    3682             :     return 0;
    3683           0 :   if ((Subtarget->inMicroMips64r6Mode()) && (Subtarget->hasStandardEncoding())) {
    3684           0 :     return fastEmitInst_ri(Mips::DSLL_MM64R6, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
    3685             :   }
    3686           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3687           0 :     return fastEmitInst_ri(Mips::DSLL, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
    3688             :   }
    3689             :   return 0;
    3690             : }
    3691             : 
    3692             : unsigned fastEmit_ISD_SHL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3693           0 :   switch (VT.SimpleTy) {
    3694           0 :   case MVT::i64: return fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1);
    3695             :   default: return 0;
    3696             :   }
    3697             : }
    3698             : 
    3699             : // FastEmit functions for ISD::SRA.
    3700             : 
    3701           0 : unsigned fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3702           0 :   if (RetVT.SimpleTy != MVT::i64)
    3703             :     return 0;
    3704           0 :   if ((Subtarget->inMicroMips64r6Mode()) && (Subtarget->hasStandardEncoding())) {
    3705           0 :     return fastEmitInst_ri(Mips::DSRA_MM64R6, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
    3706             :   }
    3707           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3708           0 :     return fastEmitInst_ri(Mips::DSRA, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
    3709             :   }
    3710             :   return 0;
    3711             : }
    3712             : 
    3713             : unsigned fastEmit_ISD_SRA_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3714           0 :   switch (VT.SimpleTy) {
    3715           0 :   case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1);
    3716             :   default: return 0;
    3717             :   }
    3718             : }
    3719             : 
    3720             : // FastEmit functions for ISD::SRL.
    3721             : 
    3722           0 : unsigned fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3723           0 :   if (RetVT.SimpleTy != MVT::i64)
    3724             :     return 0;
    3725           0 :   if ((Subtarget->inMicroMips64r6Mode()) && (Subtarget->hasStandardEncoding())) {
    3726           0 :     return fastEmitInst_ri(Mips::DSRL_MM64R6, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
    3727             :   }
    3728           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3729           0 :     return fastEmitInst_ri(Mips::DSRL, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
    3730             :   }
    3731             :   return 0;
    3732             : }
    3733             : 
    3734             : unsigned fastEmit_ISD_SRL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3735           0 :   switch (VT.SimpleTy) {
    3736           0 :   case MVT::i64: return fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1);
    3737             :   default: return 0;
    3738             :   }
    3739             : }
    3740             : 
    3741             : // Top-level FastEmit function.
    3742             : 
    3743           7 : unsigned fastEmit_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3744           7 :   switch (Opcode) {
    3745           0 :   case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1);
    3746           0 :   case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1);
    3747           0 :   case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1);
    3748           0 :   case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1);
    3749             :   default: return 0;
    3750             :   }
    3751             : }
    3752             : 
    3753             : // FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
    3754             : 
    3755             : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3756           0 :   if (RetVT.SimpleTy != MVT::f32)
    3757             :     return 0;
    3758           0 :   if ((Subtarget->hasMSA())) {
    3759           0 :     return fastEmitInst_ri(Mips::COPY_FW_PSEUDO, &Mips::FGR32RegClass, Op0, Op0IsKill, imm1);
    3760             :   }
    3761             :   return 0;
    3762             : }
    3763             : 
    3764           0 : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3765           0 :   switch (VT.SimpleTy) {
    3766           0 :   case MVT::v4f32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(RetVT, Op0, Op0IsKill, imm1);
    3767             :   default: return 0;
    3768             :   }
    3769             : }
    3770             : 
    3771             : // Top-level FastEmit function.
    3772             : 
    3773             : unsigned fastEmit_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3774           0 :   switch (Opcode) {
    3775           0 :   case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(VT, RetVT, Op0, Op0IsKill, imm1);
    3776             :   default: return 0;
    3777             :   }
    3778             : }
    3779             : 
    3780             : // FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
    3781             : 
    3782             : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3783           0 :   if (RetVT.SimpleTy != MVT::f64)
    3784             :     return 0;
    3785           0 :   if ((Subtarget->hasMSA())) {
    3786           0 :     return fastEmitInst_ri(Mips::COPY_FD_PSEUDO, &Mips::FGR64RegClass, Op0, Op0IsKill, imm1);
    3787             :   }
    3788             :   return 0;
    3789             : }
    3790             : 
    3791           0 : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3792           0 :   switch (VT.SimpleTy) {
    3793           0 :   case MVT::v2f64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(RetVT, Op0, Op0IsKill, imm1);
    3794             :   default: return 0;
    3795             :   }
    3796             : }
    3797             : 
    3798             : // Top-level FastEmit function.
    3799             : 
    3800             : unsigned fastEmit_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3801           0 :   switch (Opcode) {
    3802           0 :   case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(VT, RetVT, Op0, Op0IsKill, imm1);
    3803             :   default: return 0;
    3804             :   }
    3805             : }
    3806             : 
    3807             : // FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
    3808             : 
    3809             : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3810           0 :   if (RetVT.SimpleTy != MVT::i32)
    3811             :     return 0;
    3812           0 :   if ((Subtarget->hasMSA())) {
    3813           0 :     return fastEmitInst_ri(Mips::COPY_S_W, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3814             :   }
    3815             :   return 0;
    3816             : }
    3817             : 
    3818           0 : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3819           0 :   switch (VT.SimpleTy) {
    3820           0 :   case MVT::v4i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(RetVT, Op0, Op0IsKill, imm1);
    3821             :   default: return 0;
    3822             :   }
    3823             : }
    3824             : 
    3825             : // Top-level FastEmit function.
    3826             : 
    3827             : unsigned fastEmit_ri_Predicate_immZExt4(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3828           7 :   switch (Opcode) {
    3829           0 :   case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(VT, RetVT, Op0, Op0IsKill, imm1);
    3830             :   default: return 0;
    3831             :   }
    3832             : }
    3833             : 
    3834             : // FastEmit functions for ISD::ADD.
    3835             : 
    3836             : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3837           1 :   if (RetVT.SimpleTy != MVT::i32)
    3838             :     return 0;
    3839           1 :   if ((Subtarget->inMicroMipsMode())) {
    3840           0 :     return fastEmitInst_ri(Mips::ADDIUR2_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
    3841             :   }
    3842             :   return 0;
    3843             : }
    3844             : 
    3845           1 : unsigned fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3846           1 :   switch (VT.SimpleTy) {
    3847           1 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(RetVT, Op0, Op0IsKill, imm1);
    3848             :   default: return 0;
    3849             :   }
    3850             : }
    3851             : 
    3852             : // Top-level FastEmit function.
    3853             : 
    3854             : unsigned fastEmit_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3855           1 :   switch (Opcode) {
    3856           1 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(VT, RetVT, Op0, Op0IsKill, imm1);
    3857             :   default: return 0;
    3858             :   }
    3859             : }
    3860             : 
    3861             : // FastEmit functions for ISD::ADD.
    3862             : 
    3863             : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3864           1 :   if (RetVT.SimpleTy != MVT::i32)
    3865             :     return 0;
    3866           1 :   if ((Subtarget->inMicroMipsMode())) {
    3867           0 :     return fastEmitInst_ri(Mips::ADDIUS5_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3868             :   }
    3869             :   return 0;
    3870             : }
    3871             : 
    3872           1 : unsigned fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3873           1 :   switch (VT.SimpleTy) {
    3874           1 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(RetVT, Op0, Op0IsKill, imm1);
    3875             :   default: return 0;
    3876             :   }
    3877             : }
    3878             : 
    3879             : // Top-level FastEmit function.
    3880             : 
    3881             : unsigned fastEmit_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3882           7 :   switch (Opcode) {
    3883           1 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(VT, RetVT, Op0, Op0IsKill, imm1);
    3884             :   default: return 0;
    3885             :   }
    3886             : }
    3887             : 
    3888             : // FastEmit functions for ISD::AND.
    3889             : 
    3890           0 : unsigned fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3891           0 :   if (RetVT.SimpleTy != MVT::i32)
    3892             :     return 0;
    3893           0 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding())) {
    3894           0 :     return fastEmitInst_ri(Mips::ANDI16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
    3895             :   }
    3896           0 :   if ((Subtarget->inMicroMipsMode())) {
    3897           0 :     return fastEmitInst_ri(Mips::ANDI16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
    3898             :   }
    3899             :   return 0;
    3900             : }
    3901             : 
    3902             : unsigned fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3903           0 :   switch (VT.SimpleTy) {
    3904           0 :   case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(RetVT, Op0, Op0IsKill, imm1);
    3905             :   default: return 0;
    3906             :   }
    3907             : }
    3908             : 
    3909             : // Top-level FastEmit function.
    3910             : 
    3911           1 : unsigned fastEmit_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3912           1 :   switch (Opcode) {
    3913           0 :   case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(VT, RetVT, Op0, Op0IsKill, imm1);
    3914             :   default: return 0;
    3915             :   }
    3916             : }
    3917             : 
    3918             : // FastEmit functions for ISD::SHL.
    3919             : 
    3920             : unsigned fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3921           0 :   if (RetVT.SimpleTy != MVT::i32)
    3922             :     return 0;
    3923           0 :   if ((Subtarget->inMicroMipsMode())) {
    3924           0 :     return fastEmitInst_ri(Mips::SLL16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
    3925             :   }
    3926             :   return 0;
    3927             : }
    3928             : 
    3929           0 : unsigned fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3930           0 :   switch (VT.SimpleTy) {
    3931           0 :   case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, Op0IsKill, imm1);
    3932             :   default: return 0;
    3933             :   }
    3934             : }
    3935             : 
    3936             : // FastEmit functions for ISD::SRL.
    3937             : 
    3938             : unsigned fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3939           0 :   if (RetVT.SimpleTy != MVT::i32)
    3940             :     return 0;
    3941           0 :   if ((Subtarget->inMicroMipsMode())) {
    3942           0 :     return fastEmitInst_ri(Mips::SRL16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
    3943             :   }
    3944             :   return 0;
    3945             : }
    3946             : 
    3947           0 : unsigned fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3948           0 :   switch (VT.SimpleTy) {
    3949           0 :   case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, Op0IsKill, imm1);
    3950             :   default: return 0;
    3951             :   }
    3952             : }
    3953             : 
    3954             : // Top-level FastEmit function.
    3955             : 
    3956           1 : unsigned fastEmit_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3957           1 :   switch (Opcode) {
    3958           0 :   case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, Op0IsKill, imm1);
    3959           0 :   case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, Op0IsKill, imm1);
    3960             :   default: return 0;
    3961             :   }
    3962             : }
    3963             : 
    3964             : // FastEmit functions for ISD::Constant.
    3965             : 
    3966             : unsigned fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) {
    3967           7 :   if (RetVT.SimpleTy != MVT::i32)
    3968             :     return 0;
    3969           7 :   if ((Subtarget->inMips16Mode())) {
    3970           0 :     return fastEmitInst_i(Mips::LwConstant32, &Mips::CPU16RegsRegClass, imm0);
    3971             :   }
    3972             :   return 0;
    3973             : }
    3974             : 
    3975           7 : unsigned fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) {
    3976           7 :   switch (VT.SimpleTy) {
    3977           7 :   case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0);
    3978             :   default: return 0;
    3979             :   }
    3980             : }
    3981             : 
    3982             : // Top-level FastEmit function.
    3983             : 
    3984           7 : unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override {
    3985           7 :   switch (Opcode) {
    3986           7 :   case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0);
    3987             :   default: return 0;
    3988             :   }
    3989             : }
    3990             : 

Generated by: LCOV version 1.13