LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/Mips - MipsGenFastISel.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 145 1719 8.4 %
Date: 2018-02-20 03:34:22 Functions: 31 287 10.8 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* "Fast" Instruction Selector for the Mips target                            *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : 
      10             : // FastEmit Immediate Predicate functions.
      11             : static bool Predicate_immZExt5(int64_t Imm) {
      12           7 : return Imm == (Imm & 0x1f);
      13             : }
      14             : static bool Predicate_immZExt6(int64_t Imm) {
      15           7 : return Imm == (Imm & 0x3f);
      16             : }
      17             : static bool Predicate_immSExt6(int64_t Imm) {
      18             : return isInt<6>(Imm);
      19             : }
      20             : static bool Predicate_immZExt4Ptr(int64_t Imm) {
      21             : return isUInt<4>(Imm);
      22             : }
      23             : static bool Predicate_immZExt3Ptr(int64_t Imm) {
      24             : return isUInt<3>(Imm);
      25             : }
      26             : static bool Predicate_immZExt2Ptr(int64_t Imm) {
      27             : return isUInt<2>(Imm);
      28             : }
      29             : static bool Predicate_immZExt1Ptr(int64_t Imm) {
      30             : return isUInt<1>(Imm);
      31             : }
      32             : static bool Predicate_immZExt4(int64_t Imm) {
      33             : return isUInt<4>(Imm);
      34             : }
      35             : static bool Predicate_immZExt3(int64_t Imm) {
      36             : return isUInt<3>(Imm);
      37             : }
      38             : static bool Predicate_immZExt2(int64_t Imm) {
      39             : return isUInt<2>(Imm);
      40             : }
      41             : static bool Predicate_immZExt1(int64_t Imm) {
      42             : return isUInt<1>(Imm);
      43             : }
      44             : static bool Predicate_immZExt8(int64_t Imm) {
      45             : return isUInt<8>(Imm);
      46             : }
      47             : static bool Predicate_immSExtAddiur2(int64_t Imm) {
      48          13 : return Imm == 1 || Imm == -1 ||
      49           6 :                                            ((Imm % 4 == 0) &&
      50           6 :                                             Imm < 28 && Imm > 0);
      51             : }
      52             : static bool Predicate_immSExtAddius5(int64_t Imm) {
      53           7 : return Imm >= -8 && Imm <= 7;
      54             : }
      55           7 : static bool Predicate_immZExtAndi16(int64_t Imm) {
      56          13 : return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
      57           6 :             Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
      58          13 :             Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
      59             : }
      60             : static bool Predicate_immZExt2Shift(int64_t Imm) {
      61           7 : return Imm >= 1 && Imm <= 8;
      62             : }
      63             : 
      64             : 
      65             : // FastEmit functions for ISD::BITCAST.
      66             : 
      67           0 : unsigned fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      68           0 :   if (RetVT.SimpleTy != MVT::f32)
      69             :     return 0;
      70           0 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
      71           0 :     return fastEmitInst_r(Mips::MTC1_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill);
      72             :   }
      73           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
      74           0 :     return fastEmitInst_r(Mips::MTC1_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
      75             :   }
      76           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
      77           0 :     return fastEmitInst_r(Mips::MTC1, &Mips::FGR32RegClass, Op0, Op0IsKill);
      78             :   }
      79             :   return 0;
      80             : }
      81             : 
      82           0 : unsigned fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      83           0 :   if (RetVT.SimpleTy != MVT::f64)
      84             :     return 0;
      85           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
      86           0 :     return fastEmitInst_r(Mips::DMTC1, &Mips::FGR64RegClass, Op0, Op0IsKill);
      87             :   }
      88             :   return 0;
      89             : }
      90             : 
      91           0 : unsigned fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      92           0 :   if (RetVT.SimpleTy != MVT::i32)
      93             :     return 0;
      94           0 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
      95           0 :     return fastEmitInst_r(Mips::MFC1_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
      96             :   }
      97           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
      98           0 :     return fastEmitInst_r(Mips::MFC1_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
      99             :   }
     100           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
     101           0 :     return fastEmitInst_r(Mips::MFC1, &Mips::GPR32RegClass, Op0, Op0IsKill);
     102             :   }
     103             :   return 0;
     104             : }
     105             : 
     106           0 : unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     107           0 :   if (RetVT.SimpleTy != MVT::i64)
     108             :     return 0;
     109           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
     110           0 :     return fastEmitInst_r(Mips::DMFC1, &Mips::GPR64RegClass, Op0, Op0IsKill);
     111             :   }
     112             :   return 0;
     113             : }
     114             : 
     115           0 : unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     116           0 :   switch (VT.SimpleTy) {
     117           0 :   case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0, Op0IsKill);
     118           0 :   case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0, Op0IsKill);
     119           0 :   case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0, Op0IsKill);
     120           0 :   case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0, Op0IsKill);
     121             :   default: return 0;
     122             :   }
     123             : }
     124             : 
     125             : // FastEmit functions for ISD::BRIND.
     126             : 
     127           0 : unsigned fastEmit_ISD_BRIND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     128           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     129             :     return 0;
     130           0 :   if ((Subtarget->inMips16Mode())) {
     131           0 :     return fastEmitInst_r(Mips::JrcRx16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill);
     132             :   }
     133             :   if ((!Subtarget->inMips16Mode())) {
     134           0 :     return fastEmitInst_r(Mips::PseudoIndirectBranch, &Mips::GPR32RegClass, Op0, Op0IsKill);
     135             :   }
     136             :   return 0;
     137             : }
     138             : 
     139             : unsigned fastEmit_ISD_BRIND_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     140           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     141             :     return 0;
     142           0 :   if ((!Subtarget->inMips16Mode())) {
     143           0 :     return fastEmitInst_r(Mips::PseudoIndirectBranch64, &Mips::GPR64RegClass, Op0, Op0IsKill);
     144             :   }
     145             :   return 0;
     146             : }
     147             : 
     148           0 : unsigned fastEmit_ISD_BRIND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     149           0 :   switch (VT.SimpleTy) {
     150           0 :   case MVT::i32: return fastEmit_ISD_BRIND_MVT_i32_r(RetVT, Op0, Op0IsKill);
     151           0 :   case MVT::i64: return fastEmit_ISD_BRIND_MVT_i64_r(RetVT, Op0, Op0IsKill);
     152             :   default: return 0;
     153             :   }
     154             : }
     155             : 
     156             : // FastEmit functions for ISD::CTLZ.
     157             : 
     158           0 : unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     159           0 :   if (RetVT.SimpleTy != MVT::i32)
     160             :     return 0;
     161           0 :   if ((Subtarget->inMicroMipsMode())) {
     162           0 :     return fastEmitInst_r(Mips::CLZ_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
     163             :   }
     164           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding())) {
     165           0 :     return fastEmitInst_r(Mips::CLZ_R6, &Mips::GPR32RegClass, Op0, Op0IsKill);
     166             :   }
     167           0 :   if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
     168           0 :     return fastEmitInst_r(Mips::CLZ, &Mips::GPR32RegClass, Op0, Op0IsKill);
     169             :   }
     170             :   return 0;
     171             : }
     172             : 
     173           0 : unsigned fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     174           0 :   if (RetVT.SimpleTy != MVT::i64)
     175             :     return 0;
     176           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
     177           0 :     return fastEmitInst_r(Mips::DCLZ_R6, &Mips::GPR64RegClass, Op0, Op0IsKill);
     178             :   }
     179           0 :   if ((Subtarget->hasMips64()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips64r6())) {
     180           0 :     return fastEmitInst_r(Mips::DCLZ, &Mips::GPR64RegClass, Op0, Op0IsKill);
     181             :   }
     182             :   return 0;
     183             : }
     184             : 
     185           0 : unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     186           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     187             :     return 0;
     188           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     189           0 :     return fastEmitInst_r(Mips::NLZC_B, &Mips::MSA128BRegClass, Op0, Op0IsKill);
     190             :   }
     191             :   return 0;
     192             : }
     193             : 
     194           0 : unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     195           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     196             :     return 0;
     197           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     198           0 :     return fastEmitInst_r(Mips::NLZC_H, &Mips::MSA128HRegClass, Op0, Op0IsKill);
     199             :   }
     200             :   return 0;
     201             : }
     202             : 
     203           0 : unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     204           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     205             :     return 0;
     206           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     207           0 :     return fastEmitInst_r(Mips::NLZC_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     208             :   }
     209             :   return 0;
     210             : }
     211             : 
     212           0 : unsigned fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     213           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     214             :     return 0;
     215           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     216           0 :     return fastEmitInst_r(Mips::NLZC_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     217             :   }
     218             :   return 0;
     219             : }
     220             : 
     221           0 : unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     222           0 :   switch (VT.SimpleTy) {
     223           0 :   case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
     224           0 :   case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0, Op0IsKill);
     225           0 :   case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     226           0 :   case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     227           0 :   case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     228           0 :   case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     229             :   default: return 0;
     230             :   }
     231             : }
     232             : 
     233             : // FastEmit functions for ISD::CTPOP.
     234             : 
     235             : unsigned fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     236           0 :   if (RetVT.SimpleTy != MVT::i32)
     237             :     return 0;
     238           0 :   if ((Subtarget->hasCnMips())) {
     239           0 :     return fastEmitInst_r(Mips::POP, &Mips::GPR32RegClass, Op0, Op0IsKill);
     240             :   }
     241             :   return 0;
     242             : }
     243             : 
     244             : unsigned fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     245           0 :   if (RetVT.SimpleTy != MVT::i64)
     246             :     return 0;
     247           0 :   if ((Subtarget->hasCnMips())) {
     248           0 :     return fastEmitInst_r(Mips::DPOP, &Mips::GPR64RegClass, Op0, Op0IsKill);
     249             :   }
     250             :   return 0;
     251             : }
     252             : 
     253           0 : unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     254           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     255             :     return 0;
     256           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     257           0 :     return fastEmitInst_r(Mips::PCNT_B, &Mips::MSA128BRegClass, Op0, Op0IsKill);
     258             :   }
     259             :   return 0;
     260             : }
     261             : 
     262           0 : unsigned fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     263           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     264             :     return 0;
     265           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     266           0 :     return fastEmitInst_r(Mips::PCNT_H, &Mips::MSA128HRegClass, Op0, Op0IsKill);
     267             :   }
     268             :   return 0;
     269             : }
     270             : 
     271           0 : unsigned fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     272           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     273             :     return 0;
     274           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     275           0 :     return fastEmitInst_r(Mips::PCNT_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     276             :   }
     277             :   return 0;
     278             : }
     279             : 
     280           0 : unsigned fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     281           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     282             :     return 0;
     283           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     284           0 :     return fastEmitInst_r(Mips::PCNT_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     285             :   }
     286             :   return 0;
     287             : }
     288             : 
     289           0 : unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     290           0 :   switch (VT.SimpleTy) {
     291           0 :   case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0, Op0IsKill);
     292           0 :   case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0, Op0IsKill);
     293           0 :   case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     294           0 :   case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     295           0 :   case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     296           0 :   case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     297             :   default: return 0;
     298             :   }
     299             : }
     300             : 
     301             : // FastEmit functions for ISD::FABS.
     302             : 
     303           0 : unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     304           0 :   if (RetVT.SimpleTy != MVT::f32)
     305             :     return 0;
     306           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
     307           0 :     return fastEmitInst_r(Mips::FABS_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
     308             :   }
     309           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
     310           0 :     return fastEmitInst_r(Mips::FABS_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
     311             :   }
     312             :   return 0;
     313             : }
     314             : 
     315           0 : unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     316           0 :   if (RetVT.SimpleTy != MVT::f64)
     317             :     return 0;
     318           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
     319           0 :     return fastEmitInst_r(Mips::FABS_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill);
     320             :   }
     321           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
     322           0 :     return fastEmitInst_r(Mips::FABS_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     323             :   }
     324           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
     325           0 :     return fastEmitInst_r(Mips::FABS_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
     326             :   }
     327           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
     328           0 :     return fastEmitInst_r(Mips::FABS_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     329             :   }
     330             :   return 0;
     331             : }
     332             : 
     333             : unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     334           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     335             :     return 0;
     336           0 :   if ((Subtarget->hasMSA())) {
     337           0 :     return fastEmitInst_r(Mips::FABS_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     338             :   }
     339             :   return 0;
     340             : }
     341             : 
     342             : unsigned fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     343           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     344             :     return 0;
     345           0 :   if ((Subtarget->hasMSA())) {
     346           0 :     return fastEmitInst_r(Mips::FABS_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     347             :   }
     348             :   return 0;
     349             : }
     350             : 
     351           0 : unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     352           0 :   switch (VT.SimpleTy) {
     353           0 :   case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill);
     354           0 :   case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0, Op0IsKill);
     355           0 :   case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     356           0 :   case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     357             :   default: return 0;
     358             :   }
     359             : }
     360             : 
     361             : // FastEmit functions for ISD::FEXP2.
     362             : 
     363             : unsigned fastEmit_ISD_FEXP2_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     364           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     365             :     return 0;
     366           0 :   if ((Subtarget->hasMSA())) {
     367           0 :     return fastEmitInst_r(Mips::FEXP2_W_1_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     368             :   }
     369             :   return 0;
     370             : }
     371             : 
     372             : unsigned fastEmit_ISD_FEXP2_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     373           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     374             :     return 0;
     375           0 :   if ((Subtarget->hasMSA())) {
     376           0 :     return fastEmitInst_r(Mips::FEXP2_D_1_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     377             :   }
     378             :   return 0;
     379             : }
     380             : 
     381           0 : unsigned fastEmit_ISD_FEXP2_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     382           0 :   switch (VT.SimpleTy) {
     383           0 :   case MVT::v4f32: return fastEmit_ISD_FEXP2_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     384           0 :   case MVT::v2f64: return fastEmit_ISD_FEXP2_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     385             :   default: return 0;
     386             :   }
     387             : }
     388             : 
     389             : // FastEmit functions for ISD::FLOG2.
     390             : 
     391           0 : unsigned fastEmit_ISD_FLOG2_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     392           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     393             :     return 0;
     394           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     395           0 :     return fastEmitInst_r(Mips::FLOG2_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     396             :   }
     397             :   return 0;
     398             : }
     399             : 
     400           0 : unsigned fastEmit_ISD_FLOG2_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     401           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     402             :     return 0;
     403           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     404           0 :     return fastEmitInst_r(Mips::FLOG2_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     405             :   }
     406             :   return 0;
     407             : }
     408             : 
     409           0 : unsigned fastEmit_ISD_FLOG2_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     410           0 :   switch (VT.SimpleTy) {
     411           0 :   case MVT::v4f32: return fastEmit_ISD_FLOG2_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     412           0 :   case MVT::v2f64: return fastEmit_ISD_FLOG2_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     413             :   default: return 0;
     414             :   }
     415             : }
     416             : 
     417             : // FastEmit functions for ISD::FNEG.
     418             : 
     419           0 : unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     420           0 :   if (RetVT.SimpleTy != MVT::f32)
     421             :     return 0;
     422           0 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
     423           0 :     return fastEmitInst_r(Mips::FNEG_S_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill);
     424             :   }
     425           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
     426           0 :     return fastEmitInst_r(Mips::FNEG_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
     427             :   }
     428           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
     429           0 :     return fastEmitInst_r(Mips::FNEG_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
     430             :   }
     431             :   return 0;
     432             : }
     433             : 
     434           0 : unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     435           0 :   if (RetVT.SimpleTy != MVT::f64)
     436             :     return 0;
     437           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
     438           0 :     return fastEmitInst_r(Mips::FNEG_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill);
     439             :   }
     440           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
     441           0 :     return fastEmitInst_r(Mips::FNEG_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     442             :   }
     443           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
     444           0 :     return fastEmitInst_r(Mips::FNEG_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
     445             :   }
     446           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
     447           0 :     return fastEmitInst_r(Mips::FNEG_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     448             :   }
     449             :   return 0;
     450             : }
     451             : 
     452           0 : unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     453           0 :   switch (VT.SimpleTy) {
     454           0 :   case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill);
     455           0 :   case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0, Op0IsKill);
     456             :   default: return 0;
     457             :   }
     458             : }
     459             : 
     460             : // FastEmit functions for ISD::FP_EXTEND.
     461             : 
     462             : unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
     463           0 :   if ((Subtarget->hasMSA())) {
     464           0 :     return fastEmitInst_r(Mips::MSA_FP_EXTEND_W_PSEUDO, &Mips::FGR32RegClass, Op0, Op0IsKill);
     465             :   }
     466             :   return 0;
     467             : }
     468             : 
     469             : unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
     470           0 :   if ((Subtarget->hasMSA())) {
     471           0 :     return fastEmitInst_r(Mips::MSA_FP_EXTEND_D_PSEUDO, &Mips::FGR64RegClass, Op0, Op0IsKill);
     472             :   }
     473             :   return 0;
     474             : }
     475             : 
     476           0 : unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     477           0 : switch (RetVT.SimpleTy) {
     478           0 :   case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(Op0, Op0IsKill);
     479           0 :   case MVT::f64: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(Op0, Op0IsKill);
     480             :   default: return 0;
     481             : }
     482             : }
     483             : 
     484           0 : unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     485           0 :   if (RetVT.SimpleTy != MVT::f64)
     486             :     return 0;
     487           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit())) {
     488           0 :     return fastEmitInst_r(Mips::CVT_D32_S_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     489             :   }
     490           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())) {
     491           0 :     return fastEmitInst_r(Mips::CVT_D64_S_MM, &Mips::FGR64RegClass, Op0, Op0IsKill);
     492             :   }
     493           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
     494           0 :     return fastEmitInst_r(Mips::CVT_D64_S, &Mips::FGR64RegClass, Op0, Op0IsKill);
     495             :   }
     496           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
     497           0 :     return fastEmitInst_r(Mips::CVT_D32_S, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     498             :   }
     499             :   return 0;
     500             : }
     501             : 
     502           0 : unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     503           0 :   switch (VT.SimpleTy) {
     504           0 :   case MVT::f16: return fastEmit_ISD_FP_EXTEND_MVT_f16_r(RetVT, Op0, Op0IsKill);
     505           0 :   case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0, Op0IsKill);
     506             :   default: return 0;
     507             :   }
     508             : }
     509             : 
     510             : // FastEmit functions for ISD::FP_ROUND.
     511             : 
     512             : unsigned fastEmit_ISD_FP_ROUND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     513           0 :   if (RetVT.SimpleTy != MVT::f16)
     514             :     return 0;
     515           0 :   if ((Subtarget->hasMSA())) {
     516           0 :     return fastEmitInst_r(Mips::MSA_FP_ROUND_W_PSEUDO, &Mips::MSA128F16RegClass, Op0, Op0IsKill);
     517             :   }
     518             :   return 0;
     519             : }
     520             : 
     521             : unsigned fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(unsigned Op0, bool Op0IsKill) {
     522           0 :   if ((Subtarget->hasMSA())) {
     523           0 :     return fastEmitInst_r(Mips::MSA_FP_ROUND_D_PSEUDO, &Mips::MSA128F16RegClass, Op0, Op0IsKill);
     524             :   }
     525             :   return 0;
     526             : }
     527             : 
     528           0 : unsigned fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
     529           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit())) {
     530           0 :     return fastEmitInst_r(Mips::CVT_S_D32_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
     531             :   }
     532           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())) {
     533           0 :     return fastEmitInst_r(Mips::CVT_S_D64_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
     534             :   }
     535           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
     536           0 :     return fastEmitInst_r(Mips::CVT_S_D64, &Mips::FGR32RegClass, Op0, Op0IsKill);
     537             :   }
     538           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
     539           0 :     return fastEmitInst_r(Mips::CVT_S_D32, &Mips::FGR32RegClass, Op0, Op0IsKill);
     540             :   }
     541             :   return 0;
     542             : }
     543             : 
     544           0 : unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     545           0 : switch (RetVT.SimpleTy) {
     546           0 :   case MVT::f16: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(Op0, Op0IsKill);
     547           0 :   case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(Op0, Op0IsKill);
     548             :   default: return 0;
     549             : }
     550             : }
     551             : 
     552           0 : unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     553           0 :   switch (VT.SimpleTy) {
     554           0 :   case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f32_r(RetVT, Op0, Op0IsKill);
     555           0 :   case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
     556             :   default: return 0;
     557             :   }
     558             : }
     559             : 
     560             : // FastEmit functions for ISD::FP_TO_SINT.
     561             : 
     562           0 : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     563           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     564             :     return 0;
     565           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     566           0 :     return fastEmitInst_r(Mips::FTRUNC_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     567             :   }
     568             :   return 0;
     569             : }
     570             : 
     571           0 : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     572           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     573             :     return 0;
     574           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     575           0 :     return fastEmitInst_r(Mips::FTRUNC_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     576             :   }
     577             :   return 0;
     578             : }
     579             : 
     580           4 : unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     581           4 :   switch (VT.SimpleTy) {
     582           0 :   case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     583           0 :   case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     584             :   default: return 0;
     585             :   }
     586             : }
     587             : 
     588             : // FastEmit functions for ISD::FP_TO_UINT.
     589             : 
     590           0 : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     591           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     592             :     return 0;
     593           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     594           0 :     return fastEmitInst_r(Mips::FTRUNC_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     595             :   }
     596             :   return 0;
     597             : }
     598             : 
     599           0 : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     600           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     601             :     return 0;
     602           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     603           0 :     return fastEmitInst_r(Mips::FTRUNC_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     604             :   }
     605             :   return 0;
     606             : }
     607             : 
     608           0 : unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     609           0 :   switch (VT.SimpleTy) {
     610           0 :   case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     611           0 :   case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     612             :   default: return 0;
     613             :   }
     614             : }
     615             : 
     616             : // FastEmit functions for ISD::FRINT.
     617             : 
     618           0 : unsigned fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     619           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     620             :     return 0;
     621           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     622           0 :     return fastEmitInst_r(Mips::FRINT_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     623             :   }
     624             :   return 0;
     625             : }
     626             : 
     627           0 : unsigned fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     628           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     629             :     return 0;
     630           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     631           0 :     return fastEmitInst_r(Mips::FRINT_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     632             :   }
     633             :   return 0;
     634             : }
     635             : 
     636           0 : unsigned fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     637           0 :   switch (VT.SimpleTy) {
     638           0 :   case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     639           0 :   case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     640             :   default: return 0;
     641             :   }
     642             : }
     643             : 
     644             : // FastEmit functions for ISD::FSQRT.
     645             : 
     646           0 : unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     647           0 :   if (RetVT.SimpleTy != MVT::f32)
     648             :     return 0;
     649           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
     650           0 :     return fastEmitInst_r(Mips::FSQRT_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
     651             :   }
     652           0 :   if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
     653           0 :     return fastEmitInst_r(Mips::FSQRT_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
     654             :   }
     655             :   return 0;
     656             : }
     657             : 
     658           0 : unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     659           0 :   if (RetVT.SimpleTy != MVT::f64)
     660             :     return 0;
     661           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
     662           0 :     return fastEmitInst_r(Mips::FSQRT_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill);
     663             :   }
     664           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
     665           0 :     return fastEmitInst_r(Mips::FSQRT_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     666             :   }
     667           0 :   if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
     668           0 :     return fastEmitInst_r(Mips::FSQRT_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
     669             :   }
     670           0 :   if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
     671           0 :     return fastEmitInst_r(Mips::FSQRT_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     672             :   }
     673             :   return 0;
     674             : }
     675             : 
     676           0 : unsigned fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     677           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     678             :     return 0;
     679           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     680           0 :     return fastEmitInst_r(Mips::FSQRT_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     681             :   }
     682             :   return 0;
     683             : }
     684             : 
     685           0 : unsigned fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     686           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     687             :     return 0;
     688           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     689           0 :     return fastEmitInst_r(Mips::FSQRT_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     690             :   }
     691             :   return 0;
     692             : }
     693             : 
     694           0 : unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     695           0 :   switch (VT.SimpleTy) {
     696           0 :   case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill);
     697           0 :   case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0, Op0IsKill);
     698           0 :   case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     699           0 :   case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     700             :   default: return 0;
     701             :   }
     702             : }
     703             : 
     704             : // FastEmit functions for ISD::SIGN_EXTEND.
     705             : 
     706             : unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     707           0 :   if (RetVT.SimpleTy != MVT::i64)
     708             :     return 0;
     709           0 :   if ((Subtarget->hasStandardEncoding())) {
     710           0 :     return fastEmitInst_r(Mips::SLL64_32, &Mips::GPR64RegClass, Op0, Op0IsKill);
     711             :   }
     712             :   return 0;
     713             : }
     714             : 
     715           0 : unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     716           0 :   switch (VT.SimpleTy) {
     717           0 :   case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0, Op0IsKill);
     718             :   default: return 0;
     719             :   }
     720             : }
     721             : 
     722             : // FastEmit functions for ISD::SINT_TO_FP.
     723             : 
     724             : unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
     725           0 :   if ((Subtarget->hasStandardEncoding())) {
     726           0 :     return fastEmitInst_r(Mips::PseudoCVT_S_W, &Mips::FGR32RegClass, Op0, Op0IsKill);
     727             :   }
     728             :   return 0;
     729             : }
     730             : 
     731           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
     732           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
     733           0 :     return fastEmitInst_r(Mips::PseudoCVT_D64_W, &Mips::FGR64RegClass, Op0, Op0IsKill);
     734             :   }
     735           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit())) {
     736           0 :     return fastEmitInst_r(Mips::PseudoCVT_D32_W, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     737             :   }
     738             :   return 0;
     739             : }
     740             : 
     741           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     742           0 : switch (RetVT.SimpleTy) {
     743           0 :   case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0, Op0IsKill);
     744           0 :   case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0, Op0IsKill);
     745             :   default: return 0;
     746             : }
     747             : }
     748             : 
     749           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     750           0 :   if (RetVT.SimpleTy != MVT::f64)
     751             :     return 0;
     752           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
     753           0 :     return fastEmitInst_r(Mips::PseudoCVT_D64_L, &Mips::FGR64RegClass, Op0, Op0IsKill);
     754             :   }
     755             :   return 0;
     756             : }
     757             : 
     758           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     759           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     760             :     return 0;
     761           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     762           0 :     return fastEmitInst_r(Mips::FFINT_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     763             :   }
     764             :   return 0;
     765             : }
     766             : 
     767           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     768           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     769             :     return 0;
     770           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     771           0 :     return fastEmitInst_r(Mips::FFINT_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     772             :   }
     773             :   return 0;
     774             : }
     775             : 
     776           0 : unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     777           0 :   switch (VT.SimpleTy) {
     778           0 :   case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0, Op0IsKill);
     779           0 :   case MVT::i64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_r(RetVT, Op0, Op0IsKill);
     780           0 :   case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     781           0 :   case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     782             :   default: return 0;
     783             :   }
     784             : }
     785             : 
     786             : // FastEmit functions for ISD::UINT_TO_FP.
     787             : 
     788           0 : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     789           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     790             :     return 0;
     791           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     792           0 :     return fastEmitInst_r(Mips::FFINT_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     793             :   }
     794             :   return 0;
     795             : }
     796             : 
     797           0 : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     798           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     799             :     return 0;
     800           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     801           0 :     return fastEmitInst_r(Mips::FFINT_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     802             :   }
     803             :   return 0;
     804             : }
     805             : 
     806           0 : unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     807           0 :   switch (VT.SimpleTy) {
     808           0 :   case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     809           0 :   case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     810             :   default: return 0;
     811             :   }
     812             : }
     813             : 
     814             : // FastEmit functions for MipsISD::JmpLink.
     815             : 
     816           0 : unsigned fastEmit_MipsISD_JmpLink_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     817           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     818             :     return 0;
     819           0 :   if ((Subtarget->inMicroMips32r6Mode())) {
     820           0 :     return fastEmitInst_r(Mips::JALRC16_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
     821             :   }
     822           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
     823           0 :     return fastEmitInst_r(Mips::JALR16_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
     824             :   }
     825           0 :   if ((Subtarget->inMips16Mode())) {
     826           0 :     return fastEmitInst_r(Mips::JumpLinkReg16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill);
     827             :   }
     828           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
     829           0 :     return fastEmitInst_r(Mips::JALRPseudo, &Mips::GPR32RegClass, Op0, Op0IsKill);
     830             :   }
     831             :   return 0;
     832             : }
     833             : 
     834             : unsigned fastEmit_MipsISD_JmpLink_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     835           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     836             :     return 0;
     837           0 :   if ((Subtarget->hasStandardEncoding())) {
     838           0 :     return fastEmitInst_r(Mips::JALR64Pseudo, &Mips::GPR64RegClass, Op0, Op0IsKill);
     839             :   }
     840             :   return 0;
     841             : }
     842             : 
     843           0 : unsigned fastEmit_MipsISD_JmpLink_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     844           0 :   switch (VT.SimpleTy) {
     845           0 :   case MVT::i32: return fastEmit_MipsISD_JmpLink_MVT_i32_r(RetVT, Op0, Op0IsKill);
     846           0 :   case MVT::i64: return fastEmit_MipsISD_JmpLink_MVT_i64_r(RetVT, Op0, Op0IsKill);
     847             :   default: return 0;
     848             :   }
     849             : }
     850             : 
     851             : // FastEmit functions for MipsISD::MFHI.
     852             : 
     853           0 : unsigned fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(unsigned Op0, bool Op0IsKill) {
     854           0 :   if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
     855           0 :     return fastEmitInst_r(Mips::MFHI_DSP_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
     856             :   }
     857           0 :   if ((Subtarget->hasDSP())) {
     858           0 :     return fastEmitInst_r(Mips::MFHI_DSP, &Mips::GPR32RegClass, Op0, Op0IsKill);
     859             :   }
     860           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
     861           0 :     return fastEmitInst_r(Mips::PseudoMFHI, &Mips::GPR32RegClass, Op0, Op0IsKill);
     862             :   }
     863             :   return 0;
     864             : }
     865             : 
     866           0 : unsigned fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(unsigned Op0, bool Op0IsKill) {
     867           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
     868           0 :     return fastEmitInst_r(Mips::PseudoMFHI64, &Mips::GPR64RegClass, Op0, Op0IsKill);
     869             :   }
     870             :   return 0;
     871             : }
     872             : 
     873           0 : unsigned fastEmit_MipsISD_MFHI_MVT_Untyped_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     874           0 : switch (RetVT.SimpleTy) {
     875           0 :   case MVT::i32: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(Op0, Op0IsKill);
     876           0 :   case MVT::i64: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(Op0, Op0IsKill);
     877             :   default: return 0;
     878             : }
     879             : }
     880             : 
     881             : unsigned fastEmit_MipsISD_MFHI_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     882           0 :   switch (VT.SimpleTy) {
     883           0 :   case MVT::Untyped: return fastEmit_MipsISD_MFHI_MVT_Untyped_r(RetVT, Op0, Op0IsKill);
     884             :   default: return 0;
     885             :   }
     886             : }
     887             : 
     888             : // FastEmit functions for MipsISD::MFLO.
     889             : 
     890           0 : unsigned fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(unsigned Op0, bool Op0IsKill) {
     891           0 :   if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
     892           0 :     return fastEmitInst_r(Mips::MFLO_DSP_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
     893             :   }
     894           0 :   if ((Subtarget->hasDSP())) {
     895           0 :     return fastEmitInst_r(Mips::MFLO_DSP, &Mips::GPR32RegClass, Op0, Op0IsKill);
     896             :   }
     897           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
     898           0 :     return fastEmitInst_r(Mips::PseudoMFLO, &Mips::GPR32RegClass, Op0, Op0IsKill);
     899             :   }
     900             :   return 0;
     901             : }
     902             : 
     903           0 : unsigned fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(unsigned Op0, bool Op0IsKill) {
     904           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
     905           0 :     return fastEmitInst_r(Mips::PseudoMFLO64, &Mips::GPR64RegClass, Op0, Op0IsKill);
     906             :   }
     907             :   return 0;
     908             : }
     909             : 
     910           0 : unsigned fastEmit_MipsISD_MFLO_MVT_Untyped_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     911           0 : switch (RetVT.SimpleTy) {
     912           0 :   case MVT::i32: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(Op0, Op0IsKill);
     913           0 :   case MVT::i64: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(Op0, Op0IsKill);
     914             :   default: return 0;
     915             : }
     916             : }
     917             : 
     918             : unsigned fastEmit_MipsISD_MFLO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     919           0 :   switch (VT.SimpleTy) {
     920           0 :   case MVT::Untyped: return fastEmit_MipsISD_MFLO_MVT_Untyped_r(RetVT, Op0, Op0IsKill);
     921             :   default: return 0;
     922             :   }
     923             : }
     924             : 
     925             : // FastEmit functions for MipsISD::MTC1_D64.
     926             : 
     927           0 : unsigned fastEmit_MipsISD_MTC1_D64_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     928           0 :   if (RetVT.SimpleTy != MVT::f64)
     929             :     return 0;
     930           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
     931           0 :     return fastEmitInst_r(Mips::MTC1_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
     932             :   }
     933             :   return 0;
     934             : }
     935             : 
     936             : unsigned fastEmit_MipsISD_MTC1_D64_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     937           0 :   switch (VT.SimpleTy) {
     938           0 :   case MVT::i32: return fastEmit_MipsISD_MTC1_D64_MVT_i32_r(RetVT, Op0, Op0IsKill);
     939             :   default: return 0;
     940             :   }
     941             : }
     942             : 
     943             : // FastEmit functions for MipsISD::TailCall.
     944             : 
     945             : unsigned fastEmit_MipsISD_TailCall_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     946           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     947             :     return 0;
     948           0 :   if ((Subtarget->hasStandardEncoding())) {
     949           0 :     return fastEmitInst_r(Mips::TAILCALLREG, &Mips::GPR32RegClass, Op0, Op0IsKill);
     950             :   }
     951             :   return 0;
     952             : }
     953             : 
     954             : unsigned fastEmit_MipsISD_TailCall_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     955           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     956             :     return 0;
     957           0 :   if ((Subtarget->hasStandardEncoding())) {
     958           0 :     return fastEmitInst_r(Mips::TAILCALLREG64, &Mips::GPR64RegClass, Op0, Op0IsKill);
     959             :   }
     960             :   return 0;
     961             : }
     962             : 
     963           0 : unsigned fastEmit_MipsISD_TailCall_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     964           0 :   switch (VT.SimpleTy) {
     965           0 :   case MVT::i32: return fastEmit_MipsISD_TailCall_MVT_i32_r(RetVT, Op0, Op0IsKill);
     966           0 :   case MVT::i64: return fastEmit_MipsISD_TailCall_MVT_i64_r(RetVT, Op0, Op0IsKill);
     967             :   default: return 0;
     968             :   }
     969             : }
     970             : 
     971             : // FastEmit functions for MipsISD::TruncIntFP.
     972             : 
     973             : unsigned fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
     974           0 :   if ((Subtarget->hasStandardEncoding())) {
     975           0 :     return fastEmitInst_r(Mips::TRUNC_W_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
     976             :   }
     977             :   return 0;
     978             : }
     979             : 
     980           0 : unsigned fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
     981           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
     982           0 :     return fastEmitInst_r(Mips::TRUNC_L_S, &Mips::FGR64RegClass, Op0, Op0IsKill);
     983             :   }
     984             :   return 0;
     985             : }
     986             : 
     987           0 : unsigned fastEmit_MipsISD_TruncIntFP_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     988           0 : switch (RetVT.SimpleTy) {
     989           0 :   case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(Op0, Op0IsKill);
     990           0 :   case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(Op0, Op0IsKill);
     991             :   default: return 0;
     992             : }
     993             : }
     994             : 
     995           0 : unsigned fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
     996           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
     997           0 :     return fastEmitInst_r(Mips::TRUNC_W_D64, &Mips::FGR32RegClass, Op0, Op0IsKill);
     998             :   }
     999           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit())) {
    1000           0 :     return fastEmitInst_r(Mips::TRUNC_W_D32, &Mips::FGR32RegClass, Op0, Op0IsKill);
    1001             :   }
    1002             :   return 0;
    1003             : }
    1004             : 
    1005           0 : unsigned fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
    1006           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
    1007           0 :     return fastEmitInst_r(Mips::TRUNC_L_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
    1008             :   }
    1009             :   return 0;
    1010             : }
    1011             : 
    1012           0 : unsigned fastEmit_MipsISD_TruncIntFP_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1013           0 : switch (RetVT.SimpleTy) {
    1014           0 :   case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(Op0, Op0IsKill);
    1015           0 :   case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(Op0, Op0IsKill);
    1016             :   default: return 0;
    1017             : }
    1018             : }
    1019             : 
    1020           0 : unsigned fastEmit_MipsISD_TruncIntFP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1021           0 :   switch (VT.SimpleTy) {
    1022           0 :   case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1023           0 :   case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1024             :   default: return 0;
    1025             :   }
    1026             : }
    1027             : 
    1028             : // FastEmit functions for MipsISD::VALL_NONZERO.
    1029             : 
    1030             : unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1031           0 :   if (RetVT.SimpleTy != MVT::i32)
    1032             :     return 0;
    1033           0 :   return fastEmitInst_r(Mips::SNZ_B_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1034             : }
    1035             : 
    1036             : unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1037           0 :   if (RetVT.SimpleTy != MVT::i32)
    1038             :     return 0;
    1039           0 :   return fastEmitInst_r(Mips::SNZ_H_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1040             : }
    1041             : 
    1042             : unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1043           0 :   if (RetVT.SimpleTy != MVT::i32)
    1044             :     return 0;
    1045           0 :   return fastEmitInst_r(Mips::SNZ_W_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1046             : }
    1047             : 
    1048             : unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1049           0 :   if (RetVT.SimpleTy != MVT::i32)
    1050             :     return 0;
    1051           0 :   return fastEmitInst_r(Mips::SNZ_D_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1052             : }
    1053             : 
    1054           0 : unsigned fastEmit_MipsISD_VALL_NONZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1055           0 :   switch (VT.SimpleTy) {
    1056           0 :   case MVT::v16i8: return fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1057           0 :   case MVT::v8i16: return fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    1058           0 :   case MVT::v4i32: return fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    1059           0 :   case MVT::v2i64: return fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
    1060             :   default: return 0;
    1061             :   }
    1062             : }
    1063             : 
    1064             : // FastEmit functions for MipsISD::VALL_ZERO.
    1065             : 
    1066             : unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1067           0 :   if (RetVT.SimpleTy != MVT::i32)
    1068             :     return 0;
    1069           0 :   return fastEmitInst_r(Mips::SZ_B_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1070             : }
    1071             : 
    1072             : unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1073           0 :   if (RetVT.SimpleTy != MVT::i32)
    1074             :     return 0;
    1075           0 :   return fastEmitInst_r(Mips::SZ_H_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1076             : }
    1077             : 
    1078             : unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1079           0 :   if (RetVT.SimpleTy != MVT::i32)
    1080             :     return 0;
    1081           0 :   return fastEmitInst_r(Mips::SZ_W_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1082             : }
    1083             : 
    1084             : unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1085           0 :   if (RetVT.SimpleTy != MVT::i32)
    1086             :     return 0;
    1087           0 :   return fastEmitInst_r(Mips::SZ_D_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1088             : }
    1089             : 
    1090           0 : unsigned fastEmit_MipsISD_VALL_ZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1091           0 :   switch (VT.SimpleTy) {
    1092           0 :   case MVT::v16i8: return fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1093           0 :   case MVT::v8i16: return fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    1094           0 :   case MVT::v4i32: return fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    1095           0 :   case MVT::v2i64: return fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
    1096             :   default: return 0;
    1097             :   }
    1098             : }
    1099             : 
    1100             : // FastEmit functions for MipsISD::VANY_NONZERO.
    1101             : 
    1102             : unsigned fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1103           0 :   if (RetVT.SimpleTy != MVT::i32)
    1104             :     return 0;
    1105           0 :   return fastEmitInst_r(Mips::SNZ_V_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1106             : }
    1107             : 
    1108             : unsigned fastEmit_MipsISD_VANY_NONZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1109           0 :   switch (VT.SimpleTy) {
    1110           0 :   case MVT::v16i8: return fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1111             :   default: return 0;
    1112             :   }
    1113             : }
    1114             : 
    1115             : // FastEmit functions for MipsISD::VANY_ZERO.
    1116             : 
    1117             : unsigned fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1118           0 :   if (RetVT.SimpleTy != MVT::i32)
    1119             :     return 0;
    1120           0 :   return fastEmitInst_r(Mips::SZ_V_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1121             : }
    1122             : 
    1123             : unsigned fastEmit_MipsISD_VANY_ZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1124           0 :   switch (VT.SimpleTy) {
    1125           0 :   case MVT::v16i8: return fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1126             :   default: return 0;
    1127             :   }
    1128             : }
    1129             : 
    1130             : // Top-level FastEmit function.
    1131             : 
    1132           4 : unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill) override {
    1133           4 :   switch (Opcode) {
    1134           0 :   case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0, Op0IsKill);
    1135           0 :   case ISD::BRIND: return fastEmit_ISD_BRIND_r(VT, RetVT, Op0, Op0IsKill);
    1136           0 :   case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill);
    1137           0 :   case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill);
    1138           0 :   case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill);
    1139           0 :   case ISD::FEXP2: return fastEmit_ISD_FEXP2_r(VT, RetVT, Op0, Op0IsKill);
    1140           0 :   case ISD::FLOG2: return fastEmit_ISD_FLOG2_r(VT, RetVT, Op0, Op0IsKill);
    1141           0 :   case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill);
    1142           0 :   case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
    1143           0 :   case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill);
    1144           4 :   case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill);
    1145           0 :   case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill);
    1146           0 :   case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0, Op0IsKill);
    1147           0 :   case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill);
    1148           0 :   case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
    1149           0 :   case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill);
    1150           0 :   case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill);
    1151           0 :   case MipsISD::JmpLink: return fastEmit_MipsISD_JmpLink_r(VT, RetVT, Op0, Op0IsKill);
    1152           0 :   case MipsISD::MFHI: return fastEmit_MipsISD_MFHI_r(VT, RetVT, Op0, Op0IsKill);
    1153           0 :   case MipsISD::MFLO: return fastEmit_MipsISD_MFLO_r(VT, RetVT, Op0, Op0IsKill);
    1154           0 :   case MipsISD::MTC1_D64: return fastEmit_MipsISD_MTC1_D64_r(VT, RetVT, Op0, Op0IsKill);
    1155           0 :   case MipsISD::TailCall: return fastEmit_MipsISD_TailCall_r(VT, RetVT, Op0, Op0IsKill);
    1156           0 :   case MipsISD::TruncIntFP: return fastEmit_MipsISD_TruncIntFP_r(VT, RetVT, Op0, Op0IsKill);
    1157           0 :   case MipsISD::VALL_NONZERO: return fastEmit_MipsISD_VALL_NONZERO_r(VT, RetVT, Op0, Op0IsKill);
    1158           0 :   case MipsISD::VALL_ZERO: return fastEmit_MipsISD_VALL_ZERO_r(VT, RetVT, Op0, Op0IsKill);
    1159           0 :   case MipsISD::VANY_NONZERO: return fastEmit_MipsISD_VANY_NONZERO_r(VT, RetVT, Op0, Op0IsKill);
    1160           0 :   case MipsISD::VANY_ZERO: return fastEmit_MipsISD_VANY_ZERO_r(VT, RetVT, Op0, Op0IsKill);
    1161             :   default: return 0;
    1162             :   }
    1163             : }
    1164             : 
    1165             : // FastEmit functions for ISD::ADD.
    1166             : 
    1167           6 : unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1168           6 :   if (RetVT.SimpleTy != MVT::i32)
    1169             :     return 0;
    1170           6 :   if ((Subtarget->inMicroMips32r6Mode())) {
    1171           0 :     return fastEmitInst_rr(Mips::ADDU16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1172             :   }
    1173           6 :   if ((Subtarget->inMips16Mode())) {
    1174           0 :     return fastEmitInst_rr(Mips::AdduRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1175             :   }
    1176           6 :   if ((Subtarget->inMicroMipsMode())) {
    1177           0 :     return fastEmitInst_rr(Mips::ADDu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1178             :   }
    1179             :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
    1180             :     return fastEmitInst_rr(Mips::ADDU16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1181             :   }
    1182             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1183          12 :     return fastEmitInst_rr(Mips::ADDu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1184             :   }
    1185             :   return 0;
    1186             : }
    1187             : 
    1188           0 : unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1189           0 :   if (RetVT.SimpleTy != MVT::i64)
    1190             :     return 0;
    1191           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1192           0 :     return fastEmitInst_rr(Mips::DADDu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1193             :   }
    1194             :   return 0;
    1195             : }
    1196             : 
    1197             : unsigned fastEmit_ISD_ADD_MVT_v4i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1198           0 :   if (RetVT.SimpleTy != MVT::v4i8)
    1199             :     return 0;
    1200           0 :   if ((Subtarget->hasDSP())) {
    1201             :     return fastEmitInst_rr(Mips::ADDU_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1202             :   }
    1203             :   return 0;
    1204             : }
    1205             : 
    1206           0 : unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1207           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1208             :     return 0;
    1209           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1210           0 :     return fastEmitInst_rr(Mips::ADDV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1211             :   }
    1212             :   return 0;
    1213             : }
    1214             : 
    1215             : unsigned fastEmit_ISD_ADD_MVT_v2i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1216           0 :   if (RetVT.SimpleTy != MVT::v2i16)
    1217             :     return 0;
    1218           0 :   if ((Subtarget->hasDSP())) {
    1219             :     return fastEmitInst_rr(Mips::ADDQ_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1220             :   }
    1221             :   return 0;
    1222             : }
    1223             : 
    1224           0 : unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1225           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1226             :     return 0;
    1227           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1228           0 :     return fastEmitInst_rr(Mips::ADDV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1229             :   }
    1230             :   return 0;
    1231             : }
    1232             : 
    1233           0 : unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1234           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1235             :     return 0;
    1236           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1237           0 :     return fastEmitInst_rr(Mips::ADDV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1238             :   }
    1239             :   return 0;
    1240             : }
    1241             : 
    1242           0 : unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1243           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1244             :     return 0;
    1245           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1246           0 :     return fastEmitInst_rr(Mips::ADDV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1247             :   }
    1248             :   return 0;
    1249             : }
    1250             : 
    1251           6 : unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1252           6 :   switch (VT.SimpleTy) {
    1253           6 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1254           0 :   case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1255           0 :   case MVT::v4i8: return fastEmit_ISD_ADD_MVT_v4i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1256           0 :   case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1257           0 :   case MVT::v2i16: return fastEmit_ISD_ADD_MVT_v2i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1258           0 :   case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1259           0 :   case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1260           0 :   case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1261             :   default: return 0;
    1262             :   }
    1263             : }
    1264             : 
    1265             : // FastEmit functions for ISD::ADDC.
    1266             : 
    1267           0 : unsigned fastEmit_ISD_ADDC_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1268           0 :   if (RetVT.SimpleTy != MVT::i32)
    1269             :     return 0;
    1270           0 :   if ((Subtarget->hasDSP())) {
    1271           0 :     return fastEmitInst_rr(Mips::ADDSC, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1272             :   }
    1273           0 :   if ((Subtarget->inMips16Mode())) {
    1274           0 :     return fastEmitInst_rr(Mips::AdduRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1275             :   }
    1276             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP())) {
    1277           0 :     return fastEmitInst_rr(Mips::ADDu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1278             :   }
    1279             :   return 0;
    1280             : }
    1281             : 
    1282           0 : unsigned fastEmit_ISD_ADDC_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1283           0 :   if (RetVT.SimpleTy != MVT::i64)
    1284             :     return 0;
    1285           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->inMicroMipsMode())) {
    1286           0 :     return fastEmitInst_rr(Mips::DADDu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1287             :   }
    1288             :   return 0;
    1289             : }
    1290             : 
    1291           0 : unsigned fastEmit_ISD_ADDC_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1292           0 :   switch (VT.SimpleTy) {
    1293           0 :   case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1294           0 :   case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1295             :   default: return 0;
    1296             :   }
    1297             : }
    1298             : 
    1299             : // FastEmit functions for ISD::ADDE.
    1300             : 
    1301             : unsigned fastEmit_ISD_ADDE_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1302           0 :   if (RetVT.SimpleTy != MVT::i32)
    1303             :     return 0;
    1304           0 :   if ((Subtarget->hasDSP())) {
    1305             :     return fastEmitInst_rr(Mips::ADDWC, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1306             :   }
    1307             :   return 0;
    1308             : }
    1309             : 
    1310           0 : unsigned fastEmit_ISD_ADDE_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1311           0 :   switch (VT.SimpleTy) {
    1312           0 :   case MVT::i32: return fastEmit_ISD_ADDE_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1313             :   default: return 0;
    1314             :   }
    1315             : }
    1316             : 
    1317             : // FastEmit functions for ISD::AND.
    1318             : 
    1319           5 : unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1320           5 :   if (RetVT.SimpleTy != MVT::i32)
    1321             :     return 0;
    1322           5 :   if ((Subtarget->inMips16Mode())) {
    1323           0 :     return fastEmitInst_rr(Mips::AndRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1324             :   }
    1325             :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding())) {
    1326           0 :     return fastEmitInst_rr(Mips::AND_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1327             :   }
    1328           5 :   if ((Subtarget->inMicroMipsMode())) {
    1329           0 :     return fastEmitInst_rr(Mips::AND_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1330             :   }
    1331             :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
    1332             :     return fastEmitInst_rr(Mips::AND16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1333             :   }
    1334             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1335          10 :     return fastEmitInst_rr(Mips::AND, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1336             :   }
    1337             :   return 0;
    1338             : }
    1339             : 
    1340             : unsigned fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1341           0 :   if (RetVT.SimpleTy != MVT::i64)
    1342             :     return 0;
    1343           0 :   if ((Subtarget->hasStandardEncoding())) {
    1344             :     return fastEmitInst_rr(Mips::AND64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1345             :   }
    1346             :   return 0;
    1347             : }
    1348             : 
    1349           0 : unsigned fastEmit_ISD_AND_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1350           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1351             :     return 0;
    1352           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1353           0 :     return fastEmitInst_rr(Mips::AND_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1354             :   }
    1355             :   return 0;
    1356             : }
    1357             : 
    1358             : unsigned fastEmit_ISD_AND_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1359           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1360             :     return 0;
    1361           0 :   if ((Subtarget->hasMSA())) {
    1362             :     return fastEmitInst_rr(Mips::AND_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1363             :   }
    1364             :   return 0;
    1365             : }
    1366             : 
    1367             : unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1368           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1369             :     return 0;
    1370           0 :   if ((Subtarget->hasMSA())) {
    1371             :     return fastEmitInst_rr(Mips::AND_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1372             :   }
    1373             :   return 0;
    1374             : }
    1375             : 
    1376             : unsigned fastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1377           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1378             :     return 0;
    1379           0 :   if ((Subtarget->hasMSA())) {
    1380             :     return fastEmitInst_rr(Mips::AND_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1381             :   }
    1382             :   return 0;
    1383             : }
    1384             : 
    1385           5 : unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1386           5 :   switch (VT.SimpleTy) {
    1387           5 :   case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1388           0 :   case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1389           0 :   case MVT::v16i8: return fastEmit_ISD_AND_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1390           0 :   case MVT::v8i16: return fastEmit_ISD_AND_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1391           0 :   case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1392           0 :   case MVT::v2i64: return fastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1393             :   default: return 0;
    1394             :   }
    1395             : }
    1396             : 
    1397             : // FastEmit functions for ISD::FADD.
    1398             : 
    1399           0 : unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1400           0 :   if (RetVT.SimpleTy != MVT::f32)
    1401             :     return 0;
    1402           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
    1403           0 :     return fastEmitInst_rr(Mips::FADD_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1404             :   }
    1405           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
    1406           0 :     return fastEmitInst_rr(Mips::FADD_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1407             :   }
    1408             :   return 0;
    1409             : }
    1410             : 
    1411           0 : unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1412           0 :   if (RetVT.SimpleTy != MVT::f64)
    1413             :     return 0;
    1414           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
    1415           0 :     return fastEmitInst_rr(Mips::FADD_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1416             :   }
    1417           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
    1418           0 :     return fastEmitInst_rr(Mips::FADD_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1419             :   }
    1420           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
    1421           0 :     return fastEmitInst_rr(Mips::FADD_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1422             :   }
    1423           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
    1424           0 :     return fastEmitInst_rr(Mips::FADD_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1425             :   }
    1426             :   return 0;
    1427             : }
    1428             : 
    1429           0 : unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1430           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1431             :     return 0;
    1432           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1433           0 :     return fastEmitInst_rr(Mips::FADD_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1434             :   }
    1435             :   return 0;
    1436             : }
    1437             : 
    1438           0 : unsigned fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1439           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1440             :     return 0;
    1441           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1442           0 :     return fastEmitInst_rr(Mips::FADD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1443             :   }
    1444             :   return 0;
    1445             : }
    1446             : 
    1447           0 : unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1448           0 :   switch (VT.SimpleTy) {
    1449           0 :   case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1450           0 :   case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1451           0 :   case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1452           0 :   case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1453             :   default: return 0;
    1454             :   }
    1455             : }
    1456             : 
    1457             : // FastEmit functions for ISD::FDIV.
    1458             : 
    1459           0 : unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1460           0 :   if (RetVT.SimpleTy != MVT::f32)
    1461             :     return 0;
    1462           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
    1463           0 :     return fastEmitInst_rr(Mips::FDIV_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1464             :   }
    1465           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
    1466           0 :     return fastEmitInst_rr(Mips::FDIV_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1467             :   }
    1468             :   return 0;
    1469             : }
    1470             : 
    1471           0 : unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1472           0 :   if (RetVT.SimpleTy != MVT::f64)
    1473             :     return 0;
    1474           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
    1475           0 :     return fastEmitInst_rr(Mips::FDIV_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1476             :   }
    1477           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
    1478           0 :     return fastEmitInst_rr(Mips::FDIV_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1479             :   }
    1480           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
    1481           0 :     return fastEmitInst_rr(Mips::FDIV_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1482             :   }
    1483           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
    1484           0 :     return fastEmitInst_rr(Mips::FDIV_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1485             :   }
    1486             :   return 0;
    1487             : }
    1488             : 
    1489           0 : unsigned fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1490           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1491             :     return 0;
    1492           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1493           0 :     return fastEmitInst_rr(Mips::FDIV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1494             :   }
    1495             :   return 0;
    1496             : }
    1497             : 
    1498           0 : unsigned fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1499           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1500             :     return 0;
    1501           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1502           0 :     return fastEmitInst_rr(Mips::FDIV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1503             :   }
    1504             :   return 0;
    1505             : }
    1506             : 
    1507           0 : unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1508           0 :   switch (VT.SimpleTy) {
    1509           0 :   case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1510           0 :   case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1511           0 :   case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1512           0 :   case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1513             :   default: return 0;
    1514             :   }
    1515             : }
    1516             : 
    1517             : // FastEmit functions for ISD::FMUL.
    1518             : 
    1519           0 : unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1520           0 :   if (RetVT.SimpleTy != MVT::f32)
    1521             :     return 0;
    1522           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
    1523           0 :     return fastEmitInst_rr(Mips::FMUL_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1524             :   }
    1525           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
    1526           0 :     return fastEmitInst_rr(Mips::FMUL_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1527             :   }
    1528             :   return 0;
    1529             : }
    1530             : 
    1531           0 : unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1532           0 :   if (RetVT.SimpleTy != MVT::f64)
    1533             :     return 0;
    1534           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
    1535           0 :     return fastEmitInst_rr(Mips::FMUL_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1536             :   }
    1537           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
    1538           0 :     return fastEmitInst_rr(Mips::FMUL_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1539             :   }
    1540           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
    1541           0 :     return fastEmitInst_rr(Mips::FMUL_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1542             :   }
    1543           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
    1544           0 :     return fastEmitInst_rr(Mips::FMUL_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1545             :   }
    1546             :   return 0;
    1547             : }
    1548             : 
    1549           0 : unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1550           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1551             :     return 0;
    1552           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1553           0 :     return fastEmitInst_rr(Mips::FMUL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1554             :   }
    1555             :   return 0;
    1556             : }
    1557             : 
    1558           0 : unsigned fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1559           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1560             :     return 0;
    1561           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1562           0 :     return fastEmitInst_rr(Mips::FMUL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1563             :   }
    1564             :   return 0;
    1565             : }
    1566             : 
    1567           0 : unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1568           0 :   switch (VT.SimpleTy) {
    1569           0 :   case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1570           0 :   case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1571           0 :   case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1572           0 :   case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1573             :   default: return 0;
    1574             :   }
    1575             : }
    1576             : 
    1577             : // FastEmit functions for ISD::FSUB.
    1578             : 
    1579           0 : unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1580           0 :   if (RetVT.SimpleTy != MVT::f32)
    1581             :     return 0;
    1582           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
    1583           0 :     return fastEmitInst_rr(Mips::FSUB_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1584             :   }
    1585           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
    1586           0 :     return fastEmitInst_rr(Mips::FSUB_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1587             :   }
    1588             :   return 0;
    1589             : }
    1590             : 
    1591           0 : unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1592           0 :   if (RetVT.SimpleTy != MVT::f64)
    1593             :     return 0;
    1594           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
    1595           0 :     return fastEmitInst_rr(Mips::FSUB_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1596             :   }
    1597           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
    1598           0 :     return fastEmitInst_rr(Mips::FSUB_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1599             :   }
    1600           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
    1601           0 :     return fastEmitInst_rr(Mips::FSUB_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1602             :   }
    1603           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
    1604           0 :     return fastEmitInst_rr(Mips::FSUB_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1605             :   }
    1606             :   return 0;
    1607             : }
    1608             : 
    1609           0 : unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1610           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1611             :     return 0;
    1612           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1613           0 :     return fastEmitInst_rr(Mips::FSUB_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1614             :   }
    1615             :   return 0;
    1616             : }
    1617             : 
    1618           0 : unsigned fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1619           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1620             :     return 0;
    1621           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1622           0 :     return fastEmitInst_rr(Mips::FSUB_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1623             :   }
    1624             :   return 0;
    1625             : }
    1626             : 
    1627           0 : unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1628           0 :   switch (VT.SimpleTy) {
    1629           0 :   case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1630           0 :   case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1631           0 :   case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1632           0 :   case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1633             :   default: return 0;
    1634             :   }
    1635             : }
    1636             : 
    1637             : // FastEmit functions for ISD::MUL.
    1638             : 
    1639           2 : unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1640           2 :   if (RetVT.SimpleTy != MVT::i32)
    1641             :     return 0;
    1642           2 :   if ((Subtarget->inMips16Mode())) {
    1643           0 :     return fastEmitInst_rr(Mips::MultRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1644             :   }
    1645             :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding())) {
    1646           0 :     return fastEmitInst_rr(Mips::MUL_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1647             :   }
    1648           2 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1649           0 :     return fastEmitInst_rr(Mips::MUL_R6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1650             :   }
    1651             :   if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    1652           2 :     return fastEmitInst_rr(Mips::MUL, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1653             :   }
    1654             :   return 0;
    1655             : }
    1656             : 
    1657           0 : unsigned fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1658           0 :   if (RetVT.SimpleTy != MVT::i64)
    1659             :     return 0;
    1660           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1661           0 :     return fastEmitInst_rr(Mips::DMUL_R6, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1662             :   }
    1663           0 :   if ((Subtarget->hasCnMips())) {
    1664           0 :     return fastEmitInst_rr(Mips::DMUL, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1665             :   }
    1666             :   return 0;
    1667             : }
    1668             : 
    1669           0 : unsigned fastEmit_ISD_MUL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1670           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1671             :     return 0;
    1672           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1673           0 :     return fastEmitInst_rr(Mips::MULV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1674             :   }
    1675             :   return 0;
    1676             : }
    1677             : 
    1678             : unsigned fastEmit_ISD_MUL_MVT_v2i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1679           0 :   if (RetVT.SimpleTy != MVT::v2i16)
    1680             :     return 0;
    1681           0 :   if ((Subtarget->hasDSPR2())) {
    1682             :     return fastEmitInst_rr(Mips::MUL_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1683             :   }
    1684             :   return 0;
    1685             : }
    1686             : 
    1687           0 : unsigned fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1688           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1689             :     return 0;
    1690           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1691           0 :     return fastEmitInst_rr(Mips::MULV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1692             :   }
    1693             :   return 0;
    1694             : }
    1695             : 
    1696           0 : unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1697           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1698             :     return 0;
    1699           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1700           0 :     return fastEmitInst_rr(Mips::MULV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1701             :   }
    1702             :   return 0;
    1703             : }
    1704             : 
    1705           0 : unsigned fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1706           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1707             :     return 0;
    1708           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1709           0 :     return fastEmitInst_rr(Mips::MULV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1710             :   }
    1711             :   return 0;
    1712             : }
    1713             : 
    1714           2 : unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1715           2 :   switch (VT.SimpleTy) {
    1716           2 :   case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1717           0 :   case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1718           0 :   case MVT::v16i8: return fastEmit_ISD_MUL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1719           0 :   case MVT::v2i16: return fastEmit_ISD_MUL_MVT_v2i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1720           0 :   case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1721           0 :   case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1722           0 :   case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1723             :   default: return 0;
    1724             :   }
    1725             : }
    1726             : 
    1727             : // FastEmit functions for ISD::MULHS.
    1728             : 
    1729           0 : unsigned fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1730           0 :   if (RetVT.SimpleTy != MVT::i32)
    1731             :     return 0;
    1732           0 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding())) {
    1733           0 :     return fastEmitInst_rr(Mips::MUH_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1734             :   }
    1735           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1736           0 :     return fastEmitInst_rr(Mips::MUH, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1737             :   }
    1738             :   return 0;
    1739             : }
    1740             : 
    1741           0 : unsigned fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1742           0 :   if (RetVT.SimpleTy != MVT::i64)
    1743             :     return 0;
    1744           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1745           0 :     return fastEmitInst_rr(Mips::DMUH, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1746             :   }
    1747             :   return 0;
    1748             : }
    1749             : 
    1750           0 : unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1751           0 :   switch (VT.SimpleTy) {
    1752           0 :   case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1753           0 :   case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1754             :   default: return 0;
    1755             :   }
    1756             : }
    1757             : 
    1758             : // FastEmit functions for ISD::MULHU.
    1759             : 
    1760           0 : unsigned fastEmit_ISD_MULHU_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1761           0 :   if (RetVT.SimpleTy != MVT::i32)
    1762             :     return 0;
    1763           0 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding())) {
    1764           0 :     return fastEmitInst_rr(Mips::MUHU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1765             :   }
    1766           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1767           0 :     return fastEmitInst_rr(Mips::MUHU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1768             :   }
    1769             :   return 0;
    1770             : }
    1771             : 
    1772           0 : unsigned fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1773           0 :   if (RetVT.SimpleTy != MVT::i64)
    1774             :     return 0;
    1775           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1776           0 :     return fastEmitInst_rr(Mips::DMUHU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1777             :   }
    1778             :   return 0;
    1779             : }
    1780             : 
    1781           0 : unsigned fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1782           0 :   switch (VT.SimpleTy) {
    1783           0 :   case MVT::i32: return fastEmit_ISD_MULHU_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1784           0 :   case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1785             :   default: return 0;
    1786             :   }
    1787             : }
    1788             : 
    1789             : // FastEmit functions for ISD::OR.
    1790             : 
    1791           4 : unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1792           4 :   if (RetVT.SimpleTy != MVT::i32)
    1793             :     return 0;
    1794           4 :   if ((Subtarget->inMips16Mode())) {
    1795           0 :     return fastEmitInst_rr(Mips::OrRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1796             :   }
    1797             :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding())) {
    1798           0 :     return fastEmitInst_rr(Mips::OR_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1799             :   }
    1800           4 :   if ((Subtarget->inMicroMipsMode())) {
    1801           0 :     return fastEmitInst_rr(Mips::OR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1802             :   }
    1803             :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
    1804             :     return fastEmitInst_rr(Mips::OR16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1805             :   }
    1806             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1807           8 :     return fastEmitInst_rr(Mips::OR, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1808             :   }
    1809             :   return 0;
    1810             : }
    1811             : 
    1812             : unsigned fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1813           0 :   if (RetVT.SimpleTy != MVT::i64)
    1814             :     return 0;
    1815           0 :   if ((Subtarget->hasStandardEncoding())) {
    1816             :     return fastEmitInst_rr(Mips::OR64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1817             :   }
    1818             :   return 0;
    1819             : }
    1820             : 
    1821           0 : unsigned fastEmit_ISD_OR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1822           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1823             :     return 0;
    1824           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1825           0 :     return fastEmitInst_rr(Mips::OR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1826             :   }
    1827             :   return 0;
    1828             : }
    1829             : 
    1830             : unsigned fastEmit_ISD_OR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1831           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1832             :     return 0;
    1833           0 :   if ((Subtarget->hasMSA())) {
    1834             :     return fastEmitInst_rr(Mips::OR_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1835             :   }
    1836             :   return 0;
    1837             : }
    1838             : 
    1839             : unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1840           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1841             :     return 0;
    1842           0 :   if ((Subtarget->hasMSA())) {
    1843             :     return fastEmitInst_rr(Mips::OR_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1844             :   }
    1845             :   return 0;
    1846             : }
    1847             : 
    1848             : unsigned fastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1849           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1850             :     return 0;
    1851           0 :   if ((Subtarget->hasMSA())) {
    1852             :     return fastEmitInst_rr(Mips::OR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1853             :   }
    1854             :   return 0;
    1855             : }
    1856             : 
    1857           4 : unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1858           4 :   switch (VT.SimpleTy) {
    1859           4 :   case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1860           0 :   case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1861           0 :   case MVT::v16i8: return fastEmit_ISD_OR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1862           0 :   case MVT::v8i16: return fastEmit_ISD_OR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1863           0 :   case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1864           0 :   case MVT::v2i64: return fastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1865             :   default: return 0;
    1866             :   }
    1867             : }
    1868             : 
    1869             : // FastEmit functions for ISD::ROTR.
    1870             : 
    1871           0 : unsigned fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1872           0 :   if (RetVT.SimpleTy != MVT::i32)
    1873             :     return 0;
    1874           0 :   if ((Subtarget->inMicroMipsMode())) {
    1875           0 :     return fastEmitInst_rr(Mips::ROTRV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1876             :   }
    1877           0 :   if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1878           0 :     return fastEmitInst_rr(Mips::ROTRV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1879             :   }
    1880             :   return 0;
    1881             : }
    1882             : 
    1883             : unsigned fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1884           0 :   switch (VT.SimpleTy) {
    1885           0 :   case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1886             :   default: return 0;
    1887             :   }
    1888             : }
    1889             : 
    1890             : // FastEmit functions for ISD::SDIV.
    1891             : 
    1892           4 : unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1893           4 :   if (RetVT.SimpleTy != MVT::i32)
    1894             :     return 0;
    1895           4 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding())) {
    1896           0 :     return fastEmitInst_rr(Mips::DIV_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1897             :   }
    1898           4 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1899           0 :     return fastEmitInst_rr(Mips::DIV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1900             :   }
    1901             :   return 0;
    1902             : }
    1903             : 
    1904           0 : unsigned fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1905           0 :   if (RetVT.SimpleTy != MVT::i64)
    1906             :     return 0;
    1907           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1908           0 :     return fastEmitInst_rr(Mips::DDIV, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1909             :   }
    1910             :   return 0;
    1911             : }
    1912             : 
    1913           0 : unsigned fastEmit_ISD_SDIV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1914           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1915             :     return 0;
    1916           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1917           0 :     return fastEmitInst_rr(Mips::DIV_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1918             :   }
    1919             :   return 0;
    1920             : }
    1921             : 
    1922           0 : unsigned fastEmit_ISD_SDIV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1923           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1924             :     return 0;
    1925           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1926           0 :     return fastEmitInst_rr(Mips::DIV_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1927             :   }
    1928             :   return 0;
    1929             : }
    1930             : 
    1931           0 : unsigned fastEmit_ISD_SDIV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1932           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1933             :     return 0;
    1934           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1935           0 :     return fastEmitInst_rr(Mips::DIV_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1936             :   }
    1937             :   return 0;
    1938             : }
    1939             : 
    1940           0 : unsigned fastEmit_ISD_SDIV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1941           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1942             :     return 0;
    1943           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1944           0 :     return fastEmitInst_rr(Mips::DIV_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1945             :   }
    1946             :   return 0;
    1947             : }
    1948             : 
    1949           4 : unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1950           4 :   switch (VT.SimpleTy) {
    1951           4 :   case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1952           0 :   case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1953           0 :   case MVT::v16i8: return fastEmit_ISD_SDIV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1954           0 :   case MVT::v8i16: return fastEmit_ISD_SDIV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1955           0 :   case MVT::v4i32: return fastEmit_ISD_SDIV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1956           0 :   case MVT::v2i64: return fastEmit_ISD_SDIV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1957             :   default: return 0;
    1958             :   }
    1959             : }
    1960             : 
    1961             : // FastEmit functions for ISD::SHL.
    1962             : 
    1963           0 : unsigned fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1964           0 :   if (RetVT.SimpleTy != MVT::i32)
    1965             :     return 0;
    1966           0 :   if ((Subtarget->inMicroMipsMode())) {
    1967           0 :     return fastEmitInst_rr(Mips::SLLV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1968             :   }
    1969           0 :   if ((Subtarget->inMips16Mode())) {
    1970           0 :     return fastEmitInst_rr(Mips::SllvRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1971             :   }
    1972             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1973           0 :     return fastEmitInst_rr(Mips::SLLV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1974             :   }
    1975             :   return 0;
    1976             : }
    1977             : 
    1978           0 : unsigned fastEmit_ISD_SHL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1979           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1980             :     return 0;
    1981           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1982           0 :     return fastEmitInst_rr(Mips::SLL_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1983             :   }
    1984             :   return 0;
    1985             : }
    1986             : 
    1987           0 : unsigned fastEmit_ISD_SHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1988           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1989             :     return 0;
    1990           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1991           0 :     return fastEmitInst_rr(Mips::SLL_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1992             :   }
    1993             :   return 0;
    1994             : }
    1995             : 
    1996           0 : unsigned fastEmit_ISD_SHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1997           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1998             :     return 0;
    1999           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2000           0 :     return fastEmitInst_rr(Mips::SLL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2001             :   }
    2002             :   return 0;
    2003             : }
    2004             : 
    2005           0 : unsigned fastEmit_ISD_SHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2006           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2007             :     return 0;
    2008           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2009           0 :     return fastEmitInst_rr(Mips::SLL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2010             :   }
    2011             :   return 0;
    2012             : }
    2013             : 
    2014           0 : unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2015           0 :   switch (VT.SimpleTy) {
    2016           0 :   case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2017           0 :   case MVT::v16i8: return fastEmit_ISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2018           0 :   case MVT::v8i16: return fastEmit_ISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2019           0 :   case MVT::v4i32: return fastEmit_ISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2020           0 :   case MVT::v2i64: return fastEmit_ISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2021             :   default: return 0;
    2022             :   }
    2023             : }
    2024             : 
    2025             : // FastEmit functions for ISD::SMAX.
    2026             : 
    2027           0 : unsigned fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2028           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2029             :     return 0;
    2030           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2031           0 :     return fastEmitInst_rr(Mips::MAX_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2032             :   }
    2033             :   return 0;
    2034             : }
    2035             : 
    2036           0 : unsigned fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2037           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2038             :     return 0;
    2039           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2040           0 :     return fastEmitInst_rr(Mips::MAX_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2041             :   }
    2042             :   return 0;
    2043             : }
    2044             : 
    2045           0 : unsigned fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2046           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2047             :     return 0;
    2048           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2049           0 :     return fastEmitInst_rr(Mips::MAX_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2050             :   }
    2051             :   return 0;
    2052             : }
    2053             : 
    2054           0 : unsigned fastEmit_ISD_SMAX_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2055           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2056             :     return 0;
    2057           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2058           0 :     return fastEmitInst_rr(Mips::MAX_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2059             :   }
    2060             :   return 0;
    2061             : }
    2062             : 
    2063           0 : unsigned fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2064           0 :   switch (VT.SimpleTy) {
    2065           0 :   case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2066           0 :   case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2067           0 :   case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2068           0 :   case MVT::v2i64: return fastEmit_ISD_SMAX_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2069             :   default: return 0;
    2070             :   }
    2071             : }
    2072             : 
    2073             : // FastEmit functions for ISD::SMIN.
    2074             : 
    2075           0 : unsigned fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2076           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2077             :     return 0;
    2078           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2079           0 :     return fastEmitInst_rr(Mips::MIN_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2080             :   }
    2081             :   return 0;
    2082             : }
    2083             : 
    2084           0 : unsigned fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2085           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2086             :     return 0;
    2087           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2088           0 :     return fastEmitInst_rr(Mips::MIN_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2089             :   }
    2090             :   return 0;
    2091             : }
    2092             : 
    2093           0 : unsigned fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2094           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2095             :     return 0;
    2096           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2097           0 :     return fastEmitInst_rr(Mips::MIN_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2098             :   }
    2099             :   return 0;
    2100             : }
    2101             : 
    2102           0 : unsigned fastEmit_ISD_SMIN_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2103           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2104             :     return 0;
    2105           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2106           0 :     return fastEmitInst_rr(Mips::MIN_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2107             :   }
    2108             :   return 0;
    2109             : }
    2110             : 
    2111           0 : unsigned fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2112           0 :   switch (VT.SimpleTy) {
    2113           0 :   case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2114           0 :   case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2115           0 :   case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2116           0 :   case MVT::v2i64: return fastEmit_ISD_SMIN_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2117             :   default: return 0;
    2118             :   }
    2119             : }
    2120             : 
    2121             : // FastEmit functions for ISD::SRA.
    2122             : 
    2123           0 : unsigned fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2124           0 :   if (RetVT.SimpleTy != MVT::i32)
    2125             :     return 0;
    2126           0 :   if ((Subtarget->inMicroMipsMode())) {
    2127           0 :     return fastEmitInst_rr(Mips::SRAV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2128             :   }
    2129           0 :   if ((Subtarget->inMips16Mode())) {
    2130           0 :     return fastEmitInst_rr(Mips::SravRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2131             :   }
    2132             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2133           0 :     return fastEmitInst_rr(Mips::SRAV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2134             :   }
    2135             :   return 0;
    2136             : }
    2137             : 
    2138           0 : unsigned fastEmit_ISD_SRA_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2139           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2140             :     return 0;
    2141           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2142           0 :     return fastEmitInst_rr(Mips::SRA_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2143             :   }
    2144             :   return 0;
    2145             : }
    2146             : 
    2147           0 : unsigned fastEmit_ISD_SRA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2148           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2149             :     return 0;
    2150           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2151           0 :     return fastEmitInst_rr(Mips::SRA_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2152             :   }
    2153             :   return 0;
    2154             : }
    2155             : 
    2156           0 : unsigned fastEmit_ISD_SRA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2157           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2158             :     return 0;
    2159           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2160           0 :     return fastEmitInst_rr(Mips::SRA_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2161             :   }
    2162             :   return 0;
    2163             : }
    2164             : 
    2165           0 : unsigned fastEmit_ISD_SRA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2166           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2167             :     return 0;
    2168           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2169           0 :     return fastEmitInst_rr(Mips::SRA_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2170             :   }
    2171             :   return 0;
    2172             : }
    2173             : 
    2174           0 : unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2175           0 :   switch (VT.SimpleTy) {
    2176           0 :   case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2177           0 :   case MVT::v16i8: return fastEmit_ISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2178           0 :   case MVT::v8i16: return fastEmit_ISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2179           0 :   case MVT::v4i32: return fastEmit_ISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2180           0 :   case MVT::v2i64: return fastEmit_ISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2181             :   default: return 0;
    2182             :   }
    2183             : }
    2184             : 
    2185             : // FastEmit functions for ISD::SREM.
    2186             : 
    2187           4 : unsigned fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2188           4 :   if (RetVT.SimpleTy != MVT::i32)
    2189             :     return 0;
    2190           4 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding())) {
    2191           0 :     return fastEmitInst_rr(Mips::MOD_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2192             :   }
    2193           4 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2194           0 :     return fastEmitInst_rr(Mips::MOD, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2195             :   }
    2196             :   return 0;
    2197             : }
    2198             : 
    2199           0 : unsigned fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2200           0 :   if (RetVT.SimpleTy != MVT::i64)
    2201             :     return 0;
    2202           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2203           0 :     return fastEmitInst_rr(Mips::DMOD, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2204             :   }
    2205             :   return 0;
    2206             : }
    2207             : 
    2208           0 : unsigned fastEmit_ISD_SREM_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2209           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2210             :     return 0;
    2211           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2212           0 :     return fastEmitInst_rr(Mips::MOD_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2213             :   }
    2214             :   return 0;
    2215             : }
    2216             : 
    2217           0 : unsigned fastEmit_ISD_SREM_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2218           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2219             :     return 0;
    2220           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2221           0 :     return fastEmitInst_rr(Mips::MOD_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2222             :   }
    2223             :   return 0;
    2224             : }
    2225             : 
    2226           0 : unsigned fastEmit_ISD_SREM_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2227           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2228             :     return 0;
    2229           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2230           0 :     return fastEmitInst_rr(Mips::MOD_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2231             :   }
    2232             :   return 0;
    2233             : }
    2234             : 
    2235           0 : unsigned fastEmit_ISD_SREM_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2236           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2237             :     return 0;
    2238           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2239           0 :     return fastEmitInst_rr(Mips::MOD_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2240             :   }
    2241             :   return 0;
    2242             : }
    2243             : 
    2244           4 : unsigned fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2245           4 :   switch (VT.SimpleTy) {
    2246           4 :   case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2247           0 :   case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2248           0 :   case MVT::v16i8: return fastEmit_ISD_SREM_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2249           0 :   case MVT::v8i16: return fastEmit_ISD_SREM_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2250           0 :   case MVT::v4i32: return fastEmit_ISD_SREM_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2251           0 :   case MVT::v2i64: return fastEmit_ISD_SREM_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2252             :   default: return 0;
    2253             :   }
    2254             : }
    2255             : 
    2256             : // FastEmit functions for ISD::SRL.
    2257             : 
    2258           0 : unsigned fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2259           0 :   if (RetVT.SimpleTy != MVT::i32)
    2260             :     return 0;
    2261           0 :   if ((Subtarget->inMicroMipsMode())) {
    2262           0 :     return fastEmitInst_rr(Mips::SRLV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2263             :   }
    2264           0 :   if ((Subtarget->inMips16Mode())) {
    2265           0 :     return fastEmitInst_rr(Mips::SrlvRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2266             :   }
    2267             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2268           0 :     return fastEmitInst_rr(Mips::SRLV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2269             :   }
    2270             :   return 0;
    2271             : }
    2272             : 
    2273           0 : unsigned fastEmit_ISD_SRL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2274           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2275             :     return 0;
    2276           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2277           0 :     return fastEmitInst_rr(Mips::SRL_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2278             :   }
    2279             :   return 0;
    2280             : }
    2281             : 
    2282           0 : unsigned fastEmit_ISD_SRL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2283           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2284             :     return 0;
    2285           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2286           0 :     return fastEmitInst_rr(Mips::SRL_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2287             :   }
    2288             :   return 0;
    2289             : }
    2290             : 
    2291           0 : unsigned fastEmit_ISD_SRL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2292           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2293             :     return 0;
    2294           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2295           0 :     return fastEmitInst_rr(Mips::SRL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2296             :   }
    2297             :   return 0;
    2298             : }
    2299             : 
    2300           0 : unsigned fastEmit_ISD_SRL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2301           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2302             :     return 0;
    2303           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2304           0 :     return fastEmitInst_rr(Mips::SRL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2305             :   }
    2306             :   return 0;
    2307             : }
    2308             : 
    2309           0 : unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2310           0 :   switch (VT.SimpleTy) {
    2311           0 :   case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2312           0 :   case MVT::v16i8: return fastEmit_ISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2313           0 :   case MVT::v8i16: return fastEmit_ISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2314           0 :   case MVT::v4i32: return fastEmit_ISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2315           0 :   case MVT::v2i64: return fastEmit_ISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2316             :   default: return 0;
    2317             :   }
    2318             : }
    2319             : 
    2320             : // FastEmit functions for ISD::SUB.
    2321             : 
    2322           0 : unsigned fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2323           0 :   if (RetVT.SimpleTy != MVT::i32)
    2324             :     return 0;
    2325           0 :   if ((Subtarget->inMicroMips32r6Mode())) {
    2326           0 :     return fastEmitInst_rr(Mips::SUBU16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2327             :   }
    2328           0 :   if ((Subtarget->inMips16Mode())) {
    2329           0 :     return fastEmitInst_rr(Mips::SubuRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2330             :   }
    2331           0 :   if ((Subtarget->inMicroMipsMode())) {
    2332           0 :     return fastEmitInst_rr(Mips::SUBu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2333             :   }
    2334             :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
    2335             :     return fastEmitInst_rr(Mips::SUBU16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2336             :   }
    2337             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2338           0 :     return fastEmitInst_rr(Mips::SUBu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2339             :   }
    2340             :   return 0;
    2341             : }
    2342             : 
    2343           0 : unsigned fastEmit_ISD_SUB_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2344           0 :   if (RetVT.SimpleTy != MVT::i64)
    2345             :     return 0;
    2346           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2347           0 :     return fastEmitInst_rr(Mips::DSUBu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2348             :   }
    2349             :   return 0;
    2350             : }
    2351             : 
    2352             : unsigned fastEmit_ISD_SUB_MVT_v4i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2353           0 :   if (RetVT.SimpleTy != MVT::v4i8)
    2354             :     return 0;
    2355           0 :   if ((Subtarget->hasDSP())) {
    2356             :     return fastEmitInst_rr(Mips::SUBU_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2357             :   }
    2358             :   return 0;
    2359             : }
    2360             : 
    2361           0 : unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2362           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2363             :     return 0;
    2364           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2365           0 :     return fastEmitInst_rr(Mips::SUBV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2366             :   }
    2367             :   return 0;
    2368             : }
    2369             : 
    2370             : unsigned fastEmit_ISD_SUB_MVT_v2i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2371           0 :   if (RetVT.SimpleTy != MVT::v2i16)
    2372             :     return 0;
    2373           0 :   if ((Subtarget->hasDSP())) {
    2374             :     return fastEmitInst_rr(Mips::SUBQ_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2375             :   }
    2376             :   return 0;
    2377             : }
    2378             : 
    2379           0 : unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2380           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2381             :     return 0;
    2382           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2383           0 :     return fastEmitInst_rr(Mips::SUBV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2384             :   }
    2385             :   return 0;
    2386             : }
    2387             : 
    2388           0 : unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2389           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2390             :     return 0;
    2391           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2392           0 :     return fastEmitInst_rr(Mips::SUBV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2393             :   }
    2394             :   return 0;
    2395             : }
    2396             : 
    2397           0 : unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2398           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2399             :     return 0;
    2400           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2401           0 :     return fastEmitInst_rr(Mips::SUBV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2402             :   }
    2403             :   return 0;
    2404             : }
    2405             : 
    2406           0 : unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2407           0 :   switch (VT.SimpleTy) {
    2408           0 :   case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2409           0 :   case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2410           0 :   case MVT::v4i8: return fastEmit_ISD_SUB_MVT_v4i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2411           0 :   case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2412           0 :   case MVT::v2i16: return fastEmit_ISD_SUB_MVT_v2i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2413           0 :   case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2414           0 :   case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2415           0 :   case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2416             :   default: return 0;
    2417             :   }
    2418             : }
    2419             : 
    2420             : // FastEmit functions for ISD::SUBC.
    2421             : 
    2422           0 : unsigned fastEmit_ISD_SUBC_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2423           0 :   if (RetVT.SimpleTy != MVT::i32)
    2424             :     return 0;
    2425           0 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding())) {
    2426           0 :     return fastEmitInst_rr(Mips::SUBU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2427             :   }
    2428           0 :   if ((Subtarget->inMicroMipsMode())) {
    2429           0 :     return fastEmitInst_rr(Mips::SUBu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2430             :   }
    2431           0 :   if ((Subtarget->inMips16Mode())) {
    2432           0 :     return fastEmitInst_rr(Mips::SubuRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2433             :   }
    2434             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2435           0 :     return fastEmitInst_rr(Mips::SUBu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2436             :   }
    2437             :   return 0;
    2438             : }
    2439             : 
    2440           0 : unsigned fastEmit_ISD_SUBC_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2441           0 :   if (RetVT.SimpleTy != MVT::i64)
    2442             :     return 0;
    2443           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2444           0 :     return fastEmitInst_rr(Mips::DSUBu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2445             :   }
    2446             :   return 0;
    2447             : }
    2448             : 
    2449           0 : unsigned fastEmit_ISD_SUBC_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2450           0 :   switch (VT.SimpleTy) {
    2451           0 :   case MVT::i32: return fastEmit_ISD_SUBC_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2452           0 :   case MVT::i64: return fastEmit_ISD_SUBC_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2453             :   default: return 0;
    2454             :   }
    2455             : }
    2456             : 
    2457             : // FastEmit functions for ISD::UDIV.
    2458             : 
    2459           4 : unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2460           4 :   if (RetVT.SimpleTy != MVT::i32)
    2461             :     return 0;
    2462           4 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding())) {
    2463           0 :     return fastEmitInst_rr(Mips::DIVU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2464             :   }
    2465           4 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2466           0 :     return fastEmitInst_rr(Mips::DIVU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2467             :   }
    2468             :   return 0;
    2469             : }
    2470             : 
    2471           0 : unsigned fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2472           0 :   if (RetVT.SimpleTy != MVT::i64)
    2473             :     return 0;
    2474           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2475           0 :     return fastEmitInst_rr(Mips::DDIVU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2476             :   }
    2477             :   return 0;
    2478             : }
    2479             : 
    2480           0 : unsigned fastEmit_ISD_UDIV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2481           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2482             :     return 0;
    2483           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2484           0 :     return fastEmitInst_rr(Mips::DIV_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2485             :   }
    2486             :   return 0;
    2487             : }
    2488             : 
    2489           0 : unsigned fastEmit_ISD_UDIV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2490           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2491             :     return 0;
    2492           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2493           0 :     return fastEmitInst_rr(Mips::DIV_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2494             :   }
    2495             :   return 0;
    2496             : }
    2497             : 
    2498           0 : unsigned fastEmit_ISD_UDIV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2499           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2500             :     return 0;
    2501           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2502           0 :     return fastEmitInst_rr(Mips::DIV_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2503             :   }
    2504             :   return 0;
    2505             : }
    2506             : 
    2507           0 : unsigned fastEmit_ISD_UDIV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2508           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2509             :     return 0;
    2510           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2511           0 :     return fastEmitInst_rr(Mips::DIV_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2512             :   }
    2513             :   return 0;
    2514             : }
    2515             : 
    2516           4 : unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2517           4 :   switch (VT.SimpleTy) {
    2518           4 :   case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2519           0 :   case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2520           0 :   case MVT::v16i8: return fastEmit_ISD_UDIV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2521           0 :   case MVT::v8i16: return fastEmit_ISD_UDIV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2522           0 :   case MVT::v4i32: return fastEmit_ISD_UDIV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2523           0 :   case MVT::v2i64: return fastEmit_ISD_UDIV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2524             :   default: return 0;
    2525             :   }
    2526             : }
    2527             : 
    2528             : // FastEmit functions for ISD::UMAX.
    2529             : 
    2530           0 : unsigned fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2531           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2532             :     return 0;
    2533           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2534           0 :     return fastEmitInst_rr(Mips::MAX_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2535             :   }
    2536             :   return 0;
    2537             : }
    2538             : 
    2539           0 : unsigned fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2540           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2541             :     return 0;
    2542           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2543           0 :     return fastEmitInst_rr(Mips::MAX_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2544             :   }
    2545             :   return 0;
    2546             : }
    2547             : 
    2548           0 : unsigned fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2549           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2550             :     return 0;
    2551           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2552           0 :     return fastEmitInst_rr(Mips::MAX_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2553             :   }
    2554             :   return 0;
    2555             : }
    2556             : 
    2557           0 : unsigned fastEmit_ISD_UMAX_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2558           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2559             :     return 0;
    2560           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2561           0 :     return fastEmitInst_rr(Mips::MAX_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2562             :   }
    2563             :   return 0;
    2564             : }
    2565             : 
    2566           0 : unsigned fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2567           0 :   switch (VT.SimpleTy) {
    2568           0 :   case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2569           0 :   case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2570           0 :   case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2571           0 :   case MVT::v2i64: return fastEmit_ISD_UMAX_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2572             :   default: return 0;
    2573             :   }
    2574             : }
    2575             : 
    2576             : // FastEmit functions for ISD::UMIN.
    2577             : 
    2578           0 : unsigned fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2579           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2580             :     return 0;
    2581           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2582           0 :     return fastEmitInst_rr(Mips::MIN_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2583             :   }
    2584             :   return 0;
    2585             : }
    2586             : 
    2587           0 : unsigned fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2588           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2589             :     return 0;
    2590           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2591           0 :     return fastEmitInst_rr(Mips::MIN_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2592             :   }
    2593             :   return 0;
    2594             : }
    2595             : 
    2596           0 : unsigned fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2597           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2598             :     return 0;
    2599           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2600           0 :     return fastEmitInst_rr(Mips::MIN_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2601             :   }
    2602             :   return 0;
    2603             : }
    2604             : 
    2605           0 : unsigned fastEmit_ISD_UMIN_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2606           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2607             :     return 0;
    2608           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2609           0 :     return fastEmitInst_rr(Mips::MIN_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2610             :   }
    2611             :   return 0;
    2612             : }
    2613             : 
    2614           0 : unsigned fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2615           0 :   switch (VT.SimpleTy) {
    2616           0 :   case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2617           0 :   case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2618           0 :   case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2619           0 :   case MVT::v2i64: return fastEmit_ISD_UMIN_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2620             :   default: return 0;
    2621             :   }
    2622             : }
    2623             : 
    2624             : // FastEmit functions for ISD::UREM.
    2625             : 
    2626           4 : unsigned fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2627           4 :   if (RetVT.SimpleTy != MVT::i32)
    2628             :     return 0;
    2629           4 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding())) {
    2630           0 :     return fastEmitInst_rr(Mips::MODU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2631             :   }
    2632           4 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2633           0 :     return fastEmitInst_rr(Mips::MODU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2634             :   }
    2635             :   return 0;
    2636             : }
    2637             : 
    2638           0 : unsigned fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2639           0 :   if (RetVT.SimpleTy != MVT::i64)
    2640             :     return 0;
    2641           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2642           0 :     return fastEmitInst_rr(Mips::DMODU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2643             :   }
    2644             :   return 0;
    2645             : }
    2646             : 
    2647           0 : unsigned fastEmit_ISD_UREM_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2648           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2649             :     return 0;
    2650           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2651           0 :     return fastEmitInst_rr(Mips::MOD_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2652             :   }
    2653             :   return 0;
    2654             : }
    2655             : 
    2656           0 : unsigned fastEmit_ISD_UREM_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2657           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2658             :     return 0;
    2659           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2660           0 :     return fastEmitInst_rr(Mips::MOD_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2661             :   }
    2662             :   return 0;
    2663             : }
    2664             : 
    2665           0 : unsigned fastEmit_ISD_UREM_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2666           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2667             :     return 0;
    2668           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2669           0 :     return fastEmitInst_rr(Mips::MOD_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2670             :   }
    2671             :   return 0;
    2672             : }
    2673             : 
    2674           0 : unsigned fastEmit_ISD_UREM_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2675           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2676             :     return 0;
    2677           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2678           0 :     return fastEmitInst_rr(Mips::MOD_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2679             :   }
    2680             :   return 0;
    2681             : }
    2682             : 
    2683           4 : unsigned fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2684           4 :   switch (VT.SimpleTy) {
    2685           4 :   case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2686           0 :   case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2687           0 :   case MVT::v16i8: return fastEmit_ISD_UREM_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2688           0 :   case MVT::v8i16: return fastEmit_ISD_UREM_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2689           0 :   case MVT::v4i32: return fastEmit_ISD_UREM_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2690           0 :   case MVT::v2i64: return fastEmit_ISD_UREM_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2691             :   default: return 0;
    2692             :   }
    2693             : }
    2694             : 
    2695             : // FastEmit functions for ISD::XOR.
    2696             : 
    2697           4 : unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2698           4 :   if (RetVT.SimpleTy != MVT::i32)
    2699             :     return 0;
    2700           4 :   if ((Subtarget->inMips16Mode())) {
    2701           0 :     return fastEmitInst_rr(Mips::XorRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2702             :   }
    2703             :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding())) {
    2704           0 :     return fastEmitInst_rr(Mips::XOR_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2705             :   }
    2706           4 :   if ((Subtarget->inMicroMipsMode())) {
    2707           0 :     return fastEmitInst_rr(Mips::XOR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2708             :   }
    2709             :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
    2710             :     return fastEmitInst_rr(Mips::XOR16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2711             :   }
    2712             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2713           8 :     return fastEmitInst_rr(Mips::XOR, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2714             :   }
    2715             :   return 0;
    2716             : }
    2717             : 
    2718             : unsigned fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2719           0 :   if (RetVT.SimpleTy != MVT::i64)
    2720             :     return 0;
    2721           0 :   if ((Subtarget->hasStandardEncoding())) {
    2722             :     return fastEmitInst_rr(Mips::XOR64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2723             :   }
    2724             :   return 0;
    2725             : }
    2726             : 
    2727           0 : unsigned fastEmit_ISD_XOR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2728           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2729             :     return 0;
    2730           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2731           0 :     return fastEmitInst_rr(Mips::XOR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2732             :   }
    2733             :   return 0;
    2734             : }
    2735             : 
    2736             : unsigned fastEmit_ISD_XOR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2737           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2738             :     return 0;
    2739           0 :   if ((Subtarget->hasMSA())) {
    2740             :     return fastEmitInst_rr(Mips::XOR_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2741             :   }
    2742             :   return 0;
    2743             : }
    2744             : 
    2745             : unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2746           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2747             :     return 0;
    2748           0 :   if ((Subtarget->hasMSA())) {
    2749             :     return fastEmitInst_rr(Mips::XOR_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2750             :   }
    2751             :   return 0;
    2752             : }
    2753             : 
    2754             : unsigned fastEmit_ISD_XOR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2755           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2756             :     return 0;
    2757           0 :   if ((Subtarget->hasMSA())) {
    2758             :     return fastEmitInst_rr(Mips::XOR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2759             :   }
    2760             :   return 0;
    2761             : }
    2762             : 
    2763           4 : unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2764           4 :   switch (VT.SimpleTy) {
    2765           4 :   case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2766           0 :   case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2767           0 :   case MVT::v16i8: return fastEmit_ISD_XOR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2768           0 :   case MVT::v8i16: return fastEmit_ISD_XOR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2769           0 :   case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2770           0 :   case MVT::v2i64: return fastEmit_ISD_XOR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2771             :   default: return 0;
    2772             :   }
    2773             : }
    2774             : 
    2775             : // FastEmit functions for MipsISD::BuildPairF64.
    2776             : 
    2777           0 : unsigned fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2778           0 :   if (RetVT.SimpleTy != MVT::f64)
    2779             :     return 0;
    2780           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
    2781           0 :     return fastEmitInst_rr(Mips::BuildPairF64_64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2782             :   }
    2783           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
    2784           0 :     return fastEmitInst_rr(Mips::BuildPairF64, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2785             :   }
    2786             :   return 0;
    2787             : }
    2788             : 
    2789             : unsigned fastEmit_MipsISD_BuildPairF64_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2790           0 :   switch (VT.SimpleTy) {
    2791           0 :   case MVT::i32: return fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2792             :   default: return 0;
    2793             :   }
    2794             : }
    2795             : 
    2796             : // FastEmit functions for MipsISD::DivRem.
    2797             : 
    2798           0 : unsigned fastEmit_MipsISD_DivRem_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2799           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    2800             :     return 0;
    2801           0 :   if ((Subtarget->inMicroMipsMode())) {
    2802           0 :     return fastEmitInst_rr(Mips::SDIV_MM_Pseudo, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2803             :   }
    2804           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    2805           0 :     return fastEmitInst_rr(Mips::PseudoSDIV, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2806             :   }
    2807             :   return 0;
    2808             : }
    2809             : 
    2810           0 : unsigned fastEmit_MipsISD_DivRem_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2811           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    2812             :     return 0;
    2813           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    2814           0 :     return fastEmitInst_rr(Mips::PseudoDSDIV, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2815             :   }
    2816             :   return 0;
    2817             : }
    2818             : 
    2819           0 : unsigned fastEmit_MipsISD_DivRem_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2820           0 :   switch (VT.SimpleTy) {
    2821           0 :   case MVT::i32: return fastEmit_MipsISD_DivRem_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2822           0 :   case MVT::i64: return fastEmit_MipsISD_DivRem_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2823             :   default: return 0;
    2824             :   }
    2825             : }
    2826             : 
    2827             : // FastEmit functions for MipsISD::DivRem16.
    2828             : 
    2829             : unsigned fastEmit_MipsISD_DivRem16_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2830           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2831             :     return 0;
    2832           0 :   if ((Subtarget->inMips16Mode())) {
    2833             :     return fastEmitInst_rr(Mips::DivRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2834             :   }
    2835             :   return 0;
    2836             : }
    2837             : 
    2838           0 : unsigned fastEmit_MipsISD_DivRem16_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2839           0 :   switch (VT.SimpleTy) {
    2840           0 :   case MVT::i32: return fastEmit_MipsISD_DivRem16_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2841             :   default: return 0;
    2842             :   }
    2843             : }
    2844             : 
    2845             : // FastEmit functions for MipsISD::DivRemU.
    2846             : 
    2847           0 : unsigned fastEmit_MipsISD_DivRemU_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2848           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    2849             :     return 0;
    2850           0 :   if ((Subtarget->inMicroMipsMode())) {
    2851           0 :     return fastEmitInst_rr(Mips::UDIV_MM_Pseudo, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2852             :   }
    2853           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    2854           0 :     return fastEmitInst_rr(Mips::PseudoUDIV, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2855             :   }
    2856             :   return 0;
    2857             : }
    2858             : 
    2859           0 : unsigned fastEmit_MipsISD_DivRemU_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2860           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    2861             :     return 0;
    2862           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    2863           0 :     return fastEmitInst_rr(Mips::PseudoDUDIV, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2864             :   }
    2865             :   return 0;
    2866             : }
    2867             : 
    2868           0 : unsigned fastEmit_MipsISD_DivRemU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2869           0 :   switch (VT.SimpleTy) {
    2870           0 :   case MVT::i32: return fastEmit_MipsISD_DivRemU_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2871           0 :   case MVT::i64: return fastEmit_MipsISD_DivRemU_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2872             :   default: return 0;
    2873             :   }
    2874             : }
    2875             : 
    2876             : // FastEmit functions for MipsISD::DivRemU16.
    2877             : 
    2878             : unsigned fastEmit_MipsISD_DivRemU16_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2879           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2880             :     return 0;
    2881           0 :   if ((Subtarget->inMips16Mode())) {
    2882             :     return fastEmitInst_rr(Mips::DivuRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2883             :   }
    2884             :   return 0;
    2885             : }
    2886             : 
    2887           0 : unsigned fastEmit_MipsISD_DivRemU16_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2888           0 :   switch (VT.SimpleTy) {
    2889           0 :   case MVT::i32: return fastEmit_MipsISD_DivRemU16_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2890             :   default: return 0;
    2891             :   }
    2892             : }
    2893             : 
    2894             : // FastEmit functions for MipsISD::EH_RETURN.
    2895             : 
    2896             : unsigned fastEmit_MipsISD_EH_RETURN_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2897           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2898             :     return 0;
    2899             :   return fastEmitInst_rr(Mips::MIPSeh_return32, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2900             : }
    2901             : 
    2902             : unsigned fastEmit_MipsISD_EH_RETURN_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2903           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2904             :     return 0;
    2905             :   return fastEmitInst_rr(Mips::MIPSeh_return64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2906             : }
    2907             : 
    2908           0 : unsigned fastEmit_MipsISD_EH_RETURN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2909           0 :   switch (VT.SimpleTy) {
    2910           0 :   case MVT::i32: return fastEmit_MipsISD_EH_RETURN_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2911           0 :   case MVT::i64: return fastEmit_MipsISD_EH_RETURN_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2912             :   default: return 0;
    2913             :   }
    2914             : }
    2915             : 
    2916             : // FastEmit functions for MipsISD::ILVEV.
    2917             : 
    2918           0 : unsigned fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2919           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2920             :     return 0;
    2921           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2922           0 :     return fastEmitInst_rr(Mips::ILVEV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2923             :   }
    2924             :   return 0;
    2925             : }
    2926             : 
    2927           0 : unsigned fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2928           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2929             :     return 0;
    2930           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2931           0 :     return fastEmitInst_rr(Mips::ILVEV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2932             :   }
    2933             :   return 0;
    2934             : }
    2935             : 
    2936           0 : unsigned fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2937           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2938             :     return 0;
    2939           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2940           0 :     return fastEmitInst_rr(Mips::ILVEV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2941             :   }
    2942             :   return 0;
    2943             : }
    2944             : 
    2945           0 : unsigned fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2946           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2947             :     return 0;
    2948           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2949           0 :     return fastEmitInst_rr(Mips::ILVEV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2950             :   }
    2951             :   return 0;
    2952             : }
    2953             : 
    2954           0 : unsigned fastEmit_MipsISD_ILVEV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2955           0 :   switch (VT.SimpleTy) {
    2956           0 :   case MVT::v16i8: return fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2957           0 :   case MVT::v8i16: return fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2958           0 :   case MVT::v4i32: return fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2959           0 :   case MVT::v2i64: return fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2960             :   default: return 0;
    2961             :   }
    2962             : }
    2963             : 
    2964             : // FastEmit functions for MipsISD::ILVL.
    2965             : 
    2966           0 : unsigned fastEmit_MipsISD_ILVL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2967           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2968             :     return 0;
    2969           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2970           0 :     return fastEmitInst_rr(Mips::ILVL_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2971             :   }
    2972             :   return 0;
    2973             : }
    2974             : 
    2975           0 : unsigned fastEmit_MipsISD_ILVL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2976           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2977             :     return 0;
    2978           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2979           0 :     return fastEmitInst_rr(Mips::ILVL_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2980             :   }
    2981             :   return 0;
    2982             : }
    2983             : 
    2984           0 : unsigned fastEmit_MipsISD_ILVL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2985           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2986             :     return 0;
    2987           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2988           0 :     return fastEmitInst_rr(Mips::ILVL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2989             :   }
    2990             :   return 0;
    2991             : }
    2992             : 
    2993           0 : unsigned fastEmit_MipsISD_ILVL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2994           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2995             :     return 0;
    2996           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2997           0 :     return fastEmitInst_rr(Mips::ILVL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2998             :   }
    2999             :   return 0;
    3000             : }
    3001             : 
    3002           0 : unsigned fastEmit_MipsISD_ILVL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3003           0 :   switch (VT.SimpleTy) {
    3004           0 :   case MVT::v16i8: return fastEmit_MipsISD_ILVL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3005           0 :   case MVT::v8i16: return fastEmit_MipsISD_ILVL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3006           0 :   case MVT::v4i32: return fastEmit_MipsISD_ILVL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3007           0 :   case MVT::v2i64: return fastEmit_MipsISD_ILVL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3008             :   default: return 0;
    3009             :   }
    3010             : }
    3011             : 
    3012             : // FastEmit functions for MipsISD::ILVOD.
    3013             : 
    3014           0 : unsigned fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3015           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3016             :     return 0;
    3017           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3018           0 :     return fastEmitInst_rr(Mips::ILVOD_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3019             :   }
    3020             :   return 0;
    3021             : }
    3022             : 
    3023           0 : unsigned fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3024           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3025             :     return 0;
    3026           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3027           0 :     return fastEmitInst_rr(Mips::ILVOD_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3028             :   }
    3029             :   return 0;
    3030             : }
    3031             : 
    3032           0 : unsigned fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3033           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3034             :     return 0;
    3035           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3036           0 :     return fastEmitInst_rr(Mips::ILVOD_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3037             :   }
    3038             :   return 0;
    3039             : }
    3040             : 
    3041           0 : unsigned fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3042           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3043             :     return 0;
    3044           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3045           0 :     return fastEmitInst_rr(Mips::ILVOD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3046             :   }
    3047             :   return 0;
    3048             : }
    3049             : 
    3050           0 : unsigned fastEmit_MipsISD_ILVOD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3051           0 :   switch (VT.SimpleTy) {
    3052           0 :   case MVT::v16i8: return fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3053           0 :   case MVT::v8i16: return fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3054           0 :   case MVT::v4i32: return fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3055           0 :   case MVT::v2i64: return fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3056             :   default: return 0;
    3057             :   }
    3058             : }
    3059             : 
    3060             : // FastEmit functions for MipsISD::ILVR.
    3061             : 
    3062           0 : unsigned fastEmit_MipsISD_ILVR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3063           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3064             :     return 0;
    3065           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3066           0 :     return fastEmitInst_rr(Mips::ILVR_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3067             :   }
    3068             :   return 0;
    3069             : }
    3070             : 
    3071           0 : unsigned fastEmit_MipsISD_ILVR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3072           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3073             :     return 0;
    3074           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3075           0 :     return fastEmitInst_rr(Mips::ILVR_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3076             :   }
    3077             :   return 0;
    3078             : }
    3079             : 
    3080           0 : unsigned fastEmit_MipsISD_ILVR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3081           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3082             :     return 0;
    3083           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3084           0 :     return fastEmitInst_rr(Mips::ILVR_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3085             :   }
    3086             :   return 0;
    3087             : }
    3088             : 
    3089           0 : unsigned fastEmit_MipsISD_ILVR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3090           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3091             :     return 0;
    3092           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3093           0 :     return fastEmitInst_rr(Mips::ILVR_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3094             :   }
    3095             :   return 0;
    3096             : }
    3097             : 
    3098           0 : unsigned fastEmit_MipsISD_ILVR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3099           0 :   switch (VT.SimpleTy) {
    3100           0 :   case MVT::v16i8: return fastEmit_MipsISD_ILVR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3101           0 :   case MVT::v8i16: return fastEmit_MipsISD_ILVR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3102           0 :   case MVT::v4i32: return fastEmit_MipsISD_ILVR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3103           0 :   case MVT::v2i64: return fastEmit_MipsISD_ILVR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3104             :   default: return 0;
    3105             :   }
    3106             : }
    3107             : 
    3108             : // FastEmit functions for MipsISD::MTLOHI.
    3109             : 
    3110             : unsigned fastEmit_MipsISD_MTLOHI_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3111           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    3112             :     return 0;
    3113           0 :   if ((Subtarget->hasStandardEncoding())) {
    3114             :     return fastEmitInst_rr(Mips::PseudoMTLOHI_DSP, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3115             :   }
    3116             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    3117             :     return fastEmitInst_rr(Mips::PseudoMTLOHI, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3118             :   }
    3119             :   return 0;
    3120             : }
    3121             : 
    3122           0 : unsigned fastEmit_MipsISD_MTLOHI_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3123           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    3124             :     return 0;
    3125           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    3126           0 :     return fastEmitInst_rr(Mips::PseudoMTLOHI64, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3127             :   }
    3128             :   return 0;
    3129             : }
    3130             : 
    3131           0 : unsigned fastEmit_MipsISD_MTLOHI_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3132           0 :   switch (VT.SimpleTy) {
    3133           0 :   case MVT::i32: return fastEmit_MipsISD_MTLOHI_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3134           0 :   case MVT::i64: return fastEmit_MipsISD_MTLOHI_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3135             :   default: return 0;
    3136             :   }
    3137             : }
    3138             : 
    3139             : // FastEmit functions for MipsISD::Mult.
    3140             : 
    3141           0 : unsigned fastEmit_MipsISD_Mult_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3142           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    3143             :     return 0;
    3144           0 :   if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
    3145           0 :     return fastEmitInst_rr(Mips::MULT_DSP_MM, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3146             :   }
    3147           0 :   if ((Subtarget->hasDSP())) {
    3148           0 :     return fastEmitInst_rr(Mips::MULT_DSP, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3149             :   }
    3150           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    3151           0 :     return fastEmitInst_rr(Mips::PseudoMULT, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3152             :   }
    3153             :   return 0;
    3154             : }
    3155             : 
    3156           0 : unsigned fastEmit_MipsISD_Mult_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3157           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    3158             :     return 0;
    3159           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    3160           0 :     return fastEmitInst_rr(Mips::PseudoDMULT, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3161             :   }
    3162             :   return 0;
    3163             : }
    3164             : 
    3165           0 : unsigned fastEmit_MipsISD_Mult_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3166           0 :   switch (VT.SimpleTy) {
    3167           0 :   case MVT::i32: return fastEmit_MipsISD_Mult_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3168           0 :   case MVT::i64: return fastEmit_MipsISD_Mult_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3169             :   default: return 0;
    3170             :   }
    3171             : }
    3172             : 
    3173             : // FastEmit functions for MipsISD::Multu.
    3174             : 
    3175           0 : unsigned fastEmit_MipsISD_Multu_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3176           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    3177             :     return 0;
    3178           0 :   if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
    3179           0 :     return fastEmitInst_rr(Mips::MULTU_DSP_MM, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3180             :   }
    3181           0 :   if ((Subtarget->hasDSP())) {
    3182           0 :     return fastEmitInst_rr(Mips::MULTU_DSP, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3183             :   }
    3184           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    3185           0 :     return fastEmitInst_rr(Mips::PseudoMULTu, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3186             :   }
    3187             :   return 0;
    3188             : }
    3189             : 
    3190           0 : unsigned fastEmit_MipsISD_Multu_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3191           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    3192             :     return 0;
    3193           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    3194           0 :     return fastEmitInst_rr(Mips::PseudoDMULTu, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3195             :   }
    3196             :   return 0;
    3197             : }
    3198             : 
    3199           0 : unsigned fastEmit_MipsISD_Multu_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3200           0 :   switch (VT.SimpleTy) {
    3201           0 :   case MVT::i32: return fastEmit_MipsISD_Multu_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3202           0 :   case MVT::i64: return fastEmit_MipsISD_Multu_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3203             :   default: return 0;
    3204             :   }
    3205             : }
    3206             : 
    3207             : // FastEmit functions for MipsISD::PCKEV.
    3208             : 
    3209           0 : unsigned fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3210           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3211             :     return 0;
    3212           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3213           0 :     return fastEmitInst_rr(Mips::PCKEV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3214             :   }
    3215             :   return 0;
    3216             : }
    3217             : 
    3218           0 : unsigned fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3219           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3220             :     return 0;
    3221           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3222           0 :     return fastEmitInst_rr(Mips::PCKEV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3223             :   }
    3224             :   return 0;
    3225             : }
    3226             : 
    3227           0 : unsigned fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3228           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3229             :     return 0;
    3230           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3231           0 :     return fastEmitInst_rr(Mips::PCKEV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3232             :   }
    3233             :   return 0;
    3234             : }
    3235             : 
    3236           0 : unsigned fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3237           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3238             :     return 0;
    3239           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3240           0 :     return fastEmitInst_rr(Mips::PCKEV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3241             :   }
    3242             :   return 0;
    3243             : }
    3244             : 
    3245           0 : unsigned fastEmit_MipsISD_PCKEV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3246           0 :   switch (VT.SimpleTy) {
    3247           0 :   case MVT::v16i8: return fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3248           0 :   case MVT::v8i16: return fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3249           0 :   case MVT::v4i32: return fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3250           0 :   case MVT::v2i64: return fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3251             :   default: return 0;
    3252             :   }
    3253             : }
    3254             : 
    3255             : // FastEmit functions for MipsISD::PCKOD.
    3256             : 
    3257           0 : unsigned fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3258           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3259             :     return 0;
    3260           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3261           0 :     return fastEmitInst_rr(Mips::PCKOD_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3262             :   }
    3263             :   return 0;
    3264             : }
    3265             : 
    3266           0 : unsigned fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3267           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3268             :     return 0;
    3269           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3270           0 :     return fastEmitInst_rr(Mips::PCKOD_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3271             :   }
    3272             :   return 0;
    3273             : }
    3274             : 
    3275           0 : unsigned fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3276           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3277             :     return 0;
    3278           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3279           0 :     return fastEmitInst_rr(Mips::PCKOD_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3280             :   }
    3281             :   return 0;
    3282             : }
    3283             : 
    3284           0 : unsigned fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3285           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3286             :     return 0;
    3287           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3288           0 :     return fastEmitInst_rr(Mips::PCKOD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3289             :   }
    3290             :   return 0;
    3291             : }
    3292             : 
    3293           0 : unsigned fastEmit_MipsISD_PCKOD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3294           0 :   switch (VT.SimpleTy) {
    3295           0 :   case MVT::v16i8: return fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3296           0 :   case MVT::v8i16: return fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3297           0 :   case MVT::v4i32: return fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3298           0 :   case MVT::v2i64: return fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3299             :   default: return 0;
    3300             :   }
    3301             : }
    3302             : 
    3303             : // FastEmit functions for MipsISD::VNOR.
    3304             : 
    3305           0 : unsigned fastEmit_MipsISD_VNOR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3306           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3307             :     return 0;
    3308           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3309           0 :     return fastEmitInst_rr(Mips::NOR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3310             :   }
    3311             :   return 0;
    3312             : }
    3313             : 
    3314             : unsigned fastEmit_MipsISD_VNOR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3315           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3316             :     return 0;
    3317           0 :   if ((Subtarget->hasMSA())) {
    3318             :     return fastEmitInst_rr(Mips::NOR_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3319             :   }
    3320             :   return 0;
    3321             : }
    3322             : 
    3323             : unsigned fastEmit_MipsISD_VNOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3324           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3325             :     return 0;
    3326           0 :   if ((Subtarget->hasMSA())) {
    3327             :     return fastEmitInst_rr(Mips::NOR_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3328             :   }
    3329             :   return 0;
    3330             : }
    3331             : 
    3332             : unsigned fastEmit_MipsISD_VNOR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3333           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3334             :     return 0;
    3335           0 :   if ((Subtarget->hasMSA())) {
    3336             :     return fastEmitInst_rr(Mips::NOR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3337             :   }
    3338             :   return 0;
    3339             : }
    3340             : 
    3341           0 : unsigned fastEmit_MipsISD_VNOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3342           0 :   switch (VT.SimpleTy) {
    3343           0 :   case MVT::v16i8: return fastEmit_MipsISD_VNOR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3344           0 :   case MVT::v8i16: return fastEmit_MipsISD_VNOR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3345           0 :   case MVT::v4i32: return fastEmit_MipsISD_VNOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3346           0 :   case MVT::v2i64: return fastEmit_MipsISD_VNOR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3347             :   default: return 0;
    3348             :   }
    3349             : }
    3350             : 
    3351             : // Top-level FastEmit function.
    3352             : 
    3353          37 : unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) override {
    3354          37 :   switch (Opcode) {
    3355           6 :   case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3356           0 :   case ISD::ADDC: return fastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3357           0 :   case ISD::ADDE: return fastEmit_ISD_ADDE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3358           5 :   case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3359           0 :   case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3360           0 :   case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3361           0 :   case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3362           0 :   case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3363           2 :   case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3364           0 :   case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3365           0 :   case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3366           4 :   case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3367           0 :   case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3368           4 :   case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3369           0 :   case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3370           0 :   case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3371           0 :   case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3372           0 :   case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3373           4 :   case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3374           0 :   case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3375           0 :   case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3376           0 :   case ISD::SUBC: return fastEmit_ISD_SUBC_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3377           4 :   case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3378           0 :   case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3379           0 :   case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3380           4 :   case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3381           4 :   case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3382           0 :   case MipsISD::BuildPairF64: return fastEmit_MipsISD_BuildPairF64_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3383           0 :   case MipsISD::DivRem: return fastEmit_MipsISD_DivRem_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3384           0 :   case MipsISD::DivRem16: return fastEmit_MipsISD_DivRem16_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3385           0 :   case MipsISD::DivRemU: return fastEmit_MipsISD_DivRemU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3386           0 :   case MipsISD::DivRemU16: return fastEmit_MipsISD_DivRemU16_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3387           0 :   case MipsISD::EH_RETURN: return fastEmit_MipsISD_EH_RETURN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3388           0 :   case MipsISD::ILVEV: return fastEmit_MipsISD_ILVEV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3389           0 :   case MipsISD::ILVL: return fastEmit_MipsISD_ILVL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3390           0 :   case MipsISD::ILVOD: return fastEmit_MipsISD_ILVOD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3391           0 :   case MipsISD::ILVR: return fastEmit_MipsISD_ILVR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3392           0 :   case MipsISD::MTLOHI: return fastEmit_MipsISD_MTLOHI_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3393           0 :   case MipsISD::Mult: return fastEmit_MipsISD_Mult_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3394           0 :   case MipsISD::Multu: return fastEmit_MipsISD_Multu_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3395           0 :   case MipsISD::PCKEV: return fastEmit_MipsISD_PCKEV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3396           0 :   case MipsISD::PCKOD: return fastEmit_MipsISD_PCKOD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3397           0 :   case MipsISD::VNOR: return fastEmit_MipsISD_VNOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3398             :   default: return 0;
    3399             :   }
    3400             : }
    3401             : 
    3402             : // FastEmit functions for MipsISD::ExtractElementF64.
    3403             : 
    3404           0 : unsigned fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3405           0 :   if (RetVT.SimpleTy != MVT::i32)
    3406             :     return 0;
    3407           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
    3408           0 :     return fastEmitInst_ri(Mips::ExtractElementF64_64, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3409             :   }
    3410           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
    3411           0 :     return fastEmitInst_ri(Mips::ExtractElementF64, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3412             :   }
    3413             :   return 0;
    3414             : }
    3415             : 
    3416             : unsigned fastEmit_MipsISD_ExtractElementF64_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3417           0 :   switch (VT.SimpleTy) {
    3418           0 :   case MVT::f64: return fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(RetVT, Op0, Op0IsKill, imm1);
    3419             :   default: return 0;
    3420             :   }
    3421             : }
    3422             : 
    3423             : // FastEmit functions for MipsISD::SHLL_DSP.
    3424             : 
    3425             : unsigned fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3426           0 :   if (RetVT.SimpleTy != MVT::v4i8)
    3427             :     return 0;
    3428           0 :   if ((Subtarget->hasDSP())) {
    3429           0 :     return fastEmitInst_ri(Mips::SHLL_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
    3430             :   }
    3431             :   return 0;
    3432             : }
    3433             : 
    3434             : unsigned fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3435           0 :   if (RetVT.SimpleTy != MVT::v2i16)
    3436             :     return 0;
    3437           0 :   if ((Subtarget->hasDSP())) {
    3438           0 :     return fastEmitInst_ri(Mips::SHLL_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
    3439             :   }
    3440             :   return 0;
    3441             : }
    3442             : 
    3443           0 : unsigned fastEmit_MipsISD_SHLL_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3444           0 :   switch (VT.SimpleTy) {
    3445           0 :   case MVT::v4i8: return fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(RetVT, Op0, Op0IsKill, imm1);
    3446           0 :   case MVT::v2i16: return fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(RetVT, Op0, Op0IsKill, imm1);
    3447             :   default: return 0;
    3448             :   }
    3449             : }
    3450             : 
    3451             : // FastEmit functions for MipsISD::SHRA_DSP.
    3452             : 
    3453             : unsigned fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3454           0 :   if (RetVT.SimpleTy != MVT::v4i8)
    3455             :     return 0;
    3456           0 :   if ((Subtarget->hasDSPR2())) {
    3457           0 :     return fastEmitInst_ri(Mips::SHRA_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
    3458             :   }
    3459             :   return 0;
    3460             : }
    3461             : 
    3462             : unsigned fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3463           0 :   if (RetVT.SimpleTy != MVT::v2i16)
    3464             :     return 0;
    3465           0 :   if ((Subtarget->hasDSP())) {
    3466           0 :     return fastEmitInst_ri(Mips::SHRA_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
    3467             :   }
    3468             :   return 0;
    3469             : }
    3470             : 
    3471           0 : unsigned fastEmit_MipsISD_SHRA_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3472           0 :   switch (VT.SimpleTy) {
    3473           0 :   case MVT::v4i8: return fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(RetVT, Op0, Op0IsKill, imm1);
    3474           0 :   case MVT::v2i16: return fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(RetVT, Op0, Op0IsKill, imm1);
    3475             :   default: return 0;
    3476             :   }
    3477             : }
    3478             : 
    3479             : // FastEmit functions for MipsISD::SHRL_DSP.
    3480             : 
    3481             : unsigned fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3482           0 :   if (RetVT.SimpleTy != MVT::v4i8)
    3483             :     return 0;
    3484           0 :   if ((Subtarget->hasDSP())) {
    3485           0 :     return fastEmitInst_ri(Mips::SHRL_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
    3486             :   }
    3487             :   return 0;
    3488             : }
    3489             : 
    3490             : unsigned fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3491           0 :   if (RetVT.SimpleTy != MVT::v2i16)
    3492             :     return 0;
    3493           0 :   if ((Subtarget->hasDSPR2())) {
    3494           0 :     return fastEmitInst_ri(Mips::SHRL_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
    3495             :   }
    3496             :   return 0;
    3497             : }
    3498             : 
    3499           0 : unsigned fastEmit_MipsISD_SHRL_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3500           0 :   switch (VT.SimpleTy) {
    3501           0 :   case MVT::v4i8: return fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(RetVT, Op0, Op0IsKill, imm1);
    3502           0 :   case MVT::v2i16: return fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(RetVT, Op0, Op0IsKill, imm1);
    3503             :   default: return 0;
    3504             :   }
    3505             : }
    3506             : 
    3507             : // Top-level FastEmit function.
    3508             : 
    3509           7 : unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) override {
    3510          14 :   if (VT == MVT::i32 && Predicate_immZExt5(imm1))
    3511           7 :     if (unsigned Reg = fastEmit_ri_Predicate_immZExt5(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3512             :       return Reg;
    3513             : 
    3514          14 :   if (VT == MVT::i32 && Predicate_immZExt6(imm1))
    3515           7 :     if (unsigned Reg = fastEmit_ri_Predicate_immZExt6(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3516             :       return Reg;
    3517             : 
    3518           7 :   if (VT == MVT::iPTR && Predicate_immZExt2Ptr(imm1))
    3519           0 :     if (unsigned Reg = fastEmit_ri_Predicate_immZExt2Ptr(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3520             :       return Reg;
    3521             : 
    3522           7 :   if (VT == MVT::iPTR && Predicate_immZExt1Ptr(imm1))
    3523           0 :     if (unsigned Reg = fastEmit_ri_Predicate_immZExt1Ptr(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3524             :       return Reg;
    3525             : 
    3526           7 :   if (VT == MVT::i32 && Predicate_immZExt4(imm1))
    3527           7 :     if (unsigned Reg = fastEmit_ri_Predicate_immZExt4(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3528             :       return Reg;
    3529             : 
    3530           7 :   if (VT == MVT::i32 && Predicate_immSExtAddiur2(imm1))
    3531           2 :     if (unsigned Reg = fastEmit_ri_Predicate_immSExtAddiur2(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3532             :       return Reg;
    3533             : 
    3534          14 :   if (VT == MVT::i32 && Predicate_immSExtAddius5(imm1))
    3535           8 :     if (unsigned Reg = fastEmit_ri_Predicate_immSExtAddius5(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3536             :       return Reg;
    3537             : 
    3538           7 :   if (VT == MVT::i32 && Predicate_immZExtAndi16(imm1))
    3539           1 :     if (unsigned Reg = fastEmit_ri_Predicate_immZExtAndi16(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3540             :       return Reg;
    3541             : 
    3542          14 :   if (VT == MVT::i32 && Predicate_immZExt2Shift(imm1))
    3543           1 :     if (unsigned Reg = fastEmit_ri_Predicate_immZExt2Shift(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3544             :       return Reg;
    3545             : 
    3546           7 :   switch (Opcode) {
    3547           0 :   case MipsISD::ExtractElementF64: return fastEmit_MipsISD_ExtractElementF64_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    3548           0 :   case MipsISD::SHLL_DSP: return fastEmit_MipsISD_SHLL_DSP_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    3549           0 :   case MipsISD::SHRA_DSP: return fastEmit_MipsISD_SHRA_DSP_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    3550           0 :   case MipsISD::SHRL_DSP: return fastEmit_MipsISD_SHRL_DSP_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    3551             :   default: return 0;
    3552             :   }
    3553             : }
    3554             : 
    3555             : // FastEmit functions for ISD::ROTR.
    3556             : 
    3557           0 : unsigned fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3558           0 :   if (RetVT.SimpleTy != MVT::i32)
    3559             :     return 0;
    3560           0 :   if ((Subtarget->inMicroMipsMode())) {
    3561           0 :     return fastEmitInst_ri(Mips::ROTR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3562             :   }
    3563           0 :   if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3564           0 :     return fastEmitInst_ri(Mips::ROTR, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3565             :   }
    3566             :   return 0;
    3567             : }
    3568             : 
    3569             : unsigned fastEmit_ISD_ROTR_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3570           0 :   switch (VT.SimpleTy) {
    3571           0 :   case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1);
    3572             :   default: return 0;
    3573             :   }
    3574             : }
    3575             : 
    3576             : // FastEmit functions for ISD::SHL.
    3577             : 
    3578           0 : unsigned fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3579           0 :   if (RetVT.SimpleTy != MVT::i32)
    3580             :     return 0;
    3581           0 :   if ((Subtarget->inMicroMipsMode())) {
    3582           0 :     return fastEmitInst_ri(Mips::SLL_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3583             :   }
    3584           0 :   if ((Subtarget->inMips16Mode())) {
    3585           0 :     return fastEmitInst_ri(Mips::SllX16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, imm1);
    3586             :   }
    3587             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3588           0 :     return fastEmitInst_ri(Mips::SLL, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3589             :   }
    3590             :   return 0;
    3591             : }
    3592             : 
    3593             : unsigned fastEmit_ISD_SHL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3594           0 :   switch (VT.SimpleTy) {
    3595           0 :   case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1);
    3596             :   default: return 0;
    3597             :   }
    3598             : }
    3599             : 
    3600             : // FastEmit functions for ISD::SRA.
    3601             : 
    3602           0 : unsigned fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3603           0 :   if (RetVT.SimpleTy != MVT::i32)
    3604             :     return 0;
    3605           0 :   if ((Subtarget->inMicroMipsMode())) {
    3606           0 :     return fastEmitInst_ri(Mips::SRA_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3607             :   }
    3608           0 :   if ((Subtarget->inMips16Mode())) {
    3609           0 :     return fastEmitInst_ri(Mips::SraX16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, imm1);
    3610             :   }
    3611             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3612           0 :     return fastEmitInst_ri(Mips::SRA, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3613             :   }
    3614             :   return 0;
    3615             : }
    3616             : 
    3617             : unsigned fastEmit_ISD_SRA_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3618           0 :   switch (VT.SimpleTy) {
    3619           0 :   case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1);
    3620             :   default: return 0;
    3621             :   }
    3622             : }
    3623             : 
    3624             : // FastEmit functions for ISD::SRL.
    3625             : 
    3626           0 : unsigned fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3627           0 :   if (RetVT.SimpleTy != MVT::i32)
    3628             :     return 0;
    3629           0 :   if ((Subtarget->inMicroMipsMode())) {
    3630           0 :     return fastEmitInst_ri(Mips::SRL_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3631             :   }
    3632           0 :   if ((Subtarget->inMips16Mode())) {
    3633           0 :     return fastEmitInst_ri(Mips::SrlX16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, imm1);
    3634             :   }
    3635             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3636           0 :     return fastEmitInst_ri(Mips::SRL, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3637             :   }
    3638             :   return 0;
    3639             : }
    3640             : 
    3641             : unsigned fastEmit_ISD_SRL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3642           0 :   switch (VT.SimpleTy) {
    3643           0 :   case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1);
    3644             :   default: return 0;
    3645             :   }
    3646             : }
    3647             : 
    3648             : // Top-level FastEmit function.
    3649             : 
    3650           7 : unsigned fastEmit_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3651           7 :   switch (Opcode) {
    3652           0 :   case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1);
    3653           0 :   case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1);
    3654           0 :   case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1);
    3655           0 :   case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1);
    3656             :   default: return 0;
    3657             :   }
    3658             : }
    3659             : 
    3660             : // FastEmit functions for ISD::ROTR.
    3661             : 
    3662           0 : unsigned fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3663           0 :   if (RetVT.SimpleTy != MVT::i64)
    3664             :     return 0;
    3665           0 :   if ((Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3666           0 :     return fastEmitInst_ri(Mips::DROTR, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
    3667             :   }
    3668             :   return 0;
    3669             : }
    3670             : 
    3671             : unsigned fastEmit_ISD_ROTR_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3672           0 :   switch (VT.SimpleTy) {
    3673           0 :   case MVT::i64: return fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1);
    3674             :   default: return 0;
    3675             :   }
    3676             : }
    3677             : 
    3678             : // FastEmit functions for ISD::SHL.
    3679             : 
    3680           0 : unsigned fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3681           0 :   if (RetVT.SimpleTy != MVT::i64)
    3682             :     return 0;
    3683           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3684           0 :     return fastEmitInst_ri(Mips::DSLL, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
    3685             :   }
    3686             :   return 0;
    3687             : }
    3688             : 
    3689             : unsigned fastEmit_ISD_SHL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3690           0 :   switch (VT.SimpleTy) {
    3691           0 :   case MVT::i64: return fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1);
    3692             :   default: return 0;
    3693             :   }
    3694             : }
    3695             : 
    3696             : // FastEmit functions for ISD::SRA.
    3697             : 
    3698           0 : unsigned fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3699           0 :   if (RetVT.SimpleTy != MVT::i64)
    3700             :     return 0;
    3701           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3702           0 :     return fastEmitInst_ri(Mips::DSRA, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
    3703             :   }
    3704             :   return 0;
    3705             : }
    3706             : 
    3707             : unsigned fastEmit_ISD_SRA_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3708           0 :   switch (VT.SimpleTy) {
    3709           0 :   case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1);
    3710             :   default: return 0;
    3711             :   }
    3712             : }
    3713             : 
    3714             : // FastEmit functions for ISD::SRL.
    3715             : 
    3716           0 : unsigned fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3717           0 :   if (RetVT.SimpleTy != MVT::i64)
    3718             :     return 0;
    3719           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3720           0 :     return fastEmitInst_ri(Mips::DSRL, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
    3721             :   }
    3722             :   return 0;
    3723             : }
    3724             : 
    3725             : unsigned fastEmit_ISD_SRL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3726           0 :   switch (VT.SimpleTy) {
    3727           0 :   case MVT::i64: return fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1);
    3728             :   default: return 0;
    3729             :   }
    3730             : }
    3731             : 
    3732             : // Top-level FastEmit function.
    3733             : 
    3734           7 : unsigned fastEmit_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3735           7 :   switch (Opcode) {
    3736           0 :   case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1);
    3737           0 :   case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1);
    3738           0 :   case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1);
    3739           0 :   case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1);
    3740             :   default: return 0;
    3741             :   }
    3742             : }
    3743             : 
    3744             : // FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
    3745             : 
    3746             : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3747           0 :   if (RetVT.SimpleTy != MVT::f32)
    3748             :     return 0;
    3749           0 :   if ((Subtarget->hasMSA())) {
    3750           0 :     return fastEmitInst_ri(Mips::COPY_FW_PSEUDO, &Mips::FGR32RegClass, Op0, Op0IsKill, imm1);
    3751             :   }
    3752             :   return 0;
    3753             : }
    3754             : 
    3755           0 : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3756           0 :   switch (VT.SimpleTy) {
    3757           0 :   case MVT::v4f32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(RetVT, Op0, Op0IsKill, imm1);
    3758             :   default: return 0;
    3759             :   }
    3760             : }
    3761             : 
    3762             : // Top-level FastEmit function.
    3763             : 
    3764             : unsigned fastEmit_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3765           0 :   switch (Opcode) {
    3766           0 :   case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(VT, RetVT, Op0, Op0IsKill, imm1);
    3767             :   default: return 0;
    3768             :   }
    3769             : }
    3770             : 
    3771             : // FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
    3772             : 
    3773             : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3774           0 :   if (RetVT.SimpleTy != MVT::f64)
    3775             :     return 0;
    3776           0 :   if ((Subtarget->hasMSA())) {
    3777           0 :     return fastEmitInst_ri(Mips::COPY_FD_PSEUDO, &Mips::FGR64RegClass, Op0, Op0IsKill, imm1);
    3778             :   }
    3779             :   return 0;
    3780             : }
    3781             : 
    3782           0 : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3783           0 :   switch (VT.SimpleTy) {
    3784           0 :   case MVT::v2f64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(RetVT, Op0, Op0IsKill, imm1);
    3785             :   default: return 0;
    3786             :   }
    3787             : }
    3788             : 
    3789             : // Top-level FastEmit function.
    3790             : 
    3791             : unsigned fastEmit_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3792           0 :   switch (Opcode) {
    3793           0 :   case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(VT, RetVT, Op0, Op0IsKill, imm1);
    3794             :   default: return 0;
    3795             :   }
    3796             : }
    3797             : 
    3798             : // FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
    3799             : 
    3800             : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3801           0 :   if (RetVT.SimpleTy != MVT::i32)
    3802             :     return 0;
    3803           0 :   if ((Subtarget->hasMSA())) {
    3804           0 :     return fastEmitInst_ri(Mips::COPY_S_W, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3805             :   }
    3806             :   return 0;
    3807             : }
    3808             : 
    3809           0 : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3810           0 :   switch (VT.SimpleTy) {
    3811           0 :   case MVT::v4i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(RetVT, Op0, Op0IsKill, imm1);
    3812             :   default: return 0;
    3813             :   }
    3814             : }
    3815             : 
    3816             : // Top-level FastEmit function.
    3817             : 
    3818             : unsigned fastEmit_ri_Predicate_immZExt4(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3819           7 :   switch (Opcode) {
    3820           0 :   case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(VT, RetVT, Op0, Op0IsKill, imm1);
    3821             :   default: return 0;
    3822             :   }
    3823             : }
    3824             : 
    3825             : // FastEmit functions for ISD::ADD.
    3826             : 
    3827             : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3828           1 :   if (RetVT.SimpleTy != MVT::i32)
    3829             :     return 0;
    3830           1 :   if ((Subtarget->inMicroMipsMode())) {
    3831           0 :     return fastEmitInst_ri(Mips::ADDIUR2_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
    3832             :   }
    3833             :   return 0;
    3834             : }
    3835             : 
    3836           1 : unsigned fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3837           1 :   switch (VT.SimpleTy) {
    3838           1 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(RetVT, Op0, Op0IsKill, imm1);
    3839             :   default: return 0;
    3840             :   }
    3841             : }
    3842             : 
    3843             : // Top-level FastEmit function.
    3844             : 
    3845             : unsigned fastEmit_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3846           1 :   switch (Opcode) {
    3847           1 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(VT, RetVT, Op0, Op0IsKill, imm1);
    3848             :   default: return 0;
    3849             :   }
    3850             : }
    3851             : 
    3852             : // FastEmit functions for ISD::ADD.
    3853             : 
    3854             : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3855           1 :   if (RetVT.SimpleTy != MVT::i32)
    3856             :     return 0;
    3857           1 :   if ((Subtarget->inMicroMipsMode())) {
    3858           0 :     return fastEmitInst_ri(Mips::ADDIUS5_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3859             :   }
    3860             :   return 0;
    3861             : }
    3862             : 
    3863           1 : unsigned fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3864           1 :   switch (VT.SimpleTy) {
    3865           1 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(RetVT, Op0, Op0IsKill, imm1);
    3866             :   default: return 0;
    3867             :   }
    3868             : }
    3869             : 
    3870             : // Top-level FastEmit function.
    3871             : 
    3872             : unsigned fastEmit_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3873           7 :   switch (Opcode) {
    3874           1 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(VT, RetVT, Op0, Op0IsKill, imm1);
    3875             :   default: return 0;
    3876             :   }
    3877             : }
    3878             : 
    3879             : // FastEmit functions for ISD::AND.
    3880             : 
    3881           0 : unsigned fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3882           0 :   if (RetVT.SimpleTy != MVT::i32)
    3883             :     return 0;
    3884           0 :   if ((Subtarget->inMicroMips32r6Mode()) && (Subtarget->hasStandardEncoding())) {
    3885           0 :     return fastEmitInst_ri(Mips::ANDI16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
    3886             :   }
    3887           0 :   if ((Subtarget->inMicroMipsMode())) {
    3888           0 :     return fastEmitInst_ri(Mips::ANDI16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
    3889             :   }
    3890             :   return 0;
    3891             : }
    3892             : 
    3893             : unsigned fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3894           0 :   switch (VT.SimpleTy) {
    3895           0 :   case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(RetVT, Op0, Op0IsKill, imm1);
    3896             :   default: return 0;
    3897             :   }
    3898             : }
    3899             : 
    3900             : // Top-level FastEmit function.
    3901             : 
    3902           1 : unsigned fastEmit_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3903           1 :   switch (Opcode) {
    3904           0 :   case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(VT, RetVT, Op0, Op0IsKill, imm1);
    3905             :   default: return 0;
    3906             :   }
    3907             : }
    3908             : 
    3909             : // FastEmit functions for ISD::SHL.
    3910             : 
    3911             : unsigned fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3912           0 :   if (RetVT.SimpleTy != MVT::i32)
    3913             :     return 0;
    3914           0 :   if ((Subtarget->inMicroMipsMode())) {
    3915           0 :     return fastEmitInst_ri(Mips::SLL16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
    3916             :   }
    3917             :   return 0;
    3918             : }
    3919             : 
    3920           0 : unsigned fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3921           0 :   switch (VT.SimpleTy) {
    3922           0 :   case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, Op0IsKill, imm1);
    3923             :   default: return 0;
    3924             :   }
    3925             : }
    3926             : 
    3927             : // FastEmit functions for ISD::SRL.
    3928             : 
    3929             : unsigned fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3930           0 :   if (RetVT.SimpleTy != MVT::i32)
    3931             :     return 0;
    3932           0 :   if ((Subtarget->inMicroMipsMode())) {
    3933           0 :     return fastEmitInst_ri(Mips::SRL16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
    3934             :   }
    3935             :   return 0;
    3936             : }
    3937             : 
    3938           0 : unsigned fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3939           0 :   switch (VT.SimpleTy) {
    3940           0 :   case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, Op0IsKill, imm1);
    3941             :   default: return 0;
    3942             :   }
    3943             : }
    3944             : 
    3945             : // Top-level FastEmit function.
    3946             : 
    3947           1 : unsigned fastEmit_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3948           1 :   switch (Opcode) {
    3949           0 :   case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, Op0IsKill, imm1);
    3950           0 :   case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, Op0IsKill, imm1);
    3951             :   default: return 0;
    3952             :   }
    3953             : }
    3954             : 
    3955             : // FastEmit functions for ISD::Constant.
    3956             : 
    3957             : unsigned fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) {
    3958           7 :   if (RetVT.SimpleTy != MVT::i32)
    3959             :     return 0;
    3960           7 :   if ((Subtarget->inMips16Mode())) {
    3961           0 :     return fastEmitInst_i(Mips::LwConstant32, &Mips::CPU16RegsRegClass, imm0);
    3962             :   }
    3963             :   return 0;
    3964             : }
    3965             : 
    3966           7 : unsigned fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) {
    3967           7 :   switch (VT.SimpleTy) {
    3968           7 :   case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0);
    3969             :   default: return 0;
    3970             :   }
    3971             : }
    3972             : 
    3973             : // Top-level FastEmit function.
    3974             : 
    3975           7 : unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override {
    3976           7 :   switch (Opcode) {
    3977           7 :   case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0);
    3978             :   default: return 0;
    3979             :   }
    3980             : }
    3981             : 

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