LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/Mips - MipsGenFastISel.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 150 1804 8.3 %
Date: 2018-07-13 00:08:38 Functions: 31 312 9.9 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* "Fast" Instruction Selector for the Mips target                            *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : 
      10             : // FastEmit Immediate Predicate functions.
      11             : static bool Predicate_immZExt5(int64_t Imm) {
      12           7 : return Imm == (Imm & 0x1f);
      13             : }
      14             : static bool Predicate_immZExt6(int64_t Imm) {
      15           7 : return Imm == (Imm & 0x3f);
      16             : }
      17             : static bool Predicate_immSExt6(int64_t Imm) {
      18             : return isInt<6>(Imm);
      19             : }
      20             : static bool Predicate_immZExt4Ptr(int64_t Imm) {
      21             : return isUInt<4>(Imm);
      22             : }
      23             : static bool Predicate_immZExt3Ptr(int64_t Imm) {
      24             : return isUInt<3>(Imm);
      25             : }
      26             : static bool Predicate_immZExt2Ptr(int64_t Imm) {
      27             : return isUInt<2>(Imm);
      28             : }
      29             : static bool Predicate_immZExt1Ptr(int64_t Imm) {
      30             : return isUInt<1>(Imm);
      31             : }
      32             : static bool Predicate_immZExt4(int64_t Imm) {
      33             : return isUInt<4>(Imm);
      34             : }
      35             : static bool Predicate_immZExt3(int64_t Imm) {
      36             : return isUInt<3>(Imm);
      37             : }
      38             : static bool Predicate_immZExt2(int64_t Imm) {
      39             : return isUInt<2>(Imm);
      40             : }
      41             : static bool Predicate_immZExt1(int64_t Imm) {
      42             : return isUInt<1>(Imm);
      43             : }
      44             : static bool Predicate_immZExt8(int64_t Imm) {
      45             : return isUInt<8>(Imm);
      46             : }
      47             : static bool Predicate_immSExtAddiur2(int64_t Imm) {
      48          13 : return Imm == 1 || Imm == -1 ||
      49           6 :                                            ((Imm % 4 == 0) &&
      50           6 :                                             Imm < 28 && Imm > 0);
      51             : }
      52             : static bool Predicate_immSExtAddius5(int64_t Imm) {
      53           7 : return Imm >= -8 && Imm <= 7;
      54             : }
      55           7 : static bool Predicate_immZExtAndi16(int64_t Imm) {
      56          13 : return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
      57           6 :             Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
      58          13 :             Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
      59             : }
      60             : static bool Predicate_immZExt2Shift(int64_t Imm) {
      61           7 : return Imm >= 1 && Imm <= 8;
      62             : }
      63             : 
      64             : 
      65             : // FastEmit functions for ISD::BITCAST.
      66             : 
      67           0 : unsigned fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      68           0 :   if (RetVT.SimpleTy != MVT::f32)
      69             :     return 0;
      70           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
      71           0 :     return fastEmitInst_r(Mips::MTC1_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill);
      72             :   }
      73           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
      74           0 :     return fastEmitInst_r(Mips::MTC1_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
      75             :   }
      76           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
      77           0 :     return fastEmitInst_r(Mips::MTC1, &Mips::FGR32RegClass, Op0, Op0IsKill);
      78             :   }
      79             :   return 0;
      80             : }
      81             : 
      82           0 : unsigned fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      83           0 :   if (RetVT.SimpleTy != MVT::f64)
      84             :     return 0;
      85           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
      86           0 :     return fastEmitInst_r(Mips::DMTC1, &Mips::FGR64RegClass, Op0, Op0IsKill);
      87             :   }
      88             :   return 0;
      89             : }
      90             : 
      91           0 : unsigned fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      92           0 :   if (RetVT.SimpleTy != MVT::i32)
      93             :     return 0;
      94           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
      95           0 :     return fastEmitInst_r(Mips::MFC1_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
      96             :   }
      97           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
      98           0 :     return fastEmitInst_r(Mips::MFC1_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
      99             :   }
     100           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
     101           0 :     return fastEmitInst_r(Mips::MFC1, &Mips::GPR32RegClass, Op0, Op0IsKill);
     102             :   }
     103             :   return 0;
     104             : }
     105             : 
     106           0 : unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     107           0 :   if (RetVT.SimpleTy != MVT::i64)
     108             :     return 0;
     109           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
     110           0 :     return fastEmitInst_r(Mips::DMFC1, &Mips::GPR64RegClass, Op0, Op0IsKill);
     111             :   }
     112             :   return 0;
     113             : }
     114             : 
     115           0 : unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     116           0 :   switch (VT.SimpleTy) {
     117           0 :   case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0, Op0IsKill);
     118           0 :   case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0, Op0IsKill);
     119           0 :   case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0, Op0IsKill);
     120           0 :   case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0, Op0IsKill);
     121             :   default: return 0;
     122             :   }
     123             : }
     124             : 
     125             : // FastEmit functions for ISD::BRIND.
     126             : 
     127           0 : unsigned fastEmit_ISD_BRIND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     128           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     129             :     return 0;
     130           0 :   if ((Subtarget->inMips16Mode())) {
     131           0 :     return fastEmitInst_r(Mips::JrcRx16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill);
     132             :   }
     133           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
     134           0 :     return fastEmitInst_r(Mips::PseudoIndirectBranch_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
     135             :   }
     136           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
     137           0 :     return fastEmitInst_r(Mips::PseudoIndirectBranch_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
     138             :   }
     139           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
     140           0 :     return fastEmitInst_r(Mips::PseudoIndrectHazardBranchR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
     141             :   }
     142           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
     143           0 :     return fastEmitInst_r(Mips::PseudoIndirectBranchR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
     144             :   }
     145           0 :   if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
     146           0 :     return fastEmitInst_r(Mips::PseudoIndirectHazardBranch, &Mips::GPR32RegClass, Op0, Op0IsKill);
     147             :   }
     148           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
     149           0 :     return fastEmitInst_r(Mips::PseudoIndirectBranch, &Mips::GPR32RegClass, Op0, Op0IsKill);
     150             :   }
     151             :   return 0;
     152             : }
     153             : 
     154           0 : unsigned fastEmit_ISD_BRIND_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     155           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     156             :     return 0;
     157           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
     158           0 :     return fastEmitInst_r(Mips::PseudoIndrectHazardBranch64R6, &Mips::GPR64RegClass, Op0, Op0IsKill);
     159             :   }
     160           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
     161           0 :     return fastEmitInst_r(Mips::PseudoIndirectBranch64R6, &Mips::GPR64RegClass, Op0, Op0IsKill);
     162             :   }
     163           0 :   if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
     164           0 :     return fastEmitInst_r(Mips::PseudoIndirectHazardBranch64, &Mips::GPR64RegClass, Op0, Op0IsKill);
     165             :   }
     166           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
     167           0 :     return fastEmitInst_r(Mips::PseudoIndirectBranch64, &Mips::GPR64RegClass, Op0, Op0IsKill);
     168             :   }
     169             :   return 0;
     170             : }
     171             : 
     172           0 : unsigned fastEmit_ISD_BRIND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     173           0 :   switch (VT.SimpleTy) {
     174           0 :   case MVT::i32: return fastEmit_ISD_BRIND_MVT_i32_r(RetVT, Op0, Op0IsKill);
     175           0 :   case MVT::i64: return fastEmit_ISD_BRIND_MVT_i64_r(RetVT, Op0, Op0IsKill);
     176             :   default: return 0;
     177             :   }
     178             : }
     179             : 
     180             : // FastEmit functions for ISD::CTLZ.
     181             : 
     182           0 : unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     183           0 :   if (RetVT.SimpleTy != MVT::i32)
     184             :     return 0;
     185           0 :   if ((Subtarget->inMicroMipsMode())) {
     186           0 :     return fastEmitInst_r(Mips::CLZ_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
     187             :   }
     188           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding())) {
     189           0 :     return fastEmitInst_r(Mips::CLZ_R6, &Mips::GPR32RegClass, Op0, Op0IsKill);
     190             :   }
     191           0 :   if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
     192           0 :     return fastEmitInst_r(Mips::CLZ, &Mips::GPR32RegClass, Op0, Op0IsKill);
     193             :   }
     194             :   return 0;
     195             : }
     196             : 
     197           0 : unsigned fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     198           0 :   if (RetVT.SimpleTy != MVT::i64)
     199             :     return 0;
     200           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
     201           0 :     return fastEmitInst_r(Mips::DCLZ_R6, &Mips::GPR64RegClass, Op0, Op0IsKill);
     202             :   }
     203           0 :   if ((Subtarget->hasMips64()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips64r6())) {
     204           0 :     return fastEmitInst_r(Mips::DCLZ, &Mips::GPR64RegClass, Op0, Op0IsKill);
     205             :   }
     206             :   return 0;
     207             : }
     208             : 
     209           0 : unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     210           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     211             :     return 0;
     212           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     213           0 :     return fastEmitInst_r(Mips::NLZC_B, &Mips::MSA128BRegClass, Op0, Op0IsKill);
     214             :   }
     215             :   return 0;
     216             : }
     217             : 
     218           0 : unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     219           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     220             :     return 0;
     221           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     222           0 :     return fastEmitInst_r(Mips::NLZC_H, &Mips::MSA128HRegClass, Op0, Op0IsKill);
     223             :   }
     224             :   return 0;
     225             : }
     226             : 
     227           0 : unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     228           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     229             :     return 0;
     230           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     231           0 :     return fastEmitInst_r(Mips::NLZC_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     232             :   }
     233             :   return 0;
     234             : }
     235             : 
     236           0 : unsigned fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     237           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     238             :     return 0;
     239           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     240           0 :     return fastEmitInst_r(Mips::NLZC_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     241             :   }
     242             :   return 0;
     243             : }
     244             : 
     245           0 : unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     246           0 :   switch (VT.SimpleTy) {
     247           0 :   case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
     248           0 :   case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0, Op0IsKill);
     249           0 :   case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     250           0 :   case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     251           0 :   case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     252           0 :   case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     253             :   default: return 0;
     254             :   }
     255             : }
     256             : 
     257             : // FastEmit functions for ISD::CTPOP.
     258             : 
     259             : unsigned fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     260           0 :   if (RetVT.SimpleTy != MVT::i32)
     261             :     return 0;
     262           0 :   if ((Subtarget->hasCnMips())) {
     263           0 :     return fastEmitInst_r(Mips::POP, &Mips::GPR32RegClass, Op0, Op0IsKill);
     264             :   }
     265             :   return 0;
     266             : }
     267             : 
     268             : unsigned fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     269           0 :   if (RetVT.SimpleTy != MVT::i64)
     270             :     return 0;
     271           0 :   if ((Subtarget->hasCnMips())) {
     272           0 :     return fastEmitInst_r(Mips::DPOP, &Mips::GPR64RegClass, Op0, Op0IsKill);
     273             :   }
     274             :   return 0;
     275             : }
     276             : 
     277           0 : unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     278           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     279             :     return 0;
     280           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     281           0 :     return fastEmitInst_r(Mips::PCNT_B, &Mips::MSA128BRegClass, Op0, Op0IsKill);
     282             :   }
     283             :   return 0;
     284             : }
     285             : 
     286           0 : unsigned fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     287           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     288             :     return 0;
     289           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     290           0 :     return fastEmitInst_r(Mips::PCNT_H, &Mips::MSA128HRegClass, Op0, Op0IsKill);
     291             :   }
     292             :   return 0;
     293             : }
     294             : 
     295           0 : unsigned fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     296           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     297             :     return 0;
     298           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     299           0 :     return fastEmitInst_r(Mips::PCNT_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     300             :   }
     301             :   return 0;
     302             : }
     303             : 
     304           0 : unsigned fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     305           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     306             :     return 0;
     307           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     308           0 :     return fastEmitInst_r(Mips::PCNT_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     309             :   }
     310             :   return 0;
     311             : }
     312             : 
     313           0 : unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     314           0 :   switch (VT.SimpleTy) {
     315           0 :   case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0, Op0IsKill);
     316           0 :   case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0, Op0IsKill);
     317           0 :   case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     318           0 :   case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     319           0 :   case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     320           0 :   case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     321             :   default: return 0;
     322             :   }
     323             : }
     324             : 
     325             : // FastEmit functions for ISD::FABS.
     326             : 
     327           0 : unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     328           0 :   if (RetVT.SimpleTy != MVT::f32)
     329             :     return 0;
     330           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
     331           0 :     return fastEmitInst_r(Mips::FABS_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
     332             :   }
     333           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
     334           0 :     return fastEmitInst_r(Mips::FABS_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
     335             :   }
     336             :   return 0;
     337             : }
     338             : 
     339           0 : unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     340           0 :   if (RetVT.SimpleTy != MVT::f64)
     341             :     return 0;
     342           0 :   if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
     343           0 :     return fastEmitInst_r(Mips::FABS_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill);
     344             :   }
     345           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
     346           0 :     return fastEmitInst_r(Mips::FABS_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     347             :   }
     348           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
     349           0 :     return fastEmitInst_r(Mips::FABS_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
     350             :   }
     351           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
     352           0 :     return fastEmitInst_r(Mips::FABS_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     353             :   }
     354             :   return 0;
     355             : }
     356             : 
     357           0 : unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     358           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     359             :     return 0;
     360           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     361           0 :     return fastEmitInst_r(Mips::FABS_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     362             :   }
     363             :   return 0;
     364             : }
     365             : 
     366           0 : unsigned fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     367           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     368             :     return 0;
     369           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     370           0 :     return fastEmitInst_r(Mips::FABS_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     371             :   }
     372             :   return 0;
     373             : }
     374             : 
     375           0 : unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     376           0 :   switch (VT.SimpleTy) {
     377           0 :   case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill);
     378           0 :   case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0, Op0IsKill);
     379           0 :   case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     380           0 :   case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     381             :   default: return 0;
     382             :   }
     383             : }
     384             : 
     385             : // FastEmit functions for ISD::FEXP2.
     386             : 
     387           0 : unsigned fastEmit_ISD_FEXP2_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     388           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     389             :     return 0;
     390           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     391           0 :     return fastEmitInst_r(Mips::FEXP2_W_1_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     392             :   }
     393             :   return 0;
     394             : }
     395             : 
     396           0 : unsigned fastEmit_ISD_FEXP2_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     397           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     398             :     return 0;
     399           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     400           0 :     return fastEmitInst_r(Mips::FEXP2_D_1_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     401             :   }
     402             :   return 0;
     403             : }
     404             : 
     405           0 : unsigned fastEmit_ISD_FEXP2_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     406           0 :   switch (VT.SimpleTy) {
     407           0 :   case MVT::v4f32: return fastEmit_ISD_FEXP2_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     408           0 :   case MVT::v2f64: return fastEmit_ISD_FEXP2_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     409             :   default: return 0;
     410             :   }
     411             : }
     412             : 
     413             : // FastEmit functions for ISD::FLOG2.
     414             : 
     415           0 : unsigned fastEmit_ISD_FLOG2_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     416           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     417             :     return 0;
     418           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     419           0 :     return fastEmitInst_r(Mips::FLOG2_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     420             :   }
     421             :   return 0;
     422             : }
     423             : 
     424           0 : unsigned fastEmit_ISD_FLOG2_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     425           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     426             :     return 0;
     427           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     428           0 :     return fastEmitInst_r(Mips::FLOG2_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     429             :   }
     430             :   return 0;
     431             : }
     432             : 
     433           0 : unsigned fastEmit_ISD_FLOG2_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     434           0 :   switch (VT.SimpleTy) {
     435           0 :   case MVT::v4f32: return fastEmit_ISD_FLOG2_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     436           0 :   case MVT::v2f64: return fastEmit_ISD_FLOG2_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     437             :   default: return 0;
     438             :   }
     439             : }
     440             : 
     441             : // FastEmit functions for ISD::FNEG.
     442             : 
     443           0 : unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     444           0 :   if (RetVT.SimpleTy != MVT::f32)
     445             :     return 0;
     446           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
     447           0 :     return fastEmitInst_r(Mips::FNEG_S_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill);
     448             :   }
     449           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
     450           0 :     return fastEmitInst_r(Mips::FNEG_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
     451             :   }
     452           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
     453           0 :     return fastEmitInst_r(Mips::FNEG_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
     454             :   }
     455             :   return 0;
     456             : }
     457             : 
     458           0 : unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     459           0 :   if (RetVT.SimpleTy != MVT::f64)
     460             :     return 0;
     461           0 :   if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
     462           0 :     return fastEmitInst_r(Mips::FNEG_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill);
     463             :   }
     464           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
     465           0 :     return fastEmitInst_r(Mips::FNEG_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     466             :   }
     467           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
     468           0 :     return fastEmitInst_r(Mips::FNEG_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
     469             :   }
     470           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
     471           0 :     return fastEmitInst_r(Mips::FNEG_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     472             :   }
     473             :   return 0;
     474             : }
     475             : 
     476           0 : unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     477           0 :   switch (VT.SimpleTy) {
     478           0 :   case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill);
     479           0 :   case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0, Op0IsKill);
     480             :   default: return 0;
     481             :   }
     482             : }
     483             : 
     484             : // FastEmit functions for ISD::FP_EXTEND.
     485             : 
     486             : unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
     487           0 :   if ((Subtarget->hasMSA())) {
     488           0 :     return fastEmitInst_r(Mips::MSA_FP_EXTEND_W_PSEUDO, &Mips::FGR32RegClass, Op0, Op0IsKill);
     489             :   }
     490             :   return 0;
     491             : }
     492             : 
     493             : unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
     494           0 :   if ((Subtarget->hasMSA())) {
     495           0 :     return fastEmitInst_r(Mips::MSA_FP_EXTEND_D_PSEUDO, &Mips::FGR64RegClass, Op0, Op0IsKill);
     496             :   }
     497             :   return 0;
     498             : }
     499             : 
     500           0 : unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     501           0 : switch (RetVT.SimpleTy) {
     502           0 :   case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(Op0, Op0IsKill);
     503           0 :   case MVT::f64: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(Op0, Op0IsKill);
     504             :   default: return 0;
     505             : }
     506             : }
     507             : 
     508           0 : unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     509           0 :   if (RetVT.SimpleTy != MVT::f64)
     510             :     return 0;
     511           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit())) {
     512           0 :     return fastEmitInst_r(Mips::CVT_D32_S_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     513             :   }
     514           0 :   if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())) {
     515           0 :     return fastEmitInst_r(Mips::CVT_D64_S_MM, &Mips::FGR64RegClass, Op0, Op0IsKill);
     516             :   }
     517           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
     518           0 :     return fastEmitInst_r(Mips::CVT_D64_S, &Mips::FGR64RegClass, Op0, Op0IsKill);
     519             :   }
     520           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
     521           0 :     return fastEmitInst_r(Mips::CVT_D32_S, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     522             :   }
     523             :   return 0;
     524             : }
     525             : 
     526           0 : unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     527           0 :   switch (VT.SimpleTy) {
     528           0 :   case MVT::f16: return fastEmit_ISD_FP_EXTEND_MVT_f16_r(RetVT, Op0, Op0IsKill);
     529           0 :   case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0, Op0IsKill);
     530             :   default: return 0;
     531             :   }
     532             : }
     533             : 
     534             : // FastEmit functions for ISD::FP_ROUND.
     535             : 
     536             : unsigned fastEmit_ISD_FP_ROUND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     537           0 :   if (RetVT.SimpleTy != MVT::f16)
     538             :     return 0;
     539           0 :   if ((Subtarget->hasMSA())) {
     540           0 :     return fastEmitInst_r(Mips::MSA_FP_ROUND_W_PSEUDO, &Mips::MSA128F16RegClass, Op0, Op0IsKill);
     541             :   }
     542             :   return 0;
     543             : }
     544             : 
     545             : unsigned fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(unsigned Op0, bool Op0IsKill) {
     546           0 :   if ((Subtarget->hasMSA())) {
     547           0 :     return fastEmitInst_r(Mips::MSA_FP_ROUND_D_PSEUDO, &Mips::MSA128F16RegClass, Op0, Op0IsKill);
     548             :   }
     549             :   return 0;
     550             : }
     551             : 
     552           0 : unsigned fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
     553           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit())) {
     554           0 :     return fastEmitInst_r(Mips::CVT_S_D32_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
     555             :   }
     556           0 :   if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())) {
     557           0 :     return fastEmitInst_r(Mips::CVT_S_D64_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
     558             :   }
     559           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
     560           0 :     return fastEmitInst_r(Mips::CVT_S_D64, &Mips::FGR32RegClass, Op0, Op0IsKill);
     561             :   }
     562           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
     563           0 :     return fastEmitInst_r(Mips::CVT_S_D32, &Mips::FGR32RegClass, Op0, Op0IsKill);
     564             :   }
     565             :   return 0;
     566             : }
     567             : 
     568           0 : unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     569           0 : switch (RetVT.SimpleTy) {
     570           0 :   case MVT::f16: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(Op0, Op0IsKill);
     571           0 :   case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(Op0, Op0IsKill);
     572             :   default: return 0;
     573             : }
     574             : }
     575             : 
     576           0 : unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     577           0 :   switch (VT.SimpleTy) {
     578           0 :   case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f32_r(RetVT, Op0, Op0IsKill);
     579           0 :   case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
     580             :   default: return 0;
     581             :   }
     582             : }
     583             : 
     584             : // FastEmit functions for ISD::FP_TO_SINT.
     585             : 
     586           0 : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     587           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     588             :     return 0;
     589           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     590           0 :     return fastEmitInst_r(Mips::FTRUNC_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     591             :   }
     592             :   return 0;
     593             : }
     594             : 
     595           0 : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     596           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     597             :     return 0;
     598           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     599           0 :     return fastEmitInst_r(Mips::FTRUNC_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     600             :   }
     601             :   return 0;
     602             : }
     603             : 
     604           4 : unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     605           4 :   switch (VT.SimpleTy) {
     606           0 :   case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     607           0 :   case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     608             :   default: return 0;
     609             :   }
     610             : }
     611             : 
     612             : // FastEmit functions for ISD::FP_TO_UINT.
     613             : 
     614           0 : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     615           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     616             :     return 0;
     617           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     618           0 :     return fastEmitInst_r(Mips::FTRUNC_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     619             :   }
     620             :   return 0;
     621             : }
     622             : 
     623           0 : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     624           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     625             :     return 0;
     626           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     627           0 :     return fastEmitInst_r(Mips::FTRUNC_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     628             :   }
     629             :   return 0;
     630             : }
     631             : 
     632           0 : unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     633           0 :   switch (VT.SimpleTy) {
     634           0 :   case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     635           0 :   case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     636             :   default: return 0;
     637             :   }
     638             : }
     639             : 
     640             : // FastEmit functions for ISD::FRINT.
     641             : 
     642           0 : unsigned fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     643           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     644             :     return 0;
     645           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     646           0 :     return fastEmitInst_r(Mips::FRINT_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     647             :   }
     648             :   return 0;
     649             : }
     650             : 
     651           0 : unsigned fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     652           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     653             :     return 0;
     654           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     655           0 :     return fastEmitInst_r(Mips::FRINT_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     656             :   }
     657             :   return 0;
     658             : }
     659             : 
     660           0 : unsigned fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     661           0 :   switch (VT.SimpleTy) {
     662           0 :   case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     663           0 :   case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     664             :   default: return 0;
     665             :   }
     666             : }
     667             : 
     668             : // FastEmit functions for ISD::FSQRT.
     669             : 
     670           0 : unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     671           0 :   if (RetVT.SimpleTy != MVT::f32)
     672             :     return 0;
     673           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
     674           0 :     return fastEmitInst_r(Mips::FSQRT_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
     675             :   }
     676           0 :   if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
     677           0 :     return fastEmitInst_r(Mips::FSQRT_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
     678             :   }
     679             :   return 0;
     680             : }
     681             : 
     682           0 : unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     683           0 :   if (RetVT.SimpleTy != MVT::f64)
     684             :     return 0;
     685           0 :   if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
     686           0 :     return fastEmitInst_r(Mips::FSQRT_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill);
     687             :   }
     688           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
     689           0 :     return fastEmitInst_r(Mips::FSQRT_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     690             :   }
     691           0 :   if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
     692           0 :     return fastEmitInst_r(Mips::FSQRT_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
     693             :   }
     694           0 :   if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
     695           0 :     return fastEmitInst_r(Mips::FSQRT_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     696             :   }
     697             :   return 0;
     698             : }
     699             : 
     700           0 : unsigned fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     701           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     702             :     return 0;
     703           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     704           0 :     return fastEmitInst_r(Mips::FSQRT_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     705             :   }
     706             :   return 0;
     707             : }
     708             : 
     709           0 : unsigned fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     710           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     711             :     return 0;
     712           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     713           0 :     return fastEmitInst_r(Mips::FSQRT_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     714             :   }
     715             :   return 0;
     716             : }
     717             : 
     718           0 : unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     719           0 :   switch (VT.SimpleTy) {
     720           0 :   case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill);
     721           0 :   case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0, Op0IsKill);
     722           0 :   case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     723           0 :   case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     724             :   default: return 0;
     725             :   }
     726             : }
     727             : 
     728             : // FastEmit functions for ISD::SIGN_EXTEND.
     729             : 
     730             : unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     731           0 :   if (RetVT.SimpleTy != MVT::i64)
     732             :     return 0;
     733           0 :   if ((Subtarget->hasStandardEncoding())) {
     734           0 :     return fastEmitInst_r(Mips::SLL64_32, &Mips::GPR64RegClass, Op0, Op0IsKill);
     735             :   }
     736             :   return 0;
     737             : }
     738             : 
     739           0 : unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     740           0 :   switch (VT.SimpleTy) {
     741           0 :   case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0, Op0IsKill);
     742             :   default: return 0;
     743             :   }
     744             : }
     745             : 
     746             : // FastEmit functions for ISD::SINT_TO_FP.
     747             : 
     748             : unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
     749           0 :   if ((Subtarget->hasStandardEncoding())) {
     750           0 :     return fastEmitInst_r(Mips::PseudoCVT_S_W, &Mips::FGR32RegClass, Op0, Op0IsKill);
     751             :   }
     752             :   return 0;
     753             : }
     754             : 
     755           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
     756           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
     757           0 :     return fastEmitInst_r(Mips::PseudoCVT_D64_W, &Mips::FGR64RegClass, Op0, Op0IsKill);
     758             :   }
     759           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit())) {
     760           0 :     return fastEmitInst_r(Mips::PseudoCVT_D32_W, &Mips::AFGR64RegClass, Op0, Op0IsKill);
     761             :   }
     762             :   return 0;
     763             : }
     764             : 
     765           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     766           0 : switch (RetVT.SimpleTy) {
     767           0 :   case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0, Op0IsKill);
     768           0 :   case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0, Op0IsKill);
     769             :   default: return 0;
     770             : }
     771             : }
     772             : 
     773           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     774           0 :   if (RetVT.SimpleTy != MVT::f64)
     775             :     return 0;
     776           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
     777           0 :     return fastEmitInst_r(Mips::PseudoCVT_D64_L, &Mips::FGR64RegClass, Op0, Op0IsKill);
     778             :   }
     779             :   return 0;
     780             : }
     781             : 
     782           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     783           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     784             :     return 0;
     785           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     786           0 :     return fastEmitInst_r(Mips::FFINT_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     787             :   }
     788             :   return 0;
     789             : }
     790             : 
     791           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     792           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     793             :     return 0;
     794           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     795           0 :     return fastEmitInst_r(Mips::FFINT_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     796             :   }
     797             :   return 0;
     798             : }
     799             : 
     800           0 : unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     801           0 :   switch (VT.SimpleTy) {
     802           0 :   case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0, Op0IsKill);
     803           0 :   case MVT::i64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_r(RetVT, Op0, Op0IsKill);
     804           0 :   case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     805           0 :   case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     806             :   default: return 0;
     807             :   }
     808             : }
     809             : 
     810             : // FastEmit functions for ISD::UINT_TO_FP.
     811             : 
     812           0 : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     813           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     814             :     return 0;
     815           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     816           0 :     return fastEmitInst_r(Mips::FFINT_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
     817             :   }
     818             :   return 0;
     819             : }
     820             : 
     821           0 : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     822           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     823             :     return 0;
     824           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
     825           0 :     return fastEmitInst_r(Mips::FFINT_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
     826             :   }
     827             :   return 0;
     828             : }
     829             : 
     830           0 : unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     831           0 :   switch (VT.SimpleTy) {
     832           0 :   case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     833           0 :   case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     834             :   default: return 0;
     835             :   }
     836             : }
     837             : 
     838             : // FastEmit functions for MipsISD::JmpLink.
     839             : 
     840           0 : unsigned fastEmit_MipsISD_JmpLink_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     841           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     842             :     return 0;
     843           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
     844           0 :     return fastEmitInst_r(Mips::JALR16_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
     845             :   }
     846           0 :   if ((Subtarget->inMips16Mode())) {
     847           0 :     return fastEmitInst_r(Mips::JumpLinkReg16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill);
     848             :   }
     849           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (Subtarget->useIndirectJumpsHazard())) {
     850           0 :     return fastEmitInst_r(Mips::JALRHBPseudo, &Mips::GPR32RegClass, Op0, Op0IsKill);
     851             :   }
     852           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode())) {
     853           0 :     return fastEmitInst_r(Mips::JALRPseudo, &Mips::GPR32RegClass, Op0, Op0IsKill);
     854             :   }
     855             :   return 0;
     856             : }
     857             : 
     858           0 : unsigned fastEmit_MipsISD_JmpLink_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     859           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     860             :     return 0;
     861           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->useIndirectJumpsHazard())) {
     862           0 :     return fastEmitInst_r(Mips::JALRHB64Pseudo, &Mips::GPR64RegClass, Op0, Op0IsKill);
     863             :   }
     864           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard())) {
     865           0 :     return fastEmitInst_r(Mips::JALR64Pseudo, &Mips::GPR64RegClass, Op0, Op0IsKill);
     866             :   }
     867             :   return 0;
     868             : }
     869             : 
     870           0 : unsigned fastEmit_MipsISD_JmpLink_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     871           0 :   switch (VT.SimpleTy) {
     872           0 :   case MVT::i32: return fastEmit_MipsISD_JmpLink_MVT_i32_r(RetVT, Op0, Op0IsKill);
     873           0 :   case MVT::i64: return fastEmit_MipsISD_JmpLink_MVT_i64_r(RetVT, Op0, Op0IsKill);
     874             :   default: return 0;
     875             :   }
     876             : }
     877             : 
     878             : // FastEmit functions for MipsISD::MFHI.
     879             : 
     880           0 : unsigned fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(unsigned Op0, bool Op0IsKill) {
     881           0 :   if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
     882           0 :     return fastEmitInst_r(Mips::MFHI_DSP_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
     883             :   }
     884           0 :   if ((Subtarget->hasDSP())) {
     885           0 :     return fastEmitInst_r(Mips::MFHI_DSP, &Mips::GPR32RegClass, Op0, Op0IsKill);
     886             :   }
     887           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
     888           0 :     return fastEmitInst_r(Mips::PseudoMFHI, &Mips::GPR32RegClass, Op0, Op0IsKill);
     889             :   }
     890             :   return 0;
     891             : }
     892             : 
     893           0 : unsigned fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(unsigned Op0, bool Op0IsKill) {
     894           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
     895           0 :     return fastEmitInst_r(Mips::PseudoMFHI64, &Mips::GPR64RegClass, Op0, Op0IsKill);
     896             :   }
     897             :   return 0;
     898             : }
     899             : 
     900           0 : unsigned fastEmit_MipsISD_MFHI_MVT_Untyped_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     901           0 : switch (RetVT.SimpleTy) {
     902           0 :   case MVT::i32: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(Op0, Op0IsKill);
     903           0 :   case MVT::i64: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(Op0, Op0IsKill);
     904             :   default: return 0;
     905             : }
     906             : }
     907             : 
     908             : unsigned fastEmit_MipsISD_MFHI_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     909           0 :   switch (VT.SimpleTy) {
     910           0 :   case MVT::Untyped: return fastEmit_MipsISD_MFHI_MVT_Untyped_r(RetVT, Op0, Op0IsKill);
     911             :   default: return 0;
     912             :   }
     913             : }
     914             : 
     915             : // FastEmit functions for MipsISD::MFLO.
     916             : 
     917           0 : unsigned fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(unsigned Op0, bool Op0IsKill) {
     918           0 :   if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
     919           0 :     return fastEmitInst_r(Mips::MFLO_DSP_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
     920             :   }
     921           0 :   if ((Subtarget->hasDSP())) {
     922           0 :     return fastEmitInst_r(Mips::MFLO_DSP, &Mips::GPR32RegClass, Op0, Op0IsKill);
     923             :   }
     924           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
     925           0 :     return fastEmitInst_r(Mips::PseudoMFLO, &Mips::GPR32RegClass, Op0, Op0IsKill);
     926             :   }
     927             :   return 0;
     928             : }
     929             : 
     930           0 : unsigned fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(unsigned Op0, bool Op0IsKill) {
     931           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
     932           0 :     return fastEmitInst_r(Mips::PseudoMFLO64, &Mips::GPR64RegClass, Op0, Op0IsKill);
     933             :   }
     934             :   return 0;
     935             : }
     936             : 
     937           0 : unsigned fastEmit_MipsISD_MFLO_MVT_Untyped_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     938           0 : switch (RetVT.SimpleTy) {
     939           0 :   case MVT::i32: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(Op0, Op0IsKill);
     940           0 :   case MVT::i64: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(Op0, Op0IsKill);
     941             :   default: return 0;
     942             : }
     943             : }
     944             : 
     945             : unsigned fastEmit_MipsISD_MFLO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     946           0 :   switch (VT.SimpleTy) {
     947           0 :   case MVT::Untyped: return fastEmit_MipsISD_MFLO_MVT_Untyped_r(RetVT, Op0, Op0IsKill);
     948             :   default: return 0;
     949             :   }
     950             : }
     951             : 
     952             : // FastEmit functions for MipsISD::MTC1_D64.
     953             : 
     954           0 : unsigned fastEmit_MipsISD_MTC1_D64_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     955           0 :   if (RetVT.SimpleTy != MVT::f64)
     956             :     return 0;
     957           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
     958           0 :     return fastEmitInst_r(Mips::MTC1_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
     959             :   }
     960             :   return 0;
     961             : }
     962             : 
     963             : unsigned fastEmit_MipsISD_MTC1_D64_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     964           0 :   switch (VT.SimpleTy) {
     965           0 :   case MVT::i32: return fastEmit_MipsISD_MTC1_D64_MVT_i32_r(RetVT, Op0, Op0IsKill);
     966             :   default: return 0;
     967             :   }
     968             : }
     969             : 
     970             : // FastEmit functions for MipsISD::TailCall.
     971             : 
     972           0 : unsigned fastEmit_MipsISD_TailCall_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     973           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     974             :     return 0;
     975           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
     976           0 :     return fastEmitInst_r(Mips::TAILCALLREG_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
     977             :   }
     978           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
     979           0 :     return fastEmitInst_r(Mips::TAILCALLREG_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
     980             :   }
     981           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
     982           0 :     return fastEmitInst_r(Mips::TAILCALLHBR6REG, &Mips::GPR32RegClass, Op0, Op0IsKill);
     983             :   }
     984           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
     985           0 :     return fastEmitInst_r(Mips::TAILCALLR6REG, &Mips::GPR32RegClass, Op0, Op0IsKill);
     986             :   }
     987           0 :   if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
     988           0 :     return fastEmitInst_r(Mips::TAILCALLREGHB, &Mips::GPR32RegClass, Op0, Op0IsKill);
     989             :   }
     990           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
     991           0 :     return fastEmitInst_r(Mips::TAILCALLREG, &Mips::GPR32RegClass, Op0, Op0IsKill);
     992             :   }
     993             :   return 0;
     994             : }
     995             : 
     996           0 : unsigned fastEmit_MipsISD_TailCall_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     997           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     998             :     return 0;
     999           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
    1000           0 :     return fastEmitInst_r(Mips::TAILCALLHB64R6REG, &Mips::GPR64RegClass, Op0, Op0IsKill);
    1001             :   }
    1002           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
    1003           0 :     return fastEmitInst_r(Mips::TAILCALL64R6REG, &Mips::GPR64RegClass, Op0, Op0IsKill);
    1004             :   }
    1005           0 :   if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
    1006           0 :     return fastEmitInst_r(Mips::TAILCALLREGHB64, &Mips::GPR64RegClass, Op0, Op0IsKill);
    1007             :   }
    1008           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    1009           0 :     return fastEmitInst_r(Mips::TAILCALLREG64, &Mips::GPR64RegClass, Op0, Op0IsKill);
    1010             :   }
    1011             :   return 0;
    1012             : }
    1013             : 
    1014           0 : unsigned fastEmit_MipsISD_TailCall_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1015           0 :   switch (VT.SimpleTy) {
    1016           0 :   case MVT::i32: return fastEmit_MipsISD_TailCall_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1017           0 :   case MVT::i64: return fastEmit_MipsISD_TailCall_MVT_i64_r(RetVT, Op0, Op0IsKill);
    1018             :   default: return 0;
    1019             :   }
    1020             : }
    1021             : 
    1022             : // FastEmit functions for MipsISD::TruncIntFP.
    1023             : 
    1024             : unsigned fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
    1025           0 :   if ((Subtarget->hasStandardEncoding())) {
    1026           0 :     return fastEmitInst_r(Mips::TRUNC_W_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
    1027             :   }
    1028             :   return 0;
    1029             : }
    1030             : 
    1031           0 : unsigned fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
    1032           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
    1033           0 :     return fastEmitInst_r(Mips::TRUNC_L_S, &Mips::FGR64RegClass, Op0, Op0IsKill);
    1034             :   }
    1035             :   return 0;
    1036             : }
    1037             : 
    1038           0 : unsigned fastEmit_MipsISD_TruncIntFP_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1039           0 : switch (RetVT.SimpleTy) {
    1040           0 :   case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(Op0, Op0IsKill);
    1041           0 :   case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(Op0, Op0IsKill);
    1042             :   default: return 0;
    1043             : }
    1044             : }
    1045             : 
    1046           0 : unsigned fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
    1047           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
    1048           0 :     return fastEmitInst_r(Mips::TRUNC_W_D64, &Mips::FGR32RegClass, Op0, Op0IsKill);
    1049             :   }
    1050           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit())) {
    1051           0 :     return fastEmitInst_r(Mips::TRUNC_W_D32, &Mips::FGR32RegClass, Op0, Op0IsKill);
    1052             :   }
    1053             :   return 0;
    1054             : }
    1055             : 
    1056           0 : unsigned fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
    1057           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
    1058           0 :     return fastEmitInst_r(Mips::TRUNC_L_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
    1059             :   }
    1060             :   return 0;
    1061             : }
    1062             : 
    1063           0 : unsigned fastEmit_MipsISD_TruncIntFP_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1064           0 : switch (RetVT.SimpleTy) {
    1065           0 :   case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(Op0, Op0IsKill);
    1066           0 :   case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(Op0, Op0IsKill);
    1067             :   default: return 0;
    1068             : }
    1069             : }
    1070             : 
    1071           0 : unsigned fastEmit_MipsISD_TruncIntFP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1072           0 :   switch (VT.SimpleTy) {
    1073           0 :   case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1074           0 :   case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1075             :   default: return 0;
    1076             :   }
    1077             : }
    1078             : 
    1079             : // FastEmit functions for MipsISD::VALL_NONZERO.
    1080             : 
    1081             : unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1082           0 :   if (RetVT.SimpleTy != MVT::i32)
    1083             :     return 0;
    1084           0 :   return fastEmitInst_r(Mips::SNZ_B_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1085             : }
    1086             : 
    1087             : unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1088           0 :   if (RetVT.SimpleTy != MVT::i32)
    1089             :     return 0;
    1090           0 :   return fastEmitInst_r(Mips::SNZ_H_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1091             : }
    1092             : 
    1093             : unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1094           0 :   if (RetVT.SimpleTy != MVT::i32)
    1095             :     return 0;
    1096           0 :   return fastEmitInst_r(Mips::SNZ_W_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1097             : }
    1098             : 
    1099             : unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1100           0 :   if (RetVT.SimpleTy != MVT::i32)
    1101             :     return 0;
    1102           0 :   return fastEmitInst_r(Mips::SNZ_D_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1103             : }
    1104             : 
    1105           0 : unsigned fastEmit_MipsISD_VALL_NONZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1106           0 :   switch (VT.SimpleTy) {
    1107           0 :   case MVT::v16i8: return fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1108           0 :   case MVT::v8i16: return fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    1109           0 :   case MVT::v4i32: return fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    1110           0 :   case MVT::v2i64: return fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
    1111             :   default: return 0;
    1112             :   }
    1113             : }
    1114             : 
    1115             : // FastEmit functions for MipsISD::VALL_ZERO.
    1116             : 
    1117             : unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1118           0 :   if (RetVT.SimpleTy != MVT::i32)
    1119             :     return 0;
    1120           0 :   return fastEmitInst_r(Mips::SZ_B_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1121             : }
    1122             : 
    1123             : unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1124           0 :   if (RetVT.SimpleTy != MVT::i32)
    1125             :     return 0;
    1126           0 :   return fastEmitInst_r(Mips::SZ_H_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1127             : }
    1128             : 
    1129             : unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1130           0 :   if (RetVT.SimpleTy != MVT::i32)
    1131             :     return 0;
    1132           0 :   return fastEmitInst_r(Mips::SZ_W_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1133             : }
    1134             : 
    1135             : unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1136           0 :   if (RetVT.SimpleTy != MVT::i32)
    1137             :     return 0;
    1138           0 :   return fastEmitInst_r(Mips::SZ_D_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1139             : }
    1140             : 
    1141           0 : unsigned fastEmit_MipsISD_VALL_ZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1142           0 :   switch (VT.SimpleTy) {
    1143           0 :   case MVT::v16i8: return fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1144           0 :   case MVT::v8i16: return fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    1145           0 :   case MVT::v4i32: return fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    1146           0 :   case MVT::v2i64: return fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
    1147             :   default: return 0;
    1148             :   }
    1149             : }
    1150             : 
    1151             : // FastEmit functions for MipsISD::VANY_NONZERO.
    1152             : 
    1153             : unsigned fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1154           0 :   if (RetVT.SimpleTy != MVT::i32)
    1155             :     return 0;
    1156           0 :   return fastEmitInst_r(Mips::SNZ_V_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1157             : }
    1158             : 
    1159             : unsigned fastEmit_MipsISD_VANY_NONZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1160           0 :   switch (VT.SimpleTy) {
    1161           0 :   case MVT::v16i8: return fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1162             :   default: return 0;
    1163             :   }
    1164             : }
    1165             : 
    1166             : // FastEmit functions for MipsISD::VANY_ZERO.
    1167             : 
    1168             : unsigned fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1169           0 :   if (RetVT.SimpleTy != MVT::i32)
    1170             :     return 0;
    1171           0 :   return fastEmitInst_r(Mips::SZ_V_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
    1172             : }
    1173             : 
    1174             : unsigned fastEmit_MipsISD_VANY_ZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1175           0 :   switch (VT.SimpleTy) {
    1176           0 :   case MVT::v16i8: return fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1177             :   default: return 0;
    1178             :   }
    1179             : }
    1180             : 
    1181             : // Top-level FastEmit function.
    1182             : 
    1183           4 : unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill) override {
    1184           4 :   switch (Opcode) {
    1185           0 :   case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0, Op0IsKill);
    1186           0 :   case ISD::BRIND: return fastEmit_ISD_BRIND_r(VT, RetVT, Op0, Op0IsKill);
    1187           0 :   case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill);
    1188           0 :   case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill);
    1189           0 :   case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill);
    1190           0 :   case ISD::FEXP2: return fastEmit_ISD_FEXP2_r(VT, RetVT, Op0, Op0IsKill);
    1191           0 :   case ISD::FLOG2: return fastEmit_ISD_FLOG2_r(VT, RetVT, Op0, Op0IsKill);
    1192           0 :   case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill);
    1193           0 :   case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
    1194           0 :   case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill);
    1195           4 :   case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill);
    1196           0 :   case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill);
    1197           0 :   case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0, Op0IsKill);
    1198           0 :   case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill);
    1199           0 :   case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
    1200           0 :   case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill);
    1201           0 :   case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill);
    1202           0 :   case MipsISD::JmpLink: return fastEmit_MipsISD_JmpLink_r(VT, RetVT, Op0, Op0IsKill);
    1203           0 :   case MipsISD::MFHI: return fastEmit_MipsISD_MFHI_r(VT, RetVT, Op0, Op0IsKill);
    1204           0 :   case MipsISD::MFLO: return fastEmit_MipsISD_MFLO_r(VT, RetVT, Op0, Op0IsKill);
    1205           0 :   case MipsISD::MTC1_D64: return fastEmit_MipsISD_MTC1_D64_r(VT, RetVT, Op0, Op0IsKill);
    1206           0 :   case MipsISD::TailCall: return fastEmit_MipsISD_TailCall_r(VT, RetVT, Op0, Op0IsKill);
    1207           0 :   case MipsISD::TruncIntFP: return fastEmit_MipsISD_TruncIntFP_r(VT, RetVT, Op0, Op0IsKill);
    1208           0 :   case MipsISD::VALL_NONZERO: return fastEmit_MipsISD_VALL_NONZERO_r(VT, RetVT, Op0, Op0IsKill);
    1209           0 :   case MipsISD::VALL_ZERO: return fastEmit_MipsISD_VALL_ZERO_r(VT, RetVT, Op0, Op0IsKill);
    1210           0 :   case MipsISD::VANY_NONZERO: return fastEmit_MipsISD_VANY_NONZERO_r(VT, RetVT, Op0, Op0IsKill);
    1211           0 :   case MipsISD::VANY_ZERO: return fastEmit_MipsISD_VANY_ZERO_r(VT, RetVT, Op0, Op0IsKill);
    1212             :   default: return 0;
    1213             :   }
    1214             : }
    1215             : 
    1216             : // FastEmit functions for ISD::ADD.
    1217             : 
    1218           6 : unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1219           6 :   if (RetVT.SimpleTy != MVT::i32)
    1220             :     return 0;
    1221           6 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
    1222           0 :     return fastEmitInst_rr(Mips::ADDU16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1223             :   }
    1224           6 :   if ((Subtarget->inMips16Mode())) {
    1225           0 :     return fastEmitInst_rr(Mips::AdduRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1226             :   }
    1227           6 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
    1228           0 :     return fastEmitInst_rr(Mips::ADDu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1229             :   }
    1230           6 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1231          12 :     return fastEmitInst_rr(Mips::ADDu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1232             :   }
    1233             :   return 0;
    1234             : }
    1235             : 
    1236           0 : unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1237           0 :   if (RetVT.SimpleTy != MVT::i64)
    1238             :     return 0;
    1239           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1240           0 :     return fastEmitInst_rr(Mips::DADDu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1241             :   }
    1242             :   return 0;
    1243             : }
    1244             : 
    1245             : unsigned fastEmit_ISD_ADD_MVT_v4i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1246           0 :   if (RetVT.SimpleTy != MVT::v4i8)
    1247             :     return 0;
    1248           0 :   if ((Subtarget->hasDSP())) {
    1249             :     return fastEmitInst_rr(Mips::ADDU_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1250             :   }
    1251             :   return 0;
    1252             : }
    1253             : 
    1254           0 : unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1255           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1256             :     return 0;
    1257           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1258           0 :     return fastEmitInst_rr(Mips::ADDV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1259             :   }
    1260             :   return 0;
    1261             : }
    1262             : 
    1263             : unsigned fastEmit_ISD_ADD_MVT_v2i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1264           0 :   if (RetVT.SimpleTy != MVT::v2i16)
    1265             :     return 0;
    1266           0 :   if ((Subtarget->hasDSP())) {
    1267             :     return fastEmitInst_rr(Mips::ADDQ_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1268             :   }
    1269             :   return 0;
    1270             : }
    1271             : 
    1272           0 : unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1273           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1274             :     return 0;
    1275           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1276           0 :     return fastEmitInst_rr(Mips::ADDV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1277             :   }
    1278             :   return 0;
    1279             : }
    1280             : 
    1281           0 : unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1282           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1283             :     return 0;
    1284           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1285           0 :     return fastEmitInst_rr(Mips::ADDV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1286             :   }
    1287             :   return 0;
    1288             : }
    1289             : 
    1290           0 : unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1291           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1292             :     return 0;
    1293           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1294           0 :     return fastEmitInst_rr(Mips::ADDV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1295             :   }
    1296             :   return 0;
    1297             : }
    1298             : 
    1299           6 : unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1300           6 :   switch (VT.SimpleTy) {
    1301           6 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1302           0 :   case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1303           0 :   case MVT::v4i8: return fastEmit_ISD_ADD_MVT_v4i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1304           0 :   case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1305           0 :   case MVT::v2i16: return fastEmit_ISD_ADD_MVT_v2i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1306           0 :   case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1307           0 :   case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1308           0 :   case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1309             :   default: return 0;
    1310             :   }
    1311             : }
    1312             : 
    1313             : // FastEmit functions for ISD::ADDC.
    1314             : 
    1315           0 : unsigned fastEmit_ISD_ADDC_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1316           0 :   if (RetVT.SimpleTy != MVT::i32)
    1317             :     return 0;
    1318           0 :   if ((Subtarget->hasDSP())) {
    1319           0 :     return fastEmitInst_rr(Mips::ADDSC, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1320             :   }
    1321           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP())) {
    1322           0 :     return fastEmitInst_rr(Mips::ADDu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1323             :   }
    1324             :   return 0;
    1325             : }
    1326             : 
    1327           0 : unsigned fastEmit_ISD_ADDC_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1328           0 :   if (RetVT.SimpleTy != MVT::i64)
    1329             :     return 0;
    1330           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->inMicroMipsMode())) {
    1331           0 :     return fastEmitInst_rr(Mips::DADDu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1332             :   }
    1333             :   return 0;
    1334             : }
    1335             : 
    1336           0 : unsigned fastEmit_ISD_ADDC_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1337           0 :   switch (VT.SimpleTy) {
    1338           0 :   case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1339           0 :   case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1340             :   default: return 0;
    1341             :   }
    1342             : }
    1343             : 
    1344             : // FastEmit functions for ISD::ADDE.
    1345             : 
    1346             : unsigned fastEmit_ISD_ADDE_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1347           0 :   if (RetVT.SimpleTy != MVT::i32)
    1348             :     return 0;
    1349           0 :   if ((Subtarget->hasDSP())) {
    1350             :     return fastEmitInst_rr(Mips::ADDWC, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1351             :   }
    1352             :   return 0;
    1353             : }
    1354             : 
    1355           0 : unsigned fastEmit_ISD_ADDE_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1356           0 :   switch (VT.SimpleTy) {
    1357           0 :   case MVT::i32: return fastEmit_ISD_ADDE_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1358             :   default: return 0;
    1359             :   }
    1360             : }
    1361             : 
    1362             : // FastEmit functions for ISD::AND.
    1363             : 
    1364           5 : unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1365           5 :   if (RetVT.SimpleTy != MVT::i32)
    1366             :     return 0;
    1367           5 :   if ((Subtarget->inMips16Mode())) {
    1368           0 :     return fastEmitInst_rr(Mips::AndRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1369             :   }
    1370           5 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
    1371           0 :     return fastEmitInst_rr(Mips::AND_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1372             :   }
    1373           5 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
    1374           0 :     return fastEmitInst_rr(Mips::AND_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1375             :   }
    1376           5 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1377          10 :     return fastEmitInst_rr(Mips::AND, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1378             :   }
    1379             :   return 0;
    1380             : }
    1381             : 
    1382           0 : unsigned fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1383           0 :   if (RetVT.SimpleTy != MVT::i64)
    1384             :     return 0;
    1385           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())) {
    1386           0 :     return fastEmitInst_rr(Mips::AND64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1387             :   }
    1388             :   return 0;
    1389             : }
    1390             : 
    1391           0 : unsigned fastEmit_ISD_AND_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1392           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1393             :     return 0;
    1394           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1395           0 :     return fastEmitInst_rr(Mips::AND_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1396             :   }
    1397             :   return 0;
    1398             : }
    1399             : 
    1400           0 : unsigned fastEmit_ISD_AND_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1401           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1402             :     return 0;
    1403           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1404           0 :     return fastEmitInst_rr(Mips::AND_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1405             :   }
    1406             :   return 0;
    1407             : }
    1408             : 
    1409           0 : unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1410           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1411             :     return 0;
    1412           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1413           0 :     return fastEmitInst_rr(Mips::AND_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1414             :   }
    1415             :   return 0;
    1416             : }
    1417             : 
    1418           0 : unsigned fastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1419           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1420             :     return 0;
    1421           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1422           0 :     return fastEmitInst_rr(Mips::AND_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1423             :   }
    1424             :   return 0;
    1425             : }
    1426             : 
    1427           5 : unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1428           5 :   switch (VT.SimpleTy) {
    1429           5 :   case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1430           0 :   case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1431           0 :   case MVT::v16i8: return fastEmit_ISD_AND_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1432           0 :   case MVT::v8i16: return fastEmit_ISD_AND_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1433           0 :   case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1434           0 :   case MVT::v2i64: return fastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1435             :   default: return 0;
    1436             :   }
    1437             : }
    1438             : 
    1439             : // FastEmit functions for ISD::FADD.
    1440             : 
    1441           0 : unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1442           0 :   if (RetVT.SimpleTy != MVT::f32)
    1443             :     return 0;
    1444           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
    1445           0 :     return fastEmitInst_rr(Mips::FADD_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1446             :   }
    1447           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
    1448           0 :     return fastEmitInst_rr(Mips::FADD_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1449             :   }
    1450             :   return 0;
    1451             : }
    1452             : 
    1453           0 : unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1454           0 :   if (RetVT.SimpleTy != MVT::f64)
    1455             :     return 0;
    1456           0 :   if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
    1457           0 :     return fastEmitInst_rr(Mips::FADD_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1458             :   }
    1459           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
    1460           0 :     return fastEmitInst_rr(Mips::FADD_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1461             :   }
    1462           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
    1463           0 :     return fastEmitInst_rr(Mips::FADD_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1464             :   }
    1465           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
    1466           0 :     return fastEmitInst_rr(Mips::FADD_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1467             :   }
    1468             :   return 0;
    1469             : }
    1470             : 
    1471           0 : unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1472           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1473             :     return 0;
    1474           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1475           0 :     return fastEmitInst_rr(Mips::FADD_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1476             :   }
    1477             :   return 0;
    1478             : }
    1479             : 
    1480           0 : unsigned fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1481           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1482             :     return 0;
    1483           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1484           0 :     return fastEmitInst_rr(Mips::FADD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1485             :   }
    1486             :   return 0;
    1487             : }
    1488             : 
    1489           0 : unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1490           0 :   switch (VT.SimpleTy) {
    1491           0 :   case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1492           0 :   case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1493           0 :   case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1494           0 :   case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1495             :   default: return 0;
    1496             :   }
    1497             : }
    1498             : 
    1499             : // FastEmit functions for ISD::FDIV.
    1500             : 
    1501           0 : unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1502           0 :   if (RetVT.SimpleTy != MVT::f32)
    1503             :     return 0;
    1504           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
    1505           0 :     return fastEmitInst_rr(Mips::FDIV_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1506             :   }
    1507           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
    1508           0 :     return fastEmitInst_rr(Mips::FDIV_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1509             :   }
    1510             :   return 0;
    1511             : }
    1512             : 
    1513           0 : unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1514           0 :   if (RetVT.SimpleTy != MVT::f64)
    1515             :     return 0;
    1516           0 :   if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
    1517           0 :     return fastEmitInst_rr(Mips::FDIV_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1518             :   }
    1519           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
    1520           0 :     return fastEmitInst_rr(Mips::FDIV_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1521             :   }
    1522           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
    1523           0 :     return fastEmitInst_rr(Mips::FDIV_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1524             :   }
    1525           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
    1526           0 :     return fastEmitInst_rr(Mips::FDIV_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1527             :   }
    1528             :   return 0;
    1529             : }
    1530             : 
    1531           0 : unsigned fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1532           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1533             :     return 0;
    1534           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1535           0 :     return fastEmitInst_rr(Mips::FDIV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1536             :   }
    1537             :   return 0;
    1538             : }
    1539             : 
    1540           0 : unsigned fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1541           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1542             :     return 0;
    1543           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1544           0 :     return fastEmitInst_rr(Mips::FDIV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1545             :   }
    1546             :   return 0;
    1547             : }
    1548             : 
    1549           0 : unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1550           0 :   switch (VT.SimpleTy) {
    1551           0 :   case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1552           0 :   case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1553           0 :   case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1554           0 :   case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1555             :   default: return 0;
    1556             :   }
    1557             : }
    1558             : 
    1559             : // FastEmit functions for ISD::FMUL.
    1560             : 
    1561           0 : unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1562           0 :   if (RetVT.SimpleTy != MVT::f32)
    1563             :     return 0;
    1564           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
    1565           0 :     return fastEmitInst_rr(Mips::FMUL_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1566             :   }
    1567           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
    1568           0 :     return fastEmitInst_rr(Mips::FMUL_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1569             :   }
    1570             :   return 0;
    1571             : }
    1572             : 
    1573           0 : unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1574           0 :   if (RetVT.SimpleTy != MVT::f64)
    1575             :     return 0;
    1576           0 :   if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
    1577           0 :     return fastEmitInst_rr(Mips::FMUL_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1578             :   }
    1579           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
    1580           0 :     return fastEmitInst_rr(Mips::FMUL_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1581             :   }
    1582           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
    1583           0 :     return fastEmitInst_rr(Mips::FMUL_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1584             :   }
    1585           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
    1586           0 :     return fastEmitInst_rr(Mips::FMUL_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1587             :   }
    1588             :   return 0;
    1589             : }
    1590             : 
    1591           0 : unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1592           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1593             :     return 0;
    1594           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1595           0 :     return fastEmitInst_rr(Mips::FMUL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1596             :   }
    1597             :   return 0;
    1598             : }
    1599             : 
    1600           0 : unsigned fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1601           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1602             :     return 0;
    1603           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1604           0 :     return fastEmitInst_rr(Mips::FMUL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1605             :   }
    1606             :   return 0;
    1607             : }
    1608             : 
    1609           0 : unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1610           0 :   switch (VT.SimpleTy) {
    1611           0 :   case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1612           0 :   case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1613           0 :   case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1614           0 :   case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1615             :   default: return 0;
    1616             :   }
    1617             : }
    1618             : 
    1619             : // FastEmit functions for ISD::FSUB.
    1620             : 
    1621           0 : unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1622           0 :   if (RetVT.SimpleTy != MVT::f32)
    1623             :     return 0;
    1624           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
    1625           0 :     return fastEmitInst_rr(Mips::FSUB_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1626             :   }
    1627           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
    1628           0 :     return fastEmitInst_rr(Mips::FSUB_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1629             :   }
    1630             :   return 0;
    1631             : }
    1632             : 
    1633           0 : unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1634           0 :   if (RetVT.SimpleTy != MVT::f64)
    1635             :     return 0;
    1636           0 :   if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
    1637           0 :     return fastEmitInst_rr(Mips::FSUB_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1638             :   }
    1639           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
    1640           0 :     return fastEmitInst_rr(Mips::FSUB_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1641             :   }
    1642           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
    1643           0 :     return fastEmitInst_rr(Mips::FSUB_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1644             :   }
    1645           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
    1646           0 :     return fastEmitInst_rr(Mips::FSUB_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1647             :   }
    1648             :   return 0;
    1649             : }
    1650             : 
    1651           0 : unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1652           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1653             :     return 0;
    1654           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1655           0 :     return fastEmitInst_rr(Mips::FSUB_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1656             :   }
    1657             :   return 0;
    1658             : }
    1659             : 
    1660           0 : unsigned fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1661           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1662             :     return 0;
    1663           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1664           0 :     return fastEmitInst_rr(Mips::FSUB_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1665             :   }
    1666             :   return 0;
    1667             : }
    1668             : 
    1669           0 : unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1670           0 :   switch (VT.SimpleTy) {
    1671           0 :   case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1672           0 :   case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1673           0 :   case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1674           0 :   case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1675             :   default: return 0;
    1676             :   }
    1677             : }
    1678             : 
    1679             : // FastEmit functions for ISD::MUL.
    1680             : 
    1681           2 : unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1682           2 :   if (RetVT.SimpleTy != MVT::i32)
    1683             :     return 0;
    1684           2 :   if ((Subtarget->inMips16Mode())) {
    1685           0 :     return fastEmitInst_rr(Mips::MultRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1686             :   }
    1687           2 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
    1688           0 :     return fastEmitInst_rr(Mips::MUL_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1689             :   }
    1690           2 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
    1691           0 :     return fastEmitInst_rr(Mips::MUL_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1692             :   }
    1693           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1694           0 :     return fastEmitInst_rr(Mips::MUL_R6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1695             :   }
    1696           2 :   if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    1697           2 :     return fastEmitInst_rr(Mips::MUL, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1698             :   }
    1699             :   return 0;
    1700             : }
    1701             : 
    1702           0 : unsigned fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1703           0 :   if (RetVT.SimpleTy != MVT::i64)
    1704             :     return 0;
    1705           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1706           0 :     return fastEmitInst_rr(Mips::DMUL_R6, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1707             :   }
    1708           0 :   if ((Subtarget->hasCnMips())) {
    1709           0 :     return fastEmitInst_rr(Mips::DMUL, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1710             :   }
    1711             :   return 0;
    1712             : }
    1713             : 
    1714           0 : unsigned fastEmit_ISD_MUL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1715           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1716             :     return 0;
    1717           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1718           0 :     return fastEmitInst_rr(Mips::MULV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1719             :   }
    1720             :   return 0;
    1721             : }
    1722             : 
    1723             : unsigned fastEmit_ISD_MUL_MVT_v2i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1724           0 :   if (RetVT.SimpleTy != MVT::v2i16)
    1725             :     return 0;
    1726           0 :   if ((Subtarget->hasDSPR2())) {
    1727             :     return fastEmitInst_rr(Mips::MUL_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1728             :   }
    1729             :   return 0;
    1730             : }
    1731             : 
    1732           0 : unsigned fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1733           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1734             :     return 0;
    1735           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1736           0 :     return fastEmitInst_rr(Mips::MULV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1737             :   }
    1738             :   return 0;
    1739             : }
    1740             : 
    1741           0 : unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1742           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1743             :     return 0;
    1744           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1745           0 :     return fastEmitInst_rr(Mips::MULV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1746             :   }
    1747             :   return 0;
    1748             : }
    1749             : 
    1750           0 : unsigned fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1751           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1752             :     return 0;
    1753           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1754           0 :     return fastEmitInst_rr(Mips::MULV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1755             :   }
    1756             :   return 0;
    1757             : }
    1758             : 
    1759           2 : unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1760           2 :   switch (VT.SimpleTy) {
    1761           2 :   case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1762           0 :   case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1763           0 :   case MVT::v16i8: return fastEmit_ISD_MUL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1764           0 :   case MVT::v2i16: return fastEmit_ISD_MUL_MVT_v2i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1765           0 :   case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1766           0 :   case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1767           0 :   case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1768             :   default: return 0;
    1769             :   }
    1770             : }
    1771             : 
    1772             : // FastEmit functions for ISD::MULHS.
    1773             : 
    1774           0 : unsigned fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1775           0 :   if (RetVT.SimpleTy != MVT::i32)
    1776             :     return 0;
    1777           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
    1778           0 :     return fastEmitInst_rr(Mips::MUH_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1779             :   }
    1780           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1781           0 :     return fastEmitInst_rr(Mips::MUH, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1782             :   }
    1783             :   return 0;
    1784             : }
    1785             : 
    1786           0 : unsigned fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1787           0 :   if (RetVT.SimpleTy != MVT::i64)
    1788             :     return 0;
    1789           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1790           0 :     return fastEmitInst_rr(Mips::DMUH, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1791             :   }
    1792             :   return 0;
    1793             : }
    1794             : 
    1795           0 : unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1796           0 :   switch (VT.SimpleTy) {
    1797           0 :   case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1798           0 :   case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1799             :   default: return 0;
    1800             :   }
    1801             : }
    1802             : 
    1803             : // FastEmit functions for ISD::MULHU.
    1804             : 
    1805           0 : unsigned fastEmit_ISD_MULHU_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1806           0 :   if (RetVT.SimpleTy != MVT::i32)
    1807             :     return 0;
    1808           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
    1809           0 :     return fastEmitInst_rr(Mips::MUHU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1810             :   }
    1811           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1812           0 :     return fastEmitInst_rr(Mips::MUHU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1813             :   }
    1814             :   return 0;
    1815             : }
    1816             : 
    1817           0 : unsigned fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1818           0 :   if (RetVT.SimpleTy != MVT::i64)
    1819             :     return 0;
    1820           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1821           0 :     return fastEmitInst_rr(Mips::DMUHU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1822             :   }
    1823             :   return 0;
    1824             : }
    1825             : 
    1826           0 : unsigned fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1827           0 :   switch (VT.SimpleTy) {
    1828           0 :   case MVT::i32: return fastEmit_ISD_MULHU_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1829           0 :   case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1830             :   default: return 0;
    1831             :   }
    1832             : }
    1833             : 
    1834             : // FastEmit functions for ISD::OR.
    1835             : 
    1836           4 : unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1837           4 :   if (RetVT.SimpleTy != MVT::i32)
    1838             :     return 0;
    1839           4 :   if ((Subtarget->inMips16Mode())) {
    1840           0 :     return fastEmitInst_rr(Mips::OrRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1841             :   }
    1842           4 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
    1843           0 :     return fastEmitInst_rr(Mips::OR_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1844             :   }
    1845           4 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
    1846           0 :     return fastEmitInst_rr(Mips::OR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1847             :   }
    1848           4 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1849           8 :     return fastEmitInst_rr(Mips::OR, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1850             :   }
    1851             :   return 0;
    1852             : }
    1853             : 
    1854           0 : unsigned fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1855           0 :   if (RetVT.SimpleTy != MVT::i64)
    1856             :     return 0;
    1857           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())) {
    1858           0 :     return fastEmitInst_rr(Mips::OR64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1859             :   }
    1860             :   return 0;
    1861             : }
    1862             : 
    1863           0 : unsigned fastEmit_ISD_OR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1864           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1865             :     return 0;
    1866           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1867           0 :     return fastEmitInst_rr(Mips::OR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1868             :   }
    1869             :   return 0;
    1870             : }
    1871             : 
    1872           0 : unsigned fastEmit_ISD_OR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1873           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1874             :     return 0;
    1875           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1876           0 :     return fastEmitInst_rr(Mips::OR_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1877             :   }
    1878             :   return 0;
    1879             : }
    1880             : 
    1881           0 : unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1882           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1883             :     return 0;
    1884           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1885           0 :     return fastEmitInst_rr(Mips::OR_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1886             :   }
    1887             :   return 0;
    1888             : }
    1889             : 
    1890           0 : unsigned fastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1891           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1892             :     return 0;
    1893           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1894           0 :     return fastEmitInst_rr(Mips::OR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1895             :   }
    1896             :   return 0;
    1897             : }
    1898             : 
    1899           4 : unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1900           4 :   switch (VT.SimpleTy) {
    1901           4 :   case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1902           0 :   case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1903           0 :   case MVT::v16i8: return fastEmit_ISD_OR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1904           0 :   case MVT::v8i16: return fastEmit_ISD_OR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1905           0 :   case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1906           0 :   case MVT::v2i64: return fastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1907             :   default: return 0;
    1908             :   }
    1909             : }
    1910             : 
    1911             : // FastEmit functions for ISD::ROTR.
    1912             : 
    1913           0 : unsigned fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1914           0 :   if (RetVT.SimpleTy != MVT::i32)
    1915             :     return 0;
    1916           0 :   if ((Subtarget->inMicroMipsMode())) {
    1917           0 :     return fastEmitInst_rr(Mips::ROTRV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1918             :   }
    1919           0 :   if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1920           0 :     return fastEmitInst_rr(Mips::ROTRV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1921             :   }
    1922             :   return 0;
    1923             : }
    1924             : 
    1925             : unsigned fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1926           0 :   switch (VT.SimpleTy) {
    1927           0 :   case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1928             :   default: return 0;
    1929             :   }
    1930             : }
    1931             : 
    1932             : // FastEmit functions for ISD::SDIV.
    1933             : 
    1934           4 : unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1935           4 :   if (RetVT.SimpleTy != MVT::i32)
    1936             :     return 0;
    1937           4 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
    1938           0 :     return fastEmitInst_rr(Mips::DIV_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1939             :   }
    1940           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1941           0 :     return fastEmitInst_rr(Mips::DIV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1942             :   }
    1943             :   return 0;
    1944             : }
    1945             : 
    1946           0 : unsigned fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1947           0 :   if (RetVT.SimpleTy != MVT::i64)
    1948             :     return 0;
    1949           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    1950           0 :     return fastEmitInst_rr(Mips::DDIV, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1951             :   }
    1952             :   return 0;
    1953             : }
    1954             : 
    1955           0 : unsigned fastEmit_ISD_SDIV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1956           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1957             :     return 0;
    1958           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1959           0 :     return fastEmitInst_rr(Mips::DIV_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1960             :   }
    1961             :   return 0;
    1962             : }
    1963             : 
    1964           0 : unsigned fastEmit_ISD_SDIV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1965           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1966             :     return 0;
    1967           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1968           0 :     return fastEmitInst_rr(Mips::DIV_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1969             :   }
    1970             :   return 0;
    1971             : }
    1972             : 
    1973           0 : unsigned fastEmit_ISD_SDIV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1974           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1975             :     return 0;
    1976           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1977           0 :     return fastEmitInst_rr(Mips::DIV_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1978             :   }
    1979             :   return 0;
    1980             : }
    1981             : 
    1982           0 : unsigned fastEmit_ISD_SDIV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1983           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1984             :     return 0;
    1985           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    1986           0 :     return fastEmitInst_rr(Mips::DIV_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1987             :   }
    1988             :   return 0;
    1989             : }
    1990             : 
    1991           4 : unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1992           4 :   switch (VT.SimpleTy) {
    1993           4 :   case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1994           0 :   case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1995           0 :   case MVT::v16i8: return fastEmit_ISD_SDIV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1996           0 :   case MVT::v8i16: return fastEmit_ISD_SDIV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1997           0 :   case MVT::v4i32: return fastEmit_ISD_SDIV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1998           0 :   case MVT::v2i64: return fastEmit_ISD_SDIV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1999             :   default: return 0;
    2000             :   }
    2001             : }
    2002             : 
    2003             : // FastEmit functions for ISD::SHL.
    2004             : 
    2005           0 : unsigned fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2006           0 :   if (RetVT.SimpleTy != MVT::i32)
    2007             :     return 0;
    2008           0 :   if ((Subtarget->inMicroMipsMode())) {
    2009           0 :     return fastEmitInst_rr(Mips::SLLV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2010             :   }
    2011           0 :   if ((Subtarget->inMips16Mode())) {
    2012           0 :     return fastEmitInst_rr(Mips::SllvRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2013             :   }
    2014             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2015           0 :     return fastEmitInst_rr(Mips::SLLV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2016             :   }
    2017             :   return 0;
    2018             : }
    2019             : 
    2020           0 : unsigned fastEmit_ISD_SHL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2021           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2022             :     return 0;
    2023           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2024           0 :     return fastEmitInst_rr(Mips::SLL_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2025             :   }
    2026             :   return 0;
    2027             : }
    2028             : 
    2029           0 : unsigned fastEmit_ISD_SHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2030           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2031             :     return 0;
    2032           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2033           0 :     return fastEmitInst_rr(Mips::SLL_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2034             :   }
    2035             :   return 0;
    2036             : }
    2037             : 
    2038           0 : unsigned fastEmit_ISD_SHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2039           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2040             :     return 0;
    2041           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2042           0 :     return fastEmitInst_rr(Mips::SLL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2043             :   }
    2044             :   return 0;
    2045             : }
    2046             : 
    2047           0 : unsigned fastEmit_ISD_SHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2048           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2049             :     return 0;
    2050           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2051           0 :     return fastEmitInst_rr(Mips::SLL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2052             :   }
    2053             :   return 0;
    2054             : }
    2055             : 
    2056           0 : unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2057           0 :   switch (VT.SimpleTy) {
    2058           0 :   case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2059           0 :   case MVT::v16i8: return fastEmit_ISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2060           0 :   case MVT::v8i16: return fastEmit_ISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2061           0 :   case MVT::v4i32: return fastEmit_ISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2062           0 :   case MVT::v2i64: return fastEmit_ISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2063             :   default: return 0;
    2064             :   }
    2065             : }
    2066             : 
    2067             : // FastEmit functions for ISD::SMAX.
    2068             : 
    2069           0 : unsigned fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2070           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2071             :     return 0;
    2072           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2073           0 :     return fastEmitInst_rr(Mips::MAX_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2074             :   }
    2075             :   return 0;
    2076             : }
    2077             : 
    2078           0 : unsigned fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2079           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2080             :     return 0;
    2081           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2082           0 :     return fastEmitInst_rr(Mips::MAX_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2083             :   }
    2084             :   return 0;
    2085             : }
    2086             : 
    2087           0 : unsigned fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2088           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2089             :     return 0;
    2090           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2091           0 :     return fastEmitInst_rr(Mips::MAX_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2092             :   }
    2093             :   return 0;
    2094             : }
    2095             : 
    2096           0 : unsigned fastEmit_ISD_SMAX_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2097           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2098             :     return 0;
    2099           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2100           0 :     return fastEmitInst_rr(Mips::MAX_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2101             :   }
    2102             :   return 0;
    2103             : }
    2104             : 
    2105           0 : unsigned fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2106           0 :   switch (VT.SimpleTy) {
    2107           0 :   case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2108           0 :   case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2109           0 :   case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2110           0 :   case MVT::v2i64: return fastEmit_ISD_SMAX_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2111             :   default: return 0;
    2112             :   }
    2113             : }
    2114             : 
    2115             : // FastEmit functions for ISD::SMIN.
    2116             : 
    2117           0 : unsigned fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2118           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2119             :     return 0;
    2120           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2121           0 :     return fastEmitInst_rr(Mips::MIN_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2122             :   }
    2123             :   return 0;
    2124             : }
    2125             : 
    2126           0 : unsigned fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2127           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2128             :     return 0;
    2129           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2130           0 :     return fastEmitInst_rr(Mips::MIN_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2131             :   }
    2132             :   return 0;
    2133             : }
    2134             : 
    2135           0 : unsigned fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2136           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2137             :     return 0;
    2138           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2139           0 :     return fastEmitInst_rr(Mips::MIN_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2140             :   }
    2141             :   return 0;
    2142             : }
    2143             : 
    2144           0 : unsigned fastEmit_ISD_SMIN_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2145           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2146             :     return 0;
    2147           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2148           0 :     return fastEmitInst_rr(Mips::MIN_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2149             :   }
    2150             :   return 0;
    2151             : }
    2152             : 
    2153           0 : unsigned fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2154           0 :   switch (VT.SimpleTy) {
    2155           0 :   case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2156           0 :   case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2157           0 :   case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2158           0 :   case MVT::v2i64: return fastEmit_ISD_SMIN_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2159             :   default: return 0;
    2160             :   }
    2161             : }
    2162             : 
    2163             : // FastEmit functions for ISD::SRA.
    2164             : 
    2165           0 : unsigned fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2166           0 :   if (RetVT.SimpleTy != MVT::i32)
    2167             :     return 0;
    2168           0 :   if ((Subtarget->inMicroMipsMode())) {
    2169           0 :     return fastEmitInst_rr(Mips::SRAV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2170             :   }
    2171           0 :   if ((Subtarget->inMips16Mode())) {
    2172           0 :     return fastEmitInst_rr(Mips::SravRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2173             :   }
    2174             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2175           0 :     return fastEmitInst_rr(Mips::SRAV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2176             :   }
    2177             :   return 0;
    2178             : }
    2179             : 
    2180           0 : unsigned fastEmit_ISD_SRA_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2181           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2182             :     return 0;
    2183           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2184           0 :     return fastEmitInst_rr(Mips::SRA_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2185             :   }
    2186             :   return 0;
    2187             : }
    2188             : 
    2189           0 : unsigned fastEmit_ISD_SRA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2190           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2191             :     return 0;
    2192           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2193           0 :     return fastEmitInst_rr(Mips::SRA_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2194             :   }
    2195             :   return 0;
    2196             : }
    2197             : 
    2198           0 : unsigned fastEmit_ISD_SRA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2199           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2200             :     return 0;
    2201           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2202           0 :     return fastEmitInst_rr(Mips::SRA_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2203             :   }
    2204             :   return 0;
    2205             : }
    2206             : 
    2207           0 : unsigned fastEmit_ISD_SRA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2208           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2209             :     return 0;
    2210           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2211           0 :     return fastEmitInst_rr(Mips::SRA_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2212             :   }
    2213             :   return 0;
    2214             : }
    2215             : 
    2216           0 : unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2217           0 :   switch (VT.SimpleTy) {
    2218           0 :   case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2219           0 :   case MVT::v16i8: return fastEmit_ISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2220           0 :   case MVT::v8i16: return fastEmit_ISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2221           0 :   case MVT::v4i32: return fastEmit_ISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2222           0 :   case MVT::v2i64: return fastEmit_ISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2223             :   default: return 0;
    2224             :   }
    2225             : }
    2226             : 
    2227             : // FastEmit functions for ISD::SREM.
    2228             : 
    2229           4 : unsigned fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2230           4 :   if (RetVT.SimpleTy != MVT::i32)
    2231             :     return 0;
    2232           4 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
    2233           0 :     return fastEmitInst_rr(Mips::MOD_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2234             :   }
    2235           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2236           0 :     return fastEmitInst_rr(Mips::MOD, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2237             :   }
    2238             :   return 0;
    2239             : }
    2240             : 
    2241           0 : unsigned fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2242           0 :   if (RetVT.SimpleTy != MVT::i64)
    2243             :     return 0;
    2244           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2245           0 :     return fastEmitInst_rr(Mips::DMOD, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2246             :   }
    2247             :   return 0;
    2248             : }
    2249             : 
    2250           0 : unsigned fastEmit_ISD_SREM_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2251           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2252             :     return 0;
    2253           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2254           0 :     return fastEmitInst_rr(Mips::MOD_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2255             :   }
    2256             :   return 0;
    2257             : }
    2258             : 
    2259           0 : unsigned fastEmit_ISD_SREM_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2260           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2261             :     return 0;
    2262           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2263           0 :     return fastEmitInst_rr(Mips::MOD_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2264             :   }
    2265             :   return 0;
    2266             : }
    2267             : 
    2268           0 : unsigned fastEmit_ISD_SREM_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2269           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2270             :     return 0;
    2271           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2272           0 :     return fastEmitInst_rr(Mips::MOD_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2273             :   }
    2274             :   return 0;
    2275             : }
    2276             : 
    2277           0 : unsigned fastEmit_ISD_SREM_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2278           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2279             :     return 0;
    2280           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2281           0 :     return fastEmitInst_rr(Mips::MOD_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2282             :   }
    2283             :   return 0;
    2284             : }
    2285             : 
    2286           4 : unsigned fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2287           4 :   switch (VT.SimpleTy) {
    2288           4 :   case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2289           0 :   case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2290           0 :   case MVT::v16i8: return fastEmit_ISD_SREM_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2291           0 :   case MVT::v8i16: return fastEmit_ISD_SREM_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2292           0 :   case MVT::v4i32: return fastEmit_ISD_SREM_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2293           0 :   case MVT::v2i64: return fastEmit_ISD_SREM_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2294             :   default: return 0;
    2295             :   }
    2296             : }
    2297             : 
    2298             : // FastEmit functions for ISD::SRL.
    2299             : 
    2300           0 : unsigned fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2301           0 :   if (RetVT.SimpleTy != MVT::i32)
    2302             :     return 0;
    2303           0 :   if ((Subtarget->inMicroMipsMode())) {
    2304           0 :     return fastEmitInst_rr(Mips::SRLV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2305             :   }
    2306           0 :   if ((Subtarget->inMips16Mode())) {
    2307           0 :     return fastEmitInst_rr(Mips::SrlvRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2308             :   }
    2309             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2310           0 :     return fastEmitInst_rr(Mips::SRLV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2311             :   }
    2312             :   return 0;
    2313             : }
    2314             : 
    2315           0 : unsigned fastEmit_ISD_SRL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2316           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2317             :     return 0;
    2318           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2319           0 :     return fastEmitInst_rr(Mips::SRL_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2320             :   }
    2321             :   return 0;
    2322             : }
    2323             : 
    2324           0 : unsigned fastEmit_ISD_SRL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2325           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2326             :     return 0;
    2327           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2328           0 :     return fastEmitInst_rr(Mips::SRL_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2329             :   }
    2330             :   return 0;
    2331             : }
    2332             : 
    2333           0 : unsigned fastEmit_ISD_SRL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2334           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2335             :     return 0;
    2336           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2337           0 :     return fastEmitInst_rr(Mips::SRL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2338             :   }
    2339             :   return 0;
    2340             : }
    2341             : 
    2342           0 : unsigned fastEmit_ISD_SRL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2343           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2344             :     return 0;
    2345           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2346           0 :     return fastEmitInst_rr(Mips::SRL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2347             :   }
    2348             :   return 0;
    2349             : }
    2350             : 
    2351           0 : unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2352           0 :   switch (VT.SimpleTy) {
    2353           0 :   case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2354           0 :   case MVT::v16i8: return fastEmit_ISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2355           0 :   case MVT::v8i16: return fastEmit_ISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2356           0 :   case MVT::v4i32: return fastEmit_ISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2357           0 :   case MVT::v2i64: return fastEmit_ISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2358             :   default: return 0;
    2359             :   }
    2360             : }
    2361             : 
    2362             : // FastEmit functions for ISD::SUB.
    2363             : 
    2364           0 : unsigned fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2365           0 :   if (RetVT.SimpleTy != MVT::i32)
    2366             :     return 0;
    2367           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
    2368           0 :     return fastEmitInst_rr(Mips::SUBU16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2369             :   }
    2370           0 :   if ((Subtarget->inMips16Mode())) {
    2371           0 :     return fastEmitInst_rr(Mips::SubuRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2372             :   }
    2373           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
    2374           0 :     return fastEmitInst_rr(Mips::SUBu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2375             :   }
    2376           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2377           0 :     return fastEmitInst_rr(Mips::SUBu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2378             :   }
    2379             :   return 0;
    2380             : }
    2381             : 
    2382           0 : unsigned fastEmit_ISD_SUB_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2383           0 :   if (RetVT.SimpleTy != MVT::i64)
    2384             :     return 0;
    2385           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2386           0 :     return fastEmitInst_rr(Mips::DSUBu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2387             :   }
    2388             :   return 0;
    2389             : }
    2390             : 
    2391             : unsigned fastEmit_ISD_SUB_MVT_v4i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2392           0 :   if (RetVT.SimpleTy != MVT::v4i8)
    2393             :     return 0;
    2394           0 :   if ((Subtarget->hasDSP())) {
    2395             :     return fastEmitInst_rr(Mips::SUBU_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2396             :   }
    2397             :   return 0;
    2398             : }
    2399             : 
    2400           0 : unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2401           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2402             :     return 0;
    2403           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2404           0 :     return fastEmitInst_rr(Mips::SUBV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2405             :   }
    2406             :   return 0;
    2407             : }
    2408             : 
    2409             : unsigned fastEmit_ISD_SUB_MVT_v2i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2410           0 :   if (RetVT.SimpleTy != MVT::v2i16)
    2411             :     return 0;
    2412           0 :   if ((Subtarget->hasDSP())) {
    2413             :     return fastEmitInst_rr(Mips::SUBQ_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2414             :   }
    2415             :   return 0;
    2416             : }
    2417             : 
    2418           0 : unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2419           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2420             :     return 0;
    2421           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2422           0 :     return fastEmitInst_rr(Mips::SUBV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2423             :   }
    2424             :   return 0;
    2425             : }
    2426             : 
    2427           0 : unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2428           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2429             :     return 0;
    2430           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2431           0 :     return fastEmitInst_rr(Mips::SUBV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2432             :   }
    2433             :   return 0;
    2434             : }
    2435             : 
    2436           0 : unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2437           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2438             :     return 0;
    2439           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2440           0 :     return fastEmitInst_rr(Mips::SUBV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2441             :   }
    2442             :   return 0;
    2443             : }
    2444             : 
    2445           0 : unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2446           0 :   switch (VT.SimpleTy) {
    2447           0 :   case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2448           0 :   case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2449           0 :   case MVT::v4i8: return fastEmit_ISD_SUB_MVT_v4i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2450           0 :   case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2451           0 :   case MVT::v2i16: return fastEmit_ISD_SUB_MVT_v2i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2452           0 :   case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2453           0 :   case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2454           0 :   case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2455             :   default: return 0;
    2456             :   }
    2457             : }
    2458             : 
    2459             : // FastEmit functions for ISD::SUBC.
    2460             : 
    2461           0 : unsigned fastEmit_ISD_SUBC_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2462           0 :   if (RetVT.SimpleTy != MVT::i32)
    2463             :     return 0;
    2464           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
    2465           0 :     return fastEmitInst_rr(Mips::SUBU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2466             :   }
    2467           0 :   if ((Subtarget->inMicroMipsMode())) {
    2468           0 :     return fastEmitInst_rr(Mips::SUBu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2469             :   }
    2470           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2471           0 :     return fastEmitInst_rr(Mips::SUBu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2472             :   }
    2473             :   return 0;
    2474             : }
    2475             : 
    2476           0 : unsigned fastEmit_ISD_SUBC_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2477           0 :   if (RetVT.SimpleTy != MVT::i64)
    2478             :     return 0;
    2479           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2480           0 :     return fastEmitInst_rr(Mips::DSUBu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2481             :   }
    2482             :   return 0;
    2483             : }
    2484             : 
    2485           0 : unsigned fastEmit_ISD_SUBC_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2486           0 :   switch (VT.SimpleTy) {
    2487           0 :   case MVT::i32: return fastEmit_ISD_SUBC_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2488           0 :   case MVT::i64: return fastEmit_ISD_SUBC_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2489             :   default: return 0;
    2490             :   }
    2491             : }
    2492             : 
    2493             : // FastEmit functions for ISD::UDIV.
    2494             : 
    2495           4 : unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2496           4 :   if (RetVT.SimpleTy != MVT::i32)
    2497             :     return 0;
    2498           4 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
    2499           0 :     return fastEmitInst_rr(Mips::DIVU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2500             :   }
    2501           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2502           0 :     return fastEmitInst_rr(Mips::DIVU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2503             :   }
    2504             :   return 0;
    2505             : }
    2506             : 
    2507           0 : unsigned fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2508           0 :   if (RetVT.SimpleTy != MVT::i64)
    2509             :     return 0;
    2510           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2511           0 :     return fastEmitInst_rr(Mips::DDIVU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2512             :   }
    2513             :   return 0;
    2514             : }
    2515             : 
    2516           0 : unsigned fastEmit_ISD_UDIV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2517           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2518             :     return 0;
    2519           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2520           0 :     return fastEmitInst_rr(Mips::DIV_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2521             :   }
    2522             :   return 0;
    2523             : }
    2524             : 
    2525           0 : unsigned fastEmit_ISD_UDIV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2526           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2527             :     return 0;
    2528           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2529           0 :     return fastEmitInst_rr(Mips::DIV_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2530             :   }
    2531             :   return 0;
    2532             : }
    2533             : 
    2534           0 : unsigned fastEmit_ISD_UDIV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2535           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2536             :     return 0;
    2537           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2538           0 :     return fastEmitInst_rr(Mips::DIV_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2539             :   }
    2540             :   return 0;
    2541             : }
    2542             : 
    2543           0 : unsigned fastEmit_ISD_UDIV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2544           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2545             :     return 0;
    2546           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2547           0 :     return fastEmitInst_rr(Mips::DIV_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2548             :   }
    2549             :   return 0;
    2550             : }
    2551             : 
    2552           4 : unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2553           4 :   switch (VT.SimpleTy) {
    2554           4 :   case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2555           0 :   case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2556           0 :   case MVT::v16i8: return fastEmit_ISD_UDIV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2557           0 :   case MVT::v8i16: return fastEmit_ISD_UDIV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2558           0 :   case MVT::v4i32: return fastEmit_ISD_UDIV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2559           0 :   case MVT::v2i64: return fastEmit_ISD_UDIV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2560             :   default: return 0;
    2561             :   }
    2562             : }
    2563             : 
    2564             : // FastEmit functions for ISD::UMAX.
    2565             : 
    2566           0 : unsigned fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2567           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2568             :     return 0;
    2569           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2570           0 :     return fastEmitInst_rr(Mips::MAX_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2571             :   }
    2572             :   return 0;
    2573             : }
    2574             : 
    2575           0 : unsigned fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2576           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2577             :     return 0;
    2578           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2579           0 :     return fastEmitInst_rr(Mips::MAX_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2580             :   }
    2581             :   return 0;
    2582             : }
    2583             : 
    2584           0 : unsigned fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2585           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2586             :     return 0;
    2587           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2588           0 :     return fastEmitInst_rr(Mips::MAX_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2589             :   }
    2590             :   return 0;
    2591             : }
    2592             : 
    2593           0 : unsigned fastEmit_ISD_UMAX_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2594           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2595             :     return 0;
    2596           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2597           0 :     return fastEmitInst_rr(Mips::MAX_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2598             :   }
    2599             :   return 0;
    2600             : }
    2601             : 
    2602           0 : unsigned fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2603           0 :   switch (VT.SimpleTy) {
    2604           0 :   case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2605           0 :   case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2606           0 :   case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2607           0 :   case MVT::v2i64: return fastEmit_ISD_UMAX_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2608             :   default: return 0;
    2609             :   }
    2610             : }
    2611             : 
    2612             : // FastEmit functions for ISD::UMIN.
    2613             : 
    2614           0 : unsigned fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2615           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2616             :     return 0;
    2617           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2618           0 :     return fastEmitInst_rr(Mips::MIN_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2619             :   }
    2620             :   return 0;
    2621             : }
    2622             : 
    2623           0 : unsigned fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2624           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2625             :     return 0;
    2626           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2627           0 :     return fastEmitInst_rr(Mips::MIN_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2628             :   }
    2629             :   return 0;
    2630             : }
    2631             : 
    2632           0 : unsigned fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2633           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2634             :     return 0;
    2635           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2636           0 :     return fastEmitInst_rr(Mips::MIN_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2637             :   }
    2638             :   return 0;
    2639             : }
    2640             : 
    2641           0 : unsigned fastEmit_ISD_UMIN_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2642           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2643             :     return 0;
    2644           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2645           0 :     return fastEmitInst_rr(Mips::MIN_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2646             :   }
    2647             :   return 0;
    2648             : }
    2649             : 
    2650           0 : unsigned fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2651           0 :   switch (VT.SimpleTy) {
    2652           0 :   case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2653           0 :   case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2654           0 :   case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2655           0 :   case MVT::v2i64: return fastEmit_ISD_UMIN_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2656             :   default: return 0;
    2657             :   }
    2658             : }
    2659             : 
    2660             : // FastEmit functions for ISD::UREM.
    2661             : 
    2662           4 : unsigned fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2663           4 :   if (RetVT.SimpleTy != MVT::i32)
    2664             :     return 0;
    2665           4 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
    2666           0 :     return fastEmitInst_rr(Mips::MODU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2667             :   }
    2668           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2669           0 :     return fastEmitInst_rr(Mips::MODU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2670             :   }
    2671             :   return 0;
    2672             : }
    2673             : 
    2674           0 : unsigned fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2675           0 :   if (RetVT.SimpleTy != MVT::i64)
    2676             :     return 0;
    2677           0 :   if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2678           0 :     return fastEmitInst_rr(Mips::DMODU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2679             :   }
    2680             :   return 0;
    2681             : }
    2682             : 
    2683           0 : unsigned fastEmit_ISD_UREM_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2684           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2685             :     return 0;
    2686           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2687           0 :     return fastEmitInst_rr(Mips::MOD_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2688             :   }
    2689             :   return 0;
    2690             : }
    2691             : 
    2692           0 : unsigned fastEmit_ISD_UREM_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2693           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2694             :     return 0;
    2695           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2696           0 :     return fastEmitInst_rr(Mips::MOD_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2697             :   }
    2698             :   return 0;
    2699             : }
    2700             : 
    2701           0 : unsigned fastEmit_ISD_UREM_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2702           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2703             :     return 0;
    2704           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2705           0 :     return fastEmitInst_rr(Mips::MOD_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2706             :   }
    2707             :   return 0;
    2708             : }
    2709             : 
    2710           0 : unsigned fastEmit_ISD_UREM_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2711           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2712             :     return 0;
    2713           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2714           0 :     return fastEmitInst_rr(Mips::MOD_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2715             :   }
    2716             :   return 0;
    2717             : }
    2718             : 
    2719           4 : unsigned fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2720           4 :   switch (VT.SimpleTy) {
    2721           4 :   case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2722           0 :   case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2723           0 :   case MVT::v16i8: return fastEmit_ISD_UREM_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2724           0 :   case MVT::v8i16: return fastEmit_ISD_UREM_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2725           0 :   case MVT::v4i32: return fastEmit_ISD_UREM_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2726           0 :   case MVT::v2i64: return fastEmit_ISD_UREM_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2727             :   default: return 0;
    2728             :   }
    2729             : }
    2730             : 
    2731             : // FastEmit functions for ISD::XOR.
    2732             : 
    2733           4 : unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2734           4 :   if (RetVT.SimpleTy != MVT::i32)
    2735             :     return 0;
    2736           4 :   if ((Subtarget->inMips16Mode())) {
    2737           0 :     return fastEmitInst_rr(Mips::XorRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2738             :   }
    2739           4 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
    2740           0 :     return fastEmitInst_rr(Mips::XOR_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2741             :   }
    2742           4 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
    2743           0 :     return fastEmitInst_rr(Mips::XOR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2744             :   }
    2745           4 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    2746           8 :     return fastEmitInst_rr(Mips::XOR, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2747             :   }
    2748             :   return 0;
    2749             : }
    2750             : 
    2751           0 : unsigned fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2752           0 :   if (RetVT.SimpleTy != MVT::i64)
    2753             :     return 0;
    2754           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())) {
    2755           0 :     return fastEmitInst_rr(Mips::XOR64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2756             :   }
    2757             :   return 0;
    2758             : }
    2759             : 
    2760           0 : unsigned fastEmit_ISD_XOR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2761           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2762             :     return 0;
    2763           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2764           0 :     return fastEmitInst_rr(Mips::XOR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2765             :   }
    2766             :   return 0;
    2767             : }
    2768             : 
    2769           0 : unsigned fastEmit_ISD_XOR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2770           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2771             :     return 0;
    2772           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2773           0 :     return fastEmitInst_rr(Mips::XOR_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2774             :   }
    2775             :   return 0;
    2776             : }
    2777             : 
    2778           0 : unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2779           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2780             :     return 0;
    2781           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2782           0 :     return fastEmitInst_rr(Mips::XOR_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2783             :   }
    2784             :   return 0;
    2785             : }
    2786             : 
    2787           0 : unsigned fastEmit_ISD_XOR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2788           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2789             :     return 0;
    2790           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2791           0 :     return fastEmitInst_rr(Mips::XOR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2792             :   }
    2793             :   return 0;
    2794             : }
    2795             : 
    2796           4 : unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2797           4 :   switch (VT.SimpleTy) {
    2798           4 :   case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2799           0 :   case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2800           0 :   case MVT::v16i8: return fastEmit_ISD_XOR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2801           0 :   case MVT::v8i16: return fastEmit_ISD_XOR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2802           0 :   case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2803           0 :   case MVT::v2i64: return fastEmit_ISD_XOR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2804             :   default: return 0;
    2805             :   }
    2806             : }
    2807             : 
    2808             : // FastEmit functions for MipsISD::BuildPairF64.
    2809             : 
    2810           0 : unsigned fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2811           0 :   if (RetVT.SimpleTy != MVT::f64)
    2812             :     return 0;
    2813           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
    2814           0 :     return fastEmitInst_rr(Mips::BuildPairF64_64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2815             :   }
    2816           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
    2817           0 :     return fastEmitInst_rr(Mips::BuildPairF64, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2818             :   }
    2819             :   return 0;
    2820             : }
    2821             : 
    2822             : unsigned fastEmit_MipsISD_BuildPairF64_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2823           0 :   switch (VT.SimpleTy) {
    2824           0 :   case MVT::i32: return fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2825             :   default: return 0;
    2826             :   }
    2827             : }
    2828             : 
    2829             : // FastEmit functions for MipsISD::DivRem.
    2830             : 
    2831           0 : unsigned fastEmit_MipsISD_DivRem_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2832           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    2833             :     return 0;
    2834           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    2835           0 :     return fastEmitInst_rr(Mips::SDIV_MM_Pseudo, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2836             :   }
    2837           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    2838           0 :     return fastEmitInst_rr(Mips::PseudoSDIV, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2839             :   }
    2840             :   return 0;
    2841             : }
    2842             : 
    2843           0 : unsigned fastEmit_MipsISD_DivRem_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2844           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    2845             :     return 0;
    2846           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    2847           0 :     return fastEmitInst_rr(Mips::PseudoDSDIV, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2848             :   }
    2849             :   return 0;
    2850             : }
    2851             : 
    2852           0 : unsigned fastEmit_MipsISD_DivRem_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2853           0 :   switch (VT.SimpleTy) {
    2854           0 :   case MVT::i32: return fastEmit_MipsISD_DivRem_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2855           0 :   case MVT::i64: return fastEmit_MipsISD_DivRem_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2856             :   default: return 0;
    2857             :   }
    2858             : }
    2859             : 
    2860             : // FastEmit functions for MipsISD::DivRem16.
    2861             : 
    2862             : unsigned fastEmit_MipsISD_DivRem16_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2863           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2864             :     return 0;
    2865           0 :   if ((Subtarget->inMips16Mode())) {
    2866             :     return fastEmitInst_rr(Mips::DivRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2867             :   }
    2868             :   return 0;
    2869             : }
    2870             : 
    2871           0 : unsigned fastEmit_MipsISD_DivRem16_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2872           0 :   switch (VT.SimpleTy) {
    2873           0 :   case MVT::i32: return fastEmit_MipsISD_DivRem16_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2874             :   default: return 0;
    2875             :   }
    2876             : }
    2877             : 
    2878             : // FastEmit functions for MipsISD::DivRemU.
    2879             : 
    2880           0 : unsigned fastEmit_MipsISD_DivRemU_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2881           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    2882             :     return 0;
    2883           0 :   if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    2884           0 :     return fastEmitInst_rr(Mips::UDIV_MM_Pseudo, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2885             :   }
    2886           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    2887           0 :     return fastEmitInst_rr(Mips::PseudoUDIV, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2888             :   }
    2889             :   return 0;
    2890             : }
    2891             : 
    2892           0 : unsigned fastEmit_MipsISD_DivRemU_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2893           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    2894             :     return 0;
    2895           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    2896           0 :     return fastEmitInst_rr(Mips::PseudoDUDIV, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2897             :   }
    2898             :   return 0;
    2899             : }
    2900             : 
    2901           0 : unsigned fastEmit_MipsISD_DivRemU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2902           0 :   switch (VT.SimpleTy) {
    2903           0 :   case MVT::i32: return fastEmit_MipsISD_DivRemU_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2904           0 :   case MVT::i64: return fastEmit_MipsISD_DivRemU_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2905             :   default: return 0;
    2906             :   }
    2907             : }
    2908             : 
    2909             : // FastEmit functions for MipsISD::DivRemU16.
    2910             : 
    2911             : unsigned fastEmit_MipsISD_DivRemU16_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2912           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2913             :     return 0;
    2914           0 :   if ((Subtarget->inMips16Mode())) {
    2915             :     return fastEmitInst_rr(Mips::DivuRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2916             :   }
    2917             :   return 0;
    2918             : }
    2919             : 
    2920           0 : unsigned fastEmit_MipsISD_DivRemU16_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2921           0 :   switch (VT.SimpleTy) {
    2922           0 :   case MVT::i32: return fastEmit_MipsISD_DivRemU16_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2923             :   default: return 0;
    2924             :   }
    2925             : }
    2926             : 
    2927             : // FastEmit functions for MipsISD::EH_RETURN.
    2928             : 
    2929             : unsigned fastEmit_MipsISD_EH_RETURN_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2930           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2931             :     return 0;
    2932             :   return fastEmitInst_rr(Mips::MIPSeh_return32, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2933             : }
    2934             : 
    2935             : unsigned fastEmit_MipsISD_EH_RETURN_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2936           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2937             :     return 0;
    2938             :   return fastEmitInst_rr(Mips::MIPSeh_return64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2939             : }
    2940             : 
    2941           0 : unsigned fastEmit_MipsISD_EH_RETURN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2942           0 :   switch (VT.SimpleTy) {
    2943           0 :   case MVT::i32: return fastEmit_MipsISD_EH_RETURN_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2944           0 :   case MVT::i64: return fastEmit_MipsISD_EH_RETURN_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2945             :   default: return 0;
    2946             :   }
    2947             : }
    2948             : 
    2949             : // FastEmit functions for MipsISD::ILVEV.
    2950             : 
    2951           0 : unsigned fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2952           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2953             :     return 0;
    2954           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2955           0 :     return fastEmitInst_rr(Mips::ILVEV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2956             :   }
    2957             :   return 0;
    2958             : }
    2959             : 
    2960           0 : unsigned fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2961           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2962             :     return 0;
    2963           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2964           0 :     return fastEmitInst_rr(Mips::ILVEV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2965             :   }
    2966             :   return 0;
    2967             : }
    2968             : 
    2969           0 : unsigned fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2970           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2971             :     return 0;
    2972           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2973           0 :     return fastEmitInst_rr(Mips::ILVEV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2974             :   }
    2975             :   return 0;
    2976             : }
    2977             : 
    2978           0 : unsigned fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2979           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2980             :     return 0;
    2981           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    2982           0 :     return fastEmitInst_rr(Mips::ILVEV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2983             :   }
    2984             :   return 0;
    2985             : }
    2986             : 
    2987           0 : unsigned fastEmit_MipsISD_ILVEV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2988           0 :   switch (VT.SimpleTy) {
    2989           0 :   case MVT::v16i8: return fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2990           0 :   case MVT::v8i16: return fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2991           0 :   case MVT::v4i32: return fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2992           0 :   case MVT::v2i64: return fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2993             :   default: return 0;
    2994             :   }
    2995             : }
    2996             : 
    2997             : // FastEmit functions for MipsISD::ILVL.
    2998             : 
    2999           0 : unsigned fastEmit_MipsISD_ILVL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3000           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3001             :     return 0;
    3002           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3003           0 :     return fastEmitInst_rr(Mips::ILVL_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3004             :   }
    3005             :   return 0;
    3006             : }
    3007             : 
    3008           0 : unsigned fastEmit_MipsISD_ILVL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3009           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3010             :     return 0;
    3011           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3012           0 :     return fastEmitInst_rr(Mips::ILVL_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3013             :   }
    3014             :   return 0;
    3015             : }
    3016             : 
    3017           0 : unsigned fastEmit_MipsISD_ILVL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3018           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3019             :     return 0;
    3020           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3021           0 :     return fastEmitInst_rr(Mips::ILVL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3022             :   }
    3023             :   return 0;
    3024             : }
    3025             : 
    3026           0 : unsigned fastEmit_MipsISD_ILVL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3027           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3028             :     return 0;
    3029           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3030           0 :     return fastEmitInst_rr(Mips::ILVL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3031             :   }
    3032             :   return 0;
    3033             : }
    3034             : 
    3035           0 : unsigned fastEmit_MipsISD_ILVL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3036           0 :   switch (VT.SimpleTy) {
    3037           0 :   case MVT::v16i8: return fastEmit_MipsISD_ILVL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3038           0 :   case MVT::v8i16: return fastEmit_MipsISD_ILVL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3039           0 :   case MVT::v4i32: return fastEmit_MipsISD_ILVL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3040           0 :   case MVT::v2i64: return fastEmit_MipsISD_ILVL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3041             :   default: return 0;
    3042             :   }
    3043             : }
    3044             : 
    3045             : // FastEmit functions for MipsISD::ILVOD.
    3046             : 
    3047           0 : unsigned fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3048           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3049             :     return 0;
    3050           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3051           0 :     return fastEmitInst_rr(Mips::ILVOD_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3052             :   }
    3053             :   return 0;
    3054             : }
    3055             : 
    3056           0 : unsigned fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3057           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3058             :     return 0;
    3059           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3060           0 :     return fastEmitInst_rr(Mips::ILVOD_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3061             :   }
    3062             :   return 0;
    3063             : }
    3064             : 
    3065           0 : unsigned fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3066           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3067             :     return 0;
    3068           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3069           0 :     return fastEmitInst_rr(Mips::ILVOD_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3070             :   }
    3071             :   return 0;
    3072             : }
    3073             : 
    3074           0 : unsigned fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3075           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3076             :     return 0;
    3077           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3078           0 :     return fastEmitInst_rr(Mips::ILVOD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3079             :   }
    3080             :   return 0;
    3081             : }
    3082             : 
    3083           0 : unsigned fastEmit_MipsISD_ILVOD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3084           0 :   switch (VT.SimpleTy) {
    3085           0 :   case MVT::v16i8: return fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3086           0 :   case MVT::v8i16: return fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3087           0 :   case MVT::v4i32: return fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3088           0 :   case MVT::v2i64: return fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3089             :   default: return 0;
    3090             :   }
    3091             : }
    3092             : 
    3093             : // FastEmit functions for MipsISD::ILVR.
    3094             : 
    3095           0 : unsigned fastEmit_MipsISD_ILVR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3096           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3097             :     return 0;
    3098           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3099           0 :     return fastEmitInst_rr(Mips::ILVR_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3100             :   }
    3101             :   return 0;
    3102             : }
    3103             : 
    3104           0 : unsigned fastEmit_MipsISD_ILVR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3105           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3106             :     return 0;
    3107           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3108           0 :     return fastEmitInst_rr(Mips::ILVR_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3109             :   }
    3110             :   return 0;
    3111             : }
    3112             : 
    3113           0 : unsigned fastEmit_MipsISD_ILVR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3114           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3115             :     return 0;
    3116           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3117           0 :     return fastEmitInst_rr(Mips::ILVR_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3118             :   }
    3119             :   return 0;
    3120             : }
    3121             : 
    3122           0 : unsigned fastEmit_MipsISD_ILVR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3123           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3124             :     return 0;
    3125           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3126           0 :     return fastEmitInst_rr(Mips::ILVR_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3127             :   }
    3128             :   return 0;
    3129             : }
    3130             : 
    3131           0 : unsigned fastEmit_MipsISD_ILVR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3132           0 :   switch (VT.SimpleTy) {
    3133           0 :   case MVT::v16i8: return fastEmit_MipsISD_ILVR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3134           0 :   case MVT::v8i16: return fastEmit_MipsISD_ILVR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3135           0 :   case MVT::v4i32: return fastEmit_MipsISD_ILVR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3136           0 :   case MVT::v2i64: return fastEmit_MipsISD_ILVR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3137             :   default: return 0;
    3138             :   }
    3139             : }
    3140             : 
    3141             : // FastEmit functions for MipsISD::MTLOHI.
    3142             : 
    3143             : unsigned fastEmit_MipsISD_MTLOHI_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3144           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    3145             :     return 0;
    3146           0 :   if ((Subtarget->hasStandardEncoding())) {
    3147             :     return fastEmitInst_rr(Mips::PseudoMTLOHI_DSP, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3148             :   }
    3149             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    3150             :     return fastEmitInst_rr(Mips::PseudoMTLOHI, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3151             :   }
    3152             :   return 0;
    3153             : }
    3154             : 
    3155           0 : unsigned fastEmit_MipsISD_MTLOHI_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3156           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    3157             :     return 0;
    3158           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    3159           0 :     return fastEmitInst_rr(Mips::PseudoMTLOHI64, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3160             :   }
    3161             :   return 0;
    3162             : }
    3163             : 
    3164           0 : unsigned fastEmit_MipsISD_MTLOHI_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3165           0 :   switch (VT.SimpleTy) {
    3166           0 :   case MVT::i32: return fastEmit_MipsISD_MTLOHI_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3167           0 :   case MVT::i64: return fastEmit_MipsISD_MTLOHI_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3168             :   default: return 0;
    3169             :   }
    3170             : }
    3171             : 
    3172             : // FastEmit functions for MipsISD::Mult.
    3173             : 
    3174           0 : unsigned fastEmit_MipsISD_Mult_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3175           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    3176             :     return 0;
    3177           0 :   if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
    3178           0 :     return fastEmitInst_rr(Mips::MULT_DSP_MM, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3179             :   }
    3180           0 :   if ((Subtarget->hasDSP())) {
    3181           0 :     return fastEmitInst_rr(Mips::MULT_DSP, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3182             :   }
    3183           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    3184           0 :     return fastEmitInst_rr(Mips::PseudoMULT, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3185             :   }
    3186             :   return 0;
    3187             : }
    3188             : 
    3189           0 : unsigned fastEmit_MipsISD_Mult_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3190           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    3191             :     return 0;
    3192           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    3193           0 :     return fastEmitInst_rr(Mips::PseudoDMULT, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3194             :   }
    3195             :   return 0;
    3196             : }
    3197             : 
    3198           0 : unsigned fastEmit_MipsISD_Mult_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3199           0 :   switch (VT.SimpleTy) {
    3200           0 :   case MVT::i32: return fastEmit_MipsISD_Mult_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3201           0 :   case MVT::i64: return fastEmit_MipsISD_Mult_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3202             :   default: return 0;
    3203             :   }
    3204             : }
    3205             : 
    3206             : // FastEmit functions for MipsISD::Multu.
    3207             : 
    3208           0 : unsigned fastEmit_MipsISD_Multu_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3209           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    3210             :     return 0;
    3211           0 :   if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
    3212           0 :     return fastEmitInst_rr(Mips::MULTU_DSP_MM, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3213             :   }
    3214           0 :   if ((Subtarget->hasDSP())) {
    3215           0 :     return fastEmitInst_rr(Mips::MULTU_DSP, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3216             :   }
    3217           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    3218           0 :     return fastEmitInst_rr(Mips::PseudoMULTu, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3219             :   }
    3220             :   return 0;
    3221             : }
    3222             : 
    3223           0 : unsigned fastEmit_MipsISD_Multu_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3224           0 :   if (RetVT.SimpleTy != MVT::Untyped)
    3225             :     return 0;
    3226           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
    3227           0 :     return fastEmitInst_rr(Mips::PseudoDMULTu, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3228             :   }
    3229             :   return 0;
    3230             : }
    3231             : 
    3232           0 : unsigned fastEmit_MipsISD_Multu_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3233           0 :   switch (VT.SimpleTy) {
    3234           0 :   case MVT::i32: return fastEmit_MipsISD_Multu_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3235           0 :   case MVT::i64: return fastEmit_MipsISD_Multu_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3236             :   default: return 0;
    3237             :   }
    3238             : }
    3239             : 
    3240             : // FastEmit functions for MipsISD::PCKEV.
    3241             : 
    3242           0 : unsigned fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3243           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3244             :     return 0;
    3245           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3246           0 :     return fastEmitInst_rr(Mips::PCKEV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3247             :   }
    3248             :   return 0;
    3249             : }
    3250             : 
    3251           0 : unsigned fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3252           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3253             :     return 0;
    3254           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3255           0 :     return fastEmitInst_rr(Mips::PCKEV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3256             :   }
    3257             :   return 0;
    3258             : }
    3259             : 
    3260           0 : unsigned fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3261           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3262             :     return 0;
    3263           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3264           0 :     return fastEmitInst_rr(Mips::PCKEV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3265             :   }
    3266             :   return 0;
    3267             : }
    3268             : 
    3269           0 : unsigned fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3270           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3271             :     return 0;
    3272           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3273           0 :     return fastEmitInst_rr(Mips::PCKEV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3274             :   }
    3275             :   return 0;
    3276             : }
    3277             : 
    3278           0 : unsigned fastEmit_MipsISD_PCKEV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3279           0 :   switch (VT.SimpleTy) {
    3280           0 :   case MVT::v16i8: return fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3281           0 :   case MVT::v8i16: return fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3282           0 :   case MVT::v4i32: return fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3283           0 :   case MVT::v2i64: return fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3284             :   default: return 0;
    3285             :   }
    3286             : }
    3287             : 
    3288             : // FastEmit functions for MipsISD::PCKOD.
    3289             : 
    3290           0 : unsigned fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3291           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3292             :     return 0;
    3293           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3294           0 :     return fastEmitInst_rr(Mips::PCKOD_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3295             :   }
    3296             :   return 0;
    3297             : }
    3298             : 
    3299           0 : unsigned fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3300           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3301             :     return 0;
    3302           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3303           0 :     return fastEmitInst_rr(Mips::PCKOD_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3304             :   }
    3305             :   return 0;
    3306             : }
    3307             : 
    3308           0 : unsigned fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3309           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3310             :     return 0;
    3311           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3312           0 :     return fastEmitInst_rr(Mips::PCKOD_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3313             :   }
    3314             :   return 0;
    3315             : }
    3316             : 
    3317           0 : unsigned fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3318           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3319             :     return 0;
    3320           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3321           0 :     return fastEmitInst_rr(Mips::PCKOD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3322             :   }
    3323             :   return 0;
    3324             : }
    3325             : 
    3326           0 : unsigned fastEmit_MipsISD_PCKOD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3327           0 :   switch (VT.SimpleTy) {
    3328           0 :   case MVT::v16i8: return fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3329           0 :   case MVT::v8i16: return fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3330           0 :   case MVT::v4i32: return fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3331           0 :   case MVT::v2i64: return fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3332             :   default: return 0;
    3333             :   }
    3334             : }
    3335             : 
    3336             : // FastEmit functions for MipsISD::VNOR.
    3337             : 
    3338           0 : unsigned fastEmit_MipsISD_VNOR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3339           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    3340             :     return 0;
    3341           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3342           0 :     return fastEmitInst_rr(Mips::NOR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3343             :   }
    3344             :   return 0;
    3345             : }
    3346             : 
    3347           0 : unsigned fastEmit_MipsISD_VNOR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3348           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    3349             :     return 0;
    3350           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3351           0 :     return fastEmitInst_rr(Mips::NOR_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3352             :   }
    3353             :   return 0;
    3354             : }
    3355             : 
    3356           0 : unsigned fastEmit_MipsISD_VNOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3357           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3358             :     return 0;
    3359           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3360           0 :     return fastEmitInst_rr(Mips::NOR_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3361             :   }
    3362             :   return 0;
    3363             : }
    3364             : 
    3365           0 : unsigned fastEmit_MipsISD_VNOR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3366           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    3367             :     return 0;
    3368           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3369           0 :     return fastEmitInst_rr(Mips::NOR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    3370             :   }
    3371             :   return 0;
    3372             : }
    3373             : 
    3374           0 : unsigned fastEmit_MipsISD_VNOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    3375           0 :   switch (VT.SimpleTy) {
    3376           0 :   case MVT::v16i8: return fastEmit_MipsISD_VNOR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3377           0 :   case MVT::v8i16: return fastEmit_MipsISD_VNOR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3378           0 :   case MVT::v4i32: return fastEmit_MipsISD_VNOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3379           0 :   case MVT::v2i64: return fastEmit_MipsISD_VNOR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3380             :   default: return 0;
    3381             :   }
    3382             : }
    3383             : 
    3384             : // Top-level FastEmit function.
    3385             : 
    3386          37 : unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) override {
    3387          37 :   switch (Opcode) {
    3388           6 :   case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3389           0 :   case ISD::ADDC: return fastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3390           0 :   case ISD::ADDE: return fastEmit_ISD_ADDE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3391           5 :   case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3392           0 :   case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3393           0 :   case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3394           0 :   case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3395           0 :   case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3396           2 :   case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3397           0 :   case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3398           0 :   case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3399           4 :   case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3400           0 :   case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3401           4 :   case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3402           0 :   case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3403           0 :   case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3404           0 :   case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3405           0 :   case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3406           4 :   case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3407           0 :   case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3408           0 :   case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3409           0 :   case ISD::SUBC: return fastEmit_ISD_SUBC_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3410           4 :   case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3411           0 :   case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3412           0 :   case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3413           4 :   case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3414           4 :   case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3415           0 :   case MipsISD::BuildPairF64: return fastEmit_MipsISD_BuildPairF64_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3416           0 :   case MipsISD::DivRem: return fastEmit_MipsISD_DivRem_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3417           0 :   case MipsISD::DivRem16: return fastEmit_MipsISD_DivRem16_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3418           0 :   case MipsISD::DivRemU: return fastEmit_MipsISD_DivRemU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3419           0 :   case MipsISD::DivRemU16: return fastEmit_MipsISD_DivRemU16_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3420           0 :   case MipsISD::EH_RETURN: return fastEmit_MipsISD_EH_RETURN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3421           0 :   case MipsISD::ILVEV: return fastEmit_MipsISD_ILVEV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3422           0 :   case MipsISD::ILVL: return fastEmit_MipsISD_ILVL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3423           0 :   case MipsISD::ILVOD: return fastEmit_MipsISD_ILVOD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3424           0 :   case MipsISD::ILVR: return fastEmit_MipsISD_ILVR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3425           0 :   case MipsISD::MTLOHI: return fastEmit_MipsISD_MTLOHI_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3426           0 :   case MipsISD::Mult: return fastEmit_MipsISD_Mult_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3427           0 :   case MipsISD::Multu: return fastEmit_MipsISD_Multu_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3428           0 :   case MipsISD::PCKEV: return fastEmit_MipsISD_PCKEV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3429           0 :   case MipsISD::PCKOD: return fastEmit_MipsISD_PCKOD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3430           0 :   case MipsISD::VNOR: return fastEmit_MipsISD_VNOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    3431             :   default: return 0;
    3432             :   }
    3433             : }
    3434             : 
    3435             : // FastEmit functions for MipsISD::ExtractElementF64.
    3436             : 
    3437           0 : unsigned fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3438           0 :   if (RetVT.SimpleTy != MVT::i32)
    3439             :     return 0;
    3440           0 :   if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
    3441           0 :     return fastEmitInst_ri(Mips::ExtractElementF64_64, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3442             :   }
    3443           0 :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
    3444           0 :     return fastEmitInst_ri(Mips::ExtractElementF64, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3445             :   }
    3446             :   return 0;
    3447             : }
    3448             : 
    3449             : unsigned fastEmit_MipsISD_ExtractElementF64_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3450           0 :   switch (VT.SimpleTy) {
    3451           0 :   case MVT::f64: return fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(RetVT, Op0, Op0IsKill, imm1);
    3452             :   default: return 0;
    3453             :   }
    3454             : }
    3455             : 
    3456             : // FastEmit functions for MipsISD::SHLL_DSP.
    3457             : 
    3458             : unsigned fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3459           0 :   if (RetVT.SimpleTy != MVT::v4i8)
    3460             :     return 0;
    3461           0 :   if ((Subtarget->hasDSP())) {
    3462           0 :     return fastEmitInst_ri(Mips::SHLL_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
    3463             :   }
    3464             :   return 0;
    3465             : }
    3466             : 
    3467             : unsigned fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3468           0 :   if (RetVT.SimpleTy != MVT::v2i16)
    3469             :     return 0;
    3470           0 :   if ((Subtarget->hasDSP())) {
    3471           0 :     return fastEmitInst_ri(Mips::SHLL_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
    3472             :   }
    3473             :   return 0;
    3474             : }
    3475             : 
    3476           0 : unsigned fastEmit_MipsISD_SHLL_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3477           0 :   switch (VT.SimpleTy) {
    3478           0 :   case MVT::v4i8: return fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(RetVT, Op0, Op0IsKill, imm1);
    3479           0 :   case MVT::v2i16: return fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(RetVT, Op0, Op0IsKill, imm1);
    3480             :   default: return 0;
    3481             :   }
    3482             : }
    3483             : 
    3484             : // FastEmit functions for MipsISD::SHRA_DSP.
    3485             : 
    3486             : unsigned fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3487           0 :   if (RetVT.SimpleTy != MVT::v4i8)
    3488             :     return 0;
    3489           0 :   if ((Subtarget->hasDSPR2())) {
    3490           0 :     return fastEmitInst_ri(Mips::SHRA_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
    3491             :   }
    3492             :   return 0;
    3493             : }
    3494             : 
    3495             : unsigned fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3496           0 :   if (RetVT.SimpleTy != MVT::v2i16)
    3497             :     return 0;
    3498           0 :   if ((Subtarget->hasDSP())) {
    3499           0 :     return fastEmitInst_ri(Mips::SHRA_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
    3500             :   }
    3501             :   return 0;
    3502             : }
    3503             : 
    3504           0 : unsigned fastEmit_MipsISD_SHRA_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3505           0 :   switch (VT.SimpleTy) {
    3506           0 :   case MVT::v4i8: return fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(RetVT, Op0, Op0IsKill, imm1);
    3507           0 :   case MVT::v2i16: return fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(RetVT, Op0, Op0IsKill, imm1);
    3508             :   default: return 0;
    3509             :   }
    3510             : }
    3511             : 
    3512             : // FastEmit functions for MipsISD::SHRL_DSP.
    3513             : 
    3514             : unsigned fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3515           0 :   if (RetVT.SimpleTy != MVT::v4i8)
    3516             :     return 0;
    3517           0 :   if ((Subtarget->hasDSP())) {
    3518           0 :     return fastEmitInst_ri(Mips::SHRL_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
    3519             :   }
    3520             :   return 0;
    3521             : }
    3522             : 
    3523             : unsigned fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3524           0 :   if (RetVT.SimpleTy != MVT::v2i16)
    3525             :     return 0;
    3526           0 :   if ((Subtarget->hasDSPR2())) {
    3527           0 :     return fastEmitInst_ri(Mips::SHRL_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
    3528             :   }
    3529             :   return 0;
    3530             : }
    3531             : 
    3532           0 : unsigned fastEmit_MipsISD_SHRL_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3533           0 :   switch (VT.SimpleTy) {
    3534           0 :   case MVT::v4i8: return fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(RetVT, Op0, Op0IsKill, imm1);
    3535           0 :   case MVT::v2i16: return fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(RetVT, Op0, Op0IsKill, imm1);
    3536             :   default: return 0;
    3537             :   }
    3538             : }
    3539             : 
    3540             : // Top-level FastEmit function.
    3541             : 
    3542           7 : unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) override {
    3543          14 :   if (VT == MVT::i32 && Predicate_immZExt5(imm1))
    3544           7 :     if (unsigned Reg = fastEmit_ri_Predicate_immZExt5(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3545             :       return Reg;
    3546             : 
    3547          14 :   if (VT == MVT::i32 && Predicate_immZExt6(imm1))
    3548           7 :     if (unsigned Reg = fastEmit_ri_Predicate_immZExt6(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3549             :       return Reg;
    3550             : 
    3551           7 :   if (VT == MVT::iPTR && Predicate_immZExt2Ptr(imm1))
    3552           0 :     if (unsigned Reg = fastEmit_ri_Predicate_immZExt2Ptr(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3553             :       return Reg;
    3554             : 
    3555           7 :   if (VT == MVT::iPTR && Predicate_immZExt1Ptr(imm1))
    3556           0 :     if (unsigned Reg = fastEmit_ri_Predicate_immZExt1Ptr(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3557             :       return Reg;
    3558             : 
    3559           7 :   if (VT == MVT::i32 && Predicate_immZExt4(imm1))
    3560           7 :     if (unsigned Reg = fastEmit_ri_Predicate_immZExt4(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3561             :       return Reg;
    3562             : 
    3563           7 :   if (VT == MVT::i32 && Predicate_immSExtAddiur2(imm1))
    3564           2 :     if (unsigned Reg = fastEmit_ri_Predicate_immSExtAddiur2(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3565             :       return Reg;
    3566             : 
    3567          14 :   if (VT == MVT::i32 && Predicate_immSExtAddius5(imm1))
    3568           8 :     if (unsigned Reg = fastEmit_ri_Predicate_immSExtAddius5(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3569             :       return Reg;
    3570             : 
    3571           7 :   if (VT == MVT::i32 && Predicate_immZExtAndi16(imm1))
    3572           1 :     if (unsigned Reg = fastEmit_ri_Predicate_immZExtAndi16(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3573             :       return Reg;
    3574             : 
    3575          14 :   if (VT == MVT::i32 && Predicate_immZExt2Shift(imm1))
    3576           1 :     if (unsigned Reg = fastEmit_ri_Predicate_immZExt2Shift(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3577             :       return Reg;
    3578             : 
    3579           7 :   switch (Opcode) {
    3580           0 :   case MipsISD::ExtractElementF64: return fastEmit_MipsISD_ExtractElementF64_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    3581           0 :   case MipsISD::SHLL_DSP: return fastEmit_MipsISD_SHLL_DSP_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    3582           0 :   case MipsISD::SHRA_DSP: return fastEmit_MipsISD_SHRA_DSP_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    3583           0 :   case MipsISD::SHRL_DSP: return fastEmit_MipsISD_SHRL_DSP_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    3584             :   default: return 0;
    3585             :   }
    3586             : }
    3587             : 
    3588             : // FastEmit functions for ISD::ROTR.
    3589             : 
    3590           0 : unsigned fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3591           0 :   if (RetVT.SimpleTy != MVT::i32)
    3592             :     return 0;
    3593           0 :   if ((Subtarget->inMicroMipsMode())) {
    3594           0 :     return fastEmitInst_ri(Mips::ROTR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3595             :   }
    3596           0 :   if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3597           0 :     return fastEmitInst_ri(Mips::ROTR, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3598             :   }
    3599             :   return 0;
    3600             : }
    3601             : 
    3602             : unsigned fastEmit_ISD_ROTR_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3603           0 :   switch (VT.SimpleTy) {
    3604           0 :   case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1);
    3605             :   default: return 0;
    3606             :   }
    3607             : }
    3608             : 
    3609             : // FastEmit functions for ISD::SHL.
    3610             : 
    3611           0 : unsigned fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3612           0 :   if (RetVT.SimpleTy != MVT::i32)
    3613             :     return 0;
    3614           0 :   if ((Subtarget->inMicroMipsMode())) {
    3615           0 :     return fastEmitInst_ri(Mips::SLL_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3616             :   }
    3617           0 :   if ((Subtarget->inMips16Mode())) {
    3618           0 :     return fastEmitInst_ri(Mips::SllX16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, imm1);
    3619             :   }
    3620             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3621           0 :     return fastEmitInst_ri(Mips::SLL, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3622             :   }
    3623             :   return 0;
    3624             : }
    3625             : 
    3626             : unsigned fastEmit_ISD_SHL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3627           0 :   switch (VT.SimpleTy) {
    3628           0 :   case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1);
    3629             :   default: return 0;
    3630             :   }
    3631             : }
    3632             : 
    3633             : // FastEmit functions for ISD::SRA.
    3634             : 
    3635           0 : unsigned fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3636           0 :   if (RetVT.SimpleTy != MVT::i32)
    3637             :     return 0;
    3638           0 :   if ((Subtarget->inMicroMipsMode())) {
    3639           0 :     return fastEmitInst_ri(Mips::SRA_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3640             :   }
    3641           0 :   if ((Subtarget->inMips16Mode())) {
    3642           0 :     return fastEmitInst_ri(Mips::SraX16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, imm1);
    3643             :   }
    3644             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3645           0 :     return fastEmitInst_ri(Mips::SRA, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3646             :   }
    3647             :   return 0;
    3648             : }
    3649             : 
    3650             : unsigned fastEmit_ISD_SRA_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3651           0 :   switch (VT.SimpleTy) {
    3652           0 :   case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1);
    3653             :   default: return 0;
    3654             :   }
    3655             : }
    3656             : 
    3657             : // FastEmit functions for ISD::SRL.
    3658             : 
    3659           0 : unsigned fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3660           0 :   if (RetVT.SimpleTy != MVT::i32)
    3661             :     return 0;
    3662           0 :   if ((Subtarget->inMicroMipsMode())) {
    3663           0 :     return fastEmitInst_ri(Mips::SRL_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3664             :   }
    3665           0 :   if ((Subtarget->inMips16Mode())) {
    3666           0 :     return fastEmitInst_ri(Mips::SrlX16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, imm1);
    3667             :   }
    3668             :   if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3669           0 :     return fastEmitInst_ri(Mips::SRL, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3670             :   }
    3671             :   return 0;
    3672             : }
    3673             : 
    3674             : unsigned fastEmit_ISD_SRL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3675           0 :   switch (VT.SimpleTy) {
    3676           0 :   case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1);
    3677             :   default: return 0;
    3678             :   }
    3679             : }
    3680             : 
    3681             : // Top-level FastEmit function.
    3682             : 
    3683           7 : unsigned fastEmit_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3684           7 :   switch (Opcode) {
    3685           0 :   case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1);
    3686           0 :   case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1);
    3687           0 :   case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1);
    3688           0 :   case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1);
    3689             :   default: return 0;
    3690             :   }
    3691             : }
    3692             : 
    3693             : // FastEmit functions for ISD::ROTR.
    3694             : 
    3695           0 : unsigned fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3696           0 :   if (RetVT.SimpleTy != MVT::i64)
    3697             :     return 0;
    3698           0 :   if ((Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3699           0 :     return fastEmitInst_ri(Mips::DROTR, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
    3700             :   }
    3701             :   return 0;
    3702             : }
    3703             : 
    3704             : unsigned fastEmit_ISD_ROTR_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3705           0 :   switch (VT.SimpleTy) {
    3706           0 :   case MVT::i64: return fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1);
    3707             :   default: return 0;
    3708             :   }
    3709             : }
    3710             : 
    3711             : // FastEmit functions for ISD::SHL.
    3712             : 
    3713           0 : unsigned fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3714           0 :   if (RetVT.SimpleTy != MVT::i64)
    3715             :     return 0;
    3716           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3717           0 :     return fastEmitInst_ri(Mips::DSLL, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
    3718             :   }
    3719             :   return 0;
    3720             : }
    3721             : 
    3722             : unsigned fastEmit_ISD_SHL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3723           0 :   switch (VT.SimpleTy) {
    3724           0 :   case MVT::i64: return fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1);
    3725             :   default: return 0;
    3726             :   }
    3727             : }
    3728             : 
    3729             : // FastEmit functions for ISD::SRA.
    3730             : 
    3731           0 : unsigned fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3732           0 :   if (RetVT.SimpleTy != MVT::i64)
    3733             :     return 0;
    3734           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3735           0 :     return fastEmitInst_ri(Mips::DSRA, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
    3736             :   }
    3737             :   return 0;
    3738             : }
    3739             : 
    3740             : unsigned fastEmit_ISD_SRA_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3741           0 :   switch (VT.SimpleTy) {
    3742           0 :   case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1);
    3743             :   default: return 0;
    3744             :   }
    3745             : }
    3746             : 
    3747             : // FastEmit functions for ISD::SRL.
    3748             : 
    3749           0 : unsigned fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3750           0 :   if (RetVT.SimpleTy != MVT::i64)
    3751             :     return 0;
    3752           0 :   if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
    3753           0 :     return fastEmitInst_ri(Mips::DSRL, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
    3754             :   }
    3755             :   return 0;
    3756             : }
    3757             : 
    3758             : unsigned fastEmit_ISD_SRL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3759           0 :   switch (VT.SimpleTy) {
    3760           0 :   case MVT::i64: return fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1);
    3761             :   default: return 0;
    3762             :   }
    3763             : }
    3764             : 
    3765             : // Top-level FastEmit function.
    3766             : 
    3767           7 : unsigned fastEmit_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3768           7 :   switch (Opcode) {
    3769           0 :   case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1);
    3770           0 :   case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1);
    3771           0 :   case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1);
    3772           0 :   case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1);
    3773             :   default: return 0;
    3774             :   }
    3775             : }
    3776             : 
    3777             : // FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
    3778             : 
    3779           0 : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3780           0 :   if (RetVT.SimpleTy != MVT::f32)
    3781             :     return 0;
    3782           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3783           0 :     return fastEmitInst_ri(Mips::COPY_FW_PSEUDO, &Mips::FGR32RegClass, Op0, Op0IsKill, imm1);
    3784             :   }
    3785             :   return 0;
    3786             : }
    3787             : 
    3788             : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3789           0 :   switch (VT.SimpleTy) {
    3790           0 :   case MVT::v4f32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(RetVT, Op0, Op0IsKill, imm1);
    3791             :   default: return 0;
    3792             :   }
    3793             : }
    3794             : 
    3795             : // Top-level FastEmit function.
    3796             : 
    3797           0 : unsigned fastEmit_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3798           0 :   switch (Opcode) {
    3799           0 :   case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(VT, RetVT, Op0, Op0IsKill, imm1);
    3800             :   default: return 0;
    3801             :   }
    3802             : }
    3803             : 
    3804             : // FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
    3805             : 
    3806           0 : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3807           0 :   if (RetVT.SimpleTy != MVT::f64)
    3808             :     return 0;
    3809           0 :   if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
    3810           0 :     return fastEmitInst_ri(Mips::COPY_FD_PSEUDO, &Mips::FGR64RegClass, Op0, Op0IsKill, imm1);
    3811             :   }
    3812             :   return 0;
    3813             : }
    3814             : 
    3815             : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3816           0 :   switch (VT.SimpleTy) {
    3817           0 :   case MVT::v2f64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(RetVT, Op0, Op0IsKill, imm1);
    3818             :   default: return 0;
    3819             :   }
    3820             : }
    3821             : 
    3822             : // Top-level FastEmit function.
    3823             : 
    3824           0 : unsigned fastEmit_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3825           0 :   switch (Opcode) {
    3826           0 :   case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(VT, RetVT, Op0, Op0IsKill, imm1);
    3827             :   default: return 0;
    3828             :   }
    3829             : }
    3830             : 
    3831             : // FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
    3832             : 
    3833             : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3834           0 :   if (RetVT.SimpleTy != MVT::i32)
    3835             :     return 0;
    3836           0 :   if ((Subtarget->hasMSA())) {
    3837           0 :     return fastEmitInst_ri(Mips::COPY_S_W, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3838             :   }
    3839             :   return 0;
    3840             : }
    3841             : 
    3842           0 : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3843           0 :   switch (VT.SimpleTy) {
    3844           0 :   case MVT::v4i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(RetVT, Op0, Op0IsKill, imm1);
    3845             :   default: return 0;
    3846             :   }
    3847             : }
    3848             : 
    3849             : // Top-level FastEmit function.
    3850             : 
    3851             : unsigned fastEmit_ri_Predicate_immZExt4(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3852           7 :   switch (Opcode) {
    3853           0 :   case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(VT, RetVT, Op0, Op0IsKill, imm1);
    3854             :   default: return 0;
    3855             :   }
    3856             : }
    3857             : 
    3858             : // FastEmit functions for ISD::ADD.
    3859             : 
    3860             : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3861           1 :   if (RetVT.SimpleTy != MVT::i32)
    3862             :     return 0;
    3863           1 :   if ((Subtarget->inMicroMipsMode())) {
    3864           0 :     return fastEmitInst_ri(Mips::ADDIUR2_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
    3865             :   }
    3866             :   return 0;
    3867             : }
    3868             : 
    3869           1 : unsigned fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3870           1 :   switch (VT.SimpleTy) {
    3871           1 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(RetVT, Op0, Op0IsKill, imm1);
    3872             :   default: return 0;
    3873             :   }
    3874             : }
    3875             : 
    3876             : // Top-level FastEmit function.
    3877             : 
    3878             : unsigned fastEmit_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3879           1 :   switch (Opcode) {
    3880           1 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(VT, RetVT, Op0, Op0IsKill, imm1);
    3881             :   default: return 0;
    3882             :   }
    3883             : }
    3884             : 
    3885             : // FastEmit functions for ISD::ADD.
    3886             : 
    3887             : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3888           1 :   if (RetVT.SimpleTy != MVT::i32)
    3889             :     return 0;
    3890           1 :   if ((Subtarget->inMicroMipsMode())) {
    3891           0 :     return fastEmitInst_ri(Mips::ADDIUS5_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
    3892             :   }
    3893             :   return 0;
    3894             : }
    3895             : 
    3896           1 : unsigned fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3897           1 :   switch (VT.SimpleTy) {
    3898           1 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(RetVT, Op0, Op0IsKill, imm1);
    3899             :   default: return 0;
    3900             :   }
    3901             : }
    3902             : 
    3903             : // Top-level FastEmit function.
    3904             : 
    3905             : unsigned fastEmit_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3906           7 :   switch (Opcode) {
    3907           1 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(VT, RetVT, Op0, Op0IsKill, imm1);
    3908             :   default: return 0;
    3909             :   }
    3910             : }
    3911             : 
    3912             : // FastEmit functions for ISD::AND.
    3913             : 
    3914           0 : unsigned fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3915           0 :   if (RetVT.SimpleTy != MVT::i32)
    3916             :     return 0;
    3917           0 :   if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
    3918           0 :     return fastEmitInst_ri(Mips::ANDI16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
    3919             :   }
    3920           0 :   if ((Subtarget->inMicroMipsMode())) {
    3921           0 :     return fastEmitInst_ri(Mips::ANDI16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
    3922             :   }
    3923             :   return 0;
    3924             : }
    3925             : 
    3926             : unsigned fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3927           0 :   switch (VT.SimpleTy) {
    3928           0 :   case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(RetVT, Op0, Op0IsKill, imm1);
    3929             :   default: return 0;
    3930             :   }
    3931             : }
    3932             : 
    3933             : // Top-level FastEmit function.
    3934             : 
    3935           1 : unsigned fastEmit_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3936           1 :   switch (Opcode) {
    3937           0 :   case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(VT, RetVT, Op0, Op0IsKill, imm1);
    3938             :   default: return 0;
    3939             :   }
    3940             : }
    3941             : 
    3942             : // FastEmit functions for ISD::SHL.
    3943             : 
    3944             : unsigned fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3945           0 :   if (RetVT.SimpleTy != MVT::i32)
    3946             :     return 0;
    3947           0 :   if ((Subtarget->inMicroMipsMode())) {
    3948           0 :     return fastEmitInst_ri(Mips::SLL16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
    3949             :   }
    3950             :   return 0;
    3951             : }
    3952             : 
    3953           0 : unsigned fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3954           0 :   switch (VT.SimpleTy) {
    3955           0 :   case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, Op0IsKill, imm1);
    3956             :   default: return 0;
    3957             :   }
    3958             : }
    3959             : 
    3960             : // FastEmit functions for ISD::SRL.
    3961             : 
    3962             : unsigned fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3963           0 :   if (RetVT.SimpleTy != MVT::i32)
    3964             :     return 0;
    3965           0 :   if ((Subtarget->inMicroMipsMode())) {
    3966           0 :     return fastEmitInst_ri(Mips::SRL16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
    3967             :   }
    3968             :   return 0;
    3969             : }
    3970             : 
    3971           0 : unsigned fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3972           0 :   switch (VT.SimpleTy) {
    3973           0 :   case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, Op0IsKill, imm1);
    3974             :   default: return 0;
    3975             :   }
    3976             : }
    3977             : 
    3978             : // Top-level FastEmit function.
    3979             : 
    3980           1 : unsigned fastEmit_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3981           1 :   switch (Opcode) {
    3982           0 :   case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, Op0IsKill, imm1);
    3983           0 :   case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, Op0IsKill, imm1);
    3984             :   default: return 0;
    3985             :   }
    3986             : }
    3987             : 
    3988             : // FastEmit functions for ISD::Constant.
    3989             : 
    3990             : unsigned fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) {
    3991           7 :   if (RetVT.SimpleTy != MVT::i32)
    3992             :     return 0;
    3993           7 :   if ((Subtarget->inMips16Mode())) {
    3994           0 :     return fastEmitInst_i(Mips::LwConstant32, &Mips::CPU16RegsRegClass, imm0);
    3995             :   }
    3996             :   return 0;
    3997             : }
    3998             : 
    3999           7 : unsigned fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) {
    4000           7 :   switch (VT.SimpleTy) {
    4001           7 :   case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0);
    4002             :   default: return 0;
    4003             :   }
    4004             : }
    4005             : 
    4006             : // Top-level FastEmit function.
    4007             : 
    4008           7 : unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override {
    4009           7 :   switch (Opcode) {
    4010           7 :   case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0);
    4011             :   default: return 0;
    4012             :   }
    4013             : }
    4014             : 

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