Line data Source code
1 : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2 : |* *|
3 : |* Global Instruction Selector for the Mips target *|
4 : |* *|
5 : |* Automatically generated file, do not edit! *|
6 : |* *|
7 : \*===----------------------------------------------------------------------===*/
8 :
9 : #ifdef GET_GLOBALISEL_PREDICATE_BITSET
10 : const unsigned MAX_SUBTARGET_PREDICATES = 41;
11 : using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
12 : #endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
13 :
14 : #ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15 : mutable MatcherState State;
16 : typedef ComplexRendererFns(MipsInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17 : typedef void(MipsInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&) const;
18 : const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
19 : static MipsInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20 : static MipsInstructionSelector::CustomRendererFn CustomRenderers[];
21 : bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22 : bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23 : bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24 : const int64_t *getMatchTable() const override;
25 : bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
26 : #endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
27 :
28 : #ifdef GET_GLOBALISEL_TEMPORARIES_INIT
29 : , State(0),
30 20614 : ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
31 : #endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
32 :
33 : #ifdef GET_GLOBALISEL_IMPL
34 : // Bits for subtarget features that participate in instruction matching.
35 : enum SubtargetFeatureBits : uint8_t {
36 : Feature_HasMips2Bit = 7,
37 : Feature_HasMips3Bit = 16,
38 : Feature_HasMips4_32Bit = 26,
39 : Feature_NotMips4_32Bit = 27,
40 : Feature_HasMips4_32r2Bit = 17,
41 : Feature_HasMips32Bit = 3,
42 : Feature_HasMips32r2Bit = 6,
43 : Feature_HasMips32r6Bit = 28,
44 : Feature_NotMips32r6Bit = 4,
45 : Feature_IsGP64bitBit = 21,
46 : Feature_IsPTR64bitBit = 23,
47 : Feature_HasMips64Bit = 24,
48 : Feature_HasMips64r2Bit = 22,
49 : Feature_HasMips64r6Bit = 29,
50 : Feature_NotMips64r6Bit = 5,
51 : Feature_InMips16ModeBit = 30,
52 : Feature_NotInMips16ModeBit = 0,
53 : Feature_HasCnMipsBit = 25,
54 : Feature_NotCnMipsBit = 8,
55 : Feature_IsN64Bit = 37,
56 : Feature_RelocNotPICBit = 9,
57 : Feature_RelocPICBit = 36,
58 : Feature_NoNaNsFPMathBit = 20,
59 : Feature_HasStdEncBit = 1,
60 : Feature_NotDSPBit = 11,
61 : Feature_InMicroMipsBit = 34,
62 : Feature_NotInMicroMipsBit = 2,
63 : Feature_IsLEBit = 39,
64 : Feature_IsBEBit = 40,
65 : Feature_IsNotNaClBit = 18,
66 : Feature_HasEVABit = 35,
67 : Feature_HasMSABit = 33,
68 : Feature_HasMadd4Bit = 19,
69 : Feature_UseIndirectJumpsHazardBit = 12,
70 : Feature_NoIndirectJumpGuardsBit = 10,
71 : Feature_AllowFPOpFusionBit = 38,
72 : Feature_IsFP64bitBit = 15,
73 : Feature_NotFP64bitBit = 14,
74 : Feature_IsNotSoftFloatBit = 13,
75 : Feature_HasDSPBit = 31,
76 : Feature_HasDSPR2Bit = 32,
77 : };
78 :
79 0 : PredicateBitset MipsInstructionSelector::
80 : computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const {
81 0 : PredicateBitset Features;
82 0 : if (Subtarget->hasMips2())
83 0 : Features[Feature_HasMips2Bit] = 1;
84 0 : if (Subtarget->hasMips3())
85 0 : Features[Feature_HasMips3Bit] = 1;
86 0 : if (Subtarget->hasMips4_32())
87 0 : Features[Feature_HasMips4_32Bit] = 1;
88 0 : if (!Subtarget->hasMips4_32())
89 0 : Features[Feature_NotMips4_32Bit] = 1;
90 0 : if (Subtarget->hasMips4_32r2())
91 0 : Features[Feature_HasMips4_32r2Bit] = 1;
92 : if (Subtarget->hasMips32())
93 0 : Features[Feature_HasMips32Bit] = 1;
94 : if (Subtarget->hasMips32r2())
95 0 : Features[Feature_HasMips32r2Bit] = 1;
96 : if (Subtarget->hasMips32r6())
97 0 : Features[Feature_HasMips32r6Bit] = 1;
98 : if (!Subtarget->hasMips32r6())
99 0 : Features[Feature_NotMips32r6Bit] = 1;
100 0 : if (Subtarget->isGP64bit())
101 0 : Features[Feature_IsGP64bitBit] = 1;
102 0 : if (Subtarget->isABI_N64())
103 0 : Features[Feature_IsPTR64bitBit] = 1;
104 0 : if (Subtarget->hasMips64())
105 0 : Features[Feature_HasMips64Bit] = 1;
106 0 : if (Subtarget->hasMips64r2())
107 0 : Features[Feature_HasMips64r2Bit] = 1;
108 0 : if (Subtarget->hasMips64r6())
109 0 : Features[Feature_HasMips64r6Bit] = 1;
110 0 : if (!Subtarget->hasMips64r6())
111 0 : Features[Feature_NotMips64r6Bit] = 1;
112 0 : if (Subtarget->inMips16Mode())
113 0 : Features[Feature_InMips16ModeBit] = 1;
114 0 : if (!Subtarget->inMips16Mode())
115 0 : Features[Feature_NotInMips16ModeBit] = 1;
116 0 : if (Subtarget->hasCnMips())
117 0 : Features[Feature_HasCnMipsBit] = 1;
118 0 : if (!Subtarget->hasCnMips())
119 0 : Features[Feature_NotCnMipsBit] = 1;
120 0 : if (Subtarget->isABI_N64())
121 0 : Features[Feature_IsN64Bit] = 1;
122 0 : if (!TM.isPositionIndependent())
123 0 : Features[Feature_RelocNotPICBit] = 1;
124 0 : if (TM.isPositionIndependent())
125 0 : Features[Feature_RelocPICBit] = 1;
126 0 : if (TM.Options.NoNaNsFPMath)
127 0 : Features[Feature_NoNaNsFPMathBit] = 1;
128 0 : if (Subtarget->hasStandardEncoding())
129 0 : Features[Feature_HasStdEncBit] = 1;
130 0 : if (!Subtarget->hasDSP())
131 0 : Features[Feature_NotDSPBit] = 1;
132 0 : if (Subtarget->inMicroMipsMode())
133 0 : Features[Feature_InMicroMipsBit] = 1;
134 : if (!Subtarget->inMicroMipsMode())
135 0 : Features[Feature_NotInMicroMipsBit] = 1;
136 0 : if (Subtarget->isLittle())
137 0 : Features[Feature_IsLEBit] = 1;
138 0 : if (!Subtarget->isLittle())
139 0 : Features[Feature_IsBEBit] = 1;
140 0 : if (!Subtarget->isTargetNaCl())
141 0 : Features[Feature_IsNotNaClBit] = 1;
142 0 : if (Subtarget->hasEVA())
143 0 : Features[Feature_HasEVABit] = 1;
144 0 : if (Subtarget->hasMSA())
145 0 : Features[Feature_HasMSABit] = 1;
146 0 : if (!Subtarget->disableMadd4())
147 0 : Features[Feature_HasMadd4Bit] = 1;
148 : if (Subtarget->useIndirectJumpsHazard())
149 0 : Features[Feature_UseIndirectJumpsHazardBit] = 1;
150 : if (!Subtarget->useIndirectJumpsHazard())
151 0 : Features[Feature_NoIndirectJumpGuardsBit] = 1;
152 0 : if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast)
153 0 : Features[Feature_AllowFPOpFusionBit] = 1;
154 0 : if (Subtarget->isFP64bit())
155 0 : Features[Feature_IsFP64bitBit] = 1;
156 0 : if (!Subtarget->isFP64bit())
157 0 : Features[Feature_NotFP64bitBit] = 1;
158 0 : if (!Subtarget->useSoftFloat())
159 0 : Features[Feature_IsNotSoftFloatBit] = 1;
160 0 : if (Subtarget->hasDSP())
161 0 : Features[Feature_HasDSPBit] = 1;
162 0 : if (Subtarget->hasDSPR2())
163 0 : Features[Feature_HasDSPR2Bit] = 1;
164 0 : return Features;
165 : }
166 :
167 0 : PredicateBitset MipsInstructionSelector::
168 : computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget, const MachineFunction *MF) const {
169 : PredicateBitset Features;
170 0 : return Features;
171 : }
172 :
173 : // LLT Objects.
174 : enum {
175 : GILLT_s16,
176 : GILLT_s32,
177 : GILLT_s64,
178 : GILLT_v2s16,
179 : GILLT_v2s64,
180 : GILLT_v4s8,
181 : GILLT_v4s32,
182 : GILLT_v8s16,
183 : GILLT_v16s8,
184 : };
185 : const static size_t NumTypeObjects = 9;
186 : const static LLT TypeObjects[] = {
187 : LLT::scalar(16),
188 : LLT::scalar(32),
189 : LLT::scalar(64),
190 : LLT::vector(2, 16),
191 : LLT::vector(2, 64),
192 : LLT::vector(4, 8),
193 : LLT::vector(4, 32),
194 : LLT::vector(8, 16),
195 : LLT::vector(16, 8),
196 : };
197 :
198 : // Feature bitsets.
199 : enum {
200 : GIFBS_Invalid,
201 : GIFBS_HasCnMips,
202 : GIFBS_HasDSP,
203 : GIFBS_HasDSPR2,
204 : GIFBS_HasMSA,
205 : GIFBS_InMicroMips,
206 : GIFBS_InMips16Mode,
207 : GIFBS_IsFP64bit,
208 : GIFBS_NotFP64bit,
209 : GIFBS_HasDSP_InMicroMips,
210 : GIFBS_HasDSP_NotInMicroMips,
211 : GIFBS_HasDSPR2_InMicroMips,
212 : GIFBS_HasMSA_HasStdEnc,
213 : GIFBS_HasMSA_IsBE,
214 : GIFBS_HasMSA_IsLE,
215 : GIFBS_HasMips32r6_HasStdEnc,
216 : GIFBS_HasMips32r6_InMicroMips,
217 : GIFBS_HasMips64r2_HasStdEnc,
218 : GIFBS_HasMips64r6_HasStdEnc,
219 : GIFBS_HasStdEnc_IsNotSoftFloat,
220 : GIFBS_HasStdEnc_NotInMicroMips,
221 : GIFBS_HasStdEnc_NotMips4_32,
222 : GIFBS_InMicroMips_IsFP64bit,
223 : GIFBS_InMicroMips_IsNotSoftFloat,
224 : GIFBS_InMicroMips_NotFP64bit,
225 : GIFBS_InMicroMips_NotMips32r6,
226 : GIFBS_IsGP64bit_NotInMips16Mode,
227 : GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
228 : GIFBS_HasMSA_HasMips64_HasStdEnc,
229 : GIFBS_HasMips3_HasStdEnc_IsGP64bit,
230 : GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
231 : GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips,
232 : GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
233 : GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
234 : GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
235 : GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips,
236 : GIFBS_HasStdEnc_IsFP64bit_NotMips4_32,
237 : GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
238 : GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips,
239 : GIFBS_HasStdEnc_NotFP64bit_NotMips4_32,
240 : GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC,
241 : GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
242 : GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
243 : GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
244 : GIFBS_InMicroMips_NotMips32r6_RelocNotPIC,
245 : GIFBS_InMicroMips_NotMips32r6_RelocPIC,
246 : GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
247 : GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
248 : GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6,
249 : GIFBS_HasMips64_HasStdEnc_NotInMicroMips_NotMips64r6,
250 : GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips,
251 : GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
252 : GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
253 : GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
254 : GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
255 : GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotMips32r6_NotMips32r6,
256 : GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
257 : GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
258 : GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
259 : GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
260 : GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
261 : GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6_NotMips32r6,
262 : GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
263 : GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
264 : GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
265 : GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
266 : };
267 : const static PredicateBitset FeatureBitsets[] {
268 : {}, // GIFBS_Invalid
269 : {Feature_HasCnMipsBit, },
270 : {Feature_HasDSPBit, },
271 : {Feature_HasDSPR2Bit, },
272 : {Feature_HasMSABit, },
273 : {Feature_InMicroMipsBit, },
274 : {Feature_InMips16ModeBit, },
275 : {Feature_IsFP64bitBit, },
276 : {Feature_NotFP64bitBit, },
277 : {Feature_HasDSPBit, Feature_InMicroMipsBit, },
278 : {Feature_HasDSPBit, Feature_NotInMicroMipsBit, },
279 : {Feature_HasDSPR2Bit, Feature_InMicroMipsBit, },
280 : {Feature_HasMSABit, Feature_HasStdEncBit, },
281 : {Feature_HasMSABit, Feature_IsBEBit, },
282 : {Feature_HasMSABit, Feature_IsLEBit, },
283 : {Feature_HasMips32r6Bit, Feature_HasStdEncBit, },
284 : {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, },
285 : {Feature_HasMips64r2Bit, Feature_HasStdEncBit, },
286 : {Feature_HasMips64r6Bit, Feature_HasStdEncBit, },
287 : {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, },
288 : {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
289 : {Feature_HasStdEncBit, Feature_NotMips4_32Bit, },
290 : {Feature_InMicroMipsBit, Feature_IsFP64bitBit, },
291 : {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
292 : {Feature_InMicroMipsBit, Feature_NotFP64bitBit, },
293 : {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, },
294 : {Feature_IsGP64bitBit, Feature_NotInMips16ModeBit, },
295 : {Feature_AllowFPOpFusionBit, Feature_HasMSABit, Feature_HasStdEncBit, },
296 : {Feature_HasMSABit, Feature_HasMips64Bit, Feature_HasStdEncBit, },
297 : {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, },
298 : {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
299 : {Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
300 : {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
301 : {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
302 : {Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
303 : {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, },
304 : {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, },
305 : {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
306 : {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
307 : {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, },
308 : {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_RelocNotPICBit, },
309 : {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },
310 : {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, },
311 : {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, },
312 : {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocNotPICBit, },
313 : {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocPICBit, },
314 : {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
315 : {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
316 : {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
317 : {Feature_HasMips64Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips64r6Bit, },
318 : {Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
319 : {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
320 : {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
321 : {Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
322 : {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
323 : {Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotMips32r6Bit, Feature_NotMips32r6Bit, },
324 : {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
325 : {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
326 : {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
327 : {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
328 : {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
329 : {Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips32r6Bit, },
330 : {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
331 : {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
332 : {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
333 : {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
334 : };
335 :
336 : // ComplexPattern predicates.
337 : enum {
338 : GICP_Invalid,
339 : };
340 : // See constructor for table contents
341 :
342 : // PatFrag predicates.
343 : enum {
344 : GIPFP_I64_Predicate_immLi16 = GIPFP_I64_Invalid + 1,
345 : GIPFP_I64_Predicate_immSExt10,
346 : GIPFP_I64_Predicate_immSExt6,
347 : GIPFP_I64_Predicate_immSExtAddiur2,
348 : GIPFP_I64_Predicate_immSExtAddius5,
349 : GIPFP_I64_Predicate_immZExt1,
350 : GIPFP_I64_Predicate_immZExt10,
351 : GIPFP_I64_Predicate_immZExt1Ptr,
352 : GIPFP_I64_Predicate_immZExt2,
353 : GIPFP_I64_Predicate_immZExt2Lsa,
354 : GIPFP_I64_Predicate_immZExt2Ptr,
355 : GIPFP_I64_Predicate_immZExt2Shift,
356 : GIPFP_I64_Predicate_immZExt3,
357 : GIPFP_I64_Predicate_immZExt3Ptr,
358 : GIPFP_I64_Predicate_immZExt4,
359 : GIPFP_I64_Predicate_immZExt4Ptr,
360 : GIPFP_I64_Predicate_immZExt5,
361 : GIPFP_I64_Predicate_immZExt5_64,
362 : GIPFP_I64_Predicate_immZExt6,
363 : GIPFP_I64_Predicate_immZExt8,
364 : GIPFP_I64_Predicate_immZExtAndi16,
365 : GIPFP_I64_Predicate_immi32Cst15,
366 : GIPFP_I64_Predicate_immi32Cst31,
367 : GIPFP_I64_Predicate_immi32Cst7,
368 : };
369 14 : bool MipsInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
370 14 : switch (PredicateID) {
371 0 : case GIPFP_I64_Predicate_immLi16: {
372 0 : return Imm >= -1 && Imm <= 126;
373 : llvm_unreachable("ImmediateCode should have returned");
374 : return false;
375 : }
376 : case GIPFP_I64_Predicate_immSExt10: {
377 0 : return isInt<10>(Imm);
378 : llvm_unreachable("ImmediateCode should have returned");
379 : return false;
380 : }
381 : case GIPFP_I64_Predicate_immSExt6: {
382 0 : return isInt<6>(Imm);
383 : llvm_unreachable("ImmediateCode should have returned");
384 : return false;
385 : }
386 0 : case GIPFP_I64_Predicate_immSExtAddiur2: {
387 0 : return Imm == 1 || Imm == -1 ||
388 0 : ((Imm % 4 == 0) &&
389 0 : Imm < 28 && Imm > 0);
390 : llvm_unreachable("ImmediateCode should have returned");
391 : return false;
392 : }
393 0 : case GIPFP_I64_Predicate_immSExtAddius5: {
394 0 : return Imm >= -8 && Imm <= 7;
395 : llvm_unreachable("ImmediateCode should have returned");
396 : return false;
397 : }
398 0 : case GIPFP_I64_Predicate_immZExt1: {
399 0 : return isUInt<1>(Imm);
400 : llvm_unreachable("ImmediateCode should have returned");
401 : return false;
402 : }
403 0 : case GIPFP_I64_Predicate_immZExt10: {
404 0 : return isUInt<10>(Imm);
405 : llvm_unreachable("ImmediateCode should have returned");
406 : return false;
407 : }
408 0 : case GIPFP_I64_Predicate_immZExt1Ptr: {
409 0 : return isUInt<1>(Imm);
410 : llvm_unreachable("ImmediateCode should have returned");
411 : return false;
412 : }
413 0 : case GIPFP_I64_Predicate_immZExt2: {
414 0 : return isUInt<2>(Imm);
415 : llvm_unreachable("ImmediateCode should have returned");
416 : return false;
417 : }
418 0 : case GIPFP_I64_Predicate_immZExt2Lsa: {
419 0 : return isUInt<2>(Imm - 1);
420 : llvm_unreachable("ImmediateCode should have returned");
421 : return false;
422 : }
423 0 : case GIPFP_I64_Predicate_immZExt2Ptr: {
424 0 : return isUInt<2>(Imm);
425 : llvm_unreachable("ImmediateCode should have returned");
426 : return false;
427 : }
428 0 : case GIPFP_I64_Predicate_immZExt2Shift: {
429 0 : return Imm >= 1 && Imm <= 8;
430 : llvm_unreachable("ImmediateCode should have returned");
431 : return false;
432 : }
433 0 : case GIPFP_I64_Predicate_immZExt3: {
434 0 : return isUInt<3>(Imm);
435 : llvm_unreachable("ImmediateCode should have returned");
436 : return false;
437 : }
438 0 : case GIPFP_I64_Predicate_immZExt3Ptr: {
439 0 : return isUInt<3>(Imm);
440 : llvm_unreachable("ImmediateCode should have returned");
441 : return false;
442 : }
443 0 : case GIPFP_I64_Predicate_immZExt4: {
444 0 : return isUInt<4>(Imm);
445 : llvm_unreachable("ImmediateCode should have returned");
446 : return false;
447 : }
448 0 : case GIPFP_I64_Predicate_immZExt4Ptr: {
449 0 : return isUInt<4>(Imm);
450 : llvm_unreachable("ImmediateCode should have returned");
451 : return false;
452 : }
453 14 : case GIPFP_I64_Predicate_immZExt5: {
454 14 : return Imm == (Imm & 0x1f);
455 : llvm_unreachable("ImmediateCode should have returned");
456 : return false;
457 : }
458 0 : case GIPFP_I64_Predicate_immZExt5_64: {
459 0 : return Imm == (Imm & 0x1f);
460 : llvm_unreachable("ImmediateCode should have returned");
461 : return false;
462 : }
463 0 : case GIPFP_I64_Predicate_immZExt6: {
464 0 : return Imm == (Imm & 0x3f);
465 : llvm_unreachable("ImmediateCode should have returned");
466 : return false;
467 : }
468 0 : case GIPFP_I64_Predicate_immZExt8: {
469 0 : return isUInt<8>(Imm);
470 : llvm_unreachable("ImmediateCode should have returned");
471 : return false;
472 : }
473 0 : case GIPFP_I64_Predicate_immZExtAndi16: {
474 0 : return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
475 0 : Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
476 0 : Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
477 : llvm_unreachable("ImmediateCode should have returned");
478 : return false;
479 : }
480 0 : case GIPFP_I64_Predicate_immi32Cst15: {
481 0 : return isUInt<32>(Imm) && Imm == 15;
482 : llvm_unreachable("ImmediateCode should have returned");
483 : return false;
484 : }
485 0 : case GIPFP_I64_Predicate_immi32Cst31: {
486 0 : return isUInt<32>(Imm) && Imm == 31;
487 : llvm_unreachable("ImmediateCode should have returned");
488 : return false;
489 : }
490 0 : case GIPFP_I64_Predicate_immi32Cst7: {
491 0 : return isUInt<32>(Imm) && Imm == 7;
492 : llvm_unreachable("ImmediateCode should have returned");
493 : return false;
494 : }
495 : }
496 0 : llvm_unreachable("Unknown predicate");
497 : return false;
498 : }
499 0 : bool MipsInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
500 0 : llvm_unreachable("Unknown predicate");
501 : return false;
502 : }
503 0 : bool MipsInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
504 0 : llvm_unreachable("Unknown predicate");
505 : return false;
506 : }
507 0 : bool MipsInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
508 : const MachineFunction &MF = *MI.getParent()->getParent();
509 : const MachineRegisterInfo &MRI = MF.getRegInfo();
510 : (void)MRI;
511 0 : llvm_unreachable("Unknown predicate");
512 : return false;
513 : }
514 :
515 : MipsInstructionSelector::ComplexMatcherMemFn
516 : MipsInstructionSelector::ComplexPredicateFns[] = {
517 : nullptr, // GICP_Invalid
518 : };
519 :
520 : // Custom renderers.
521 : enum {
522 : GICR_Invalid,
523 : };
524 : MipsInstructionSelector::CustomRendererFn
525 : MipsInstructionSelector::CustomRenderers[] = {
526 : nullptr, // GICP_Invalid
527 : };
528 :
529 144 : bool MipsInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
530 144 : MachineFunction &MF = *I.getParent()->getParent();
531 144 : MachineRegisterInfo &MRI = MF.getRegInfo();
532 : // FIXME: This should be computed on a per-function basis rather than per-insn.
533 144 : AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);
534 144 : const PredicateBitset AvailableFeatures = getAvailableFeatures();
535 : NewMIVector OutMIs;
536 : State.MIs.clear();
537 144 : State.MIs.push_back(&I);
538 :
539 144 : if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
540 64 : return true;
541 : }
542 :
543 : return false;
544 : }
545 :
546 0 : const int64_t *MipsInstructionSelector::getMatchTable() const {
547 : constexpr static int64_t MatchTable0[] = {
548 : GIM_SwitchOpcode, /*MI*/0, /*[*/34, 135, /*)*//*default:*//*Label 42*/ 38274,
549 : /*TargetOpcode::G_ADD*//*Label 0*/ 106,
550 : /*TargetOpcode::G_SUB*//*Label 1*/ 1283,
551 : /*TargetOpcode::G_MUL*//*Label 2*/ 1895,
552 : /*TargetOpcode::G_SDIV*//*Label 3*/ 2271,
553 : /*TargetOpcode::G_UDIV*//*Label 4*/ 2492,
554 : /*TargetOpcode::G_SREM*//*Label 5*/ 2713,
555 : /*TargetOpcode::G_UREM*//*Label 6*/ 2934,
556 : /*TargetOpcode::G_AND*//*Label 7*/ 3155,
557 : /*TargetOpcode::G_OR*//*Label 8*/ 3599,
558 : /*TargetOpcode::G_XOR*//*Label 9*/ 3901, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
559 : /*TargetOpcode::G_BITCAST*//*Label 10*/ 4695, 0, 0,
560 : /*TargetOpcode::G_LOAD*//*Label 11*/ 8348,
561 : /*TargetOpcode::G_SEXTLOAD*//*Label 12*/ 8414,
562 : /*TargetOpcode::G_ZEXTLOAD*//*Label 13*/ 8480, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
563 : /*TargetOpcode::G_INTRINSIC*//*Label 14*/ 8546,
564 : /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 15*/ 25057, 0,
565 : /*TargetOpcode::G_TRUNC*//*Label 16*/ 29981,
566 : /*TargetOpcode::G_CONSTANT*//*Label 17*/ 30038, 0, 0, 0,
567 : /*TargetOpcode::G_SEXT*//*Label 18*/ 30098,
568 : /*TargetOpcode::G_ZEXT*//*Label 19*/ 30126,
569 : /*TargetOpcode::G_SHL*//*Label 20*/ 30211,
570 : /*TargetOpcode::G_LSHR*//*Label 21*/ 30735,
571 : /*TargetOpcode::G_ASHR*//*Label 22*/ 31259, 0, 0,
572 : /*TargetOpcode::G_SELECT*//*Label 23*/ 31740, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
573 : /*TargetOpcode::G_FADD*//*Label 24*/ 33194,
574 : /*TargetOpcode::G_FSUB*//*Label 25*/ 34073,
575 : /*TargetOpcode::G_FMUL*//*Label 26*/ 34649,
576 : /*TargetOpcode::G_FMA*//*Label 27*/ 35086,
577 : /*TargetOpcode::G_FDIV*//*Label 28*/ 35176, 0, 0, 0,
578 : /*TargetOpcode::G_FEXP2*//*Label 29*/ 35427, 0,
579 : /*TargetOpcode::G_FLOG2*//*Label 30*/ 35485,
580 : /*TargetOpcode::G_FNEG*//*Label 31*/ 35543,
581 : /*TargetOpcode::G_FPEXT*//*Label 32*/ 36839,
582 : /*TargetOpcode::G_FPTRUNC*//*Label 33*/ 36988,
583 : /*TargetOpcode::G_FPTOSI*//*Label 34*/ 37116,
584 : /*TargetOpcode::G_FPTOUI*//*Label 35*/ 37174,
585 : /*TargetOpcode::G_SITOFP*//*Label 36*/ 37232,
586 : /*TargetOpcode::G_UITOFP*//*Label 37*/ 37385, 0, 0, 0,
587 : /*TargetOpcode::G_BR*//*Label 38*/ 37443, 0, 0, 0, 0, 0,
588 : /*TargetOpcode::G_CTLZ*//*Label 39*/ 37528, 0,
589 : /*TargetOpcode::G_CTPOP*//*Label 40*/ 37963,
590 : /*TargetOpcode::G_BSWAP*//*Label 41*/ 38122,
591 : // Label 0: @106
592 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 51*/ 1282,
593 : /*GILLT_s32*//*Label 43*/ 120,
594 : /*GILLT_s64*//*Label 44*/ 469,
595 : /*GILLT_v2s16*//*Label 45*/ 632,
596 : /*GILLT_v2s64*//*Label 46*/ 659,
597 : /*GILLT_v4s8*//*Label 47*/ 808,
598 : /*GILLT_v4s32*//*Label 48*/ 835,
599 : /*GILLT_v8s16*//*Label 49*/ 984,
600 : /*GILLT_v16s8*//*Label 50*/ 1133,
601 : // Label 43: @120
602 : GIM_Try, /*On fail goto*//*Label 52*/ 468,
603 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
604 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
605 : GIM_Try, /*On fail goto*//*Label 53*/ 198, // Rule ID 2309 //
606 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
607 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
608 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
609 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
610 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
611 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
612 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
613 : GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
614 : GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
615 : GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
616 : // MIs[2] Operand 1
617 : // No operand predicates
618 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
619 : GIM_CheckIsSafeToFold, /*InsnID*/1,
620 : GIM_CheckIsSafeToFold, /*InsnID*/2,
621 : // (add:{ *:[i32] } (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR32Opnd:{ *:[i32] }:$rt) => (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
622 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LSA,
623 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
624 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
625 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
626 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
627 : GIR_EraseFromParent, /*InsnID*/0,
628 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
629 : // GIR_Coverage, 2309,
630 : GIR_Done,
631 : // Label 53: @198
632 : GIM_Try, /*On fail goto*//*Label 54*/ 266, // Rule ID 802 //
633 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
634 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
635 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
636 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
637 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
638 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
639 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
640 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
641 : GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
642 : GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
643 : GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
644 : // MIs[2] Operand 1
645 : // No operand predicates
646 : GIM_CheckIsSafeToFold, /*InsnID*/1,
647 : GIM_CheckIsSafeToFold, /*InsnID*/2,
648 : // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa)) => (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
649 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LSA,
650 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
651 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
652 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
653 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
654 : GIR_EraseFromParent, /*InsnID*/0,
655 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
656 : // GIR_Coverage, 802,
657 : GIR_Done,
658 : // Label 54: @266
659 : GIM_Try, /*On fail goto*//*Label 55*/ 309, // Rule ID 2084 //
660 : GIM_CheckFeatures, GIFBS_InMicroMips,
661 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
662 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
663 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
664 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
665 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExtAddiur2,
666 : // MIs[1] Operand 1
667 : // No operand predicates
668 : GIM_CheckIsSafeToFold, /*InsnID*/1,
669 : // (add:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm) => (ADDIUR2_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm)
670 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDIUR2_MM,
671 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
672 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
673 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
674 : GIR_EraseFromParent, /*InsnID*/0,
675 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
676 : // GIR_Coverage, 2084,
677 : GIR_Done,
678 : // Label 55: @309
679 : GIM_Try, /*On fail goto*//*Label 56*/ 352, // Rule ID 2085 //
680 : GIM_CheckFeatures, GIFBS_InMicroMips,
681 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
682 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
683 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
684 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
685 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExtAddius5,
686 : // MIs[1] Operand 1
687 : // No operand predicates
688 : GIM_CheckIsSafeToFold, /*InsnID*/1,
689 : // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm) => (ADDIUS5_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm)
690 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDIUS5_MM,
691 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
692 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
693 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
694 : GIR_EraseFromParent, /*InsnID*/0,
695 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
696 : // GIR_Coverage, 2085,
697 : GIR_Done,
698 : // Label 56: @352
699 : GIM_Try, /*On fail goto*//*Label 57*/ 375, // Rule ID 1174 //
700 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
701 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
702 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
703 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
704 : // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (ADDU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
705 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU16_MMR6,
706 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
707 : // GIR_Coverage, 1174,
708 : GIR_Done,
709 : // Label 57: @375
710 : GIM_Try, /*On fail goto*//*Label 58*/ 398, // Rule ID 34 //
711 : GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
712 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
713 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
714 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
715 : // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
716 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDu,
717 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
718 : // GIR_Coverage, 34,
719 : GIR_Done,
720 : // Label 58: @398
721 : GIM_Try, /*On fail goto*//*Label 59*/ 421, // Rule ID 1028 //
722 : GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
723 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
724 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
725 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
726 : // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (ADDU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
727 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU16_MM,
728 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
729 : // GIR_Coverage, 1028,
730 : GIR_Done,
731 : // Label 59: @421
732 : GIM_Try, /*On fail goto*//*Label 60*/ 444, // Rule ID 1040 //
733 : GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
734 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
735 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
736 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
737 : // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
738 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDu_MM,
739 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
740 : // GIR_Coverage, 1040,
741 : GIR_Done,
742 : // Label 60: @444
743 : GIM_Try, /*On fail goto*//*Label 61*/ 467, // Rule ID 1745 //
744 : GIM_CheckFeatures, GIFBS_InMips16Mode,
745 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
746 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
747 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
748 : // (add:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (AdduRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
749 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AdduRxRyRz16,
750 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
751 : // GIR_Coverage, 1745,
752 : GIR_Done,
753 : // Label 61: @467
754 : GIM_Reject,
755 : // Label 52: @468
756 : GIM_Reject,
757 : // Label 44: @469
758 : GIM_Try, /*On fail goto*//*Label 62*/ 631,
759 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
760 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
761 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
762 : GIM_Try, /*On fail goto*//*Label 63*/ 547, // Rule ID 2310 //
763 : GIM_CheckFeatures, GIFBS_HasMSA_HasMips64_HasStdEnc,
764 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
765 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
766 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
767 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
768 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
769 : GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
770 : GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
771 : GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
772 : // MIs[2] Operand 1
773 : // No operand predicates
774 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
775 : GIM_CheckIsSafeToFold, /*InsnID*/1,
776 : GIM_CheckIsSafeToFold, /*InsnID*/2,
777 : // (add:{ *:[i64] } (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR64Opnd:{ *:[i64] }:$rt) => (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
778 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DLSA,
779 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
780 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
781 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
782 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
783 : GIR_EraseFromParent, /*InsnID*/0,
784 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
785 : // GIR_Coverage, 2310,
786 : GIR_Done,
787 : // Label 63: @547
788 : GIM_Try, /*On fail goto*//*Label 64*/ 611, // Rule ID 803 //
789 : GIM_CheckFeatures, GIFBS_HasMSA_HasMips64_HasStdEnc,
790 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
791 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
792 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
793 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
794 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
795 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
796 : GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
797 : GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
798 : GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
799 : // MIs[2] Operand 1
800 : // No operand predicates
801 : GIM_CheckIsSafeToFold, /*InsnID*/1,
802 : GIM_CheckIsSafeToFold, /*InsnID*/2,
803 : // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa)) => (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
804 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DLSA,
805 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
806 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
807 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
808 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
809 : GIR_EraseFromParent, /*InsnID*/0,
810 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
811 : // GIR_Coverage, 803,
812 : GIR_Done,
813 : // Label 64: @611
814 : GIM_Try, /*On fail goto*//*Label 65*/ 630, // Rule ID 180 //
815 : GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
816 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
817 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
818 : // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
819 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DADDu,
820 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
821 : // GIR_Coverage, 180,
822 : GIR_Done,
823 : // Label 65: @630
824 : GIM_Reject,
825 : // Label 62: @631
826 : GIM_Reject,
827 : // Label 45: @632
828 : GIM_Try, /*On fail goto*//*Label 66*/ 658, // Rule ID 1844 //
829 : GIM_CheckFeatures, GIFBS_HasDSP,
830 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
831 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
832 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
833 : // (add:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
834 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDQ_PH,
835 : GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
836 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
837 : // GIR_Coverage, 1844,
838 : GIR_Done,
839 : // Label 66: @658
840 : GIM_Reject,
841 : // Label 46: @659
842 : GIM_Try, /*On fail goto*//*Label 67*/ 807,
843 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
844 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
845 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
846 : GIM_Try, /*On fail goto*//*Label 68*/ 730, // Rule ID 2314 //
847 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
848 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
849 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
850 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
851 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
852 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
853 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
854 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
855 : GIM_CheckIsSafeToFold, /*InsnID*/1,
856 : // (add:{ *:[v2i64] } (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt), MSA128DOpnd:{ *:[v2i64] }:$wd_in) => (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
857 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_D,
858 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
859 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
860 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
861 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
862 : GIR_EraseFromParent, /*InsnID*/0,
863 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
864 : // GIR_Coverage, 2314,
865 : GIR_Done,
866 : // Label 68: @730
867 : GIM_Try, /*On fail goto*//*Label 69*/ 787, // Rule ID 811 //
868 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
869 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
870 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
871 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
872 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
873 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
874 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
875 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
876 : GIM_CheckIsSafeToFold, /*InsnID*/1,
877 : // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)) => (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
878 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_D,
879 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
880 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
881 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
882 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
883 : GIR_EraseFromParent, /*InsnID*/0,
884 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
885 : // GIR_Coverage, 811,
886 : GIR_Done,
887 : // Label 69: @787
888 : GIM_Try, /*On fail goto*//*Label 70*/ 806, // Rule ID 478 //
889 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
890 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
891 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
892 : // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
893 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_D,
894 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
895 : // GIR_Coverage, 478,
896 : GIR_Done,
897 : // Label 70: @806
898 : GIM_Reject,
899 : // Label 67: @807
900 : GIM_Reject,
901 : // Label 47: @808
902 : GIM_Try, /*On fail goto*//*Label 71*/ 834, // Rule ID 1850 //
903 : GIM_CheckFeatures, GIFBS_HasDSP,
904 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
905 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
906 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
907 : // (add:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
908 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU_QB,
909 : GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
910 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
911 : // GIR_Coverage, 1850,
912 : GIR_Done,
913 : // Label 71: @834
914 : GIM_Reject,
915 : // Label 48: @835
916 : GIM_Try, /*On fail goto*//*Label 72*/ 983,
917 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
918 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
919 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
920 : GIM_Try, /*On fail goto*//*Label 73*/ 906, // Rule ID 2313 //
921 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
922 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
923 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
924 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
925 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
926 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
927 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
928 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
929 : GIM_CheckIsSafeToFold, /*InsnID*/1,
930 : // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt), MSA128WOpnd:{ *:[v4i32] }:$wd_in) => (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
931 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_W,
932 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
933 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
934 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
935 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
936 : GIR_EraseFromParent, /*InsnID*/0,
937 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
938 : // GIR_Coverage, 2313,
939 : GIR_Done,
940 : // Label 73: @906
941 : GIM_Try, /*On fail goto*//*Label 74*/ 963, // Rule ID 810 //
942 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
943 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
944 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
945 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
946 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
947 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
948 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
949 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
950 : GIM_CheckIsSafeToFold, /*InsnID*/1,
951 : // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)) => (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
952 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_W,
953 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
954 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
955 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
956 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
957 : GIR_EraseFromParent, /*InsnID*/0,
958 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
959 : // GIR_Coverage, 810,
960 : GIR_Done,
961 : // Label 74: @963
962 : GIM_Try, /*On fail goto*//*Label 75*/ 982, // Rule ID 477 //
963 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
964 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
965 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
966 : // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
967 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_W,
968 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
969 : // GIR_Coverage, 477,
970 : GIR_Done,
971 : // Label 75: @982
972 : GIM_Reject,
973 : // Label 72: @983
974 : GIM_Reject,
975 : // Label 49: @984
976 : GIM_Try, /*On fail goto*//*Label 76*/ 1132,
977 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
978 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
979 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
980 : GIM_Try, /*On fail goto*//*Label 77*/ 1055, // Rule ID 2312 //
981 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
982 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
983 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
984 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
985 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
986 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
987 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
988 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
989 : GIM_CheckIsSafeToFold, /*InsnID*/1,
990 : // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt), MSA128HOpnd:{ *:[v8i16] }:$wd_in) => (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
991 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_H,
992 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
993 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
994 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
995 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
996 : GIR_EraseFromParent, /*InsnID*/0,
997 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
998 : // GIR_Coverage, 2312,
999 : GIR_Done,
1000 : // Label 77: @1055
1001 : GIM_Try, /*On fail goto*//*Label 78*/ 1112, // Rule ID 809 //
1002 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1003 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1004 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1005 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1006 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1007 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1008 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1009 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1010 : GIM_CheckIsSafeToFold, /*InsnID*/1,
1011 : // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)) => (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1012 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_H,
1013 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1014 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1015 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1016 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1017 : GIR_EraseFromParent, /*InsnID*/0,
1018 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1019 : // GIR_Coverage, 809,
1020 : GIR_Done,
1021 : // Label 78: @1112
1022 : GIM_Try, /*On fail goto*//*Label 79*/ 1131, // Rule ID 476 //
1023 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1024 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1025 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1026 : // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1027 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_H,
1028 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1029 : // GIR_Coverage, 476,
1030 : GIR_Done,
1031 : // Label 79: @1131
1032 : GIM_Reject,
1033 : // Label 76: @1132
1034 : GIM_Reject,
1035 : // Label 50: @1133
1036 : GIM_Try, /*On fail goto*//*Label 80*/ 1281,
1037 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1038 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1039 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1040 : GIM_Try, /*On fail goto*//*Label 81*/ 1204, // Rule ID 2311 //
1041 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1042 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1043 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1044 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1045 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1046 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1047 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1048 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1049 : GIM_CheckIsSafeToFold, /*InsnID*/1,
1050 : // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt), MSA128BOpnd:{ *:[v16i8] }:$wd_in) => (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1051 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_B,
1052 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1053 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
1054 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1055 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1056 : GIR_EraseFromParent, /*InsnID*/0,
1057 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1058 : // GIR_Coverage, 2311,
1059 : GIR_Done,
1060 : // Label 81: @1204
1061 : GIM_Try, /*On fail goto*//*Label 82*/ 1261, // Rule ID 808 //
1062 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1063 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1064 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1065 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1066 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1067 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1068 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1069 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1070 : GIM_CheckIsSafeToFold, /*InsnID*/1,
1071 : // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)) => (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1072 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_B,
1073 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1074 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1075 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1076 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1077 : GIR_EraseFromParent, /*InsnID*/0,
1078 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1079 : // GIR_Coverage, 808,
1080 : GIR_Done,
1081 : // Label 82: @1261
1082 : GIM_Try, /*On fail goto*//*Label 83*/ 1280, // Rule ID 475 //
1083 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1084 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1085 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1086 : // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1087 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_B,
1088 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1089 : // GIR_Coverage, 475,
1090 : GIR_Done,
1091 : // Label 83: @1280
1092 : GIM_Reject,
1093 : // Label 80: @1281
1094 : GIM_Reject,
1095 : // Label 51: @1282
1096 : GIM_Reject,
1097 : // Label 1: @1283
1098 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 92*/ 1894,
1099 : /*GILLT_s32*//*Label 84*/ 1297,
1100 : /*GILLT_s64*//*Label 85*/ 1456,
1101 : /*GILLT_v2s16*//*Label 86*/ 1488,
1102 : /*GILLT_v2s64*//*Label 87*/ 1515,
1103 : /*GILLT_v4s8*//*Label 88*/ 1603,
1104 : /*GILLT_v4s32*//*Label 89*/ 1630,
1105 : /*GILLT_v8s16*//*Label 90*/ 1718,
1106 : /*GILLT_v16s8*//*Label 91*/ 1806,
1107 : // Label 84: @1297
1108 : GIM_Try, /*On fail goto*//*Label 93*/ 1455,
1109 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1110 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1111 : GIM_Try, /*On fail goto*//*Label 94*/ 1339, // Rule ID 1744 //
1112 : GIM_CheckFeatures, GIFBS_InMips16Mode,
1113 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
1114 : GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
1115 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
1116 : // (sub:{ *:[i32] } 0:{ *:[i32] }, CPU16Regs:{ *:[i32] }:$r) => (NegRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
1117 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NegRxRy16,
1118 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
1119 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // r
1120 : GIR_EraseFromParent, /*InsnID*/0,
1121 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1122 : // GIR_Coverage, 1744,
1123 : GIR_Done,
1124 : // Label 94: @1339
1125 : GIM_Try, /*On fail goto*//*Label 95*/ 1362, // Rule ID 1176 //
1126 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1127 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
1128 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
1129 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
1130 : // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (SUBU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
1131 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU16_MMR6,
1132 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1133 : // GIR_Coverage, 1176,
1134 : GIR_Done,
1135 : // Label 95: @1362
1136 : GIM_Try, /*On fail goto*//*Label 96*/ 1385, // Rule ID 35 //
1137 : GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
1138 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1139 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1140 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1141 : // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1142 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBu,
1143 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1144 : // GIR_Coverage, 35,
1145 : GIR_Done,
1146 : // Label 96: @1385
1147 : GIM_Try, /*On fail goto*//*Label 97*/ 1408, // Rule ID 1032 //
1148 : GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
1149 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
1150 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
1151 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
1152 : // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (SUBU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
1153 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU16_MM,
1154 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1155 : // GIR_Coverage, 1032,
1156 : GIR_Done,
1157 : // Label 97: @1408
1158 : GIM_Try, /*On fail goto*//*Label 98*/ 1431, // Rule ID 1041 //
1159 : GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
1160 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1161 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1162 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1163 : // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1164 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBu_MM,
1165 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1166 : // GIR_Coverage, 1041,
1167 : GIR_Done,
1168 : // Label 98: @1431
1169 : GIM_Try, /*On fail goto*//*Label 99*/ 1454, // Rule ID 1749 //
1170 : GIM_CheckFeatures, GIFBS_InMips16Mode,
1171 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
1172 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
1173 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
1174 : // (sub:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (SubuRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
1175 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SubuRxRyRz16,
1176 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1177 : // GIR_Coverage, 1749,
1178 : GIR_Done,
1179 : // Label 99: @1454
1180 : GIM_Reject,
1181 : // Label 93: @1455
1182 : GIM_Reject,
1183 : // Label 85: @1456
1184 : GIM_Try, /*On fail goto*//*Label 100*/ 1487, // Rule ID 181 //
1185 : GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
1186 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1187 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1188 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1189 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1190 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1191 : // (sub:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DSUBu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1192 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSUBu,
1193 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1194 : // GIR_Coverage, 181,
1195 : GIR_Done,
1196 : // Label 100: @1487
1197 : GIM_Reject,
1198 : // Label 86: @1488
1199 : GIM_Try, /*On fail goto*//*Label 101*/ 1514, // Rule ID 1846 //
1200 : GIM_CheckFeatures, GIFBS_HasDSP,
1201 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1202 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
1203 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
1204 : // (sub:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1205 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBQ_PH,
1206 : GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
1207 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1208 : // GIR_Coverage, 1846,
1209 : GIR_Done,
1210 : // Label 101: @1514
1211 : GIM_Reject,
1212 : // Label 87: @1515
1213 : GIM_Try, /*On fail goto*//*Label 102*/ 1602,
1214 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1215 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1216 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1217 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1218 : GIM_Try, /*On fail goto*//*Label 103*/ 1586, // Rule ID 867 //
1219 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1220 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1221 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1222 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
1223 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
1224 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1225 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1226 : GIM_CheckIsSafeToFold, /*InsnID*/1,
1227 : // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)) => (MSUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1228 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_D,
1229 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1230 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1231 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1232 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1233 : GIR_EraseFromParent, /*InsnID*/0,
1234 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1235 : // GIR_Coverage, 867,
1236 : GIR_Done,
1237 : // Label 103: @1586
1238 : GIM_Try, /*On fail goto*//*Label 104*/ 1601, // Rule ID 996 //
1239 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1240 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1241 : // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1242 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_D,
1243 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1244 : // GIR_Coverage, 996,
1245 : GIR_Done,
1246 : // Label 104: @1601
1247 : GIM_Reject,
1248 : // Label 102: @1602
1249 : GIM_Reject,
1250 : // Label 88: @1603
1251 : GIM_Try, /*On fail goto*//*Label 105*/ 1629, // Rule ID 1852 //
1252 : GIM_CheckFeatures, GIFBS_HasDSP,
1253 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
1254 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
1255 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
1256 : // (sub:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
1257 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU_QB,
1258 : GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
1259 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1260 : // GIR_Coverage, 1852,
1261 : GIR_Done,
1262 : // Label 105: @1629
1263 : GIM_Reject,
1264 : // Label 89: @1630
1265 : GIM_Try, /*On fail goto*//*Label 106*/ 1717,
1266 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1267 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1268 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1269 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1270 : GIM_Try, /*On fail goto*//*Label 107*/ 1701, // Rule ID 866 //
1271 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1272 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1273 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1274 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1275 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1276 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1277 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1278 : GIM_CheckIsSafeToFold, /*InsnID*/1,
1279 : // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)) => (MSUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1280 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_W,
1281 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1282 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1283 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1284 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1285 : GIR_EraseFromParent, /*InsnID*/0,
1286 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1287 : // GIR_Coverage, 866,
1288 : GIR_Done,
1289 : // Label 107: @1701
1290 : GIM_Try, /*On fail goto*//*Label 108*/ 1716, // Rule ID 995 //
1291 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1292 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1293 : // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1294 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_W,
1295 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1296 : // GIR_Coverage, 995,
1297 : GIR_Done,
1298 : // Label 108: @1716
1299 : GIM_Reject,
1300 : // Label 106: @1717
1301 : GIM_Reject,
1302 : // Label 90: @1718
1303 : GIM_Try, /*On fail goto*//*Label 109*/ 1805,
1304 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1305 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1306 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1307 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1308 : GIM_Try, /*On fail goto*//*Label 110*/ 1789, // Rule ID 865 //
1309 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1310 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1311 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1312 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1313 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1314 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1315 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1316 : GIM_CheckIsSafeToFold, /*InsnID*/1,
1317 : // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)) => (MSUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1318 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_H,
1319 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1320 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1321 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1322 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1323 : GIR_EraseFromParent, /*InsnID*/0,
1324 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1325 : // GIR_Coverage, 865,
1326 : GIR_Done,
1327 : // Label 110: @1789
1328 : GIM_Try, /*On fail goto*//*Label 111*/ 1804, // Rule ID 994 //
1329 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1330 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1331 : // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1332 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_H,
1333 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1334 : // GIR_Coverage, 994,
1335 : GIR_Done,
1336 : // Label 111: @1804
1337 : GIM_Reject,
1338 : // Label 109: @1805
1339 : GIM_Reject,
1340 : // Label 91: @1806
1341 : GIM_Try, /*On fail goto*//*Label 112*/ 1893,
1342 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1343 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1344 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1345 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1346 : GIM_Try, /*On fail goto*//*Label 113*/ 1877, // Rule ID 864 //
1347 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1348 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1349 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1350 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1351 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1352 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1353 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1354 : GIM_CheckIsSafeToFold, /*InsnID*/1,
1355 : // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)) => (MSUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1356 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_B,
1357 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1358 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1359 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1360 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1361 : GIR_EraseFromParent, /*InsnID*/0,
1362 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1363 : // GIR_Coverage, 864,
1364 : GIR_Done,
1365 : // Label 113: @1877
1366 : GIM_Try, /*On fail goto*//*Label 114*/ 1892, // Rule ID 993 //
1367 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1368 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1369 : // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1370 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_B,
1371 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1372 : // GIR_Coverage, 993,
1373 : GIR_Done,
1374 : // Label 114: @1892
1375 : GIM_Reject,
1376 : // Label 112: @1893
1377 : GIM_Reject,
1378 : // Label 92: @1894
1379 : GIM_Reject,
1380 : // Label 2: @1895
1381 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 122*/ 2270,
1382 : /*GILLT_s32*//*Label 115*/ 1909,
1383 : /*GILLT_s64*//*Label 116*/ 2054,
1384 : /*GILLT_v2s16*//*Label 117*/ 2115,
1385 : /*GILLT_v2s64*//*Label 118*/ 2142, 0,
1386 : /*GILLT_v4s32*//*Label 119*/ 2174,
1387 : /*GILLT_v8s16*//*Label 120*/ 2206,
1388 : /*GILLT_v16s8*//*Label 121*/ 2238,
1389 : // Label 115: @1909
1390 : GIM_Try, /*On fail goto*//*Label 123*/ 2053,
1391 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1392 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1393 : GIM_Try, /*On fail goto*//*Label 124*/ 1948, // Rule ID 36 //
1394 : GIM_CheckFeatures, GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
1395 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1396 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1397 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1398 : // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1399 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL,
1400 : GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1401 : GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1402 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1403 : // GIR_Coverage, 36,
1404 : GIR_Done,
1405 : // Label 124: @1948
1406 : GIM_Try, /*On fail goto*//*Label 125*/ 1971, // Rule ID 304 //
1407 : GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1408 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1409 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1410 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1411 : // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1412 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_R6,
1413 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1414 : // GIR_Coverage, 304,
1415 : GIR_Done,
1416 : // Label 125: @1971
1417 : GIM_Try, /*On fail goto*//*Label 126*/ 2000, // Rule ID 1042 //
1418 : GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
1419 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1420 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1421 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1422 : // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_MM:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1423 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_MM,
1424 : GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1425 : GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1426 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1427 : // GIR_Coverage, 1042,
1428 : GIR_Done,
1429 : // Label 126: @2000
1430 : GIM_Try, /*On fail goto*//*Label 127*/ 2023, // Rule ID 1145 //
1431 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1432 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1433 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1434 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1435 : // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1436 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_MMR6,
1437 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1438 : // GIR_Coverage, 1145,
1439 : GIR_Done,
1440 : // Label 127: @2023
1441 : GIM_Try, /*On fail goto*//*Label 128*/ 2052, // Rule ID 1747 //
1442 : GIM_CheckFeatures, GIFBS_InMips16Mode,
1443 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
1444 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
1445 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
1446 : // (mul:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (MultRxRyRz16:{ *:[i32] }:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
1447 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MultRxRyRz16,
1448 : GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1449 : GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1450 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1451 : // GIR_Coverage, 1747,
1452 : GIR_Done,
1453 : // Label 128: @2052
1454 : GIM_Reject,
1455 : // Label 123: @2053
1456 : GIM_Reject,
1457 : // Label 116: @2054
1458 : GIM_Try, /*On fail goto*//*Label 129*/ 2114,
1459 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1460 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1461 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1462 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1463 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1464 : GIM_Try, /*On fail goto*//*Label 130*/ 2102, // Rule ID 246 //
1465 : GIM_CheckFeatures, GIFBS_HasCnMips,
1466 : // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUL:{ *:[i64] }:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1467 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUL,
1468 : GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1469 : GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1470 : GIR_AddImplicitDef, /*InsnID*/0, Mips::P0,
1471 : GIR_AddImplicitDef, /*InsnID*/0, Mips::P1,
1472 : GIR_AddImplicitDef, /*InsnID*/0, Mips::P2,
1473 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1474 : // GIR_Coverage, 246,
1475 : GIR_Done,
1476 : // Label 130: @2102
1477 : GIM_Try, /*On fail goto*//*Label 131*/ 2113, // Rule ID 319 //
1478 : GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1479 : // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUL_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1480 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUL_R6,
1481 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1482 : // GIR_Coverage, 319,
1483 : GIR_Done,
1484 : // Label 131: @2113
1485 : GIM_Reject,
1486 : // Label 129: @2114
1487 : GIM_Reject,
1488 : // Label 117: @2115
1489 : GIM_Try, /*On fail goto*//*Label 132*/ 2141, // Rule ID 1848 //
1490 : GIM_CheckFeatures, GIFBS_HasDSPR2,
1491 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1492 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
1493 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
1494 : // (mul:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1495 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_PH,
1496 : GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag21,
1497 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1498 : // GIR_Coverage, 1848,
1499 : GIR_Done,
1500 : // Label 132: @2141
1501 : GIM_Reject,
1502 : // Label 118: @2142
1503 : GIM_Try, /*On fail goto*//*Label 133*/ 2173, // Rule ID 875 //
1504 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1505 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1506 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1507 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1508 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1509 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1510 : // (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MULV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1511 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_D,
1512 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1513 : // GIR_Coverage, 875,
1514 : GIR_Done,
1515 : // Label 133: @2173
1516 : GIM_Reject,
1517 : // Label 119: @2174
1518 : GIM_Try, /*On fail goto*//*Label 134*/ 2205, // Rule ID 874 //
1519 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1520 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1521 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1522 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1523 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1524 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1525 : // (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MULV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1526 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_W,
1527 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1528 : // GIR_Coverage, 874,
1529 : GIR_Done,
1530 : // Label 134: @2205
1531 : GIM_Reject,
1532 : // Label 120: @2206
1533 : GIM_Try, /*On fail goto*//*Label 135*/ 2237, // Rule ID 873 //
1534 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1535 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1536 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1537 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1538 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1539 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1540 : // (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MULV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1541 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_H,
1542 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1543 : // GIR_Coverage, 873,
1544 : GIR_Done,
1545 : // Label 135: @2237
1546 : GIM_Reject,
1547 : // Label 121: @2238
1548 : GIM_Try, /*On fail goto*//*Label 136*/ 2269, // Rule ID 872 //
1549 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1550 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1551 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1552 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1553 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1554 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1555 : // (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MULV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1556 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_B,
1557 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1558 : // GIR_Coverage, 872,
1559 : GIR_Done,
1560 : // Label 136: @2269
1561 : GIM_Reject,
1562 : // Label 122: @2270
1563 : GIM_Reject,
1564 : // Label 3: @2271
1565 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 143*/ 2491,
1566 : /*GILLT_s32*//*Label 137*/ 2285,
1567 : /*GILLT_s64*//*Label 138*/ 2331, 0,
1568 : /*GILLT_v2s64*//*Label 139*/ 2363, 0,
1569 : /*GILLT_v4s32*//*Label 140*/ 2395,
1570 : /*GILLT_v8s16*//*Label 141*/ 2427,
1571 : /*GILLT_v16s8*//*Label 142*/ 2459,
1572 : // Label 137: @2285
1573 : GIM_Try, /*On fail goto*//*Label 144*/ 2330,
1574 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1575 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1576 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1577 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1578 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1579 : GIM_Try, /*On fail goto*//*Label 145*/ 2318, // Rule ID 298 //
1580 : GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1581 : // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1582 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV,
1583 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1584 : // GIR_Coverage, 298,
1585 : GIR_Done,
1586 : // Label 145: @2318
1587 : GIM_Try, /*On fail goto*//*Label 146*/ 2329, // Rule ID 1138 //
1588 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1589 : // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIV_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1590 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_MMR6,
1591 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1592 : // GIR_Coverage, 1138,
1593 : GIR_Done,
1594 : // Label 146: @2329
1595 : GIM_Reject,
1596 : // Label 144: @2330
1597 : GIM_Reject,
1598 : // Label 138: @2331
1599 : GIM_Try, /*On fail goto*//*Label 147*/ 2362, // Rule ID 313 //
1600 : GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1601 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1602 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1603 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1604 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1605 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1606 : // (sdiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DDIV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1607 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DDIV,
1608 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1609 : // GIR_Coverage, 313,
1610 : GIR_Done,
1611 : // Label 147: @2362
1612 : GIM_Reject,
1613 : // Label 139: @2363
1614 : GIM_Try, /*On fail goto*//*Label 148*/ 2394, // Rule ID 615 //
1615 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1616 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1617 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1618 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1619 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1620 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1621 : // (sdiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (DIV_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1622 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_D,
1623 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1624 : // GIR_Coverage, 615,
1625 : GIR_Done,
1626 : // Label 148: @2394
1627 : GIM_Reject,
1628 : // Label 140: @2395
1629 : GIM_Try, /*On fail goto*//*Label 149*/ 2426, // Rule ID 614 //
1630 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1631 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1632 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1633 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1634 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1635 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1636 : // (sdiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DIV_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1637 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_W,
1638 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1639 : // GIR_Coverage, 614,
1640 : GIR_Done,
1641 : // Label 149: @2426
1642 : GIM_Reject,
1643 : // Label 141: @2427
1644 : GIM_Try, /*On fail goto*//*Label 150*/ 2458, // Rule ID 613 //
1645 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1646 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1647 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1648 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1649 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1650 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1651 : // (sdiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DIV_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1652 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_H,
1653 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1654 : // GIR_Coverage, 613,
1655 : GIR_Done,
1656 : // Label 150: @2458
1657 : GIM_Reject,
1658 : // Label 142: @2459
1659 : GIM_Try, /*On fail goto*//*Label 151*/ 2490, // Rule ID 612 //
1660 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1661 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1662 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1663 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1664 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1665 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1666 : // (sdiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DIV_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1667 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_B,
1668 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1669 : // GIR_Coverage, 612,
1670 : GIR_Done,
1671 : // Label 151: @2490
1672 : GIM_Reject,
1673 : // Label 143: @2491
1674 : GIM_Reject,
1675 : // Label 4: @2492
1676 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 158*/ 2712,
1677 : /*GILLT_s32*//*Label 152*/ 2506,
1678 : /*GILLT_s64*//*Label 153*/ 2552, 0,
1679 : /*GILLT_v2s64*//*Label 154*/ 2584, 0,
1680 : /*GILLT_v4s32*//*Label 155*/ 2616,
1681 : /*GILLT_v8s16*//*Label 156*/ 2648,
1682 : /*GILLT_v16s8*//*Label 157*/ 2680,
1683 : // Label 152: @2506
1684 : GIM_Try, /*On fail goto*//*Label 159*/ 2551,
1685 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1686 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1687 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1688 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1689 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1690 : GIM_Try, /*On fail goto*//*Label 160*/ 2539, // Rule ID 299 //
1691 : GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1692 : // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIVU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1693 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIVU,
1694 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1695 : // GIR_Coverage, 299,
1696 : GIR_Done,
1697 : // Label 160: @2539
1698 : GIM_Try, /*On fail goto*//*Label 161*/ 2550, // Rule ID 1139 //
1699 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1700 : // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIVU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1701 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIVU_MMR6,
1702 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1703 : // GIR_Coverage, 1139,
1704 : GIR_Done,
1705 : // Label 161: @2550
1706 : GIM_Reject,
1707 : // Label 159: @2551
1708 : GIM_Reject,
1709 : // Label 153: @2552
1710 : GIM_Try, /*On fail goto*//*Label 162*/ 2583, // Rule ID 314 //
1711 : GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1712 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1713 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1714 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1715 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1716 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1717 : // (udiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DDIVU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1718 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DDIVU,
1719 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1720 : // GIR_Coverage, 314,
1721 : GIR_Done,
1722 : // Label 162: @2583
1723 : GIM_Reject,
1724 : // Label 154: @2584
1725 : GIM_Try, /*On fail goto*//*Label 163*/ 2615, // Rule ID 619 //
1726 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1727 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1728 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1729 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1730 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1731 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1732 : // (udiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (DIV_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1733 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_D,
1734 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1735 : // GIR_Coverage, 619,
1736 : GIR_Done,
1737 : // Label 163: @2615
1738 : GIM_Reject,
1739 : // Label 155: @2616
1740 : GIM_Try, /*On fail goto*//*Label 164*/ 2647, // Rule ID 618 //
1741 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1742 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1743 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1744 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1745 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1746 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1747 : // (udiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DIV_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1748 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_W,
1749 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1750 : // GIR_Coverage, 618,
1751 : GIR_Done,
1752 : // Label 164: @2647
1753 : GIM_Reject,
1754 : // Label 156: @2648
1755 : GIM_Try, /*On fail goto*//*Label 165*/ 2679, // Rule ID 617 //
1756 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1757 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1758 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1759 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1760 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1761 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1762 : // (udiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DIV_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1763 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_H,
1764 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1765 : // GIR_Coverage, 617,
1766 : GIR_Done,
1767 : // Label 165: @2679
1768 : GIM_Reject,
1769 : // Label 157: @2680
1770 : GIM_Try, /*On fail goto*//*Label 166*/ 2711, // Rule ID 616 //
1771 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1772 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1773 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1774 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1775 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1776 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1777 : // (udiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DIV_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1778 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_B,
1779 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1780 : // GIR_Coverage, 616,
1781 : GIR_Done,
1782 : // Label 166: @2711
1783 : GIM_Reject,
1784 : // Label 158: @2712
1785 : GIM_Reject,
1786 : // Label 5: @2713
1787 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 173*/ 2933,
1788 : /*GILLT_s32*//*Label 167*/ 2727,
1789 : /*GILLT_s64*//*Label 168*/ 2773, 0,
1790 : /*GILLT_v2s64*//*Label 169*/ 2805, 0,
1791 : /*GILLT_v4s32*//*Label 170*/ 2837,
1792 : /*GILLT_v8s16*//*Label 171*/ 2869,
1793 : /*GILLT_v16s8*//*Label 172*/ 2901,
1794 : // Label 167: @2727
1795 : GIM_Try, /*On fail goto*//*Label 174*/ 2772,
1796 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1797 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1798 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1799 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1800 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1801 : GIM_Try, /*On fail goto*//*Label 175*/ 2760, // Rule ID 300 //
1802 : GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1803 : // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MOD:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1804 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD,
1805 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1806 : // GIR_Coverage, 300,
1807 : GIR_Done,
1808 : // Label 175: @2760
1809 : GIM_Try, /*On fail goto*//*Label 176*/ 2771, // Rule ID 1143 //
1810 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1811 : // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MOD_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1812 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_MMR6,
1813 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1814 : // GIR_Coverage, 1143,
1815 : GIR_Done,
1816 : // Label 176: @2771
1817 : GIM_Reject,
1818 : // Label 174: @2772
1819 : GIM_Reject,
1820 : // Label 168: @2773
1821 : GIM_Try, /*On fail goto*//*Label 177*/ 2804, // Rule ID 315 //
1822 : GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1823 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1824 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1825 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1826 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1827 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1828 : // (srem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMOD:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1829 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMOD,
1830 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1831 : // GIR_Coverage, 315,
1832 : GIR_Done,
1833 : // Label 177: @2804
1834 : GIM_Reject,
1835 : // Label 169: @2805
1836 : GIM_Try, /*On fail goto*//*Label 178*/ 2836, // Rule ID 855 //
1837 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1838 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1839 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1840 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1841 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1842 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1843 : // (srem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MOD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1844 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_D,
1845 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1846 : // GIR_Coverage, 855,
1847 : GIR_Done,
1848 : // Label 178: @2836
1849 : GIM_Reject,
1850 : // Label 170: @2837
1851 : GIM_Try, /*On fail goto*//*Label 179*/ 2868, // Rule ID 854 //
1852 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1853 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1854 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1855 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1856 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1857 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1858 : // (srem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MOD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1859 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_W,
1860 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1861 : // GIR_Coverage, 854,
1862 : GIR_Done,
1863 : // Label 179: @2868
1864 : GIM_Reject,
1865 : // Label 171: @2869
1866 : GIM_Try, /*On fail goto*//*Label 180*/ 2900, // Rule ID 853 //
1867 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1868 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1869 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1870 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1871 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1872 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1873 : // (srem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MOD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1874 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_H,
1875 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1876 : // GIR_Coverage, 853,
1877 : GIR_Done,
1878 : // Label 180: @2900
1879 : GIM_Reject,
1880 : // Label 172: @2901
1881 : GIM_Try, /*On fail goto*//*Label 181*/ 2932, // Rule ID 852 //
1882 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1883 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1884 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1885 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1886 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1887 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1888 : // (srem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MOD_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1889 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_B,
1890 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1891 : // GIR_Coverage, 852,
1892 : GIR_Done,
1893 : // Label 181: @2932
1894 : GIM_Reject,
1895 : // Label 173: @2933
1896 : GIM_Reject,
1897 : // Label 6: @2934
1898 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 188*/ 3154,
1899 : /*GILLT_s32*//*Label 182*/ 2948,
1900 : /*GILLT_s64*//*Label 183*/ 2994, 0,
1901 : /*GILLT_v2s64*//*Label 184*/ 3026, 0,
1902 : /*GILLT_v4s32*//*Label 185*/ 3058,
1903 : /*GILLT_v8s16*//*Label 186*/ 3090,
1904 : /*GILLT_v16s8*//*Label 187*/ 3122,
1905 : // Label 182: @2948
1906 : GIM_Try, /*On fail goto*//*Label 189*/ 2993,
1907 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1908 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1909 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1910 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1911 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1912 : GIM_Try, /*On fail goto*//*Label 190*/ 2981, // Rule ID 301 //
1913 : GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1914 : // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1915 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MODU,
1916 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1917 : // GIR_Coverage, 301,
1918 : GIR_Done,
1919 : // Label 190: @2981
1920 : GIM_Try, /*On fail goto*//*Label 191*/ 2992, // Rule ID 1144 //
1921 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1922 : // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1923 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MODU_MMR6,
1924 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1925 : // GIR_Coverage, 1144,
1926 : GIR_Done,
1927 : // Label 191: @2992
1928 : GIM_Reject,
1929 : // Label 189: @2993
1930 : GIM_Reject,
1931 : // Label 183: @2994
1932 : GIM_Try, /*On fail goto*//*Label 192*/ 3025, // Rule ID 316 //
1933 : GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1934 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1935 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1936 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1937 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1938 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1939 : // (urem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMODU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1940 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMODU,
1941 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1942 : // GIR_Coverage, 316,
1943 : GIR_Done,
1944 : // Label 192: @3025
1945 : GIM_Reject,
1946 : // Label 184: @3026
1947 : GIM_Try, /*On fail goto*//*Label 193*/ 3057, // Rule ID 859 //
1948 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1949 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1950 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1951 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1952 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1953 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1954 : // (urem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MOD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1955 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_D,
1956 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1957 : // GIR_Coverage, 859,
1958 : GIR_Done,
1959 : // Label 193: @3057
1960 : GIM_Reject,
1961 : // Label 185: @3058
1962 : GIM_Try, /*On fail goto*//*Label 194*/ 3089, // Rule ID 858 //
1963 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1964 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1965 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1966 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1967 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1968 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1969 : // (urem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MOD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1970 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_W,
1971 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1972 : // GIR_Coverage, 858,
1973 : GIR_Done,
1974 : // Label 194: @3089
1975 : GIM_Reject,
1976 : // Label 186: @3090
1977 : GIM_Try, /*On fail goto*//*Label 195*/ 3121, // Rule ID 857 //
1978 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1979 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1980 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1981 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1982 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1983 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1984 : // (urem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MOD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1985 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_H,
1986 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1987 : // GIR_Coverage, 857,
1988 : GIR_Done,
1989 : // Label 195: @3121
1990 : GIM_Reject,
1991 : // Label 187: @3122
1992 : GIM_Try, /*On fail goto*//*Label 196*/ 3153, // Rule ID 856 //
1993 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1994 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1995 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1996 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1997 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1998 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1999 : // (urem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MOD_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2000 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_B,
2001 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2002 : // GIR_Coverage, 856,
2003 : GIR_Done,
2004 : // Label 196: @3153
2005 : GIM_Reject,
2006 : // Label 188: @3154
2007 : GIM_Reject,
2008 : // Label 7: @3155
2009 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 203*/ 3598,
2010 : /*GILLT_s32*//*Label 197*/ 3169,
2011 : /*GILLT_s64*//*Label 198*/ 3382, 0,
2012 : /*GILLT_v2s64*//*Label 199*/ 3470, 0,
2013 : /*GILLT_v4s32*//*Label 200*/ 3502,
2014 : /*GILLT_v8s16*//*Label 201*/ 3534,
2015 : /*GILLT_v16s8*//*Label 202*/ 3566,
2016 : // Label 197: @3169
2017 : GIM_Try, /*On fail goto*//*Label 204*/ 3381,
2018 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2019 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2020 : GIM_Try, /*On fail goto*//*Label 205*/ 3222, // Rule ID 2087 //
2021 : GIM_CheckFeatures, GIFBS_InMicroMips,
2022 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2023 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2024 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2025 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2026 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExtAndi16,
2027 : // MIs[1] Operand 1
2028 : // No operand predicates
2029 : GIM_CheckIsSafeToFold, /*InsnID*/1,
2030 : // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm) => (ANDI16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
2031 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDI16_MM,
2032 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2033 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
2034 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2035 : GIR_EraseFromParent, /*InsnID*/0,
2036 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2037 : // GIR_Coverage, 2087,
2038 : GIR_Done,
2039 : // Label 205: @3222
2040 : GIM_Try, /*On fail goto*//*Label 206*/ 3265, // Rule ID 2240 //
2041 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2042 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2043 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2044 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2045 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2046 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExtAndi16,
2047 : // MIs[1] Operand 1
2048 : // No operand predicates
2049 : GIM_CheckIsSafeToFold, /*InsnID*/1,
2050 : // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm) => (ANDI16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
2051 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDI16_MMR6,
2052 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2053 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
2054 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2055 : GIR_EraseFromParent, /*InsnID*/0,
2056 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2057 : // GIR_Coverage, 2240,
2058 : GIR_Done,
2059 : // Label 206: @3265
2060 : GIM_Try, /*On fail goto*//*Label 207*/ 3288, // Rule ID 39 //
2061 : GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2062 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2063 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2064 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2065 : // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2066 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND,
2067 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2068 : // GIR_Coverage, 39,
2069 : GIR_Done,
2070 : // Label 207: @3288
2071 : GIM_Try, /*On fail goto*//*Label 208*/ 3311, // Rule ID 1029 //
2072 : GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2073 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2074 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2075 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
2076 : // (and:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (AND16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2077 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND16_MM,
2078 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2079 : // GIR_Coverage, 1029,
2080 : GIR_Done,
2081 : // Label 208: @3311
2082 : GIM_Try, /*On fail goto*//*Label 209*/ 3334, // Rule ID 1045 //
2083 : GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2084 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2085 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2086 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2087 : // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2088 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_MM,
2089 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2090 : // GIR_Coverage, 1045,
2091 : GIR_Done,
2092 : // Label 209: @3334
2093 : GIM_Try, /*On fail goto*//*Label 210*/ 3357, // Rule ID 1136 //
2094 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2095 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2096 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2097 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2098 : // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2099 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_MMR6,
2100 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2101 : // GIR_Coverage, 1136,
2102 : GIR_Done,
2103 : // Label 210: @3357
2104 : GIM_Try, /*On fail goto*//*Label 211*/ 3380, // Rule ID 1746 //
2105 : GIM_CheckFeatures, GIFBS_InMips16Mode,
2106 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2107 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2108 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
2109 : // (and:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (AndRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2110 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AndRxRxRy16,
2111 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2112 : // GIR_Coverage, 1746,
2113 : GIR_Done,
2114 : // Label 211: @3380
2115 : GIM_Reject,
2116 : // Label 204: @3381
2117 : GIM_Reject,
2118 : // Label 198: @3382
2119 : GIM_Try, /*On fail goto*//*Label 212*/ 3469,
2120 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2121 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2122 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2123 : GIM_Try, /*On fail goto*//*Label 213*/ 3449, // Rule ID 241 //
2124 : GIM_CheckFeatures, GIFBS_HasCnMips,
2125 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2126 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
2127 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2128 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2129 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2130 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2131 : GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
2132 : GIM_CheckIsSafeToFold, /*InsnID*/1,
2133 : // (and:{ *:[i64] } (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), 255:{ *:[i64] }) => (BADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2134 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BADDu,
2135 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2136 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2137 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2138 : GIR_EraseFromParent, /*InsnID*/0,
2139 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2140 : // GIR_Coverage, 241,
2141 : GIR_Done,
2142 : // Label 213: @3449
2143 : GIM_Try, /*On fail goto*//*Label 214*/ 3468, // Rule ID 184 //
2144 : GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2145 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2146 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2147 : // (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (AND64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2148 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND64,
2149 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2150 : // GIR_Coverage, 184,
2151 : GIR_Done,
2152 : // Label 214: @3468
2153 : GIM_Reject,
2154 : // Label 212: @3469
2155 : GIM_Reject,
2156 : // Label 199: @3470
2157 : GIM_Try, /*On fail goto*//*Label 215*/ 3501, // Rule ID 486 //
2158 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2159 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2160 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
2161 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2162 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
2163 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
2164 : // (and:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AND_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2165 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_D_PSEUDO,
2166 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2167 : // GIR_Coverage, 486,
2168 : GIR_Done,
2169 : // Label 215: @3501
2170 : GIM_Reject,
2171 : // Label 200: @3502
2172 : GIM_Try, /*On fail goto*//*Label 216*/ 3533, // Rule ID 485 //
2173 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2174 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2175 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2176 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
2177 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
2178 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
2179 : // (and:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AND_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2180 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_W_PSEUDO,
2181 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2182 : // GIR_Coverage, 485,
2183 : GIR_Done,
2184 : // Label 216: @3533
2185 : GIM_Reject,
2186 : // Label 201: @3534
2187 : GIM_Try, /*On fail goto*//*Label 217*/ 3565, // Rule ID 484 //
2188 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2189 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2190 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2191 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
2192 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
2193 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
2194 : // (and:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AND_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2195 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_H_PSEUDO,
2196 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2197 : // GIR_Coverage, 484,
2198 : GIR_Done,
2199 : // Label 217: @3565
2200 : GIM_Reject,
2201 : // Label 202: @3566
2202 : GIM_Try, /*On fail goto*//*Label 218*/ 3597, // Rule ID 483 //
2203 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2204 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2205 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2206 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
2207 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
2208 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
2209 : // (and:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AND_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2210 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V,
2211 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2212 : // GIR_Coverage, 483,
2213 : GIR_Done,
2214 : // Label 218: @3597
2215 : GIM_Reject,
2216 : // Label 203: @3598
2217 : GIM_Reject,
2218 : // Label 8: @3599
2219 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 225*/ 3900,
2220 : /*GILLT_s32*//*Label 219*/ 3613,
2221 : /*GILLT_s64*//*Label 220*/ 3740, 0,
2222 : /*GILLT_v2s64*//*Label 221*/ 3772, 0,
2223 : /*GILLT_v4s32*//*Label 222*/ 3804,
2224 : /*GILLT_v8s16*//*Label 223*/ 3836,
2225 : /*GILLT_v16s8*//*Label 224*/ 3868,
2226 : // Label 219: @3613
2227 : GIM_Try, /*On fail goto*//*Label 226*/ 3739,
2228 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2229 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2230 : GIM_Try, /*On fail goto*//*Label 227*/ 3646, // Rule ID 40 //
2231 : GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2232 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2233 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2234 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2235 : // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2236 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR,
2237 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2238 : // GIR_Coverage, 40,
2239 : GIR_Done,
2240 : // Label 227: @3646
2241 : GIM_Try, /*On fail goto*//*Label 228*/ 3669, // Rule ID 1031 //
2242 : GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2243 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2244 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2245 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
2246 : // (or:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (OR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2247 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR16_MM,
2248 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2249 : // GIR_Coverage, 1031,
2250 : GIR_Done,
2251 : // Label 228: @3669
2252 : GIM_Try, /*On fail goto*//*Label 229*/ 3692, // Rule ID 1046 //
2253 : GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2254 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2255 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2256 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2257 : // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2258 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_MM,
2259 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2260 : // GIR_Coverage, 1046,
2261 : GIR_Done,
2262 : // Label 229: @3692
2263 : GIM_Try, /*On fail goto*//*Label 230*/ 3715, // Rule ID 1149 //
2264 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2265 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2266 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2267 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2268 : // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2269 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_MMR6,
2270 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2271 : // GIR_Coverage, 1149,
2272 : GIR_Done,
2273 : // Label 230: @3715
2274 : GIM_Try, /*On fail goto*//*Label 231*/ 3738, // Rule ID 1748 //
2275 : GIM_CheckFeatures, GIFBS_InMips16Mode,
2276 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2277 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2278 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
2279 : // (or:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (OrRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2280 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OrRxRxRy16,
2281 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2282 : // GIR_Coverage, 1748,
2283 : GIR_Done,
2284 : // Label 231: @3738
2285 : GIM_Reject,
2286 : // Label 226: @3739
2287 : GIM_Reject,
2288 : // Label 220: @3740
2289 : GIM_Try, /*On fail goto*//*Label 232*/ 3771, // Rule ID 185 //
2290 : GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2291 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2292 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2293 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2294 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2295 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2296 : // (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (OR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2297 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR64,
2298 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2299 : // GIR_Coverage, 185,
2300 : GIR_Done,
2301 : // Label 232: @3771
2302 : GIM_Reject,
2303 : // Label 221: @3772
2304 : GIM_Try, /*On fail goto*//*Label 233*/ 3803, // Rule ID 892 //
2305 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2306 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2307 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
2308 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2309 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
2310 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
2311 : // (or:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (OR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2312 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_D_PSEUDO,
2313 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2314 : // GIR_Coverage, 892,
2315 : GIR_Done,
2316 : // Label 233: @3803
2317 : GIM_Reject,
2318 : // Label 222: @3804
2319 : GIM_Try, /*On fail goto*//*Label 234*/ 3835, // Rule ID 891 //
2320 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2321 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2322 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2323 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
2324 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
2325 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
2326 : // (or:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (OR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2327 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_W_PSEUDO,
2328 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2329 : // GIR_Coverage, 891,
2330 : GIR_Done,
2331 : // Label 234: @3835
2332 : GIM_Reject,
2333 : // Label 223: @3836
2334 : GIM_Try, /*On fail goto*//*Label 235*/ 3867, // Rule ID 890 //
2335 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2336 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2337 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2338 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
2339 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
2340 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
2341 : // (or:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (OR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2342 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_H_PSEUDO,
2343 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2344 : // GIR_Coverage, 890,
2345 : GIR_Done,
2346 : // Label 235: @3867
2347 : GIM_Reject,
2348 : // Label 224: @3868
2349 : GIM_Try, /*On fail goto*//*Label 236*/ 3899, // Rule ID 889 //
2350 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2351 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2352 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2353 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
2354 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
2355 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
2356 : // (or:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (OR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2357 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V,
2358 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2359 : // GIR_Coverage, 889,
2360 : GIR_Done,
2361 : // Label 236: @3899
2362 : GIM_Reject,
2363 : // Label 225: @3900
2364 : GIM_Reject,
2365 : // Label 9: @3901
2366 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 243*/ 4694,
2367 : /*GILLT_s32*//*Label 237*/ 3915,
2368 : /*GILLT_s64*//*Label 238*/ 4478, 0,
2369 : /*GILLT_v2s64*//*Label 239*/ 4566, 0,
2370 : /*GILLT_v4s32*//*Label 240*/ 4598,
2371 : /*GILLT_v8s16*//*Label 241*/ 4630,
2372 : /*GILLT_v16s8*//*Label 242*/ 4662,
2373 : // Label 237: @3915
2374 : GIM_Try, /*On fail goto*//*Label 244*/ 4477,
2375 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2376 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2377 : GIM_Try, /*On fail goto*//*Label 245*/ 3982, // Rule ID 42 //
2378 : GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2379 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2380 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2381 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2382 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2383 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2384 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2385 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2386 : GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2387 : GIM_CheckIsSafeToFold, /*InsnID*/1,
2388 : // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2389 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
2390 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2391 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2392 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2393 : GIR_EraseFromParent, /*InsnID*/0,
2394 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2395 : // GIR_Coverage, 42,
2396 : GIR_Done,
2397 : // Label 245: @3982
2398 : GIM_Try, /*On fail goto*//*Label 246*/ 4039, // Rule ID 1048 //
2399 : GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2400 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2401 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2402 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2403 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2404 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2405 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2406 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2407 : GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2408 : GIM_CheckIsSafeToFold, /*InsnID*/1,
2409 : // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2410 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MM,
2411 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2412 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2413 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2414 : GIR_EraseFromParent, /*InsnID*/0,
2415 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2416 : // GIR_Coverage, 1048,
2417 : GIR_Done,
2418 : // Label 246: @4039
2419 : GIM_Try, /*On fail goto*//*Label 247*/ 4096, // Rule ID 1148 //
2420 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2421 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2422 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2423 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2424 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2425 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2426 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2427 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2428 : GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2429 : GIM_CheckIsSafeToFold, /*InsnID*/1,
2430 : // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2431 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
2432 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2433 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2434 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2435 : GIR_EraseFromParent, /*InsnID*/0,
2436 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2437 : // GIR_Coverage, 1148,
2438 : GIR_Done,
2439 : // Label 247: @4096
2440 : GIM_Try, /*On fail goto*//*Label 248*/ 4128, // Rule ID 1175 //
2441 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2442 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2443 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2444 : GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2445 : // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }) => (NOT16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
2446 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MMR6,
2447 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2448 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
2449 : GIR_EraseFromParent, /*InsnID*/0,
2450 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2451 : // GIR_Coverage, 1175,
2452 : GIR_Done,
2453 : // Label 248: @4128
2454 : GIM_Try, /*On fail goto*//*Label 249*/ 4160, // Rule ID 1030 //
2455 : GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2456 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2457 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2458 : GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2459 : // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }) => (NOT16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
2460 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MM,
2461 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2462 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
2463 : GIR_EraseFromParent, /*InsnID*/0,
2464 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2465 : // GIR_Coverage, 1030,
2466 : GIR_Done,
2467 : // Label 249: @4160
2468 : GIM_Try, /*On fail goto*//*Label 250*/ 4195, // Rule ID 1362 //
2469 : GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2470 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2471 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2472 : GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2473 : // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2474 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
2475 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2476 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2477 : GIR_AddRegister, /*InsnID*/0, Mips::ZERO,
2478 : GIR_EraseFromParent, /*InsnID*/0,
2479 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2480 : // GIR_Coverage, 1362,
2481 : GIR_Done,
2482 : // Label 250: @4195
2483 : GIM_Try, /*On fail goto*//*Label 251*/ 4227, // Rule ID 1743 //
2484 : GIM_CheckFeatures, GIFBS_InMips16Mode,
2485 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2486 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2487 : GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2488 : // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, -1:{ *:[i32] }) => (NotRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
2489 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NotRxRy16,
2490 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
2491 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // r
2492 : GIR_EraseFromParent, /*InsnID*/0,
2493 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2494 : // GIR_Coverage, 1743,
2495 : GIR_Done,
2496 : // Label 251: @4227
2497 : GIM_Try, /*On fail goto*//*Label 252*/ 4259, // Rule ID 2082 //
2498 : GIM_CheckFeatures, GIFBS_InMicroMips,
2499 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2500 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2501 : GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2502 : // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOT16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
2503 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MM,
2504 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2505 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2506 : GIR_EraseFromParent, /*InsnID*/0,
2507 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2508 : // GIR_Coverage, 2082,
2509 : GIR_Done,
2510 : // Label 252: @4259
2511 : GIM_Try, /*On fail goto*//*Label 253*/ 4294, // Rule ID 2083 //
2512 : GIM_CheckFeatures, GIFBS_InMicroMips,
2513 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2514 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2515 : GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2516 : // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2517 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MM,
2518 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2519 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2520 : GIR_AddRegister, /*InsnID*/0, Mips::ZERO,
2521 : GIR_EraseFromParent, /*InsnID*/0,
2522 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2523 : // GIR_Coverage, 2083,
2524 : GIR_Done,
2525 : // Label 253: @4294
2526 : GIM_Try, /*On fail goto*//*Label 254*/ 4326, // Rule ID 2243 //
2527 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2528 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2529 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2530 : GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2531 : // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOT16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
2532 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MMR6,
2533 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2534 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2535 : GIR_EraseFromParent, /*InsnID*/0,
2536 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2537 : // GIR_Coverage, 2243,
2538 : GIR_Done,
2539 : // Label 254: @4326
2540 : GIM_Try, /*On fail goto*//*Label 255*/ 4361, // Rule ID 2244 //
2541 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2542 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2543 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2544 : GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2545 : // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2546 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
2547 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2548 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2549 : GIR_AddRegister, /*InsnID*/0, Mips::ZERO,
2550 : GIR_EraseFromParent, /*InsnID*/0,
2551 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2552 : // GIR_Coverage, 2244,
2553 : GIR_Done,
2554 : // Label 255: @4361
2555 : GIM_Try, /*On fail goto*//*Label 256*/ 4384, // Rule ID 41 //
2556 : GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2557 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2558 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2559 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2560 : // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2561 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR,
2562 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2563 : // GIR_Coverage, 41,
2564 : GIR_Done,
2565 : // Label 256: @4384
2566 : GIM_Try, /*On fail goto*//*Label 257*/ 4407, // Rule ID 1033 //
2567 : GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2568 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2569 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2570 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
2571 : // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (XOR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2572 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR16_MM,
2573 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2574 : // GIR_Coverage, 1033,
2575 : GIR_Done,
2576 : // Label 257: @4407
2577 : GIM_Try, /*On fail goto*//*Label 258*/ 4430, // Rule ID 1047 //
2578 : GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2579 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2580 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2581 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2582 : // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2583 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_MM,
2584 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2585 : // GIR_Coverage, 1047,
2586 : GIR_Done,
2587 : // Label 258: @4430
2588 : GIM_Try, /*On fail goto*//*Label 259*/ 4453, // Rule ID 1152 //
2589 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2590 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2591 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2592 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2593 : // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2594 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_MMR6,
2595 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2596 : // GIR_Coverage, 1152,
2597 : GIR_Done,
2598 : // Label 259: @4453
2599 : GIM_Try, /*On fail goto*//*Label 260*/ 4476, // Rule ID 1750 //
2600 : GIM_CheckFeatures, GIFBS_InMips16Mode,
2601 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2602 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2603 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
2604 : // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2605 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XorRxRxRy16,
2606 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2607 : // GIR_Coverage, 1750,
2608 : GIR_Done,
2609 : // Label 260: @4476
2610 : GIM_Reject,
2611 : // Label 244: @4477
2612 : GIM_Reject,
2613 : // Label 238: @4478
2614 : GIM_Try, /*On fail goto*//*Label 261*/ 4565,
2615 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2616 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2617 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2618 : GIM_Try, /*On fail goto*//*Label 262*/ 4545, // Rule ID 187 //
2619 : GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2620 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2621 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2622 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2623 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2624 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2625 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2626 : GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2627 : GIM_CheckIsSafeToFold, /*InsnID*/1,
2628 : // (xor:{ *:[i64] } (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), -1:{ *:[i64] }) => (NOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2629 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR64,
2630 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2631 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2632 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2633 : GIR_EraseFromParent, /*InsnID*/0,
2634 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2635 : // GIR_Coverage, 187,
2636 : GIR_Done,
2637 : // Label 262: @4545
2638 : GIM_Try, /*On fail goto*//*Label 263*/ 4564, // Rule ID 186 //
2639 : GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2640 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2641 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2642 : // (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (XOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2643 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR64,
2644 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2645 : // GIR_Coverage, 186,
2646 : GIR_Done,
2647 : // Label 263: @4564
2648 : GIM_Reject,
2649 : // Label 261: @4565
2650 : GIM_Reject,
2651 : // Label 239: @4566
2652 : GIM_Try, /*On fail goto*//*Label 264*/ 4597, // Rule ID 1008 //
2653 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2654 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2655 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
2656 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2657 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
2658 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
2659 : // (xor:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (XOR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2660 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_D_PSEUDO,
2661 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2662 : // GIR_Coverage, 1008,
2663 : GIR_Done,
2664 : // Label 264: @4597
2665 : GIM_Reject,
2666 : // Label 240: @4598
2667 : GIM_Try, /*On fail goto*//*Label 265*/ 4629, // Rule ID 1007 //
2668 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2669 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2670 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2671 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
2672 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
2673 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
2674 : // (xor:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (XOR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2675 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_W_PSEUDO,
2676 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2677 : // GIR_Coverage, 1007,
2678 : GIR_Done,
2679 : // Label 265: @4629
2680 : GIM_Reject,
2681 : // Label 241: @4630
2682 : GIM_Try, /*On fail goto*//*Label 266*/ 4661, // Rule ID 1006 //
2683 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2684 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2685 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2686 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
2687 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
2688 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
2689 : // (xor:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (XOR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2690 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_H_PSEUDO,
2691 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2692 : // GIR_Coverage, 1006,
2693 : GIR_Done,
2694 : // Label 266: @4661
2695 : GIM_Reject,
2696 : // Label 242: @4662
2697 : GIM_Try, /*On fail goto*//*Label 267*/ 4693, // Rule ID 1005 //
2698 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2699 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2700 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2701 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
2702 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
2703 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
2704 : // (xor:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (XOR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2705 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V,
2706 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2707 : // GIR_Coverage, 1005,
2708 : GIR_Done,
2709 : // Label 267: @4693
2710 : GIM_Reject,
2711 : // Label 243: @4694
2712 : GIM_Reject,
2713 : // Label 10: @4695
2714 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 276*/ 8347,
2715 : /*GILLT_s32*//*Label 268*/ 4709,
2716 : /*GILLT_s64*//*Label 269*/ 4948,
2717 : /*GILLT_v2s16*//*Label 270*/ 4994,
2718 : /*GILLT_v2s64*//*Label 271*/ 5040,
2719 : /*GILLT_v4s8*//*Label 272*/ 6013,
2720 : /*GILLT_v4s32*//*Label 273*/ 6059,
2721 : /*GILLT_v8s16*//*Label 274*/ 6962,
2722 : /*GILLT_v16s8*//*Label 275*/ 7760,
2723 : // Label 268: @4709
2724 : GIM_Try, /*On fail goto*//*Label 277*/ 4732, // Rule ID 117 //
2725 : GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
2726 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2727 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2728 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
2729 : // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
2730 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1,
2731 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2732 : // GIR_Coverage, 117,
2733 : GIR_Done,
2734 : // Label 277: @4732
2735 : GIM_Try, /*On fail goto*//*Label 278*/ 4755, // Rule ID 118 //
2736 : GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
2737 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2738 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
2739 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2740 : // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
2741 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1,
2742 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2743 : // GIR_Coverage, 118,
2744 : GIR_Done,
2745 : // Label 278: @4755
2746 : GIM_Try, /*On fail goto*//*Label 279*/ 4778, // Rule ID 1128 //
2747 : GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
2748 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2749 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2750 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
2751 : // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1_MM:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
2752 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1_MM,
2753 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2754 : // GIR_Coverage, 1128,
2755 : GIR_Done,
2756 : // Label 279: @4778
2757 : GIM_Try, /*On fail goto*//*Label 280*/ 4801, // Rule ID 1129 //
2758 : GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
2759 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2760 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
2761 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2762 : // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1_MM:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
2763 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1_MM,
2764 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2765 : // GIR_Coverage, 1129,
2766 : GIR_Done,
2767 : // Label 280: @4801
2768 : GIM_Try, /*On fail goto*//*Label 281*/ 4824, // Rule ID 1141 //
2769 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
2770 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2771 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
2772 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2773 : // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1_MMR6:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
2774 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1_MMR6,
2775 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2776 : // GIR_Coverage, 1141,
2777 : GIR_Done,
2778 : // Label 281: @4824
2779 : GIM_Try, /*On fail goto*//*Label 282*/ 4847, // Rule ID 1142 //
2780 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
2781 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2782 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2783 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
2784 : // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
2785 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1_MMR6,
2786 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2787 : // GIR_Coverage, 1142,
2788 : GIR_Done,
2789 : // Label 282: @4847
2790 : GIM_Try, /*On fail goto*//*Label 283*/ 4872, // Rule ID 1831 //
2791 : GIM_CheckFeatures, GIFBS_HasDSP,
2792 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
2793 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2794 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
2795 : // (bitconvert:{ *:[i32] } DSPR:{ *:[v2i16] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v2i16] }:$src, GPR32:{ *:[i32] })
2796 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2797 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR32*/11,
2798 : // GIR_Coverage, 1831,
2799 : GIR_Done,
2800 : // Label 283: @4872
2801 : GIM_Try, /*On fail goto*//*Label 284*/ 4897, // Rule ID 1832 //
2802 : GIM_CheckFeatures, GIFBS_HasDSP,
2803 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
2804 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2805 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
2806 : // (bitconvert:{ *:[i32] } DSPR:{ *:[v4i8] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v4i8] }:$src, GPR32:{ *:[i32] })
2807 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2808 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR32*/11,
2809 : // GIR_Coverage, 1832,
2810 : GIR_Done,
2811 : // Label 284: @4897
2812 : GIM_Try, /*On fail goto*//*Label 285*/ 4922, // Rule ID 1835 //
2813 : GIM_CheckFeatures, GIFBS_HasDSP,
2814 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
2815 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
2816 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
2817 : // (bitconvert:{ *:[f32] } DSPR:{ *:[v2i16] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v2i16] }:$src, FGR32:{ *:[i32] })
2818 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2819 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FGR32*/8,
2820 : // GIR_Coverage, 1835,
2821 : GIR_Done,
2822 : // Label 285: @4922
2823 : GIM_Try, /*On fail goto*//*Label 286*/ 4947, // Rule ID 1836 //
2824 : GIM_CheckFeatures, GIFBS_HasDSP,
2825 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
2826 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
2827 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
2828 : // (bitconvert:{ *:[f32] } DSPR:{ *:[v4i8] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v4i8] }:$src, FGR32:{ *:[i32] })
2829 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2830 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FGR32*/8,
2831 : // GIR_Coverage, 1836,
2832 : GIR_Done,
2833 : // Label 286: @4947
2834 : GIM_Reject,
2835 : // Label 269: @4948
2836 : GIM_Try, /*On fail goto*//*Label 287*/ 4993,
2837 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2838 : GIM_Try, /*On fail goto*//*Label 288*/ 4973, // Rule ID 119 //
2839 : GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
2840 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
2841 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2842 : // (bitconvert:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt) => (DMTC1:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt)
2843 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMTC1,
2844 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2845 : // GIR_Coverage, 119,
2846 : GIR_Done,
2847 : // Label 288: @4973
2848 : GIM_Try, /*On fail goto*//*Label 289*/ 4992, // Rule ID 120 //
2849 : GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
2850 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2851 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
2852 : // (bitconvert:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs) => (DMFC1:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs)
2853 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMFC1,
2854 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2855 : // GIR_Coverage, 120,
2856 : GIR_Done,
2857 : // Label 289: @4992
2858 : GIM_Reject,
2859 : // Label 287: @4993
2860 : GIM_Reject,
2861 : // Label 270: @4994
2862 : GIM_Try, /*On fail goto*//*Label 290*/ 5039,
2863 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2864 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
2865 : GIM_Try, /*On fail goto*//*Label 291*/ 5021, // Rule ID 1833 //
2866 : GIM_CheckFeatures, GIFBS_HasDSP,
2867 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2868 : // (bitconvert:{ *:[v2i16] } GPR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i16] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
2869 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2870 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7,
2871 : // GIR_Coverage, 1833,
2872 : GIR_Done,
2873 : // Label 291: @5021
2874 : GIM_Try, /*On fail goto*//*Label 292*/ 5038, // Rule ID 1837 //
2875 : GIM_CheckFeatures, GIFBS_HasDSP,
2876 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
2877 : // (bitconvert:{ *:[v2i16] } FGR32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i16] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
2878 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2879 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7,
2880 : // GIR_Coverage, 1837,
2881 : GIR_Done,
2882 : // Label 292: @5038
2883 : GIM_Reject,
2884 : // Label 290: @5039
2885 : GIM_Reject,
2886 : // Label 271: @5040
2887 : GIM_Try, /*On fail goto*//*Label 293*/ 5061, // Rule ID 1918 //
2888 : GIM_CheckFeatures, GIFBS_HasMSA,
2889 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2890 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2891 : // (bitconvert:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src, MSA128D:{ *:[i32] })
2892 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2893 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2894 : // GIR_Coverage, 1918,
2895 : GIR_Done,
2896 : // Label 293: @5061
2897 : GIM_Try, /*On fail goto*//*Label 294*/ 5082, // Rule ID 1921 //
2898 : GIM_CheckFeatures, GIFBS_HasMSA,
2899 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2900 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2901 : // (bitconvert:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src, MSA128D:{ *:[i32] })
2902 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2903 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2904 : // GIR_Coverage, 1921,
2905 : GIR_Done,
2906 : // Label 294: @5082
2907 : GIM_Try, /*On fail goto*//*Label 295*/ 5103, // Rule ID 1938 //
2908 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2909 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2910 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2911 : // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
2912 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2913 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2914 : // GIR_Coverage, 1938,
2915 : GIR_Done,
2916 : // Label 295: @5103
2917 : GIM_Try, /*On fail goto*//*Label 296*/ 5124, // Rule ID 1939 //
2918 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2919 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2920 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2921 : // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
2922 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2923 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2924 : // GIR_Coverage, 1939,
2925 : GIR_Done,
2926 : // Label 296: @5124
2927 : GIM_Try, /*On fail goto*//*Label 297*/ 5145, // Rule ID 1940 //
2928 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2929 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2930 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2931 : // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
2932 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2933 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2934 : // GIR_Coverage, 1940,
2935 : GIR_Done,
2936 : // Label 297: @5145
2937 : GIM_Try, /*On fail goto*//*Label 298*/ 5166, // Rule ID 1941 //
2938 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2939 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2940 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2941 : // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
2942 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2943 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2944 : // GIR_Coverage, 1941,
2945 : GIR_Done,
2946 : // Label 298: @5166
2947 : GIM_Try, /*On fail goto*//*Label 299*/ 5187, // Rule ID 1942 //
2948 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2949 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2950 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2951 : // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
2952 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2953 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2954 : // GIR_Coverage, 1942,
2955 : GIR_Done,
2956 : // Label 299: @5187
2957 : GIM_Try, /*On fail goto*//*Label 300*/ 5208, // Rule ID 1948 //
2958 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2959 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2960 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2961 : // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
2962 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2963 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2964 : // GIR_Coverage, 1948,
2965 : GIR_Done,
2966 : // Label 300: @5208
2967 : GIM_Try, /*On fail goto*//*Label 301*/ 5229, // Rule ID 1949 //
2968 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2969 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2970 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2971 : // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
2972 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2973 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2974 : // GIR_Coverage, 1949,
2975 : GIR_Done,
2976 : // Label 301: @5229
2977 : GIM_Try, /*On fail goto*//*Label 302*/ 5250, // Rule ID 1950 //
2978 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2979 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2980 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2981 : // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
2982 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2983 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2984 : // GIR_Coverage, 1950,
2985 : GIR_Done,
2986 : // Label 302: @5250
2987 : GIM_Try, /*On fail goto*//*Label 303*/ 5271, // Rule ID 1951 //
2988 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2989 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2990 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2991 : // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
2992 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2993 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2994 : // GIR_Coverage, 1951,
2995 : GIR_Done,
2996 : // Label 303: @5271
2997 : GIM_Try, /*On fail goto*//*Label 304*/ 5292, // Rule ID 1952 //
2998 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2999 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3000 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3001 : // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
3002 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3003 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3004 : // GIR_Coverage, 1952,
3005 : GIR_Done,
3006 : // Label 304: @5292
3007 : GIM_Try, /*On fail goto*//*Label 305*/ 5392, // Rule ID 1957 //
3008 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3009 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3010 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3011 : // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3012 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3013 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3014 : GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
3015 : GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
3016 : GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
3017 : GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
3018 : GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
3019 : GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
3020 : GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
3021 : GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
3022 : GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
3023 : GIR_AddImm, /*InsnID*/3, /*Imm*/27,
3024 : GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3025 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3026 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3027 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
3028 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3029 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3030 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3031 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3032 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3033 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3034 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3035 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3036 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3037 : GIR_EraseFromParent, /*InsnID*/0,
3038 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3039 : // GIR_Coverage, 1957,
3040 : GIR_Done,
3041 : // Label 305: @5392
3042 : GIM_Try, /*On fail goto*//*Label 306*/ 5492, // Rule ID 1958 //
3043 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3044 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3045 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3046 : // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3047 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3048 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3049 : GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
3050 : GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
3051 : GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
3052 : GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
3053 : GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
3054 : GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
3055 : GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
3056 : GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
3057 : GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
3058 : GIR_AddImm, /*InsnID*/3, /*Imm*/27,
3059 : GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3060 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3061 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3062 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
3063 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3064 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3065 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3066 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3067 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3068 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3069 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3070 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3071 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3072 : GIR_EraseFromParent, /*InsnID*/0,
3073 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3074 : // GIR_Coverage, 1958,
3075 : GIR_Done,
3076 : // Label 306: @5492
3077 : GIM_Try, /*On fail goto*//*Label 307*/ 5557, // Rule ID 1962 //
3078 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3079 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3080 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3081 : // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3082 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3083 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3084 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3085 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3086 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3087 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3088 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3089 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3090 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3091 : GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3092 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3093 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3094 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3095 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3096 : GIR_EraseFromParent, /*InsnID*/0,
3097 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3098 : // GIR_Coverage, 1962,
3099 : GIR_Done,
3100 : // Label 307: @5557
3101 : GIM_Try, /*On fail goto*//*Label 308*/ 5622, // Rule ID 1963 //
3102 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3103 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3104 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3105 : // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3106 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3107 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3108 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3109 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3110 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3111 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3112 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3113 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3114 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3115 : GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3116 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3117 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3118 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3119 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3120 : GIR_EraseFromParent, /*InsnID*/0,
3121 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3122 : // GIR_Coverage, 1963,
3123 : GIR_Done,
3124 : // Label 308: @5622
3125 : GIM_Try, /*On fail goto*//*Label 309*/ 5687, // Rule ID 1967 //
3126 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3127 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3128 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3129 : // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3130 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3131 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3132 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3133 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3134 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3135 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3136 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3137 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3138 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3139 : GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3140 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3141 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3142 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3143 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3144 : GIR_EraseFromParent, /*InsnID*/0,
3145 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3146 : // GIR_Coverage, 1967,
3147 : GIR_Done,
3148 : // Label 309: @5687
3149 : GIM_Try, /*On fail goto*//*Label 310*/ 5752, // Rule ID 1968 //
3150 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3151 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3152 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3153 : // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3154 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3155 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3156 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3157 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3158 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3159 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3160 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3161 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3162 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3163 : GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3164 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3165 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3166 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3167 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3168 : GIR_EraseFromParent, /*InsnID*/0,
3169 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3170 : // GIR_Coverage, 1968,
3171 : GIR_Done,
3172 : // Label 310: @5752
3173 : GIM_Try, /*On fail goto*//*Label 311*/ 5817, // Rule ID 1972 //
3174 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3175 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3176 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3177 : // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3178 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3179 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3180 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3181 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3182 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3183 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3184 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3185 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3186 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3187 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3188 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3189 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3190 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3191 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3192 : GIR_EraseFromParent, /*InsnID*/0,
3193 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3194 : // GIR_Coverage, 1972,
3195 : GIR_Done,
3196 : // Label 311: @5817
3197 : GIM_Try, /*On fail goto*//*Label 312*/ 5882, // Rule ID 1973 //
3198 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3199 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3200 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3201 : // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3202 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3203 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3204 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3205 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3206 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3207 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3208 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3209 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3210 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3211 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3212 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3213 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3214 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3215 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3216 : GIR_EraseFromParent, /*InsnID*/0,
3217 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3218 : // GIR_Coverage, 1973,
3219 : GIR_Done,
3220 : // Label 312: @5882
3221 : GIM_Try, /*On fail goto*//*Label 313*/ 5947, // Rule ID 1977 //
3222 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3223 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3224 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3225 : // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3226 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3227 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3228 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3229 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3230 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3231 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3232 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3233 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3234 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3235 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3236 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3237 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3238 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3239 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3240 : GIR_EraseFromParent, /*InsnID*/0,
3241 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3242 : // GIR_Coverage, 1977,
3243 : GIR_Done,
3244 : // Label 313: @5947
3245 : GIM_Try, /*On fail goto*//*Label 314*/ 6012, // Rule ID 1978 //
3246 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3247 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3248 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3249 : // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3250 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3251 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3252 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3253 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3254 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3255 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3256 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3257 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3258 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3259 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3260 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3261 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3262 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3263 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3264 : GIR_EraseFromParent, /*InsnID*/0,
3265 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3266 : // GIR_Coverage, 1978,
3267 : GIR_Done,
3268 : // Label 314: @6012
3269 : GIM_Reject,
3270 : // Label 272: @6013
3271 : GIM_Try, /*On fail goto*//*Label 315*/ 6058,
3272 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3273 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
3274 : GIM_Try, /*On fail goto*//*Label 316*/ 6040, // Rule ID 1834 //
3275 : GIM_CheckFeatures, GIFBS_HasDSP,
3276 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
3277 : // (bitconvert:{ *:[v4i8] } GPR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i8] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
3278 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3279 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7,
3280 : // GIR_Coverage, 1834,
3281 : GIR_Done,
3282 : // Label 316: @6040
3283 : GIM_Try, /*On fail goto*//*Label 317*/ 6057, // Rule ID 1838 //
3284 : GIM_CheckFeatures, GIFBS_HasDSP,
3285 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
3286 : // (bitconvert:{ *:[v4i8] } FGR32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i8] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
3287 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3288 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7,
3289 : // GIR_Coverage, 1838,
3290 : GIR_Done,
3291 : // Label 317: @6057
3292 : GIM_Reject,
3293 : // Label 315: @6058
3294 : GIM_Reject,
3295 : // Label 273: @6059
3296 : GIM_Try, /*On fail goto*//*Label 318*/ 6080, // Rule ID 1917 //
3297 : GIM_CheckFeatures, GIFBS_HasMSA,
3298 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3299 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3300 : // (bitconvert:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] })
3301 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3302 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3303 : // GIR_Coverage, 1917,
3304 : GIR_Done,
3305 : // Label 318: @6080
3306 : GIM_Try, /*On fail goto*//*Label 319*/ 6101, // Rule ID 1920 //
3307 : GIM_CheckFeatures, GIFBS_HasMSA,
3308 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3309 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3310 : // (bitconvert:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] })
3311 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3312 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3313 : // GIR_Coverage, 1920,
3314 : GIR_Done,
3315 : // Label 319: @6101
3316 : GIM_Try, /*On fail goto*//*Label 320*/ 6122, // Rule ID 1933 //
3317 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3318 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3319 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3320 : // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
3321 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3322 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3323 : // GIR_Coverage, 1933,
3324 : GIR_Done,
3325 : // Label 320: @6122
3326 : GIM_Try, /*On fail goto*//*Label 321*/ 6143, // Rule ID 1934 //
3327 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3328 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3329 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3330 : // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
3331 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3332 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3333 : // GIR_Coverage, 1934,
3334 : GIR_Done,
3335 : // Label 321: @6143
3336 : GIM_Try, /*On fail goto*//*Label 322*/ 6164, // Rule ID 1935 //
3337 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3338 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3339 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3340 : // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
3341 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3342 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3343 : // GIR_Coverage, 1935,
3344 : GIR_Done,
3345 : // Label 322: @6164
3346 : GIM_Try, /*On fail goto*//*Label 323*/ 6185, // Rule ID 1936 //
3347 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3348 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3349 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3350 : // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
3351 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3352 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3353 : // GIR_Coverage, 1936,
3354 : GIR_Done,
3355 : // Label 323: @6185
3356 : GIM_Try, /*On fail goto*//*Label 324*/ 6206, // Rule ID 1937 //
3357 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3358 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3359 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3360 : // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
3361 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3362 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3363 : // GIR_Coverage, 1937,
3364 : GIR_Done,
3365 : // Label 324: @6206
3366 : GIM_Try, /*On fail goto*//*Label 325*/ 6227, // Rule ID 1943 //
3367 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3368 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3369 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3370 : // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
3371 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3372 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3373 : // GIR_Coverage, 1943,
3374 : GIR_Done,
3375 : // Label 325: @6227
3376 : GIM_Try, /*On fail goto*//*Label 326*/ 6248, // Rule ID 1944 //
3377 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3378 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3379 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3380 : // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
3381 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3382 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3383 : // GIR_Coverage, 1944,
3384 : GIR_Done,
3385 : // Label 326: @6248
3386 : GIM_Try, /*On fail goto*//*Label 327*/ 6269, // Rule ID 1945 //
3387 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3388 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3389 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3390 : // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
3391 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3392 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3393 : // GIR_Coverage, 1945,
3394 : GIR_Done,
3395 : // Label 327: @6269
3396 : GIM_Try, /*On fail goto*//*Label 328*/ 6290, // Rule ID 1946 //
3397 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3398 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3399 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3400 : // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
3401 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3402 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3403 : // GIR_Coverage, 1946,
3404 : GIR_Done,
3405 : // Label 328: @6290
3406 : GIM_Try, /*On fail goto*//*Label 329*/ 6311, // Rule ID 1947 //
3407 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3408 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3409 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3410 : // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
3411 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3412 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3413 : // GIR_Coverage, 1947,
3414 : GIR_Done,
3415 : // Label 329: @6311
3416 : GIM_Try, /*On fail goto*//*Label 330*/ 6376, // Rule ID 1955 //
3417 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3418 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3419 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3420 : // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
3421 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3422 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3423 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3424 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3425 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3426 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3427 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3428 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3429 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3430 : GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3431 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3432 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3433 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3434 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3435 : GIR_EraseFromParent, /*InsnID*/0,
3436 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3437 : // GIR_Coverage, 1955,
3438 : GIR_Done,
3439 : // Label 330: @6376
3440 : GIM_Try, /*On fail goto*//*Label 331*/ 6441, // Rule ID 1956 //
3441 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3442 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3443 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3444 : // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
3445 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3446 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3447 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3448 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3449 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3450 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3451 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3452 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3453 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3454 : GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3455 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3456 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3457 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3458 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3459 : GIR_EraseFromParent, /*InsnID*/0,
3460 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3461 : // GIR_Coverage, 1956,
3462 : GIR_Done,
3463 : // Label 331: @6441
3464 : GIM_Try, /*On fail goto*//*Label 332*/ 6506, // Rule ID 1960 //
3465 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3466 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3467 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3468 : // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3469 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3470 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3471 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3472 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3473 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3474 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3475 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3476 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3477 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3478 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3479 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3480 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3481 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3482 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3483 : GIR_EraseFromParent, /*InsnID*/0,
3484 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3485 : // GIR_Coverage, 1960,
3486 : GIR_Done,
3487 : // Label 332: @6506
3488 : GIM_Try, /*On fail goto*//*Label 333*/ 6571, // Rule ID 1961 //
3489 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3490 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3491 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3492 : // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3493 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3494 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3495 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3496 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3497 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3498 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3499 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3500 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3501 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3502 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3503 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3504 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3505 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3506 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3507 : GIR_EraseFromParent, /*InsnID*/0,
3508 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3509 : // GIR_Coverage, 1961,
3510 : GIR_Done,
3511 : // Label 333: @6571
3512 : GIM_Try, /*On fail goto*//*Label 334*/ 6636, // Rule ID 1965 //
3513 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3514 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3515 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3516 : // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3517 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3518 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3519 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3520 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3521 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3522 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3523 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3524 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3525 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3526 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3527 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3528 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3529 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3530 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3531 : GIR_EraseFromParent, /*InsnID*/0,
3532 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3533 : // GIR_Coverage, 1965,
3534 : GIR_Done,
3535 : // Label 334: @6636
3536 : GIM_Try, /*On fail goto*//*Label 335*/ 6701, // Rule ID 1966 //
3537 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3538 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3539 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3540 : // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3541 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3542 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3543 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3544 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3545 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3546 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3547 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3548 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3549 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3550 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3551 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3552 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3553 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3554 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3555 : GIR_EraseFromParent, /*InsnID*/0,
3556 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3557 : // GIR_Coverage, 1966,
3558 : GIR_Done,
3559 : // Label 335: @6701
3560 : GIM_Try, /*On fail goto*//*Label 336*/ 6766, // Rule ID 1982 //
3561 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3562 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3563 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3564 : // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3565 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3566 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3567 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3568 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3569 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3570 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3571 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3572 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3573 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3574 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3575 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3576 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3577 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3578 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3579 : GIR_EraseFromParent, /*InsnID*/0,
3580 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3581 : // GIR_Coverage, 1982,
3582 : GIR_Done,
3583 : // Label 336: @6766
3584 : GIM_Try, /*On fail goto*//*Label 337*/ 6831, // Rule ID 1983 //
3585 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3586 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3587 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3588 : // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3589 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3590 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3591 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3592 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3593 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3594 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3595 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3596 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3597 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3598 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3599 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3600 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3601 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3602 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3603 : GIR_EraseFromParent, /*InsnID*/0,
3604 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3605 : // GIR_Coverage, 1983,
3606 : GIR_Done,
3607 : // Label 337: @6831
3608 : GIM_Try, /*On fail goto*//*Label 338*/ 6896, // Rule ID 1987 //
3609 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3610 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3611 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3612 : // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3613 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3614 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3615 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3616 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3617 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3618 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3619 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3620 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3621 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3622 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3623 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3624 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3625 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3626 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3627 : GIR_EraseFromParent, /*InsnID*/0,
3628 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3629 : // GIR_Coverage, 1987,
3630 : GIR_Done,
3631 : // Label 338: @6896
3632 : GIM_Try, /*On fail goto*//*Label 339*/ 6961, // Rule ID 1988 //
3633 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3634 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3635 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3636 : // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3637 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3638 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3639 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3640 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3641 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3642 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3643 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3644 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3645 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3646 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3647 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3648 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3649 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3650 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3651 : GIR_EraseFromParent, /*InsnID*/0,
3652 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3653 : // GIR_Coverage, 1988,
3654 : GIR_Done,
3655 : // Label 339: @6961
3656 : GIM_Reject,
3657 : // Label 274: @6962
3658 : GIM_Try, /*On fail goto*//*Label 340*/ 6983, // Rule ID 1916 //
3659 : GIM_CheckFeatures, GIFBS_HasMSA,
3660 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3661 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3662 : // (bitconvert:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] })
3663 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3664 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3665 : // GIR_Coverage, 1916,
3666 : GIR_Done,
3667 : // Label 340: @6983
3668 : GIM_Try, /*On fail goto*//*Label 341*/ 7004, // Rule ID 1919 //
3669 : GIM_CheckFeatures, GIFBS_HasMSA,
3670 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3671 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3672 : // (bitconvert:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] })
3673 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3674 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3675 : // GIR_Coverage, 1919,
3676 : GIR_Done,
3677 : // Label 341: @7004
3678 : GIM_Try, /*On fail goto*//*Label 342*/ 7025, // Rule ID 1928 //
3679 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3680 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3681 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3682 : // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src, MSA128H:{ *:[i32] })
3683 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3684 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3685 : // GIR_Coverage, 1928,
3686 : GIR_Done,
3687 : // Label 342: @7025
3688 : GIM_Try, /*On fail goto*//*Label 343*/ 7046, // Rule ID 1929 //
3689 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3690 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3691 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3692 : // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] })
3693 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3694 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3695 : // GIR_Coverage, 1929,
3696 : GIR_Done,
3697 : // Label 343: @7046
3698 : GIM_Try, /*On fail goto*//*Label 344*/ 7067, // Rule ID 1930 //
3699 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3700 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3701 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3702 : // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] })
3703 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3704 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3705 : // GIR_Coverage, 1930,
3706 : GIR_Done,
3707 : // Label 344: @7067
3708 : GIM_Try, /*On fail goto*//*Label 345*/ 7088, // Rule ID 1931 //
3709 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3710 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3711 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3712 : // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] })
3713 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3714 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3715 : // GIR_Coverage, 1931,
3716 : GIR_Done,
3717 : // Label 345: @7088
3718 : GIM_Try, /*On fail goto*//*Label 346*/ 7109, // Rule ID 1932 //
3719 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3720 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3721 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3722 : // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] })
3723 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3724 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3725 : // GIR_Coverage, 1932,
3726 : GIR_Done,
3727 : // Label 346: @7109
3728 : GIM_Try, /*On fail goto*//*Label 347*/ 7174, // Rule ID 1953 //
3729 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3730 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3731 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3732 : // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3733 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3734 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3735 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3736 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3737 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3738 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3739 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3740 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3741 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3742 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3743 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3744 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3745 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3746 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3747 : GIR_EraseFromParent, /*InsnID*/0,
3748 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3749 : // GIR_Coverage, 1953,
3750 : GIR_Done,
3751 : // Label 347: @7174
3752 : GIM_Try, /*On fail goto*//*Label 348*/ 7239, // Rule ID 1954 //
3753 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3754 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3755 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3756 : // (bitconvert:{ *:[v8f16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3757 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3758 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3759 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3760 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3761 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3762 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3763 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3764 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3765 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3766 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3767 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3768 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3769 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3770 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3771 : GIR_EraseFromParent, /*InsnID*/0,
3772 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3773 : // GIR_Coverage, 1954,
3774 : GIR_Done,
3775 : // Label 348: @7239
3776 : GIM_Try, /*On fail goto*//*Label 349*/ 7304, // Rule ID 1970 //
3777 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3778 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3779 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3780 : // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3781 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3782 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3783 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3784 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3785 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3786 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3787 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3788 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3789 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3790 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3791 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3792 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3793 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3794 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3795 : GIR_EraseFromParent, /*InsnID*/0,
3796 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3797 : // GIR_Coverage, 1970,
3798 : GIR_Done,
3799 : // Label 349: @7304
3800 : GIM_Try, /*On fail goto*//*Label 350*/ 7369, // Rule ID 1971 //
3801 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3802 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3803 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3804 : // (bitconvert:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3805 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3806 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3807 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3808 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3809 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3810 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3811 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3812 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3813 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3814 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3815 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3816 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3817 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3818 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3819 : GIR_EraseFromParent, /*InsnID*/0,
3820 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3821 : // GIR_Coverage, 1971,
3822 : GIR_Done,
3823 : // Label 350: @7369
3824 : GIM_Try, /*On fail goto*//*Label 351*/ 7434, // Rule ID 1975 //
3825 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3826 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3827 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3828 : // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3829 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3830 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3831 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3832 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3833 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3834 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3835 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3836 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3837 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3838 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3839 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3840 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3841 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3842 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3843 : GIR_EraseFromParent, /*InsnID*/0,
3844 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3845 : // GIR_Coverage, 1975,
3846 : GIR_Done,
3847 : // Label 351: @7434
3848 : GIM_Try, /*On fail goto*//*Label 352*/ 7499, // Rule ID 1976 //
3849 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3850 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3851 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3852 : // (bitconvert:{ *:[v8f16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3853 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3854 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3855 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3856 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3857 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3858 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3859 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3860 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3861 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3862 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3863 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3864 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3865 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3866 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3867 : GIR_EraseFromParent, /*InsnID*/0,
3868 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3869 : // GIR_Coverage, 1976,
3870 : GIR_Done,
3871 : // Label 352: @7499
3872 : GIM_Try, /*On fail goto*//*Label 353*/ 7564, // Rule ID 1980 //
3873 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3874 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3875 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3876 : // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3877 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3878 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3879 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3880 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3881 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3882 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3883 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3884 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3885 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3886 : GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3887 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3888 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3889 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3890 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3891 : GIR_EraseFromParent, /*InsnID*/0,
3892 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3893 : // GIR_Coverage, 1980,
3894 : GIR_Done,
3895 : // Label 353: @7564
3896 : GIM_Try, /*On fail goto*//*Label 354*/ 7629, // Rule ID 1981 //
3897 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3898 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3899 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3900 : // (bitconvert:{ *:[v8f16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3901 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3902 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3903 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3904 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3905 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3906 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3907 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3908 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3909 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3910 : GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3911 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3912 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3913 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3914 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3915 : GIR_EraseFromParent, /*InsnID*/0,
3916 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3917 : // GIR_Coverage, 1981,
3918 : GIR_Done,
3919 : // Label 354: @7629
3920 : GIM_Try, /*On fail goto*//*Label 355*/ 7694, // Rule ID 1985 //
3921 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3922 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3923 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3924 : // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3925 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3926 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3927 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3928 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3929 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3930 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3931 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3932 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3933 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3934 : GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3935 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3936 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3937 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3938 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3939 : GIR_EraseFromParent, /*InsnID*/0,
3940 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3941 : // GIR_Coverage, 1985,
3942 : GIR_Done,
3943 : // Label 355: @7694
3944 : GIM_Try, /*On fail goto*//*Label 356*/ 7759, // Rule ID 1986 //
3945 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3946 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3947 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3948 : // (bitconvert:{ *:[v8f16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3949 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3950 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3951 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3952 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3953 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3954 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3955 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3956 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3957 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3958 : GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3959 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3960 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3961 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3962 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3963 : GIR_EraseFromParent, /*InsnID*/0,
3964 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3965 : // GIR_Coverage, 1986,
3966 : GIR_Done,
3967 : // Label 356: @7759
3968 : GIM_Reject,
3969 : // Label 275: @7760
3970 : GIM_Try, /*On fail goto*//*Label 357*/ 7781, // Rule ID 1922 //
3971 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3972 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3973 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
3974 : // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] })
3975 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3976 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
3977 : // GIR_Coverage, 1922,
3978 : GIR_Done,
3979 : // Label 357: @7781
3980 : GIM_Try, /*On fail goto*//*Label 358*/ 7802, // Rule ID 1923 //
3981 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3982 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3983 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
3984 : // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] })
3985 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3986 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
3987 : // GIR_Coverage, 1923,
3988 : GIR_Done,
3989 : // Label 358: @7802
3990 : GIM_Try, /*On fail goto*//*Label 359*/ 7823, // Rule ID 1924 //
3991 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3992 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3993 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
3994 : // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] })
3995 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3996 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
3997 : // GIR_Coverage, 1924,
3998 : GIR_Done,
3999 : // Label 359: @7823
4000 : GIM_Try, /*On fail goto*//*Label 360*/ 7844, // Rule ID 1925 //
4001 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4002 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4003 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4004 : // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] })
4005 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4006 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4007 : // GIR_Coverage, 1925,
4008 : GIR_Done,
4009 : // Label 360: @7844
4010 : GIM_Try, /*On fail goto*//*Label 361*/ 7865, // Rule ID 1926 //
4011 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4012 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4013 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4014 : // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] })
4015 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4016 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4017 : // GIR_Coverage, 1926,
4018 : GIR_Done,
4019 : // Label 361: @7865
4020 : GIM_Try, /*On fail goto*//*Label 362*/ 7886, // Rule ID 1927 //
4021 : GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4022 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4023 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4024 : // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] })
4025 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4026 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4027 : // GIR_Coverage, 1927,
4028 : GIR_Done,
4029 : // Label 362: @7886
4030 : GIM_Try, /*On fail goto*//*Label 363*/ 7951, // Rule ID 1959 //
4031 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4032 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4033 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4034 : // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4035 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4036 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4037 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4038 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4039 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4040 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4041 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4042 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4043 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4044 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4045 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4046 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4047 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4048 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4049 : GIR_EraseFromParent, /*InsnID*/0,
4050 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4051 : // GIR_Coverage, 1959,
4052 : GIR_Done,
4053 : // Label 363: @7951
4054 : GIM_Try, /*On fail goto*//*Label 364*/ 8016, // Rule ID 1964 //
4055 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4056 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4057 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4058 : // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4059 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4060 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4061 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4062 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4063 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4064 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4065 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4066 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4067 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4068 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4069 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4070 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4071 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4072 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4073 : GIR_EraseFromParent, /*InsnID*/0,
4074 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4075 : // GIR_Coverage, 1964,
4076 : GIR_Done,
4077 : // Label 364: @8016
4078 : GIM_Try, /*On fail goto*//*Label 365*/ 8081, // Rule ID 1969 //
4079 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4080 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4081 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4082 : // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
4083 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4084 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4085 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4086 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4087 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4088 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4089 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4090 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4091 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4092 : GIR_AddImm, /*InsnID*/1, /*Imm*/27,
4093 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4094 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4095 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4096 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4097 : GIR_EraseFromParent, /*InsnID*/0,
4098 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4099 : // GIR_Coverage, 1969,
4100 : GIR_Done,
4101 : // Label 365: @8081
4102 : GIM_Try, /*On fail goto*//*Label 366*/ 8146, // Rule ID 1974 //
4103 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4104 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4105 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4106 : // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
4107 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4108 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4109 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4110 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4111 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4112 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4113 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4114 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4115 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4116 : GIR_AddImm, /*InsnID*/1, /*Imm*/27,
4117 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4118 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4119 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4120 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4121 : GIR_EraseFromParent, /*InsnID*/0,
4122 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4123 : // GIR_Coverage, 1974,
4124 : GIR_Done,
4125 : // Label 366: @8146
4126 : GIM_Try, /*On fail goto*//*Label 367*/ 8246, // Rule ID 1979 //
4127 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4128 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4129 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4130 : // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4131 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4132 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4133 : GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
4134 : GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
4135 : GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
4136 : GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
4137 : GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
4138 : GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
4139 : GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
4140 : GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
4141 : GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
4142 : GIR_AddImm, /*InsnID*/3, /*Imm*/27,
4143 : GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4144 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4145 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4146 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
4147 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4148 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
4149 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4150 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4151 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4152 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4153 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4154 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4155 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4156 : GIR_EraseFromParent, /*InsnID*/0,
4157 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4158 : // GIR_Coverage, 1979,
4159 : GIR_Done,
4160 : // Label 367: @8246
4161 : GIM_Try, /*On fail goto*//*Label 368*/ 8346, // Rule ID 1984 //
4162 : GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4163 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4164 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4165 : // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4166 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4167 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4168 : GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
4169 : GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
4170 : GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
4171 : GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
4172 : GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
4173 : GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
4174 : GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
4175 : GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
4176 : GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
4177 : GIR_AddImm, /*InsnID*/3, /*Imm*/27,
4178 : GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4179 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4180 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4181 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
4182 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4183 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
4184 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4185 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4186 : GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4187 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4188 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4189 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4190 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4191 : GIR_EraseFromParent, /*InsnID*/0,
4192 : GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4193 : // GIR_Coverage, 1984,
4194 : GIR_Done,
4195 : // Label 368: @8346
4196 : GIM_Reject,
4197 : // Label 276: @8347
4198 : GIM_Reject,
4199 : // Label 11: @8348
4200 : GIM_Try, /*On fail goto*//*Label 369*/ 8413, // Rule ID 1907 //
4201 : GIM_CheckFeatures, GIFBS_HasDSP,
4202 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4203 : GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
4204 : GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
4205 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4206 : // MIs[0] Operand 1
4207 : GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4208 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4209 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4210 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4211 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4212 : GIM_CheckIsSafeToFold, /*InsnID*/1,
4213 : // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LWX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4214 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LWX,
4215 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4216 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4217 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4218 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
4219 : GIR_EraseFromParent, /*InsnID*/0,
4220 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4221 : // GIR_Coverage, 1907,
4222 : GIR_Done,
4223 : // Label 369: @8413
4224 : GIM_Reject,
4225 : // Label 12: @8414
4226 : GIM_Try, /*On fail goto*//*Label 370*/ 8479, // Rule ID 1906 //
4227 : GIM_CheckFeatures, GIFBS_HasDSP,
4228 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4229 : GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
4230 : GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
4231 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4232 : // MIs[0] Operand 1
4233 : GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4234 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4235 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4236 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4237 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4238 : GIM_CheckIsSafeToFold, /*InsnID*/1,
4239 : // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LHX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4240 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LHX,
4241 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4242 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4243 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4244 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
4245 : GIR_EraseFromParent, /*InsnID*/0,
4246 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4247 : // GIR_Coverage, 1906,
4248 : GIR_Done,
4249 : // Label 370: @8479
4250 : GIM_Reject,
4251 : // Label 13: @8480
4252 : GIM_Try, /*On fail goto*//*Label 371*/ 8545, // Rule ID 1905 //
4253 : GIM_CheckFeatures, GIFBS_HasDSP,
4254 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4255 : GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
4256 : GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
4257 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4258 : // MIs[0] Operand 1
4259 : GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4260 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4261 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4262 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4263 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4264 : GIM_CheckIsSafeToFold, /*InsnID*/1,
4265 : // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LBUX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4266 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LBUX,
4267 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4268 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4269 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4270 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
4271 : GIR_EraseFromParent, /*InsnID*/0,
4272 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4273 : // GIR_Coverage, 1905,
4274 : GIR_Done,
4275 : // Label 371: @8545
4276 : GIM_Reject,
4277 : // Label 14: @8546
4278 : GIM_Try, /*On fail goto*//*Label 372*/ 10740,
4279 : GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
4280 : GIM_Try, /*On fail goto*//*Label 373*/ 8598, // Rule ID 400 //
4281 : GIM_CheckFeatures, GIFBS_HasDSP,
4282 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
4283 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
4284 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4285 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4286 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4287 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4288 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt8,
4289 : // MIs[1] Operand 1
4290 : // No operand predicates
4291 : GIM_CheckIsSafeToFold, /*InsnID*/1,
4292 : // (intrinsic_wo_chain:{ *:[v4i8] } 3509:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm) => (REPL_QB:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
4293 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_QB,
4294 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4295 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4296 : GIR_EraseFromParent, /*InsnID*/0,
4297 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4298 : // GIR_Coverage, 400,
4299 : GIR_Done,
4300 : // Label 373: @8598
4301 : GIM_Try, /*On fail goto*//*Label 374*/ 8645, // Rule ID 401 //
4302 : GIM_CheckFeatures, GIFBS_HasDSP,
4303 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
4304 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4305 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4306 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4307 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4308 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4309 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExt10,
4310 : // MIs[1] Operand 1
4311 : // No operand predicates
4312 : GIM_CheckIsSafeToFold, /*InsnID*/1,
4313 : // (intrinsic_wo_chain:{ *:[v2i16] } 3508:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm) => (REPL_PH:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
4314 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_PH,
4315 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4316 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4317 : GIR_EraseFromParent, /*InsnID*/0,
4318 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4319 : // GIR_Coverage, 401,
4320 : GIR_Done,
4321 : // Label 374: @8645
4322 : GIM_Try, /*On fail goto*//*Label 375*/ 8692, // Rule ID 1254 //
4323 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
4324 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
4325 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4326 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4327 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4328 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4329 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4330 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExt10,
4331 : // MIs[1] Operand 1
4332 : // No operand predicates
4333 : GIM_CheckIsSafeToFold, /*InsnID*/1,
4334 : // (intrinsic_wo_chain:{ *:[v2i16] } 3508:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm) => (REPL_PH_MM:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
4335 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_PH_MM,
4336 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4337 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4338 : GIR_EraseFromParent, /*InsnID*/0,
4339 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4340 : // GIR_Coverage, 1254,
4341 : GIR_Done,
4342 : // Label 375: @8692
4343 : GIM_Try, /*On fail goto*//*Label 376*/ 8739, // Rule ID 1255 //
4344 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
4345 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
4346 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
4347 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4348 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4349 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4350 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4351 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt8,
4352 : // MIs[1] Operand 1
4353 : // No operand predicates
4354 : GIM_CheckIsSafeToFold, /*InsnID*/1,
4355 : // (intrinsic_wo_chain:{ *:[v4i8] } 3509:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm) => (REPL_QB_MM:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
4356 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_QB_MM,
4357 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
4358 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4359 : GIR_EraseFromParent, /*InsnID*/0,
4360 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4361 : // GIR_Coverage, 1255,
4362 : GIR_Done,
4363 : // Label 376: @8739
4364 : GIM_Try, /*On fail goto*//*Label 377*/ 8779, // Rule ID 334 //
4365 : GIM_CheckFeatures, GIFBS_HasDSP,
4366 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_raddu_w_qb,
4367 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4368 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4369 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4370 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4371 : // (intrinsic_wo_chain:{ *:[i32] } 3506:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (RADDU_W_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
4372 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RADDU_W_QB,
4373 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4374 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
4375 : GIR_EraseFromParent, /*InsnID*/0,
4376 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4377 : // GIR_Coverage, 334,
4378 : GIR_Done,
4379 : // Label 377: @8779
4380 : GIM_Try, /*On fail goto*//*Label 378*/ 8819, // Rule ID 341 //
4381 : GIM_CheckFeatures, GIFBS_HasDSP,
4382 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phl,
4383 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4384 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
4385 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4386 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4387 : // (intrinsic_wo_chain:{ *:[i32] } 3488:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECEQ_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
4388 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHL,
4389 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4390 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4391 : GIR_EraseFromParent, /*InsnID*/0,
4392 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4393 : // GIR_Coverage, 341,
4394 : GIR_Done,
4395 : // Label 378: @8819
4396 : GIM_Try, /*On fail goto*//*Label 379*/ 8859, // Rule ID 342 //
4397 : GIM_CheckFeatures, GIFBS_HasDSP,
4398 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phr,
4399 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4400 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
4401 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4402 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4403 : // (intrinsic_wo_chain:{ *:[i32] } 3489:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECEQ_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
4404 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHR,
4405 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4406 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4407 : GIR_EraseFromParent, /*InsnID*/0,
4408 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4409 : // GIR_Coverage, 342,
4410 : GIR_Done,
4411 : // Label 379: @8859
4412 : GIM_Try, /*On fail goto*//*Label 380*/ 8899, // Rule ID 343 //
4413 : GIM_CheckFeatures, GIFBS_HasDSP,
4414 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbl,
4415 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4416 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4417 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4418 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4419 : // (intrinsic_wo_chain:{ *:[v2i16] } 3490:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4420 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBL,
4421 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4422 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4423 : GIR_EraseFromParent, /*InsnID*/0,
4424 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4425 : // GIR_Coverage, 343,
4426 : GIR_Done,
4427 : // Label 380: @8899
4428 : GIM_Try, /*On fail goto*//*Label 381*/ 8939, // Rule ID 344 //
4429 : GIM_CheckFeatures, GIFBS_HasDSP,
4430 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbr,
4431 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4432 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4433 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4434 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4435 : // (intrinsic_wo_chain:{ *:[v2i16] } 3492:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4436 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBR,
4437 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4438 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4439 : GIR_EraseFromParent, /*InsnID*/0,
4440 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4441 : // GIR_Coverage, 344,
4442 : GIR_Done,
4443 : // Label 381: @8939
4444 : GIM_Try, /*On fail goto*//*Label 382*/ 8979, // Rule ID 345 //
4445 : GIM_CheckFeatures, GIFBS_HasDSP,
4446 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbla,
4447 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4448 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4449 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4450 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4451 : // (intrinsic_wo_chain:{ *:[v2i16] } 3491:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4452 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBLA,
4453 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4454 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4455 : GIR_EraseFromParent, /*InsnID*/0,
4456 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4457 : // GIR_Coverage, 345,
4458 : GIR_Done,
4459 : // Label 382: @8979
4460 : GIM_Try, /*On fail goto*//*Label 383*/ 9019, // Rule ID 346 //
4461 : GIM_CheckFeatures, GIFBS_HasDSP,
4462 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbra,
4463 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4464 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4465 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4466 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4467 : // (intrinsic_wo_chain:{ *:[v2i16] } 3493:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4468 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBRA,
4469 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4470 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4471 : GIR_EraseFromParent, /*InsnID*/0,
4472 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4473 : // GIR_Coverage, 346,
4474 : GIR_Done,
4475 : // Label 383: @9019
4476 : GIM_Try, /*On fail goto*//*Label 384*/ 9059, // Rule ID 347 //
4477 : GIM_CheckFeatures, GIFBS_HasDSP,
4478 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbl,
4479 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4480 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4481 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4482 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4483 : // (intrinsic_wo_chain:{ *:[v2i16] } 3494:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4484 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBL,
4485 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4486 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4487 : GIR_EraseFromParent, /*InsnID*/0,
4488 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4489 : // GIR_Coverage, 347,
4490 : GIR_Done,
4491 : // Label 384: @9059
4492 : GIM_Try, /*On fail goto*//*Label 385*/ 9099, // Rule ID 348 //
4493 : GIM_CheckFeatures, GIFBS_HasDSP,
4494 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbr,
4495 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4496 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4497 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4498 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4499 : // (intrinsic_wo_chain:{ *:[v2i16] } 3496:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4500 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBR,
4501 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4502 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4503 : GIR_EraseFromParent, /*InsnID*/0,
4504 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4505 : // GIR_Coverage, 348,
4506 : GIR_Done,
4507 : // Label 385: @9099
4508 : GIM_Try, /*On fail goto*//*Label 386*/ 9139, // Rule ID 349 //
4509 : GIM_CheckFeatures, GIFBS_HasDSP,
4510 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbla,
4511 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4512 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4513 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4514 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4515 : // (intrinsic_wo_chain:{ *:[v2i16] } 3495:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4516 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBLA,
4517 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4518 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4519 : GIR_EraseFromParent, /*InsnID*/0,
4520 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4521 : // GIR_Coverage, 349,
4522 : GIR_Done,
4523 : // Label 386: @9139
4524 : GIM_Try, /*On fail goto*//*Label 387*/ 9179, // Rule ID 350 //
4525 : GIM_CheckFeatures, GIFBS_HasDSP,
4526 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbra,
4527 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4528 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4529 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4530 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4531 : // (intrinsic_wo_chain:{ *:[v2i16] } 3497:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4532 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBRA,
4533 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4534 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4535 : GIR_EraseFromParent, /*InsnID*/0,
4536 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4537 : // GIR_Coverage, 350,
4538 : GIR_Done,
4539 : // Label 387: @9179
4540 : GIM_Try, /*On fail goto*//*Label 388*/ 9219, // Rule ID 398 //
4541 : GIM_CheckFeatures, GIFBS_HasDSP,
4542 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_bitrev,
4543 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4544 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4545 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4546 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
4547 : // (intrinsic_wo_chain:{ *:[i32] } 3064:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (BITREV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
4548 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BITREV,
4549 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4550 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4551 : GIR_EraseFromParent, /*InsnID*/0,
4552 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4553 : // GIR_Coverage, 398,
4554 : GIR_Done,
4555 : // Label 388: @9219
4556 : GIM_Try, /*On fail goto*//*Label 389*/ 9259, // Rule ID 402 //
4557 : GIM_CheckFeatures, GIFBS_HasDSP,
4558 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
4559 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
4560 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4561 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4562 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
4563 : // (intrinsic_wo_chain:{ *:[v4i8] } 3509:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (REPLV_QB:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rt)
4564 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_QB,
4565 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4566 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4567 : GIR_EraseFromParent, /*InsnID*/0,
4568 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4569 : // GIR_Coverage, 402,
4570 : GIR_Done,
4571 : // Label 389: @9259
4572 : GIM_Try, /*On fail goto*//*Label 390*/ 9299, // Rule ID 403 //
4573 : GIM_CheckFeatures, GIFBS_HasDSP,
4574 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
4575 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4576 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4577 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4578 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
4579 : // (intrinsic_wo_chain:{ *:[v2i16] } 3508:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (REPLV_PH:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rt)
4580 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_PH,
4581 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4582 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4583 : GIR_EraseFromParent, /*InsnID*/0,
4584 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4585 : // GIR_Coverage, 403,
4586 : GIR_Done,
4587 : // Label 390: @9299
4588 : GIM_Try, /*On fail goto*//*Label 391*/ 9339, // Rule ID 648 //
4589 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4590 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fclass_w,
4591 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4592 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4593 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4594 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4595 : // (intrinsic_wo_chain:{ *:[v4i32] } 3216:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FCLASS_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
4596 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCLASS_W,
4597 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4598 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4599 : GIR_EraseFromParent, /*InsnID*/0,
4600 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4601 : // GIR_Coverage, 648,
4602 : GIR_Done,
4603 : // Label 391: @9339
4604 : GIM_Try, /*On fail goto*//*Label 392*/ 9379, // Rule ID 649 //
4605 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4606 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fclass_d,
4607 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4608 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
4609 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4610 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
4611 : // (intrinsic_wo_chain:{ *:[v2i64] } 3215:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FCLASS_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
4612 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCLASS_D,
4613 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4614 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4615 : GIR_EraseFromParent, /*InsnID*/0,
4616 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4617 : // GIR_Coverage, 649,
4618 : GIR_Done,
4619 : // Label 392: @9379
4620 : GIM_Try, /*On fail goto*//*Label 393*/ 9419, // Rule ID 672 //
4621 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4622 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupl_w,
4623 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4624 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4625 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4626 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
4627 : // (intrinsic_wo_chain:{ *:[v4f32] } 3242:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws) => (FEXUPL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
4628 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPL_W,
4629 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4630 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4631 : GIR_EraseFromParent, /*InsnID*/0,
4632 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4633 : // GIR_Coverage, 672,
4634 : GIR_Done,
4635 : // Label 393: @9419
4636 : GIM_Try, /*On fail goto*//*Label 394*/ 9459, // Rule ID 673 //
4637 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4638 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupl_d,
4639 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4640 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4641 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4642 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4643 : // (intrinsic_wo_chain:{ *:[v2f64] } 3241:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXUPL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
4644 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPL_D,
4645 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4646 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4647 : GIR_EraseFromParent, /*InsnID*/0,
4648 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4649 : // GIR_Coverage, 673,
4650 : GIR_Done,
4651 : // Label 394: @9459
4652 : GIM_Try, /*On fail goto*//*Label 395*/ 9499, // Rule ID 674 //
4653 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4654 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupr_w,
4655 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4656 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4657 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4658 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
4659 : // (intrinsic_wo_chain:{ *:[v4f32] } 3244:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws) => (FEXUPR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
4660 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPR_W,
4661 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4662 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4663 : GIR_EraseFromParent, /*InsnID*/0,
4664 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4665 : // GIR_Coverage, 674,
4666 : GIR_Done,
4667 : // Label 395: @9499
4668 : GIM_Try, /*On fail goto*//*Label 396*/ 9539, // Rule ID 675 //
4669 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4670 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupr_d,
4671 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4672 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4673 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4674 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4675 : // (intrinsic_wo_chain:{ *:[v2f64] } 3243:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXUPR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
4676 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPR_D,
4677 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4678 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4679 : GIR_EraseFromParent, /*InsnID*/0,
4680 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4681 : // GIR_Coverage, 675,
4682 : GIR_Done,
4683 : // Label 396: @9539
4684 : GIM_Try, /*On fail goto*//*Label 397*/ 9579, // Rule ID 680 //
4685 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4686 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffql_w,
4687 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4688 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4689 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4690 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
4691 : // (intrinsic_wo_chain:{ *:[v4f32] } 3250:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (FFQL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
4692 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQL_W,
4693 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4694 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4695 : GIR_EraseFromParent, /*InsnID*/0,
4696 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4697 : // GIR_Coverage, 680,
4698 : GIR_Done,
4699 : // Label 397: @9579
4700 : GIM_Try, /*On fail goto*//*Label 398*/ 9619, // Rule ID 681 //
4701 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4702 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffql_d,
4703 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4704 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4705 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4706 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4707 : // (intrinsic_wo_chain:{ *:[v2f64] } 3249:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFQL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws)
4708 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQL_D,
4709 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4710 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4711 : GIR_EraseFromParent, /*InsnID*/0,
4712 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4713 : // GIR_Coverage, 681,
4714 : GIR_Done,
4715 : // Label 398: @9619
4716 : GIM_Try, /*On fail goto*//*Label 399*/ 9659, // Rule ID 682 //
4717 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4718 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffqr_w,
4719 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4720 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4721 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4722 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
4723 : // (intrinsic_wo_chain:{ *:[v4f32] } 3252:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (FFQR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
4724 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQR_W,
4725 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4726 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4727 : GIR_EraseFromParent, /*InsnID*/0,
4728 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4729 : // GIR_Coverage, 682,
4730 : GIR_Done,
4731 : // Label 399: @9659
4732 : GIM_Try, /*On fail goto*//*Label 400*/ 9699, // Rule ID 683 //
4733 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4734 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffqr_d,
4735 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4736 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4737 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4738 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4739 : // (intrinsic_wo_chain:{ *:[v2f64] } 3251:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFQR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws)
4740 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQR_D,
4741 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4742 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4743 : GIR_EraseFromParent, /*InsnID*/0,
4744 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4745 : // GIR_Coverage, 683,
4746 : GIR_Done,
4747 : // Label 400: @9699
4748 : GIM_Try, /*On fail goto*//*Label 401*/ 9739, // Rule ID 708 //
4749 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4750 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frcp_w,
4751 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4752 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4753 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4754 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4755 : // (intrinsic_wo_chain:{ *:[v4f32] } 3274:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRCP_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
4756 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRCP_W,
4757 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4758 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4759 : GIR_EraseFromParent, /*InsnID*/0,
4760 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4761 : // GIR_Coverage, 708,
4762 : GIR_Done,
4763 : // Label 401: @9739
4764 : GIM_Try, /*On fail goto*//*Label 402*/ 9779, // Rule ID 709 //
4765 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4766 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frcp_d,
4767 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4768 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
4769 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4770 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
4771 : // (intrinsic_wo_chain:{ *:[v2f64] } 3273:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRCP_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
4772 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRCP_D,
4773 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4774 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4775 : GIR_EraseFromParent, /*InsnID*/0,
4776 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4777 : // GIR_Coverage, 709,
4778 : GIR_Done,
4779 : // Label 402: @9779
4780 : GIM_Try, /*On fail goto*//*Label 403*/ 9819, // Rule ID 710 //
4781 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4782 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frsqrt_w,
4783 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4784 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4785 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4786 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4787 : // (intrinsic_wo_chain:{ *:[v4f32] } 3278:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRSQRT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
4788 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRSQRT_W,
4789 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4790 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4791 : GIR_EraseFromParent, /*InsnID*/0,
4792 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4793 : // GIR_Coverage, 710,
4794 : GIR_Done,
4795 : // Label 403: @9819
4796 : GIM_Try, /*On fail goto*//*Label 404*/ 9859, // Rule ID 711 //
4797 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4798 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frsqrt_d,
4799 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4800 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
4801 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4802 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
4803 : // (intrinsic_wo_chain:{ *:[v2f64] } 3277:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRSQRT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
4804 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRSQRT_D,
4805 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4806 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4807 : GIR_EraseFromParent, /*InsnID*/0,
4808 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4809 : // GIR_Coverage, 711,
4810 : GIR_Done,
4811 : // Label 404: @9859
4812 : GIM_Try, /*On fail goto*//*Label 405*/ 9899, // Rule ID 738 //
4813 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4814 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_s_w,
4815 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4816 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4817 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4818 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4819 : // (intrinsic_wo_chain:{ *:[v4i32] } 3306:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTINT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
4820 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_S_W,
4821 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4822 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4823 : GIR_EraseFromParent, /*InsnID*/0,
4824 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4825 : // GIR_Coverage, 738,
4826 : GIR_Done,
4827 : // Label 405: @9899
4828 : GIM_Try, /*On fail goto*//*Label 406*/ 9939, // Rule ID 739 //
4829 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4830 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_s_d,
4831 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4832 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
4833 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4834 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
4835 : // (intrinsic_wo_chain:{ *:[v2i64] } 3305:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTINT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
4836 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_S_D,
4837 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4838 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4839 : GIR_EraseFromParent, /*InsnID*/0,
4840 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4841 : // GIR_Coverage, 739,
4842 : GIR_Done,
4843 : // Label 406: @9939
4844 : GIM_Try, /*On fail goto*//*Label 407*/ 9979, // Rule ID 740 //
4845 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4846 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_u_w,
4847 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4848 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4849 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4850 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4851 : // (intrinsic_wo_chain:{ *:[v4i32] } 3308:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTINT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
4852 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_U_W,
4853 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4854 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4855 : GIR_EraseFromParent, /*InsnID*/0,
4856 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4857 : // GIR_Coverage, 740,
4858 : GIR_Done,
4859 : // Label 407: @9979
4860 : GIM_Try, /*On fail goto*//*Label 408*/ 10019, // Rule ID 741 //
4861 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4862 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_u_d,
4863 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4864 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
4865 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4866 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
4867 : // (intrinsic_wo_chain:{ *:[v2i64] } 3307:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTINT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
4868 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_U_D,
4869 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4870 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4871 : GIR_EraseFromParent, /*InsnID*/0,
4872 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4873 : // GIR_Coverage, 741,
4874 : GIR_Done,
4875 : // Label 408: @10019
4876 : GIM_Try, /*On fail goto*//*Label 409*/ 10059, // Rule ID 876 //
4877 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4878 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_b,
4879 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
4880 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
4881 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4882 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
4883 : // (intrinsic_wo_chain:{ *:[v16i8] } 3461:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws) => (NLOC_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
4884 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_B,
4885 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4886 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4887 : GIR_EraseFromParent, /*InsnID*/0,
4888 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4889 : // GIR_Coverage, 876,
4890 : GIR_Done,
4891 : // Label 409: @10059
4892 : GIM_Try, /*On fail goto*//*Label 410*/ 10099, // Rule ID 877 //
4893 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4894 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_h,
4895 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
4896 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4897 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
4898 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
4899 : // (intrinsic_wo_chain:{ *:[v8i16] } 3463:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (NLOC_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
4900 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_H,
4901 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4902 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4903 : GIR_EraseFromParent, /*InsnID*/0,
4904 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4905 : // GIR_Coverage, 877,
4906 : GIR_Done,
4907 : // Label 410: @10099
4908 : GIM_Try, /*On fail goto*//*Label 411*/ 10139, // Rule ID 878 //
4909 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4910 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_w,
4911 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4912 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4913 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4914 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4915 : // (intrinsic_wo_chain:{ *:[v4i32] } 3464:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (NLOC_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
4916 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_W,
4917 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4918 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4919 : GIR_EraseFromParent, /*InsnID*/0,
4920 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4921 : // GIR_Coverage, 878,
4922 : GIR_Done,
4923 : // Label 411: @10139
4924 : GIM_Try, /*On fail goto*//*Label 412*/ 10179, // Rule ID 879 //
4925 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4926 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_d,
4927 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4928 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
4929 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4930 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
4931 : // (intrinsic_wo_chain:{ *:[v2i64] } 3462:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws) => (NLOC_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
4932 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_D,
4933 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4934 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4935 : GIR_EraseFromParent, /*InsnID*/0,
4936 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4937 : // GIR_Coverage, 879,
4938 : GIR_Done,
4939 : // Label 412: @10179
4940 : GIM_Try, /*On fail goto*//*Label 413*/ 10219, // Rule ID 1217 //
4941 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
4942 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phl,
4943 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4944 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
4945 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4946 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4947 : // (intrinsic_wo_chain:{ *:[i32] } 3488:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (PRECEQ_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs)
4948 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHL_MM,
4949 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
4950 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
4951 : GIR_EraseFromParent, /*InsnID*/0,
4952 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4953 : // GIR_Coverage, 1217,
4954 : GIR_Done,
4955 : // Label 413: @10219
4956 : GIM_Try, /*On fail goto*//*Label 414*/ 10259, // Rule ID 1218 //
4957 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
4958 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phr,
4959 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4960 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
4961 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4962 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4963 : // (intrinsic_wo_chain:{ *:[i32] } 3489:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (PRECEQ_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs)
4964 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHR_MM,
4965 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
4966 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
4967 : GIR_EraseFromParent, /*InsnID*/0,
4968 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4969 : // GIR_Coverage, 1218,
4970 : GIR_Done,
4971 : // Label 414: @10259
4972 : GIM_Try, /*On fail goto*//*Label 415*/ 10299, // Rule ID 1219 //
4973 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
4974 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbl,
4975 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4976 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4977 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4978 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4979 : // (intrinsic_wo_chain:{ *:[v2i16] } 3490:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
4980 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBL_MM,
4981 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
4982 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
4983 : GIR_EraseFromParent, /*InsnID*/0,
4984 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4985 : // GIR_Coverage, 1219,
4986 : GIR_Done,
4987 : // Label 415: @10299
4988 : GIM_Try, /*On fail goto*//*Label 416*/ 10339, // Rule ID 1220 //
4989 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
4990 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbla,
4991 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4992 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4993 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4994 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4995 : // (intrinsic_wo_chain:{ *:[v2i16] } 3491:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
4996 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBLA_MM,
4997 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
4998 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
4999 : GIR_EraseFromParent, /*InsnID*/0,
5000 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5001 : // GIR_Coverage, 1220,
5002 : GIR_Done,
5003 : // Label 416: @10339
5004 : GIM_Try, /*On fail goto*//*Label 417*/ 10379, // Rule ID 1221 //
5005 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5006 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbr,
5007 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5008 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5009 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5010 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5011 : // (intrinsic_wo_chain:{ *:[v2i16] } 3492:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
5012 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBR_MM,
5013 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5014 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5015 : GIR_EraseFromParent, /*InsnID*/0,
5016 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5017 : // GIR_Coverage, 1221,
5018 : GIR_Done,
5019 : // Label 417: @10379
5020 : GIM_Try, /*On fail goto*//*Label 418*/ 10419, // Rule ID 1222 //
5021 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5022 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbra,
5023 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5024 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5025 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5026 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5027 : // (intrinsic_wo_chain:{ *:[v2i16] } 3493:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
5028 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBRA_MM,
5029 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5030 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5031 : GIR_EraseFromParent, /*InsnID*/0,
5032 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5033 : // GIR_Coverage, 1222,
5034 : GIR_Done,
5035 : // Label 418: @10419
5036 : GIM_Try, /*On fail goto*//*Label 419*/ 10459, // Rule ID 1223 //
5037 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5038 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbl,
5039 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5040 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5041 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5042 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5043 : // (intrinsic_wo_chain:{ *:[v2i16] } 3494:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
5044 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBL_MM,
5045 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5046 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5047 : GIR_EraseFromParent, /*InsnID*/0,
5048 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5049 : // GIR_Coverage, 1223,
5050 : GIR_Done,
5051 : // Label 419: @10459
5052 : GIM_Try, /*On fail goto*//*Label 420*/ 10499, // Rule ID 1224 //
5053 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5054 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbla,
5055 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5056 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5057 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5058 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5059 : // (intrinsic_wo_chain:{ *:[v2i16] } 3495:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
5060 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBLA_MM,
5061 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5062 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5063 : GIR_EraseFromParent, /*InsnID*/0,
5064 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5065 : // GIR_Coverage, 1224,
5066 : GIR_Done,
5067 : // Label 420: @10499
5068 : GIM_Try, /*On fail goto*//*Label 421*/ 10539, // Rule ID 1225 //
5069 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5070 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbr,
5071 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5072 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5073 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5074 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5075 : // (intrinsic_wo_chain:{ *:[v2i16] } 3496:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
5076 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBR_MM,
5077 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5078 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5079 : GIR_EraseFromParent, /*InsnID*/0,
5080 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5081 : // GIR_Coverage, 1225,
5082 : GIR_Done,
5083 : // Label 421: @10539
5084 : GIM_Try, /*On fail goto*//*Label 422*/ 10579, // Rule ID 1226 //
5085 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5086 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbra,
5087 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5088 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5089 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5090 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5091 : // (intrinsic_wo_chain:{ *:[v2i16] } 3497:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
5092 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBRA_MM,
5093 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5094 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5095 : GIR_EraseFromParent, /*InsnID*/0,
5096 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5097 : // GIR_Coverage, 1226,
5098 : GIR_Done,
5099 : // Label 422: @10579
5100 : GIM_Try, /*On fail goto*//*Label 423*/ 10619, // Rule ID 1252 //
5101 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5102 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_raddu_w_qb,
5103 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
5104 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5105 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
5106 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5107 : // (intrinsic_wo_chain:{ *:[i32] } 3506:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (RADDU_W_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
5108 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RADDU_W_QB_MM,
5109 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5110 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5111 : GIR_EraseFromParent, /*InsnID*/0,
5112 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5113 : // GIR_Coverage, 1252,
5114 : GIR_Done,
5115 : // Label 423: @10619
5116 : GIM_Try, /*On fail goto*//*Label 424*/ 10659, // Rule ID 1256 //
5117 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5118 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
5119 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5120 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5121 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5122 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
5123 : // (intrinsic_wo_chain:{ *:[v2i16] } 3508:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (REPLV_PH_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs)
5124 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_PH_MM,
5125 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5126 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5127 : GIR_EraseFromParent, /*InsnID*/0,
5128 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5129 : // GIR_Coverage, 1256,
5130 : GIR_Done,
5131 : // Label 424: @10659
5132 : GIM_Try, /*On fail goto*//*Label 425*/ 10699, // Rule ID 1257 //
5133 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5134 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
5135 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
5136 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5137 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5138 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
5139 : // (intrinsic_wo_chain:{ *:[v4i8] } 3509:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (REPLV_QB_MM:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rs)
5140 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_QB_MM,
5141 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5142 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5143 : GIR_EraseFromParent, /*InsnID*/0,
5144 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5145 : // GIR_Coverage, 1257,
5146 : GIR_Done,
5147 : // Label 425: @10699
5148 : GIM_Try, /*On fail goto*//*Label 426*/ 10739, // Rule ID 1267 //
5149 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5150 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_bitrev,
5151 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
5152 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5153 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
5154 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
5155 : // (intrinsic_wo_chain:{ *:[i32] } 3064:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (BITREV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
5156 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BITREV_MM,
5157 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5158 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5159 : GIR_EraseFromParent, /*InsnID*/0,
5160 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5161 : // GIR_Coverage, 1267,
5162 : GIR_Done,
5163 : // Label 426: @10739
5164 : GIM_Reject,
5165 : // Label 372: @10740
5166 : GIM_Try, /*On fail goto*//*Label 427*/ 22008,
5167 : GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
5168 : GIM_Try, /*On fail goto*//*Label 428*/ 10804, // Rule ID 357 //
5169 : GIM_CheckFeatures, GIFBS_HasDSP,
5170 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph,
5171 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5172 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
5173 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5174 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5175 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5176 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5177 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5178 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
5179 : // MIs[1] Operand 1
5180 : // No operand predicates
5181 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5182 : // (intrinsic_wo_chain:{ *:[v2i16] } 3528:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$rs_sa) => (SHRA_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa)
5183 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_PH,
5184 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5185 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
5186 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
5187 : GIR_EraseFromParent, /*InsnID*/0,
5188 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5189 : // GIR_Coverage, 357,
5190 : GIR_Done,
5191 : // Label 428: @10804
5192 : GIM_Try, /*On fail goto*//*Label 429*/ 10863, // Rule ID 361 //
5193 : GIM_CheckFeatures, GIFBS_HasDSP,
5194 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w,
5195 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
5196 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5197 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5198 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
5199 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
5200 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5201 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5202 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
5203 : // MIs[1] Operand 1
5204 : // No operand predicates
5205 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5206 : // (intrinsic_wo_chain:{ *:[i32] } 3530:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$rs_sa) => (SHRA_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa)
5207 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_W,
5208 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5209 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
5210 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
5211 : GIR_EraseFromParent, /*InsnID*/0,
5212 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5213 : // GIR_Coverage, 361,
5214 : GIR_Done,
5215 : // Label 429: @10863
5216 : GIM_Try, /*On fail goto*//*Label 430*/ 10922, // Rule ID 452 //
5217 : GIM_CheckFeatures, GIFBS_HasDSPR2,
5218 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb,
5219 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
5220 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5221 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5222 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5223 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5224 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5225 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5226 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
5227 : // MIs[1] Operand 1
5228 : // No operand predicates
5229 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5230 : // (intrinsic_wo_chain:{ *:[v4i8] } 3529:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$rs_sa) => (SHRA_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] }):$rs_sa)
5231 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_QB,
5232 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5233 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
5234 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
5235 : GIR_EraseFromParent, /*InsnID*/0,
5236 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5237 : // GIR_Coverage, 452,
5238 : GIR_Done,
5239 : // Label 430: @10922
5240 : GIM_Try, /*On fail goto*//*Label 431*/ 10981, // Rule ID 906 //
5241 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5242 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_b,
5243 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
5244 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
5245 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5246 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
5247 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
5248 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5249 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5250 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
5251 : // MIs[1] Operand 1
5252 : // No operand predicates
5253 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5254 : // (intrinsic_wo_chain:{ *:[v16i8] } 3510:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$m) => (SAT_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] }):$m)
5255 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_B,
5256 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5257 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5258 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5259 : GIR_EraseFromParent, /*InsnID*/0,
5260 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5261 : // GIR_Coverage, 906,
5262 : GIR_Done,
5263 : // Label 431: @10981
5264 : GIM_Try, /*On fail goto*//*Label 432*/ 11040, // Rule ID 907 //
5265 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5266 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_h,
5267 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
5268 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
5269 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5270 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
5271 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
5272 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5273 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5274 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
5275 : // MIs[1] Operand 1
5276 : // No operand predicates
5277 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5278 : // (intrinsic_wo_chain:{ *:[v8i16] } 3512:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$m) => (SAT_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] }):$m)
5279 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_H,
5280 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5281 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5282 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5283 : GIR_EraseFromParent, /*InsnID*/0,
5284 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5285 : // GIR_Coverage, 907,
5286 : GIR_Done,
5287 : // Label 432: @11040
5288 : GIM_Try, /*On fail goto*//*Label 433*/ 11099, // Rule ID 908 //
5289 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5290 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_w,
5291 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5292 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5293 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5294 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5295 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5296 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5297 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5298 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
5299 : // MIs[1] Operand 1
5300 : // No operand predicates
5301 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5302 : // (intrinsic_wo_chain:{ *:[v4i32] } 3513:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$m) => (SAT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] }):$m)
5303 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_W,
5304 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5305 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5306 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5307 : GIR_EraseFromParent, /*InsnID*/0,
5308 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5309 : // GIR_Coverage, 908,
5310 : GIR_Done,
5311 : // Label 433: @11099
5312 : GIM_Try, /*On fail goto*//*Label 434*/ 11158, // Rule ID 909 //
5313 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5314 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_d,
5315 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5316 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
5317 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5318 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5319 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
5320 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5321 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5322 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6,
5323 : // MIs[1] Operand 1
5324 : // No operand predicates
5325 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5326 : // (intrinsic_wo_chain:{ *:[v2i64] } 3511:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$m) => (SAT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] }):$m)
5327 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_D,
5328 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5329 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5330 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5331 : GIR_EraseFromParent, /*InsnID*/0,
5332 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5333 : // GIR_Coverage, 909,
5334 : GIR_Done,
5335 : // Label 434: @11158
5336 : GIM_Try, /*On fail goto*//*Label 435*/ 11217, // Rule ID 910 //
5337 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5338 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_b,
5339 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
5340 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
5341 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5342 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
5343 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
5344 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5345 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5346 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
5347 : // MIs[1] Operand 1
5348 : // No operand predicates
5349 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5350 : // (intrinsic_wo_chain:{ *:[v16i8] } 3514:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$m) => (SAT_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] }):$m)
5351 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_B,
5352 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5353 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5354 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5355 : GIR_EraseFromParent, /*InsnID*/0,
5356 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5357 : // GIR_Coverage, 910,
5358 : GIR_Done,
5359 : // Label 435: @11217
5360 : GIM_Try, /*On fail goto*//*Label 436*/ 11276, // Rule ID 911 //
5361 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5362 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_h,
5363 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
5364 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
5365 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5366 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
5367 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
5368 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5369 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5370 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
5371 : // MIs[1] Operand 1
5372 : // No operand predicates
5373 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5374 : // (intrinsic_wo_chain:{ *:[v8i16] } 3516:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$m) => (SAT_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] }):$m)
5375 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_H,
5376 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5377 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5378 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5379 : GIR_EraseFromParent, /*InsnID*/0,
5380 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5381 : // GIR_Coverage, 911,
5382 : GIR_Done,
5383 : // Label 436: @11276
5384 : GIM_Try, /*On fail goto*//*Label 437*/ 11335, // Rule ID 912 //
5385 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5386 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_w,
5387 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5388 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5389 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5390 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5391 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5392 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5393 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5394 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
5395 : // MIs[1] Operand 1
5396 : // No operand predicates
5397 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5398 : // (intrinsic_wo_chain:{ *:[v4i32] } 3517:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$m) => (SAT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] }):$m)
5399 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_W,
5400 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5401 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5402 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5403 : GIR_EraseFromParent, /*InsnID*/0,
5404 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5405 : // GIR_Coverage, 912,
5406 : GIR_Done,
5407 : // Label 437: @11335
5408 : GIM_Try, /*On fail goto*//*Label 438*/ 11394, // Rule ID 913 //
5409 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5410 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_d,
5411 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5412 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
5413 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5414 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5415 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
5416 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5417 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5418 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6,
5419 : // MIs[1] Operand 1
5420 : // No operand predicates
5421 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5422 : // (intrinsic_wo_chain:{ *:[v2i64] } 3515:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$m) => (SAT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] }):$m)
5423 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_D,
5424 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5425 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5426 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5427 : GIR_EraseFromParent, /*InsnID*/0,
5428 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5429 : // GIR_Coverage, 913,
5430 : GIR_Done,
5431 : // Label 438: @11394
5432 : GIM_Try, /*On fail goto*//*Label 439*/ 11453, // Rule ID 953 //
5433 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5434 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_b,
5435 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
5436 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
5437 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5438 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
5439 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
5440 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5441 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5442 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
5443 : // MIs[1] Operand 1
5444 : // No operand predicates
5445 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5446 : // (intrinsic_wo_chain:{ *:[v16i8] } 3569:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$m) => (SRARI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] }):$m)
5447 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_B,
5448 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5449 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5450 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5451 : GIR_EraseFromParent, /*InsnID*/0,
5452 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5453 : // GIR_Coverage, 953,
5454 : GIR_Done,
5455 : // Label 439: @11453
5456 : GIM_Try, /*On fail goto*//*Label 440*/ 11512, // Rule ID 954 //
5457 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5458 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_h,
5459 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
5460 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
5461 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5462 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
5463 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
5464 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5465 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5466 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
5467 : // MIs[1] Operand 1
5468 : // No operand predicates
5469 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5470 : // (intrinsic_wo_chain:{ *:[v8i16] } 3571:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$m) => (SRARI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] }):$m)
5471 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_H,
5472 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5473 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5474 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5475 : GIR_EraseFromParent, /*InsnID*/0,
5476 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5477 : // GIR_Coverage, 954,
5478 : GIR_Done,
5479 : // Label 440: @11512
5480 : GIM_Try, /*On fail goto*//*Label 441*/ 11571, // Rule ID 955 //
5481 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5482 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_w,
5483 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5484 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5485 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5486 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5487 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5488 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5489 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5490 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
5491 : // MIs[1] Operand 1
5492 : // No operand predicates
5493 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5494 : // (intrinsic_wo_chain:{ *:[v4i32] } 3572:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$m) => (SRARI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] }):$m)
5495 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_W,
5496 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5497 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5498 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5499 : GIR_EraseFromParent, /*InsnID*/0,
5500 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5501 : // GIR_Coverage, 955,
5502 : GIR_Done,
5503 : // Label 441: @11571
5504 : GIM_Try, /*On fail goto*//*Label 442*/ 11630, // Rule ID 956 //
5505 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5506 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_d,
5507 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5508 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
5509 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5510 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5511 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
5512 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5513 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5514 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6,
5515 : // MIs[1] Operand 1
5516 : // No operand predicates
5517 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5518 : // (intrinsic_wo_chain:{ *:[v2i64] } 3570:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$m) => (SRARI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] }):$m)
5519 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_D,
5520 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5521 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5522 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5523 : GIR_EraseFromParent, /*InsnID*/0,
5524 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5525 : // GIR_Coverage, 956,
5526 : GIR_Done,
5527 : // Label 442: @11630
5528 : GIM_Try, /*On fail goto*//*Label 443*/ 11689, // Rule ID 969 //
5529 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5530 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_b,
5531 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
5532 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
5533 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5534 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
5535 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
5536 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5537 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5538 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
5539 : // MIs[1] Operand 1
5540 : // No operand predicates
5541 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5542 : // (intrinsic_wo_chain:{ *:[v16i8] } 3585:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$m) => (SRLRI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] }):$m)
5543 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_B,
5544 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5545 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5546 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5547 : GIR_EraseFromParent, /*InsnID*/0,
5548 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5549 : // GIR_Coverage, 969,
5550 : GIR_Done,
5551 : // Label 443: @11689
5552 : GIM_Try, /*On fail goto*//*Label 444*/ 11748, // Rule ID 970 //
5553 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5554 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_h,
5555 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
5556 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
5557 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5558 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
5559 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
5560 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5561 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5562 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
5563 : // MIs[1] Operand 1
5564 : // No operand predicates
5565 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5566 : // (intrinsic_wo_chain:{ *:[v8i16] } 3587:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$m) => (SRLRI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] }):$m)
5567 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_H,
5568 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5569 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5570 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5571 : GIR_EraseFromParent, /*InsnID*/0,
5572 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5573 : // GIR_Coverage, 970,
5574 : GIR_Done,
5575 : // Label 444: @11748
5576 : GIM_Try, /*On fail goto*//*Label 445*/ 11807, // Rule ID 971 //
5577 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5578 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_w,
5579 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
5580 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5581 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5582 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
5583 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
5584 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5585 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5586 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
5587 : // MIs[1] Operand 1
5588 : // No operand predicates
5589 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5590 : // (intrinsic_wo_chain:{ *:[v4i32] } 3588:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$m) => (SRLRI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] }):$m)
5591 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_W,
5592 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5593 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5594 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5595 : GIR_EraseFromParent, /*InsnID*/0,
5596 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5597 : // GIR_Coverage, 971,
5598 : GIR_Done,
5599 : // Label 445: @11807
5600 : GIM_Try, /*On fail goto*//*Label 446*/ 11866, // Rule ID 972 //
5601 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
5602 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_d,
5603 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
5604 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
5605 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5606 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
5607 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
5608 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5609 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5610 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6,
5611 : // MIs[1] Operand 1
5612 : // No operand predicates
5613 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5614 : // (intrinsic_wo_chain:{ *:[v2i64] } 3586:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$m) => (SRLRI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] }):$m)
5615 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_D,
5616 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
5617 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
5618 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
5619 : GIR_EraseFromParent, /*InsnID*/0,
5620 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5621 : // GIR_Coverage, 972,
5622 : GIR_Done,
5623 : // Label 446: @11866
5624 : GIM_Try, /*On fail goto*//*Label 447*/ 11925, // Rule ID 1211 //
5625 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5626 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph,
5627 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5628 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
5629 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5630 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5631 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5632 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5633 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5634 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
5635 : // MIs[1] Operand 1
5636 : // No operand predicates
5637 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5638 : // (intrinsic_wo_chain:{ *:[v2i16] } 3528:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$sa) => (SHRA_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa)
5639 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_PH_MM,
5640 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5641 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5642 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
5643 : GIR_EraseFromParent, /*InsnID*/0,
5644 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5645 : // GIR_Coverage, 1211,
5646 : GIR_Done,
5647 : // Label 447: @11925
5648 : GIM_Try, /*On fail goto*//*Label 448*/ 11984, // Rule ID 1215 //
5649 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
5650 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w,
5651 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
5652 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5653 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5654 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
5655 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
5656 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5657 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5658 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
5659 : // MIs[1] Operand 1
5660 : // No operand predicates
5661 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5662 : // (intrinsic_wo_chain:{ *:[i32] } 3530:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (SHRA_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa)
5663 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_W_MM,
5664 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5665 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5666 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
5667 : GIR_EraseFromParent, /*InsnID*/0,
5668 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5669 : // GIR_Coverage, 1215,
5670 : GIR_Done,
5671 : // Label 448: @11984
5672 : GIM_Try, /*On fail goto*//*Label 449*/ 12043, // Rule ID 1290 //
5673 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
5674 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb,
5675 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
5676 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5677 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5678 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5679 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5680 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5681 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5682 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
5683 : // MIs[1] Operand 1
5684 : // No operand predicates
5685 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5686 : // (intrinsic_wo_chain:{ *:[v4i8] } 3529:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$sa) => (SHRA_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] }):$sa)
5687 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_QB_MMR2,
5688 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
5689 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5690 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
5691 : GIR_EraseFromParent, /*InsnID*/0,
5692 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5693 : // GIR_Coverage, 1290,
5694 : GIR_Done,
5695 : // Label 449: @12043
5696 : GIM_Try, /*On fail goto*//*Label 450*/ 12098, // Rule ID 1861 //
5697 : GIM_CheckFeatures, GIFBS_HasDSP,
5698 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_ph,
5699 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5700 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
5701 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5702 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5703 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5704 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5705 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
5706 : // MIs[1] Operand 1
5707 : // No operand predicates
5708 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5709 : // (intrinsic_wo_chain:{ *:[v2i16] } 3526:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHRA_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
5710 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_PH,
5711 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5712 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
5713 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
5714 : GIR_EraseFromParent, /*InsnID*/0,
5715 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5716 : // GIR_Coverage, 1861,
5717 : GIR_Done,
5718 : // Label 450: @12098
5719 : GIM_Try, /*On fail goto*//*Label 451*/ 12153, // Rule ID 1862 //
5720 : GIM_CheckFeatures, GIFBS_HasDSPR2,
5721 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_ph,
5722 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5723 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
5724 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5725 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5726 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5727 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5728 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
5729 : // MIs[1] Operand 1
5730 : // No operand predicates
5731 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5732 : // (intrinsic_wo_chain:{ *:[v2i16] } 3531:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHRL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
5733 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRL_PH,
5734 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5735 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
5736 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
5737 : GIR_EraseFromParent, /*InsnID*/0,
5738 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5739 : // GIR_Coverage, 1862,
5740 : GIR_Done,
5741 : // Label 451: @12153
5742 : GIM_Try, /*On fail goto*//*Label 452*/ 12208, // Rule ID 1867 //
5743 : GIM_CheckFeatures, GIFBS_HasDSPR2,
5744 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_qb,
5745 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
5746 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5747 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5748 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5749 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5750 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5751 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
5752 : // MIs[1] Operand 1
5753 : // No operand predicates
5754 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5755 : // (intrinsic_wo_chain:{ *:[v4i8] } 3527:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHRA_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
5756 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_QB,
5757 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5758 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
5759 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
5760 : GIR_EraseFromParent, /*InsnID*/0,
5761 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5762 : // GIR_Coverage, 1867,
5763 : GIR_Done,
5764 : // Label 452: @12208
5765 : GIM_Try, /*On fail goto*//*Label 453*/ 12263, // Rule ID 1868 //
5766 : GIM_CheckFeatures, GIFBS_HasDSP,
5767 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_qb,
5768 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
5769 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5770 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5771 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5772 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
5773 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
5774 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
5775 : // MIs[1] Operand 1
5776 : // No operand predicates
5777 : GIM_CheckIsSafeToFold, /*InsnID*/1,
5778 : // (intrinsic_wo_chain:{ *:[v4i8] } 3532:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHRL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
5779 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRL_QB,
5780 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5781 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
5782 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
5783 : GIR_EraseFromParent, /*InsnID*/0,
5784 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5785 : // GIR_Coverage, 1868,
5786 : GIR_Done,
5787 : // Label 453: @12263
5788 : GIM_Try, /*On fail goto*//*Label 454*/ 12315, // Rule ID 327 //
5789 : GIM_CheckFeatures, GIFBS_HasDSP,
5790 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_s_qb,
5791 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
5792 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5793 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
5794 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5795 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5796 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
5797 : // (intrinsic_wo_chain:{ *:[v4i8] } 3000:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
5798 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_QB,
5799 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5800 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5801 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
5802 : GIR_EraseFromParent, /*InsnID*/0,
5803 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5804 : // GIR_Coverage, 327,
5805 : GIR_Done,
5806 : // Label 454: @12315
5807 : GIM_Try, /*On fail goto*//*Label 455*/ 12367, // Rule ID 328 //
5808 : GIM_CheckFeatures, GIFBS_HasDSP,
5809 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_s_qb,
5810 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
5811 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5812 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
5813 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5814 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5815 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
5816 : // (intrinsic_wo_chain:{ *:[v4i8] } 3619:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
5817 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_QB,
5818 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5819 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5820 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
5821 : GIR_EraseFromParent, /*InsnID*/0,
5822 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5823 : // GIR_Coverage, 328,
5824 : GIR_Done,
5825 : // Label 455: @12367
5826 : GIM_Try, /*On fail goto*//*Label 456*/ 12419, // Rule ID 329 //
5827 : GIM_CheckFeatures, GIFBS_HasDSP,
5828 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_s_ph,
5829 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5830 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
5831 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
5832 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5833 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5834 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
5835 : // (intrinsic_wo_chain:{ *:[v2i16] } 2978:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
5836 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_PH,
5837 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5838 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5839 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
5840 : GIR_EraseFromParent, /*InsnID*/0,
5841 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5842 : // GIR_Coverage, 329,
5843 : GIR_Done,
5844 : // Label 456: @12419
5845 : GIM_Try, /*On fail goto*//*Label 457*/ 12471, // Rule ID 330 //
5846 : GIM_CheckFeatures, GIFBS_HasDSP,
5847 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_s_ph,
5848 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5849 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
5850 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
5851 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5852 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5853 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
5854 : // (intrinsic_wo_chain:{ *:[v2i16] } 3594:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
5855 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_PH,
5856 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5857 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5858 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
5859 : GIR_EraseFromParent, /*InsnID*/0,
5860 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5861 : // GIR_Coverage, 330,
5862 : GIR_Done,
5863 : // Label 457: @12471
5864 : GIM_Try, /*On fail goto*//*Label 458*/ 12523, // Rule ID 333 //
5865 : GIM_CheckFeatures, GIFBS_HasDSP,
5866 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_modsub,
5867 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
5868 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5869 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5870 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
5871 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
5872 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
5873 : // (intrinsic_wo_chain:{ *:[i32] } 3426:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODSUB:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
5874 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MODSUB,
5875 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5876 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5877 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
5878 : GIR_EraseFromParent, /*InsnID*/0,
5879 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5880 : // GIR_Coverage, 333,
5881 : GIR_Done,
5882 : // Label 458: @12523
5883 : GIM_Try, /*On fail goto*//*Label 459*/ 12575, // Rule ID 337 //
5884 : GIM_CheckFeatures, GIFBS_HasDSP,
5885 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_qb_ph,
5886 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
5887 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
5888 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
5889 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5890 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5891 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
5892 : // (intrinsic_wo_chain:{ *:[v4i8] } 3502:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQ_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
5893 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_QB_PH,
5894 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5895 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5896 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
5897 : GIR_EraseFromParent, /*InsnID*/0,
5898 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5899 : // GIR_Coverage, 337,
5900 : GIR_Done,
5901 : // Label 459: @12575
5902 : GIM_Try, /*On fail goto*//*Label 460*/ 12627, // Rule ID 338 //
5903 : GIM_CheckFeatures, GIFBS_HasDSP,
5904 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_ph_w,
5905 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5906 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5907 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5908 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5909 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
5910 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
5911 : // (intrinsic_wo_chain:{ *:[v2i16] } 3501:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
5912 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_PH_W,
5913 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5914 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
5915 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
5916 : GIR_EraseFromParent, /*InsnID*/0,
5917 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5918 : // GIR_Coverage, 338,
5919 : GIR_Done,
5920 : // Label 460: @12627
5921 : GIM_Try, /*On fail goto*//*Label 461*/ 12679, // Rule ID 352 //
5922 : GIM_CheckFeatures, GIFBS_HasDSP,
5923 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_qb,
5924 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
5925 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
5926 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5927 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5928 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5929 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
5930 : // (intrinsic_wo_chain:{ *:[v4i8] } 3532:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
5931 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_QB,
5932 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5933 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
5934 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
5935 : GIR_EraseFromParent, /*InsnID*/0,
5936 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5937 : // GIR_Coverage, 352,
5938 : GIR_Done,
5939 : // Label 461: @12679
5940 : GIM_Try, /*On fail goto*//*Label 462*/ 12731, // Rule ID 356 //
5941 : GIM_CheckFeatures, GIFBS_HasDSP,
5942 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_ph,
5943 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5944 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
5945 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5946 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5947 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5948 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
5949 : // (intrinsic_wo_chain:{ *:[v2i16] } 3526:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
5950 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_PH,
5951 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5952 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
5953 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
5954 : GIR_EraseFromParent, /*InsnID*/0,
5955 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5956 : // GIR_Coverage, 356,
5957 : GIR_Done,
5958 : // Label 462: @12731
5959 : GIM_Try, /*On fail goto*//*Label 463*/ 12783, // Rule ID 358 //
5960 : GIM_CheckFeatures, GIFBS_HasDSP,
5961 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph,
5962 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
5963 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
5964 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5965 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
5966 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
5967 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
5968 : // (intrinsic_wo_chain:{ *:[v2i16] } 3528:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
5969 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_PH,
5970 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5971 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
5972 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
5973 : GIR_EraseFromParent, /*InsnID*/0,
5974 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5975 : // GIR_Coverage, 358,
5976 : GIR_Done,
5977 : // Label 463: @12783
5978 : GIM_Try, /*On fail goto*//*Label 464*/ 12835, // Rule ID 362 //
5979 : GIM_CheckFeatures, GIFBS_HasDSP,
5980 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w,
5981 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
5982 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5983 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
5984 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
5985 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
5986 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
5987 : // (intrinsic_wo_chain:{ *:[i32] } 3530:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
5988 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_W,
5989 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
5990 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
5991 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
5992 : GIR_EraseFromParent, /*InsnID*/0,
5993 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5994 : // GIR_Coverage, 362,
5995 : GIR_Done,
5996 : // Label 464: @12835
5997 : GIM_Try, /*On fail goto*//*Label 465*/ 12887, // Rule ID 399 //
5998 : GIM_CheckFeatures, GIFBS_HasDSP,
5999 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_packrl_ph,
6000 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6001 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6002 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
6003 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6004 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6005 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6006 : // (intrinsic_wo_chain:{ *:[v2i16] } 3473:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PACKRL_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
6007 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PACKRL_PH,
6008 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6009 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6010 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6011 : GIR_EraseFromParent, /*InsnID*/0,
6012 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6013 : // GIR_Coverage, 399,
6014 : GIR_Done,
6015 : // Label 465: @12887
6016 : GIM_Try, /*On fail goto*//*Label 466*/ 12939, // Rule ID 423 //
6017 : GIM_CheckFeatures, GIFBS_HasDSPR2,
6018 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adduh_qb,
6019 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6020 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6021 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
6022 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6023 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6024 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6025 : // (intrinsic_wo_chain:{ *:[v4i8] } 3001:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
6026 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_QB,
6027 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6028 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6029 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6030 : GIR_EraseFromParent, /*InsnID*/0,
6031 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6032 : // GIR_Coverage, 423,
6033 : GIR_Done,
6034 : // Label 466: @12939
6035 : GIM_Try, /*On fail goto*//*Label 467*/ 12991, // Rule ID 424 //
6036 : GIM_CheckFeatures, GIFBS_HasDSPR2,
6037 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adduh_r_qb,
6038 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6039 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6040 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
6041 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6042 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6043 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6044 : // (intrinsic_wo_chain:{ *:[v4i8] } 3002:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
6045 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_R_QB,
6046 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6047 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6048 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6049 : GIR_EraseFromParent, /*InsnID*/0,
6050 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6051 : // GIR_Coverage, 424,
6052 : GIR_Done,
6053 : // Label 467: @12991
6054 : GIM_Try, /*On fail goto*//*Label 468*/ 13043, // Rule ID 425 //
6055 : GIM_CheckFeatures, GIFBS_HasDSPR2,
6056 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subuh_qb,
6057 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6058 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6059 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
6060 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6061 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6062 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6063 : // (intrinsic_wo_chain:{ *:[v4i8] } 3620:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
6064 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_QB,
6065 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6066 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6067 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6068 : GIR_EraseFromParent, /*InsnID*/0,
6069 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6070 : // GIR_Coverage, 425,
6071 : GIR_Done,
6072 : // Label 468: @13043
6073 : GIM_Try, /*On fail goto*//*Label 469*/ 13095, // Rule ID 426 //
6074 : GIM_CheckFeatures, GIFBS_HasDSPR2,
6075 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subuh_r_qb,
6076 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6077 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6078 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
6079 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6080 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6081 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6082 : // (intrinsic_wo_chain:{ *:[v4i8] } 3621:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
6083 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_R_QB,
6084 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6085 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6086 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6087 : GIR_EraseFromParent, /*InsnID*/0,
6088 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6089 : // GIR_Coverage, 426,
6090 : GIR_Done,
6091 : // Label 469: @13095
6092 : GIM_Try, /*On fail goto*//*Label 470*/ 13147, // Rule ID 427 //
6093 : GIM_CheckFeatures, GIFBS_HasDSPR2,
6094 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_ph,
6095 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6096 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6097 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
6098 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6099 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6100 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6101 : // (intrinsic_wo_chain:{ *:[v2i16] } 2980:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
6102 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_PH,
6103 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6104 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6105 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6106 : GIR_EraseFromParent, /*InsnID*/0,
6107 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6108 : // GIR_Coverage, 427,
6109 : GIR_Done,
6110 : // Label 470: @13147
6111 : GIM_Try, /*On fail goto*//*Label 471*/ 13199, // Rule ID 428 //
6112 : GIM_CheckFeatures, GIFBS_HasDSPR2,
6113 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_ph,
6114 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6115 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6116 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
6117 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6118 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6119 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6120 : // (intrinsic_wo_chain:{ *:[v2i16] } 2981:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
6121 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_PH,
6122 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6123 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6124 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6125 : GIR_EraseFromParent, /*InsnID*/0,
6126 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6127 : // GIR_Coverage, 428,
6128 : GIR_Done,
6129 : // Label 471: @13199
6130 : GIM_Try, /*On fail goto*//*Label 472*/ 13251, // Rule ID 429 //
6131 : GIM_CheckFeatures, GIFBS_HasDSPR2,
6132 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_ph,
6133 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6134 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6135 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
6136 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6137 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6138 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6139 : // (intrinsic_wo_chain:{ *:[v2i16] } 3596:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
6140 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_PH,
6141 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6142 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6143 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6144 : GIR_EraseFromParent, /*InsnID*/0,
6145 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6146 : // GIR_Coverage, 429,
6147 : GIR_Done,
6148 : // Label 472: @13251
6149 : GIM_Try, /*On fail goto*//*Label 473*/ 13303, // Rule ID 430 //
6150 : GIM_CheckFeatures, GIFBS_HasDSPR2,
6151 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_r_ph,
6152 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6153 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6154 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
6155 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6156 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6157 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
6158 : // (intrinsic_wo_chain:{ *:[v2i16] } 3597:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
6159 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_PH,
6160 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6161 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6162 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6163 : GIR_EraseFromParent, /*InsnID*/0,
6164 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6165 : // GIR_Coverage, 430,
6166 : GIR_Done,
6167 : // Label 473: @13303
6168 : GIM_Try, /*On fail goto*//*Label 474*/ 13355, // Rule ID 431 //
6169 : GIM_CheckFeatures, GIFBS_HasDSPR2,
6170 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_w,
6171 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
6172 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
6173 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6174 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
6175 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
6176 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6177 : // (intrinsic_wo_chain:{ *:[i32] } 2983:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
6178 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_W,
6179 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6180 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6181 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6182 : GIR_EraseFromParent, /*InsnID*/0,
6183 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6184 : // GIR_Coverage, 431,
6185 : GIR_Done,
6186 : // Label 474: @13355
6187 : GIM_Try, /*On fail goto*//*Label 475*/ 13407, // Rule ID 432 //
6188 : GIM_CheckFeatures, GIFBS_HasDSPR2,
6189 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_w,
6190 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
6191 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
6192 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6193 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
6194 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
6195 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6196 : // (intrinsic_wo_chain:{ *:[i32] } 2982:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
6197 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_W,
6198 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6199 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6200 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6201 : GIR_EraseFromParent, /*InsnID*/0,
6202 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6203 : // GIR_Coverage, 432,
6204 : GIR_Done,
6205 : // Label 475: @13407
6206 : GIM_Try, /*On fail goto*//*Label 476*/ 13459, // Rule ID 433 //
6207 : GIM_CheckFeatures, GIFBS_HasDSPR2,
6208 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_w,
6209 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
6210 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
6211 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6212 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
6213 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
6214 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6215 : // (intrinsic_wo_chain:{ *:[i32] } 3599:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
6216 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_W,
6217 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6218 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6219 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6220 : GIR_EraseFromParent, /*InsnID*/0,
6221 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6222 : // GIR_Coverage, 433,
6223 : GIR_Done,
6224 : // Label 476: @13459
6225 : GIM_Try, /*On fail goto*//*Label 477*/ 13511, // Rule ID 434 //
6226 : GIM_CheckFeatures, GIFBS_HasDSPR2,
6227 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_r_w,
6228 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
6229 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
6230 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6231 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
6232 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
6233 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6234 : // (intrinsic_wo_chain:{ *:[i32] } 3598:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
6235 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_W,
6236 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6237 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
6238 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
6239 : GIR_EraseFromParent, /*InsnID*/0,
6240 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6241 : // GIR_Coverage, 434,
6242 : GIR_Done,
6243 : // Label 477: @13511
6244 : GIM_Try, /*On fail goto*//*Label 478*/ 13563, // Rule ID 451 //
6245 : GIM_CheckFeatures, GIFBS_HasDSPR2,
6246 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_qb,
6247 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6248 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6249 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6250 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6251 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6252 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6253 : // (intrinsic_wo_chain:{ *:[v4i8] } 3527:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
6254 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_QB,
6255 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6256 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
6257 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
6258 : GIR_EraseFromParent, /*InsnID*/0,
6259 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6260 : // GIR_Coverage, 451,
6261 : GIR_Done,
6262 : // Label 478: @13563
6263 : GIM_Try, /*On fail goto*//*Label 479*/ 13615, // Rule ID 453 //
6264 : GIM_CheckFeatures, GIFBS_HasDSPR2,
6265 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb,
6266 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
6267 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
6268 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6269 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6270 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6271 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6272 : // (intrinsic_wo_chain:{ *:[v4i8] } 3529:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
6273 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_QB,
6274 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6275 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
6276 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
6277 : GIR_EraseFromParent, /*InsnID*/0,
6278 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6279 : // GIR_Coverage, 453,
6280 : GIR_Done,
6281 : // Label 479: @13615
6282 : GIM_Try, /*On fail goto*//*Label 480*/ 13667, // Rule ID 454 //
6283 : GIM_CheckFeatures, GIFBS_HasDSPR2,
6284 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_ph,
6285 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
6286 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
6287 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
6288 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
6289 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
6290 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
6291 : // (intrinsic_wo_chain:{ *:[v2i16] } 3531:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
6292 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_PH,
6293 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
6294 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
6295 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
6296 : GIR_EraseFromParent, /*InsnID*/0,
6297 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6298 : // GIR_Coverage, 454,
6299 : GIR_Done,
6300 : // Label 480: @13667
6301 : GIM_Try, /*On fail goto*//*Label 481*/ 13719, // Rule ID 459 //
6302 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6303 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_b,
6304 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6305 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6306 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6307 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6308 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6309 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6310 : // (intrinsic_wo_chain:{ *:[v16i8] } 2973:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADD_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6311 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_B,
6312 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6313 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6314 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6315 : GIR_EraseFromParent, /*InsnID*/0,
6316 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6317 : // GIR_Coverage, 459,
6318 : GIR_Done,
6319 : // Label 481: @13719
6320 : GIM_Try, /*On fail goto*//*Label 482*/ 13771, // Rule ID 460 //
6321 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6322 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_h,
6323 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
6324 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6325 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
6326 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
6327 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
6328 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
6329 : // (intrinsic_wo_chain:{ *:[v8i16] } 2975:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADD_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
6330 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_H,
6331 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6332 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6333 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6334 : GIR_EraseFromParent, /*InsnID*/0,
6335 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6336 : // GIR_Coverage, 460,
6337 : GIR_Done,
6338 : // Label 482: @13771
6339 : GIM_Try, /*On fail goto*//*Label 483*/ 13823, // Rule ID 461 //
6340 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6341 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_w,
6342 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
6343 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6344 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
6345 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
6346 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
6347 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
6348 : // (intrinsic_wo_chain:{ *:[v4i32] } 2976:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADD_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
6349 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_W,
6350 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6351 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6352 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6353 : GIR_EraseFromParent, /*InsnID*/0,
6354 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6355 : // GIR_Coverage, 461,
6356 : GIR_Done,
6357 : // Label 483: @13823
6358 : GIM_Try, /*On fail goto*//*Label 484*/ 13875, // Rule ID 462 //
6359 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6360 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_d,
6361 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
6362 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
6363 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
6364 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
6365 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
6366 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
6367 : // (intrinsic_wo_chain:{ *:[v2i64] } 2974:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADD_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
6368 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_D,
6369 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6370 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6371 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6372 : GIR_EraseFromParent, /*InsnID*/0,
6373 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6374 : // GIR_Coverage, 462,
6375 : GIR_Done,
6376 : // Label 484: @13875
6377 : GIM_Try, /*On fail goto*//*Label 485*/ 13927, // Rule ID 463 //
6378 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6379 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_b,
6380 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6381 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6382 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6383 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6384 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6385 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6386 : // (intrinsic_wo_chain:{ *:[v16i8] } 2984:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6387 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_B,
6388 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6389 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6390 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6391 : GIR_EraseFromParent, /*InsnID*/0,
6392 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6393 : // GIR_Coverage, 463,
6394 : GIR_Done,
6395 : // Label 485: @13927
6396 : GIM_Try, /*On fail goto*//*Label 486*/ 13979, // Rule ID 464 //
6397 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6398 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_h,
6399 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
6400 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6401 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
6402 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
6403 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
6404 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
6405 : // (intrinsic_wo_chain:{ *:[v8i16] } 2986:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
6406 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_H,
6407 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6408 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6409 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6410 : GIR_EraseFromParent, /*InsnID*/0,
6411 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6412 : // GIR_Coverage, 464,
6413 : GIR_Done,
6414 : // Label 486: @13979
6415 : GIM_Try, /*On fail goto*//*Label 487*/ 14031, // Rule ID 465 //
6416 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6417 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_w,
6418 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
6419 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6420 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
6421 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
6422 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
6423 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
6424 : // (intrinsic_wo_chain:{ *:[v4i32] } 2987:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
6425 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_W,
6426 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6427 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6428 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6429 : GIR_EraseFromParent, /*InsnID*/0,
6430 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6431 : // GIR_Coverage, 465,
6432 : GIR_Done,
6433 : // Label 487: @14031
6434 : GIM_Try, /*On fail goto*//*Label 488*/ 14083, // Rule ID 466 //
6435 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6436 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_d,
6437 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
6438 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
6439 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
6440 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
6441 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
6442 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
6443 : // (intrinsic_wo_chain:{ *:[v2i64] } 2985:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
6444 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_D,
6445 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6446 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6447 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6448 : GIR_EraseFromParent, /*InsnID*/0,
6449 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6450 : // GIR_Coverage, 466,
6451 : GIR_Done,
6452 : // Label 488: @14083
6453 : GIM_Try, /*On fail goto*//*Label 489*/ 14135, // Rule ID 467 //
6454 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6455 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_b,
6456 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6457 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6458 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6459 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6460 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6461 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6462 : // (intrinsic_wo_chain:{ *:[v16i8] } 2988:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6463 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_B,
6464 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6465 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6466 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6467 : GIR_EraseFromParent, /*InsnID*/0,
6468 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6469 : // GIR_Coverage, 467,
6470 : GIR_Done,
6471 : // Label 489: @14135
6472 : GIM_Try, /*On fail goto*//*Label 490*/ 14187, // Rule ID 468 //
6473 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6474 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_h,
6475 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
6476 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6477 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
6478 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
6479 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
6480 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
6481 : // (intrinsic_wo_chain:{ *:[v8i16] } 2990:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
6482 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_H,
6483 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6484 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6485 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6486 : GIR_EraseFromParent, /*InsnID*/0,
6487 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6488 : // GIR_Coverage, 468,
6489 : GIR_Done,
6490 : // Label 490: @14187
6491 : GIM_Try, /*On fail goto*//*Label 491*/ 14239, // Rule ID 469 //
6492 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6493 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_w,
6494 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
6495 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6496 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
6497 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
6498 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
6499 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
6500 : // (intrinsic_wo_chain:{ *:[v4i32] } 2991:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
6501 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_W,
6502 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6503 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6504 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6505 : GIR_EraseFromParent, /*InsnID*/0,
6506 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6507 : // GIR_Coverage, 469,
6508 : GIR_Done,
6509 : // Label 491: @14239
6510 : GIM_Try, /*On fail goto*//*Label 492*/ 14291, // Rule ID 470 //
6511 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6512 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_d,
6513 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
6514 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
6515 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
6516 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
6517 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
6518 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
6519 : // (intrinsic_wo_chain:{ *:[v2i64] } 2989:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
6520 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_D,
6521 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6522 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6523 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6524 : GIR_EraseFromParent, /*InsnID*/0,
6525 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6526 : // GIR_Coverage, 470,
6527 : GIR_Done,
6528 : // Label 492: @14291
6529 : GIM_Try, /*On fail goto*//*Label 493*/ 14343, // Rule ID 471 //
6530 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6531 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_b,
6532 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6533 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6534 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6535 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6536 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6537 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6538 : // (intrinsic_wo_chain:{ *:[v16i8] } 2992:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6539 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_B,
6540 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6541 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6542 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6543 : GIR_EraseFromParent, /*InsnID*/0,
6544 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6545 : // GIR_Coverage, 471,
6546 : GIR_Done,
6547 : // Label 493: @14343
6548 : GIM_Try, /*On fail goto*//*Label 494*/ 14395, // Rule ID 472 //
6549 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6550 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_h,
6551 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
6552 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6553 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
6554 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
6555 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
6556 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
6557 : // (intrinsic_wo_chain:{ *:[v8i16] } 2994:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
6558 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_H,
6559 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6560 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6561 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6562 : GIR_EraseFromParent, /*InsnID*/0,
6563 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6564 : // GIR_Coverage, 472,
6565 : GIR_Done,
6566 : // Label 494: @14395
6567 : GIM_Try, /*On fail goto*//*Label 495*/ 14447, // Rule ID 473 //
6568 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6569 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_w,
6570 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
6571 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6572 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
6573 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
6574 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
6575 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
6576 : // (intrinsic_wo_chain:{ *:[v4i32] } 2995:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
6577 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_W,
6578 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6579 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6580 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6581 : GIR_EraseFromParent, /*InsnID*/0,
6582 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6583 : // GIR_Coverage, 473,
6584 : GIR_Done,
6585 : // Label 495: @14447
6586 : GIM_Try, /*On fail goto*//*Label 496*/ 14499, // Rule ID 474 //
6587 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6588 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_d,
6589 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
6590 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
6591 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
6592 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
6593 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
6594 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
6595 : // (intrinsic_wo_chain:{ *:[v2i64] } 2993:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
6596 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_D,
6597 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6598 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6599 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6600 : GIR_EraseFromParent, /*InsnID*/0,
6601 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6602 : // GIR_Coverage, 474,
6603 : GIR_Done,
6604 : // Label 496: @14499
6605 : GIM_Try, /*On fail goto*//*Label 497*/ 14551, // Rule ID 488 //
6606 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6607 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_b,
6608 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6609 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6610 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6611 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6612 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6613 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6614 : // (intrinsic_wo_chain:{ *:[v16i8] } 3015:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ASUB_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6615 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_B,
6616 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6617 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6618 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6619 : GIR_EraseFromParent, /*InsnID*/0,
6620 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6621 : // GIR_Coverage, 488,
6622 : GIR_Done,
6623 : // Label 497: @14551
6624 : GIM_Try, /*On fail goto*//*Label 498*/ 14603, // Rule ID 489 //
6625 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6626 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_h,
6627 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
6628 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6629 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
6630 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
6631 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
6632 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
6633 : // (intrinsic_wo_chain:{ *:[v8i16] } 3017:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ASUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
6634 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_H,
6635 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6636 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6637 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6638 : GIR_EraseFromParent, /*InsnID*/0,
6639 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6640 : // GIR_Coverage, 489,
6641 : GIR_Done,
6642 : // Label 498: @14603
6643 : GIM_Try, /*On fail goto*//*Label 499*/ 14655, // Rule ID 490 //
6644 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6645 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_w,
6646 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
6647 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6648 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
6649 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
6650 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
6651 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
6652 : // (intrinsic_wo_chain:{ *:[v4i32] } 3018:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ASUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
6653 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_W,
6654 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6655 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6656 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6657 : GIR_EraseFromParent, /*InsnID*/0,
6658 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6659 : // GIR_Coverage, 490,
6660 : GIR_Done,
6661 : // Label 499: @14655
6662 : GIM_Try, /*On fail goto*//*Label 500*/ 14707, // Rule ID 491 //
6663 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6664 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_d,
6665 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
6666 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
6667 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
6668 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
6669 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
6670 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
6671 : // (intrinsic_wo_chain:{ *:[v2i64] } 3016:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ASUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
6672 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_D,
6673 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6674 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6675 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6676 : GIR_EraseFromParent, /*InsnID*/0,
6677 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6678 : // GIR_Coverage, 491,
6679 : GIR_Done,
6680 : // Label 500: @14707
6681 : GIM_Try, /*On fail goto*//*Label 501*/ 14759, // Rule ID 492 //
6682 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6683 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_b,
6684 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6685 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6686 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6687 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6688 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6689 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6690 : // (intrinsic_wo_chain:{ *:[v16i8] } 3019:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ASUB_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6691 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_B,
6692 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6693 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6694 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6695 : GIR_EraseFromParent, /*InsnID*/0,
6696 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6697 : // GIR_Coverage, 492,
6698 : GIR_Done,
6699 : // Label 501: @14759
6700 : GIM_Try, /*On fail goto*//*Label 502*/ 14811, // Rule ID 493 //
6701 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6702 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_h,
6703 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
6704 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6705 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
6706 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
6707 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
6708 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
6709 : // (intrinsic_wo_chain:{ *:[v8i16] } 3021:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ASUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
6710 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_H,
6711 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6712 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6713 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6714 : GIR_EraseFromParent, /*InsnID*/0,
6715 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6716 : // GIR_Coverage, 493,
6717 : GIR_Done,
6718 : // Label 502: @14811
6719 : GIM_Try, /*On fail goto*//*Label 503*/ 14863, // Rule ID 494 //
6720 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6721 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_w,
6722 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
6723 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6724 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
6725 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
6726 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
6727 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
6728 : // (intrinsic_wo_chain:{ *:[v4i32] } 3022:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ASUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
6729 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_W,
6730 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6731 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6732 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6733 : GIR_EraseFromParent, /*InsnID*/0,
6734 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6735 : // GIR_Coverage, 494,
6736 : GIR_Done,
6737 : // Label 503: @14863
6738 : GIM_Try, /*On fail goto*//*Label 504*/ 14915, // Rule ID 495 //
6739 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6740 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_d,
6741 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
6742 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
6743 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
6744 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
6745 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
6746 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
6747 : // (intrinsic_wo_chain:{ *:[v2i64] } 3020:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ASUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
6748 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_D,
6749 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6750 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6751 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6752 : GIR_EraseFromParent, /*InsnID*/0,
6753 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6754 : // GIR_Coverage, 495,
6755 : GIR_Done,
6756 : // Label 504: @14915
6757 : GIM_Try, /*On fail goto*//*Label 505*/ 14967, // Rule ID 496 //
6758 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6759 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_b,
6760 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6761 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6762 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6763 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6764 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6765 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6766 : // (intrinsic_wo_chain:{ *:[v16i8] } 3023:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVE_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6767 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_B,
6768 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6769 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6770 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6771 : GIR_EraseFromParent, /*InsnID*/0,
6772 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6773 : // GIR_Coverage, 496,
6774 : GIR_Done,
6775 : // Label 505: @14967
6776 : GIM_Try, /*On fail goto*//*Label 506*/ 15019, // Rule ID 497 //
6777 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6778 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_h,
6779 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
6780 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6781 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
6782 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
6783 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
6784 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
6785 : // (intrinsic_wo_chain:{ *:[v8i16] } 3025:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVE_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
6786 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_H,
6787 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6788 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6789 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6790 : GIR_EraseFromParent, /*InsnID*/0,
6791 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6792 : // GIR_Coverage, 497,
6793 : GIR_Done,
6794 : // Label 506: @15019
6795 : GIM_Try, /*On fail goto*//*Label 507*/ 15071, // Rule ID 498 //
6796 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6797 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_w,
6798 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
6799 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6800 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
6801 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
6802 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
6803 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
6804 : // (intrinsic_wo_chain:{ *:[v4i32] } 3026:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVE_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
6805 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_W,
6806 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6807 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6808 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6809 : GIR_EraseFromParent, /*InsnID*/0,
6810 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6811 : // GIR_Coverage, 498,
6812 : GIR_Done,
6813 : // Label 507: @15071
6814 : GIM_Try, /*On fail goto*//*Label 508*/ 15123, // Rule ID 499 //
6815 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6816 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_d,
6817 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
6818 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
6819 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
6820 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
6821 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
6822 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
6823 : // (intrinsic_wo_chain:{ *:[v2i64] } 3024:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVE_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
6824 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_D,
6825 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6826 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6827 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6828 : GIR_EraseFromParent, /*InsnID*/0,
6829 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6830 : // GIR_Coverage, 499,
6831 : GIR_Done,
6832 : // Label 508: @15123
6833 : GIM_Try, /*On fail goto*//*Label 509*/ 15175, // Rule ID 500 //
6834 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6835 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_b,
6836 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6837 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6838 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6839 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6840 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6841 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6842 : // (intrinsic_wo_chain:{ *:[v16i8] } 3027:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVE_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6843 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_B,
6844 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6845 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6846 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6847 : GIR_EraseFromParent, /*InsnID*/0,
6848 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6849 : // GIR_Coverage, 500,
6850 : GIR_Done,
6851 : // Label 509: @15175
6852 : GIM_Try, /*On fail goto*//*Label 510*/ 15227, // Rule ID 501 //
6853 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6854 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_h,
6855 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
6856 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6857 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
6858 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
6859 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
6860 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
6861 : // (intrinsic_wo_chain:{ *:[v8i16] } 3029:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVE_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
6862 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_H,
6863 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6864 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6865 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6866 : GIR_EraseFromParent, /*InsnID*/0,
6867 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6868 : // GIR_Coverage, 501,
6869 : GIR_Done,
6870 : // Label 510: @15227
6871 : GIM_Try, /*On fail goto*//*Label 511*/ 15279, // Rule ID 502 //
6872 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6873 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_w,
6874 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
6875 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6876 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
6877 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
6878 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
6879 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
6880 : // (intrinsic_wo_chain:{ *:[v4i32] } 3030:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVE_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
6881 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_W,
6882 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6883 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6884 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6885 : GIR_EraseFromParent, /*InsnID*/0,
6886 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6887 : // GIR_Coverage, 502,
6888 : GIR_Done,
6889 : // Label 511: @15279
6890 : GIM_Try, /*On fail goto*//*Label 512*/ 15331, // Rule ID 503 //
6891 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6892 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_d,
6893 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
6894 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
6895 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
6896 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
6897 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
6898 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
6899 : // (intrinsic_wo_chain:{ *:[v2i64] } 3028:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVE_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
6900 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_D,
6901 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6902 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6903 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6904 : GIR_EraseFromParent, /*InsnID*/0,
6905 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6906 : // GIR_Coverage, 503,
6907 : GIR_Done,
6908 : // Label 512: @15331
6909 : GIM_Try, /*On fail goto*//*Label 513*/ 15383, // Rule ID 504 //
6910 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6911 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_b,
6912 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6913 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6914 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6915 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6916 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6917 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6918 : // (intrinsic_wo_chain:{ *:[v16i8] } 3031:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVER_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6919 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_B,
6920 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6921 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6922 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6923 : GIR_EraseFromParent, /*InsnID*/0,
6924 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6925 : // GIR_Coverage, 504,
6926 : GIR_Done,
6927 : // Label 513: @15383
6928 : GIM_Try, /*On fail goto*//*Label 514*/ 15435, // Rule ID 505 //
6929 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6930 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_h,
6931 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
6932 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6933 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
6934 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
6935 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
6936 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
6937 : // (intrinsic_wo_chain:{ *:[v8i16] } 3033:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVER_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
6938 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_H,
6939 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6940 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6941 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6942 : GIR_EraseFromParent, /*InsnID*/0,
6943 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6944 : // GIR_Coverage, 505,
6945 : GIR_Done,
6946 : // Label 514: @15435
6947 : GIM_Try, /*On fail goto*//*Label 515*/ 15487, // Rule ID 506 //
6948 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6949 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_w,
6950 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
6951 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6952 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
6953 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
6954 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
6955 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
6956 : // (intrinsic_wo_chain:{ *:[v4i32] } 3034:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVER_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
6957 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_W,
6958 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6959 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6960 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6961 : GIR_EraseFromParent, /*InsnID*/0,
6962 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6963 : // GIR_Coverage, 506,
6964 : GIR_Done,
6965 : // Label 515: @15487
6966 : GIM_Try, /*On fail goto*//*Label 516*/ 15539, // Rule ID 507 //
6967 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6968 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_d,
6969 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
6970 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
6971 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
6972 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
6973 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
6974 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
6975 : // (intrinsic_wo_chain:{ *:[v2i64] } 3032:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVER_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
6976 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_D,
6977 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6978 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6979 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6980 : GIR_EraseFromParent, /*InsnID*/0,
6981 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6982 : // GIR_Coverage, 507,
6983 : GIR_Done,
6984 : // Label 516: @15539
6985 : GIM_Try, /*On fail goto*//*Label 517*/ 15591, // Rule ID 508 //
6986 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
6987 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_b,
6988 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
6989 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6990 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
6991 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
6992 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
6993 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
6994 : // (intrinsic_wo_chain:{ *:[v16i8] } 3035:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVER_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
6995 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_B,
6996 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
6997 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
6998 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
6999 : GIR_EraseFromParent, /*InsnID*/0,
7000 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7001 : // GIR_Coverage, 508,
7002 : GIR_Done,
7003 : // Label 517: @15591
7004 : GIM_Try, /*On fail goto*//*Label 518*/ 15643, // Rule ID 509 //
7005 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7006 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_h,
7007 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7008 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
7009 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
7010 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7011 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
7012 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
7013 : // (intrinsic_wo_chain:{ *:[v8i16] } 3037:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVER_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
7014 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_H,
7015 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7016 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7017 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7018 : GIR_EraseFromParent, /*InsnID*/0,
7019 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7020 : // GIR_Coverage, 509,
7021 : GIR_Done,
7022 : // Label 518: @15643
7023 : GIM_Try, /*On fail goto*//*Label 519*/ 15695, // Rule ID 510 //
7024 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7025 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_w,
7026 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7027 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7028 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7029 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7030 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7031 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7032 : // (intrinsic_wo_chain:{ *:[v4i32] } 3038:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVER_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
7033 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_W,
7034 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7035 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7036 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7037 : GIR_EraseFromParent, /*InsnID*/0,
7038 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7039 : // GIR_Coverage, 510,
7040 : GIR_Done,
7041 : // Label 519: @15695
7042 : GIM_Try, /*On fail goto*//*Label 520*/ 15747, // Rule ID 511 //
7043 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7044 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_d,
7045 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7046 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7047 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7048 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7049 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7050 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7051 : // (intrinsic_wo_chain:{ *:[v2i64] } 3036:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVER_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
7052 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_D,
7053 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7054 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7055 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7056 : GIR_EraseFromParent, /*InsnID*/0,
7057 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7058 : // GIR_Coverage, 511,
7059 : GIR_Done,
7060 : // Label 520: @15747
7061 : GIM_Try, /*On fail goto*//*Label 521*/ 15799, // Rule ID 620 //
7062 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7063 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_s_h,
7064 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7065 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
7066 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
7067 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7068 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
7069 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
7070 : // (intrinsic_wo_chain:{ *:[v8i16] } 3170:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DOTP_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
7071 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_S_H,
7072 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7073 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7074 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7075 : GIR_EraseFromParent, /*InsnID*/0,
7076 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7077 : // GIR_Coverage, 620,
7078 : GIR_Done,
7079 : // Label 521: @15799
7080 : GIM_Try, /*On fail goto*//*Label 522*/ 15851, // Rule ID 621 //
7081 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7082 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_s_w,
7083 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7084 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
7085 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
7086 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7087 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
7088 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
7089 : // (intrinsic_wo_chain:{ *:[v4i32] } 3171:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DOTP_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
7090 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_S_W,
7091 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7092 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7093 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7094 : GIR_EraseFromParent, /*InsnID*/0,
7095 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7096 : // GIR_Coverage, 621,
7097 : GIR_Done,
7098 : // Label 522: @15851
7099 : GIM_Try, /*On fail goto*//*Label 523*/ 15903, // Rule ID 622 //
7100 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7101 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_s_d,
7102 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7103 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7104 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7105 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7106 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7107 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7108 : // (intrinsic_wo_chain:{ *:[v2i64] } 3169:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DOTP_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
7109 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_S_D,
7110 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7111 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7112 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7113 : GIR_EraseFromParent, /*InsnID*/0,
7114 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7115 : // GIR_Coverage, 622,
7116 : GIR_Done,
7117 : // Label 523: @15903
7118 : GIM_Try, /*On fail goto*//*Label 524*/ 15955, // Rule ID 623 //
7119 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7120 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_u_h,
7121 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7122 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
7123 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
7124 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7125 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
7126 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
7127 : // (intrinsic_wo_chain:{ *:[v8i16] } 3173:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DOTP_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
7128 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_U_H,
7129 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7130 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7131 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7132 : GIR_EraseFromParent, /*InsnID*/0,
7133 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7134 : // GIR_Coverage, 623,
7135 : GIR_Done,
7136 : // Label 524: @15955
7137 : GIM_Try, /*On fail goto*//*Label 525*/ 16007, // Rule ID 624 //
7138 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7139 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_u_w,
7140 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7141 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
7142 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
7143 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7144 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
7145 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
7146 : // (intrinsic_wo_chain:{ *:[v4i32] } 3174:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DOTP_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
7147 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_U_W,
7148 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7149 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7150 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7151 : GIR_EraseFromParent, /*InsnID*/0,
7152 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7153 : // GIR_Coverage, 624,
7154 : GIR_Done,
7155 : // Label 525: @16007
7156 : GIM_Try, /*On fail goto*//*Label 526*/ 16059, // Rule ID 625 //
7157 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7158 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_u_d,
7159 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7160 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7161 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7162 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7163 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7164 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7165 : // (intrinsic_wo_chain:{ *:[v2i64] } 3172:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DOTP_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
7166 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_U_D,
7167 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7168 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7169 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7170 : GIR_EraseFromParent, /*InsnID*/0,
7171 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7172 : // GIR_Coverage, 625,
7173 : GIR_Done,
7174 : // Label 526: @16059
7175 : GIM_Try, /*On fail goto*//*Label 527*/ 16111, // Rule ID 640 //
7176 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7177 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fcaf_w,
7178 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7179 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7180 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7181 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7182 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7183 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7184 : // (intrinsic_wo_chain:{ *:[v4i32] } 3212:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FCAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7185 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCAF_W,
7186 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7187 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7188 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7189 : GIR_EraseFromParent, /*InsnID*/0,
7190 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7191 : // GIR_Coverage, 640,
7192 : GIR_Done,
7193 : // Label 527: @16111
7194 : GIM_Try, /*On fail goto*//*Label 528*/ 16163, // Rule ID 641 //
7195 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7196 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fcaf_d,
7197 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7198 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7199 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7200 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7201 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7202 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7203 : // (intrinsic_wo_chain:{ *:[v2i64] } 3211:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FCAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7204 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCAF_D,
7205 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7206 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7207 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7208 : GIR_EraseFromParent, /*InsnID*/0,
7209 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7210 : // GIR_Coverage, 641,
7211 : GIR_Done,
7212 : // Label 528: @16163
7213 : GIM_Try, /*On fail goto*//*Label 529*/ 16215, // Rule ID 666 //
7214 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7215 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexdo_h,
7216 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7217 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7218 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7219 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7220 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7221 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7222 : // (intrinsic_wo_chain:{ *:[v8f16] } 3237:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FEXDO_H:{ *:[v8f16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7223 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXDO_H,
7224 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7225 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7226 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7227 : GIR_EraseFromParent, /*InsnID*/0,
7228 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7229 : // GIR_Coverage, 666,
7230 : GIR_Done,
7231 : // Label 529: @16215
7232 : GIM_Try, /*On fail goto*//*Label 530*/ 16267, // Rule ID 667 //
7233 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7234 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexdo_w,
7235 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7236 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7237 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7238 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7239 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7240 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7241 : // (intrinsic_wo_chain:{ *:[v4f32] } 3238:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FEXDO_W:{ *:[v4f32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7242 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXDO_W,
7243 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7244 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7245 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7246 : GIR_EraseFromParent, /*InsnID*/0,
7247 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7248 : // GIR_Coverage, 667,
7249 : GIR_Done,
7250 : // Label 530: @16267
7251 : GIM_Try, /*On fail goto*//*Label 531*/ 16319, // Rule ID 694 //
7252 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7253 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_w,
7254 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7255 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7256 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7257 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7258 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7259 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7260 : // (intrinsic_wo_chain:{ *:[v4f32] } 3264:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMAX_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7261 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_W,
7262 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7263 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7264 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7265 : GIR_EraseFromParent, /*InsnID*/0,
7266 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7267 : // GIR_Coverage, 694,
7268 : GIR_Done,
7269 : // Label 531: @16319
7270 : GIM_Try, /*On fail goto*//*Label 532*/ 16371, // Rule ID 695 //
7271 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7272 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_d,
7273 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7274 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7275 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7276 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7277 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7278 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7279 : // (intrinsic_wo_chain:{ *:[v2f64] } 3263:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMAX_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7280 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_D,
7281 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7282 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7283 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7284 : GIR_EraseFromParent, /*InsnID*/0,
7285 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7286 : // GIR_Coverage, 695,
7287 : GIR_Done,
7288 : // Label 532: @16371
7289 : GIM_Try, /*On fail goto*//*Label 533*/ 16423, // Rule ID 696 //
7290 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7291 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_a_w,
7292 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7293 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7294 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7295 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7296 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7297 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7298 : // (intrinsic_wo_chain:{ *:[v4f32] } 3262:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMAX_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7299 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_A_W,
7300 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7301 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7302 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7303 : GIR_EraseFromParent, /*InsnID*/0,
7304 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7305 : // GIR_Coverage, 696,
7306 : GIR_Done,
7307 : // Label 533: @16423
7308 : GIM_Try, /*On fail goto*//*Label 534*/ 16475, // Rule ID 697 //
7309 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7310 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_a_d,
7311 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7312 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7313 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7314 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7315 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7316 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7317 : // (intrinsic_wo_chain:{ *:[v2f64] } 3261:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMAX_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7318 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_A_D,
7319 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7320 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7321 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7322 : GIR_EraseFromParent, /*InsnID*/0,
7323 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7324 : // GIR_Coverage, 697,
7325 : GIR_Done,
7326 : // Label 534: @16475
7327 : GIM_Try, /*On fail goto*//*Label 535*/ 16527, // Rule ID 698 //
7328 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7329 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_w,
7330 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7331 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7332 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7333 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7334 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7335 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7336 : // (intrinsic_wo_chain:{ *:[v4f32] } 3268:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMIN_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7337 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_W,
7338 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7339 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7340 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7341 : GIR_EraseFromParent, /*InsnID*/0,
7342 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7343 : // GIR_Coverage, 698,
7344 : GIR_Done,
7345 : // Label 535: @16527
7346 : GIM_Try, /*On fail goto*//*Label 536*/ 16579, // Rule ID 699 //
7347 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7348 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_d,
7349 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7350 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7351 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7352 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7353 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7354 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7355 : // (intrinsic_wo_chain:{ *:[v2f64] } 3267:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMIN_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7356 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_D,
7357 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7358 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7359 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7360 : GIR_EraseFromParent, /*InsnID*/0,
7361 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7362 : // GIR_Coverage, 699,
7363 : GIR_Done,
7364 : // Label 536: @16579
7365 : GIM_Try, /*On fail goto*//*Label 537*/ 16631, // Rule ID 700 //
7366 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7367 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_a_w,
7368 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7369 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7370 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7371 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7372 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7373 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7374 : // (intrinsic_wo_chain:{ *:[v4f32] } 3266:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMIN_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7375 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_A_W,
7376 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7377 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7378 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7379 : GIR_EraseFromParent, /*InsnID*/0,
7380 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7381 : // GIR_Coverage, 700,
7382 : GIR_Done,
7383 : // Label 537: @16631
7384 : GIM_Try, /*On fail goto*//*Label 538*/ 16683, // Rule ID 701 //
7385 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7386 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_a_d,
7387 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7388 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7389 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7390 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7391 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7392 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7393 : // (intrinsic_wo_chain:{ *:[v2f64] } 3265:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMIN_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7394 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_A_D,
7395 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7396 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7397 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7398 : GIR_EraseFromParent, /*InsnID*/0,
7399 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7400 : // GIR_Coverage, 701,
7401 : GIR_Done,
7402 : // Label 538: @16683
7403 : GIM_Try, /*On fail goto*//*Label 539*/ 16735, // Rule ID 712 //
7404 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7405 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsaf_w,
7406 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7407 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7408 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7409 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7410 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7411 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7412 : // (intrinsic_wo_chain:{ *:[v4i32] } 3280:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7413 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSAF_W,
7414 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7415 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7416 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7417 : GIR_EraseFromParent, /*InsnID*/0,
7418 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7419 : // GIR_Coverage, 712,
7420 : GIR_Done,
7421 : // Label 539: @16735
7422 : GIM_Try, /*On fail goto*//*Label 540*/ 16787, // Rule ID 713 //
7423 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7424 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsaf_d,
7425 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7426 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7427 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7428 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7429 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7430 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7431 : // (intrinsic_wo_chain:{ *:[v2i64] } 3279:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7432 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSAF_D,
7433 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7434 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7435 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7436 : GIR_EraseFromParent, /*InsnID*/0,
7437 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7438 : // GIR_Coverage, 713,
7439 : GIR_Done,
7440 : // Label 540: @16787
7441 : GIM_Try, /*On fail goto*//*Label 541*/ 16839, // Rule ID 714 //
7442 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7443 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fseq_w,
7444 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7445 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7446 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7447 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7448 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7449 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7450 : // (intrinsic_wo_chain:{ *:[v4i32] } 3282:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7451 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSEQ_W,
7452 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7453 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7454 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7455 : GIR_EraseFromParent, /*InsnID*/0,
7456 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7457 : // GIR_Coverage, 714,
7458 : GIR_Done,
7459 : // Label 541: @16839
7460 : GIM_Try, /*On fail goto*//*Label 542*/ 16891, // Rule ID 715 //
7461 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7462 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fseq_d,
7463 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7464 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7465 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7466 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7467 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7468 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7469 : // (intrinsic_wo_chain:{ *:[v2i64] } 3281:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7470 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSEQ_D,
7471 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7472 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7473 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7474 : GIR_EraseFromParent, /*InsnID*/0,
7475 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7476 : // GIR_Coverage, 715,
7477 : GIR_Done,
7478 : // Label 542: @16891
7479 : GIM_Try, /*On fail goto*//*Label 543*/ 16943, // Rule ID 716 //
7480 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7481 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsle_w,
7482 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7483 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7484 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7485 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7486 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7487 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7488 : // (intrinsic_wo_chain:{ *:[v4i32] } 3284:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSLE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7489 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLE_W,
7490 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7491 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7492 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7493 : GIR_EraseFromParent, /*InsnID*/0,
7494 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7495 : // GIR_Coverage, 716,
7496 : GIR_Done,
7497 : // Label 543: @16943
7498 : GIM_Try, /*On fail goto*//*Label 544*/ 16995, // Rule ID 717 //
7499 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7500 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsle_d,
7501 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7502 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7503 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7504 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7505 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7506 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7507 : // (intrinsic_wo_chain:{ *:[v2i64] } 3283:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSLE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7508 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLE_D,
7509 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7510 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7511 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7512 : GIR_EraseFromParent, /*InsnID*/0,
7513 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7514 : // GIR_Coverage, 717,
7515 : GIR_Done,
7516 : // Label 544: @16995
7517 : GIM_Try, /*On fail goto*//*Label 545*/ 17047, // Rule ID 718 //
7518 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7519 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fslt_w,
7520 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7521 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7522 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7523 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7524 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7525 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7526 : // (intrinsic_wo_chain:{ *:[v4i32] } 3286:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSLT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7527 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLT_W,
7528 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7529 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7530 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7531 : GIR_EraseFromParent, /*InsnID*/0,
7532 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7533 : // GIR_Coverage, 718,
7534 : GIR_Done,
7535 : // Label 545: @17047
7536 : GIM_Try, /*On fail goto*//*Label 546*/ 17099, // Rule ID 719 //
7537 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7538 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fslt_d,
7539 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7540 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7541 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7542 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7543 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7544 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7545 : // (intrinsic_wo_chain:{ *:[v2i64] } 3285:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSLT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7546 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLT_D,
7547 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7548 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7549 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7550 : GIR_EraseFromParent, /*InsnID*/0,
7551 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7552 : // GIR_Coverage, 719,
7553 : GIR_Done,
7554 : // Label 546: @17099
7555 : GIM_Try, /*On fail goto*//*Label 547*/ 17151, // Rule ID 720 //
7556 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7557 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsne_w,
7558 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7559 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7560 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7561 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7562 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7563 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7564 : // (intrinsic_wo_chain:{ *:[v4i32] } 3288:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7565 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSNE_W,
7566 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7567 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7568 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7569 : GIR_EraseFromParent, /*InsnID*/0,
7570 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7571 : // GIR_Coverage, 720,
7572 : GIR_Done,
7573 : // Label 547: @17151
7574 : GIM_Try, /*On fail goto*//*Label 548*/ 17203, // Rule ID 721 //
7575 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7576 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsne_d,
7577 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7578 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7579 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7580 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7581 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7582 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7583 : // (intrinsic_wo_chain:{ *:[v2i64] } 3287:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7584 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSNE_D,
7585 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7586 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7587 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7588 : GIR_EraseFromParent, /*InsnID*/0,
7589 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7590 : // GIR_Coverage, 721,
7591 : GIR_Done,
7592 : // Label 548: @17203
7593 : GIM_Try, /*On fail goto*//*Label 549*/ 17255, // Rule ID 722 //
7594 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7595 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsor_w,
7596 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7597 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7598 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7599 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7600 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7601 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7602 : // (intrinsic_wo_chain:{ *:[v4i32] } 3290:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSOR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7603 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSOR_W,
7604 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7605 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7606 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7607 : GIR_EraseFromParent, /*InsnID*/0,
7608 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7609 : // GIR_Coverage, 722,
7610 : GIR_Done,
7611 : // Label 549: @17255
7612 : GIM_Try, /*On fail goto*//*Label 550*/ 17307, // Rule ID 723 //
7613 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7614 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsor_d,
7615 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7616 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7617 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7618 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7619 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7620 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7621 : // (intrinsic_wo_chain:{ *:[v2i64] } 3289:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSOR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7622 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSOR_D,
7623 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7624 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7625 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7626 : GIR_EraseFromParent, /*InsnID*/0,
7627 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7628 : // GIR_Coverage, 723,
7629 : GIR_Done,
7630 : // Label 550: @17307
7631 : GIM_Try, /*On fail goto*//*Label 551*/ 17359, // Rule ID 728 //
7632 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7633 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsueq_w,
7634 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7635 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7636 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7637 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7638 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7639 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7640 : // (intrinsic_wo_chain:{ *:[v4i32] } 3296:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7641 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUEQ_W,
7642 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7643 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7644 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7645 : GIR_EraseFromParent, /*InsnID*/0,
7646 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7647 : // GIR_Coverage, 728,
7648 : GIR_Done,
7649 : // Label 551: @17359
7650 : GIM_Try, /*On fail goto*//*Label 552*/ 17411, // Rule ID 729 //
7651 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7652 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsueq_d,
7653 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7654 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7655 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7656 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7657 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7658 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7659 : // (intrinsic_wo_chain:{ *:[v2i64] } 3295:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7660 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUEQ_D,
7661 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7662 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7663 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7664 : GIR_EraseFromParent, /*InsnID*/0,
7665 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7666 : // GIR_Coverage, 729,
7667 : GIR_Done,
7668 : // Label 552: @17411
7669 : GIM_Try, /*On fail goto*//*Label 553*/ 17463, // Rule ID 730 //
7670 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7671 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsule_w,
7672 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7673 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7674 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7675 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7676 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7677 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7678 : // (intrinsic_wo_chain:{ *:[v4i32] } 3298:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSULE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7679 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULE_W,
7680 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7681 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7682 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7683 : GIR_EraseFromParent, /*InsnID*/0,
7684 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7685 : // GIR_Coverage, 730,
7686 : GIR_Done,
7687 : // Label 553: @17463
7688 : GIM_Try, /*On fail goto*//*Label 554*/ 17515, // Rule ID 731 //
7689 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7690 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsule_d,
7691 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7692 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7693 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7694 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7695 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7696 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7697 : // (intrinsic_wo_chain:{ *:[v2i64] } 3297:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSULE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7698 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULE_D,
7699 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7700 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7701 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7702 : GIR_EraseFromParent, /*InsnID*/0,
7703 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7704 : // GIR_Coverage, 731,
7705 : GIR_Done,
7706 : // Label 554: @17515
7707 : GIM_Try, /*On fail goto*//*Label 555*/ 17567, // Rule ID 732 //
7708 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7709 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsult_w,
7710 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7711 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7712 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7713 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7714 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7715 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7716 : // (intrinsic_wo_chain:{ *:[v4i32] } 3300:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSULT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7717 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULT_W,
7718 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7719 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7720 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7721 : GIR_EraseFromParent, /*InsnID*/0,
7722 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7723 : // GIR_Coverage, 732,
7724 : GIR_Done,
7725 : // Label 555: @17567
7726 : GIM_Try, /*On fail goto*//*Label 556*/ 17619, // Rule ID 733 //
7727 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7728 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsult_d,
7729 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7730 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7731 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7732 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7733 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7734 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7735 : // (intrinsic_wo_chain:{ *:[v2i64] } 3299:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSULT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7736 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULT_D,
7737 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7738 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7739 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7740 : GIR_EraseFromParent, /*InsnID*/0,
7741 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7742 : // GIR_Coverage, 733,
7743 : GIR_Done,
7744 : // Label 556: @17619
7745 : GIM_Try, /*On fail goto*//*Label 557*/ 17671, // Rule ID 734 //
7746 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7747 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsun_w,
7748 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7749 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7750 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7751 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7752 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7753 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7754 : // (intrinsic_wo_chain:{ *:[v4i32] } 3302:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUN_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7755 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUN_W,
7756 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7757 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7758 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7759 : GIR_EraseFromParent, /*InsnID*/0,
7760 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7761 : // GIR_Coverage, 734,
7762 : GIR_Done,
7763 : // Label 557: @17671
7764 : GIM_Try, /*On fail goto*//*Label 558*/ 17723, // Rule ID 735 //
7765 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7766 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsun_d,
7767 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7768 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7769 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7770 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7771 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7772 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7773 : // (intrinsic_wo_chain:{ *:[v2i64] } 3301:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUN_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7774 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUN_D,
7775 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7776 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7777 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7778 : GIR_EraseFromParent, /*InsnID*/0,
7779 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7780 : // GIR_Coverage, 735,
7781 : GIR_Done,
7782 : // Label 558: @17723
7783 : GIM_Try, /*On fail goto*//*Label 559*/ 17775, // Rule ID 736 //
7784 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7785 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsune_w,
7786 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7787 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7788 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7789 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7790 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7791 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7792 : // (intrinsic_wo_chain:{ *:[v4i32] } 3304:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7793 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUNE_W,
7794 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7795 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7796 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7797 : GIR_EraseFromParent, /*InsnID*/0,
7798 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7799 : // GIR_Coverage, 736,
7800 : GIR_Done,
7801 : // Label 559: @17775
7802 : GIM_Try, /*On fail goto*//*Label 560*/ 17827, // Rule ID 737 //
7803 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7804 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsune_d,
7805 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7806 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7807 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7808 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7809 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7810 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7811 : // (intrinsic_wo_chain:{ *:[v2i64] } 3303:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7812 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUNE_D,
7813 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7814 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7815 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7816 : GIR_EraseFromParent, /*InsnID*/0,
7817 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7818 : // GIR_Coverage, 737,
7819 : GIR_Done,
7820 : // Label 560: @17827
7821 : GIM_Try, /*On fail goto*//*Label 561*/ 17879, // Rule ID 742 //
7822 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7823 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftq_h,
7824 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7825 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7826 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7827 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7828 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7829 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7830 : // (intrinsic_wo_chain:{ *:[v8i16] } 3309:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FTQ_H:{ *:[v8i16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
7831 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTQ_H,
7832 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7833 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7834 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7835 : GIR_EraseFromParent, /*InsnID*/0,
7836 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7837 : // GIR_Coverage, 742,
7838 : GIR_Done,
7839 : // Label 561: @17879
7840 : GIM_Try, /*On fail goto*//*Label 562*/ 17931, // Rule ID 743 //
7841 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7842 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftq_w,
7843 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7844 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7845 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
7846 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7847 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
7848 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
7849 : // (intrinsic_wo_chain:{ *:[v4i32] } 3310:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FTQ_W:{ *:[v4i32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
7850 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTQ_W,
7851 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7852 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7853 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7854 : GIR_EraseFromParent, /*InsnID*/0,
7855 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7856 : // GIR_Coverage, 743,
7857 : GIR_Done,
7858 : // Label 562: @17931
7859 : GIM_Try, /*On fail goto*//*Label 563*/ 17983, // Rule ID 748 //
7860 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7861 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_s_h,
7862 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7863 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
7864 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
7865 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7866 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
7867 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
7868 : // (intrinsic_wo_chain:{ *:[v8i16] } 3316:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HADD_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
7869 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_S_H,
7870 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7871 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7872 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7873 : GIR_EraseFromParent, /*InsnID*/0,
7874 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7875 : // GIR_Coverage, 748,
7876 : GIR_Done,
7877 : // Label 563: @17983
7878 : GIM_Try, /*On fail goto*//*Label 564*/ 18035, // Rule ID 749 //
7879 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7880 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_s_w,
7881 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7882 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
7883 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
7884 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7885 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
7886 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
7887 : // (intrinsic_wo_chain:{ *:[v4i32] } 3317:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HADD_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
7888 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_S_W,
7889 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7890 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7891 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7892 : GIR_EraseFromParent, /*InsnID*/0,
7893 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7894 : // GIR_Coverage, 749,
7895 : GIR_Done,
7896 : // Label 564: @18035
7897 : GIM_Try, /*On fail goto*//*Label 565*/ 18087, // Rule ID 750 //
7898 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7899 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_s_d,
7900 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7901 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7902 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7903 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7904 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7905 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7906 : // (intrinsic_wo_chain:{ *:[v2i64] } 3315:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HADD_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
7907 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_S_D,
7908 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7909 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7910 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7911 : GIR_EraseFromParent, /*InsnID*/0,
7912 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7913 : // GIR_Coverage, 750,
7914 : GIR_Done,
7915 : // Label 565: @18087
7916 : GIM_Try, /*On fail goto*//*Label 566*/ 18139, // Rule ID 751 //
7917 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7918 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_u_h,
7919 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7920 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
7921 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
7922 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7923 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
7924 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
7925 : // (intrinsic_wo_chain:{ *:[v8i16] } 3319:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HADD_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
7926 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_U_H,
7927 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7928 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7929 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7930 : GIR_EraseFromParent, /*InsnID*/0,
7931 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7932 : // GIR_Coverage, 751,
7933 : GIR_Done,
7934 : // Label 566: @18139
7935 : GIM_Try, /*On fail goto*//*Label 567*/ 18191, // Rule ID 752 //
7936 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7937 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_u_w,
7938 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7939 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
7940 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
7941 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7942 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
7943 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
7944 : // (intrinsic_wo_chain:{ *:[v4i32] } 3320:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HADD_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
7945 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_U_W,
7946 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7947 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7948 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7949 : GIR_EraseFromParent, /*InsnID*/0,
7950 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7951 : // GIR_Coverage, 752,
7952 : GIR_Done,
7953 : // Label 567: @18191
7954 : GIM_Try, /*On fail goto*//*Label 568*/ 18243, // Rule ID 753 //
7955 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7956 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_u_d,
7957 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
7958 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
7959 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
7960 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
7961 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
7962 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
7963 : // (intrinsic_wo_chain:{ *:[v2i64] } 3318:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HADD_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
7964 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_U_D,
7965 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7966 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7967 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7968 : GIR_EraseFromParent, /*InsnID*/0,
7969 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7970 : // GIR_Coverage, 753,
7971 : GIR_Done,
7972 : // Label 568: @18243
7973 : GIM_Try, /*On fail goto*//*Label 569*/ 18295, // Rule ID 754 //
7974 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7975 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_s_h,
7976 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
7977 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
7978 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
7979 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
7980 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
7981 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
7982 : // (intrinsic_wo_chain:{ *:[v8i16] } 3322:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HSUB_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
7983 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_S_H,
7984 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
7985 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
7986 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
7987 : GIR_EraseFromParent, /*InsnID*/0,
7988 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7989 : // GIR_Coverage, 754,
7990 : GIR_Done,
7991 : // Label 569: @18295
7992 : GIM_Try, /*On fail goto*//*Label 570*/ 18347, // Rule ID 755 //
7993 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
7994 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_s_w,
7995 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
7996 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
7997 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
7998 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
7999 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8000 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8001 : // (intrinsic_wo_chain:{ *:[v4i32] } 3323:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HSUB_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8002 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_S_W,
8003 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8004 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8005 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8006 : GIR_EraseFromParent, /*InsnID*/0,
8007 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8008 : // GIR_Coverage, 755,
8009 : GIR_Done,
8010 : // Label 570: @18347
8011 : GIM_Try, /*On fail goto*//*Label 571*/ 18399, // Rule ID 756 //
8012 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8013 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_s_d,
8014 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8015 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8016 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8017 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8018 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8019 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8020 : // (intrinsic_wo_chain:{ *:[v2i64] } 3321:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HSUB_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8021 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_S_D,
8022 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8023 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8024 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8025 : GIR_EraseFromParent, /*InsnID*/0,
8026 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8027 : // GIR_Coverage, 756,
8028 : GIR_Done,
8029 : // Label 571: @18399
8030 : GIM_Try, /*On fail goto*//*Label 572*/ 18451, // Rule ID 757 //
8031 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8032 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_u_h,
8033 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8034 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8035 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8036 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8037 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8038 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8039 : // (intrinsic_wo_chain:{ *:[v8i16] } 3325:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HSUB_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8040 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_U_H,
8041 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8042 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8043 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8044 : GIR_EraseFromParent, /*InsnID*/0,
8045 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8046 : // GIR_Coverage, 757,
8047 : GIR_Done,
8048 : // Label 572: @18451
8049 : GIM_Try, /*On fail goto*//*Label 573*/ 18503, // Rule ID 758 //
8050 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8051 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_u_w,
8052 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8053 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8054 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8055 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8056 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8057 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8058 : // (intrinsic_wo_chain:{ *:[v4i32] } 3326:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HSUB_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8059 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_U_W,
8060 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8061 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8062 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8063 : GIR_EraseFromParent, /*InsnID*/0,
8064 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8065 : // GIR_Coverage, 758,
8066 : GIR_Done,
8067 : // Label 573: @18503
8068 : GIM_Try, /*On fail goto*//*Label 574*/ 18555, // Rule ID 759 //
8069 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8070 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_u_d,
8071 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8072 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8073 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8074 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8075 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8076 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8077 : // (intrinsic_wo_chain:{ *:[v2i64] } 3324:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HSUB_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8078 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_U_D,
8079 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8080 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8081 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8082 : GIR_EraseFromParent, /*InsnID*/0,
8083 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8084 : // GIR_Coverage, 759,
8085 : GIR_Done,
8086 : // Label 574: @18555
8087 : GIM_Try, /*On fail goto*//*Label 575*/ 18607, // Rule ID 812 //
8088 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8089 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_b,
8090 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8091 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8092 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8093 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8094 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8095 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8096 : // (intrinsic_wo_chain:{ *:[v16i8] } 3378:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MAX_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8097 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_B,
8098 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8099 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8100 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8101 : GIR_EraseFromParent, /*InsnID*/0,
8102 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8103 : // GIR_Coverage, 812,
8104 : GIR_Done,
8105 : // Label 575: @18607
8106 : GIM_Try, /*On fail goto*//*Label 576*/ 18659, // Rule ID 813 //
8107 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8108 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_h,
8109 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8110 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8111 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8112 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8113 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8114 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8115 : // (intrinsic_wo_chain:{ *:[v8i16] } 3380:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MAX_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8116 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_H,
8117 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8118 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8119 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8120 : GIR_EraseFromParent, /*InsnID*/0,
8121 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8122 : // GIR_Coverage, 813,
8123 : GIR_Done,
8124 : // Label 576: @18659
8125 : GIM_Try, /*On fail goto*//*Label 577*/ 18711, // Rule ID 814 //
8126 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8127 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_w,
8128 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8129 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8130 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8131 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8132 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8133 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8134 : // (intrinsic_wo_chain:{ *:[v4i32] } 3381:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MAX_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8135 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_W,
8136 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8137 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8138 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8139 : GIR_EraseFromParent, /*InsnID*/0,
8140 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8141 : // GIR_Coverage, 814,
8142 : GIR_Done,
8143 : // Label 577: @18711
8144 : GIM_Try, /*On fail goto*//*Label 578*/ 18763, // Rule ID 815 //
8145 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8146 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_d,
8147 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8148 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8149 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8150 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8151 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8152 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8153 : // (intrinsic_wo_chain:{ *:[v2i64] } 3379:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MAX_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8154 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_D,
8155 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8156 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8157 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8158 : GIR_EraseFromParent, /*InsnID*/0,
8159 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8160 : // GIR_Coverage, 815,
8161 : GIR_Done,
8162 : // Label 578: @18763
8163 : GIM_Try, /*On fail goto*//*Label 579*/ 18815, // Rule ID 832 //
8164 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8165 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_b,
8166 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8167 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8168 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8169 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8170 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8171 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8172 : // (intrinsic_wo_chain:{ *:[v16i8] } 3398:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MIN_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8173 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_B,
8174 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8175 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8176 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8177 : GIR_EraseFromParent, /*InsnID*/0,
8178 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8179 : // GIR_Coverage, 832,
8180 : GIR_Done,
8181 : // Label 579: @18815
8182 : GIM_Try, /*On fail goto*//*Label 580*/ 18867, // Rule ID 833 //
8183 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8184 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_h,
8185 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8186 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8187 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8188 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8189 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8190 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8191 : // (intrinsic_wo_chain:{ *:[v8i16] } 3400:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MIN_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8192 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_H,
8193 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8194 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8195 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8196 : GIR_EraseFromParent, /*InsnID*/0,
8197 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8198 : // GIR_Coverage, 833,
8199 : GIR_Done,
8200 : // Label 580: @18867
8201 : GIM_Try, /*On fail goto*//*Label 581*/ 18919, // Rule ID 834 //
8202 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8203 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_w,
8204 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8205 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8206 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8207 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8208 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8209 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8210 : // (intrinsic_wo_chain:{ *:[v4i32] } 3401:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MIN_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8211 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_W,
8212 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8213 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8214 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8215 : GIR_EraseFromParent, /*InsnID*/0,
8216 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8217 : // GIR_Coverage, 834,
8218 : GIR_Done,
8219 : // Label 581: @18919
8220 : GIM_Try, /*On fail goto*//*Label 582*/ 18971, // Rule ID 835 //
8221 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8222 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_d,
8223 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8224 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8225 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8226 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8227 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8228 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8229 : // (intrinsic_wo_chain:{ *:[v2i64] } 3399:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MIN_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8230 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_D,
8231 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8232 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8233 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8234 : GIR_EraseFromParent, /*InsnID*/0,
8235 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8236 : // GIR_Coverage, 835,
8237 : GIR_Done,
8238 : // Label 582: @18971
8239 : GIM_Try, /*On fail goto*//*Label 583*/ 19023, // Rule ID 868 //
8240 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8241 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_q_h,
8242 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8243 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8244 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8245 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8246 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8247 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8248 : // (intrinsic_wo_chain:{ *:[v8i16] } 3440:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MUL_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8249 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_Q_H,
8250 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8251 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8252 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8253 : GIR_EraseFromParent, /*InsnID*/0,
8254 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8255 : // GIR_Coverage, 868,
8256 : GIR_Done,
8257 : // Label 583: @19023
8258 : GIM_Try, /*On fail goto*//*Label 584*/ 19075, // Rule ID 869 //
8259 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8260 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_q_w,
8261 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8262 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8263 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8264 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8265 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8266 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8267 : // (intrinsic_wo_chain:{ *:[v4i32] } 3441:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MUL_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8268 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_Q_W,
8269 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8270 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8271 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8272 : GIR_EraseFromParent, /*InsnID*/0,
8273 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8274 : // GIR_Coverage, 869,
8275 : GIR_Done,
8276 : // Label 584: @19075
8277 : GIM_Try, /*On fail goto*//*Label 585*/ 19127, // Rule ID 870 //
8278 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8279 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulr_q_h,
8280 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8281 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8282 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8283 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8284 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8285 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8286 : // (intrinsic_wo_chain:{ *:[v8i16] } 3451:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MULR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8287 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULR_Q_H,
8288 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8289 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8290 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8291 : GIR_EraseFromParent, /*InsnID*/0,
8292 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8293 : // GIR_Coverage, 870,
8294 : GIR_Done,
8295 : // Label 585: @19127
8296 : GIM_Try, /*On fail goto*//*Label 586*/ 19179, // Rule ID 871 //
8297 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8298 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulr_q_w,
8299 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8300 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8301 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8302 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8303 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8304 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8305 : // (intrinsic_wo_chain:{ *:[v4i32] } 3452:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MULR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8306 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULR_Q_W,
8307 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8308 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8309 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8310 : GIR_EraseFromParent, /*InsnID*/0,
8311 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8312 : // GIR_Coverage, 871,
8313 : GIR_Done,
8314 : // Label 586: @19179
8315 : GIM_Try, /*On fail goto*//*Label 587*/ 19231, // Rule ID 949 //
8316 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8317 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_b,
8318 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8319 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8320 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8321 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8322 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8323 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8324 : // (intrinsic_wo_chain:{ *:[v16i8] } 3565:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRAR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8325 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_B,
8326 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8327 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8328 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8329 : GIR_EraseFromParent, /*InsnID*/0,
8330 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8331 : // GIR_Coverage, 949,
8332 : GIR_Done,
8333 : // Label 587: @19231
8334 : GIM_Try, /*On fail goto*//*Label 588*/ 19283, // Rule ID 950 //
8335 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8336 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_h,
8337 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8338 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8339 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8340 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8341 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8342 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8343 : // (intrinsic_wo_chain:{ *:[v8i16] } 3567:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRAR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8344 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_H,
8345 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8346 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8347 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8348 : GIR_EraseFromParent, /*InsnID*/0,
8349 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8350 : // GIR_Coverage, 950,
8351 : GIR_Done,
8352 : // Label 588: @19283
8353 : GIM_Try, /*On fail goto*//*Label 589*/ 19335, // Rule ID 951 //
8354 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8355 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_w,
8356 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8357 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8358 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8359 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8360 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8361 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8362 : // (intrinsic_wo_chain:{ *:[v4i32] } 3568:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRAR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8363 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_W,
8364 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8365 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8366 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8367 : GIR_EraseFromParent, /*InsnID*/0,
8368 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8369 : // GIR_Coverage, 951,
8370 : GIR_Done,
8371 : // Label 589: @19335
8372 : GIM_Try, /*On fail goto*//*Label 590*/ 19387, // Rule ID 952 //
8373 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8374 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_d,
8375 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8376 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8377 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8378 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8379 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8380 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8381 : // (intrinsic_wo_chain:{ *:[v2i64] } 3566:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRAR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8382 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_D,
8383 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8384 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8385 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8386 : GIR_EraseFromParent, /*InsnID*/0,
8387 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8388 : // GIR_Coverage, 952,
8389 : GIR_Done,
8390 : // Label 590: @19387
8391 : GIM_Try, /*On fail goto*//*Label 591*/ 19439, // Rule ID 965 //
8392 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8393 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_b,
8394 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8395 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8396 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8397 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8398 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8399 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8400 : // (intrinsic_wo_chain:{ *:[v16i8] } 3581:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRLR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8401 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_B,
8402 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8403 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8404 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8405 : GIR_EraseFromParent, /*InsnID*/0,
8406 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8407 : // GIR_Coverage, 965,
8408 : GIR_Done,
8409 : // Label 591: @19439
8410 : GIM_Try, /*On fail goto*//*Label 592*/ 19491, // Rule ID 966 //
8411 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8412 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_h,
8413 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8414 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8415 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8416 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8417 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8418 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8419 : // (intrinsic_wo_chain:{ *:[v8i16] } 3583:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRLR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8420 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_H,
8421 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8422 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8423 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8424 : GIR_EraseFromParent, /*InsnID*/0,
8425 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8426 : // GIR_Coverage, 966,
8427 : GIR_Done,
8428 : // Label 592: @19491
8429 : GIM_Try, /*On fail goto*//*Label 593*/ 19543, // Rule ID 967 //
8430 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8431 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_w,
8432 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8433 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8434 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8435 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8436 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8437 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8438 : // (intrinsic_wo_chain:{ *:[v4i32] } 3584:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRLR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8439 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_W,
8440 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8441 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8442 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8443 : GIR_EraseFromParent, /*InsnID*/0,
8444 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8445 : // GIR_Coverage, 967,
8446 : GIR_Done,
8447 : // Label 593: @19543
8448 : GIM_Try, /*On fail goto*//*Label 594*/ 19595, // Rule ID 968 //
8449 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8450 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_d,
8451 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8452 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8453 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8454 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8455 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8456 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8457 : // (intrinsic_wo_chain:{ *:[v2i64] } 3582:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRLR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8458 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_D,
8459 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8460 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8461 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8462 : GIR_EraseFromParent, /*InsnID*/0,
8463 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8464 : // GIR_Coverage, 968,
8465 : GIR_Done,
8466 : // Label 594: @19595
8467 : GIM_Try, /*On fail goto*//*Label 595*/ 19647, // Rule ID 977 //
8468 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8469 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_b,
8470 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8471 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8472 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8473 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8474 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8475 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8476 : // (intrinsic_wo_chain:{ *:[v16i8] } 3600:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8477 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_B,
8478 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8479 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8480 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8481 : GIR_EraseFromParent, /*InsnID*/0,
8482 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8483 : // GIR_Coverage, 977,
8484 : GIR_Done,
8485 : // Label 595: @19647
8486 : GIM_Try, /*On fail goto*//*Label 596*/ 19699, // Rule ID 978 //
8487 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8488 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_h,
8489 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8490 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8491 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8492 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8493 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8494 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8495 : // (intrinsic_wo_chain:{ *:[v8i16] } 3602:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8496 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_H,
8497 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8498 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8499 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8500 : GIR_EraseFromParent, /*InsnID*/0,
8501 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8502 : // GIR_Coverage, 978,
8503 : GIR_Done,
8504 : // Label 596: @19699
8505 : GIM_Try, /*On fail goto*//*Label 597*/ 19751, // Rule ID 979 //
8506 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8507 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_w,
8508 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8509 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8510 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8511 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8512 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8513 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8514 : // (intrinsic_wo_chain:{ *:[v4i32] } 3603:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8515 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_W,
8516 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8517 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8518 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8519 : GIR_EraseFromParent, /*InsnID*/0,
8520 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8521 : // GIR_Coverage, 979,
8522 : GIR_Done,
8523 : // Label 597: @19751
8524 : GIM_Try, /*On fail goto*//*Label 598*/ 19803, // Rule ID 980 //
8525 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8526 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_d,
8527 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8528 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8529 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8530 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8531 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8532 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8533 : // (intrinsic_wo_chain:{ *:[v2i64] } 3601:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8534 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_D,
8535 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8536 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8537 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8538 : GIR_EraseFromParent, /*InsnID*/0,
8539 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8540 : // GIR_Coverage, 980,
8541 : GIR_Done,
8542 : // Label 598: @19803
8543 : GIM_Try, /*On fail goto*//*Label 599*/ 19855, // Rule ID 981 //
8544 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8545 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_b,
8546 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8547 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8548 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8549 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8550 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8551 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8552 : // (intrinsic_wo_chain:{ *:[v16i8] } 3604:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8553 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_B,
8554 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8555 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8556 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8557 : GIR_EraseFromParent, /*InsnID*/0,
8558 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8559 : // GIR_Coverage, 981,
8560 : GIR_Done,
8561 : // Label 599: @19855
8562 : GIM_Try, /*On fail goto*//*Label 600*/ 19907, // Rule ID 982 //
8563 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8564 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_h,
8565 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8566 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8567 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8568 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8569 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8570 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8571 : // (intrinsic_wo_chain:{ *:[v8i16] } 3606:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8572 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_H,
8573 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8574 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8575 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8576 : GIR_EraseFromParent, /*InsnID*/0,
8577 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8578 : // GIR_Coverage, 982,
8579 : GIR_Done,
8580 : // Label 600: @19907
8581 : GIM_Try, /*On fail goto*//*Label 601*/ 19959, // Rule ID 983 //
8582 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8583 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_w,
8584 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8585 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8586 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8587 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8588 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8589 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8590 : // (intrinsic_wo_chain:{ *:[v4i32] } 3607:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8591 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_W,
8592 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8593 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8594 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8595 : GIR_EraseFromParent, /*InsnID*/0,
8596 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8597 : // GIR_Coverage, 983,
8598 : GIR_Done,
8599 : // Label 601: @19959
8600 : GIM_Try, /*On fail goto*//*Label 602*/ 20011, // Rule ID 984 //
8601 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8602 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_d,
8603 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8604 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8605 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8606 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8607 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8608 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8609 : // (intrinsic_wo_chain:{ *:[v2i64] } 3605:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8610 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_D,
8611 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8612 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8613 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8614 : GIR_EraseFromParent, /*InsnID*/0,
8615 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8616 : // GIR_Coverage, 984,
8617 : GIR_Done,
8618 : // Label 602: @20011
8619 : GIM_Try, /*On fail goto*//*Label 603*/ 20063, // Rule ID 985 //
8620 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8621 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_b,
8622 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8623 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8624 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8625 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8626 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8627 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8628 : // (intrinsic_wo_chain:{ *:[v16i8] } 3608:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBSUS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8629 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_B,
8630 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8631 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8632 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8633 : GIR_EraseFromParent, /*InsnID*/0,
8634 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8635 : // GIR_Coverage, 985,
8636 : GIR_Done,
8637 : // Label 603: @20063
8638 : GIM_Try, /*On fail goto*//*Label 604*/ 20115, // Rule ID 986 //
8639 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8640 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_h,
8641 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8642 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8643 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8644 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8645 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8646 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8647 : // (intrinsic_wo_chain:{ *:[v8i16] } 3610:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBSUS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8648 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_H,
8649 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8650 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8651 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8652 : GIR_EraseFromParent, /*InsnID*/0,
8653 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8654 : // GIR_Coverage, 986,
8655 : GIR_Done,
8656 : // Label 604: @20115
8657 : GIM_Try, /*On fail goto*//*Label 605*/ 20167, // Rule ID 987 //
8658 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8659 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_w,
8660 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8661 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8662 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8663 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8664 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8665 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8666 : // (intrinsic_wo_chain:{ *:[v4i32] } 3611:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBSUS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8667 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_W,
8668 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8669 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8670 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8671 : GIR_EraseFromParent, /*InsnID*/0,
8672 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8673 : // GIR_Coverage, 987,
8674 : GIR_Done,
8675 : // Label 605: @20167
8676 : GIM_Try, /*On fail goto*//*Label 606*/ 20219, // Rule ID 988 //
8677 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8678 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_d,
8679 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8680 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8681 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8682 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8683 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8684 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8685 : // (intrinsic_wo_chain:{ *:[v2i64] } 3609:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBSUS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8686 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_D,
8687 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8688 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8689 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8690 : GIR_EraseFromParent, /*InsnID*/0,
8691 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8692 : // GIR_Coverage, 988,
8693 : GIR_Done,
8694 : // Label 606: @20219
8695 : GIM_Try, /*On fail goto*//*Label 607*/ 20271, // Rule ID 989 //
8696 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8697 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_b,
8698 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
8699 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8700 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
8701 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
8702 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
8703 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
8704 : // (intrinsic_wo_chain:{ *:[v16i8] } 3612:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBSUU_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8705 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_B,
8706 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8707 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8708 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8709 : GIR_EraseFromParent, /*InsnID*/0,
8710 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8711 : // GIR_Coverage, 989,
8712 : GIR_Done,
8713 : // Label 607: @20271
8714 : GIM_Try, /*On fail goto*//*Label 608*/ 20323, // Rule ID 990 //
8715 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8716 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_h,
8717 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8718 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8719 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
8720 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
8721 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
8722 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
8723 : // (intrinsic_wo_chain:{ *:[v8i16] } 3614:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBSUU_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8724 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_H,
8725 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8726 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8727 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8728 : GIR_EraseFromParent, /*InsnID*/0,
8729 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8730 : // GIR_Coverage, 990,
8731 : GIR_Done,
8732 : // Label 608: @20323
8733 : GIM_Try, /*On fail goto*//*Label 609*/ 20375, // Rule ID 991 //
8734 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8735 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_w,
8736 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8737 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8738 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
8739 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
8740 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
8741 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
8742 : // (intrinsic_wo_chain:{ *:[v4i32] } 3615:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBSUU_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8743 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_W,
8744 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8745 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8746 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8747 : GIR_EraseFromParent, /*InsnID*/0,
8748 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8749 : // GIR_Coverage, 991,
8750 : GIR_Done,
8751 : // Label 609: @20375
8752 : GIM_Try, /*On fail goto*//*Label 610*/ 20427, // Rule ID 992 //
8753 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
8754 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_d,
8755 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8756 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8757 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
8758 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
8759 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
8760 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
8761 : // (intrinsic_wo_chain:{ *:[v2i64] } 3613:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBSUU_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8762 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_D,
8763 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
8764 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
8765 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
8766 : GIR_EraseFromParent, /*InsnID*/0,
8767 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8768 : // GIR_Coverage, 992,
8769 : GIR_Done,
8770 : // Label 610: @20427
8771 : GIM_Try, /*On fail goto*//*Label 611*/ 20479, // Rule ID 1189 //
8772 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
8773 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_s_ph,
8774 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
8775 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
8776 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
8777 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
8778 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
8779 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
8780 : // (intrinsic_wo_chain:{ *:[v2i16] } 2978:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
8781 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_PH_MM,
8782 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
8783 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
8784 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
8785 : GIR_EraseFromParent, /*InsnID*/0,
8786 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8787 : // GIR_Coverage, 1189,
8788 : GIR_Done,
8789 : // Label 611: @20479
8790 : GIM_Try, /*On fail goto*//*Label 612*/ 20531, // Rule ID 1191 //
8791 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
8792 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_s_qb,
8793 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
8794 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
8795 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
8796 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
8797 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
8798 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
8799 : // (intrinsic_wo_chain:{ *:[v4i8] } 3000:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
8800 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_QB_MM,
8801 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
8802 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
8803 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
8804 : GIR_EraseFromParent, /*InsnID*/0,
8805 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8806 : // GIR_Coverage, 1191,
8807 : GIR_Done,
8808 : // Label 612: @20531
8809 : GIM_Try, /*On fail goto*//*Label 613*/ 20583, // Rule ID 1212 //
8810 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
8811 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_ph,
8812 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
8813 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
8814 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
8815 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
8816 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
8817 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
8818 : // (intrinsic_wo_chain:{ *:[v2i16] } 3526:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
8819 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_PH_MM,
8820 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
8821 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
8822 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
8823 : GIR_EraseFromParent, /*InsnID*/0,
8824 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8825 : // GIR_Coverage, 1212,
8826 : GIR_Done,
8827 : // Label 613: @20583
8828 : GIM_Try, /*On fail goto*//*Label 614*/ 20635, // Rule ID 1213 //
8829 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
8830 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph,
8831 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
8832 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
8833 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
8834 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
8835 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
8836 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
8837 : // (intrinsic_wo_chain:{ *:[v2i16] } 3528:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
8838 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_PH_MM,
8839 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
8840 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
8841 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
8842 : GIR_EraseFromParent, /*InsnID*/0,
8843 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8844 : // GIR_Coverage, 1213,
8845 : GIR_Done,
8846 : // Label 614: @20635
8847 : GIM_Try, /*On fail goto*//*Label 615*/ 20687, // Rule ID 1214 //
8848 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
8849 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w,
8850 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
8851 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
8852 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
8853 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
8854 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
8855 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
8856 : // (intrinsic_wo_chain:{ *:[i32] } 3530:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
8857 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_W_MM,
8858 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
8859 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
8860 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
8861 : GIR_EraseFromParent, /*InsnID*/0,
8862 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8863 : // GIR_Coverage, 1214,
8864 : GIR_Done,
8865 : // Label 615: @20687
8866 : GIM_Try, /*On fail goto*//*Label 616*/ 20739, // Rule ID 1216 //
8867 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
8868 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_qb,
8869 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
8870 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
8871 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
8872 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
8873 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
8874 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
8875 : // (intrinsic_wo_chain:{ *:[v4i8] } 3532:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
8876 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_QB_MM,
8877 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
8878 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
8879 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
8880 : GIR_EraseFromParent, /*InsnID*/0,
8881 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8882 : // GIR_Coverage, 1216,
8883 : GIR_Done,
8884 : // Label 616: @20739
8885 : GIM_Try, /*On fail goto*//*Label 617*/ 20791, // Rule ID 1227 //
8886 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
8887 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_s_ph,
8888 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
8889 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
8890 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
8891 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
8892 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
8893 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
8894 : // (intrinsic_wo_chain:{ *:[v2i16] } 3594:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
8895 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_PH_MM,
8896 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
8897 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
8898 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
8899 : GIR_EraseFromParent, /*InsnID*/0,
8900 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8901 : // GIR_Coverage, 1227,
8902 : GIR_Done,
8903 : // Label 617: @20791
8904 : GIM_Try, /*On fail goto*//*Label 618*/ 20843, // Rule ID 1229 //
8905 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
8906 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_s_qb,
8907 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
8908 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
8909 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
8910 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
8911 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
8912 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
8913 : // (intrinsic_wo_chain:{ *:[v4i8] } 3619:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
8914 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_QB_MM,
8915 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
8916 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
8917 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
8918 : GIR_EraseFromParent, /*InsnID*/0,
8919 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8920 : // GIR_Coverage, 1229,
8921 : GIR_Done,
8922 : // Label 618: @20843
8923 : GIM_Try, /*On fail goto*//*Label 619*/ 20895, // Rule ID 1239 //
8924 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
8925 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_ph_w,
8926 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
8927 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
8928 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
8929 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
8930 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
8931 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
8932 : // (intrinsic_wo_chain:{ *:[v2i16] } 3501:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
8933 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_PH_W_MM,
8934 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
8935 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
8936 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
8937 : GIR_EraseFromParent, /*InsnID*/0,
8938 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8939 : // GIR_Coverage, 1239,
8940 : GIR_Done,
8941 : // Label 619: @20895
8942 : GIM_Try, /*On fail goto*//*Label 620*/ 20947, // Rule ID 1240 //
8943 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
8944 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_qb_ph,
8945 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
8946 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
8947 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
8948 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
8949 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
8950 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
8951 : // (intrinsic_wo_chain:{ *:[v4i8] } 3502:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQ_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
8952 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_QB_PH_MM,
8953 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
8954 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
8955 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
8956 : GIR_EraseFromParent, /*InsnID*/0,
8957 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8958 : // GIR_Coverage, 1240,
8959 : GIR_Done,
8960 : // Label 620: @20947
8961 : GIM_Try, /*On fail goto*//*Label 621*/ 20999, // Rule ID 1259 //
8962 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
8963 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_packrl_ph,
8964 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
8965 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
8966 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
8967 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
8968 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
8969 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
8970 : // (intrinsic_wo_chain:{ *:[v2i16] } 3473:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PACKRL_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
8971 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PACKRL_PH_MM,
8972 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
8973 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
8974 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
8975 : GIR_EraseFromParent, /*InsnID*/0,
8976 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8977 : // GIR_Coverage, 1259,
8978 : GIR_Done,
8979 : // Label 621: @20999
8980 : GIM_Try, /*On fail goto*//*Label 622*/ 21051, // Rule ID 1265 //
8981 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
8982 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_modsub,
8983 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
8984 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
8985 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
8986 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
8987 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
8988 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
8989 : // (intrinsic_wo_chain:{ *:[i32] } 3426:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODSUB_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
8990 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MODSUB_MM,
8991 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
8992 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
8993 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
8994 : GIR_EraseFromParent, /*InsnID*/0,
8995 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8996 : // GIR_Coverage, 1265,
8997 : GIR_Done,
8998 : // Label 622: @21051
8999 : GIM_Try, /*On fail goto*//*Label 623*/ 21103, // Rule ID 1278 //
9000 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9001 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_ph,
9002 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9003 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9004 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
9005 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9006 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9007 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9008 : // (intrinsic_wo_chain:{ *:[v2i16] } 2980:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9009 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_PH_MMR2,
9010 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9011 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9012 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9013 : GIR_EraseFromParent, /*InsnID*/0,
9014 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9015 : // GIR_Coverage, 1278,
9016 : GIR_Done,
9017 : // Label 623: @21103
9018 : GIM_Try, /*On fail goto*//*Label 624*/ 21155, // Rule ID 1279 //
9019 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9020 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_ph,
9021 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9022 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9023 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
9024 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9025 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9026 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9027 : // (intrinsic_wo_chain:{ *:[v2i16] } 2981:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9028 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_PH_MMR2,
9029 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9030 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9031 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9032 : GIR_EraseFromParent, /*InsnID*/0,
9033 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9034 : // GIR_Coverage, 1279,
9035 : GIR_Done,
9036 : // Label 624: @21155
9037 : GIM_Try, /*On fail goto*//*Label 625*/ 21207, // Rule ID 1280 //
9038 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9039 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_w,
9040 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9041 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9042 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9043 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9044 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9045 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9046 : // (intrinsic_wo_chain:{ *:[i32] } 2983:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9047 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_W_MMR2,
9048 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9049 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9050 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9051 : GIR_EraseFromParent, /*InsnID*/0,
9052 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9053 : // GIR_Coverage, 1280,
9054 : GIR_Done,
9055 : // Label 625: @21207
9056 : GIM_Try, /*On fail goto*//*Label 626*/ 21259, // Rule ID 1281 //
9057 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9058 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_w,
9059 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9060 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9061 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9062 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9063 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9064 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9065 : // (intrinsic_wo_chain:{ *:[i32] } 2982:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9066 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_W_MMR2,
9067 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9068 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9069 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9070 : GIR_EraseFromParent, /*InsnID*/0,
9071 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9072 : // GIR_Coverage, 1281,
9073 : GIR_Done,
9074 : // Label 626: @21259
9075 : GIM_Try, /*On fail goto*//*Label 627*/ 21311, // Rule ID 1284 //
9076 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9077 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adduh_qb,
9078 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9079 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
9080 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
9081 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9082 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9083 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9084 : // (intrinsic_wo_chain:{ *:[v4i8] } 3001:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
9085 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_QB_MMR2,
9086 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9087 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9088 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9089 : GIR_EraseFromParent, /*InsnID*/0,
9090 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9091 : // GIR_Coverage, 1284,
9092 : GIR_Done,
9093 : // Label 627: @21311
9094 : GIM_Try, /*On fail goto*//*Label 628*/ 21363, // Rule ID 1285 //
9095 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9096 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adduh_r_qb,
9097 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9098 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
9099 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
9100 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9101 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9102 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9103 : // (intrinsic_wo_chain:{ *:[v4i8] } 3002:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
9104 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_R_QB_MMR2,
9105 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9106 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9107 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9108 : GIR_EraseFromParent, /*InsnID*/0,
9109 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9110 : // GIR_Coverage, 1285,
9111 : GIR_Done,
9112 : // Label 628: @21363
9113 : GIM_Try, /*On fail goto*//*Label 629*/ 21415, // Rule ID 1291 //
9114 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9115 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_qb,
9116 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9117 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
9118 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9119 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9120 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9121 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9122 : // (intrinsic_wo_chain:{ *:[v4i8] } 3527:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
9123 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_QB_MMR2,
9124 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9125 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
9126 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9127 : GIR_EraseFromParent, /*InsnID*/0,
9128 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9129 : // GIR_Coverage, 1291,
9130 : GIR_Done,
9131 : // Label 629: @21415
9132 : GIM_Try, /*On fail goto*//*Label 630*/ 21467, // Rule ID 1292 //
9133 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9134 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb,
9135 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9136 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
9137 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9138 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9139 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9140 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9141 : // (intrinsic_wo_chain:{ *:[v4i8] } 3529:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
9142 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_QB_MMR2,
9143 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9144 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
9145 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9146 : GIR_EraseFromParent, /*InsnID*/0,
9147 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9148 : // GIR_Coverage, 1292,
9149 : GIR_Done,
9150 : // Label 630: @21467
9151 : GIM_Try, /*On fail goto*//*Label 631*/ 21519, // Rule ID 1297 //
9152 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9153 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_ph,
9154 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9155 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9156 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9157 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9158 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9159 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9160 : // (intrinsic_wo_chain:{ *:[v2i16] } 3531:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRLV_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
9161 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_PH_MMR2,
9162 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9163 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
9164 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9165 : GIR_EraseFromParent, /*InsnID*/0,
9166 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9167 : // GIR_Coverage, 1297,
9168 : GIR_Done,
9169 : // Label 631: @21519
9170 : GIM_Try, /*On fail goto*//*Label 632*/ 21571, // Rule ID 1298 //
9171 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9172 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_ph,
9173 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9174 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9175 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
9176 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9177 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9178 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9179 : // (intrinsic_wo_chain:{ *:[v2i16] } 3596:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9180 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_PH_MMR2,
9181 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9182 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9183 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9184 : GIR_EraseFromParent, /*InsnID*/0,
9185 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9186 : // GIR_Coverage, 1298,
9187 : GIR_Done,
9188 : // Label 632: @21571
9189 : GIM_Try, /*On fail goto*//*Label 633*/ 21623, // Rule ID 1299 //
9190 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9191 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_r_ph,
9192 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9193 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9194 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
9195 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9196 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9197 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9198 : // (intrinsic_wo_chain:{ *:[v2i16] } 3597:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9199 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_PH_MMR2,
9200 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9201 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9202 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9203 : GIR_EraseFromParent, /*InsnID*/0,
9204 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9205 : // GIR_Coverage, 1299,
9206 : GIR_Done,
9207 : // Label 633: @21623
9208 : GIM_Try, /*On fail goto*//*Label 634*/ 21675, // Rule ID 1300 //
9209 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9210 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_w,
9211 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9212 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9213 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9214 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9215 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9216 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9217 : // (intrinsic_wo_chain:{ *:[i32] } 3599:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9218 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_W_MMR2,
9219 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9220 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9221 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9222 : GIR_EraseFromParent, /*InsnID*/0,
9223 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9224 : // GIR_Coverage, 1300,
9225 : GIR_Done,
9226 : // Label 634: @21675
9227 : GIM_Try, /*On fail goto*//*Label 635*/ 21727, // Rule ID 1301 //
9228 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9229 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_r_w,
9230 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9231 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9232 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9233 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9234 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9235 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9236 : // (intrinsic_wo_chain:{ *:[i32] } 3598:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9237 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_W_MMR2,
9238 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9239 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9240 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9241 : GIR_EraseFromParent, /*InsnID*/0,
9242 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9243 : // GIR_Coverage, 1301,
9244 : GIR_Done,
9245 : // Label 635: @21727
9246 : GIM_Try, /*On fail goto*//*Label 636*/ 21779, // Rule ID 1304 //
9247 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9248 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subuh_qb,
9249 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9250 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
9251 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
9252 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9253 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9254 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9255 : // (intrinsic_wo_chain:{ *:[v4i8] } 3620:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
9256 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_QB_MMR2,
9257 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9258 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9259 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9260 : GIR_EraseFromParent, /*InsnID*/0,
9261 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9262 : // GIR_Coverage, 1304,
9263 : GIR_Done,
9264 : // Label 636: @21779
9265 : GIM_Try, /*On fail goto*//*Label 637*/ 21831, // Rule ID 1305 //
9266 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9267 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subuh_r_qb,
9268 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9269 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
9270 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
9271 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9272 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
9273 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
9274 : // (intrinsic_wo_chain:{ *:[v4i8] } 3621:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
9275 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_R_QB_MMR2,
9276 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9277 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
9278 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
9279 : GIR_EraseFromParent, /*InsnID*/0,
9280 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9281 : // GIR_Coverage, 1305,
9282 : GIR_Done,
9283 : // Label 637: @21831
9284 : GIM_Try, /*On fail goto*//*Label 638*/ 21875, // Rule ID 1843 //
9285 : GIM_CheckFeatures, GIFBS_HasDSP,
9286 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_ph,
9287 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9288 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9289 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
9290 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9291 : // (intrinsic_wo_chain:{ *:[v2i16] } 2977:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
9292 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_PH,
9293 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9294 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
9295 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
9296 : GIR_EraseFromParent, /*InsnID*/0,
9297 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9298 : // GIR_Coverage, 1843,
9299 : GIR_Done,
9300 : // Label 638: @21875
9301 : GIM_Try, /*On fail goto*//*Label 639*/ 21919, // Rule ID 1845 //
9302 : GIM_CheckFeatures, GIFBS_HasDSP,
9303 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_ph,
9304 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9305 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
9306 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
9307 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9308 : // (intrinsic_wo_chain:{ *:[v2i16] } 3593:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
9309 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_PH,
9310 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9311 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
9312 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
9313 : GIR_EraseFromParent, /*InsnID*/0,
9314 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9315 : // GIR_Coverage, 1845,
9316 : GIR_Done,
9317 : // Label 639: @21919
9318 : GIM_Try, /*On fail goto*//*Label 640*/ 21963, // Rule ID 1849 //
9319 : GIM_CheckFeatures, GIFBS_HasDSP,
9320 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_qb,
9321 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9322 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
9323 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
9324 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9325 : // (intrinsic_wo_chain:{ *:[v4i8] } 2998:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
9326 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_QB,
9327 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9328 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
9329 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
9330 : GIR_EraseFromParent, /*InsnID*/0,
9331 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9332 : // GIR_Coverage, 1849,
9333 : GIR_Done,
9334 : // Label 640: @21963
9335 : GIM_Try, /*On fail goto*//*Label 641*/ 22007, // Rule ID 1851 //
9336 : GIM_CheckFeatures, GIFBS_HasDSP,
9337 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_qb,
9338 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
9339 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
9340 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
9341 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9342 : // (intrinsic_wo_chain:{ *:[v4i8] } 3617:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
9343 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_QB,
9344 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
9345 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
9346 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
9347 : GIR_EraseFromParent, /*InsnID*/0,
9348 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9349 : // GIR_Coverage, 1851,
9350 : GIR_Done,
9351 : // Label 641: @22007
9352 : GIM_Reject,
9353 : // Label 427: @22008
9354 : GIM_Try, /*On fail goto*//*Label 642*/ 25056,
9355 : GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
9356 : GIM_Try, /*On fail goto*//*Label 643*/ 22084, // Rule ID 449 //
9357 : GIM_CheckFeatures, GIFBS_HasDSPR2,
9358 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_sra_ph_w,
9359 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9360 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9361 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9362 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
9363 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9364 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9365 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9366 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
9367 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
9368 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
9369 : // MIs[1] Operand 1
9370 : // No operand predicates
9371 : GIM_CheckIsSafeToFold, /*InsnID*/1,
9372 : // (intrinsic_wo_chain:{ *:[v2i16] } 3499:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (PRECR_SRA_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
9373 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_PH_W,
9374 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
9375 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9376 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
9377 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
9378 : GIR_EraseFromParent, /*InsnID*/0,
9379 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9380 : // GIR_Coverage, 449,
9381 : GIR_Done,
9382 : // Label 643: @22084
9383 : GIM_Try, /*On fail goto*//*Label 644*/ 22155, // Rule ID 450 //
9384 : GIM_CheckFeatures, GIFBS_HasDSPR2,
9385 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_sra_r_ph_w,
9386 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9387 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9388 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9389 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
9390 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9391 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9392 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9393 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
9394 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
9395 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
9396 : // MIs[1] Operand 1
9397 : // No operand predicates
9398 : GIM_CheckIsSafeToFold, /*InsnID*/1,
9399 : // (intrinsic_wo_chain:{ *:[v2i16] } 3500:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (PRECR_SRA_R_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
9400 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_R_PH_W,
9401 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
9402 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9403 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
9404 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
9405 : GIR_EraseFromParent, /*InsnID*/0,
9406 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9407 : // GIR_Coverage, 450,
9408 : GIR_Done,
9409 : // Label 644: @22155
9410 : GIM_Try, /*On fail goto*//*Label 645*/ 22226, // Rule ID 455 //
9411 : GIM_CheckFeatures, GIFBS_HasDSPR2,
9412 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_append,
9413 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9414 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9415 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9416 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
9417 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9418 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9419 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9420 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
9421 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
9422 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
9423 : // MIs[1] Operand 1
9424 : // No operand predicates
9425 : GIM_CheckIsSafeToFold, /*InsnID*/1,
9426 : // (intrinsic_wo_chain:{ *:[i32] } 3014:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (APPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
9427 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::APPEND,
9428 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
9429 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9430 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
9431 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
9432 : GIR_EraseFromParent, /*InsnID*/0,
9433 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9434 : // GIR_Coverage, 455,
9435 : GIR_Done,
9436 : // Label 645: @22226
9437 : GIM_Try, /*On fail goto*//*Label 646*/ 22297, // Rule ID 456 //
9438 : GIM_CheckFeatures, GIFBS_HasDSPR2,
9439 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_balign,
9440 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9441 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9442 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9443 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
9444 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9445 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9446 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9447 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
9448 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
9449 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt2,
9450 : // MIs[1] Operand 1
9451 : // No operand predicates
9452 : GIM_CheckIsSafeToFold, /*InsnID*/1,
9453 : // (intrinsic_wo_chain:{ *:[i32] } 3039:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2>>:$sa) => (BALIGN:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
9454 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BALIGN,
9455 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
9456 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9457 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
9458 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
9459 : GIR_EraseFromParent, /*InsnID*/0,
9460 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9461 : // GIR_Coverage, 456,
9462 : GIR_Done,
9463 : // Label 646: @22297
9464 : GIM_Try, /*On fail goto*//*Label 647*/ 22368, // Rule ID 457 //
9465 : GIM_CheckFeatures, GIFBS_HasDSPR2,
9466 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_prepend,
9467 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9468 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9469 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9470 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
9471 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9472 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9473 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9474 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
9475 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
9476 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
9477 : // MIs[1] Operand 1
9478 : // No operand predicates
9479 : GIM_CheckIsSafeToFold, /*InsnID*/1,
9480 : // (intrinsic_wo_chain:{ *:[i32] } 3505:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (PREPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
9481 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PREPEND,
9482 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
9483 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9484 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
9485 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
9486 : GIR_EraseFromParent, /*InsnID*/0,
9487 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9488 : // GIR_Coverage, 457,
9489 : GIR_Done,
9490 : // Label 647: @22368
9491 : GIM_Try, /*On fail goto*//*Label 648*/ 22439, // Rule ID 921 //
9492 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9493 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sldi_b,
9494 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
9495 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
9496 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
9497 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
9498 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
9499 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
9500 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
9501 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
9502 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
9503 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
9504 : // MIs[1] Operand 1
9505 : // No operand predicates
9506 : GIM_CheckIsSafeToFold, /*InsnID*/1,
9507 : // (intrinsic_wo_chain:{ *:[v16i8] } 3537:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$n) => (SLDI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] }):$n)
9508 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_B,
9509 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9510 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
9511 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
9512 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // n
9513 : GIR_EraseFromParent, /*InsnID*/0,
9514 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9515 : // GIR_Coverage, 921,
9516 : GIR_Done,
9517 : // Label 648: @22439
9518 : GIM_Try, /*On fail goto*//*Label 649*/ 22510, // Rule ID 922 //
9519 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9520 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sldi_h,
9521 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
9522 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
9523 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
9524 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
9525 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
9526 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
9527 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
9528 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
9529 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
9530 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
9531 : // MIs[1] Operand 1
9532 : // No operand predicates
9533 : GIM_CheckIsSafeToFold, /*InsnID*/1,
9534 : // (intrinsic_wo_chain:{ *:[v8i16] } 3539:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$n) => (SLDI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] }):$n)
9535 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_H,
9536 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9537 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
9538 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
9539 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // n
9540 : GIR_EraseFromParent, /*InsnID*/0,
9541 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9542 : // GIR_Coverage, 922,
9543 : GIR_Done,
9544 : // Label 649: @22510
9545 : GIM_Try, /*On fail goto*//*Label 650*/ 22581, // Rule ID 923 //
9546 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9547 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sldi_w,
9548 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
9549 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
9550 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
9551 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
9552 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
9553 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
9554 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
9555 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
9556 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
9557 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt2,
9558 : // MIs[1] Operand 1
9559 : // No operand predicates
9560 : GIM_CheckIsSafeToFold, /*InsnID*/1,
9561 : // (intrinsic_wo_chain:{ *:[v4i32] } 3540:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt2>>:$n) => (SLDI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] }):$n)
9562 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_W,
9563 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9564 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
9565 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
9566 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // n
9567 : GIR_EraseFromParent, /*InsnID*/0,
9568 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9569 : // GIR_Coverage, 923,
9570 : GIR_Done,
9571 : // Label 650: @22581
9572 : GIM_Try, /*On fail goto*//*Label 651*/ 22652, // Rule ID 924 //
9573 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9574 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sldi_d,
9575 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
9576 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
9577 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
9578 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
9579 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
9580 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
9581 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
9582 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
9583 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
9584 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt1,
9585 : // MIs[1] Operand 1
9586 : // No operand predicates
9587 : GIM_CheckIsSafeToFold, /*InsnID*/1,
9588 : // (intrinsic_wo_chain:{ *:[v2i64] } 3538:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt1>>:$n) => (SLDI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] }):$n)
9589 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_D,
9590 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9591 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
9592 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
9593 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // n
9594 : GIR_EraseFromParent, /*InsnID*/0,
9595 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9596 : // GIR_Coverage, 924,
9597 : GIR_Done,
9598 : // Label 651: @22652
9599 : GIM_Try, /*On fail goto*//*Label 652*/ 22723, // Rule ID 1293 //
9600 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9601 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_balign,
9602 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9603 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9604 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9605 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
9606 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9607 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9608 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9609 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
9610 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
9611 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt2,
9612 : // MIs[1] Operand 1
9613 : // No operand predicates
9614 : GIM_CheckIsSafeToFold, /*InsnID*/1,
9615 : // (intrinsic_wo_chain:{ *:[i32] } 3039:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2>>:$bp) => (BALIGN_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$bp, GPR32Opnd:{ *:[i32] }:$src)
9616 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BALIGN_MMR2,
9617 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
9618 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9619 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // bp
9620 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
9621 : GIR_EraseFromParent, /*InsnID*/0,
9622 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9623 : // GIR_Coverage, 1293,
9624 : GIR_Done,
9625 : // Label 652: @22723
9626 : GIM_Try, /*On fail goto*//*Label 653*/ 22794, // Rule ID 1315 //
9627 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9628 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_sra_ph_w,
9629 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9630 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9631 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9632 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
9633 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9634 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9635 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9636 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
9637 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
9638 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
9639 : // MIs[1] Operand 1
9640 : // No operand predicates
9641 : GIM_CheckIsSafeToFold, /*InsnID*/1,
9642 : // (intrinsic_wo_chain:{ *:[v2i16] } 3499:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (PRECR_SRA_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
9643 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_PH_W_MMR2,
9644 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
9645 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9646 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
9647 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
9648 : GIR_EraseFromParent, /*InsnID*/0,
9649 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9650 : // GIR_Coverage, 1315,
9651 : GIR_Done,
9652 : // Label 653: @22794
9653 : GIM_Try, /*On fail goto*//*Label 654*/ 22865, // Rule ID 1316 //
9654 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9655 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_sra_r_ph_w,
9656 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
9657 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9658 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9659 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
9660 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
9661 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9662 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9663 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
9664 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
9665 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
9666 : // MIs[1] Operand 1
9667 : // No operand predicates
9668 : GIM_CheckIsSafeToFold, /*InsnID*/1,
9669 : // (intrinsic_wo_chain:{ *:[v2i16] } 3500:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (PRECR_SRA_R_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
9670 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_R_PH_W_MMR2,
9671 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
9672 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9673 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
9674 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
9675 : GIR_EraseFromParent, /*InsnID*/0,
9676 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9677 : // GIR_Coverage, 1316,
9678 : GIR_Done,
9679 : // Label 654: @22865
9680 : GIM_Try, /*On fail goto*//*Label 655*/ 22936, // Rule ID 1317 //
9681 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9682 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_prepend,
9683 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9684 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9685 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9686 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
9687 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9688 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9689 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9690 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
9691 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
9692 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
9693 : // MIs[1] Operand 1
9694 : // No operand predicates
9695 : GIM_CheckIsSafeToFold, /*InsnID*/1,
9696 : // (intrinsic_wo_chain:{ *:[i32] } 3505:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (PREPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
9697 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PREPEND_MMR2,
9698 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
9699 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9700 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
9701 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
9702 : GIR_EraseFromParent, /*InsnID*/0,
9703 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9704 : // GIR_Coverage, 1317,
9705 : GIR_Done,
9706 : // Label 655: @22936
9707 : GIM_Try, /*On fail goto*//*Label 656*/ 23007, // Rule ID 1318 //
9708 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
9709 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_append,
9710 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
9711 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
9712 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
9713 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
9714 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
9715 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
9716 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
9717 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
9718 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
9719 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
9720 : // MIs[1] Operand 1
9721 : // No operand predicates
9722 : GIM_CheckIsSafeToFold, /*InsnID*/1,
9723 : // (intrinsic_wo_chain:{ *:[i32] } 3014:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (APPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
9724 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::APPEND_MMR2,
9725 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
9726 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
9727 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
9728 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
9729 : GIR_EraseFromParent, /*InsnID*/0,
9730 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9731 : // GIR_Coverage, 1318,
9732 : GIR_Done,
9733 : // Label 656: @23007
9734 : GIM_Try, /*On fail goto*//*Label 657*/ 23071, // Rule ID 520 //
9735 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9736 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsl_b,
9737 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
9738 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
9739 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
9740 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
9741 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
9742 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
9743 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
9744 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID,
9745 : // (intrinsic_wo_chain:{ *:[v16i8] } 3048:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (BINSL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9746 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_B,
9747 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9748 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
9749 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
9750 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
9751 : GIR_EraseFromParent, /*InsnID*/0,
9752 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9753 : // GIR_Coverage, 520,
9754 : GIR_Done,
9755 : // Label 657: @23071
9756 : GIM_Try, /*On fail goto*//*Label 658*/ 23135, // Rule ID 521 //
9757 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9758 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsl_h,
9759 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
9760 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
9761 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
9762 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
9763 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
9764 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
9765 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
9766 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
9767 : // (intrinsic_wo_chain:{ *:[v8i16] } 3050:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (BINSL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9768 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_H,
9769 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9770 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
9771 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
9772 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
9773 : GIR_EraseFromParent, /*InsnID*/0,
9774 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9775 : // GIR_Coverage, 521,
9776 : GIR_Done,
9777 : // Label 658: @23135
9778 : GIM_Try, /*On fail goto*//*Label 659*/ 23199, // Rule ID 522 //
9779 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9780 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsl_w,
9781 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
9782 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
9783 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
9784 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
9785 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
9786 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
9787 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
9788 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
9789 : // (intrinsic_wo_chain:{ *:[v4i32] } 3051:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (BINSL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9790 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_W,
9791 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9792 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
9793 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
9794 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
9795 : GIR_EraseFromParent, /*InsnID*/0,
9796 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9797 : // GIR_Coverage, 522,
9798 : GIR_Done,
9799 : // Label 659: @23199
9800 : GIM_Try, /*On fail goto*//*Label 660*/ 23263, // Rule ID 523 //
9801 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9802 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsl_d,
9803 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
9804 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
9805 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
9806 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64,
9807 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
9808 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
9809 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
9810 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128DRegClassID,
9811 : // (intrinsic_wo_chain:{ *:[v2i64] } 3049:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (BINSL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9812 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_D,
9813 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9814 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
9815 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
9816 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
9817 : GIR_EraseFromParent, /*InsnID*/0,
9818 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9819 : // GIR_Coverage, 523,
9820 : GIR_Done,
9821 : // Label 660: @23263
9822 : GIM_Try, /*On fail goto*//*Label 661*/ 23327, // Rule ID 528 //
9823 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9824 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsr_b,
9825 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
9826 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
9827 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
9828 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
9829 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
9830 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
9831 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
9832 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID,
9833 : // (intrinsic_wo_chain:{ *:[v16i8] } 3056:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (BINSR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9834 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_B,
9835 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9836 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
9837 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
9838 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
9839 : GIR_EraseFromParent, /*InsnID*/0,
9840 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9841 : // GIR_Coverage, 528,
9842 : GIR_Done,
9843 : // Label 661: @23327
9844 : GIM_Try, /*On fail goto*//*Label 662*/ 23391, // Rule ID 529 //
9845 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9846 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsr_h,
9847 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
9848 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
9849 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
9850 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
9851 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
9852 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
9853 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
9854 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
9855 : // (intrinsic_wo_chain:{ *:[v8i16] } 3058:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (BINSR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9856 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_H,
9857 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9858 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
9859 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
9860 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
9861 : GIR_EraseFromParent, /*InsnID*/0,
9862 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9863 : // GIR_Coverage, 529,
9864 : GIR_Done,
9865 : // Label 662: @23391
9866 : GIM_Try, /*On fail goto*//*Label 663*/ 23455, // Rule ID 530 //
9867 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9868 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsr_w,
9869 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
9870 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
9871 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
9872 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
9873 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
9874 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
9875 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
9876 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
9877 : // (intrinsic_wo_chain:{ *:[v4i32] } 3059:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (BINSR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9878 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_W,
9879 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9880 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
9881 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
9882 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
9883 : GIR_EraseFromParent, /*InsnID*/0,
9884 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9885 : // GIR_Coverage, 530,
9886 : GIR_Done,
9887 : // Label 663: @23455
9888 : GIM_Try, /*On fail goto*//*Label 664*/ 23519, // Rule ID 531 //
9889 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9890 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsr_d,
9891 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
9892 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
9893 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
9894 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64,
9895 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
9896 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
9897 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
9898 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128DRegClassID,
9899 : // (intrinsic_wo_chain:{ *:[v2i64] } 3057:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (BINSR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9900 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_D,
9901 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9902 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
9903 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
9904 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
9905 : GIR_EraseFromParent, /*InsnID*/0,
9906 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9907 : // GIR_Coverage, 531,
9908 : GIR_Done,
9909 : // Label 664: @23519
9910 : GIM_Try, /*On fail goto*//*Label 665*/ 23583, // Rule ID 626 //
9911 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9912 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_s_h,
9913 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
9914 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
9915 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
9916 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
9917 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
9918 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
9919 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
9920 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID,
9921 : // (intrinsic_wo_chain:{ *:[v8i16] } 3177:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPADD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9922 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_S_H,
9923 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9924 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
9925 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
9926 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
9927 : GIR_EraseFromParent, /*InsnID*/0,
9928 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9929 : // GIR_Coverage, 626,
9930 : GIR_Done,
9931 : // Label 665: @23583
9932 : GIM_Try, /*On fail goto*//*Label 666*/ 23647, // Rule ID 627 //
9933 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9934 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_s_w,
9935 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
9936 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
9937 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
9938 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
9939 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
9940 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
9941 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
9942 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
9943 : // (intrinsic_wo_chain:{ *:[v4i32] } 3178:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPADD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9944 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_S_W,
9945 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9946 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
9947 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
9948 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
9949 : GIR_EraseFromParent, /*InsnID*/0,
9950 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9951 : // GIR_Coverage, 627,
9952 : GIR_Done,
9953 : // Label 666: @23647
9954 : GIM_Try, /*On fail goto*//*Label 667*/ 23711, // Rule ID 628 //
9955 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9956 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_s_d,
9957 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
9958 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
9959 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
9960 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
9961 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
9962 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
9963 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
9964 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
9965 : // (intrinsic_wo_chain:{ *:[v2i64] } 3176:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPADD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9966 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_S_D,
9967 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9968 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
9969 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
9970 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
9971 : GIR_EraseFromParent, /*InsnID*/0,
9972 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9973 : // GIR_Coverage, 628,
9974 : GIR_Done,
9975 : // Label 667: @23711
9976 : GIM_Try, /*On fail goto*//*Label 668*/ 23775, // Rule ID 629 //
9977 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
9978 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_u_h,
9979 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
9980 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
9981 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
9982 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
9983 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
9984 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
9985 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
9986 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID,
9987 : // (intrinsic_wo_chain:{ *:[v8i16] } 3180:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPADD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9988 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_U_H,
9989 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
9990 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
9991 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
9992 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
9993 : GIR_EraseFromParent, /*InsnID*/0,
9994 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9995 : // GIR_Coverage, 629,
9996 : GIR_Done,
9997 : // Label 668: @23775
9998 : GIM_Try, /*On fail goto*//*Label 669*/ 23839, // Rule ID 630 //
9999 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10000 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_u_w,
10001 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10002 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10003 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
10004 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
10005 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
10006 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
10007 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
10008 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
10009 : // (intrinsic_wo_chain:{ *:[v4i32] } 3181:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPADD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10010 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_U_W,
10011 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10012 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10013 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10014 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10015 : GIR_EraseFromParent, /*InsnID*/0,
10016 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10017 : // GIR_Coverage, 630,
10018 : GIR_Done,
10019 : // Label 669: @23839
10020 : GIM_Try, /*On fail goto*//*Label 670*/ 23903, // Rule ID 631 //
10021 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10022 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_u_d,
10023 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
10024 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
10025 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10026 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
10027 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
10028 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
10029 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
10030 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
10031 : // (intrinsic_wo_chain:{ *:[v2i64] } 3179:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPADD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10032 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_U_D,
10033 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10034 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10035 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10036 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10037 : GIR_EraseFromParent, /*InsnID*/0,
10038 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10039 : // GIR_Coverage, 631,
10040 : GIR_Done,
10041 : // Label 670: @23903
10042 : GIM_Try, /*On fail goto*//*Label 671*/ 23967, // Rule ID 632 //
10043 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10044 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_s_h,
10045 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10046 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10047 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
10048 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
10049 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
10050 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
10051 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
10052 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID,
10053 : // (intrinsic_wo_chain:{ *:[v8i16] } 3197:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPSUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10054 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_S_H,
10055 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10056 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10057 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10058 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10059 : GIR_EraseFromParent, /*InsnID*/0,
10060 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10061 : // GIR_Coverage, 632,
10062 : GIR_Done,
10063 : // Label 671: @23967
10064 : GIM_Try, /*On fail goto*//*Label 672*/ 24031, // Rule ID 633 //
10065 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10066 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_s_w,
10067 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10068 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10069 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
10070 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
10071 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
10072 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
10073 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
10074 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
10075 : // (intrinsic_wo_chain:{ *:[v4i32] } 3198:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPSUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10076 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_S_W,
10077 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10078 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10079 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10080 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10081 : GIR_EraseFromParent, /*InsnID*/0,
10082 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10083 : // GIR_Coverage, 633,
10084 : GIR_Done,
10085 : // Label 672: @24031
10086 : GIM_Try, /*On fail goto*//*Label 673*/ 24095, // Rule ID 634 //
10087 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10088 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_s_d,
10089 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
10090 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
10091 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10092 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
10093 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
10094 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
10095 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
10096 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
10097 : // (intrinsic_wo_chain:{ *:[v2i64] } 3196:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPSUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10098 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_S_D,
10099 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10100 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10101 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10102 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10103 : GIR_EraseFromParent, /*InsnID*/0,
10104 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10105 : // GIR_Coverage, 634,
10106 : GIR_Done,
10107 : // Label 673: @24095
10108 : GIM_Try, /*On fail goto*//*Label 674*/ 24159, // Rule ID 635 //
10109 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10110 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_u_h,
10111 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10112 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10113 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
10114 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
10115 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
10116 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
10117 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
10118 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID,
10119 : // (intrinsic_wo_chain:{ *:[v8i16] } 3200:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPSUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10120 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_U_H,
10121 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10122 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10123 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10124 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10125 : GIR_EraseFromParent, /*InsnID*/0,
10126 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10127 : // GIR_Coverage, 635,
10128 : GIR_Done,
10129 : // Label 674: @24159
10130 : GIM_Try, /*On fail goto*//*Label 675*/ 24223, // Rule ID 636 //
10131 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10132 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_u_w,
10133 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10134 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10135 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
10136 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
10137 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
10138 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
10139 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
10140 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
10141 : // (intrinsic_wo_chain:{ *:[v4i32] } 3201:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPSUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10142 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_U_W,
10143 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10144 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10145 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10146 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10147 : GIR_EraseFromParent, /*InsnID*/0,
10148 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10149 : // GIR_Coverage, 636,
10150 : GIR_Done,
10151 : // Label 675: @24223
10152 : GIM_Try, /*On fail goto*//*Label 676*/ 24287, // Rule ID 637 //
10153 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10154 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_u_d,
10155 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
10156 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
10157 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10158 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
10159 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
10160 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
10161 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
10162 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
10163 : // (intrinsic_wo_chain:{ *:[v2i64] } 3199:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPSUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10164 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_U_D,
10165 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10166 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10167 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10168 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10169 : GIR_EraseFromParent, /*InsnID*/0,
10170 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10171 : // GIR_Coverage, 637,
10172 : GIR_Done,
10173 : // Label 676: @24287
10174 : GIM_Try, /*On fail goto*//*Label 677*/ 24351, // Rule ID 804 //
10175 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10176 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_madd_q_h,
10177 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10178 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10179 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
10180 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
10181 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
10182 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
10183 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
10184 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
10185 : // (intrinsic_wo_chain:{ *:[v8i16] } 3365:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MADD_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10186 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_Q_H,
10187 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10188 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10189 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10190 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10191 : GIR_EraseFromParent, /*InsnID*/0,
10192 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10193 : // GIR_Coverage, 804,
10194 : GIR_Done,
10195 : // Label 677: @24351
10196 : GIM_Try, /*On fail goto*//*Label 678*/ 24415, // Rule ID 805 //
10197 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10198 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_madd_q_w,
10199 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10200 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10201 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10202 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
10203 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
10204 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
10205 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
10206 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
10207 : // (intrinsic_wo_chain:{ *:[v4i32] } 3366:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MADD_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10208 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_Q_W,
10209 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10210 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10211 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10212 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10213 : GIR_EraseFromParent, /*InsnID*/0,
10214 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10215 : // GIR_Coverage, 805,
10216 : GIR_Done,
10217 : // Label 678: @24415
10218 : GIM_Try, /*On fail goto*//*Label 679*/ 24479, // Rule ID 806 //
10219 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10220 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_maddr_q_h,
10221 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10222 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10223 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
10224 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
10225 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
10226 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
10227 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
10228 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
10229 : // (intrinsic_wo_chain:{ *:[v8i16] } 3367:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MADDR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10230 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDR_Q_H,
10231 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10232 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10233 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10234 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10235 : GIR_EraseFromParent, /*InsnID*/0,
10236 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10237 : // GIR_Coverage, 806,
10238 : GIR_Done,
10239 : // Label 679: @24479
10240 : GIM_Try, /*On fail goto*//*Label 680*/ 24543, // Rule ID 807 //
10241 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10242 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_maddr_q_w,
10243 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10244 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10245 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10246 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
10247 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
10248 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
10249 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
10250 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
10251 : // (intrinsic_wo_chain:{ *:[v4i32] } 3368:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MADDR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10252 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDR_Q_W,
10253 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10254 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10255 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10256 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10257 : GIR_EraseFromParent, /*InsnID*/0,
10258 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10259 : // GIR_Coverage, 807,
10260 : GIR_Done,
10261 : // Label 680: @24543
10262 : GIM_Try, /*On fail goto*//*Label 681*/ 24607, // Rule ID 860 //
10263 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10264 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_msub_q_h,
10265 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10266 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10267 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
10268 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
10269 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
10270 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
10271 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
10272 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
10273 : // (intrinsic_wo_chain:{ *:[v8i16] } 3429:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MSUB_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10274 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_Q_H,
10275 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10276 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10277 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10278 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10279 : GIR_EraseFromParent, /*InsnID*/0,
10280 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10281 : // GIR_Coverage, 860,
10282 : GIR_Done,
10283 : // Label 681: @24607
10284 : GIM_Try, /*On fail goto*//*Label 682*/ 24671, // Rule ID 861 //
10285 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10286 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_msub_q_w,
10287 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10288 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10289 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10290 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
10291 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
10292 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
10293 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
10294 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
10295 : // (intrinsic_wo_chain:{ *:[v4i32] } 3430:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MSUB_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10296 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_Q_W,
10297 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10298 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10299 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10300 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10301 : GIR_EraseFromParent, /*InsnID*/0,
10302 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10303 : // GIR_Coverage, 861,
10304 : GIR_Done,
10305 : // Label 682: @24671
10306 : GIM_Try, /*On fail goto*//*Label 683*/ 24735, // Rule ID 862 //
10307 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10308 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_msubr_q_h,
10309 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10310 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10311 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
10312 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
10313 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
10314 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
10315 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
10316 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
10317 : // (intrinsic_wo_chain:{ *:[v8i16] } 3431:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MSUBR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10318 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBR_Q_H,
10319 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10320 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10321 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10322 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10323 : GIR_EraseFromParent, /*InsnID*/0,
10324 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10325 : // GIR_Coverage, 862,
10326 : GIR_Done,
10327 : // Label 683: @24735
10328 : GIM_Try, /*On fail goto*//*Label 684*/ 24799, // Rule ID 863 //
10329 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10330 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_msubr_q_w,
10331 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10332 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10333 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10334 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
10335 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
10336 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
10337 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
10338 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
10339 : // (intrinsic_wo_chain:{ *:[v4i32] } 3432:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MSUBR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10340 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBR_Q_W,
10341 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10342 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10343 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10344 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
10345 : GIR_EraseFromParent, /*InsnID*/0,
10346 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10347 : // GIR_Coverage, 863,
10348 : GIR_Done,
10349 : // Label 684: @24799
10350 : GIM_Try, /*On fail goto*//*Label 685*/ 24863, // Rule ID 917 //
10351 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10352 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sld_b,
10353 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
10354 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
10355 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
10356 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
10357 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
10358 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
10359 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
10360 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::GPR32RegClassID,
10361 : // (intrinsic_wo_chain:{ *:[v16i8] } 3533:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
10362 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_B,
10363 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10364 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10365 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10366 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rt
10367 : GIR_EraseFromParent, /*InsnID*/0,
10368 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10369 : // GIR_Coverage, 917,
10370 : GIR_Done,
10371 : // Label 685: @24863
10372 : GIM_Try, /*On fail goto*//*Label 686*/ 24927, // Rule ID 918 //
10373 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10374 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sld_h,
10375 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10376 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10377 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
10378 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
10379 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
10380 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
10381 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
10382 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::GPR32RegClassID,
10383 : // (intrinsic_wo_chain:{ *:[v8i16] } 3535:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
10384 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_H,
10385 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10386 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10387 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10388 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rt
10389 : GIR_EraseFromParent, /*InsnID*/0,
10390 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10391 : // GIR_Coverage, 918,
10392 : GIR_Done,
10393 : // Label 686: @24927
10394 : GIM_Try, /*On fail goto*//*Label 687*/ 24991, // Rule ID 919 //
10395 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10396 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sld_w,
10397 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10398 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10399 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10400 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
10401 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
10402 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
10403 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
10404 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::GPR32RegClassID,
10405 : // (intrinsic_wo_chain:{ *:[v4i32] } 3536:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
10406 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_W,
10407 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10408 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10409 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10410 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rt
10411 : GIR_EraseFromParent, /*InsnID*/0,
10412 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10413 : // GIR_Coverage, 919,
10414 : GIR_Done,
10415 : // Label 687: @24991
10416 : GIM_Try, /*On fail goto*//*Label 688*/ 25055, // Rule ID 920 //
10417 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
10418 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sld_d,
10419 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
10420 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
10421 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
10422 : GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
10423 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
10424 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
10425 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
10426 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::GPR32RegClassID,
10427 : // (intrinsic_wo_chain:{ *:[v2i64] } 3534:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
10428 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_D,
10429 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
10430 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
10431 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
10432 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rt
10433 : GIR_EraseFromParent, /*InsnID*/0,
10434 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10435 : // GIR_Coverage, 920,
10436 : GIR_Done,
10437 : // Label 688: @25055
10438 : GIM_Reject,
10439 : // Label 642: @25056
10440 : GIM_Reject,
10441 : // Label 15: @25057
10442 : GIM_Try, /*On fail goto*//*Label 689*/ 25090, // Rule ID 326 //
10443 : GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
10444 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_bposge32,
10445 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
10446 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
10447 : // (intrinsic_w_chain:{ *:[i32] } 3082:{ *:[iPTR] }) => (BPOSGE32_PSEUDO:{ *:[i32] })
10448 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BPOSGE32_PSEUDO,
10449 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10450 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10451 : GIR_EraseFromParent, /*InsnID*/0,
10452 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10453 : // GIR_Coverage, 326,
10454 : GIR_Done,
10455 : // Label 689: @25090
10456 : GIM_Try, /*On fail goto*//*Label 690*/ 25992,
10457 : GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
10458 : GIM_Try, /*On fail goto*//*Label 691*/ 25147, // Rule ID 413 //
10459 : GIM_CheckFeatures, GIFBS_HasDSP,
10460 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_rddsp,
10461 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
10462 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
10463 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
10464 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
10465 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
10466 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt10,
10467 : // MIs[1] Operand 1
10468 : // No operand predicates
10469 : GIM_CheckIsSafeToFold, /*InsnID*/1,
10470 : // (intrinsic_w_chain:{ *:[i32] } 3507:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt10>>:$mask) => (RDDSP:{ *:[i32] } (imm:{ *:[i32] }):$mask)
10471 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RDDSP,
10472 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
10473 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // mask
10474 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
10475 : GIR_EraseFromParent, /*InsnID*/0,
10476 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10477 : // GIR_Coverage, 413,
10478 : GIR_Done,
10479 : // Label 691: @25147
10480 : GIM_Try, /*On fail goto*//*Label 692*/ 25199, // Rule ID 414 //
10481 : GIM_CheckFeatures, GIFBS_HasDSP_NotInMicroMips,
10482 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_wrdsp,
10483 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
10484 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
10485 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
10486 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
10487 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
10488 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt10,
10489 : // MIs[1] Operand 1
10490 : // No operand predicates
10491 : GIM_CheckIsSafeToFold, /*InsnID*/1,
10492 : // (intrinsic_void 3634:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt10>>:$mask) => (WRDSP GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$mask)
10493 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::WRDSP,
10494 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
10495 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // mask
10496 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
10497 : GIR_EraseFromParent, /*InsnID*/0,
10498 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10499 : // GIR_Coverage, 414,
10500 : GIR_Done,
10501 : // Label 692: @25199
10502 : GIM_Try, /*On fail goto*//*Label 693*/ 25243, // Rule ID 335 //
10503 : GIM_CheckFeatures, GIFBS_HasDSP,
10504 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_ph,
10505 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
10506 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
10507 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
10508 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10509 : // (intrinsic_w_chain:{ *:[v2i16] } 2970:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (ABSQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt)
10510 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_PH,
10511 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
10512 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10513 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10514 : GIR_EraseFromParent, /*InsnID*/0,
10515 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10516 : // GIR_Coverage, 335,
10517 : GIR_Done,
10518 : // Label 693: @25243
10519 : GIM_Try, /*On fail goto*//*Label 694*/ 25287, // Rule ID 336 //
10520 : GIM_CheckFeatures, GIFBS_HasDSP,
10521 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_w,
10522 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
10523 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
10524 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
10525 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
10526 : // (intrinsic_w_chain:{ *:[i32] } 2972:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (ABSQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
10527 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_W,
10528 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
10529 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10530 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10531 : GIR_EraseFromParent, /*InsnID*/0,
10532 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10533 : // GIR_Coverage, 336,
10534 : GIR_Done,
10535 : // Label 694: @25287
10536 : GIM_Try, /*On fail goto*//*Label 695*/ 25331, // Rule ID 422 //
10537 : GIM_CheckFeatures, GIFBS_HasDSPR2,
10538 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_qb,
10539 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
10540 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
10541 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
10542 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10543 : // (intrinsic_w_chain:{ *:[v4i8] } 2971:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (ABSQ_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt)
10544 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_QB,
10545 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
10546 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10547 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10548 : GIR_EraseFromParent, /*InsnID*/0,
10549 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10550 : // GIR_Coverage, 422,
10551 : GIR_Done,
10552 : // Label 695: @25331
10553 : GIM_Try, /*On fail goto*//*Label 696*/ 25375, // Rule ID 1196 //
10554 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
10555 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_ph,
10556 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
10557 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
10558 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
10559 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10560 : // (intrinsic_w_chain:{ *:[v2i16] } 2970:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (ABSQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs)
10561 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_PH_MM,
10562 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
10563 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
10564 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10565 : GIR_EraseFromParent, /*InsnID*/0,
10566 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10567 : // GIR_Coverage, 1196,
10568 : GIR_Done,
10569 : // Label 696: @25375
10570 : GIM_Try, /*On fail goto*//*Label 697*/ 25419, // Rule ID 1197 //
10571 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
10572 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_w,
10573 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
10574 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
10575 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
10576 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
10577 : // (intrinsic_w_chain:{ *:[i32] } 2972:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (ABSQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
10578 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_W_MM,
10579 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
10580 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
10581 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10582 : GIR_EraseFromParent, /*InsnID*/0,
10583 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10584 : // GIR_Coverage, 1197,
10585 : GIR_Done,
10586 : // Label 697: @25419
10587 : GIM_Try, /*On fail goto*//*Label 698*/ 25463, // Rule ID 1277 //
10588 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
10589 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_qb,
10590 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
10591 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
10592 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
10593 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10594 : // (intrinsic_w_chain:{ *:[v4i8] } 2971:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (ABSQ_S_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs)
10595 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_QB_MMR2,
10596 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
10597 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
10598 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10599 : GIR_EraseFromParent, /*InsnID*/0,
10600 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10601 : // GIR_Coverage, 1277,
10602 : GIR_Done,
10603 : // Label 698: @25463
10604 : GIM_Try, /*On fail goto*//*Label 699*/ 25507, // Rule ID 389 //
10605 : GIM_CheckFeatures, GIFBS_HasDSP,
10606 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_eq_qb,
10607 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
10608 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
10609 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
10610 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10611 : // (intrinsic_void 3148:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_EQ_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
10612 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_EQ_QB,
10613 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
10614 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10615 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10616 : GIR_EraseFromParent, /*InsnID*/0,
10617 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10618 : // GIR_Coverage, 389,
10619 : GIR_Done,
10620 : // Label 699: @25507
10621 : GIM_Try, /*On fail goto*//*Label 700*/ 25551, // Rule ID 390 //
10622 : GIM_CheckFeatures, GIFBS_HasDSP,
10623 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_lt_qb,
10624 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
10625 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
10626 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
10627 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10628 : // (intrinsic_void 3150:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LT_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
10629 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LT_QB,
10630 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
10631 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10632 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10633 : GIR_EraseFromParent, /*InsnID*/0,
10634 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10635 : // GIR_Coverage, 390,
10636 : GIR_Done,
10637 : // Label 700: @25551
10638 : GIM_Try, /*On fail goto*//*Label 701*/ 25595, // Rule ID 391 //
10639 : GIM_CheckFeatures, GIFBS_HasDSP,
10640 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_le_qb,
10641 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
10642 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
10643 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
10644 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10645 : // (intrinsic_void 3149:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LE_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
10646 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LE_QB,
10647 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
10648 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10649 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10650 : GIR_EraseFromParent, /*InsnID*/0,
10651 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10652 : // GIR_Coverage, 391,
10653 : GIR_Done,
10654 : // Label 701: @25595
10655 : GIM_Try, /*On fail goto*//*Label 702*/ 25639, // Rule ID 395 //
10656 : GIM_CheckFeatures, GIFBS_HasDSP,
10657 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_eq_ph,
10658 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
10659 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
10660 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
10661 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10662 : // (intrinsic_void 3139:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_EQ_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
10663 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_PH,
10664 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
10665 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10666 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10667 : GIR_EraseFromParent, /*InsnID*/0,
10668 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10669 : // GIR_Coverage, 395,
10670 : GIR_Done,
10671 : // Label 702: @25639
10672 : GIM_Try, /*On fail goto*//*Label 703*/ 25683, // Rule ID 396 //
10673 : GIM_CheckFeatures, GIFBS_HasDSP,
10674 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_lt_ph,
10675 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
10676 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
10677 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
10678 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10679 : // (intrinsic_void 3141:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LT_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
10680 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_PH,
10681 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
10682 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10683 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10684 : GIR_EraseFromParent, /*InsnID*/0,
10685 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10686 : // GIR_Coverage, 396,
10687 : GIR_Done,
10688 : // Label 703: @25683
10689 : GIM_Try, /*On fail goto*//*Label 704*/ 25727, // Rule ID 397 //
10690 : GIM_CheckFeatures, GIFBS_HasDSP,
10691 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_le_ph,
10692 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
10693 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
10694 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
10695 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10696 : // (intrinsic_void 3140:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LE_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
10697 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_PH,
10698 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
10699 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10700 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10701 : GIR_EraseFromParent, /*InsnID*/0,
10702 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10703 : // GIR_Coverage, 397,
10704 : GIR_Done,
10705 : // Label 704: @25727
10706 : GIM_Try, /*On fail goto*//*Label 705*/ 25771, // Rule ID 1268 //
10707 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
10708 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_eq_ph,
10709 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
10710 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
10711 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
10712 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10713 : // (intrinsic_void 3139:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_EQ_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
10714 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_PH_MM,
10715 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
10716 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10717 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10718 : GIR_EraseFromParent, /*InsnID*/0,
10719 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10720 : // GIR_Coverage, 1268,
10721 : GIR_Done,
10722 : // Label 705: @25771
10723 : GIM_Try, /*On fail goto*//*Label 706*/ 25815, // Rule ID 1269 //
10724 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
10725 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_lt_ph,
10726 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
10727 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
10728 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
10729 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10730 : // (intrinsic_void 3141:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LT_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
10731 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_PH_MM,
10732 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
10733 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10734 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10735 : GIR_EraseFromParent, /*InsnID*/0,
10736 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10737 : // GIR_Coverage, 1269,
10738 : GIR_Done,
10739 : // Label 706: @25815
10740 : GIM_Try, /*On fail goto*//*Label 707*/ 25859, // Rule ID 1270 //
10741 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
10742 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_le_ph,
10743 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
10744 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
10745 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
10746 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10747 : // (intrinsic_void 3140:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LE_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
10748 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_PH_MM,
10749 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
10750 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10751 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10752 : GIR_EraseFromParent, /*InsnID*/0,
10753 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10754 : // GIR_Coverage, 1270,
10755 : GIR_Done,
10756 : // Label 707: @25859
10757 : GIM_Try, /*On fail goto*//*Label 708*/ 25903, // Rule ID 1274 //
10758 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
10759 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_eq_qb,
10760 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
10761 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
10762 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
10763 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10764 : // (intrinsic_void 3148:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_EQ_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
10765 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_EQ_QB_MM,
10766 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
10767 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10768 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10769 : GIR_EraseFromParent, /*InsnID*/0,
10770 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10771 : // GIR_Coverage, 1274,
10772 : GIR_Done,
10773 : // Label 708: @25903
10774 : GIM_Try, /*On fail goto*//*Label 709*/ 25947, // Rule ID 1275 //
10775 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
10776 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_lt_qb,
10777 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
10778 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
10779 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
10780 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10781 : // (intrinsic_void 3150:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LT_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
10782 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LT_QB_MM,
10783 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
10784 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10785 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10786 : GIR_EraseFromParent, /*InsnID*/0,
10787 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10788 : // GIR_Coverage, 1275,
10789 : GIR_Done,
10790 : // Label 709: @25947
10791 : GIM_Try, /*On fail goto*//*Label 710*/ 25991, // Rule ID 1276 //
10792 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
10793 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_le_qb,
10794 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
10795 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
10796 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
10797 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10798 : // (intrinsic_void 3149:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LE_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
10799 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LE_QB_MM,
10800 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
10801 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10802 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10803 : GIR_EraseFromParent, /*InsnID*/0,
10804 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10805 : // GIR_Coverage, 1276,
10806 : GIR_Done,
10807 : // Label 710: @25991
10808 : GIM_Reject,
10809 : // Label 690: @25992
10810 : GIM_Try, /*On fail goto*//*Label 711*/ 29980,
10811 : GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
10812 : GIM_Try, /*On fail goto*//*Label 712*/ 26061, // Rule ID 354 //
10813 : GIM_CheckFeatures, GIFBS_HasDSP,
10814 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_ph,
10815 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
10816 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
10817 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
10818 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
10819 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10820 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
10821 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
10822 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
10823 : // MIs[1] Operand 1
10824 : // No operand predicates
10825 : GIM_CheckIsSafeToFold, /*InsnID*/1,
10826 : // (intrinsic_w_chain:{ *:[v2i16] } 3524:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$rs_sa) => (SHLL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa)
10827 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_PH,
10828 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
10829 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10830 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
10831 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
10832 : GIR_EraseFromParent, /*InsnID*/0,
10833 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10834 : // GIR_Coverage, 354,
10835 : GIR_Done,
10836 : // Label 712: @26061
10837 : GIM_Try, /*On fail goto*//*Label 713*/ 26125, // Rule ID 359 //
10838 : GIM_CheckFeatures, GIFBS_HasDSP,
10839 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_w,
10840 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
10841 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
10842 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
10843 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
10844 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
10845 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
10846 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
10847 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
10848 : // MIs[1] Operand 1
10849 : // No operand predicates
10850 : GIM_CheckIsSafeToFold, /*InsnID*/1,
10851 : // (intrinsic_w_chain:{ *:[i32] } 3525:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$rs_sa) => (SHLL_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa)
10852 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_W,
10853 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
10854 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
10855 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
10856 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
10857 : GIR_EraseFromParent, /*InsnID*/0,
10858 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10859 : // GIR_Coverage, 359,
10860 : GIR_Done,
10861 : // Label 713: @26125
10862 : GIM_Try, /*On fail goto*//*Label 714*/ 26189, // Rule ID 1205 //
10863 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
10864 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_ph,
10865 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
10866 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
10867 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
10868 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
10869 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
10870 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
10871 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
10872 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
10873 : // MIs[1] Operand 1
10874 : // No operand predicates
10875 : GIM_CheckIsSafeToFold, /*InsnID*/1,
10876 : // (intrinsic_w_chain:{ *:[v2i16] } 3524:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$sa) => (SHLL_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa)
10877 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_PH_MM,
10878 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
10879 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
10880 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
10881 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
10882 : GIR_EraseFromParent, /*InsnID*/0,
10883 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10884 : // GIR_Coverage, 1205,
10885 : GIR_Done,
10886 : // Label 714: @26189
10887 : GIM_Try, /*On fail goto*//*Label 715*/ 26253, // Rule ID 1210 //
10888 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
10889 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_w,
10890 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
10891 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
10892 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
10893 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
10894 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
10895 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
10896 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
10897 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
10898 : // MIs[1] Operand 1
10899 : // No operand predicates
10900 : GIM_CheckIsSafeToFold, /*InsnID*/1,
10901 : // (intrinsic_w_chain:{ *:[i32] } 3525:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (SHLL_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa)
10902 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_W_MM,
10903 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
10904 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
10905 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
10906 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
10907 : GIR_EraseFromParent, /*InsnID*/0,
10908 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10909 : // GIR_Coverage, 1210,
10910 : GIR_Done,
10911 : // Label 715: @26253
10912 : GIM_Try, /*On fail goto*//*Label 716*/ 26308, // Rule ID 1860 //
10913 : GIM_CheckFeatures, GIFBS_HasDSP,
10914 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_ph,
10915 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
10916 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
10917 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
10918 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
10919 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
10920 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
10921 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
10922 : // MIs[1] Operand 1
10923 : // No operand predicates
10924 : GIM_CheckIsSafeToFold, /*InsnID*/1,
10925 : // (intrinsic_w_chain:{ *:[v2i16] } 3522:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHLL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
10926 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_PH,
10927 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
10928 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
10929 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
10930 : GIR_EraseFromParent, /*InsnID*/0,
10931 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10932 : // GIR_Coverage, 1860,
10933 : GIR_Done,
10934 : // Label 716: @26308
10935 : GIM_Try, /*On fail goto*//*Label 717*/ 26363, // Rule ID 1866 //
10936 : GIM_CheckFeatures, GIFBS_HasDSP,
10937 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_qb,
10938 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
10939 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
10940 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
10941 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
10942 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
10943 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
10944 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
10945 : // MIs[1] Operand 1
10946 : // No operand predicates
10947 : GIM_CheckIsSafeToFold, /*InsnID*/1,
10948 : // (intrinsic_w_chain:{ *:[v4i8] } 3523:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHLL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
10949 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_QB,
10950 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
10951 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
10952 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
10953 : GIR_EraseFromParent, /*InsnID*/0,
10954 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10955 : // GIR_Coverage, 1866,
10956 : GIR_Done,
10957 : // Label 717: @26363
10958 : GIM_Try, /*On fail goto*//*Label 718*/ 26419, // Rule ID 331 //
10959 : GIM_CheckFeatures, GIFBS_HasDSP,
10960 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_s_w,
10961 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
10962 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
10963 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
10964 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
10965 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
10966 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
10967 : // (intrinsic_w_chain:{ *:[i32] } 2979:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
10968 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_W,
10969 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
10970 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
10971 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
10972 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10973 : GIR_EraseFromParent, /*InsnID*/0,
10974 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10975 : // GIR_Coverage, 331,
10976 : GIR_Done,
10977 : // Label 718: @26419
10978 : GIM_Try, /*On fail goto*//*Label 719*/ 26475, // Rule ID 332 //
10979 : GIM_CheckFeatures, GIFBS_HasDSP,
10980 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_s_w,
10981 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
10982 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
10983 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
10984 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
10985 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
10986 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
10987 : // (intrinsic_w_chain:{ *:[i32] } 3595:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
10988 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_W,
10989 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
10990 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
10991 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
10992 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
10993 : GIR_EraseFromParent, /*InsnID*/0,
10994 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10995 : // GIR_Coverage, 332,
10996 : GIR_Done,
10997 : // Label 719: @26475
10998 : GIM_Try, /*On fail goto*//*Label 720*/ 26531, // Rule ID 339 //
10999 : GIM_CheckFeatures, GIFBS_HasDSP,
11000 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_rs_ph_w,
11001 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11002 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11003 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11004 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11005 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11006 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11007 : // (intrinsic_w_chain:{ *:[v2i16] } 3503:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_RS_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11008 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_RS_PH_W,
11009 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11010 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11011 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11012 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11013 : GIR_EraseFromParent, /*InsnID*/0,
11014 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11015 : // GIR_Coverage, 339,
11016 : GIR_Done,
11017 : // Label 720: @26531
11018 : GIM_Try, /*On fail goto*//*Label 721*/ 26587, // Rule ID 340 //
11019 : GIM_CheckFeatures, GIFBS_HasDSP,
11020 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrqu_s_qb_ph,
11021 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
11022 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11023 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11024 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11025 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11026 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11027 : // (intrinsic_w_chain:{ *:[v4i8] } 3504:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQU_S_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11028 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQU_S_QB_PH,
11029 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11030 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11031 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11032 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11033 : GIR_EraseFromParent, /*InsnID*/0,
11034 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11035 : // GIR_Coverage, 340,
11036 : GIR_Done,
11037 : // Label 721: @26587
11038 : GIM_Try, /*On fail goto*//*Label 722*/ 26643, // Rule ID 351 //
11039 : GIM_CheckFeatures, GIFBS_HasDSP,
11040 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_qb,
11041 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
11042 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11043 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11044 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11045 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11046 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11047 : // (intrinsic_w_chain:{ *:[v4i8] } 3523:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
11048 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_QB,
11049 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11050 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11051 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
11052 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11053 : GIR_EraseFromParent, /*InsnID*/0,
11054 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11055 : // GIR_Coverage, 351,
11056 : GIR_Done,
11057 : // Label 722: @26643
11058 : GIM_Try, /*On fail goto*//*Label 723*/ 26699, // Rule ID 353 //
11059 : GIM_CheckFeatures, GIFBS_HasDSP,
11060 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_ph,
11061 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11062 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11063 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11064 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11065 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11066 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11067 : // (intrinsic_w_chain:{ *:[v2i16] } 3522:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
11068 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_PH,
11069 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11070 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11071 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
11072 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11073 : GIR_EraseFromParent, /*InsnID*/0,
11074 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11075 : // GIR_Coverage, 353,
11076 : GIR_Done,
11077 : // Label 723: @26699
11078 : GIM_Try, /*On fail goto*//*Label 724*/ 26755, // Rule ID 355 //
11079 : GIM_CheckFeatures, GIFBS_HasDSP,
11080 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_ph,
11081 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11082 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11083 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11084 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11085 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11086 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11087 : // (intrinsic_w_chain:{ *:[v2i16] } 3524:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
11088 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_PH,
11089 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11090 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11091 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
11092 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11093 : GIR_EraseFromParent, /*InsnID*/0,
11094 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11095 : // GIR_Coverage, 355,
11096 : GIR_Done,
11097 : // Label 724: @26755
11098 : GIM_Try, /*On fail goto*//*Label 725*/ 26811, // Rule ID 360 //
11099 : GIM_CheckFeatures, GIFBS_HasDSP,
11100 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_w,
11101 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11102 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11103 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11104 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11105 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11106 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11107 : // (intrinsic_w_chain:{ *:[i32] } 3525:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
11108 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_W,
11109 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11110 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11111 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
11112 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11113 : GIR_EraseFromParent, /*InsnID*/0,
11114 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11115 : // GIR_Coverage, 360,
11116 : GIR_Done,
11117 : // Label 725: @26811
11118 : GIM_Try, /*On fail goto*//*Label 726*/ 26867, // Rule ID 363 //
11119 : GIM_CheckFeatures, GIFBS_HasDSP,
11120 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleu_s_ph_qbl,
11121 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11122 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11123 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11124 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11125 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11126 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11127 : // (intrinsic_w_chain:{ *:[v2i16] } 3445:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11128 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBL,
11129 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11130 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11131 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11132 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11133 : GIR_EraseFromParent, /*InsnID*/0,
11134 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11135 : // GIR_Coverage, 363,
11136 : GIR_Done,
11137 : // Label 726: @26867
11138 : GIM_Try, /*On fail goto*//*Label 727*/ 26923, // Rule ID 364 //
11139 : GIM_CheckFeatures, GIFBS_HasDSP,
11140 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleu_s_ph_qbr,
11141 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11142 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11143 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11144 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11145 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11146 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11147 : // (intrinsic_w_chain:{ *:[v2i16] } 3446:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11148 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBR,
11149 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11150 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11151 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11152 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11153 : GIR_EraseFromParent, /*InsnID*/0,
11154 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11155 : // GIR_Coverage, 364,
11156 : GIR_Done,
11157 : // Label 727: @26923
11158 : GIM_Try, /*On fail goto*//*Label 728*/ 26979, // Rule ID 365 //
11159 : GIM_CheckFeatures, GIFBS_HasDSP,
11160 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleq_s_w_phl,
11161 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11162 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11163 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11164 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11165 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11166 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11167 : // (intrinsic_w_chain:{ *:[i32] } 3443:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11168 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHL,
11169 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11170 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11171 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11172 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11173 : GIR_EraseFromParent, /*InsnID*/0,
11174 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11175 : // GIR_Coverage, 365,
11176 : GIR_Done,
11177 : // Label 728: @26979
11178 : GIM_Try, /*On fail goto*//*Label 729*/ 27035, // Rule ID 366 //
11179 : GIM_CheckFeatures, GIFBS_HasDSP,
11180 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleq_s_w_phr,
11181 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11182 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11183 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11184 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11185 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11186 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11187 : // (intrinsic_w_chain:{ *:[i32] } 3444:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11188 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHR,
11189 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11190 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11191 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11192 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11193 : GIR_EraseFromParent, /*InsnID*/0,
11194 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11195 : // GIR_Coverage, 366,
11196 : GIR_Done,
11197 : // Label 729: @27035
11198 : GIM_Try, /*On fail goto*//*Label 730*/ 27091, // Rule ID 367 //
11199 : GIM_CheckFeatures, GIFBS_HasDSP,
11200 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_rs_ph,
11201 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11202 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11203 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11204 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11205 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11206 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11207 : // (intrinsic_w_chain:{ *:[v2i16] } 3447:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_RS_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11208 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_PH,
11209 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11210 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11211 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11212 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11213 : GIR_EraseFromParent, /*InsnID*/0,
11214 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11215 : // GIR_Coverage, 367,
11216 : GIR_Done,
11217 : // Label 730: @27091
11218 : GIM_Try, /*On fail goto*//*Label 731*/ 27147, // Rule ID 392 //
11219 : GIM_CheckFeatures, GIFBS_HasDSP,
11220 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_eq_qb,
11221 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11222 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11223 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
11224 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11225 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11226 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11227 : // (intrinsic_w_chain:{ *:[i32] } 3145:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11228 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_EQ_QB,
11229 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11230 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11231 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11232 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11233 : GIR_EraseFromParent, /*InsnID*/0,
11234 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11235 : // GIR_Coverage, 392,
11236 : GIR_Done,
11237 : // Label 731: @27147
11238 : GIM_Try, /*On fail goto*//*Label 732*/ 27203, // Rule ID 393 //
11239 : GIM_CheckFeatures, GIFBS_HasDSP,
11240 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_lt_qb,
11241 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11242 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11243 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
11244 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11245 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11246 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11247 : // (intrinsic_w_chain:{ *:[i32] } 3147:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11248 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LT_QB,
11249 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11250 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11251 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11252 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11253 : GIR_EraseFromParent, /*InsnID*/0,
11254 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11255 : // GIR_Coverage, 393,
11256 : GIR_Done,
11257 : // Label 732: @27203
11258 : GIM_Try, /*On fail goto*//*Label 733*/ 27259, // Rule ID 394 //
11259 : GIM_CheckFeatures, GIFBS_HasDSP,
11260 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_le_qb,
11261 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11262 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11263 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
11264 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11265 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11266 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11267 : // (intrinsic_w_chain:{ *:[i32] } 3146:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11268 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LE_QB,
11269 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11270 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11271 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11272 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11273 : GIR_EraseFromParent, /*InsnID*/0,
11274 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11275 : // GIR_Coverage, 394,
11276 : GIR_Done,
11277 : // Label 733: @27259
11278 : GIM_Try, /*On fail goto*//*Label 734*/ 27315, // Rule ID 404 //
11279 : GIM_CheckFeatures, GIFBS_HasDSP,
11280 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_pick_qb,
11281 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
11282 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11283 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
11284 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11285 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11286 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11287 : // (intrinsic_w_chain:{ *:[v4i8] } 3487:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (PICK_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11288 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_QB,
11289 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11290 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11291 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11292 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11293 : GIR_EraseFromParent, /*InsnID*/0,
11294 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11295 : // GIR_Coverage, 404,
11296 : GIR_Done,
11297 : // Label 734: @27315
11298 : GIM_Try, /*On fail goto*//*Label 735*/ 27371, // Rule ID 405 //
11299 : GIM_CheckFeatures, GIFBS_HasDSP,
11300 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_pick_ph,
11301 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11302 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11303 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11304 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11305 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11306 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11307 : // (intrinsic_w_chain:{ *:[v2i16] } 3486:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PICK_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11308 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_PH,
11309 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11310 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11311 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11312 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11313 : GIR_EraseFromParent, /*InsnID*/0,
11314 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11315 : // GIR_Coverage, 405,
11316 : GIR_Done,
11317 : // Label 735: @27371
11318 : GIM_Try, /*On fail goto*//*Label 736*/ 27427, // Rule ID 409 //
11319 : GIM_CheckFeatures, GIFBS_HasDSP,
11320 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_insv,
11321 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11322 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11323 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11324 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11325 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11326 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11327 : // (intrinsic_w_chain:{ *:[i32] } 3347:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs) => (INSV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)
11328 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::INSV,
11329 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
11330 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
11331 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
11332 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11333 : GIR_EraseFromParent, /*InsnID*/0,
11334 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11335 : // GIR_Coverage, 409,
11336 : GIR_Done,
11337 : // Label 736: @27427
11338 : GIM_Try, /*On fail goto*//*Label 737*/ 27483, // Rule ID 415 //
11339 : GIM_CheckFeatures, GIFBS_HasDSPR2,
11340 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_ph,
11341 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11342 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11343 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11344 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11345 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11346 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11347 : // (intrinsic_w_chain:{ *:[v2i16] } 2997:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11348 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_PH,
11349 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11350 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11351 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11352 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11353 : GIR_EraseFromParent, /*InsnID*/0,
11354 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11355 : // GIR_Coverage, 415,
11356 : GIR_Done,
11357 : // Label 737: @27483
11358 : GIM_Try, /*On fail goto*//*Label 738*/ 27539, // Rule ID 416 //
11359 : GIM_CheckFeatures, GIFBS_HasDSPR2,
11360 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_s_ph,
11361 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11362 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11363 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11364 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11365 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11366 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11367 : // (intrinsic_w_chain:{ *:[v2i16] } 2999:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11368 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_PH,
11369 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11370 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11371 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11372 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11373 : GIR_EraseFromParent, /*InsnID*/0,
11374 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11375 : // GIR_Coverage, 416,
11376 : GIR_Done,
11377 : // Label 738: @27539
11378 : GIM_Try, /*On fail goto*//*Label 739*/ 27595, // Rule ID 417 //
11379 : GIM_CheckFeatures, GIFBS_HasDSPR2,
11380 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_ph,
11381 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11382 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11383 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11384 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11385 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11386 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11387 : // (intrinsic_w_chain:{ *:[v2i16] } 3616:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11388 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_PH,
11389 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11390 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11391 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11392 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11393 : GIR_EraseFromParent, /*InsnID*/0,
11394 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11395 : // GIR_Coverage, 417,
11396 : GIR_Done,
11397 : // Label 739: @27595
11398 : GIM_Try, /*On fail goto*//*Label 740*/ 27651, // Rule ID 418 //
11399 : GIM_CheckFeatures, GIFBS_HasDSPR2,
11400 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_s_ph,
11401 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11402 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11403 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11404 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11405 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11406 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11407 : // (intrinsic_w_chain:{ *:[v2i16] } 3618:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11408 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_PH,
11409 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11410 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11411 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11412 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11413 : GIR_EraseFromParent, /*InsnID*/0,
11414 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11415 : // GIR_Coverage, 418,
11416 : GIR_Done,
11417 : // Label 740: @27651
11418 : GIM_Try, /*On fail goto*//*Label 741*/ 27707, // Rule ID 419 //
11419 : GIM_CheckFeatures, GIFBS_HasDSPR2,
11420 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_eq_qb,
11421 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11422 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11423 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
11424 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11425 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11426 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11427 : // (intrinsic_w_chain:{ *:[i32] } 3142:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11428 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_EQ_QB,
11429 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11430 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11431 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11432 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11433 : GIR_EraseFromParent, /*InsnID*/0,
11434 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11435 : // GIR_Coverage, 419,
11436 : GIR_Done,
11437 : // Label 741: @27707
11438 : GIM_Try, /*On fail goto*//*Label 742*/ 27763, // Rule ID 420 //
11439 : GIM_CheckFeatures, GIFBS_HasDSPR2,
11440 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_lt_qb,
11441 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11442 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11443 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
11444 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11445 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11446 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11447 : // (intrinsic_w_chain:{ *:[i32] } 3144:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11448 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LT_QB,
11449 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11450 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11451 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11452 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11453 : GIR_EraseFromParent, /*InsnID*/0,
11454 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11455 : // GIR_Coverage, 420,
11456 : GIR_Done,
11457 : // Label 742: @27763
11458 : GIM_Try, /*On fail goto*//*Label 743*/ 27819, // Rule ID 421 //
11459 : GIM_CheckFeatures, GIFBS_HasDSPR2,
11460 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_le_qb,
11461 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11462 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11463 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
11464 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11465 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11466 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11467 : // (intrinsic_w_chain:{ *:[i32] } 3143:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11468 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LE_QB,
11469 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11470 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11471 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11472 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11473 : GIR_EraseFromParent, /*InsnID*/0,
11474 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11475 : // GIR_Coverage, 421,
11476 : GIR_Done,
11477 : // Label 743: @27819
11478 : GIM_Try, /*On fail goto*//*Label 744*/ 27875, // Rule ID 435 //
11479 : GIM_CheckFeatures, GIFBS_HasDSPR2,
11480 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_s_ph,
11481 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11482 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11483 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11484 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11485 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11486 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11487 : // (intrinsic_w_chain:{ *:[v2i16] } 3442:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MUL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11488 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_S_PH,
11489 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11490 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11491 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11492 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11493 : GIR_EraseFromParent, /*InsnID*/0,
11494 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11495 : // GIR_Coverage, 435,
11496 : GIR_Done,
11497 : // Label 744: @27875
11498 : GIM_Try, /*On fail goto*//*Label 745*/ 27931, // Rule ID 436 //
11499 : GIM_CheckFeatures, GIFBS_HasDSPR2,
11500 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_s_w,
11501 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11502 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11503 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11504 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11505 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11506 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11507 : // (intrinsic_w_chain:{ *:[i32] } 3450:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11508 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_W,
11509 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11510 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11511 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11512 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11513 : GIR_EraseFromParent, /*InsnID*/0,
11514 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11515 : // GIR_Coverage, 436,
11516 : GIR_Done,
11517 : // Label 745: @27931
11518 : GIM_Try, /*On fail goto*//*Label 746*/ 27987, // Rule ID 437 //
11519 : GIM_CheckFeatures, GIFBS_HasDSPR2,
11520 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_rs_w,
11521 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11522 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11523 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11524 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11525 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11526 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11527 : // (intrinsic_w_chain:{ *:[i32] } 3448:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_RS_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11528 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_W,
11529 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11530 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11531 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11532 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11533 : GIR_EraseFromParent, /*InsnID*/0,
11534 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11535 : // GIR_Coverage, 437,
11536 : GIR_Done,
11537 : // Label 746: @27987
11538 : GIM_Try, /*On fail goto*//*Label 747*/ 28043, // Rule ID 438 //
11539 : GIM_CheckFeatures, GIFBS_HasDSPR2,
11540 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_s_ph,
11541 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11542 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11543 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11544 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11545 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11546 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11547 : // (intrinsic_w_chain:{ *:[v2i16] } 3449:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11548 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_PH,
11549 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11550 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11551 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11552 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11553 : GIR_EraseFromParent, /*InsnID*/0,
11554 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11555 : // GIR_Coverage, 438,
11556 : GIR_Done,
11557 : // Label 747: @28043
11558 : GIM_Try, /*On fail goto*//*Label 748*/ 28099, // Rule ID 448 //
11559 : GIM_CheckFeatures, GIFBS_HasDSPR2,
11560 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_qb_ph,
11561 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
11562 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11563 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11564 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11565 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11566 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11567 : // (intrinsic_w_chain:{ *:[v4i8] } 3498:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECR_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11568 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_QB_PH,
11569 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11570 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11571 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11572 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11573 : GIR_EraseFromParent, /*InsnID*/0,
11574 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11575 : // GIR_Coverage, 448,
11576 : GIR_Done,
11577 : // Label 748: @28099
11578 : GIM_Try, /*On fail goto*//*Label 749*/ 28155, // Rule ID 1190 //
11579 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11580 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_s_w,
11581 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11582 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11583 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11584 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11585 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11586 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11587 : // (intrinsic_w_chain:{ *:[i32] } 2979:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11588 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_W_MM,
11589 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11590 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11591 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11592 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11593 : GIR_EraseFromParent, /*InsnID*/0,
11594 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11595 : // GIR_Coverage, 1190,
11596 : GIR_Done,
11597 : // Label 749: @28155
11598 : GIM_Try, /*On fail goto*//*Label 750*/ 28211, // Rule ID 1198 //
11599 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11600 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_insv,
11601 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11602 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11603 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11604 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11605 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11606 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11607 : // (intrinsic_w_chain:{ *:[i32] } 3347:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs) => (INSV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)
11608 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::INSV_MM,
11609 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
11610 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
11611 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
11612 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11613 : GIR_EraseFromParent, /*InsnID*/0,
11614 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11615 : // GIR_Coverage, 1198,
11616 : GIR_Done,
11617 : // Label 750: @28211
11618 : GIM_Try, /*On fail goto*//*Label 751*/ 28267, // Rule ID 1206 //
11619 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11620 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_ph,
11621 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11622 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11623 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11624 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11625 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11626 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11627 : // (intrinsic_w_chain:{ *:[v2i16] } 3522:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11628 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_PH_MM,
11629 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11630 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11631 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
11632 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11633 : GIR_EraseFromParent, /*InsnID*/0,
11634 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11635 : // GIR_Coverage, 1206,
11636 : GIR_Done,
11637 : // Label 751: @28267
11638 : GIM_Try, /*On fail goto*//*Label 752*/ 28323, // Rule ID 1207 //
11639 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11640 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_ph,
11641 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11642 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11643 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11644 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11645 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11646 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11647 : // (intrinsic_w_chain:{ *:[v2i16] } 3524:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11648 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_PH_MM,
11649 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11650 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11651 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
11652 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11653 : GIR_EraseFromParent, /*InsnID*/0,
11654 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11655 : // GIR_Coverage, 1207,
11656 : GIR_Done,
11657 : // Label 752: @28323
11658 : GIM_Try, /*On fail goto*//*Label 753*/ 28379, // Rule ID 1208 //
11659 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11660 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_qb,
11661 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
11662 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11663 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11664 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11665 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11666 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11667 : // (intrinsic_w_chain:{ *:[v4i8] } 3523:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11668 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_QB_MM,
11669 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11670 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11671 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
11672 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11673 : GIR_EraseFromParent, /*InsnID*/0,
11674 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11675 : // GIR_Coverage, 1208,
11676 : GIR_Done,
11677 : // Label 753: @28379
11678 : GIM_Try, /*On fail goto*//*Label 754*/ 28435, // Rule ID 1209 //
11679 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11680 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_w,
11681 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11682 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11683 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11684 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11685 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11686 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11687 : // (intrinsic_w_chain:{ *:[i32] } 3525:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11688 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_W_MM,
11689 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11690 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
11691 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
11692 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11693 : GIR_EraseFromParent, /*InsnID*/0,
11694 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11695 : // GIR_Coverage, 1209,
11696 : GIR_Done,
11697 : // Label 754: @28435
11698 : GIM_Try, /*On fail goto*//*Label 755*/ 28491, // Rule ID 1228 //
11699 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11700 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_s_w,
11701 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11702 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11703 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11704 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11705 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11706 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11707 : // (intrinsic_w_chain:{ *:[i32] } 3595:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11708 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_W_MM,
11709 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11710 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11711 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11712 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11713 : GIR_EraseFromParent, /*InsnID*/0,
11714 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11715 : // GIR_Coverage, 1228,
11716 : GIR_Done,
11717 : // Label 755: @28491
11718 : GIM_Try, /*On fail goto*//*Label 756*/ 28547, // Rule ID 1234 //
11719 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11720 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleq_s_w_phl,
11721 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11722 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11723 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11724 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11725 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11726 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11727 : // (intrinsic_w_chain:{ *:[i32] } 3443:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11728 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHL_MM,
11729 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11730 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11731 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11732 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11733 : GIR_EraseFromParent, /*InsnID*/0,
11734 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11735 : // GIR_Coverage, 1234,
11736 : GIR_Done,
11737 : // Label 756: @28547
11738 : GIM_Try, /*On fail goto*//*Label 757*/ 28603, // Rule ID 1235 //
11739 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11740 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleq_s_w_phr,
11741 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11742 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11743 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11744 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11745 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11746 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11747 : // (intrinsic_w_chain:{ *:[i32] } 3444:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11748 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHR_MM,
11749 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11750 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11751 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11752 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11753 : GIR_EraseFromParent, /*InsnID*/0,
11754 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11755 : // GIR_Coverage, 1235,
11756 : GIR_Done,
11757 : // Label 757: @28603
11758 : GIM_Try, /*On fail goto*//*Label 758*/ 28659, // Rule ID 1236 //
11759 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11760 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleu_s_ph_qbl,
11761 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11762 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11763 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11764 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11765 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11766 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11767 : // (intrinsic_w_chain:{ *:[v2i16] } 3445:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11768 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBL_MM,
11769 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11770 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11771 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11772 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11773 : GIR_EraseFromParent, /*InsnID*/0,
11774 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11775 : // GIR_Coverage, 1236,
11776 : GIR_Done,
11777 : // Label 758: @28659
11778 : GIM_Try, /*On fail goto*//*Label 759*/ 28715, // Rule ID 1237 //
11779 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11780 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleu_s_ph_qbr,
11781 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11782 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11783 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11784 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11785 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11786 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11787 : // (intrinsic_w_chain:{ *:[v2i16] } 3446:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11788 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBR_MM,
11789 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11790 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11791 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11792 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11793 : GIR_EraseFromParent, /*InsnID*/0,
11794 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11795 : // GIR_Coverage, 1237,
11796 : GIR_Done,
11797 : // Label 759: @28715
11798 : GIM_Try, /*On fail goto*//*Label 760*/ 28771, // Rule ID 1238 //
11799 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11800 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_rs_ph,
11801 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11802 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11803 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11804 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11805 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11806 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11807 : // (intrinsic_w_chain:{ *:[v2i16] } 3447:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_RS_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11808 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_PH_MM,
11809 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11810 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11811 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11812 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11813 : GIR_EraseFromParent, /*InsnID*/0,
11814 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11815 : // GIR_Coverage, 1238,
11816 : GIR_Done,
11817 : // Label 760: @28771
11818 : GIM_Try, /*On fail goto*//*Label 761*/ 28827, // Rule ID 1241 //
11819 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11820 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrqu_s_qb_ph,
11821 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
11822 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11823 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11824 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11825 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11826 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11827 : // (intrinsic_w_chain:{ *:[v4i8] } 3504:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQU_S_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11828 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQU_S_QB_PH_MM,
11829 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11830 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11831 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11832 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11833 : GIR_EraseFromParent, /*InsnID*/0,
11834 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11835 : // GIR_Coverage, 1241,
11836 : GIR_Done,
11837 : // Label 761: @28827
11838 : GIM_Try, /*On fail goto*//*Label 762*/ 28883, // Rule ID 1242 //
11839 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11840 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_rs_ph_w,
11841 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11842 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11843 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11844 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11845 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
11846 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
11847 : // (intrinsic_w_chain:{ *:[v2i16] } 3503:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_RS_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11848 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_RS_PH_W_MM,
11849 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11850 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11851 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11852 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11853 : GIR_EraseFromParent, /*InsnID*/0,
11854 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11855 : // GIR_Coverage, 1242,
11856 : GIR_Done,
11857 : // Label 762: @28883
11858 : GIM_Try, /*On fail goto*//*Label 763*/ 28939, // Rule ID 1260 //
11859 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11860 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_pick_ph,
11861 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11862 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11863 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11864 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11865 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11866 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11867 : // (intrinsic_w_chain:{ *:[v2i16] } 3486:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PICK_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11868 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_PH_MM,
11869 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11870 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11871 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11872 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11873 : GIR_EraseFromParent, /*InsnID*/0,
11874 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11875 : // GIR_Coverage, 1260,
11876 : GIR_Done,
11877 : // Label 763: @28939
11878 : GIM_Try, /*On fail goto*//*Label 764*/ 28995, // Rule ID 1261 //
11879 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11880 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_pick_qb,
11881 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
11882 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11883 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
11884 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11885 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11886 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11887 : // (intrinsic_w_chain:{ *:[v4i8] } 3487:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (PICK_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11888 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_QB_MM,
11889 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11890 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11891 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11892 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11893 : GIR_EraseFromParent, /*InsnID*/0,
11894 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11895 : // GIR_Coverage, 1261,
11896 : GIR_Done,
11897 : // Label 764: @28995
11898 : GIM_Try, /*On fail goto*//*Label 765*/ 29051, // Rule ID 1271 //
11899 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11900 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_eq_qb,
11901 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11902 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11903 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
11904 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11905 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11906 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11907 : // (intrinsic_w_chain:{ *:[i32] } 3145:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_EQ_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11908 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_EQ_QB_MM,
11909 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11910 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11911 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11912 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11913 : GIR_EraseFromParent, /*InsnID*/0,
11914 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11915 : // GIR_Coverage, 1271,
11916 : GIR_Done,
11917 : // Label 765: @29051
11918 : GIM_Try, /*On fail goto*//*Label 766*/ 29107, // Rule ID 1272 //
11919 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11920 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_lt_qb,
11921 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11922 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11923 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
11924 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11925 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11926 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11927 : // (intrinsic_w_chain:{ *:[i32] } 3147:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LT_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11928 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LT_QB_MM,
11929 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11930 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11931 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11932 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11933 : GIR_EraseFromParent, /*InsnID*/0,
11934 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11935 : // GIR_Coverage, 1272,
11936 : GIR_Done,
11937 : // Label 766: @29107
11938 : GIM_Try, /*On fail goto*//*Label 767*/ 29163, // Rule ID 1273 //
11939 : GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
11940 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_le_qb,
11941 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11942 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
11943 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
11944 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
11945 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11946 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11947 : // (intrinsic_w_chain:{ *:[i32] } 3146:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LE_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11948 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LE_QB_MM,
11949 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11950 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11951 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11952 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11953 : GIR_EraseFromParent, /*InsnID*/0,
11954 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11955 : // GIR_Coverage, 1273,
11956 : GIR_Done,
11957 : // Label 767: @29163
11958 : GIM_Try, /*On fail goto*//*Label 768*/ 29219, // Rule ID 1282 //
11959 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
11960 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_ph,
11961 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11962 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11963 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11964 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11965 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11966 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11967 : // (intrinsic_w_chain:{ *:[v2i16] } 2997:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11968 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_PH_MMR2,
11969 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11970 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11971 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11972 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11973 : GIR_EraseFromParent, /*InsnID*/0,
11974 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11975 : // GIR_Coverage, 1282,
11976 : GIR_Done,
11977 : // Label 768: @29219
11978 : GIM_Try, /*On fail goto*//*Label 769*/ 29275, // Rule ID 1283 //
11979 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
11980 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_s_ph,
11981 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
11982 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
11983 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
11984 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
11985 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
11986 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
11987 : // (intrinsic_w_chain:{ *:[v2i16] } 2999:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11988 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_PH_MMR2,
11989 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
11990 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
11991 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
11992 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
11993 : GIR_EraseFromParent, /*InsnID*/0,
11994 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11995 : // GIR_Coverage, 1283,
11996 : GIR_Done,
11997 : // Label 769: @29275
11998 : GIM_Try, /*On fail goto*//*Label 770*/ 29331, // Rule ID 1294 //
11999 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12000 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_eq_qb,
12001 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12002 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
12003 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
12004 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12005 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12006 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12007 : // (intrinsic_w_chain:{ *:[i32] } 3142:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_EQ_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12008 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_EQ_QB_MMR2,
12009 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12010 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12011 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12012 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12013 : GIR_EraseFromParent, /*InsnID*/0,
12014 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12015 : // GIR_Coverage, 1294,
12016 : GIR_Done,
12017 : // Label 770: @29331
12018 : GIM_Try, /*On fail goto*//*Label 771*/ 29387, // Rule ID 1295 //
12019 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12020 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_lt_qb,
12021 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12022 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
12023 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
12024 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12025 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12026 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12027 : // (intrinsic_w_chain:{ *:[i32] } 3144:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LT_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12028 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LT_QB_MMR2,
12029 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12030 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12031 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12032 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12033 : GIR_EraseFromParent, /*InsnID*/0,
12034 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12035 : // GIR_Coverage, 1295,
12036 : GIR_Done,
12037 : // Label 771: @29387
12038 : GIM_Try, /*On fail goto*//*Label 772*/ 29443, // Rule ID 1296 //
12039 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12040 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_le_qb,
12041 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12042 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
12043 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
12044 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12045 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12046 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12047 : // (intrinsic_w_chain:{ *:[i32] } 3143:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LE_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12048 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LE_QB_MMR2,
12049 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12050 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12051 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12052 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12053 : GIR_EraseFromParent, /*InsnID*/0,
12054 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12055 : // GIR_Coverage, 1296,
12056 : GIR_Done,
12057 : // Label 772: @29443
12058 : GIM_Try, /*On fail goto*//*Label 773*/ 29499, // Rule ID 1302 //
12059 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12060 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_ph,
12061 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
12062 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
12063 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12064 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12065 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12066 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12067 : // (intrinsic_w_chain:{ *:[v2i16] } 3616:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12068 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_PH_MMR2,
12069 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12070 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12071 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12072 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12073 : GIR_EraseFromParent, /*InsnID*/0,
12074 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12075 : // GIR_Coverage, 1302,
12076 : GIR_Done,
12077 : // Label 773: @29499
12078 : GIM_Try, /*On fail goto*//*Label 774*/ 29555, // Rule ID 1303 //
12079 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12080 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_s_ph,
12081 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
12082 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
12083 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12084 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12085 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12086 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12087 : // (intrinsic_w_chain:{ *:[v2i16] } 3618:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12088 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_PH_MMR2,
12089 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12090 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12091 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12092 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12093 : GIR_EraseFromParent, /*InsnID*/0,
12094 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12095 : // GIR_Coverage, 1303,
12096 : GIR_Done,
12097 : // Label 774: @29555
12098 : GIM_Try, /*On fail goto*//*Label 775*/ 29611, // Rule ID 1310 //
12099 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12100 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_s_ph,
12101 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
12102 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
12103 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12104 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12105 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12106 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12107 : // (intrinsic_w_chain:{ *:[v2i16] } 3442:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MUL_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12108 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_S_PH_MMR2,
12109 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12110 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12111 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12112 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12113 : GIR_EraseFromParent, /*InsnID*/0,
12114 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12115 : // GIR_Coverage, 1310,
12116 : GIR_Done,
12117 : // Label 775: @29611
12118 : GIM_Try, /*On fail goto*//*Label 776*/ 29667, // Rule ID 1311 //
12119 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12120 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_rs_w,
12121 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12122 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12123 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12124 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12125 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12126 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
12127 : // (intrinsic_w_chain:{ *:[i32] } 3448:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_RS_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
12128 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_W_MMR2,
12129 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12130 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12131 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12132 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12133 : GIR_EraseFromParent, /*InsnID*/0,
12134 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12135 : // GIR_Coverage, 1311,
12136 : GIR_Done,
12137 : // Label 776: @29667
12138 : GIM_Try, /*On fail goto*//*Label 777*/ 29723, // Rule ID 1312 //
12139 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12140 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_s_ph,
12141 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
12142 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
12143 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12144 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12145 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12146 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12147 : // (intrinsic_w_chain:{ *:[v2i16] } 3449:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12148 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_PH_MMR2,
12149 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12150 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12151 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12152 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12153 : GIR_EraseFromParent, /*InsnID*/0,
12154 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12155 : // GIR_Coverage, 1312,
12156 : GIR_Done,
12157 : // Label 777: @29723
12158 : GIM_Try, /*On fail goto*//*Label 778*/ 29779, // Rule ID 1313 //
12159 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12160 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_s_w,
12161 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12162 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12163 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12164 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12165 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12166 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
12167 : // (intrinsic_w_chain:{ *:[i32] } 3450:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_S_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
12168 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_W_MMR2,
12169 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12170 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12171 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12172 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12173 : GIR_EraseFromParent, /*InsnID*/0,
12174 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12175 : // GIR_Coverage, 1313,
12176 : GIR_Done,
12177 : // Label 778: @29779
12178 : GIM_Try, /*On fail goto*//*Label 779*/ 29835, // Rule ID 1314 //
12179 : GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
12180 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_qb_ph,
12181 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
12182 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
12183 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12184 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12185 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
12186 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
12187 : // (intrinsic_w_chain:{ *:[v4i8] } 3498:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECR_QB_PH_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12188 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_QB_PH_MMR2,
12189 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12190 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
12191 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
12192 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12193 : GIR_EraseFromParent, /*InsnID*/0,
12194 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12195 : // GIR_Coverage, 1314,
12196 : GIR_Done,
12197 : // Label 779: @29835
12198 : GIM_Try, /*On fail goto*//*Label 780*/ 29883, // Rule ID 1847 //
12199 : GIM_CheckFeatures, GIFBS_HasDSPR2,
12200 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_ph,
12201 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
12202 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
12203 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
12204 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
12205 : // (intrinsic_w_chain:{ *:[v2i16] } 3439:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
12206 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_PH,
12207 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12208 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
12209 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
12210 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12211 : GIR_EraseFromParent, /*InsnID*/0,
12212 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12213 : // GIR_Coverage, 1847,
12214 : GIR_Done,
12215 : // Label 780: @29883
12216 : GIM_Try, /*On fail goto*//*Label 781*/ 29931, // Rule ID 1853 //
12217 : GIM_CheckFeatures, GIFBS_HasDSP,
12218 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addsc,
12219 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12220 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12221 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12222 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12223 : // (intrinsic_w_chain:{ *:[i32] } 2996:{ *:[iPTR] }, i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) => (ADDSC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)
12224 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDSC,
12225 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12226 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
12227 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
12228 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12229 : GIR_EraseFromParent, /*InsnID*/0,
12230 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12231 : // GIR_Coverage, 1853,
12232 : GIR_Done,
12233 : // Label 781: @29931
12234 : GIM_Try, /*On fail goto*//*Label 782*/ 29979, // Rule ID 1855 //
12235 : GIM_CheckFeatures, GIFBS_HasDSP,
12236 : GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addwc,
12237 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12238 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12239 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12240 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12241 : // (intrinsic_w_chain:{ *:[i32] } 3011:{ *:[iPTR] }, i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) => (ADDWC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)
12242 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDWC,
12243 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12244 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
12245 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
12246 : GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
12247 : GIR_EraseFromParent, /*InsnID*/0,
12248 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12249 : // GIR_Coverage, 1855,
12250 : GIR_Done,
12251 : // Label 782: @29979
12252 : GIM_Reject,
12253 : // Label 711: @29980
12254 : GIM_Reject,
12255 : // Label 16: @29981
12256 : GIM_Try, /*On fail goto*//*Label 783*/ 30037, // Rule ID 1523 //
12257 : GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit,
12258 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12259 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
12260 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12261 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
12262 : // (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$src) => (SLL:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$src, sub_32:{ *:[i32] }), 0:{ *:[i32] })
12263 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
12264 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
12265 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
12266 : GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/1, // src
12267 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12268 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL,
12269 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12270 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12271 : GIR_AddImm, /*InsnID*/0, /*Imm*/0,
12272 : GIR_EraseFromParent, /*InsnID*/0,
12273 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12274 : // GIR_Coverage, 1523,
12275 : GIR_Done,
12276 : // Label 783: @30037
12277 : GIM_Reject,
12278 : // Label 17: @30038
12279 : GIM_Try, /*On fail goto*//*Label 784*/ 30097,
12280 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12281 : GIM_Try, /*On fail goto*//*Label 785*/ 30070, // Rule ID 2077 //
12282 : GIM_CheckFeatures, GIFBS_InMicroMips,
12283 : GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_immLi16,
12284 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
12285 : // MIs[0] Operand 1
12286 : // No operand predicates
12287 : // (imm:{ *:[i32] })<<P:Predicate_immLi16>>:$imm => (LI16_MM:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immLi16>>:$imm)
12288 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LI16_MM,
12289 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12290 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
12291 : GIR_EraseFromParent, /*InsnID*/0,
12292 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12293 : // GIR_Coverage, 2077,
12294 : GIR_Done,
12295 : // Label 785: @30070
12296 : GIM_Try, /*On fail goto*//*Label 786*/ 30096, // Rule ID 1771 //
12297 : GIM_CheckFeatures, GIFBS_InMips16Mode,
12298 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
12299 : // MIs[0] Operand 1
12300 : // No operand predicates
12301 : // (imm:{ *:[i32] }):$imm => (LwConstant32:{ *:[i32] } (imm:{ *:[i32] }):$imm, -1:{ *:[i32] })
12302 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LwConstant32,
12303 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
12304 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
12305 : GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
12306 : GIR_EraseFromParent, /*InsnID*/0,
12307 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12308 : // GIR_Coverage, 1771,
12309 : GIR_Done,
12310 : // Label 786: @30096
12311 : GIM_Reject,
12312 : // Label 784: @30097
12313 : GIM_Reject,
12314 : // Label 18: @30098
12315 : GIM_Try, /*On fail goto*//*Label 787*/ 30125, // Rule ID 1530 //
12316 : GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit,
12317 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
12318 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
12319 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
12320 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12321 : // (sext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (SLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src)
12322 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL64_32,
12323 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12324 : // GIR_Coverage, 1530,
12325 : GIR_Done,
12326 : // Label 787: @30125
12327 : GIM_Reject,
12328 : // Label 19: @30126
12329 : GIM_Try, /*On fail goto*//*Label 788*/ 30210,
12330 : GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
12331 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
12332 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
12333 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12334 : GIM_Try, /*On fail goto*//*Label 789*/ 30183, // Rule ID 1529 //
12335 : GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit,
12336 : // (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (DSRL:{ *:[i64] } (DSLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src), 32:{ *:[i32] })
12337 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
12338 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::DSLL64_32,
12339 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
12340 : GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
12341 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12342 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRL,
12343 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12344 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12345 : GIR_AddImm, /*InsnID*/0, /*Imm*/32,
12346 : GIR_EraseFromParent, /*InsnID*/0,
12347 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12348 : // GIR_Coverage, 1529,
12349 : GIR_Done,
12350 : // Label 789: @30183
12351 : GIM_Try, /*On fail goto*//*Label 790*/ 30209, // Rule ID 1531 //
12352 : GIM_CheckFeatures, GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips,
12353 : // (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (DEXT64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src, 0:{ *:[i32] }, 32:{ *:[i32] })
12354 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DEXT64_32,
12355 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
12356 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12357 : GIR_AddImm, /*InsnID*/0, /*Imm*/0,
12358 : GIR_AddImm, /*InsnID*/0, /*Imm*/32,
12359 : GIR_EraseFromParent, /*InsnID*/0,
12360 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12361 : // GIR_Coverage, 1531,
12362 : GIR_Done,
12363 : // Label 790: @30209
12364 : GIM_Reject,
12365 : // Label 788: @30210
12366 : GIM_Reject,
12367 : // Label 20: @30211
12368 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 797*/ 30734,
12369 : /*GILLT_s32*//*Label 791*/ 30225,
12370 : /*GILLT_s64*//*Label 792*/ 30478, 0,
12371 : /*GILLT_v2s64*//*Label 793*/ 30606, 0,
12372 : /*GILLT_v4s32*//*Label 794*/ 30638,
12373 : /*GILLT_v8s16*//*Label 795*/ 30670,
12374 : /*GILLT_v16s8*//*Label 796*/ 30702,
12375 : // Label 791: @30225
12376 : GIM_Try, /*On fail goto*//*Label 798*/ 30477,
12377 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
12378 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12379 : GIM_Try, /*On fail goto*//*Label 799*/ 30278, // Rule ID 43 //
12380 : GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
12381 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12382 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12383 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
12384 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
12385 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
12386 : // MIs[1] Operand 1
12387 : // No operand predicates
12388 : GIM_CheckIsSafeToFold, /*InsnID*/1,
12389 : // (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (SLL:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
12390 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL,
12391 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12392 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
12393 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
12394 : GIR_EraseFromParent, /*InsnID*/0,
12395 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12396 : // GIR_Coverage, 43,
12397 : GIR_Done,
12398 : // Label 799: @30278
12399 : GIM_Try, /*On fail goto*//*Label 800*/ 30321, // Rule ID 1753 //
12400 : GIM_CheckFeatures, GIFBS_InMips16Mode,
12401 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
12402 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
12403 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
12404 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
12405 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
12406 : // MIs[1] Operand 1
12407 : // No operand predicates
12408 : GIM_CheckIsSafeToFold, /*InsnID*/1,
12409 : // (shl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SllX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
12410 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SllX16,
12411 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
12412 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
12413 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
12414 : GIR_EraseFromParent, /*InsnID*/0,
12415 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12416 : // GIR_Coverage, 1753,
12417 : GIR_Done,
12418 : // Label 800: @30321
12419 : GIM_Try, /*On fail goto*//*Label 801*/ 30364, // Rule ID 2089 //
12420 : GIM_CheckFeatures, GIFBS_InMicroMips,
12421 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
12422 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
12423 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
12424 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
12425 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt2Shift,
12426 : // MIs[1] Operand 1
12427 : // No operand predicates
12428 : GIM_CheckIsSafeToFold, /*InsnID*/1,
12429 : // (shl:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm) => (SLL16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)
12430 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL16_MM,
12431 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12432 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12433 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
12434 : GIR_EraseFromParent, /*InsnID*/0,
12435 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12436 : // GIR_Coverage, 2089,
12437 : GIR_Done,
12438 : // Label 801: @30364
12439 : GIM_Try, /*On fail goto*//*Label 802*/ 30407, // Rule ID 2090 //
12440 : GIM_CheckFeatures, GIFBS_InMicroMips,
12441 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12442 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12443 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
12444 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
12445 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
12446 : // MIs[1] Operand 1
12447 : // No operand predicates
12448 : GIM_CheckIsSafeToFold, /*InsnID*/1,
12449 : // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SLL_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
12450 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_MM,
12451 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12452 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12453 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
12454 : GIR_EraseFromParent, /*InsnID*/0,
12455 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12456 : // GIR_Coverage, 2090,
12457 : GIR_Done,
12458 : // Label 802: @30407
12459 : GIM_Try, /*On fail goto*//*Label 803*/ 30430, // Rule ID 46 //
12460 : GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
12461 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12462 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12463 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12464 : // (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SLLV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
12465 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLLV,
12466 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12467 : // GIR_Coverage, 46,
12468 : GIR_Done,
12469 : // Label 803: @30430
12470 : GIM_Try, /*On fail goto*//*Label 804*/ 30453, // Rule ID 1756 //
12471 : GIM_CheckFeatures, GIFBS_InMips16Mode,
12472 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
12473 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
12474 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
12475 : // (shl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SllvRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
12476 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SllvRxRy16,
12477 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12478 : // GIR_Coverage, 1756,
12479 : GIR_Done,
12480 : // Label 804: @30453
12481 : GIM_Try, /*On fail goto*//*Label 805*/ 30476, // Rule ID 2091 //
12482 : GIM_CheckFeatures, GIFBS_InMicroMips,
12483 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12484 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12485 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12486 : // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SLLV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
12487 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLLV_MM,
12488 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12489 : // GIR_Coverage, 2091,
12490 : GIR_Done,
12491 : // Label 805: @30476
12492 : GIM_Reject,
12493 : // Label 798: @30477
12494 : GIM_Reject,
12495 : // Label 792: @30478
12496 : GIM_Try, /*On fail goto*//*Label 806*/ 30605,
12497 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
12498 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12499 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
12500 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
12501 : GIM_Try, /*On fail goto*//*Label 807*/ 30531, // Rule ID 188 //
12502 : GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
12503 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
12504 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
12505 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6,
12506 : // MIs[1] Operand 1
12507 : // No operand predicates
12508 : GIM_CheckIsSafeToFold, /*InsnID*/1,
12509 : // (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSLL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
12510 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSLL,
12511 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12512 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
12513 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
12514 : GIR_EraseFromParent, /*InsnID*/0,
12515 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12516 : // GIR_Coverage, 188,
12517 : GIR_Done,
12518 : // Label 807: @30531
12519 : GIM_Try, /*On fail goto*//*Label 808*/ 30589, // Rule ID 1524 //
12520 : GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit,
12521 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
12522 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC,
12523 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
12524 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
12525 : GIM_CheckIsSafeToFold, /*InsnID*/1,
12526 : // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSLLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
12527 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
12528 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
12529 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
12530 : GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // rs
12531 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12532 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSLLV,
12533 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12534 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
12535 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12536 : GIR_EraseFromParent, /*InsnID*/0,
12537 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12538 : // GIR_Coverage, 1524,
12539 : GIR_Done,
12540 : // Label 808: @30589
12541 : GIM_Try, /*On fail goto*//*Label 809*/ 30604, // Rule ID 191 //
12542 : GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
12543 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12544 : // (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSLLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
12545 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSLLV,
12546 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12547 : // GIR_Coverage, 191,
12548 : GIR_Done,
12549 : // Label 809: @30604
12550 : GIM_Reject,
12551 : // Label 806: @30605
12552 : GIM_Reject,
12553 : // Label 793: @30606
12554 : GIM_Try, /*On fail goto*//*Label 810*/ 30637, // Rule ID 928 //
12555 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
12556 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12557 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
12558 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
12559 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
12560 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
12561 : // (shl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SLL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
12562 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL_D,
12563 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12564 : // GIR_Coverage, 928,
12565 : GIR_Done,
12566 : // Label 810: @30637
12567 : GIM_Reject,
12568 : // Label 794: @30638
12569 : GIM_Try, /*On fail goto*//*Label 811*/ 30669, // Rule ID 927 //
12570 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
12571 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12572 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
12573 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
12574 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
12575 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
12576 : // (shl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SLL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12577 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL_W,
12578 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12579 : // GIR_Coverage, 927,
12580 : GIR_Done,
12581 : // Label 811: @30669
12582 : GIM_Reject,
12583 : // Label 795: @30670
12584 : GIM_Try, /*On fail goto*//*Label 812*/ 30701, // Rule ID 926 //
12585 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
12586 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
12587 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
12588 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
12589 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
12590 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
12591 : // (shl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SLL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12592 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL_H,
12593 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12594 : // GIR_Coverage, 926,
12595 : GIR_Done,
12596 : // Label 812: @30701
12597 : GIM_Reject,
12598 : // Label 796: @30702
12599 : GIM_Try, /*On fail goto*//*Label 813*/ 30733, // Rule ID 925 //
12600 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
12601 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
12602 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
12603 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
12604 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
12605 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
12606 : // (shl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SLL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
12607 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL_B,
12608 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12609 : // GIR_Coverage, 925,
12610 : GIR_Done,
12611 : // Label 813: @30733
12612 : GIM_Reject,
12613 : // Label 797: @30734
12614 : GIM_Reject,
12615 : // Label 21: @30735
12616 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 820*/ 31258,
12617 : /*GILLT_s32*//*Label 814*/ 30749,
12618 : /*GILLT_s64*//*Label 815*/ 31002, 0,
12619 : /*GILLT_v2s64*//*Label 816*/ 31130, 0,
12620 : /*GILLT_v4s32*//*Label 817*/ 31162,
12621 : /*GILLT_v8s16*//*Label 818*/ 31194,
12622 : /*GILLT_v16s8*//*Label 819*/ 31226,
12623 : // Label 814: @30749
12624 : GIM_Try, /*On fail goto*//*Label 821*/ 31001,
12625 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
12626 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12627 : GIM_Try, /*On fail goto*//*Label 822*/ 30802, // Rule ID 44 //
12628 : GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
12629 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12630 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12631 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
12632 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
12633 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
12634 : // MIs[1] Operand 1
12635 : // No operand predicates
12636 : GIM_CheckIsSafeToFold, /*InsnID*/1,
12637 : // (srl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (SRL:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
12638 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL,
12639 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12640 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
12641 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
12642 : GIR_EraseFromParent, /*InsnID*/0,
12643 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12644 : // GIR_Coverage, 44,
12645 : GIR_Done,
12646 : // Label 822: @30802
12647 : GIM_Try, /*On fail goto*//*Label 823*/ 30845, // Rule ID 1754 //
12648 : GIM_CheckFeatures, GIFBS_InMips16Mode,
12649 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
12650 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
12651 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
12652 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
12653 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
12654 : // MIs[1] Operand 1
12655 : // No operand predicates
12656 : GIM_CheckIsSafeToFold, /*InsnID*/1,
12657 : // (srl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SrlX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
12658 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SrlX16,
12659 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
12660 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
12661 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
12662 : GIR_EraseFromParent, /*InsnID*/0,
12663 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12664 : // GIR_Coverage, 1754,
12665 : GIR_Done,
12666 : // Label 823: @30845
12667 : GIM_Try, /*On fail goto*//*Label 824*/ 30888, // Rule ID 2092 //
12668 : GIM_CheckFeatures, GIFBS_InMicroMips,
12669 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
12670 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
12671 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
12672 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
12673 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt2Shift,
12674 : // MIs[1] Operand 1
12675 : // No operand predicates
12676 : GIM_CheckIsSafeToFold, /*InsnID*/1,
12677 : // (srl:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm) => (SRL16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)
12678 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL16_MM,
12679 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12680 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12681 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
12682 : GIR_EraseFromParent, /*InsnID*/0,
12683 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12684 : // GIR_Coverage, 2092,
12685 : GIR_Done,
12686 : // Label 824: @30888
12687 : GIM_Try, /*On fail goto*//*Label 825*/ 30931, // Rule ID 2093 //
12688 : GIM_CheckFeatures, GIFBS_InMicroMips,
12689 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12690 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12691 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
12692 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
12693 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
12694 : // MIs[1] Operand 1
12695 : // No operand predicates
12696 : GIM_CheckIsSafeToFold, /*InsnID*/1,
12697 : // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SRL_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
12698 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_MM,
12699 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12700 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12701 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
12702 : GIR_EraseFromParent, /*InsnID*/0,
12703 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12704 : // GIR_Coverage, 2093,
12705 : GIR_Done,
12706 : // Label 825: @30931
12707 : GIM_Try, /*On fail goto*//*Label 826*/ 30954, // Rule ID 47 //
12708 : GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
12709 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12710 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12711 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12712 : // (srl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SRLV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
12713 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRLV,
12714 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12715 : // GIR_Coverage, 47,
12716 : GIR_Done,
12717 : // Label 826: @30954
12718 : GIM_Try, /*On fail goto*//*Label 827*/ 30977, // Rule ID 1758 //
12719 : GIM_CheckFeatures, GIFBS_InMips16Mode,
12720 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
12721 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
12722 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
12723 : // (srl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SrlvRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
12724 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SrlvRxRy16,
12725 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12726 : // GIR_Coverage, 1758,
12727 : GIR_Done,
12728 : // Label 827: @30977
12729 : GIM_Try, /*On fail goto*//*Label 828*/ 31000, // Rule ID 2094 //
12730 : GIM_CheckFeatures, GIFBS_InMicroMips,
12731 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12732 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12733 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12734 : // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SRLV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
12735 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRLV_MM,
12736 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12737 : // GIR_Coverage, 2094,
12738 : GIR_Done,
12739 : // Label 828: @31000
12740 : GIM_Reject,
12741 : // Label 821: @31001
12742 : GIM_Reject,
12743 : // Label 815: @31002
12744 : GIM_Try, /*On fail goto*//*Label 829*/ 31129,
12745 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
12746 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12747 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
12748 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
12749 : GIM_Try, /*On fail goto*//*Label 830*/ 31055, // Rule ID 189 //
12750 : GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
12751 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
12752 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
12753 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6,
12754 : // MIs[1] Operand 1
12755 : // No operand predicates
12756 : GIM_CheckIsSafeToFold, /*InsnID*/1,
12757 : // (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSRL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
12758 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRL,
12759 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12760 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
12761 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
12762 : GIR_EraseFromParent, /*InsnID*/0,
12763 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12764 : // GIR_Coverage, 189,
12765 : GIR_Done,
12766 : // Label 830: @31055
12767 : GIM_Try, /*On fail goto*//*Label 831*/ 31113, // Rule ID 1525 //
12768 : GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit,
12769 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
12770 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC,
12771 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
12772 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
12773 : GIM_CheckIsSafeToFold, /*InsnID*/1,
12774 : // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSRLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
12775 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
12776 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
12777 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
12778 : GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // rs
12779 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12780 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRLV,
12781 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12782 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
12783 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12784 : GIR_EraseFromParent, /*InsnID*/0,
12785 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12786 : // GIR_Coverage, 1525,
12787 : GIR_Done,
12788 : // Label 831: @31113
12789 : GIM_Try, /*On fail goto*//*Label 832*/ 31128, // Rule ID 193 //
12790 : GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
12791 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12792 : // (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSRLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
12793 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSRLV,
12794 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12795 : // GIR_Coverage, 193,
12796 : GIR_Done,
12797 : // Label 832: @31128
12798 : GIM_Reject,
12799 : // Label 829: @31129
12800 : GIM_Reject,
12801 : // Label 816: @31130
12802 : GIM_Try, /*On fail goto*//*Label 833*/ 31161, // Rule ID 960 //
12803 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
12804 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12805 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
12806 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
12807 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
12808 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
12809 : // (srl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
12810 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRL_D,
12811 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12812 : // GIR_Coverage, 960,
12813 : GIR_Done,
12814 : // Label 833: @31161
12815 : GIM_Reject,
12816 : // Label 817: @31162
12817 : GIM_Try, /*On fail goto*//*Label 834*/ 31193, // Rule ID 959 //
12818 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
12819 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12820 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
12821 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
12822 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
12823 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
12824 : // (srl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12825 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRL_W,
12826 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12827 : // GIR_Coverage, 959,
12828 : GIR_Done,
12829 : // Label 834: @31193
12830 : GIM_Reject,
12831 : // Label 818: @31194
12832 : GIM_Try, /*On fail goto*//*Label 835*/ 31225, // Rule ID 958 //
12833 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
12834 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
12835 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
12836 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
12837 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
12838 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
12839 : // (srl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12840 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRL_H,
12841 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12842 : // GIR_Coverage, 958,
12843 : GIR_Done,
12844 : // Label 835: @31225
12845 : GIM_Reject,
12846 : // Label 819: @31226
12847 : GIM_Try, /*On fail goto*//*Label 836*/ 31257, // Rule ID 957 //
12848 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
12849 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
12850 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
12851 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
12852 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
12853 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
12854 : // (srl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
12855 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRL_B,
12856 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12857 : // GIR_Coverage, 957,
12858 : GIR_Done,
12859 : // Label 836: @31257
12860 : GIM_Reject,
12861 : // Label 820: @31258
12862 : GIM_Reject,
12863 : // Label 22: @31259
12864 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 843*/ 31739,
12865 : /*GILLT_s32*//*Label 837*/ 31273,
12866 : /*GILLT_s64*//*Label 838*/ 31483, 0,
12867 : /*GILLT_v2s64*//*Label 839*/ 31611, 0,
12868 : /*GILLT_v4s32*//*Label 840*/ 31643,
12869 : /*GILLT_v8s16*//*Label 841*/ 31675,
12870 : /*GILLT_v16s8*//*Label 842*/ 31707,
12871 : // Label 837: @31273
12872 : GIM_Try, /*On fail goto*//*Label 844*/ 31482,
12873 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
12874 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12875 : GIM_Try, /*On fail goto*//*Label 845*/ 31326, // Rule ID 45 //
12876 : GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
12877 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12878 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12879 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
12880 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
12881 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
12882 : // MIs[1] Operand 1
12883 : // No operand predicates
12884 : GIM_CheckIsSafeToFold, /*InsnID*/1,
12885 : // (sra:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (SRA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
12886 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA,
12887 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12888 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
12889 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
12890 : GIR_EraseFromParent, /*InsnID*/0,
12891 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12892 : // GIR_Coverage, 45,
12893 : GIR_Done,
12894 : // Label 845: @31326
12895 : GIM_Try, /*On fail goto*//*Label 846*/ 31369, // Rule ID 1755 //
12896 : GIM_CheckFeatures, GIFBS_InMips16Mode,
12897 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
12898 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
12899 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
12900 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
12901 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
12902 : // MIs[1] Operand 1
12903 : // No operand predicates
12904 : GIM_CheckIsSafeToFold, /*InsnID*/1,
12905 : // (sra:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SraX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
12906 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SraX16,
12907 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
12908 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
12909 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
12910 : GIR_EraseFromParent, /*InsnID*/0,
12911 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12912 : // GIR_Coverage, 1755,
12913 : GIR_Done,
12914 : // Label 846: @31369
12915 : GIM_Try, /*On fail goto*//*Label 847*/ 31412, // Rule ID 2095 //
12916 : GIM_CheckFeatures, GIFBS_InMicroMips,
12917 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12918 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12919 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
12920 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
12921 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
12922 : // MIs[1] Operand 1
12923 : // No operand predicates
12924 : GIM_CheckIsSafeToFold, /*InsnID*/1,
12925 : // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SRA_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
12926 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_MM,
12927 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12928 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12929 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
12930 : GIR_EraseFromParent, /*InsnID*/0,
12931 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12932 : // GIR_Coverage, 2095,
12933 : GIR_Done,
12934 : // Label 847: @31412
12935 : GIM_Try, /*On fail goto*//*Label 848*/ 31435, // Rule ID 48 //
12936 : GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
12937 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12938 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12939 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12940 : // (sra:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SRAV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
12941 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRAV,
12942 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12943 : // GIR_Coverage, 48,
12944 : GIR_Done,
12945 : // Label 848: @31435
12946 : GIM_Try, /*On fail goto*//*Label 849*/ 31458, // Rule ID 1757 //
12947 : GIM_CheckFeatures, GIFBS_InMips16Mode,
12948 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
12949 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
12950 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
12951 : // (sra:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SravRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
12952 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SravRxRy16,
12953 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12954 : // GIR_Coverage, 1757,
12955 : GIR_Done,
12956 : // Label 849: @31458
12957 : GIM_Try, /*On fail goto*//*Label 850*/ 31481, // Rule ID 2096 //
12958 : GIM_CheckFeatures, GIFBS_InMicroMips,
12959 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
12960 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
12961 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
12962 : // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SRAV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
12963 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRAV_MM,
12964 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12965 : // GIR_Coverage, 2096,
12966 : GIR_Done,
12967 : // Label 850: @31481
12968 : GIM_Reject,
12969 : // Label 844: @31482
12970 : GIM_Reject,
12971 : // Label 838: @31483
12972 : GIM_Try, /*On fail goto*//*Label 851*/ 31610,
12973 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
12974 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12975 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
12976 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
12977 : GIM_Try, /*On fail goto*//*Label 852*/ 31536, // Rule ID 190 //
12978 : GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
12979 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
12980 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
12981 : GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6,
12982 : // MIs[1] Operand 1
12983 : // No operand predicates
12984 : GIM_CheckIsSafeToFold, /*InsnID*/1,
12985 : // (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSRA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
12986 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRA,
12987 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
12988 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
12989 : GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
12990 : GIR_EraseFromParent, /*InsnID*/0,
12991 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12992 : // GIR_Coverage, 190,
12993 : GIR_Done,
12994 : // Label 852: @31536
12995 : GIM_Try, /*On fail goto*//*Label 853*/ 31594, // Rule ID 1526 //
12996 : GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit,
12997 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
12998 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC,
12999 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
13000 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
13001 : GIM_CheckIsSafeToFold, /*InsnID*/1,
13002 : // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSRAV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
13003 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
13004 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
13005 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
13006 : GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // rs
13007 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
13008 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRAV,
13009 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13010 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
13011 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13012 : GIR_EraseFromParent, /*InsnID*/0,
13013 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13014 : // GIR_Coverage, 1526,
13015 : GIR_Done,
13016 : // Label 853: @31594
13017 : GIM_Try, /*On fail goto*//*Label 854*/ 31609, // Rule ID 192 //
13018 : GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
13019 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
13020 : // (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSRAV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
13021 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSRAV,
13022 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13023 : // GIR_Coverage, 192,
13024 : GIR_Done,
13025 : // Label 854: @31609
13026 : GIM_Reject,
13027 : // Label 851: @31610
13028 : GIM_Reject,
13029 : // Label 839: @31611
13030 : GIM_Try, /*On fail goto*//*Label 855*/ 31642, // Rule ID 944 //
13031 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
13032 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13033 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
13034 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
13035 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
13036 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
13037 : // (sra:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRA_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
13038 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRA_D,
13039 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13040 : // GIR_Coverage, 944,
13041 : GIR_Done,
13042 : // Label 855: @31642
13043 : GIM_Reject,
13044 : // Label 840: @31643
13045 : GIM_Try, /*On fail goto*//*Label 856*/ 31674, // Rule ID 943 //
13046 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
13047 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13048 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
13049 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
13050 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
13051 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
13052 : // (sra:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRA_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
13053 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRA_W,
13054 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13055 : // GIR_Coverage, 943,
13056 : GIR_Done,
13057 : // Label 856: @31674
13058 : GIM_Reject,
13059 : // Label 841: @31675
13060 : GIM_Try, /*On fail goto*//*Label 857*/ 31706, // Rule ID 942 //
13061 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
13062 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13063 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
13064 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
13065 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
13066 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
13067 : // (sra:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRA_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
13068 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRA_H,
13069 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13070 : // GIR_Coverage, 942,
13071 : GIR_Done,
13072 : // Label 857: @31706
13073 : GIM_Reject,
13074 : // Label 842: @31707
13075 : GIM_Try, /*On fail goto*//*Label 858*/ 31738, // Rule ID 941 //
13076 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
13077 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
13078 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
13079 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
13080 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
13081 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
13082 : // (sra:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRA_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
13083 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRA_B,
13084 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13085 : // GIR_Coverage, 941,
13086 : GIR_Done,
13087 : // Label 858: @31738
13088 : GIM_Reject,
13089 : // Label 843: @31739
13090 : GIM_Reject,
13091 : // Label 23: @31740
13092 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 861*/ 33193,
13093 : /*GILLT_s32*//*Label 859*/ 31748,
13094 : /*GILLT_s64*//*Label 860*/ 32547,
13095 : // Label 859: @31748
13096 : GIM_Try, /*On fail goto*//*Label 862*/ 31787, // Rule ID 267 //
13097 : GIM_CheckFeatures, GIFBS_HasStdEnc_NotMips4_32,
13098 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13099 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13100 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
13101 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
13102 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13103 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
13104 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
13105 : // (select:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F) => (PseudoSELECT_I:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F)
13106 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_I,
13107 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13108 : // GIR_Coverage, 267,
13109 : GIR_Done,
13110 : // Label 862: @31787
13111 : GIM_Try, /*On fail goto*//*Label 863*/ 31826, // Rule ID 269 //
13112 : GIM_CheckFeatures, GIFBS_HasStdEnc_NotMips4_32,
13113 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13114 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13115 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
13116 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
13117 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13118 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
13119 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
13120 : // (select:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F) => (PseudoSELECT_S:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F)
13121 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_S,
13122 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13123 : // GIR_Coverage, 269,
13124 : GIR_Done,
13125 : // Label 863: @31826
13126 : GIM_Try, /*On fail goto*//*Label 864*/ 31882, // Rule ID 306 //
13127 : GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
13128 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13129 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13130 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
13131 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
13132 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGRCCRegClassID,
13133 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
13134 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
13135 : // (select:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) => (SEL_S:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
13136 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SEL_S,
13137 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
13138 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fd_in
13139 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // fs
13140 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft
13141 : GIR_EraseFromParent, /*InsnID*/0,
13142 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13143 : // GIR_Coverage, 306,
13144 : GIR_Done,
13145 : // Label 864: @31882
13146 : GIM_Try, /*On fail goto*//*Label 865*/ 31938, // Rule ID 1179 //
13147 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
13148 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13149 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13150 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
13151 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
13152 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGRCCRegClassID,
13153 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
13154 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
13155 : // (select:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) => (SEL_S_MMR6:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
13156 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SEL_S_MMR6,
13157 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
13158 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fd_in
13159 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // fs
13160 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft
13161 : GIR_EraseFromParent, /*InsnID*/0,
13162 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13163 : // GIR_Coverage, 1179,
13164 : GIR_Done,
13165 : // Label 865: @31938
13166 : GIM_Try, /*On fail goto*//*Label 866*/ 31994, // Rule ID 1576 //
13167 : GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
13168 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13169 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13170 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
13171 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
13172 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13173 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
13174 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
13175 : // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
13176 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I,
13177 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13178 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
13179 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
13180 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
13181 : GIR_EraseFromParent, /*InsnID*/0,
13182 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13183 : // GIR_Coverage, 1576,
13184 : GIR_Done,
13185 : // Label 866: @31994
13186 : GIM_Try, /*On fail goto*//*Label 867*/ 32050, // Rule ID 1615 //
13187 : GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
13188 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
13189 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13190 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
13191 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
13192 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
13193 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
13194 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
13195 : // (select:{ *:[i32] } GPR64:{ *:[i64] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$cond, GPR32:{ *:[i32] }:$F)
13196 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I,
13197 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13198 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
13199 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
13200 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
13201 : GIR_EraseFromParent, /*InsnID*/0,
13202 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13203 : // GIR_Coverage, 1615,
13204 : GIR_Done,
13205 : // Label 867: @32050
13206 : GIM_Try, /*On fail goto*//*Label 868*/ 32106, // Rule ID 1631 //
13207 : GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
13208 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13209 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13210 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
13211 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
13212 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13213 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
13214 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
13215 : // (select:{ *:[f32] } GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$F)
13216 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S,
13217 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
13218 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
13219 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
13220 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
13221 : GIR_EraseFromParent, /*InsnID*/0,
13222 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13223 : // GIR_Coverage, 1631,
13224 : GIR_Done,
13225 : // Label 868: @32106
13226 : GIM_Try, /*On fail goto*//*Label 869*/ 32162, // Rule ID 1644 //
13227 : GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
13228 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
13229 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13230 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
13231 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
13232 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
13233 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
13234 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
13235 : // (select:{ *:[f32] } GPR64:{ *:[i64] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$cond, FGR32:{ *:[f32] }:$F)
13236 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_S,
13237 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
13238 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
13239 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
13240 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
13241 : GIR_EraseFromParent, /*InsnID*/0,
13242 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13243 : // GIR_Coverage, 1644,
13244 : GIR_Done,
13245 : // Label 869: @32162
13246 : GIM_Try, /*On fail goto*//*Label 870*/ 32218, // Rule ID 1802 //
13247 : GIM_CheckFeatures, GIFBS_InMips16Mode,
13248 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13249 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13250 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
13251 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
13252 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
13253 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
13254 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
13255 : // (select:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelBneZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
13256 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelBneZ,
13257 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
13258 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x
13259 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y
13260 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // a
13261 : GIR_EraseFromParent, /*InsnID*/0,
13262 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13263 : // GIR_Coverage, 1802,
13264 : GIR_Done,
13265 : // Label 870: @32218
13266 : GIM_Try, /*On fail goto*//*Label 871*/ 32274, // Rule ID 2146 //
13267 : GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6,
13268 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13269 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13270 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
13271 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
13272 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13273 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
13274 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
13275 : // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
13276 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM,
13277 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13278 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
13279 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
13280 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
13281 : GIR_EraseFromParent, /*InsnID*/0,
13282 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13283 : // GIR_Coverage, 2146,
13284 : GIR_Done,
13285 : // Label 871: @32274
13286 : GIM_Try, /*On fail goto*//*Label 872*/ 32330, // Rule ID 2160 //
13287 : GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
13288 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13289 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13290 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
13291 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
13292 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13293 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
13294 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
13295 : // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
13296 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM,
13297 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13298 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
13299 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
13300 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
13301 : GIR_EraseFromParent, /*InsnID*/0,
13302 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13303 : // GIR_Coverage, 2160,
13304 : GIR_Done,
13305 : // Label 872: @32330
13306 : GIM_Try, /*On fail goto*//*Label 873*/ 32386, // Rule ID 2189 //
13307 : GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
13308 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13309 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13310 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
13311 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
13312 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13313 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
13314 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
13315 : // (select:{ *:[f32] } GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$F)
13316 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S_MM,
13317 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
13318 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
13319 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
13320 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
13321 : GIR_EraseFromParent, /*InsnID*/0,
13322 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13323 : // GIR_Coverage, 2189,
13324 : GIR_Done,
13325 : // Label 873: @32386
13326 : GIM_Try, /*On fail goto*//*Label 874*/ 32466, // Rule ID 1713 //
13327 : GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
13328 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13329 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13330 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
13331 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
13332 : // (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) => (OR:{ *:[i32] } (SELNEZ:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond))
13333 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
13334 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
13335 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SELEQZ,
13336 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
13337 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
13338 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
13339 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
13340 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ,
13341 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
13342 : GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
13343 : GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
13344 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
13345 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR,
13346 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13347 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13348 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
13349 : GIR_EraseFromParent, /*InsnID*/0,
13350 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13351 : // GIR_Coverage, 1713,
13352 : GIR_Done,
13353 : // Label 874: @32466
13354 : GIM_Try, /*On fail goto*//*Label 875*/ 32546, // Rule ID 2206 //
13355 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
13356 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13357 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13358 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
13359 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
13360 : // (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) => (OR_MM:{ *:[i32] } (SELNEZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond))
13361 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
13362 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
13363 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SELEQZ_MMR6,
13364 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
13365 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
13366 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
13367 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
13368 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ_MMR6,
13369 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
13370 : GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
13371 : GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
13372 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
13373 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR_MM,
13374 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13375 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13376 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
13377 : GIR_EraseFromParent, /*InsnID*/0,
13378 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13379 : // GIR_Coverage, 2206,
13380 : GIR_Done,
13381 : // Label 875: @32546
13382 : GIM_Reject,
13383 : // Label 860: @32547
13384 : GIM_Try, /*On fail goto*//*Label 876*/ 32586, // Rule ID 268 //
13385 : GIM_CheckFeatures, GIFBS_HasStdEnc_NotMips4_32,
13386 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13387 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
13388 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
13389 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
13390 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13391 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
13392 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
13393 : // (select:{ *:[i64] } GPR32Opnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F) => (PseudoSELECT_I64:{ *:[i64] } GPR32Opnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F)
13394 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_I64,
13395 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13396 : // GIR_Coverage, 268,
13397 : GIR_Done,
13398 : // Label 876: @32586
13399 : GIM_Try, /*On fail goto*//*Label 877*/ 32625, // Rule ID 270 //
13400 : GIM_CheckFeatures, GIFBS_HasStdEnc_NotFP64bit_NotMips4_32,
13401 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13402 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
13403 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
13404 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
13405 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13406 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
13407 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
13408 : // (select:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F) => (PseudoSELECT_D32:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F)
13409 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_D32,
13410 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13411 : // GIR_Coverage, 270,
13412 : GIR_Done,
13413 : // Label 877: @32625
13414 : GIM_Try, /*On fail goto*//*Label 878*/ 32664, // Rule ID 271 //
13415 : GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_NotMips4_32,
13416 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13417 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
13418 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
13419 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
13420 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13421 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
13422 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
13423 : // (select:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F) => (PseudoSELECT_D64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F)
13424 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_D64,
13425 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13426 : // GIR_Coverage, 271,
13427 : GIR_Done,
13428 : // Label 878: @32664
13429 : GIM_Try, /*On fail goto*//*Label 879*/ 32720, // Rule ID 1612 //
13430 : GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
13431 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13432 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
13433 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
13434 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
13435 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13436 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
13437 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
13438 : // (select:{ *:[i64] } GPR32:{ *:[i32] }:$cond, GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$cond, GPR64:{ *:[i64] }:$F)
13439 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I64,
13440 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13441 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
13442 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
13443 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
13444 : GIR_EraseFromParent, /*InsnID*/0,
13445 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13446 : // GIR_Coverage, 1612,
13447 : GIR_Done,
13448 : // Label 879: @32720
13449 : GIM_Try, /*On fail goto*//*Label 880*/ 32776, // Rule ID 1618 //
13450 : GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
13451 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
13452 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
13453 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
13454 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
13455 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
13456 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
13457 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
13458 : // (select:{ *:[i64] } GPR64:{ *:[i64] }:$cond, GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$cond, GPR64:{ *:[i64] }:$F)
13459 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I64,
13460 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13461 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
13462 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
13463 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
13464 : GIR_EraseFromParent, /*InsnID*/0,
13465 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13466 : // GIR_Coverage, 1618,
13467 : GIR_Done,
13468 : // Label 880: @32776
13469 : GIM_Try, /*On fail goto*//*Label 881*/ 32832, // Rule ID 1657 //
13470 : GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
13471 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13472 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
13473 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
13474 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
13475 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13476 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
13477 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
13478 : // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$F)
13479 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32,
13480 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
13481 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
13482 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
13483 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
13484 : GIR_EraseFromParent, /*InsnID*/0,
13485 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13486 : // GIR_Coverage, 1657,
13487 : GIR_Done,
13488 : // Label 881: @32832
13489 : GIM_Try, /*On fail goto*//*Label 882*/ 32888, // Rule ID 1680 //
13490 : GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
13491 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13492 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
13493 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
13494 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
13495 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13496 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
13497 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
13498 : // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, FGR64:{ *:[f64] }:$F)
13499 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D64,
13500 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
13501 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
13502 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
13503 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
13504 : GIR_EraseFromParent, /*InsnID*/0,
13505 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13506 : // GIR_Coverage, 1680,
13507 : GIR_Done,
13508 : // Label 882: @32888
13509 : GIM_Try, /*On fail goto*//*Label 883*/ 32944, // Rule ID 1683 //
13510 : GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
13511 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
13512 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
13513 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
13514 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
13515 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
13516 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
13517 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
13518 : // (select:{ *:[f64] } GPR64:{ *:[i64] }:$cond, FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$cond, FGR64:{ *:[f64] }:$F)
13519 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_D64,
13520 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
13521 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
13522 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
13523 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
13524 : GIR_EraseFromParent, /*InsnID*/0,
13525 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13526 : // GIR_Coverage, 1683,
13527 : GIR_Done,
13528 : // Label 883: @32944
13529 : GIM_Try, /*On fail goto*//*Label 884*/ 33000, // Rule ID 2202 //
13530 : GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
13531 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13532 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
13533 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
13534 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
13535 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
13536 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
13537 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
13538 : // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$F)
13539 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32_MM,
13540 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
13541 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
13542 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
13543 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
13544 : GIR_EraseFromParent, /*InsnID*/0,
13545 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13546 : // GIR_Coverage, 2202,
13547 : GIR_Done,
13548 : // Label 884: @33000
13549 : GIM_Try, /*On fail goto*//*Label 885*/ 33080, // Rule ID 1716 //
13550 : GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc,
13551 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
13552 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
13553 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
13554 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
13555 : // (select:{ *:[i64] } i64:{ *:[i64] }:$cond, i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) => (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$cond), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, i64:{ *:[i64] }:$cond))
13556 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
13557 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
13558 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SELEQZ64,
13559 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
13560 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
13561 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
13562 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
13563 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ64,
13564 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
13565 : GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
13566 : GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
13567 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
13568 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR64,
13569 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13570 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13571 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
13572 : GIR_EraseFromParent, /*InsnID*/0,
13573 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13574 : // GIR_Coverage, 1716,
13575 : GIR_Done,
13576 : // Label 885: @33080
13577 : GIM_Try, /*On fail goto*//*Label 886*/ 33192, // Rule ID 1727 //
13578 : GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc,
13579 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13580 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
13581 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
13582 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
13583 : // (select:{ *:[i64] } i32:{ *:[i32] }:$cond, i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) => (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)))
13584 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
13585 : GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
13586 : GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
13587 : GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
13588 : GIR_BuildMI, /*InsnID*/4, /*Opcode*/Mips::SLL64_32,
13589 : GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
13590 : GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // cond
13591 : GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
13592 : GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SELEQZ64,
13593 : GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
13594 : GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // f
13595 : GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
13596 : GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
13597 : GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SLL64_32,
13598 : GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
13599 : GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
13600 : GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
13601 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ64,
13602 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
13603 : GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
13604 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
13605 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
13606 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR64,
13607 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
13608 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13609 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0,
13610 : GIR_EraseFromParent, /*InsnID*/0,
13611 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13612 : // GIR_Coverage, 1727,
13613 : GIR_Done,
13614 : // Label 886: @33192
13615 : GIM_Reject,
13616 : // Label 861: @33193
13617 : GIM_Reject,
13618 : // Label 24: @33194
13619 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 891*/ 34072,
13620 : /*GILLT_s32*//*Label 887*/ 33206,
13621 : /*GILLT_s64*//*Label 888*/ 33406, 0,
13622 : /*GILLT_v2s64*//*Label 889*/ 33754, 0,
13623 : /*GILLT_v4s32*//*Label 890*/ 33913,
13624 : // Label 887: @33206
13625 : GIM_Try, /*On fail goto*//*Label 892*/ 33405,
13626 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13627 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13628 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
13629 : GIM_Try, /*On fail goto*//*Label 893*/ 33277, // Rule ID 145 //
13630 : GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
13631 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13632 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
13633 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
13634 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
13635 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
13636 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
13637 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
13638 : GIM_CheckIsSafeToFold, /*InsnID*/1,
13639 : // (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
13640 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_S,
13641 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
13642 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr
13643 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
13644 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
13645 : GIR_EraseFromParent, /*InsnID*/0,
13646 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13647 : // GIR_Coverage, 145,
13648 : GIR_Done,
13649 : // Label 893: @33277
13650 : GIM_Try, /*On fail goto*//*Label 894*/ 33334, // Rule ID 2260 //
13651 : GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
13652 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
13653 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13654 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
13655 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
13656 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
13657 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
13658 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
13659 : GIM_CheckIsSafeToFold, /*InsnID*/1,
13660 : // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
13661 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_S,
13662 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
13663 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fr
13664 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
13665 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
13666 : GIR_EraseFromParent, /*InsnID*/0,
13667 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13668 : // GIR_Coverage, 2260,
13669 : GIR_Done,
13670 : // Label 894: @33334
13671 : GIM_Try, /*On fail goto*//*Label 895*/ 33353, // Rule ID 133 //
13672 : GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
13673 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
13674 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
13675 : // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
13676 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_S,
13677 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13678 : // GIR_Coverage, 133,
13679 : GIR_Done,
13680 : // Label 895: @33353
13681 : GIM_Try, /*On fail goto*//*Label 896*/ 33372, // Rule ID 1098 //
13682 : GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
13683 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
13684 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
13685 : // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
13686 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_S_MM,
13687 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13688 : // GIR_Coverage, 1098,
13689 : GIR_Done,
13690 : // Label 896: @33372
13691 : GIM_Try, /*On fail goto*//*Label 897*/ 33404, // Rule ID 1154 //
13692 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
13693 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
13694 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
13695 : // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
13696 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FADD_S_MMR6,
13697 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
13698 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft
13699 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs
13700 : GIR_EraseFromParent, /*InsnID*/0,
13701 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13702 : // GIR_Coverage, 1154,
13703 : GIR_Done,
13704 : // Label 897: @33404
13705 : GIM_Reject,
13706 : // Label 892: @33405
13707 : GIM_Reject,
13708 : // Label 888: @33406
13709 : GIM_Try, /*On fail goto*//*Label 898*/ 33753,
13710 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
13711 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
13712 : GIM_Try, /*On fail goto*//*Label 899*/ 33477, // Rule ID 147 //
13713 : GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
13714 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
13715 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13716 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
13717 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
13718 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
13719 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
13720 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
13721 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
13722 : GIM_CheckIsSafeToFold, /*InsnID*/1,
13723 : // (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
13724 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D32,
13725 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
13726 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr
13727 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
13728 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
13729 : GIR_EraseFromParent, /*InsnID*/0,
13730 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13731 : // GIR_Coverage, 147,
13732 : GIR_Done,
13733 : // Label 899: @33477
13734 : GIM_Try, /*On fail goto*//*Label 900*/ 33538, // Rule ID 149 //
13735 : GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
13736 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
13737 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13738 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
13739 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
13740 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
13741 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
13742 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
13743 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
13744 : GIM_CheckIsSafeToFold, /*InsnID*/1,
13745 : // (fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
13746 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D64,
13747 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
13748 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr
13749 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
13750 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
13751 : GIR_EraseFromParent, /*InsnID*/0,
13752 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13753 : // GIR_Coverage, 149,
13754 : GIR_Done,
13755 : // Label 900: @33538
13756 : GIM_Try, /*On fail goto*//*Label 901*/ 33599, // Rule ID 2261 //
13757 : GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
13758 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
13759 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
13760 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13761 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
13762 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
13763 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
13764 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
13765 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
13766 : GIM_CheckIsSafeToFold, /*InsnID*/1,
13767 : // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
13768 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D32,
13769 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
13770 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fr
13771 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
13772 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
13773 : GIR_EraseFromParent, /*InsnID*/0,
13774 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13775 : // GIR_Coverage, 2261,
13776 : GIR_Done,
13777 : // Label 901: @33599
13778 : GIM_Try, /*On fail goto*//*Label 902*/ 33660, // Rule ID 2262 //
13779 : GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
13780 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
13781 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
13782 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13783 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
13784 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
13785 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
13786 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
13787 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
13788 : GIM_CheckIsSafeToFold, /*InsnID*/1,
13789 : // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
13790 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D64,
13791 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
13792 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fr
13793 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
13794 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
13795 : GIR_EraseFromParent, /*InsnID*/0,
13796 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13797 : // GIR_Coverage, 2262,
13798 : GIR_Done,
13799 : // Label 902: @33660
13800 : GIM_Try, /*On fail goto*//*Label 903*/ 33683, // Rule ID 134 //
13801 : GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
13802 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
13803 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
13804 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
13805 : // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
13806 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D32,
13807 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13808 : // GIR_Coverage, 134,
13809 : GIR_Done,
13810 : // Label 903: @33683
13811 : GIM_Try, /*On fail goto*//*Label 904*/ 33706, // Rule ID 135 //
13812 : GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
13813 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
13814 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
13815 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
13816 : // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
13817 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D64,
13818 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13819 : // GIR_Coverage, 135,
13820 : GIR_Done,
13821 : // Label 904: @33706
13822 : GIM_Try, /*On fail goto*//*Label 905*/ 33729, // Rule ID 1102 //
13823 : GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
13824 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
13825 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
13826 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
13827 : // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
13828 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D32_MM,
13829 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13830 : // GIR_Coverage, 1102,
13831 : GIR_Done,
13832 : // Label 905: @33729
13833 : GIM_Try, /*On fail goto*//*Label 906*/ 33752, // Rule ID 1103 //
13834 : GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
13835 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
13836 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
13837 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
13838 : // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FADD_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
13839 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D64_MM,
13840 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13841 : // GIR_Coverage, 1103,
13842 : GIR_Done,
13843 : // Label 906: @33752
13844 : GIM_Reject,
13845 : // Label 898: @33753
13846 : GIM_Reject,
13847 : // Label 889: @33754
13848 : GIM_Try, /*On fail goto*//*Label 907*/ 33912,
13849 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13850 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
13851 : GIM_Try, /*On fail goto*//*Label 908*/ 33826, // Rule ID 2367 //
13852 : GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
13853 : GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
13854 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13855 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
13856 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
13857 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
13858 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
13859 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
13860 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
13861 : GIM_CheckIsSafeToFold, /*InsnID*/1,
13862 : // (fadd:{ *:[v2f64] } (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt), MSA128DOpnd:{ *:[v2f64] }:$wd) => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
13863 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_D,
13864 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd
13865 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd
13866 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
13867 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
13868 : GIR_EraseFromParent, /*InsnID*/0,
13869 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13870 : // GIR_Coverage, 2367,
13871 : GIR_Done,
13872 : // Label 908: @33826
13873 : GIM_Try, /*On fail goto*//*Label 909*/ 33888, // Rule ID 1911 //
13874 : GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
13875 : GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
13876 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
13877 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13878 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
13879 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
13880 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
13881 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
13882 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
13883 : GIM_CheckIsSafeToFold, /*InsnID*/1,
13884 : // (fadd:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)) => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
13885 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_D,
13886 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
13887 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
13888 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
13889 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
13890 : GIR_EraseFromParent, /*InsnID*/0,
13891 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13892 : // GIR_Coverage, 1911,
13893 : GIR_Done,
13894 : // Label 909: @33888
13895 : GIM_Try, /*On fail goto*//*Label 910*/ 33911, // Rule ID 639 //
13896 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
13897 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
13898 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
13899 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
13900 : // (fadd:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
13901 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D,
13902 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13903 : // GIR_Coverage, 639,
13904 : GIR_Done,
13905 : // Label 910: @33911
13906 : GIM_Reject,
13907 : // Label 907: @33912
13908 : GIM_Reject,
13909 : // Label 890: @33913
13910 : GIM_Try, /*On fail goto*//*Label 911*/ 34071,
13911 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13912 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
13913 : GIM_Try, /*On fail goto*//*Label 912*/ 33985, // Rule ID 2366 //
13914 : GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
13915 : GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
13916 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13917 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
13918 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
13919 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
13920 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
13921 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
13922 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
13923 : GIM_CheckIsSafeToFold, /*InsnID*/1,
13924 : // (fadd:{ *:[v4f32] } (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt), MSA128WOpnd:{ *:[v4f32] }:$wd) => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
13925 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_W,
13926 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd
13927 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd
13928 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
13929 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
13930 : GIR_EraseFromParent, /*InsnID*/0,
13931 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13932 : // GIR_Coverage, 2366,
13933 : GIR_Done,
13934 : // Label 912: @33985
13935 : GIM_Try, /*On fail goto*//*Label 913*/ 34047, // Rule ID 1910 //
13936 : GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
13937 : GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
13938 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
13939 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13940 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
13941 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
13942 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
13943 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
13944 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
13945 : GIM_CheckIsSafeToFold, /*InsnID*/1,
13946 : // (fadd:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)) => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
13947 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_W,
13948 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
13949 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
13950 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
13951 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
13952 : GIR_EraseFromParent, /*InsnID*/0,
13953 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13954 : // GIR_Coverage, 1910,
13955 : GIR_Done,
13956 : // Label 913: @34047
13957 : GIM_Try, /*On fail goto*//*Label 914*/ 34070, // Rule ID 638 //
13958 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
13959 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
13960 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
13961 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
13962 : // (fadd:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
13963 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_W,
13964 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13965 : // GIR_Coverage, 638,
13966 : GIR_Done,
13967 : // Label 914: @34070
13968 : GIM_Reject,
13969 : // Label 911: @34071
13970 : GIM_Reject,
13971 : // Label 891: @34072
13972 : GIM_Reject,
13973 : // Label 25: @34073
13974 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 919*/ 34648,
13975 : /*GILLT_s32*//*Label 915*/ 34085,
13976 : /*GILLT_s64*//*Label 916*/ 34228, 0,
13977 : /*GILLT_v2s64*//*Label 917*/ 34454, 0,
13978 : /*GILLT_v4s32*//*Label 918*/ 34551,
13979 : // Label 915: @34085
13980 : GIM_Try, /*On fail goto*//*Label 920*/ 34227,
13981 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13982 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13983 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
13984 : GIM_Try, /*On fail goto*//*Label 921*/ 34156, // Rule ID 146 //
13985 : GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
13986 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13987 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
13988 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
13989 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
13990 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
13991 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
13992 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
13993 : GIM_CheckIsSafeToFold, /*InsnID*/1,
13994 : // (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
13995 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_S,
13996 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
13997 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr
13998 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
13999 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
14000 : GIR_EraseFromParent, /*InsnID*/0,
14001 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14002 : // GIR_Coverage, 146,
14003 : GIR_Done,
14004 : // Label 921: @34156
14005 : GIM_Try, /*On fail goto*//*Label 922*/ 34175, // Rule ID 142 //
14006 : GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
14007 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
14008 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
14009 : // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
14010 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_S,
14011 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14012 : // GIR_Coverage, 142,
14013 : GIR_Done,
14014 : // Label 922: @34175
14015 : GIM_Try, /*On fail goto*//*Label 923*/ 34194, // Rule ID 1101 //
14016 : GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
14017 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
14018 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
14019 : // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
14020 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_S_MM,
14021 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14022 : // GIR_Coverage, 1101,
14023 : GIR_Done,
14024 : // Label 923: @34194
14025 : GIM_Try, /*On fail goto*//*Label 924*/ 34226, // Rule ID 1155 //
14026 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
14027 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
14028 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
14029 : // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
14030 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUB_S_MMR6,
14031 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
14032 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft
14033 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs
14034 : GIR_EraseFromParent, /*InsnID*/0,
14035 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14036 : // GIR_Coverage, 1155,
14037 : GIR_Done,
14038 : // Label 924: @34226
14039 : GIM_Reject,
14040 : // Label 920: @34227
14041 : GIM_Reject,
14042 : // Label 916: @34228
14043 : GIM_Try, /*On fail goto*//*Label 925*/ 34453,
14044 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
14045 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
14046 : GIM_Try, /*On fail goto*//*Label 926*/ 34299, // Rule ID 148 //
14047 : GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
14048 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
14049 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14050 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
14051 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
14052 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
14053 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
14054 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
14055 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
14056 : GIM_CheckIsSafeToFold, /*InsnID*/1,
14057 : // (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
14058 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_D32,
14059 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
14060 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr
14061 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
14062 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
14063 : GIR_EraseFromParent, /*InsnID*/0,
14064 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14065 : // GIR_Coverage, 148,
14066 : GIR_Done,
14067 : // Label 926: @34299
14068 : GIM_Try, /*On fail goto*//*Label 927*/ 34360, // Rule ID 150 //
14069 : GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
14070 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
14071 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14072 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
14073 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
14074 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
14075 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
14076 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
14077 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
14078 : GIM_CheckIsSafeToFold, /*InsnID*/1,
14079 : // (fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
14080 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_D64,
14081 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
14082 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr
14083 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
14084 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
14085 : GIR_EraseFromParent, /*InsnID*/0,
14086 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14087 : // GIR_Coverage, 150,
14088 : GIR_Done,
14089 : // Label 927: @34360
14090 : GIM_Try, /*On fail goto*//*Label 928*/ 34383, // Rule ID 143 //
14091 : GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
14092 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
14093 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
14094 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
14095 : // (fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
14096 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D32,
14097 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14098 : // GIR_Coverage, 143,
14099 : GIR_Done,
14100 : // Label 928: @34383
14101 : GIM_Try, /*On fail goto*//*Label 929*/ 34406, // Rule ID 144 //
14102 : GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
14103 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
14104 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
14105 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
14106 : // (fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
14107 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D64,
14108 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14109 : // GIR_Coverage, 144,
14110 : GIR_Done,
14111 : // Label 929: @34406
14112 : GIM_Try, /*On fail goto*//*Label 930*/ 34429, // Rule ID 1108 //
14113 : GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
14114 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
14115 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
14116 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
14117 : // (fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
14118 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D32_MM,
14119 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14120 : // GIR_Coverage, 1108,
14121 : GIR_Done,
14122 : // Label 930: @34429
14123 : GIM_Try, /*On fail goto*//*Label 931*/ 34452, // Rule ID 1109 //
14124 : GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
14125 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
14126 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
14127 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
14128 : // (fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
14129 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D64_MM,
14130 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14131 : // GIR_Coverage, 1109,
14132 : GIR_Done,
14133 : // Label 931: @34452
14134 : GIM_Reject,
14135 : // Label 925: @34453
14136 : GIM_Reject,
14137 : // Label 917: @34454
14138 : GIM_Try, /*On fail goto*//*Label 932*/ 34550,
14139 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
14140 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
14141 : GIM_Try, /*On fail goto*//*Label 933*/ 34526, // Rule ID 1909 //
14142 : GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
14143 : GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
14144 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
14145 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14146 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
14147 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
14148 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
14149 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
14150 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
14151 : GIM_CheckIsSafeToFold, /*InsnID*/1,
14152 : // (fsub:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)) => (FMSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
14153 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMSUB_D,
14154 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
14155 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
14156 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
14157 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
14158 : GIR_EraseFromParent, /*InsnID*/0,
14159 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14160 : // GIR_Coverage, 1909,
14161 : GIR_Done,
14162 : // Label 933: @34526
14163 : GIM_Try, /*On fail goto*//*Label 934*/ 34549, // Rule ID 727 //
14164 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
14165 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
14166 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
14167 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
14168 : // (fsub:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
14169 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D,
14170 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14171 : // GIR_Coverage, 727,
14172 : GIR_Done,
14173 : // Label 934: @34549
14174 : GIM_Reject,
14175 : // Label 932: @34550
14176 : GIM_Reject,
14177 : // Label 918: @34551
14178 : GIM_Try, /*On fail goto*//*Label 935*/ 34647,
14179 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
14180 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14181 : GIM_Try, /*On fail goto*//*Label 936*/ 34623, // Rule ID 1908 //
14182 : GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
14183 : GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
14184 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
14185 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14186 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
14187 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14188 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14189 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
14190 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
14191 : GIM_CheckIsSafeToFold, /*InsnID*/1,
14192 : // (fsub:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)) => (FMSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
14193 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMSUB_W,
14194 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
14195 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
14196 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
14197 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
14198 : GIR_EraseFromParent, /*InsnID*/0,
14199 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14200 : // GIR_Coverage, 1908,
14201 : GIR_Done,
14202 : // Label 936: @34623
14203 : GIM_Try, /*On fail goto*//*Label 937*/ 34646, // Rule ID 726 //
14204 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
14205 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
14206 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
14207 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
14208 : // (fsub:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
14209 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_W,
14210 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14211 : // GIR_Coverage, 726,
14212 : GIR_Done,
14213 : // Label 937: @34646
14214 : GIM_Reject,
14215 : // Label 935: @34647
14216 : GIM_Reject,
14217 : // Label 919: @34648
14218 : GIM_Reject,
14219 : // Label 26: @34649
14220 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 942*/ 35085,
14221 : /*GILLT_s32*//*Label 938*/ 34661,
14222 : /*GILLT_s64*//*Label 939*/ 34731, 0,
14223 : /*GILLT_v2s64*//*Label 940*/ 34835, 0,
14224 : /*GILLT_v4s32*//*Label 941*/ 34960,
14225 : // Label 938: @34661
14226 : GIM_Try, /*On fail goto*//*Label 943*/ 34730,
14227 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
14228 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14229 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
14230 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
14231 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
14232 : GIM_Try, /*On fail goto*//*Label 944*/ 34694, // Rule ID 139 //
14233 : GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
14234 : // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
14235 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_S,
14236 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14237 : // GIR_Coverage, 139,
14238 : GIR_Done,
14239 : // Label 944: @34694
14240 : GIM_Try, /*On fail goto*//*Label 945*/ 34705, // Rule ID 1100 //
14241 : GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
14242 : // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
14243 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_S_MM,
14244 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14245 : // GIR_Coverage, 1100,
14246 : GIR_Done,
14247 : // Label 945: @34705
14248 : GIM_Try, /*On fail goto*//*Label 946*/ 34729, // Rule ID 1156 //
14249 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
14250 : // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
14251 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMUL_S_MMR6,
14252 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
14253 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft
14254 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs
14255 : GIR_EraseFromParent, /*InsnID*/0,
14256 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14257 : // GIR_Coverage, 1156,
14258 : GIR_Done,
14259 : // Label 946: @34729
14260 : GIM_Reject,
14261 : // Label 943: @34730
14262 : GIM_Reject,
14263 : // Label 939: @34731
14264 : GIM_Try, /*On fail goto*//*Label 947*/ 34834,
14265 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
14266 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
14267 : GIM_Try, /*On fail goto*//*Label 948*/ 34764, // Rule ID 140 //
14268 : GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
14269 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
14270 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
14271 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
14272 : // (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
14273 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D32,
14274 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14275 : // GIR_Coverage, 140,
14276 : GIR_Done,
14277 : // Label 948: @34764
14278 : GIM_Try, /*On fail goto*//*Label 949*/ 34787, // Rule ID 141 //
14279 : GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
14280 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
14281 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
14282 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
14283 : // (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
14284 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D64,
14285 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14286 : // GIR_Coverage, 141,
14287 : GIR_Done,
14288 : // Label 949: @34787
14289 : GIM_Try, /*On fail goto*//*Label 950*/ 34810, // Rule ID 1106 //
14290 : GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
14291 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
14292 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
14293 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
14294 : // (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
14295 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D32_MM,
14296 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14297 : // GIR_Coverage, 1106,
14298 : GIR_Done,
14299 : // Label 950: @34810
14300 : GIM_Try, /*On fail goto*//*Label 951*/ 34833, // Rule ID 1107 //
14301 : GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
14302 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
14303 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
14304 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
14305 : // (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
14306 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D64_MM,
14307 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14308 : // GIR_Coverage, 1107,
14309 : GIR_Done,
14310 : // Label 951: @34833
14311 : GIM_Reject,
14312 : // Label 947: @34834
14313 : GIM_Reject,
14314 : // Label 940: @34835
14315 : GIM_Try, /*On fail goto*//*Label 952*/ 34959,
14316 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
14317 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
14318 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
14319 : GIM_Try, /*On fail goto*//*Label 953*/ 34894, // Rule ID 2308 //
14320 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
14321 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14322 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FEXP2,
14323 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
14324 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
14325 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
14326 : GIM_CheckIsSafeToFold, /*InsnID*/1,
14327 : // (fmul:{ *:[v2f64] } (fexp2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wt), MSA128DOpnd:{ *:[v2f64] }:$ws) => (FEXP2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
14328 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_D,
14329 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
14330 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
14331 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
14332 : GIR_EraseFromParent, /*InsnID*/0,
14333 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14334 : // GIR_Coverage, 2308,
14335 : GIR_Done,
14336 : // Label 953: @34894
14337 : GIM_Try, /*On fail goto*//*Label 954*/ 34939, // Rule ID 669 //
14338 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
14339 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
14340 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14341 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FEXP2,
14342 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
14343 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
14344 : GIM_CheckIsSafeToFold, /*InsnID*/1,
14345 : // (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, (fexp2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wt)) => (FEXP2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
14346 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_D,
14347 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
14348 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
14349 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
14350 : GIR_EraseFromParent, /*InsnID*/0,
14351 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14352 : // GIR_Coverage, 669,
14353 : GIR_Done,
14354 : // Label 954: @34939
14355 : GIM_Try, /*On fail goto*//*Label 955*/ 34958, // Rule ID 705 //
14356 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
14357 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
14358 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
14359 : // (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMUL_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
14360 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D,
14361 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14362 : // GIR_Coverage, 705,
14363 : GIR_Done,
14364 : // Label 955: @34958
14365 : GIM_Reject,
14366 : // Label 952: @34959
14367 : GIM_Reject,
14368 : // Label 941: @34960
14369 : GIM_Try, /*On fail goto*//*Label 956*/ 35084,
14370 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
14371 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14372 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
14373 : GIM_Try, /*On fail goto*//*Label 957*/ 35019, // Rule ID 2307 //
14374 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
14375 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14376 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FEXP2,
14377 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14378 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
14379 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
14380 : GIM_CheckIsSafeToFold, /*InsnID*/1,
14381 : // (fmul:{ *:[v4f32] } (fexp2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wt), MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXP2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
14382 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_W,
14383 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
14384 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
14385 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
14386 : GIR_EraseFromParent, /*InsnID*/0,
14387 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14388 : // GIR_Coverage, 2307,
14389 : GIR_Done,
14390 : // Label 957: @35019
14391 : GIM_Try, /*On fail goto*//*Label 958*/ 35064, // Rule ID 668 //
14392 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
14393 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
14394 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14395 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FEXP2,
14396 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14397 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
14398 : GIM_CheckIsSafeToFold, /*InsnID*/1,
14399 : // (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, (fexp2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wt)) => (FEXP2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
14400 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_W,
14401 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
14402 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
14403 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
14404 : GIR_EraseFromParent, /*InsnID*/0,
14405 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14406 : // GIR_Coverage, 668,
14407 : GIR_Done,
14408 : // Label 958: @35064
14409 : GIM_Try, /*On fail goto*//*Label 959*/ 35083, // Rule ID 704 //
14410 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
14411 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
14412 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
14413 : // (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMUL_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
14414 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_W,
14415 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14416 : // GIR_Coverage, 704,
14417 : GIR_Done,
14418 : // Label 959: @35083
14419 : GIM_Reject,
14420 : // Label 956: @35084
14421 : GIM_Reject,
14422 : // Label 942: @35085
14423 : GIM_Reject,
14424 : // Label 27: @35086
14425 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 962*/ 35175,
14426 : /*GILLT_v2s64*//*Label 960*/ 35095, 0,
14427 : /*GILLT_v4s32*//*Label 961*/ 35135,
14428 : // Label 960: @35095
14429 : GIM_Try, /*On fail goto*//*Label 963*/ 35134, // Rule ID 693 //
14430 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
14431 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
14432 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
14433 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
14434 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
14435 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
14436 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
14437 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
14438 : // (fma:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
14439 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMADD_D,
14440 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14441 : // GIR_Coverage, 693,
14442 : GIR_Done,
14443 : // Label 963: @35134
14444 : GIM_Reject,
14445 : // Label 961: @35135
14446 : GIM_Try, /*On fail goto*//*Label 964*/ 35174, // Rule ID 692 //
14447 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
14448 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
14449 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14450 : GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
14451 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
14452 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
14453 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
14454 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
14455 : // (fma:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
14456 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMADD_W,
14457 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14458 : // GIR_Coverage, 692,
14459 : GIR_Done,
14460 : // Label 964: @35174
14461 : GIM_Reject,
14462 : // Label 962: @35175
14463 : GIM_Reject,
14464 : // Label 28: @35176
14465 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 969*/ 35426,
14466 : /*GILLT_s32*//*Label 965*/ 35188,
14467 : /*GILLT_s64*//*Label 966*/ 35258, 0,
14468 : /*GILLT_v2s64*//*Label 967*/ 35362, 0,
14469 : /*GILLT_v4s32*//*Label 968*/ 35394,
14470 : // Label 965: @35188
14471 : GIM_Try, /*On fail goto*//*Label 970*/ 35257,
14472 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
14473 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
14474 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
14475 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
14476 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
14477 : GIM_Try, /*On fail goto*//*Label 971*/ 35221, // Rule ID 136 //
14478 : GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
14479 : // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
14480 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_S,
14481 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14482 : // GIR_Coverage, 136,
14483 : GIR_Done,
14484 : // Label 971: @35221
14485 : GIM_Try, /*On fail goto*//*Label 972*/ 35232, // Rule ID 1099 //
14486 : GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
14487 : // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
14488 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_S_MM,
14489 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14490 : // GIR_Coverage, 1099,
14491 : GIR_Done,
14492 : // Label 972: @35232
14493 : GIM_Try, /*On fail goto*//*Label 973*/ 35256, // Rule ID 1157 //
14494 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
14495 : // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
14496 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FDIV_S_MMR6,
14497 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
14498 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft
14499 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs
14500 : GIR_EraseFromParent, /*InsnID*/0,
14501 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14502 : // GIR_Coverage, 1157,
14503 : GIR_Done,
14504 : // Label 973: @35256
14505 : GIM_Reject,
14506 : // Label 970: @35257
14507 : GIM_Reject,
14508 : // Label 966: @35258
14509 : GIM_Try, /*On fail goto*//*Label 974*/ 35361,
14510 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
14511 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
14512 : GIM_Try, /*On fail goto*//*Label 975*/ 35291, // Rule ID 137 //
14513 : GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
14514 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
14515 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
14516 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
14517 : // (fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
14518 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D32,
14519 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14520 : // GIR_Coverage, 137,
14521 : GIR_Done,
14522 : // Label 975: @35291
14523 : GIM_Try, /*On fail goto*//*Label 976*/ 35314, // Rule ID 138 //
14524 : GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
14525 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
14526 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
14527 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
14528 : // (fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
14529 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D64,
14530 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14531 : // GIR_Coverage, 138,
14532 : GIR_Done,
14533 : // Label 976: @35314
14534 : GIM_Try, /*On fail goto*//*Label 977*/ 35337, // Rule ID 1104 //
14535 : GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
14536 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
14537 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
14538 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
14539 : // (fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
14540 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D32_MM,
14541 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14542 : // GIR_Coverage, 1104,
14543 : GIR_Done,
14544 : // Label 977: @35337
14545 : GIM_Try, /*On fail goto*//*Label 978*/ 35360, // Rule ID 1105 //
14546 : GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
14547 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
14548 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
14549 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
14550 : // (fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
14551 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D64_MM,
14552 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14553 : // GIR_Coverage, 1105,
14554 : GIR_Done,
14555 : // Label 978: @35360
14556 : GIM_Reject,
14557 : // Label 974: @35361
14558 : GIM_Reject,
14559 : // Label 967: @35362
14560 : GIM_Try, /*On fail goto*//*Label 979*/ 35393, // Rule ID 665 //
14561 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
14562 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
14563 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
14564 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
14565 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
14566 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
14567 : // (fdiv:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FDIV_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
14568 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D,
14569 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14570 : // GIR_Coverage, 665,
14571 : GIR_Done,
14572 : // Label 979: @35393
14573 : GIM_Reject,
14574 : // Label 968: @35394
14575 : GIM_Try, /*On fail goto*//*Label 980*/ 35425, // Rule ID 664 //
14576 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
14577 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
14578 : GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14579 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
14580 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
14581 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
14582 : // (fdiv:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FDIV_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
14583 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_W,
14584 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14585 : // GIR_Coverage, 664,
14586 : GIR_Done,
14587 : // Label 980: @35425
14588 : GIM_Reject,
14589 : // Label 969: @35426
14590 : GIM_Reject,
14591 : // Label 29: @35427
14592 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 983*/ 35484,
14593 : /*GILLT_v2s64*//*Label 981*/ 35436, 0,
14594 : /*GILLT_v4s32*//*Label 982*/ 35460,
14595 : // Label 981: @35436
14596 : GIM_Try, /*On fail goto*//*Label 984*/ 35459, // Rule ID 671 //
14597 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
14598 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
14599 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
14600 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
14601 : // (fexp2:{ *:[v2f64] } MSA128D:{ *:[v2f64] }:$ws) => (FEXP2_D_1_PSEUDO:{ *:[v2f64] } MSA128D:{ *:[v2f64] }:$ws)
14602 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FEXP2_D_1_PSEUDO,
14603 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14604 : // GIR_Coverage, 671,
14605 : GIR_Done,
14606 : // Label 984: @35459
14607 : GIM_Reject,
14608 : // Label 982: @35460
14609 : GIM_Try, /*On fail goto*//*Label 985*/ 35483, // Rule ID 670 //
14610 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
14611 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
14612 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
14613 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
14614 : // (fexp2:{ *:[v4f32] } MSA128W:{ *:[v4f32] }:$ws) => (FEXP2_W_1_PSEUDO:{ *:[v4f32] } MSA128W:{ *:[v4f32] }:$ws)
14615 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FEXP2_W_1_PSEUDO,
14616 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14617 : // GIR_Coverage, 670,
14618 : GIR_Done,
14619 : // Label 985: @35483
14620 : GIM_Reject,
14621 : // Label 983: @35484
14622 : GIM_Reject,
14623 : // Label 30: @35485
14624 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 988*/ 35542,
14625 : /*GILLT_v2s64*//*Label 986*/ 35494, 0,
14626 : /*GILLT_v4s32*//*Label 987*/ 35518,
14627 : // Label 986: @35494
14628 : GIM_Try, /*On fail goto*//*Label 989*/ 35517, // Rule ID 691 //
14629 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
14630 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
14631 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
14632 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
14633 : // (flog2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FLOG2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
14634 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FLOG2_D,
14635 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14636 : // GIR_Coverage, 691,
14637 : GIR_Done,
14638 : // Label 989: @35517
14639 : GIM_Reject,
14640 : // Label 987: @35518
14641 : GIM_Try, /*On fail goto*//*Label 990*/ 35541, // Rule ID 690 //
14642 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
14643 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
14644 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
14645 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
14646 : // (flog2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FLOG2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
14647 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FLOG2_W,
14648 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14649 : // GIR_Coverage, 690,
14650 : GIR_Done,
14651 : // Label 990: @35541
14652 : GIM_Reject,
14653 : // Label 988: @35542
14654 : GIM_Reject,
14655 : // Label 31: @35543
14656 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 993*/ 36838,
14657 : /*GILLT_s32*//*Label 991*/ 35551,
14658 : /*GILLT_s64*//*Label 992*/ 36052,
14659 : // Label 991: @35551
14660 : GIM_Try, /*On fail goto*//*Label 994*/ 36051,
14661 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
14662 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
14663 : GIM_Try, /*On fail goto*//*Label 995*/ 35635, // Rule ID 1423 //
14664 : GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
14665 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14666 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
14667 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14668 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14669 : GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14670 : GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
14671 : GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
14672 : GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
14673 : GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
14674 : GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
14675 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
14676 : GIM_CheckIsSafeToFold, /*InsnID*/1,
14677 : GIM_CheckIsSafeToFold, /*InsnID*/2,
14678 : // (fneg:{ *:[f32] } (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) => (NMADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
14679 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S,
14680 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
14681 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
14682 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
14683 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
14684 : GIR_EraseFromParent, /*InsnID*/0,
14685 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14686 : // GIR_Coverage, 1423,
14687 : GIR_Done,
14688 : // Label 995: @35635
14689 : GIM_Try, /*On fail goto*//*Label 996*/ 35709, // Rule ID 2162 //
14690 : GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotMips32r6_NotMips32r6,
14691 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14692 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
14693 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14694 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14695 : GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14696 : GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
14697 : GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
14698 : GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
14699 : GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
14700 : GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
14701 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
14702 : GIM_CheckIsSafeToFold, /*InsnID*/1,
14703 : GIM_CheckIsSafeToFold, /*InsnID*/2,
14704 : // (fneg:{ *:[f32] } (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) => (NMADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
14705 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S_MM,
14706 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
14707 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
14708 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
14709 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
14710 : GIR_EraseFromParent, /*InsnID*/0,
14711 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14712 : // GIR_Coverage, 2162,
14713 : GIR_Done,
14714 : // Label 996: @35709
14715 : GIM_Try, /*On fail goto*//*Label 997*/ 35783, // Rule ID 2342 //
14716 : GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
14717 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14718 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
14719 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14720 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14721 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
14722 : GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14723 : GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
14724 : GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
14725 : GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
14726 : GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
14727 : GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
14728 : GIM_CheckIsSafeToFold, /*InsnID*/1,
14729 : GIM_CheckIsSafeToFold, /*InsnID*/2,
14730 : // (fneg:{ *:[f32] } (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft))) => (NMADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
14731 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S,
14732 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
14733 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
14734 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
14735 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
14736 : GIR_EraseFromParent, /*InsnID*/0,
14737 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14738 : // GIR_Coverage, 2342,
14739 : GIR_Done,
14740 : // Label 997: @35783
14741 : GIM_Try, /*On fail goto*//*Label 998*/ 35857, // Rule ID 2439 //
14742 : GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotMips32r6_NotMips32r6,
14743 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14744 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
14745 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14746 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14747 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
14748 : GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14749 : GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
14750 : GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
14751 : GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
14752 : GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
14753 : GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
14754 : GIM_CheckIsSafeToFold, /*InsnID*/1,
14755 : GIM_CheckIsSafeToFold, /*InsnID*/2,
14756 : // (fneg:{ *:[f32] } (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft))) => (NMADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
14757 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S_MM,
14758 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
14759 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
14760 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
14761 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
14762 : GIR_EraseFromParent, /*InsnID*/0,
14763 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14764 : // GIR_Coverage, 2439,
14765 : GIR_Done,
14766 : // Label 998: @35857
14767 : GIM_Try, /*On fail goto*//*Label 999*/ 35931, // Rule ID 1424 //
14768 : GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
14769 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14770 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
14771 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14772 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14773 : GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14774 : GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
14775 : GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
14776 : GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
14777 : GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
14778 : GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
14779 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
14780 : GIM_CheckIsSafeToFold, /*InsnID*/1,
14781 : GIM_CheckIsSafeToFold, /*InsnID*/2,
14782 : // (fneg:{ *:[f32] } (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) => (NMSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
14783 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_S,
14784 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
14785 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
14786 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
14787 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
14788 : GIR_EraseFromParent, /*InsnID*/0,
14789 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14790 : // GIR_Coverage, 1424,
14791 : GIR_Done,
14792 : // Label 999: @35931
14793 : GIM_Try, /*On fail goto*//*Label 1000*/ 36005, // Rule ID 2163 //
14794 : GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotMips32r6_NotMips32r6,
14795 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14796 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
14797 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14798 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14799 : GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14800 : GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
14801 : GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
14802 : GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
14803 : GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
14804 : GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
14805 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
14806 : GIM_CheckIsSafeToFold, /*InsnID*/1,
14807 : GIM_CheckIsSafeToFold, /*InsnID*/2,
14808 : // (fneg:{ *:[f32] } (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) => (NMSUB_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
14809 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_S_MM,
14810 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
14811 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
14812 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
14813 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
14814 : GIR_EraseFromParent, /*InsnID*/0,
14815 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14816 : // GIR_Coverage, 2163,
14817 : GIR_Done,
14818 : // Label 1000: @36005
14819 : GIM_Try, /*On fail goto*//*Label 1001*/ 36020, // Rule ID 111 //
14820 : GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat,
14821 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
14822 : // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
14823 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_S,
14824 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14825 : // GIR_Coverage, 111,
14826 : GIR_Done,
14827 : // Label 1001: @36020
14828 : GIM_Try, /*On fail goto*//*Label 1002*/ 36035, // Rule ID 1121 //
14829 : GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
14830 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
14831 : // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
14832 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_S_MM,
14833 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14834 : // GIR_Coverage, 1121,
14835 : GIR_Done,
14836 : // Label 1002: @36035
14837 : GIM_Try, /*On fail goto*//*Label 1003*/ 36050, // Rule ID 1158 //
14838 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
14839 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
14840 : // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
14841 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_S_MMR6,
14842 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14843 : // GIR_Coverage, 1158,
14844 : GIR_Done,
14845 : // Label 1003: @36050
14846 : GIM_Reject,
14847 : // Label 994: @36051
14848 : GIM_Reject,
14849 : // Label 992: @36052
14850 : GIM_Try, /*On fail goto*//*Label 1004*/ 36837,
14851 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
14852 : GIM_Try, /*On fail goto*//*Label 1005*/ 36136, // Rule ID 1425 //
14853 : GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
14854 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
14855 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14856 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
14857 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
14858 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
14859 : GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14860 : GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
14861 : GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
14862 : GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
14863 : GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
14864 : GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
14865 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
14866 : GIM_CheckIsSafeToFold, /*InsnID*/1,
14867 : GIM_CheckIsSafeToFold, /*InsnID*/2,
14868 : // (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) => (NMADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
14869 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32,
14870 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
14871 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
14872 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
14873 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
14874 : GIR_EraseFromParent, /*InsnID*/0,
14875 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14876 : // GIR_Coverage, 1425,
14877 : GIR_Done,
14878 : // Label 1005: @36136
14879 : GIM_Try, /*On fail goto*//*Label 1006*/ 36214, // Rule ID 1427 //
14880 : GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
14881 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
14882 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14883 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
14884 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
14885 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
14886 : GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14887 : GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
14888 : GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
14889 : GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
14890 : GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
14891 : GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
14892 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
14893 : GIM_CheckIsSafeToFold, /*InsnID*/1,
14894 : GIM_CheckIsSafeToFold, /*InsnID*/2,
14895 : // (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr)) => (NMADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
14896 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D64,
14897 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
14898 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
14899 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
14900 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
14901 : GIR_EraseFromParent, /*InsnID*/0,
14902 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14903 : // GIR_Coverage, 1427,
14904 : GIR_Done,
14905 : // Label 1006: @36214
14906 : GIM_Try, /*On fail goto*//*Label 1007*/ 36292, // Rule ID 2164 //
14907 : GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6_NotMips32r6,
14908 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
14909 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14910 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
14911 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
14912 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
14913 : GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14914 : GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
14915 : GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
14916 : GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
14917 : GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
14918 : GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
14919 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
14920 : GIM_CheckIsSafeToFold, /*InsnID*/1,
14921 : GIM_CheckIsSafeToFold, /*InsnID*/2,
14922 : // (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) => (NMADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
14923 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32_MM,
14924 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
14925 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
14926 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
14927 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
14928 : GIR_EraseFromParent, /*InsnID*/0,
14929 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14930 : // GIR_Coverage, 2164,
14931 : GIR_Done,
14932 : // Label 1007: @36292
14933 : GIM_Try, /*On fail goto*//*Label 1008*/ 36370, // Rule ID 2343 //
14934 : GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
14935 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
14936 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14937 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
14938 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
14939 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
14940 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
14941 : GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14942 : GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
14943 : GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
14944 : GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
14945 : GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
14946 : GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
14947 : GIM_CheckIsSafeToFold, /*InsnID*/1,
14948 : GIM_CheckIsSafeToFold, /*InsnID*/2,
14949 : // (fneg:{ *:[f64] } (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft))) => (NMADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
14950 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32,
14951 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
14952 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
14953 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
14954 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
14955 : GIR_EraseFromParent, /*InsnID*/0,
14956 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14957 : // GIR_Coverage, 2343,
14958 : GIR_Done,
14959 : // Label 1008: @36370
14960 : GIM_Try, /*On fail goto*//*Label 1009*/ 36448, // Rule ID 2344 //
14961 : GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
14962 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
14963 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14964 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
14965 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
14966 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
14967 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
14968 : GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14969 : GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
14970 : GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
14971 : GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
14972 : GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
14973 : GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
14974 : GIM_CheckIsSafeToFold, /*InsnID*/1,
14975 : GIM_CheckIsSafeToFold, /*InsnID*/2,
14976 : // (fneg:{ *:[f64] } (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft))) => (NMADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
14977 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D64,
14978 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
14979 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
14980 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
14981 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
14982 : GIR_EraseFromParent, /*InsnID*/0,
14983 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14984 : // GIR_Coverage, 2344,
14985 : GIR_Done,
14986 : // Label 1009: @36448
14987 : GIM_Try, /*On fail goto*//*Label 1010*/ 36526, // Rule ID 2440 //
14988 : GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6_NotMips32r6,
14989 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
14990 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14991 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
14992 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
14993 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
14994 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
14995 : GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14996 : GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
14997 : GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
14998 : GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
14999 : GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
15000 : GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
15001 : GIM_CheckIsSafeToFold, /*InsnID*/1,
15002 : GIM_CheckIsSafeToFold, /*InsnID*/2,
15003 : // (fneg:{ *:[f64] } (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft))) => (NMADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
15004 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32_MM,
15005 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
15006 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
15007 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
15008 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
15009 : GIR_EraseFromParent, /*InsnID*/0,
15010 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15011 : // GIR_Coverage, 2440,
15012 : GIR_Done,
15013 : // Label 1010: @36526
15014 : GIM_Try, /*On fail goto*//*Label 1011*/ 36604, // Rule ID 1426 //
15015 : GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
15016 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
15017 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15018 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
15019 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
15020 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
15021 : GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
15022 : GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
15023 : GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
15024 : GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
15025 : GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
15026 : GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
15027 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
15028 : GIM_CheckIsSafeToFold, /*InsnID*/1,
15029 : GIM_CheckIsSafeToFold, /*InsnID*/2,
15030 : // (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) => (NMSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
15031 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_D32,
15032 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
15033 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
15034 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
15035 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
15036 : GIR_EraseFromParent, /*InsnID*/0,
15037 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15038 : // GIR_Coverage, 1426,
15039 : GIR_Done,
15040 : // Label 1011: @36604
15041 : GIM_Try, /*On fail goto*//*Label 1012*/ 36682, // Rule ID 1428 //
15042 : GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
15043 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
15044 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15045 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
15046 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
15047 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
15048 : GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
15049 : GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
15050 : GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
15051 : GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
15052 : GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
15053 : GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
15054 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
15055 : GIM_CheckIsSafeToFold, /*InsnID*/1,
15056 : GIM_CheckIsSafeToFold, /*InsnID*/2,
15057 : // (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr)) => (NMSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
15058 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_D64,
15059 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
15060 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
15061 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
15062 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
15063 : GIR_EraseFromParent, /*InsnID*/0,
15064 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15065 : // GIR_Coverage, 1428,
15066 : GIR_Done,
15067 : // Label 1012: @36682
15068 : GIM_Try, /*On fail goto*//*Label 1013*/ 36760, // Rule ID 2165 //
15069 : GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6_NotMips32r6,
15070 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
15071 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15072 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
15073 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
15074 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
15075 : GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
15076 : GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
15077 : GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
15078 : GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
15079 : GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
15080 : GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
15081 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
15082 : GIM_CheckIsSafeToFold, /*InsnID*/1,
15083 : GIM_CheckIsSafeToFold, /*InsnID*/2,
15084 : // (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) => (NMSUB_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
15085 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_D32_MM,
15086 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
15087 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
15088 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
15089 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
15090 : GIR_EraseFromParent, /*InsnID*/0,
15091 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15092 : // GIR_Coverage, 2165,
15093 : GIR_Done,
15094 : // Label 1013: @36760
15095 : GIM_Try, /*On fail goto*//*Label 1014*/ 36779, // Rule ID 112 //
15096 : GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
15097 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
15098 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
15099 : // (fneg:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
15100 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_D32,
15101 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15102 : // GIR_Coverage, 112,
15103 : GIR_Done,
15104 : // Label 1014: @36779
15105 : GIM_Try, /*On fail goto*//*Label 1015*/ 36798, // Rule ID 113 //
15106 : GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
15107 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
15108 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
15109 : // (fneg:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
15110 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_D64,
15111 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15112 : // GIR_Coverage, 113,
15113 : GIR_Done,
15114 : // Label 1015: @36798
15115 : GIM_Try, /*On fail goto*//*Label 1016*/ 36817, // Rule ID 1122 //
15116 : GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
15117 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
15118 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
15119 : // (fneg:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
15120 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_D32_MM,
15121 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15122 : // GIR_Coverage, 1122,
15123 : GIR_Done,
15124 : // Label 1016: @36817
15125 : GIM_Try, /*On fail goto*//*Label 1017*/ 36836, // Rule ID 1123 //
15126 : GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
15127 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
15128 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
15129 : // (fneg:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
15130 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_D64_MM,
15131 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15132 : // GIR_Coverage, 1123,
15133 : GIR_Done,
15134 : // Label 1017: @36836
15135 : GIM_Reject,
15136 : // Label 1004: @36837
15137 : GIM_Reject,
15138 : // Label 993: @36838
15139 : GIM_Reject,
15140 : // Label 32: @36839
15141 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1020*/ 36987,
15142 : /*GILLT_s32*//*Label 1018*/ 36847,
15143 : /*GILLT_s64*//*Label 1019*/ 36871,
15144 : // Label 1018: @36847
15145 : GIM_Try, /*On fail goto*//*Label 1021*/ 36870, // Rule ID 1024 //
15146 : GIM_CheckFeatures, GIFBS_HasMSA,
15147 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
15148 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
15149 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128F16RegClassID,
15150 : // (fpextend:{ *:[f32] } MSA128F16:{ *:[f16] }:$ws) => (MSA_FP_EXTEND_W_PSEUDO:{ *:[f32] } MSA128F16:{ *:[f16] }:$ws)
15151 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MSA_FP_EXTEND_W_PSEUDO,
15152 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15153 : // GIR_Coverage, 1024,
15154 : GIR_Done,
15155 : // Label 1021: @36870
15156 : GIM_Reject,
15157 : // Label 1019: @36871
15158 : GIM_Try, /*On fail goto*//*Label 1022*/ 36894, // Rule ID 1026 //
15159 : GIM_CheckFeatures, GIFBS_HasMSA,
15160 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
15161 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
15162 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128F16RegClassID,
15163 : // (fpextend:{ *:[f64] } MSA128F16:{ *:[f16] }:$ws) => (MSA_FP_EXTEND_D_PSEUDO:{ *:[f64] } MSA128F16:{ *:[f16] }:$ws)
15164 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MSA_FP_EXTEND_D_PSEUDO,
15165 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15166 : // GIR_Coverage, 1026,
15167 : GIR_Done,
15168 : // Label 1022: @36894
15169 : GIM_Try, /*On fail goto*//*Label 1023*/ 36917, // Rule ID 1412 //
15170 : GIM_CheckFeatures, GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips,
15171 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
15172 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
15173 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
15174 : // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D32_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
15175 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_D32_S,
15176 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15177 : // GIR_Coverage, 1412,
15178 : GIR_Done,
15179 : // Label 1023: @36917
15180 : GIM_Try, /*On fail goto*//*Label 1024*/ 36940, // Rule ID 1422 //
15181 : GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips,
15182 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
15183 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
15184 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
15185 : // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D64_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
15186 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_D64_S,
15187 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15188 : // GIR_Coverage, 1422,
15189 : GIR_Done,
15190 : // Label 1024: @36940
15191 : GIM_Try, /*On fail goto*//*Label 1025*/ 36963, // Rule ID 2174 //
15192 : GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit,
15193 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
15194 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
15195 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
15196 : // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D64_S_MM:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
15197 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_D64_S_MM,
15198 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15199 : // GIR_Coverage, 2174,
15200 : GIR_Done,
15201 : // Label 1025: @36963
15202 : GIM_Try, /*On fail goto*//*Label 1026*/ 36986, // Rule ID 2176 //
15203 : GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit,
15204 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
15205 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
15206 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
15207 : // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D32_S_MM:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
15208 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_D32_S_MM,
15209 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15210 : // GIR_Coverage, 2176,
15211 : GIR_Done,
15212 : // Label 1026: @36986
15213 : GIM_Reject,
15214 : // Label 1020: @36987
15215 : GIM_Reject,
15216 : // Label 33: @36988
15217 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 1029*/ 37115,
15218 : /*GILLT_s16*//*Label 1027*/ 36996,
15219 : /*GILLT_s32*//*Label 1028*/ 37043,
15220 : // Label 1027: @36996
15221 : GIM_Try, /*On fail goto*//*Label 1030*/ 37019, // Rule ID 1025 //
15222 : GIM_CheckFeatures, GIFBS_HasMSA,
15223 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
15224 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128F16RegClassID,
15225 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
15226 : // (fpround:{ *:[f16] } FGR32Opnd:{ *:[f32] }:$fs) => (MSA_FP_ROUND_W_PSEUDO:{ *:[f16] } FGR32Opnd:{ *:[f32] }:$fs)
15227 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MSA_FP_ROUND_W_PSEUDO,
15228 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15229 : // GIR_Coverage, 1025,
15230 : GIR_Done,
15231 : // Label 1030: @37019
15232 : GIM_Try, /*On fail goto*//*Label 1031*/ 37042, // Rule ID 1027 //
15233 : GIM_CheckFeatures, GIFBS_HasMSA,
15234 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
15235 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128F16RegClassID,
15236 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
15237 : // (fpround:{ *:[f16] } FGR64Opnd:{ *:[f64] }:$fs) => (MSA_FP_ROUND_D_PSEUDO:{ *:[f16] } FGR64Opnd:{ *:[f64] }:$fs)
15238 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MSA_FP_ROUND_D_PSEUDO,
15239 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15240 : // GIR_Coverage, 1027,
15241 : GIR_Done,
15242 : // Label 1031: @37042
15243 : GIM_Reject,
15244 : // Label 1028: @37043
15245 : GIM_Try, /*On fail goto*//*Label 1032*/ 37114,
15246 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
15247 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
15248 : GIM_Try, /*On fail goto*//*Label 1033*/ 37068, // Rule ID 1411 //
15249 : GIM_CheckFeatures, GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips,
15250 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
15251 : // (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D32:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)
15252 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_S_D32,
15253 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15254 : // GIR_Coverage, 1411,
15255 : GIR_Done,
15256 : // Label 1033: @37068
15257 : GIM_Try, /*On fail goto*//*Label 1034*/ 37083, // Rule ID 1421 //
15258 : GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips,
15259 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
15260 : // (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D64:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)
15261 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_S_D64,
15262 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15263 : // GIR_Coverage, 1421,
15264 : GIR_Done,
15265 : // Label 1034: @37083
15266 : GIM_Try, /*On fail goto*//*Label 1035*/ 37098, // Rule ID 2173 //
15267 : GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit,
15268 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
15269 : // (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D64_MM:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)
15270 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_S_D64_MM,
15271 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15272 : // GIR_Coverage, 2173,
15273 : GIR_Done,
15274 : // Label 1035: @37098
15275 : GIM_Try, /*On fail goto*//*Label 1036*/ 37113, // Rule ID 2175 //
15276 : GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit,
15277 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
15278 : // (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D32_MM:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)
15279 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_S_D32_MM,
15280 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15281 : // GIR_Coverage, 2175,
15282 : GIR_Done,
15283 : // Label 1036: @37113
15284 : GIM_Reject,
15285 : // Label 1032: @37114
15286 : GIM_Reject,
15287 : // Label 1029: @37115
15288 : GIM_Reject,
15289 : // Label 34: @37116
15290 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1039*/ 37173,
15291 : /*GILLT_v2s64*//*Label 1037*/ 37125, 0,
15292 : /*GILLT_v4s32*//*Label 1038*/ 37149,
15293 : // Label 1037: @37125
15294 : GIM_Try, /*On fail goto*//*Label 1040*/ 37148, // Rule ID 745 //
15295 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
15296 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
15297 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
15298 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
15299 : // (fp_to_sint:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTRUNC_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
15300 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FTRUNC_S_D,
15301 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15302 : // GIR_Coverage, 745,
15303 : GIR_Done,
15304 : // Label 1040: @37148
15305 : GIM_Reject,
15306 : // Label 1038: @37149
15307 : GIM_Try, /*On fail goto*//*Label 1041*/ 37172, // Rule ID 744 //
15308 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
15309 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
15310 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
15311 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
15312 : // (fp_to_sint:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTRUNC_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
15313 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FTRUNC_S_W,
15314 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15315 : // GIR_Coverage, 744,
15316 : GIR_Done,
15317 : // Label 1041: @37172
15318 : GIM_Reject,
15319 : // Label 1039: @37173
15320 : GIM_Reject,
15321 : // Label 35: @37174
15322 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1044*/ 37231,
15323 : /*GILLT_v2s64*//*Label 1042*/ 37183, 0,
15324 : /*GILLT_v4s32*//*Label 1043*/ 37207,
15325 : // Label 1042: @37183
15326 : GIM_Try, /*On fail goto*//*Label 1045*/ 37206, // Rule ID 747 //
15327 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
15328 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
15329 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
15330 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
15331 : // (fp_to_uint:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTRUNC_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
15332 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FTRUNC_U_D,
15333 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15334 : // GIR_Coverage, 747,
15335 : GIR_Done,
15336 : // Label 1045: @37206
15337 : GIM_Reject,
15338 : // Label 1043: @37207
15339 : GIM_Try, /*On fail goto*//*Label 1046*/ 37230, // Rule ID 746 //
15340 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
15341 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
15342 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
15343 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
15344 : // (fp_to_uint:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTRUNC_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
15345 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FTRUNC_U_W,
15346 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15347 : // GIR_Coverage, 746,
15348 : GIR_Done,
15349 : // Label 1046: @37230
15350 : GIM_Reject,
15351 : // Label 1044: @37231
15352 : GIM_Reject,
15353 : // Label 36: @37232
15354 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1051*/ 37384,
15355 : /*GILLT_s32*//*Label 1047*/ 37244,
15356 : /*GILLT_s64*//*Label 1048*/ 37266, 0,
15357 : /*GILLT_v2s64*//*Label 1049*/ 37336, 0,
15358 : /*GILLT_v4s32*//*Label 1050*/ 37360,
15359 : // Label 1047: @37244
15360 : GIM_Try, /*On fail goto*//*Label 1052*/ 37265, // Rule ID 1406 //
15361 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
15362 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
15363 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
15364 : // (sint_to_fp:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_S_W:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$src)
15365 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoCVT_S_W,
15366 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15367 : // GIR_Coverage, 1406,
15368 : GIR_Done,
15369 : // Label 1052: @37265
15370 : GIM_Reject,
15371 : // Label 1048: @37266
15372 : GIM_Try, /*On fail goto*//*Label 1053*/ 37289, // Rule ID 1409 //
15373 : GIM_CheckFeatures, GIFBS_NotFP64bit,
15374 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
15375 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
15376 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
15377 : // (sint_to_fp:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_D32_W:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)
15378 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoCVT_D32_W,
15379 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15380 : // GIR_Coverage, 1409,
15381 : GIR_Done,
15382 : // Label 1053: @37289
15383 : GIM_Try, /*On fail goto*//*Label 1054*/ 37312, // Rule ID 1415 //
15384 : GIM_CheckFeatures, GIFBS_IsFP64bit,
15385 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
15386 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
15387 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
15388 : // (sint_to_fp:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_D64_W:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)
15389 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoCVT_D64_W,
15390 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15391 : // GIR_Coverage, 1415,
15392 : GIR_Done,
15393 : // Label 1054: @37312
15394 : GIM_Try, /*On fail goto*//*Label 1055*/ 37335, // Rule ID 1417 //
15395 : GIM_CheckFeatures, GIFBS_IsFP64bit,
15396 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
15397 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
15398 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
15399 : // (sint_to_fp:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src) => (PseudoCVT_D64_L:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src)
15400 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoCVT_D64_L,
15401 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15402 : // GIR_Coverage, 1417,
15403 : GIR_Done,
15404 : // Label 1055: @37335
15405 : GIM_Reject,
15406 : // Label 1049: @37336
15407 : GIM_Try, /*On fail goto*//*Label 1056*/ 37359, // Rule ID 677 //
15408 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
15409 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
15410 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
15411 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
15412 : // (sint_to_fp:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (FFINT_S_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
15413 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FFINT_S_D,
15414 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15415 : // GIR_Coverage, 677,
15416 : GIR_Done,
15417 : // Label 1056: @37359
15418 : GIM_Reject,
15419 : // Label 1050: @37360
15420 : GIM_Try, /*On fail goto*//*Label 1057*/ 37383, // Rule ID 676 //
15421 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
15422 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
15423 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
15424 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
15425 : // (sint_to_fp:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFINT_S_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
15426 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FFINT_S_W,
15427 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15428 : // GIR_Coverage, 676,
15429 : GIR_Done,
15430 : // Label 1057: @37383
15431 : GIM_Reject,
15432 : // Label 1051: @37384
15433 : GIM_Reject,
15434 : // Label 37: @37385
15435 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1060*/ 37442,
15436 : /*GILLT_v2s64*//*Label 1058*/ 37394, 0,
15437 : /*GILLT_v4s32*//*Label 1059*/ 37418,
15438 : // Label 1058: @37394
15439 : GIM_Try, /*On fail goto*//*Label 1061*/ 37417, // Rule ID 679 //
15440 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
15441 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
15442 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
15443 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
15444 : // (uint_to_fp:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (FFINT_U_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
15445 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FFINT_U_D,
15446 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15447 : // GIR_Coverage, 679,
15448 : GIR_Done,
15449 : // Label 1061: @37417
15450 : GIM_Reject,
15451 : // Label 1059: @37418
15452 : GIM_Try, /*On fail goto*//*Label 1062*/ 37441, // Rule ID 678 //
15453 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
15454 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
15455 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
15456 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
15457 : // (uint_to_fp:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFINT_U_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
15458 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FFINT_U_W,
15459 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15460 : // GIR_Coverage, 678,
15461 : GIR_Done,
15462 : // Label 1062: @37441
15463 : GIM_Reject,
15464 : // Label 1060: @37442
15465 : GIM_Reject,
15466 : // Label 38: @37443
15467 : GIM_Try, /*On fail goto*//*Label 1063*/ 37527,
15468 : GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
15469 : GIM_Try, /*On fail goto*//*Label 1064*/ 37462, // Rule ID 73 //
15470 : GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC,
15471 : // (br (bb:{ *:[Other] }):$target) => (J (bb:{ *:[Other] }):$target)
15472 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::J,
15473 : GIR_AddImplicitDef, /*InsnID*/0, Mips::AT,
15474 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15475 : // GIR_Coverage, 73,
15476 : GIR_Done,
15477 : // Label 1064: @37462
15478 : GIM_Try, /*On fail goto*//*Label 1065*/ 37476, // Rule ID 80 //
15479 : GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
15480 : // (br (bb:{ *:[Other] }):$offset) => (B (bb:{ *:[Other] }):$offset)
15481 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::B,
15482 : GIR_AddImplicitDef, /*InsnID*/0, Mips::AT,
15483 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15484 : // GIR_Coverage, 80,
15485 : GIR_Done,
15486 : // Label 1065: @37476
15487 : GIM_Try, /*On fail goto*//*Label 1066*/ 37490, // Rule ID 1072 //
15488 : GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6_RelocNotPIC,
15489 : // (br (bb:{ *:[Other] }):$target) => (J_MM (bb:{ *:[Other] }):$target)
15490 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::J_MM,
15491 : GIR_AddImplicitDef, /*InsnID*/0, Mips::AT,
15492 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15493 : // GIR_Coverage, 1072,
15494 : GIR_Done,
15495 : // Label 1066: @37490
15496 : GIM_Try, /*On fail goto*//*Label 1067*/ 37504, // Rule ID 1081 //
15497 : GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6_RelocPIC,
15498 : // (br (bb:{ *:[Other] }):$offset) => (B_MM (bb:{ *:[Other] }):$offset)
15499 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::B_MM,
15500 : GIR_AddImplicitDef, /*InsnID*/0, Mips::AT,
15501 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15502 : // GIR_Coverage, 1081,
15503 : GIR_Done,
15504 : // Label 1067: @37504
15505 : GIM_Try, /*On fail goto*//*Label 1068*/ 37515, // Rule ID 1137 //
15506 : GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
15507 : // (br (bb:{ *:[Other] }):$offset) => (BC_MMR6 (bb:{ *:[Other] }):$offset)
15508 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::BC_MMR6,
15509 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15510 : // GIR_Coverage, 1137,
15511 : GIR_Done,
15512 : // Label 1068: @37515
15513 : GIM_Try, /*On fail goto*//*Label 1069*/ 37526, // Rule ID 1785 //
15514 : GIM_CheckFeatures, GIFBS_InMips16Mode,
15515 : // (br (bb:{ *:[Other] }):$imm16) => (Bimm16 (bb:{ *:[Other] }):$imm16)
15516 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::Bimm16,
15517 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15518 : // GIR_Coverage, 1785,
15519 : GIR_Done,
15520 : // Label 1069: @37526
15521 : GIM_Reject,
15522 : // Label 1063: @37527
15523 : GIM_Reject,
15524 : // Label 39: @37528
15525 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 1076*/ 37962,
15526 : /*GILLT_s32*//*Label 1070*/ 37542,
15527 : /*GILLT_s64*//*Label 1071*/ 37734, 0,
15528 : /*GILLT_v2s64*//*Label 1072*/ 37866, 0,
15529 : /*GILLT_v4s32*//*Label 1073*/ 37890,
15530 : /*GILLT_v8s16*//*Label 1074*/ 37914,
15531 : /*GILLT_v16s8*//*Label 1075*/ 37938,
15532 : // Label 1070: @37542
15533 : GIM_Try, /*On fail goto*//*Label 1077*/ 37733,
15534 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
15535 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
15536 : GIM_Try, /*On fail goto*//*Label 1078*/ 37597, // Rule ID 91 //
15537 : GIM_CheckFeatures, GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
15538 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15539 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
15540 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15541 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15542 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
15543 : GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
15544 : GIM_CheckIsSafeToFold, /*InsnID*/1,
15545 : // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })) => (CLO:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
15546 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CLO,
15547 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15548 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
15549 : GIR_EraseFromParent, /*InsnID*/0,
15550 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15551 : // GIR_Coverage, 91,
15552 : GIR_Done,
15553 : // Label 1078: @37597
15554 : GIM_Try, /*On fail goto*//*Label 1079*/ 37642, // Rule ID 282 //
15555 : GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc,
15556 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15557 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
15558 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15559 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15560 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
15561 : GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
15562 : GIM_CheckIsSafeToFold, /*InsnID*/1,
15563 : // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })) => (CLO_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
15564 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CLO_R6,
15565 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15566 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
15567 : GIR_EraseFromParent, /*InsnID*/0,
15568 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15569 : // GIR_Coverage, 282,
15570 : GIR_Done,
15571 : // Label 1079: @37642
15572 : GIM_Try, /*On fail goto*//*Label 1080*/ 37687, // Rule ID 1068 //
15573 : GIM_CheckFeatures, GIFBS_InMicroMips,
15574 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15575 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
15576 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15577 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15578 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
15579 : GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
15580 : GIM_CheckIsSafeToFold, /*InsnID*/1,
15581 : // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })) => (CLO_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
15582 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CLO_MM,
15583 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15584 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
15585 : GIR_EraseFromParent, /*InsnID*/0,
15586 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15587 : // GIR_Coverage, 1068,
15588 : GIR_Done,
15589 : // Label 1080: @37687
15590 : GIM_Try, /*On fail goto*//*Label 1081*/ 37702, // Rule ID 90 //
15591 : GIM_CheckFeatures, GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
15592 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
15593 : // (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (CLZ:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
15594 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CLZ,
15595 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15596 : // GIR_Coverage, 90,
15597 : GIR_Done,
15598 : // Label 1081: @37702
15599 : GIM_Try, /*On fail goto*//*Label 1082*/ 37717, // Rule ID 283 //
15600 : GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc,
15601 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
15602 : // (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (CLZ_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
15603 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CLZ_R6,
15604 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15605 : // GIR_Coverage, 283,
15606 : GIR_Done,
15607 : // Label 1082: @37717
15608 : GIM_Try, /*On fail goto*//*Label 1083*/ 37732, // Rule ID 1067 //
15609 : GIM_CheckFeatures, GIFBS_InMicroMips,
15610 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
15611 : // (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (CLZ_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
15612 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CLZ_MM,
15613 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15614 : // GIR_Coverage, 1067,
15615 : GIR_Done,
15616 : // Label 1083: @37732
15617 : GIM_Reject,
15618 : // Label 1077: @37733
15619 : GIM_Reject,
15620 : // Label 1071: @37734
15621 : GIM_Try, /*On fail goto*//*Label 1084*/ 37865,
15622 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
15623 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
15624 : GIM_Try, /*On fail goto*//*Label 1085*/ 37789, // Rule ID 236 //
15625 : GIM_CheckFeatures, GIFBS_HasMips64_HasStdEnc_NotInMicroMips_NotMips64r6,
15626 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15627 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
15628 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
15629 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
15630 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
15631 : GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
15632 : GIM_CheckIsSafeToFold, /*InsnID*/1,
15633 : // (ctlz:{ *:[i64] } (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, -1:{ *:[i64] })) => (DCLO:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
15634 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DCLO,
15635 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15636 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
15637 : GIR_EraseFromParent, /*InsnID*/0,
15638 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15639 : // GIR_Coverage, 236,
15640 : GIR_Done,
15641 : // Label 1085: @37789
15642 : GIM_Try, /*On fail goto*//*Label 1086*/ 37834, // Rule ID 311 //
15643 : GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
15644 : GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15645 : GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
15646 : GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
15647 : GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
15648 : GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
15649 : GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
15650 : GIM_CheckIsSafeToFold, /*InsnID*/1,
15651 : // (ctlz:{ *:[i64] } (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, -1:{ *:[i64] })) => (DCLO_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
15652 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DCLO_R6,
15653 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15654 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
15655 : GIR_EraseFromParent, /*InsnID*/0,
15656 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15657 : // GIR_Coverage, 311,
15658 : GIR_Done,
15659 : // Label 1086: @37834
15660 : GIM_Try, /*On fail goto*//*Label 1087*/ 37849, // Rule ID 235 //
15661 : GIM_CheckFeatures, GIFBS_HasMips64_HasStdEnc_NotInMicroMips_NotMips64r6,
15662 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
15663 : // (ctlz:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) => (DCLZ:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
15664 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DCLZ,
15665 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15666 : // GIR_Coverage, 235,
15667 : GIR_Done,
15668 : // Label 1087: @37849
15669 : GIM_Try, /*On fail goto*//*Label 1088*/ 37864, // Rule ID 312 //
15670 : GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
15671 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
15672 : // (ctlz:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) => (DCLZ_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
15673 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DCLZ_R6,
15674 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15675 : // GIR_Coverage, 312,
15676 : GIR_Done,
15677 : // Label 1088: @37864
15678 : GIM_Reject,
15679 : // Label 1084: @37865
15680 : GIM_Reject,
15681 : // Label 1072: @37866
15682 : GIM_Try, /*On fail goto*//*Label 1089*/ 37889, // Rule ID 883 //
15683 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
15684 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
15685 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
15686 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
15687 : // (ctlz:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (NLZC_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
15688 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::NLZC_D,
15689 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15690 : // GIR_Coverage, 883,
15691 : GIR_Done,
15692 : // Label 1089: @37889
15693 : GIM_Reject,
15694 : // Label 1073: @37890
15695 : GIM_Try, /*On fail goto*//*Label 1090*/ 37913, // Rule ID 882 //
15696 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
15697 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
15698 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
15699 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
15700 : // (ctlz:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (NLZC_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
15701 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::NLZC_W,
15702 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15703 : // GIR_Coverage, 882,
15704 : GIR_Done,
15705 : // Label 1090: @37913
15706 : GIM_Reject,
15707 : // Label 1074: @37914
15708 : GIM_Try, /*On fail goto*//*Label 1091*/ 37937, // Rule ID 881 //
15709 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
15710 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
15711 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
15712 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
15713 : // (ctlz:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws) => (NLZC_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
15714 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::NLZC_H,
15715 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15716 : // GIR_Coverage, 881,
15717 : GIR_Done,
15718 : // Label 1091: @37937
15719 : GIM_Reject,
15720 : // Label 1075: @37938
15721 : GIM_Try, /*On fail goto*//*Label 1092*/ 37961, // Rule ID 880 //
15722 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
15723 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
15724 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
15725 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
15726 : // (ctlz:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws) => (NLZC_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
15727 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::NLZC_B,
15728 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15729 : // GIR_Coverage, 880,
15730 : GIR_Done,
15731 : // Label 1092: @37961
15732 : GIM_Reject,
15733 : // Label 1076: @37962
15734 : GIM_Reject,
15735 : // Label 40: @37963
15736 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 1099*/ 38121,
15737 : /*GILLT_s32*//*Label 1093*/ 37977,
15738 : /*GILLT_s64*//*Label 1094*/ 38001, 0,
15739 : /*GILLT_v2s64*//*Label 1095*/ 38025, 0,
15740 : /*GILLT_v4s32*//*Label 1096*/ 38049,
15741 : /*GILLT_v8s16*//*Label 1097*/ 38073,
15742 : /*GILLT_v16s8*//*Label 1098*/ 38097,
15743 : // Label 1093: @37977
15744 : GIM_Try, /*On fail goto*//*Label 1100*/ 38000, // Rule ID 250 //
15745 : GIM_CheckFeatures, GIFBS_HasCnMips,
15746 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
15747 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
15748 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
15749 : // (ctpop:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (POP:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
15750 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::POP,
15751 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15752 : // GIR_Coverage, 250,
15753 : GIR_Done,
15754 : // Label 1100: @38000
15755 : GIM_Reject,
15756 : // Label 1094: @38001
15757 : GIM_Try, /*On fail goto*//*Label 1101*/ 38024, // Rule ID 251 //
15758 : GIM_CheckFeatures, GIFBS_HasCnMips,
15759 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
15760 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
15761 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
15762 : // (ctpop:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) => (DPOP:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
15763 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DPOP,
15764 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15765 : // GIR_Coverage, 251,
15766 : GIR_Done,
15767 : // Label 1101: @38024
15768 : GIM_Reject,
15769 : // Label 1095: @38025
15770 : GIM_Try, /*On fail goto*//*Label 1102*/ 38048, // Rule ID 905 //
15771 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
15772 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
15773 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
15774 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
15775 : // (ctpop:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (PCNT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
15776 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PCNT_D,
15777 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15778 : // GIR_Coverage, 905,
15779 : GIR_Done,
15780 : // Label 1102: @38048
15781 : GIM_Reject,
15782 : // Label 1096: @38049
15783 : GIM_Try, /*On fail goto*//*Label 1103*/ 38072, // Rule ID 904 //
15784 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
15785 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
15786 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
15787 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
15788 : // (ctpop:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (PCNT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
15789 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PCNT_W,
15790 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15791 : // GIR_Coverage, 904,
15792 : GIR_Done,
15793 : // Label 1103: @38072
15794 : GIM_Reject,
15795 : // Label 1097: @38073
15796 : GIM_Try, /*On fail goto*//*Label 1104*/ 38096, // Rule ID 903 //
15797 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
15798 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
15799 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
15800 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
15801 : // (ctpop:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws) => (PCNT_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
15802 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PCNT_H,
15803 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15804 : // GIR_Coverage, 903,
15805 : GIR_Done,
15806 : // Label 1104: @38096
15807 : GIM_Reject,
15808 : // Label 1098: @38097
15809 : GIM_Try, /*On fail goto*//*Label 1105*/ 38120, // Rule ID 902 //
15810 : GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
15811 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
15812 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
15813 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
15814 : // (ctpop:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws) => (PCNT_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
15815 : GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PCNT_B,
15816 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15817 : // GIR_Coverage, 902,
15818 : GIR_Done,
15819 : // Label 1105: @38120
15820 : GIM_Reject,
15821 : // Label 1099: @38121
15822 : GIM_Reject,
15823 : // Label 41: @38122
15824 : GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1108*/ 38273,
15825 : /*GILLT_s32*//*Label 1106*/ 38130,
15826 : /*GILLT_s64*//*Label 1107*/ 38224,
15827 : // Label 1106: @38130
15828 : GIM_Try, /*On fail goto*//*Label 1109*/ 38223,
15829 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
15830 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
15831 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
15832 : GIM_Try, /*On fail goto*//*Label 1110*/ 38183, // Rule ID 1392 //
15833 : GIM_CheckFeatures, GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips,
15834 : // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt) => (ROTR:{ *:[i32] } (WSBH:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] })
15835 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15836 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::WSBH,
15837 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
15838 : GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
15839 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15840 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ROTR,
15841 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15842 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
15843 : GIR_AddImm, /*InsnID*/0, /*Imm*/16,
15844 : GIR_EraseFromParent, /*InsnID*/0,
15845 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15846 : // GIR_Coverage, 1392,
15847 : GIR_Done,
15848 : // Label 1110: @38183
15849 : GIM_Try, /*On fail goto*//*Label 1111*/ 38222, // Rule ID 2106 //
15850 : GIM_CheckFeatures, GIFBS_InMicroMips,
15851 : // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt) => (ROTR_MM:{ *:[i32] } (WSBH_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] })
15852 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15853 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::WSBH_MM,
15854 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
15855 : GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
15856 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15857 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ROTR_MM,
15858 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15859 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
15860 : GIR_AddImm, /*InsnID*/0, /*Imm*/16,
15861 : GIR_EraseFromParent, /*InsnID*/0,
15862 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15863 : // GIR_Coverage, 2106,
15864 : GIR_Done,
15865 : // Label 1111: @38222
15866 : GIM_Reject,
15867 : // Label 1109: @38223
15868 : GIM_Reject,
15869 : // Label 1107: @38224
15870 : GIM_Try, /*On fail goto*//*Label 1112*/ 38272, // Rule ID 1534 //
15871 : GIM_CheckFeatures, GIFBS_HasMips64r2_HasStdEnc,
15872 : GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
15873 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
15874 : GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
15875 : // (bswap:{ *:[i64] } GPR64:{ *:[i64] }:$rt) => (DSHD:{ *:[i64] } (DSBH:{ *:[i64] } GPR64:{ *:[i64] }:$rt))
15876 : GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15877 : GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::DSBH,
15878 : GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
15879 : GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
15880 : GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15881 : GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSHD,
15882 : GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
15883 : GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
15884 : GIR_EraseFromParent, /*InsnID*/0,
15885 : GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15886 : // GIR_Coverage, 1534,
15887 : GIR_Done,
15888 : // Label 1112: @38272
15889 : GIM_Reject,
15890 : // Label 1108: @38273
15891 : GIM_Reject,
15892 : // Label 42: @38274
15893 : GIM_Reject,
15894 : };
15895 0 : return MatchTable0;
15896 : }
15897 : #endif // ifdef GET_GLOBALISEL_IMPL
15898 : #ifdef GET_GLOBALISEL_PREDICATES_DECL
15899 : PredicateBitset AvailableModuleFeatures;
15900 : mutable PredicateBitset AvailableFunctionFeatures;
15901 : PredicateBitset getAvailableFeatures() const {
15902 : return AvailableModuleFeatures | AvailableFunctionFeatures;
15903 : }
15904 : PredicateBitset
15905 : computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const;
15906 : PredicateBitset
15907 : computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget,
15908 : const MachineFunction *MF) const;
15909 : #endif // ifdef GET_GLOBALISEL_PREDICATES_DECL
15910 : #ifdef GET_GLOBALISEL_PREDICATES_INIT
15911 10307 : AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
15912 : AvailableFunctionFeatures()
15913 : #endif // ifdef GET_GLOBALISEL_PREDICATES_INIT
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