LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/Mips - MipsGenInstrInfo.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 44 48 91.7 %
Date: 2018-05-20 00:06:23 Functions: 5 7 71.4 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Target Instruction Enum Values and Descriptors                             *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : #ifdef GET_INSTRINFO_ENUM
      10             : #undef GET_INSTRINFO_ENUM
      11             : namespace llvm {
      12             : 
      13             : namespace Mips {
      14             :   enum {
      15             :     PHI = 0,
      16             :     INLINEASM   = 1,
      17             :     CFI_INSTRUCTION     = 2,
      18             :     EH_LABEL    = 3,
      19             :     GC_LABEL    = 4,
      20             :     ANNOTATION_LABEL    = 5,
      21             :     KILL        = 6,
      22             :     EXTRACT_SUBREG      = 7,
      23             :     INSERT_SUBREG       = 8,
      24             :     IMPLICIT_DEF        = 9,
      25             :     SUBREG_TO_REG       = 10,
      26             :     COPY_TO_REGCLASS    = 11,
      27             :     DBG_VALUE   = 12,
      28             :     DBG_LABEL   = 13,
      29             :     REG_SEQUENCE        = 14,
      30             :     COPY        = 15,
      31             :     BUNDLE      = 16,
      32             :     LIFETIME_START      = 17,
      33             :     LIFETIME_END        = 18,
      34             :     STACKMAP    = 19,
      35             :     FENTRY_CALL = 20,
      36             :     PATCHPOINT  = 21,
      37             :     LOAD_STACK_GUARD    = 22,
      38             :     STATEPOINT  = 23,
      39             :     LOCAL_ESCAPE        = 24,
      40             :     FAULTING_OP = 25,
      41             :     PATCHABLE_OP        = 26,
      42             :     PATCHABLE_FUNCTION_ENTER    = 27,
      43             :     PATCHABLE_RET       = 28,
      44             :     PATCHABLE_FUNCTION_EXIT     = 29,
      45             :     PATCHABLE_TAIL_CALL = 30,
      46             :     PATCHABLE_EVENT_CALL        = 31,
      47             :     PATCHABLE_TYPED_EVENT_CALL  = 32,
      48             :     ICALL_BRANCH_FUNNEL = 33,
      49             :     G_ADD       = 34,
      50             :     G_SUB       = 35,
      51             :     G_MUL       = 36,
      52             :     G_SDIV      = 37,
      53             :     G_UDIV      = 38,
      54             :     G_SREM      = 39,
      55             :     G_UREM      = 40,
      56             :     G_AND       = 41,
      57             :     G_OR        = 42,
      58             :     G_XOR       = 43,
      59             :     G_IMPLICIT_DEF      = 44,
      60             :     G_PHI       = 45,
      61             :     G_FRAME_INDEX       = 46,
      62             :     G_GLOBAL_VALUE      = 47,
      63             :     G_EXTRACT   = 48,
      64             :     G_UNMERGE_VALUES    = 49,
      65             :     G_INSERT    = 50,
      66             :     G_MERGE_VALUES      = 51,
      67             :     G_PTRTOINT  = 52,
      68             :     G_INTTOPTR  = 53,
      69             :     G_BITCAST   = 54,
      70             :     G_LOAD      = 55,
      71             :     G_SEXTLOAD  = 56,
      72             :     G_ZEXTLOAD  = 57,
      73             :     G_STORE     = 58,
      74             :     G_ATOMIC_CMPXCHG_WITH_SUCCESS       = 59,
      75             :     G_ATOMIC_CMPXCHG    = 60,
      76             :     G_ATOMICRMW_XCHG    = 61,
      77             :     G_ATOMICRMW_ADD     = 62,
      78             :     G_ATOMICRMW_SUB     = 63,
      79             :     G_ATOMICRMW_AND     = 64,
      80             :     G_ATOMICRMW_NAND    = 65,
      81             :     G_ATOMICRMW_OR      = 66,
      82             :     G_ATOMICRMW_XOR     = 67,
      83             :     G_ATOMICRMW_MAX     = 68,
      84             :     G_ATOMICRMW_MIN     = 69,
      85             :     G_ATOMICRMW_UMAX    = 70,
      86             :     G_ATOMICRMW_UMIN    = 71,
      87             :     G_BRCOND    = 72,
      88             :     G_BRINDIRECT        = 73,
      89             :     G_INTRINSIC = 74,
      90             :     G_INTRINSIC_W_SIDE_EFFECTS  = 75,
      91             :     G_ANYEXT    = 76,
      92             :     G_TRUNC     = 77,
      93             :     G_CONSTANT  = 78,
      94             :     G_FCONSTANT = 79,
      95             :     G_VASTART   = 80,
      96             :     G_VAARG     = 81,
      97             :     G_SEXT      = 82,
      98             :     G_ZEXT      = 83,
      99             :     G_SHL       = 84,
     100             :     G_LSHR      = 85,
     101             :     G_ASHR      = 86,
     102             :     G_ICMP      = 87,
     103             :     G_FCMP      = 88,
     104             :     G_SELECT    = 89,
     105             :     G_UADDE     = 90,
     106             :     G_USUBE     = 91,
     107             :     G_SADDO     = 92,
     108             :     G_SSUBO     = 93,
     109             :     G_UMULO     = 94,
     110             :     G_SMULO     = 95,
     111             :     G_UMULH     = 96,
     112             :     G_SMULH     = 97,
     113             :     G_FADD      = 98,
     114             :     G_FSUB      = 99,
     115             :     G_FMUL      = 100,
     116             :     G_FMA       = 101,
     117             :     G_FDIV      = 102,
     118             :     G_FREM      = 103,
     119             :     G_FPOW      = 104,
     120             :     G_FEXP      = 105,
     121             :     G_FEXP2     = 106,
     122             :     G_FLOG      = 107,
     123             :     G_FLOG2     = 108,
     124             :     G_FNEG      = 109,
     125             :     G_FPEXT     = 110,
     126             :     G_FPTRUNC   = 111,
     127             :     G_FPTOSI    = 112,
     128             :     G_FPTOUI    = 113,
     129             :     G_SITOFP    = 114,
     130             :     G_UITOFP    = 115,
     131             :     G_FABS      = 116,
     132             :     G_GEP       = 117,
     133             :     G_PTR_MASK  = 118,
     134             :     G_BR        = 119,
     135             :     G_INSERT_VECTOR_ELT = 120,
     136             :     G_EXTRACT_VECTOR_ELT        = 121,
     137             :     G_SHUFFLE_VECTOR    = 122,
     138             :     G_BSWAP     = 123,
     139             :     ABSMacro    = 124,
     140             :     ABSQ_S_PH   = 125,
     141             :     ABSQ_S_PH_MM        = 126,
     142             :     ABSQ_S_QB   = 127,
     143             :     ABSQ_S_QB_MMR2      = 128,
     144             :     ABSQ_S_W    = 129,
     145             :     ABSQ_S_W_MM = 130,
     146             :     ADD = 131,
     147             :     ADDIUPC     = 132,
     148             :     ADDIUPC_MM  = 133,
     149             :     ADDIUPC_MMR6        = 134,
     150             :     ADDIUR1SP_MM        = 135,
     151             :     ADDIUR2_MM  = 136,
     152             :     ADDIUS5_MM  = 137,
     153             :     ADDIUSP_MM  = 138,
     154             :     ADDIU_MMR6  = 139,
     155             :     ADDQH_PH    = 140,
     156             :     ADDQH_PH_MMR2       = 141,
     157             :     ADDQH_R_PH  = 142,
     158             :     ADDQH_R_PH_MMR2     = 143,
     159             :     ADDQH_R_W   = 144,
     160             :     ADDQH_R_W_MMR2      = 145,
     161             :     ADDQH_W     = 146,
     162             :     ADDQH_W_MMR2        = 147,
     163             :     ADDQ_PH     = 148,
     164             :     ADDQ_PH_MM  = 149,
     165             :     ADDQ_S_PH   = 150,
     166             :     ADDQ_S_PH_MM        = 151,
     167             :     ADDQ_S_W    = 152,
     168             :     ADDQ_S_W_MM = 153,
     169             :     ADDSC       = 154,
     170             :     ADDSC_MM    = 155,
     171             :     ADDS_A_B    = 156,
     172             :     ADDS_A_D    = 157,
     173             :     ADDS_A_H    = 158,
     174             :     ADDS_A_W    = 159,
     175             :     ADDS_S_B    = 160,
     176             :     ADDS_S_D    = 161,
     177             :     ADDS_S_H    = 162,
     178             :     ADDS_S_W    = 163,
     179             :     ADDS_U_B    = 164,
     180             :     ADDS_U_D    = 165,
     181             :     ADDS_U_H    = 166,
     182             :     ADDS_U_W    = 167,
     183             :     ADDU16_MM   = 168,
     184             :     ADDU16_MMR6 = 169,
     185             :     ADDUH_QB    = 170,
     186             :     ADDUH_QB_MMR2       = 171,
     187             :     ADDUH_R_QB  = 172,
     188             :     ADDUH_R_QB_MMR2     = 173,
     189             :     ADDU_MMR6   = 174,
     190             :     ADDU_PH     = 175,
     191             :     ADDU_PH_MMR2        = 176,
     192             :     ADDU_QB     = 177,
     193             :     ADDU_QB_MM  = 178,
     194             :     ADDU_S_PH   = 179,
     195             :     ADDU_S_PH_MMR2      = 180,
     196             :     ADDU_S_QB   = 181,
     197             :     ADDU_S_QB_MM        = 182,
     198             :     ADDVI_B     = 183,
     199             :     ADDVI_D     = 184,
     200             :     ADDVI_H     = 185,
     201             :     ADDVI_W     = 186,
     202             :     ADDV_B      = 187,
     203             :     ADDV_D      = 188,
     204             :     ADDV_H      = 189,
     205             :     ADDV_W      = 190,
     206             :     ADDWC       = 191,
     207             :     ADDWC_MM    = 192,
     208             :     ADD_A_B     = 193,
     209             :     ADD_A_D     = 194,
     210             :     ADD_A_H     = 195,
     211             :     ADD_A_W     = 196,
     212             :     ADD_MM      = 197,
     213             :     ADD_MMR6    = 198,
     214             :     ADDi        = 199,
     215             :     ADDi_MM     = 200,
     216             :     ADDiu       = 201,
     217             :     ADDiu_MM    = 202,
     218             :     ADDu        = 203,
     219             :     ADDu_MM     = 204,
     220             :     ADJCALLSTACKDOWN    = 205,
     221             :     ADJCALLSTACKUP      = 206,
     222             :     ALIGN       = 207,
     223             :     ALIGN_MMR6  = 208,
     224             :     ALUIPC      = 209,
     225             :     ALUIPC_MMR6 = 210,
     226             :     AND = 211,
     227             :     AND16_MM    = 212,
     228             :     AND16_MMR6  = 213,
     229             :     AND64       = 214,
     230             :     ANDI16_MM   = 215,
     231             :     ANDI16_MMR6 = 216,
     232             :     ANDI_B      = 217,
     233             :     ANDI_MMR6   = 218,
     234             :     AND_MM      = 219,
     235             :     AND_MMR6    = 220,
     236             :     AND_V       = 221,
     237             :     AND_V_D_PSEUDO      = 222,
     238             :     AND_V_H_PSEUDO      = 223,
     239             :     AND_V_W_PSEUDO      = 224,
     240             :     ANDi        = 225,
     241             :     ANDi64      = 226,
     242             :     ANDi_MM     = 227,
     243             :     APPEND      = 228,
     244             :     APPEND_MMR2 = 229,
     245             :     ASUB_S_B    = 230,
     246             :     ASUB_S_D    = 231,
     247             :     ASUB_S_H    = 232,
     248             :     ASUB_S_W    = 233,
     249             :     ASUB_U_B    = 234,
     250             :     ASUB_U_D    = 235,
     251             :     ASUB_U_H    = 236,
     252             :     ASUB_U_W    = 237,
     253             :     ATOMIC_CMP_SWAP_I16 = 238,
     254             :     ATOMIC_CMP_SWAP_I32 = 239,
     255             :     ATOMIC_CMP_SWAP_I64 = 240,
     256             :     ATOMIC_CMP_SWAP_I8  = 241,
     257             :     ATOMIC_LOAD_ADD_I16 = 242,
     258             :     ATOMIC_LOAD_ADD_I32 = 243,
     259             :     ATOMIC_LOAD_ADD_I64 = 244,
     260             :     ATOMIC_LOAD_ADD_I8  = 245,
     261             :     ATOMIC_LOAD_AND_I16 = 246,
     262             :     ATOMIC_LOAD_AND_I32 = 247,
     263             :     ATOMIC_LOAD_AND_I64 = 248,
     264             :     ATOMIC_LOAD_AND_I8  = 249,
     265             :     ATOMIC_LOAD_NAND_I16        = 250,
     266             :     ATOMIC_LOAD_NAND_I32        = 251,
     267             :     ATOMIC_LOAD_NAND_I64        = 252,
     268             :     ATOMIC_LOAD_NAND_I8 = 253,
     269             :     ATOMIC_LOAD_OR_I16  = 254,
     270             :     ATOMIC_LOAD_OR_I32  = 255,
     271             :     ATOMIC_LOAD_OR_I64  = 256,
     272             :     ATOMIC_LOAD_OR_I8   = 257,
     273             :     ATOMIC_LOAD_SUB_I16 = 258,
     274             :     ATOMIC_LOAD_SUB_I32 = 259,
     275             :     ATOMIC_LOAD_SUB_I64 = 260,
     276             :     ATOMIC_LOAD_SUB_I8  = 261,
     277             :     ATOMIC_LOAD_XOR_I16 = 262,
     278             :     ATOMIC_LOAD_XOR_I32 = 263,
     279             :     ATOMIC_LOAD_XOR_I64 = 264,
     280             :     ATOMIC_LOAD_XOR_I8  = 265,
     281             :     ATOMIC_SWAP_I16     = 266,
     282             :     ATOMIC_SWAP_I32     = 267,
     283             :     ATOMIC_SWAP_I64     = 268,
     284             :     ATOMIC_SWAP_I8      = 269,
     285             :     AUI = 270,
     286             :     AUIPC       = 271,
     287             :     AUIPC_MMR6  = 272,
     288             :     AUI_MMR6    = 273,
     289             :     AVER_S_B    = 274,
     290             :     AVER_S_D    = 275,
     291             :     AVER_S_H    = 276,
     292             :     AVER_S_W    = 277,
     293             :     AVER_U_B    = 278,
     294             :     AVER_U_D    = 279,
     295             :     AVER_U_H    = 280,
     296             :     AVER_U_W    = 281,
     297             :     AVE_S_B     = 282,
     298             :     AVE_S_D     = 283,
     299             :     AVE_S_H     = 284,
     300             :     AVE_S_W     = 285,
     301             :     AVE_U_B     = 286,
     302             :     AVE_U_D     = 287,
     303             :     AVE_U_H     = 288,
     304             :     AVE_U_W     = 289,
     305             :     AddiuRxImmX16       = 290,
     306             :     AddiuRxPcImmX16     = 291,
     307             :     AddiuRxRxImm16      = 292,
     308             :     AddiuRxRxImmX16     = 293,
     309             :     AddiuRxRyOffMemX16  = 294,
     310             :     AddiuSpImm16        = 295,
     311             :     AddiuSpImmX16       = 296,
     312             :     AdduRxRyRz16        = 297,
     313             :     AndRxRxRy16 = 298,
     314             :     B   = 299,
     315             :     B16_MM      = 300,
     316             :     BADDu       = 301,
     317             :     BAL = 302,
     318             :     BALC        = 303,
     319             :     BALC_MMR6   = 304,
     320             :     BALIGN      = 305,
     321             :     BALIGN_MMR2 = 306,
     322             :     BAL_BR      = 307,
     323             :     BAL_BR_MM   = 308,
     324             :     BBIT0       = 309,
     325             :     BBIT032     = 310,
     326             :     BBIT1       = 311,
     327             :     BBIT132     = 312,
     328             :     BC  = 313,
     329             :     BC16_MMR6   = 314,
     330             :     BC1EQZ      = 315,
     331             :     BC1EQZC_MMR6        = 316,
     332             :     BC1F        = 317,
     333             :     BC1FL       = 318,
     334             :     BC1F_MM     = 319,
     335             :     BC1NEZ      = 320,
     336             :     BC1NEZC_MMR6        = 321,
     337             :     BC1T        = 322,
     338             :     BC1TL       = 323,
     339             :     BC1T_MM     = 324,
     340             :     BC2EQZ      = 325,
     341             :     BC2EQZC_MMR6        = 326,
     342             :     BC2NEZ      = 327,
     343             :     BC2NEZC_MMR6        = 328,
     344             :     BCLRI_B     = 329,
     345             :     BCLRI_D     = 330,
     346             :     BCLRI_H     = 331,
     347             :     BCLRI_W     = 332,
     348             :     BCLR_B      = 333,
     349             :     BCLR_D      = 334,
     350             :     BCLR_H      = 335,
     351             :     BCLR_W      = 336,
     352             :     BC_MMR6     = 337,
     353             :     BEQ = 338,
     354             :     BEQ64       = 339,
     355             :     BEQC        = 340,
     356             :     BEQC64      = 341,
     357             :     BEQC_MMR6   = 342,
     358             :     BEQL        = 343,
     359             :     BEQLImmMacro        = 344,
     360             :     BEQZ16_MM   = 345,
     361             :     BEQZALC     = 346,
     362             :     BEQZALC_MMR6        = 347,
     363             :     BEQZC       = 348,
     364             :     BEQZC16_MMR6        = 349,
     365             :     BEQZC64     = 350,
     366             :     BEQZC_MM    = 351,
     367             :     BEQZC_MMR6  = 352,
     368             :     BEQ_MM      = 353,
     369             :     BGE = 354,
     370             :     BGEC        = 355,
     371             :     BGEC64      = 356,
     372             :     BGEC_MMR6   = 357,
     373             :     BGEImmMacro = 358,
     374             :     BGEL        = 359,
     375             :     BGELImmMacro        = 360,
     376             :     BGEU        = 361,
     377             :     BGEUC       = 362,
     378             :     BGEUC64     = 363,
     379             :     BGEUC_MMR6  = 364,
     380             :     BGEUImmMacro        = 365,
     381             :     BGEUL       = 366,
     382             :     BGEULImmMacro       = 367,
     383             :     BGEZ        = 368,
     384             :     BGEZ64      = 369,
     385             :     BGEZAL      = 370,
     386             :     BGEZALC     = 371,
     387             :     BGEZALC_MMR6        = 372,
     388             :     BGEZALL     = 373,
     389             :     BGEZALS_MM  = 374,
     390             :     BGEZAL_MM   = 375,
     391             :     BGEZC       = 376,
     392             :     BGEZC64     = 377,
     393             :     BGEZC_MMR6  = 378,
     394             :     BGEZL       = 379,
     395             :     BGEZ_MM     = 380,
     396             :     BGT = 381,
     397             :     BGTImmMacro = 382,
     398             :     BGTL        = 383,
     399             :     BGTLImmMacro        = 384,
     400             :     BGTU        = 385,
     401             :     BGTUImmMacro        = 386,
     402             :     BGTUL       = 387,
     403             :     BGTULImmMacro       = 388,
     404             :     BGTZ        = 389,
     405             :     BGTZ64      = 390,
     406             :     BGTZALC     = 391,
     407             :     BGTZALC_MMR6        = 392,
     408             :     BGTZC       = 393,
     409             :     BGTZC64     = 394,
     410             :     BGTZC_MMR6  = 395,
     411             :     BGTZL       = 396,
     412             :     BGTZ_MM     = 397,
     413             :     BINSLI_B    = 398,
     414             :     BINSLI_D    = 399,
     415             :     BINSLI_H    = 400,
     416             :     BINSLI_W    = 401,
     417             :     BINSL_B     = 402,
     418             :     BINSL_D     = 403,
     419             :     BINSL_H     = 404,
     420             :     BINSL_W     = 405,
     421             :     BINSRI_B    = 406,
     422             :     BINSRI_D    = 407,
     423             :     BINSRI_H    = 408,
     424             :     BINSRI_W    = 409,
     425             :     BINSR_B     = 410,
     426             :     BINSR_D     = 411,
     427             :     BINSR_H     = 412,
     428             :     BINSR_W     = 413,
     429             :     BITREV      = 414,
     430             :     BITREV_MM   = 415,
     431             :     BITSWAP     = 416,
     432             :     BITSWAP_MMR6        = 417,
     433             :     BLE = 418,
     434             :     BLEImmMacro = 419,
     435             :     BLEL        = 420,
     436             :     BLELImmMacro        = 421,
     437             :     BLEU        = 422,
     438             :     BLEUImmMacro        = 423,
     439             :     BLEUL       = 424,
     440             :     BLEULImmMacro       = 425,
     441             :     BLEZ        = 426,
     442             :     BLEZ64      = 427,
     443             :     BLEZALC     = 428,
     444             :     BLEZALC_MMR6        = 429,
     445             :     BLEZC       = 430,
     446             :     BLEZC64     = 431,
     447             :     BLEZC_MMR6  = 432,
     448             :     BLEZL       = 433,
     449             :     BLEZ_MM     = 434,
     450             :     BLT = 435,
     451             :     BLTC        = 436,
     452             :     BLTC64      = 437,
     453             :     BLTC_MMR6   = 438,
     454             :     BLTImmMacro = 439,
     455             :     BLTL        = 440,
     456             :     BLTLImmMacro        = 441,
     457             :     BLTU        = 442,
     458             :     BLTUC       = 443,
     459             :     BLTUC64     = 444,
     460             :     BLTUC_MMR6  = 445,
     461             :     BLTUImmMacro        = 446,
     462             :     BLTUL       = 447,
     463             :     BLTULImmMacro       = 448,
     464             :     BLTZ        = 449,
     465             :     BLTZ64      = 450,
     466             :     BLTZAL      = 451,
     467             :     BLTZALC     = 452,
     468             :     BLTZALC_MMR6        = 453,
     469             :     BLTZALL     = 454,
     470             :     BLTZALS_MM  = 455,
     471             :     BLTZAL_MM   = 456,
     472             :     BLTZC       = 457,
     473             :     BLTZC64     = 458,
     474             :     BLTZC_MMR6  = 459,
     475             :     BLTZL       = 460,
     476             :     BLTZ_MM     = 461,
     477             :     BMNZI_B     = 462,
     478             :     BMNZ_V      = 463,
     479             :     BMZI_B      = 464,
     480             :     BMZ_V       = 465,
     481             :     BNE = 466,
     482             :     BNE64       = 467,
     483             :     BNEC        = 468,
     484             :     BNEC64      = 469,
     485             :     BNEC_MMR6   = 470,
     486             :     BNEGI_B     = 471,
     487             :     BNEGI_D     = 472,
     488             :     BNEGI_H     = 473,
     489             :     BNEGI_W     = 474,
     490             :     BNEG_B      = 475,
     491             :     BNEG_D      = 476,
     492             :     BNEG_H      = 477,
     493             :     BNEG_W      = 478,
     494             :     BNEL        = 479,
     495             :     BNELImmMacro        = 480,
     496             :     BNEZ16_MM   = 481,
     497             :     BNEZALC     = 482,
     498             :     BNEZALC_MMR6        = 483,
     499             :     BNEZC       = 484,
     500             :     BNEZC16_MMR6        = 485,
     501             :     BNEZC64     = 486,
     502             :     BNEZC_MM    = 487,
     503             :     BNEZC_MMR6  = 488,
     504             :     BNE_MM      = 489,
     505             :     BNVC        = 490,
     506             :     BNVC_MMR6   = 491,
     507             :     BNZ_B       = 492,
     508             :     BNZ_D       = 493,
     509             :     BNZ_H       = 494,
     510             :     BNZ_V       = 495,
     511             :     BNZ_W       = 496,
     512             :     BOVC        = 497,
     513             :     BOVC_MMR6   = 498,
     514             :     BPOSGE32    = 499,
     515             :     BPOSGE32C_MMR3      = 500,
     516             :     BPOSGE32_MM = 501,
     517             :     BPOSGE32_PSEUDO     = 502,
     518             :     BREAK       = 503,
     519             :     BREAK16_MM  = 504,
     520             :     BREAK16_MMR6        = 505,
     521             :     BREAK_MM    = 506,
     522             :     BREAK_MMR6  = 507,
     523             :     BSELI_B     = 508,
     524             :     BSEL_D_PSEUDO       = 509,
     525             :     BSEL_FD_PSEUDO      = 510,
     526             :     BSEL_FW_PSEUDO      = 511,
     527             :     BSEL_H_PSEUDO       = 512,
     528             :     BSEL_V      = 513,
     529             :     BSEL_W_PSEUDO       = 514,
     530             :     BSETI_B     = 515,
     531             :     BSETI_D     = 516,
     532             :     BSETI_H     = 517,
     533             :     BSETI_W     = 518,
     534             :     BSET_B      = 519,
     535             :     BSET_D      = 520,
     536             :     BSET_H      = 521,
     537             :     BSET_W      = 522,
     538             :     BZ_B        = 523,
     539             :     BZ_D        = 524,
     540             :     BZ_H        = 525,
     541             :     BZ_V        = 526,
     542             :     BZ_W        = 527,
     543             :     B_MM        = 528,
     544             :     B_MMR6_Pseudo       = 529,
     545             :     B_MM_Pseudo = 530,
     546             :     BeqImm      = 531,
     547             :     BeqzRxImm16 = 532,
     548             :     BeqzRxImmX16        = 533,
     549             :     Bimm16      = 534,
     550             :     BimmX16     = 535,
     551             :     BneImm      = 536,
     552             :     BnezRxImm16 = 537,
     553             :     BnezRxImmX16        = 538,
     554             :     Break16     = 539,
     555             :     Bteqz16     = 540,
     556             :     BteqzT8CmpX16       = 541,
     557             :     BteqzT8CmpiX16      = 542,
     558             :     BteqzT8SltX16       = 543,
     559             :     BteqzT8SltiX16      = 544,
     560             :     BteqzT8SltiuX16     = 545,
     561             :     BteqzT8SltuX16      = 546,
     562             :     BteqzX16    = 547,
     563             :     Btnez16     = 548,
     564             :     BtnezT8CmpX16       = 549,
     565             :     BtnezT8CmpiX16      = 550,
     566             :     BtnezT8SltX16       = 551,
     567             :     BtnezT8SltiX16      = 552,
     568             :     BtnezT8SltiuX16     = 553,
     569             :     BtnezT8SltuX16      = 554,
     570             :     BtnezX16    = 555,
     571             :     BuildPairF64        = 556,
     572             :     BuildPairF64_64     = 557,
     573             :     CACHE       = 558,
     574             :     CACHEE      = 559,
     575             :     CACHEE_MM   = 560,
     576             :     CACHE_MM    = 561,
     577             :     CACHE_MMR6  = 562,
     578             :     CACHE_R6    = 563,
     579             :     CEIL_L_D64  = 564,
     580             :     CEIL_L_D_MMR6       = 565,
     581             :     CEIL_L_S    = 566,
     582             :     CEIL_L_S_MMR6       = 567,
     583             :     CEIL_W_D32  = 568,
     584             :     CEIL_W_D64  = 569,
     585             :     CEIL_W_D_MMR6       = 570,
     586             :     CEIL_W_MM   = 571,
     587             :     CEIL_W_S    = 572,
     588             :     CEIL_W_S_MM = 573,
     589             :     CEIL_W_S_MMR6       = 574,
     590             :     CEQI_B      = 575,
     591             :     CEQI_D      = 576,
     592             :     CEQI_H      = 577,
     593             :     CEQI_W      = 578,
     594             :     CEQ_B       = 579,
     595             :     CEQ_D       = 580,
     596             :     CEQ_H       = 581,
     597             :     CEQ_W       = 582,
     598             :     CFC1        = 583,
     599             :     CFC1_MM     = 584,
     600             :     CFC2_MM     = 585,
     601             :     CFCMSA      = 586,
     602             :     CFTC1       = 587,
     603             :     CINS        = 588,
     604             :     CINS32      = 589,
     605             :     CINS64_32   = 590,
     606             :     CINS_i32    = 591,
     607             :     CLASS_D     = 592,
     608             :     CLASS_D_MMR6        = 593,
     609             :     CLASS_S     = 594,
     610             :     CLASS_S_MMR6        = 595,
     611             :     CLEI_S_B    = 596,
     612             :     CLEI_S_D    = 597,
     613             :     CLEI_S_H    = 598,
     614             :     CLEI_S_W    = 599,
     615             :     CLEI_U_B    = 600,
     616             :     CLEI_U_D    = 601,
     617             :     CLEI_U_H    = 602,
     618             :     CLEI_U_W    = 603,
     619             :     CLE_S_B     = 604,
     620             :     CLE_S_D     = 605,
     621             :     CLE_S_H     = 606,
     622             :     CLE_S_W     = 607,
     623             :     CLE_U_B     = 608,
     624             :     CLE_U_D     = 609,
     625             :     CLE_U_H     = 610,
     626             :     CLE_U_W     = 611,
     627             :     CLO = 612,
     628             :     CLO_MM      = 613,
     629             :     CLO_MMR6    = 614,
     630             :     CLO_R6      = 615,
     631             :     CLTI_S_B    = 616,
     632             :     CLTI_S_D    = 617,
     633             :     CLTI_S_H    = 618,
     634             :     CLTI_S_W    = 619,
     635             :     CLTI_U_B    = 620,
     636             :     CLTI_U_D    = 621,
     637             :     CLTI_U_H    = 622,
     638             :     CLTI_U_W    = 623,
     639             :     CLT_S_B     = 624,
     640             :     CLT_S_D     = 625,
     641             :     CLT_S_H     = 626,
     642             :     CLT_S_W     = 627,
     643             :     CLT_U_B     = 628,
     644             :     CLT_U_D     = 629,
     645             :     CLT_U_H     = 630,
     646             :     CLT_U_W     = 631,
     647             :     CLZ = 632,
     648             :     CLZ_MM      = 633,
     649             :     CLZ_MMR6    = 634,
     650             :     CLZ_R6      = 635,
     651             :     CMPGDU_EQ_QB        = 636,
     652             :     CMPGDU_EQ_QB_MMR2   = 637,
     653             :     CMPGDU_LE_QB        = 638,
     654             :     CMPGDU_LE_QB_MMR2   = 639,
     655             :     CMPGDU_LT_QB        = 640,
     656             :     CMPGDU_LT_QB_MMR2   = 641,
     657             :     CMPGU_EQ_QB = 642,
     658             :     CMPGU_EQ_QB_MM      = 643,
     659             :     CMPGU_LE_QB = 644,
     660             :     CMPGU_LE_QB_MM      = 645,
     661             :     CMPGU_LT_QB = 646,
     662             :     CMPGU_LT_QB_MM      = 647,
     663             :     CMPU_EQ_QB  = 648,
     664             :     CMPU_EQ_QB_MM       = 649,
     665             :     CMPU_LE_QB  = 650,
     666             :     CMPU_LE_QB_MM       = 651,
     667             :     CMPU_LT_QB  = 652,
     668             :     CMPU_LT_QB_MM       = 653,
     669             :     CMP_AF_D_MMR6       = 654,
     670             :     CMP_AF_S_MMR6       = 655,
     671             :     CMP_EQ_D    = 656,
     672             :     CMP_EQ_D_MMR6       = 657,
     673             :     CMP_EQ_PH   = 658,
     674             :     CMP_EQ_PH_MM        = 659,
     675             :     CMP_EQ_S    = 660,
     676             :     CMP_EQ_S_MMR6       = 661,
     677             :     CMP_F_D     = 662,
     678             :     CMP_F_S     = 663,
     679             :     CMP_LE_D    = 664,
     680             :     CMP_LE_D_MMR6       = 665,
     681             :     CMP_LE_PH   = 666,
     682             :     CMP_LE_PH_MM        = 667,
     683             :     CMP_LE_S    = 668,
     684             :     CMP_LE_S_MMR6       = 669,
     685             :     CMP_LT_D    = 670,
     686             :     CMP_LT_D_MMR6       = 671,
     687             :     CMP_LT_PH   = 672,
     688             :     CMP_LT_PH_MM        = 673,
     689             :     CMP_LT_S    = 674,
     690             :     CMP_LT_S_MMR6       = 675,
     691             :     CMP_SAF_D   = 676,
     692             :     CMP_SAF_D_MMR6      = 677,
     693             :     CMP_SAF_S   = 678,
     694             :     CMP_SAF_S_MMR6      = 679,
     695             :     CMP_SEQ_D   = 680,
     696             :     CMP_SEQ_D_MMR6      = 681,
     697             :     CMP_SEQ_S   = 682,
     698             :     CMP_SEQ_S_MMR6      = 683,
     699             :     CMP_SLE_D   = 684,
     700             :     CMP_SLE_D_MMR6      = 685,
     701             :     CMP_SLE_S   = 686,
     702             :     CMP_SLE_S_MMR6      = 687,
     703             :     CMP_SLT_D   = 688,
     704             :     CMP_SLT_D_MMR6      = 689,
     705             :     CMP_SLT_S   = 690,
     706             :     CMP_SLT_S_MMR6      = 691,
     707             :     CMP_SUEQ_D  = 692,
     708             :     CMP_SUEQ_D_MMR6     = 693,
     709             :     CMP_SUEQ_S  = 694,
     710             :     CMP_SUEQ_S_MMR6     = 695,
     711             :     CMP_SULE_D  = 696,
     712             :     CMP_SULE_D_MMR6     = 697,
     713             :     CMP_SULE_S  = 698,
     714             :     CMP_SULE_S_MMR6     = 699,
     715             :     CMP_SULT_D  = 700,
     716             :     CMP_SULT_D_MMR6     = 701,
     717             :     CMP_SULT_S  = 702,
     718             :     CMP_SULT_S_MMR6     = 703,
     719             :     CMP_SUN_D   = 704,
     720             :     CMP_SUN_D_MMR6      = 705,
     721             :     CMP_SUN_S   = 706,
     722             :     CMP_SUN_S_MMR6      = 707,
     723             :     CMP_UEQ_D   = 708,
     724             :     CMP_UEQ_D_MMR6      = 709,
     725             :     CMP_UEQ_S   = 710,
     726             :     CMP_UEQ_S_MMR6      = 711,
     727             :     CMP_ULE_D   = 712,
     728             :     CMP_ULE_D_MMR6      = 713,
     729             :     CMP_ULE_S   = 714,
     730             :     CMP_ULE_S_MMR6      = 715,
     731             :     CMP_ULT_D   = 716,
     732             :     CMP_ULT_D_MMR6      = 717,
     733             :     CMP_ULT_S   = 718,
     734             :     CMP_ULT_S_MMR6      = 719,
     735             :     CMP_UN_D    = 720,
     736             :     CMP_UN_D_MMR6       = 721,
     737             :     CMP_UN_S    = 722,
     738             :     CMP_UN_S_MMR6       = 723,
     739             :     CONSTPOOL_ENTRY     = 724,
     740             :     COPY_FD_PSEUDO      = 725,
     741             :     COPY_FW_PSEUDO      = 726,
     742             :     COPY_S_B    = 727,
     743             :     COPY_S_D    = 728,
     744             :     COPY_S_H    = 729,
     745             :     COPY_S_W    = 730,
     746             :     COPY_U_B    = 731,
     747             :     COPY_U_H    = 732,
     748             :     COPY_U_W    = 733,
     749             :     CRC32B      = 734,
     750             :     CRC32CB     = 735,
     751             :     CRC32CD     = 736,
     752             :     CRC32CH     = 737,
     753             :     CRC32CW     = 738,
     754             :     CRC32D      = 739,
     755             :     CRC32H      = 740,
     756             :     CRC32W      = 741,
     757             :     CTC1        = 742,
     758             :     CTC1_MM     = 743,
     759             :     CTC2_MM     = 744,
     760             :     CTCMSA      = 745,
     761             :     CTTC1       = 746,
     762             :     CVT_D32_S   = 747,
     763             :     CVT_D32_S_MM        = 748,
     764             :     CVT_D32_W   = 749,
     765             :     CVT_D32_W_MM        = 750,
     766             :     CVT_D64_L   = 751,
     767             :     CVT_D64_S   = 752,
     768             :     CVT_D64_S_MM        = 753,
     769             :     CVT_D64_W   = 754,
     770             :     CVT_D64_W_MM        = 755,
     771             :     CVT_D_L_MMR6        = 756,
     772             :     CVT_L_D64   = 757,
     773             :     CVT_L_D64_MM        = 758,
     774             :     CVT_L_D_MMR6        = 759,
     775             :     CVT_L_S     = 760,
     776             :     CVT_L_S_MM  = 761,
     777             :     CVT_L_S_MMR6        = 762,
     778             :     CVT_S_D32   = 763,
     779             :     CVT_S_D32_MM        = 764,
     780             :     CVT_S_D64   = 765,
     781             :     CVT_S_D64_MM        = 766,
     782             :     CVT_S_L     = 767,
     783             :     CVT_S_L_MMR6        = 768,
     784             :     CVT_S_W     = 769,
     785             :     CVT_S_W_MM  = 770,
     786             :     CVT_S_W_MMR6        = 771,
     787             :     CVT_W_D32   = 772,
     788             :     CVT_W_D32_MM        = 773,
     789             :     CVT_W_D64   = 774,
     790             :     CVT_W_D64_MM        = 775,
     791             :     CVT_W_S     = 776,
     792             :     CVT_W_S_MM  = 777,
     793             :     CVT_W_S_MMR6        = 778,
     794             :     C_EQ_D32    = 779,
     795             :     C_EQ_D32_MM = 780,
     796             :     C_EQ_D64    = 781,
     797             :     C_EQ_D64_MM = 782,
     798             :     C_EQ_S      = 783,
     799             :     C_EQ_S_MM   = 784,
     800             :     C_F_D32     = 785,
     801             :     C_F_D32_MM  = 786,
     802             :     C_F_D64     = 787,
     803             :     C_F_D64_MM  = 788,
     804             :     C_F_S       = 789,
     805             :     C_F_S_MM    = 790,
     806             :     C_LE_D32    = 791,
     807             :     C_LE_D32_MM = 792,
     808             :     C_LE_D64    = 793,
     809             :     C_LE_D64_MM = 794,
     810             :     C_LE_S      = 795,
     811             :     C_LE_S_MM   = 796,
     812             :     C_LT_D32    = 797,
     813             :     C_LT_D32_MM = 798,
     814             :     C_LT_D64    = 799,
     815             :     C_LT_D64_MM = 800,
     816             :     C_LT_S      = 801,
     817             :     C_LT_S_MM   = 802,
     818             :     C_NGE_D32   = 803,
     819             :     C_NGE_D32_MM        = 804,
     820             :     C_NGE_D64   = 805,
     821             :     C_NGE_D64_MM        = 806,
     822             :     C_NGE_S     = 807,
     823             :     C_NGE_S_MM  = 808,
     824             :     C_NGLE_D32  = 809,
     825             :     C_NGLE_D32_MM       = 810,
     826             :     C_NGLE_D64  = 811,
     827             :     C_NGLE_D64_MM       = 812,
     828             :     C_NGLE_S    = 813,
     829             :     C_NGLE_S_MM = 814,
     830             :     C_NGL_D32   = 815,
     831             :     C_NGL_D32_MM        = 816,
     832             :     C_NGL_D64   = 817,
     833             :     C_NGL_D64_MM        = 818,
     834             :     C_NGL_S     = 819,
     835             :     C_NGL_S_MM  = 820,
     836             :     C_NGT_D32   = 821,
     837             :     C_NGT_D32_MM        = 822,
     838             :     C_NGT_D64   = 823,
     839             :     C_NGT_D64_MM        = 824,
     840             :     C_NGT_S     = 825,
     841             :     C_NGT_S_MM  = 826,
     842             :     C_OLE_D32   = 827,
     843             :     C_OLE_D32_MM        = 828,
     844             :     C_OLE_D64   = 829,
     845             :     C_OLE_D64_MM        = 830,
     846             :     C_OLE_S     = 831,
     847             :     C_OLE_S_MM  = 832,
     848             :     C_OLT_D32   = 833,
     849             :     C_OLT_D32_MM        = 834,
     850             :     C_OLT_D64   = 835,
     851             :     C_OLT_D64_MM        = 836,
     852             :     C_OLT_S     = 837,
     853             :     C_OLT_S_MM  = 838,
     854             :     C_SEQ_D32   = 839,
     855             :     C_SEQ_D32_MM        = 840,
     856             :     C_SEQ_D64   = 841,
     857             :     C_SEQ_D64_MM        = 842,
     858             :     C_SEQ_S     = 843,
     859             :     C_SEQ_S_MM  = 844,
     860             :     C_SF_D32    = 845,
     861             :     C_SF_D32_MM = 846,
     862             :     C_SF_D64    = 847,
     863             :     C_SF_D64_MM = 848,
     864             :     C_SF_S      = 849,
     865             :     C_SF_S_MM   = 850,
     866             :     C_UEQ_D32   = 851,
     867             :     C_UEQ_D32_MM        = 852,
     868             :     C_UEQ_D64   = 853,
     869             :     C_UEQ_D64_MM        = 854,
     870             :     C_UEQ_S     = 855,
     871             :     C_UEQ_S_MM  = 856,
     872             :     C_ULE_D32   = 857,
     873             :     C_ULE_D32_MM        = 858,
     874             :     C_ULE_D64   = 859,
     875             :     C_ULE_D64_MM        = 860,
     876             :     C_ULE_S     = 861,
     877             :     C_ULE_S_MM  = 862,
     878             :     C_ULT_D32   = 863,
     879             :     C_ULT_D32_MM        = 864,
     880             :     C_ULT_D64   = 865,
     881             :     C_ULT_D64_MM        = 866,
     882             :     C_ULT_S     = 867,
     883             :     C_ULT_S_MM  = 868,
     884             :     C_UN_D32    = 869,
     885             :     C_UN_D32_MM = 870,
     886             :     C_UN_D64    = 871,
     887             :     C_UN_D64_MM = 872,
     888             :     C_UN_S      = 873,
     889             :     C_UN_S_MM   = 874,
     890             :     CmpRxRy16   = 875,
     891             :     CmpiRxImm16 = 876,
     892             :     CmpiRxImmX16        = 877,
     893             :     Constant32  = 878,
     894             :     DADD        = 879,
     895             :     DADDi       = 880,
     896             :     DADDiu      = 881,
     897             :     DADDu       = 882,
     898             :     DAHI        = 883,
     899             :     DALIGN      = 884,
     900             :     DATI        = 885,
     901             :     DAUI        = 886,
     902             :     DBITSWAP    = 887,
     903             :     DCLO        = 888,
     904             :     DCLO_R6     = 889,
     905             :     DCLZ        = 890,
     906             :     DCLZ_R6     = 891,
     907             :     DDIV        = 892,
     908             :     DDIVU       = 893,
     909             :     DERET       = 894,
     910             :     DERET_MM    = 895,
     911             :     DERET_MMR6  = 896,
     912             :     DEXT        = 897,
     913             :     DEXT64_32   = 898,
     914             :     DEXTM       = 899,
     915             :     DEXTU       = 900,
     916             :     DI  = 901,
     917             :     DINS        = 902,
     918             :     DINSM       = 903,
     919             :     DINSU       = 904,
     920             :     DIV = 905,
     921             :     DIVU        = 906,
     922             :     DIVU_MMR6   = 907,
     923             :     DIV_MMR6    = 908,
     924             :     DIV_S_B     = 909,
     925             :     DIV_S_D     = 910,
     926             :     DIV_S_H     = 911,
     927             :     DIV_S_W     = 912,
     928             :     DIV_U_B     = 913,
     929             :     DIV_U_D     = 914,
     930             :     DIV_U_H     = 915,
     931             :     DIV_U_W     = 916,
     932             :     DI_MM       = 917,
     933             :     DI_MMR6     = 918,
     934             :     DLSA        = 919,
     935             :     DLSA_R6     = 920,
     936             :     DMFC0       = 921,
     937             :     DMFC1       = 922,
     938             :     DMFC2       = 923,
     939             :     DMFC2_OCTEON        = 924,
     940             :     DMFGC0      = 925,
     941             :     DMOD        = 926,
     942             :     DMODU       = 927,
     943             :     DMT = 928,
     944             :     DMTC0       = 929,
     945             :     DMTC1       = 930,
     946             :     DMTC2       = 931,
     947             :     DMTC2_OCTEON        = 932,
     948             :     DMTGC0      = 933,
     949             :     DMUH        = 934,
     950             :     DMUHU       = 935,
     951             :     DMUL        = 936,
     952             :     DMULImmMacro        = 937,
     953             :     DMULMacro   = 938,
     954             :     DMULOMacro  = 939,
     955             :     DMULOUMacro = 940,
     956             :     DMULT       = 941,
     957             :     DMULTu      = 942,
     958             :     DMULU       = 943,
     959             :     DMUL_R6     = 944,
     960             :     DOTP_S_D    = 945,
     961             :     DOTP_S_H    = 946,
     962             :     DOTP_S_W    = 947,
     963             :     DOTP_U_D    = 948,
     964             :     DOTP_U_H    = 949,
     965             :     DOTP_U_W    = 950,
     966             :     DPADD_S_D   = 951,
     967             :     DPADD_S_H   = 952,
     968             :     DPADD_S_W   = 953,
     969             :     DPADD_U_D   = 954,
     970             :     DPADD_U_H   = 955,
     971             :     DPADD_U_W   = 956,
     972             :     DPAQX_SA_W_PH       = 957,
     973             :     DPAQX_SA_W_PH_MMR2  = 958,
     974             :     DPAQX_S_W_PH        = 959,
     975             :     DPAQX_S_W_PH_MMR2   = 960,
     976             :     DPAQ_SA_L_W = 961,
     977             :     DPAQ_SA_L_W_MM      = 962,
     978             :     DPAQ_S_W_PH = 963,
     979             :     DPAQ_S_W_PH_MM      = 964,
     980             :     DPAU_H_QBL  = 965,
     981             :     DPAU_H_QBL_MM       = 966,
     982             :     DPAU_H_QBR  = 967,
     983             :     DPAU_H_QBR_MM       = 968,
     984             :     DPAX_W_PH   = 969,
     985             :     DPAX_W_PH_MMR2      = 970,
     986             :     DPA_W_PH    = 971,
     987             :     DPA_W_PH_MMR2       = 972,
     988             :     DPOP        = 973,
     989             :     DPSQX_SA_W_PH       = 974,
     990             :     DPSQX_SA_W_PH_MMR2  = 975,
     991             :     DPSQX_S_W_PH        = 976,
     992             :     DPSQX_S_W_PH_MMR2   = 977,
     993             :     DPSQ_SA_L_W = 978,
     994             :     DPSQ_SA_L_W_MM      = 979,
     995             :     DPSQ_S_W_PH = 980,
     996             :     DPSQ_S_W_PH_MM      = 981,
     997             :     DPSUB_S_D   = 982,
     998             :     DPSUB_S_H   = 983,
     999             :     DPSUB_S_W   = 984,
    1000             :     DPSUB_U_D   = 985,
    1001             :     DPSUB_U_H   = 986,
    1002             :     DPSUB_U_W   = 987,
    1003             :     DPSU_H_QBL  = 988,
    1004             :     DPSU_H_QBL_MM       = 989,
    1005             :     DPSU_H_QBR  = 990,
    1006             :     DPSU_H_QBR_MM       = 991,
    1007             :     DPSX_W_PH   = 992,
    1008             :     DPSX_W_PH_MMR2      = 993,
    1009             :     DPS_W_PH    = 994,
    1010             :     DPS_W_PH_MMR2       = 995,
    1011             :     DROL        = 996,
    1012             :     DROLImm     = 997,
    1013             :     DROR        = 998,
    1014             :     DRORImm     = 999,
    1015             :     DROTR       = 1000,
    1016             :     DROTR32     = 1001,
    1017             :     DROTRV      = 1002,
    1018             :     DSBH        = 1003,
    1019             :     DSDIV       = 1004,
    1020             :     DSDivIMacro = 1005,
    1021             :     DSDivMacro  = 1006,
    1022             :     DSHD        = 1007,
    1023             :     DSLL        = 1008,
    1024             :     DSLL32      = 1009,
    1025             :     DSLL64_32   = 1010,
    1026             :     DSLLV       = 1011,
    1027             :     DSRA        = 1012,
    1028             :     DSRA32      = 1013,
    1029             :     DSRAV       = 1014,
    1030             :     DSRL        = 1015,
    1031             :     DSRL32      = 1016,
    1032             :     DSRLV       = 1017,
    1033             :     DSUB        = 1018,
    1034             :     DSUBu       = 1019,
    1035             :     DUDIV       = 1020,
    1036             :     DUDivIMacro = 1021,
    1037             :     DUDivMacro  = 1022,
    1038             :     DVP = 1023,
    1039             :     DVPE        = 1024,
    1040             :     DVP_MMR6    = 1025,
    1041             :     DivRxRy16   = 1026,
    1042             :     DivuRxRy16  = 1027,
    1043             :     EHB = 1028,
    1044             :     EHB_MM      = 1029,
    1045             :     EHB_MMR6    = 1030,
    1046             :     EI  = 1031,
    1047             :     EI_MM       = 1032,
    1048             :     EI_MMR6     = 1033,
    1049             :     EMT = 1034,
    1050             :     ERET        = 1035,
    1051             :     ERETNC      = 1036,
    1052             :     ERETNC_MMR6 = 1037,
    1053             :     ERET_MM     = 1038,
    1054             :     ERET_MMR6   = 1039,
    1055             :     ERet        = 1040,
    1056             :     EVP = 1041,
    1057             :     EVPE        = 1042,
    1058             :     EVP_MMR6    = 1043,
    1059             :     EXT = 1044,
    1060             :     EXTP        = 1045,
    1061             :     EXTPDP      = 1046,
    1062             :     EXTPDPV     = 1047,
    1063             :     EXTPDPV_MM  = 1048,
    1064             :     EXTPDP_MM   = 1049,
    1065             :     EXTPV       = 1050,
    1066             :     EXTPV_MM    = 1051,
    1067             :     EXTP_MM     = 1052,
    1068             :     EXTRV_RS_W  = 1053,
    1069             :     EXTRV_RS_W_MM       = 1054,
    1070             :     EXTRV_R_W   = 1055,
    1071             :     EXTRV_R_W_MM        = 1056,
    1072             :     EXTRV_S_H   = 1057,
    1073             :     EXTRV_S_H_MM        = 1058,
    1074             :     EXTRV_W     = 1059,
    1075             :     EXTRV_W_MM  = 1060,
    1076             :     EXTR_RS_W   = 1061,
    1077             :     EXTR_RS_W_MM        = 1062,
    1078             :     EXTR_R_W    = 1063,
    1079             :     EXTR_R_W_MM = 1064,
    1080             :     EXTR_S_H    = 1065,
    1081             :     EXTR_S_H_MM = 1066,
    1082             :     EXTR_W      = 1067,
    1083             :     EXTR_W_MM   = 1068,
    1084             :     EXTS        = 1069,
    1085             :     EXTS32      = 1070,
    1086             :     EXT_MM      = 1071,
    1087             :     EXT_MMR6    = 1072,
    1088             :     ExtractElementF64   = 1073,
    1089             :     ExtractElementF64_64        = 1074,
    1090             :     FABS_D      = 1075,
    1091             :     FABS_D32    = 1076,
    1092             :     FABS_D32_MM = 1077,
    1093             :     FABS_D64    = 1078,
    1094             :     FABS_D64_MM = 1079,
    1095             :     FABS_S      = 1080,
    1096             :     FABS_S_MM   = 1081,
    1097             :     FABS_W      = 1082,
    1098             :     FADD_D      = 1083,
    1099             :     FADD_D32    = 1084,
    1100             :     FADD_D32_MM = 1085,
    1101             :     FADD_D64    = 1086,
    1102             :     FADD_D64_MM = 1087,
    1103             :     FADD_S      = 1088,
    1104             :     FADD_S_MM   = 1089,
    1105             :     FADD_S_MMR6 = 1090,
    1106             :     FADD_W      = 1091,
    1107             :     FCAF_D      = 1092,
    1108             :     FCAF_W      = 1093,
    1109             :     FCEQ_D      = 1094,
    1110             :     FCEQ_W      = 1095,
    1111             :     FCLASS_D    = 1096,
    1112             :     FCLASS_W    = 1097,
    1113             :     FCLE_D      = 1098,
    1114             :     FCLE_W      = 1099,
    1115             :     FCLT_D      = 1100,
    1116             :     FCLT_W      = 1101,
    1117             :     FCMP_D32    = 1102,
    1118             :     FCMP_D32_MM = 1103,
    1119             :     FCMP_D64    = 1104,
    1120             :     FCMP_S32    = 1105,
    1121             :     FCMP_S32_MM = 1106,
    1122             :     FCNE_D      = 1107,
    1123             :     FCNE_W      = 1108,
    1124             :     FCOR_D      = 1109,
    1125             :     FCOR_W      = 1110,
    1126             :     FCUEQ_D     = 1111,
    1127             :     FCUEQ_W     = 1112,
    1128             :     FCULE_D     = 1113,
    1129             :     FCULE_W     = 1114,
    1130             :     FCULT_D     = 1115,
    1131             :     FCULT_W     = 1116,
    1132             :     FCUNE_D     = 1117,
    1133             :     FCUNE_W     = 1118,
    1134             :     FCUN_D      = 1119,
    1135             :     FCUN_W      = 1120,
    1136             :     FDIV_D      = 1121,
    1137             :     FDIV_D32    = 1122,
    1138             :     FDIV_D32_MM = 1123,
    1139             :     FDIV_D64    = 1124,
    1140             :     FDIV_D64_MM = 1125,
    1141             :     FDIV_S      = 1126,
    1142             :     FDIV_S_MM   = 1127,
    1143             :     FDIV_S_MMR6 = 1128,
    1144             :     FDIV_W      = 1129,
    1145             :     FEXDO_H     = 1130,
    1146             :     FEXDO_W     = 1131,
    1147             :     FEXP2_D     = 1132,
    1148             :     FEXP2_D_1_PSEUDO    = 1133,
    1149             :     FEXP2_W     = 1134,
    1150             :     FEXP2_W_1_PSEUDO    = 1135,
    1151             :     FEXUPL_D    = 1136,
    1152             :     FEXUPL_W    = 1137,
    1153             :     FEXUPR_D    = 1138,
    1154             :     FEXUPR_W    = 1139,
    1155             :     FFINT_S_D   = 1140,
    1156             :     FFINT_S_W   = 1141,
    1157             :     FFINT_U_D   = 1142,
    1158             :     FFINT_U_W   = 1143,
    1159             :     FFQL_D      = 1144,
    1160             :     FFQL_W      = 1145,
    1161             :     FFQR_D      = 1146,
    1162             :     FFQR_W      = 1147,
    1163             :     FILL_B      = 1148,
    1164             :     FILL_D      = 1149,
    1165             :     FILL_FD_PSEUDO      = 1150,
    1166             :     FILL_FW_PSEUDO      = 1151,
    1167             :     FILL_H      = 1152,
    1168             :     FILL_W      = 1153,
    1169             :     FLOG2_D     = 1154,
    1170             :     FLOG2_W     = 1155,
    1171             :     FLOOR_L_D64 = 1156,
    1172             :     FLOOR_L_D_MMR6      = 1157,
    1173             :     FLOOR_L_S   = 1158,
    1174             :     FLOOR_L_S_MMR6      = 1159,
    1175             :     FLOOR_W_D32 = 1160,
    1176             :     FLOOR_W_D64 = 1161,
    1177             :     FLOOR_W_D_MMR6      = 1162,
    1178             :     FLOOR_W_MM  = 1163,
    1179             :     FLOOR_W_S   = 1164,
    1180             :     FLOOR_W_S_MM        = 1165,
    1181             :     FLOOR_W_S_MMR6      = 1166,
    1182             :     FMADD_D     = 1167,
    1183             :     FMADD_W     = 1168,
    1184             :     FMAX_A_D    = 1169,
    1185             :     FMAX_A_W    = 1170,
    1186             :     FMAX_D      = 1171,
    1187             :     FMAX_W      = 1172,
    1188             :     FMIN_A_D    = 1173,
    1189             :     FMIN_A_W    = 1174,
    1190             :     FMIN_D      = 1175,
    1191             :     FMIN_W      = 1176,
    1192             :     FMOV_D32    = 1177,
    1193             :     FMOV_D32_MM = 1178,
    1194             :     FMOV_D64    = 1179,
    1195             :     FMOV_D64_MM = 1180,
    1196             :     FMOV_S      = 1181,
    1197             :     FMOV_S_MM   = 1182,
    1198             :     FMOV_S_MMR6 = 1183,
    1199             :     FMSUB_D     = 1184,
    1200             :     FMSUB_W     = 1185,
    1201             :     FMUL_D      = 1186,
    1202             :     FMUL_D32    = 1187,
    1203             :     FMUL_D32_MM = 1188,
    1204             :     FMUL_D64    = 1189,
    1205             :     FMUL_D64_MM = 1190,
    1206             :     FMUL_S      = 1191,
    1207             :     FMUL_S_MM   = 1192,
    1208             :     FMUL_S_MMR6 = 1193,
    1209             :     FMUL_W      = 1194,
    1210             :     FNEG_D32    = 1195,
    1211             :     FNEG_D32_MM = 1196,
    1212             :     FNEG_D64    = 1197,
    1213             :     FNEG_D64_MM = 1198,
    1214             :     FNEG_S      = 1199,
    1215             :     FNEG_S_MM   = 1200,
    1216             :     FNEG_S_MMR6 = 1201,
    1217             :     FORK        = 1202,
    1218             :     FRCP_D      = 1203,
    1219             :     FRCP_W      = 1204,
    1220             :     FRINT_D     = 1205,
    1221             :     FRINT_W     = 1206,
    1222             :     FRSQRT_D    = 1207,
    1223             :     FRSQRT_W    = 1208,
    1224             :     FSAF_D      = 1209,
    1225             :     FSAF_W      = 1210,
    1226             :     FSEQ_D      = 1211,
    1227             :     FSEQ_W      = 1212,
    1228             :     FSLE_D      = 1213,
    1229             :     FSLE_W      = 1214,
    1230             :     FSLT_D      = 1215,
    1231             :     FSLT_W      = 1216,
    1232             :     FSNE_D      = 1217,
    1233             :     FSNE_W      = 1218,
    1234             :     FSOR_D      = 1219,
    1235             :     FSOR_W      = 1220,
    1236             :     FSQRT_D     = 1221,
    1237             :     FSQRT_D32   = 1222,
    1238             :     FSQRT_D32_MM        = 1223,
    1239             :     FSQRT_D64   = 1224,
    1240             :     FSQRT_D64_MM        = 1225,
    1241             :     FSQRT_S     = 1226,
    1242             :     FSQRT_S_MM  = 1227,
    1243             :     FSQRT_W     = 1228,
    1244             :     FSUB_D      = 1229,
    1245             :     FSUB_D32    = 1230,
    1246             :     FSUB_D32_MM = 1231,
    1247             :     FSUB_D64    = 1232,
    1248             :     FSUB_D64_MM = 1233,
    1249             :     FSUB_S      = 1234,
    1250             :     FSUB_S_MM   = 1235,
    1251             :     FSUB_S_MMR6 = 1236,
    1252             :     FSUB_W      = 1237,
    1253             :     FSUEQ_D     = 1238,
    1254             :     FSUEQ_W     = 1239,
    1255             :     FSULE_D     = 1240,
    1256             :     FSULE_W     = 1241,
    1257             :     FSULT_D     = 1242,
    1258             :     FSULT_W     = 1243,
    1259             :     FSUNE_D     = 1244,
    1260             :     FSUNE_W     = 1245,
    1261             :     FSUN_D      = 1246,
    1262             :     FSUN_W      = 1247,
    1263             :     FTINT_S_D   = 1248,
    1264             :     FTINT_S_W   = 1249,
    1265             :     FTINT_U_D   = 1250,
    1266             :     FTINT_U_W   = 1251,
    1267             :     FTQ_H       = 1252,
    1268             :     FTQ_W       = 1253,
    1269             :     FTRUNC_S_D  = 1254,
    1270             :     FTRUNC_S_W  = 1255,
    1271             :     FTRUNC_U_D  = 1256,
    1272             :     FTRUNC_U_W  = 1257,
    1273             :     GINVI       = 1258,
    1274             :     GINVI_MMR6  = 1259,
    1275             :     GINVT       = 1260,
    1276             :     GINVT_MMR6  = 1261,
    1277             :     GotPrologue16       = 1262,
    1278             :     HADD_S_D    = 1263,
    1279             :     HADD_S_H    = 1264,
    1280             :     HADD_S_W    = 1265,
    1281             :     HADD_U_D    = 1266,
    1282             :     HADD_U_H    = 1267,
    1283             :     HADD_U_W    = 1268,
    1284             :     HSUB_S_D    = 1269,
    1285             :     HSUB_S_H    = 1270,
    1286             :     HSUB_S_W    = 1271,
    1287             :     HSUB_U_D    = 1272,
    1288             :     HSUB_U_H    = 1273,
    1289             :     HSUB_U_W    = 1274,
    1290             :     HYPCALL     = 1275,
    1291             :     HYPCALL_MM  = 1276,
    1292             :     ILVEV_B     = 1277,
    1293             :     ILVEV_D     = 1278,
    1294             :     ILVEV_H     = 1279,
    1295             :     ILVEV_W     = 1280,
    1296             :     ILVL_B      = 1281,
    1297             :     ILVL_D      = 1282,
    1298             :     ILVL_H      = 1283,
    1299             :     ILVL_W      = 1284,
    1300             :     ILVOD_B     = 1285,
    1301             :     ILVOD_D     = 1286,
    1302             :     ILVOD_H     = 1287,
    1303             :     ILVOD_W     = 1288,
    1304             :     ILVR_B      = 1289,
    1305             :     ILVR_D      = 1290,
    1306             :     ILVR_H      = 1291,
    1307             :     ILVR_W      = 1292,
    1308             :     INS = 1293,
    1309             :     INSERT_B    = 1294,
    1310             :     INSERT_B_VIDX64_PSEUDO      = 1295,
    1311             :     INSERT_B_VIDX_PSEUDO        = 1296,
    1312             :     INSERT_D    = 1297,
    1313             :     INSERT_D_VIDX64_PSEUDO      = 1298,
    1314             :     INSERT_D_VIDX_PSEUDO        = 1299,
    1315             :     INSERT_FD_PSEUDO    = 1300,
    1316             :     INSERT_FD_VIDX64_PSEUDO     = 1301,
    1317             :     INSERT_FD_VIDX_PSEUDO       = 1302,
    1318             :     INSERT_FW_PSEUDO    = 1303,
    1319             :     INSERT_FW_VIDX64_PSEUDO     = 1304,
    1320             :     INSERT_FW_VIDX_PSEUDO       = 1305,
    1321             :     INSERT_H    = 1306,
    1322             :     INSERT_H_VIDX64_PSEUDO      = 1307,
    1323             :     INSERT_H_VIDX_PSEUDO        = 1308,
    1324             :     INSERT_W    = 1309,
    1325             :     INSERT_W_VIDX64_PSEUDO      = 1310,
    1326             :     INSERT_W_VIDX_PSEUDO        = 1311,
    1327             :     INSV        = 1312,
    1328             :     INSVE_B     = 1313,
    1329             :     INSVE_D     = 1314,
    1330             :     INSVE_H     = 1315,
    1331             :     INSVE_W     = 1316,
    1332             :     INSV_MM     = 1317,
    1333             :     INS_MM      = 1318,
    1334             :     INS_MMR6    = 1319,
    1335             :     J   = 1320,
    1336             :     JAL = 1321,
    1337             :     JALR        = 1322,
    1338             :     JALR16_MM   = 1323,
    1339             :     JALR64      = 1324,
    1340             :     JALR64Pseudo        = 1325,
    1341             :     JALRC16_MMR6        = 1326,
    1342             :     JALRC_HB_MMR6       = 1327,
    1343             :     JALRC_MMR6  = 1328,
    1344             :     JALRHB64Pseudo      = 1329,
    1345             :     JALRHBPseudo        = 1330,
    1346             :     JALRPseudo  = 1331,
    1347             :     JALRS16_MM  = 1332,
    1348             :     JALRS_MM    = 1333,
    1349             :     JALR_HB     = 1334,
    1350             :     JALR_HB64   = 1335,
    1351             :     JALR_MM     = 1336,
    1352             :     JALS_MM     = 1337,
    1353             :     JALX        = 1338,
    1354             :     JALX_MM     = 1339,
    1355             :     JAL_MM      = 1340,
    1356             :     JIALC       = 1341,
    1357             :     JIALC64     = 1342,
    1358             :     JIALC_MMR6  = 1343,
    1359             :     JIC = 1344,
    1360             :     JIC64       = 1345,
    1361             :     JIC_MMR6    = 1346,
    1362             :     JR  = 1347,
    1363             :     JR16_MM     = 1348,
    1364             :     JR64        = 1349,
    1365             :     JRADDIUSP   = 1350,
    1366             :     JRC16_MM    = 1351,
    1367             :     JRC16_MMR6  = 1352,
    1368             :     JRCADDIUSP_MMR6     = 1353,
    1369             :     JR_HB       = 1354,
    1370             :     JR_HB64     = 1355,
    1371             :     JR_HB64_R6  = 1356,
    1372             :     JR_HB_R6    = 1357,
    1373             :     JR_MM       = 1358,
    1374             :     J_MM        = 1359,
    1375             :     Jal16       = 1360,
    1376             :     JalB16      = 1361,
    1377             :     JalOneReg   = 1362,
    1378             :     JalTwoReg   = 1363,
    1379             :     JrRa16      = 1364,
    1380             :     JrcRa16     = 1365,
    1381             :     JrcRx16     = 1366,
    1382             :     JumpLinkReg16       = 1367,
    1383             :     LB  = 1368,
    1384             :     LB64        = 1369,
    1385             :     LBE = 1370,
    1386             :     LBE_MM      = 1371,
    1387             :     LBU16_MM    = 1372,
    1388             :     LBUX        = 1373,
    1389             :     LBUX_MM     = 1374,
    1390             :     LBU_MMR6    = 1375,
    1391             :     LB_MM       = 1376,
    1392             :     LB_MMR6     = 1377,
    1393             :     LBu = 1378,
    1394             :     LBu64       = 1379,
    1395             :     LBuE        = 1380,
    1396             :     LBuE_MM     = 1381,
    1397             :     LBu_MM      = 1382,
    1398             :     LD  = 1383,
    1399             :     LDC1        = 1384,
    1400             :     LDC164      = 1385,
    1401             :     LDC1_D64_MMR6       = 1386,
    1402             :     LDC1_MM     = 1387,
    1403             :     LDC2        = 1388,
    1404             :     LDC2_MMR6   = 1389,
    1405             :     LDC2_R6     = 1390,
    1406             :     LDC3        = 1391,
    1407             :     LDI_B       = 1392,
    1408             :     LDI_D       = 1393,
    1409             :     LDI_H       = 1394,
    1410             :     LDI_W       = 1395,
    1411             :     LDL = 1396,
    1412             :     LDMacro     = 1397,
    1413             :     LDPC        = 1398,
    1414             :     LDR = 1399,
    1415             :     LDXC1       = 1400,
    1416             :     LDXC164     = 1401,
    1417             :     LD_B        = 1402,
    1418             :     LD_D        = 1403,
    1419             :     LD_F16      = 1404,
    1420             :     LD_H        = 1405,
    1421             :     LD_W        = 1406,
    1422             :     LEA_ADDiu   = 1407,
    1423             :     LEA_ADDiu64 = 1408,
    1424             :     LEA_ADDiu_MM        = 1409,
    1425             :     LH  = 1410,
    1426             :     LH64        = 1411,
    1427             :     LHE = 1412,
    1428             :     LHE_MM      = 1413,
    1429             :     LHU16_MM    = 1414,
    1430             :     LHX = 1415,
    1431             :     LHX_MM      = 1416,
    1432             :     LH_MM       = 1417,
    1433             :     LHu = 1418,
    1434             :     LHu64       = 1419,
    1435             :     LHuE        = 1420,
    1436             :     LHuE_MM     = 1421,
    1437             :     LHu_MM      = 1422,
    1438             :     LI16_MM     = 1423,
    1439             :     LI16_MMR6   = 1424,
    1440             :     LL  = 1425,
    1441             :     LL64        = 1426,
    1442             :     LL64_R6     = 1427,
    1443             :     LLD = 1428,
    1444             :     LLD_R6      = 1429,
    1445             :     LLE = 1430,
    1446             :     LLE_MM      = 1431,
    1447             :     LL_MM       = 1432,
    1448             :     LL_R6       = 1433,
    1449             :     LOAD_ACC128 = 1434,
    1450             :     LOAD_ACC64  = 1435,
    1451             :     LOAD_ACC64DSP       = 1436,
    1452             :     LOAD_CCOND_DSP      = 1437,
    1453             :     LONG_BRANCH_ADDiu   = 1438,
    1454             :     LONG_BRANCH_DADDiu  = 1439,
    1455             :     LONG_BRANCH_LUi     = 1440,
    1456             :     LSA = 1441,
    1457             :     LSA_MMR6    = 1442,
    1458             :     LSA_R6      = 1443,
    1459             :     LUI_MMR6    = 1444,
    1460             :     LUXC1       = 1445,
    1461             :     LUXC164     = 1446,
    1462             :     LUXC1_MM    = 1447,
    1463             :     LUi = 1448,
    1464             :     LUi64       = 1449,
    1465             :     LUi_MM      = 1450,
    1466             :     LW  = 1451,
    1467             :     LW16_MM     = 1452,
    1468             :     LW64        = 1453,
    1469             :     LWC1        = 1454,
    1470             :     LWC1_MM     = 1455,
    1471             :     LWC2        = 1456,
    1472             :     LWC2_MMR6   = 1457,
    1473             :     LWC2_R6     = 1458,
    1474             :     LWC3        = 1459,
    1475             :     LWDSP       = 1460,
    1476             :     LWDSP_MM    = 1461,
    1477             :     LWE = 1462,
    1478             :     LWE_MM      = 1463,
    1479             :     LWGP_MM     = 1464,
    1480             :     LWL = 1465,
    1481             :     LWL64       = 1466,
    1482             :     LWLE        = 1467,
    1483             :     LWLE_MM     = 1468,
    1484             :     LWL_MM      = 1469,
    1485             :     LWM16_MM    = 1470,
    1486             :     LWM16_MMR6  = 1471,
    1487             :     LWM32_MM    = 1472,
    1488             :     LWM_MM      = 1473,
    1489             :     LWPC        = 1474,
    1490             :     LWPC_MMR6   = 1475,
    1491             :     LWP_MM      = 1476,
    1492             :     LWP_MMR6    = 1477,
    1493             :     LWR = 1478,
    1494             :     LWR64       = 1479,
    1495             :     LWRE        = 1480,
    1496             :     LWRE_MM     = 1481,
    1497             :     LWR_MM      = 1482,
    1498             :     LWSP_MM     = 1483,
    1499             :     LWUPC       = 1484,
    1500             :     LWU_MM      = 1485,
    1501             :     LWX = 1486,
    1502             :     LWXC1       = 1487,
    1503             :     LWXC1_MM    = 1488,
    1504             :     LWXS_MM     = 1489,
    1505             :     LWX_MM      = 1490,
    1506             :     LW_MM       = 1491,
    1507             :     LW_MMR6     = 1492,
    1508             :     LWu = 1493,
    1509             :     LbRxRyOffMemX16     = 1494,
    1510             :     LbuRxRyOffMemX16    = 1495,
    1511             :     LhRxRyOffMemX16     = 1496,
    1512             :     LhuRxRyOffMemX16    = 1497,
    1513             :     LiRxImm16   = 1498,
    1514             :     LiRxImmAlignX16     = 1499,
    1515             :     LiRxImmX16  = 1500,
    1516             :     LoadAddrImm32       = 1501,
    1517             :     LoadAddrImm64       = 1502,
    1518             :     LoadAddrReg32       = 1503,
    1519             :     LoadAddrReg64       = 1504,
    1520             :     LoadImm32   = 1505,
    1521             :     LoadImm64   = 1506,
    1522             :     LoadImmDoubleFGR    = 1507,
    1523             :     LoadImmDoubleFGR_32 = 1508,
    1524             :     LoadImmDoubleGPR    = 1509,
    1525             :     LoadImmSingleFGR    = 1510,
    1526             :     LoadImmSingleGPR    = 1511,
    1527             :     LwConstant32        = 1512,
    1528             :     LwRxPcTcp16 = 1513,
    1529             :     LwRxPcTcpX16        = 1514,
    1530             :     LwRxRyOffMemX16     = 1515,
    1531             :     LwRxSpImmX16        = 1516,
    1532             :     MADD        = 1517,
    1533             :     MADDF_D     = 1518,
    1534             :     MADDF_D_MMR6        = 1519,
    1535             :     MADDF_S     = 1520,
    1536             :     MADDF_S_MMR6        = 1521,
    1537             :     MADDR_Q_H   = 1522,
    1538             :     MADDR_Q_W   = 1523,
    1539             :     MADDU       = 1524,
    1540             :     MADDU_DSP   = 1525,
    1541             :     MADDU_DSP_MM        = 1526,
    1542             :     MADDU_MM    = 1527,
    1543             :     MADDV_B     = 1528,
    1544             :     MADDV_D     = 1529,
    1545             :     MADDV_H     = 1530,
    1546             :     MADDV_W     = 1531,
    1547             :     MADD_D32    = 1532,
    1548             :     MADD_D32_MM = 1533,
    1549             :     MADD_D64    = 1534,
    1550             :     MADD_DSP    = 1535,
    1551             :     MADD_DSP_MM = 1536,
    1552             :     MADD_MM     = 1537,
    1553             :     MADD_Q_H    = 1538,
    1554             :     MADD_Q_W    = 1539,
    1555             :     MADD_S      = 1540,
    1556             :     MADD_S_MM   = 1541,
    1557             :     MAQ_SA_W_PHL        = 1542,
    1558             :     MAQ_SA_W_PHL_MM     = 1543,
    1559             :     MAQ_SA_W_PHR        = 1544,
    1560             :     MAQ_SA_W_PHR_MM     = 1545,
    1561             :     MAQ_S_W_PHL = 1546,
    1562             :     MAQ_S_W_PHL_MM      = 1547,
    1563             :     MAQ_S_W_PHR = 1548,
    1564             :     MAQ_S_W_PHR_MM      = 1549,
    1565             :     MAXA_D      = 1550,
    1566             :     MAXA_D_MMR6 = 1551,
    1567             :     MAXA_S      = 1552,
    1568             :     MAXA_S_MMR6 = 1553,
    1569             :     MAXI_S_B    = 1554,
    1570             :     MAXI_S_D    = 1555,
    1571             :     MAXI_S_H    = 1556,
    1572             :     MAXI_S_W    = 1557,
    1573             :     MAXI_U_B    = 1558,
    1574             :     MAXI_U_D    = 1559,
    1575             :     MAXI_U_H    = 1560,
    1576             :     MAXI_U_W    = 1561,
    1577             :     MAX_A_B     = 1562,
    1578             :     MAX_A_D     = 1563,
    1579             :     MAX_A_H     = 1564,
    1580             :     MAX_A_W     = 1565,
    1581             :     MAX_D       = 1566,
    1582             :     MAX_D_MMR6  = 1567,
    1583             :     MAX_S       = 1568,
    1584             :     MAX_S_B     = 1569,
    1585             :     MAX_S_D     = 1570,
    1586             :     MAX_S_H     = 1571,
    1587             :     MAX_S_MMR6  = 1572,
    1588             :     MAX_S_W     = 1573,
    1589             :     MAX_U_B     = 1574,
    1590             :     MAX_U_D     = 1575,
    1591             :     MAX_U_H     = 1576,
    1592             :     MAX_U_W     = 1577,
    1593             :     MFC0        = 1578,
    1594             :     MFC0_MMR6   = 1579,
    1595             :     MFC1        = 1580,
    1596             :     MFC1_D64    = 1581,
    1597             :     MFC1_MM     = 1582,
    1598             :     MFC1_MMR6   = 1583,
    1599             :     MFC2        = 1584,
    1600             :     MFC2_MMR6   = 1585,
    1601             :     MFGC0       = 1586,
    1602             :     MFGC0_MM    = 1587,
    1603             :     MFHC0_MMR6  = 1588,
    1604             :     MFHC1_D32   = 1589,
    1605             :     MFHC1_D32_MM        = 1590,
    1606             :     MFHC1_D64   = 1591,
    1607             :     MFHC1_D64_MM        = 1592,
    1608             :     MFHC2_MMR6  = 1593,
    1609             :     MFHGC0      = 1594,
    1610             :     MFHGC0_MM   = 1595,
    1611             :     MFHI        = 1596,
    1612             :     MFHI16_MM   = 1597,
    1613             :     MFHI64      = 1598,
    1614             :     MFHI_DSP    = 1599,
    1615             :     MFHI_DSP_MM = 1600,
    1616             :     MFHI_MM     = 1601,
    1617             :     MFLO        = 1602,
    1618             :     MFLO16_MM   = 1603,
    1619             :     MFLO64      = 1604,
    1620             :     MFLO_DSP    = 1605,
    1621             :     MFLO_DSP_MM = 1606,
    1622             :     MFLO_MM     = 1607,
    1623             :     MFTACX      = 1608,
    1624             :     MFTC0       = 1609,
    1625             :     MFTC1       = 1610,
    1626             :     MFTDSP      = 1611,
    1627             :     MFTGPR      = 1612,
    1628             :     MFTHC1      = 1613,
    1629             :     MFTHI       = 1614,
    1630             :     MFTLO       = 1615,
    1631             :     MFTR        = 1616,
    1632             :     MINA_D      = 1617,
    1633             :     MINA_D_MMR6 = 1618,
    1634             :     MINA_S      = 1619,
    1635             :     MINA_S_MMR6 = 1620,
    1636             :     MINI_S_B    = 1621,
    1637             :     MINI_S_D    = 1622,
    1638             :     MINI_S_H    = 1623,
    1639             :     MINI_S_W    = 1624,
    1640             :     MINI_U_B    = 1625,
    1641             :     MINI_U_D    = 1626,
    1642             :     MINI_U_H    = 1627,
    1643             :     MINI_U_W    = 1628,
    1644             :     MIN_A_B     = 1629,
    1645             :     MIN_A_D     = 1630,
    1646             :     MIN_A_H     = 1631,
    1647             :     MIN_A_W     = 1632,
    1648             :     MIN_D       = 1633,
    1649             :     MIN_D_MMR6  = 1634,
    1650             :     MIN_S       = 1635,
    1651             :     MIN_S_B     = 1636,
    1652             :     MIN_S_D     = 1637,
    1653             :     MIN_S_H     = 1638,
    1654             :     MIN_S_MMR6  = 1639,
    1655             :     MIN_S_W     = 1640,
    1656             :     MIN_U_B     = 1641,
    1657             :     MIN_U_D     = 1642,
    1658             :     MIN_U_H     = 1643,
    1659             :     MIN_U_W     = 1644,
    1660             :     MIPSeh_return32     = 1645,
    1661             :     MIPSeh_return64     = 1646,
    1662             :     MOD = 1647,
    1663             :     MODSUB      = 1648,
    1664             :     MODSUB_MM   = 1649,
    1665             :     MODU        = 1650,
    1666             :     MODU_MMR6   = 1651,
    1667             :     MOD_MMR6    = 1652,
    1668             :     MOD_S_B     = 1653,
    1669             :     MOD_S_D     = 1654,
    1670             :     MOD_S_H     = 1655,
    1671             :     MOD_S_W     = 1656,
    1672             :     MOD_U_B     = 1657,
    1673             :     MOD_U_D     = 1658,
    1674             :     MOD_U_H     = 1659,
    1675             :     MOD_U_W     = 1660,
    1676             :     MOVE16_MM   = 1661,
    1677             :     MOVE16_MMR6 = 1662,
    1678             :     MOVEP_MM    = 1663,
    1679             :     MOVEP_MMR6  = 1664,
    1680             :     MOVE_V      = 1665,
    1681             :     MOVF_D32    = 1666,
    1682             :     MOVF_D32_MM = 1667,
    1683             :     MOVF_D64    = 1668,
    1684             :     MOVF_I      = 1669,
    1685             :     MOVF_I64    = 1670,
    1686             :     MOVF_I_MM   = 1671,
    1687             :     MOVF_S      = 1672,
    1688             :     MOVF_S_MM   = 1673,
    1689             :     MOVN_I64_D64        = 1674,
    1690             :     MOVN_I64_I  = 1675,
    1691             :     MOVN_I64_I64        = 1676,
    1692             :     MOVN_I64_S  = 1677,
    1693             :     MOVN_I_D32  = 1678,
    1694             :     MOVN_I_D32_MM       = 1679,
    1695             :     MOVN_I_D64  = 1680,
    1696             :     MOVN_I_I    = 1681,
    1697             :     MOVN_I_I64  = 1682,
    1698             :     MOVN_I_MM   = 1683,
    1699             :     MOVN_I_S    = 1684,
    1700             :     MOVN_I_S_MM = 1685,
    1701             :     MOVT_D32    = 1686,
    1702             :     MOVT_D32_MM = 1687,
    1703             :     MOVT_D64    = 1688,
    1704             :     MOVT_I      = 1689,
    1705             :     MOVT_I64    = 1690,
    1706             :     MOVT_I_MM   = 1691,
    1707             :     MOVT_S      = 1692,
    1708             :     MOVT_S_MM   = 1693,
    1709             :     MOVZ_I64_D64        = 1694,
    1710             :     MOVZ_I64_I  = 1695,
    1711             :     MOVZ_I64_I64        = 1696,
    1712             :     MOVZ_I64_S  = 1697,
    1713             :     MOVZ_I_D32  = 1698,
    1714             :     MOVZ_I_D32_MM       = 1699,
    1715             :     MOVZ_I_D64  = 1700,
    1716             :     MOVZ_I_I    = 1701,
    1717             :     MOVZ_I_I64  = 1702,
    1718             :     MOVZ_I_MM   = 1703,
    1719             :     MOVZ_I_S    = 1704,
    1720             :     MOVZ_I_S_MM = 1705,
    1721             :     MSA_FP_EXTEND_D_PSEUDO      = 1706,
    1722             :     MSA_FP_EXTEND_W_PSEUDO      = 1707,
    1723             :     MSA_FP_ROUND_D_PSEUDO       = 1708,
    1724             :     MSA_FP_ROUND_W_PSEUDO       = 1709,
    1725             :     MSUB        = 1710,
    1726             :     MSUBF_D     = 1711,
    1727             :     MSUBF_D_MMR6        = 1712,
    1728             :     MSUBF_S     = 1713,
    1729             :     MSUBF_S_MMR6        = 1714,
    1730             :     MSUBR_Q_H   = 1715,
    1731             :     MSUBR_Q_W   = 1716,
    1732             :     MSUBU       = 1717,
    1733             :     MSUBU_DSP   = 1718,
    1734             :     MSUBU_DSP_MM        = 1719,
    1735             :     MSUBU_MM    = 1720,
    1736             :     MSUBV_B     = 1721,
    1737             :     MSUBV_D     = 1722,
    1738             :     MSUBV_H     = 1723,
    1739             :     MSUBV_W     = 1724,
    1740             :     MSUB_D32    = 1725,
    1741             :     MSUB_D32_MM = 1726,
    1742             :     MSUB_D64    = 1727,
    1743             :     MSUB_DSP    = 1728,
    1744             :     MSUB_DSP_MM = 1729,
    1745             :     MSUB_MM     = 1730,
    1746             :     MSUB_Q_H    = 1731,
    1747             :     MSUB_Q_W    = 1732,
    1748             :     MSUB_S      = 1733,
    1749             :     MSUB_S_MM   = 1734,
    1750             :     MTC0        = 1735,
    1751             :     MTC0_MMR6   = 1736,
    1752             :     MTC1        = 1737,
    1753             :     MTC1_D64    = 1738,
    1754             :     MTC1_MM     = 1739,
    1755             :     MTC1_MMR6   = 1740,
    1756             :     MTC2        = 1741,
    1757             :     MTC2_MMR6   = 1742,
    1758             :     MTGC0       = 1743,
    1759             :     MTGC0_MM    = 1744,
    1760             :     MTHC0_MMR6  = 1745,
    1761             :     MTHC1_D32   = 1746,
    1762             :     MTHC1_D32_MM        = 1747,
    1763             :     MTHC1_D64   = 1748,
    1764             :     MTHC1_D64_MM        = 1749,
    1765             :     MTHC2_MMR6  = 1750,
    1766             :     MTHGC0      = 1751,
    1767             :     MTHGC0_MM   = 1752,
    1768             :     MTHI        = 1753,
    1769             :     MTHI64      = 1754,
    1770             :     MTHI_DSP    = 1755,
    1771             :     MTHI_DSP_MM = 1756,
    1772             :     MTHI_MM     = 1757,
    1773             :     MTHLIP      = 1758,
    1774             :     MTHLIP_MM   = 1759,
    1775             :     MTLO        = 1760,
    1776             :     MTLO64      = 1761,
    1777             :     MTLO_DSP    = 1762,
    1778             :     MTLO_DSP_MM = 1763,
    1779             :     MTLO_MM     = 1764,
    1780             :     MTM0        = 1765,
    1781             :     MTM1        = 1766,
    1782             :     MTM2        = 1767,
    1783             :     MTP0        = 1768,
    1784             :     MTP1        = 1769,
    1785             :     MTP2        = 1770,
    1786             :     MTTACX      = 1771,
    1787             :     MTTC0       = 1772,
    1788             :     MTTC1       = 1773,
    1789             :     MTTDSP      = 1774,
    1790             :     MTTGPR      = 1775,
    1791             :     MTTHC1      = 1776,
    1792             :     MTTHI       = 1777,
    1793             :     MTTLO       = 1778,
    1794             :     MTTR        = 1779,
    1795             :     MUH = 1780,
    1796             :     MUHU        = 1781,
    1797             :     MUHU_MMR6   = 1782,
    1798             :     MUH_MMR6    = 1783,
    1799             :     MUL = 1784,
    1800             :     MULEQ_S_W_PHL       = 1785,
    1801             :     MULEQ_S_W_PHL_MM    = 1786,
    1802             :     MULEQ_S_W_PHR       = 1787,
    1803             :     MULEQ_S_W_PHR_MM    = 1788,
    1804             :     MULEU_S_PH_QBL      = 1789,
    1805             :     MULEU_S_PH_QBL_MM   = 1790,
    1806             :     MULEU_S_PH_QBR      = 1791,
    1807             :     MULEU_S_PH_QBR_MM   = 1792,
    1808             :     MULImmMacro = 1793,
    1809             :     MULOMacro   = 1794,
    1810             :     MULOUMacro  = 1795,
    1811             :     MULQ_RS_PH  = 1796,
    1812             :     MULQ_RS_PH_MM       = 1797,
    1813             :     MULQ_RS_W   = 1798,
    1814             :     MULQ_RS_W_MMR2      = 1799,
    1815             :     MULQ_S_PH   = 1800,
    1816             :     MULQ_S_PH_MMR2      = 1801,
    1817             :     MULQ_S_W    = 1802,
    1818             :     MULQ_S_W_MMR2       = 1803,
    1819             :     MULR_Q_H    = 1804,
    1820             :     MULR_Q_W    = 1805,
    1821             :     MULSAQ_S_W_PH       = 1806,
    1822             :     MULSAQ_S_W_PH_MM    = 1807,
    1823             :     MULSA_W_PH  = 1808,
    1824             :     MULSA_W_PH_MMR2     = 1809,
    1825             :     MULT        = 1810,
    1826             :     MULTU_DSP   = 1811,
    1827             :     MULTU_DSP_MM        = 1812,
    1828             :     MULT_DSP    = 1813,
    1829             :     MULT_DSP_MM = 1814,
    1830             :     MULT_MM     = 1815,
    1831             :     MULTu       = 1816,
    1832             :     MULTu_MM    = 1817,
    1833             :     MULU        = 1818,
    1834             :     MULU_MMR6   = 1819,
    1835             :     MULV_B      = 1820,
    1836             :     MULV_D      = 1821,
    1837             :     MULV_H      = 1822,
    1838             :     MULV_W      = 1823,
    1839             :     MUL_MM      = 1824,
    1840             :     MUL_MMR6    = 1825,
    1841             :     MUL_PH      = 1826,
    1842             :     MUL_PH_MMR2 = 1827,
    1843             :     MUL_Q_H     = 1828,
    1844             :     MUL_Q_W     = 1829,
    1845             :     MUL_R6      = 1830,
    1846             :     MUL_S_PH    = 1831,
    1847             :     MUL_S_PH_MMR2       = 1832,
    1848             :     Mfhi16      = 1833,
    1849             :     Mflo16      = 1834,
    1850             :     Move32R16   = 1835,
    1851             :     MoveR3216   = 1836,
    1852             :     MultRxRy16  = 1837,
    1853             :     MultRxRyRz16        = 1838,
    1854             :     MultuRxRy16 = 1839,
    1855             :     MultuRxRyRz16       = 1840,
    1856             :     NLOC_B      = 1841,
    1857             :     NLOC_D      = 1842,
    1858             :     NLOC_H      = 1843,
    1859             :     NLOC_W      = 1844,
    1860             :     NLZC_B      = 1845,
    1861             :     NLZC_D      = 1846,
    1862             :     NLZC_H      = 1847,
    1863             :     NLZC_W      = 1848,
    1864             :     NMADD_D32   = 1849,
    1865             :     NMADD_D32_MM        = 1850,
    1866             :     NMADD_D64   = 1851,
    1867             :     NMADD_S     = 1852,
    1868             :     NMADD_S_MM  = 1853,
    1869             :     NMSUB_D32   = 1854,
    1870             :     NMSUB_D32_MM        = 1855,
    1871             :     NMSUB_D64   = 1856,
    1872             :     NMSUB_S     = 1857,
    1873             :     NMSUB_S_MM  = 1858,
    1874             :     NOP = 1859,
    1875             :     NOR = 1860,
    1876             :     NOR64       = 1861,
    1877             :     NORI_B      = 1862,
    1878             :     NORImm      = 1863,
    1879             :     NORImm64    = 1864,
    1880             :     NOR_MM      = 1865,
    1881             :     NOR_MMR6    = 1866,
    1882             :     NOR_V       = 1867,
    1883             :     NOR_V_D_PSEUDO      = 1868,
    1884             :     NOR_V_H_PSEUDO      = 1869,
    1885             :     NOR_V_W_PSEUDO      = 1870,
    1886             :     NOT16_MM    = 1871,
    1887             :     NOT16_MMR6  = 1872,
    1888             :     NegRxRy16   = 1873,
    1889             :     NotRxRy16   = 1874,
    1890             :     OR  = 1875,
    1891             :     OR16_MM     = 1876,
    1892             :     OR16_MMR6   = 1877,
    1893             :     OR64        = 1878,
    1894             :     ORI_B       = 1879,
    1895             :     ORI_MMR6    = 1880,
    1896             :     OR_MM       = 1881,
    1897             :     OR_MMR6     = 1882,
    1898             :     OR_V        = 1883,
    1899             :     OR_V_D_PSEUDO       = 1884,
    1900             :     OR_V_H_PSEUDO       = 1885,
    1901             :     OR_V_W_PSEUDO       = 1886,
    1902             :     ORi = 1887,
    1903             :     ORi64       = 1888,
    1904             :     ORi_MM      = 1889,
    1905             :     OrRxRxRy16  = 1890,
    1906             :     PACKRL_PH   = 1891,
    1907             :     PACKRL_PH_MM        = 1892,
    1908             :     PAUSE       = 1893,
    1909             :     PAUSE_MM    = 1894,
    1910             :     PAUSE_MMR6  = 1895,
    1911             :     PCKEV_B     = 1896,
    1912             :     PCKEV_D     = 1897,
    1913             :     PCKEV_H     = 1898,
    1914             :     PCKEV_W     = 1899,
    1915             :     PCKOD_B     = 1900,
    1916             :     PCKOD_D     = 1901,
    1917             :     PCKOD_H     = 1902,
    1918             :     PCKOD_W     = 1903,
    1919             :     PCNT_B      = 1904,
    1920             :     PCNT_D      = 1905,
    1921             :     PCNT_H      = 1906,
    1922             :     PCNT_W      = 1907,
    1923             :     PICK_PH     = 1908,
    1924             :     PICK_PH_MM  = 1909,
    1925             :     PICK_QB     = 1910,
    1926             :     PICK_QB_MM  = 1911,
    1927             :     POP = 1912,
    1928             :     PRECEQU_PH_QBL      = 1913,
    1929             :     PRECEQU_PH_QBLA     = 1914,
    1930             :     PRECEQU_PH_QBLA_MM  = 1915,
    1931             :     PRECEQU_PH_QBL_MM   = 1916,
    1932             :     PRECEQU_PH_QBR      = 1917,
    1933             :     PRECEQU_PH_QBRA     = 1918,
    1934             :     PRECEQU_PH_QBRA_MM  = 1919,
    1935             :     PRECEQU_PH_QBR_MM   = 1920,
    1936             :     PRECEQ_W_PHL        = 1921,
    1937             :     PRECEQ_W_PHL_MM     = 1922,
    1938             :     PRECEQ_W_PHR        = 1923,
    1939             :     PRECEQ_W_PHR_MM     = 1924,
    1940             :     PRECEU_PH_QBL       = 1925,
    1941             :     PRECEU_PH_QBLA      = 1926,
    1942             :     PRECEU_PH_QBLA_MM   = 1927,
    1943             :     PRECEU_PH_QBL_MM    = 1928,
    1944             :     PRECEU_PH_QBR       = 1929,
    1945             :     PRECEU_PH_QBRA      = 1930,
    1946             :     PRECEU_PH_QBRA_MM   = 1931,
    1947             :     PRECEU_PH_QBR_MM    = 1932,
    1948             :     PRECRQU_S_QB_PH     = 1933,
    1949             :     PRECRQU_S_QB_PH_MM  = 1934,
    1950             :     PRECRQ_PH_W = 1935,
    1951             :     PRECRQ_PH_W_MM      = 1936,
    1952             :     PRECRQ_QB_PH        = 1937,
    1953             :     PRECRQ_QB_PH_MM     = 1938,
    1954             :     PRECRQ_RS_PH_W      = 1939,
    1955             :     PRECRQ_RS_PH_W_MM   = 1940,
    1956             :     PRECR_QB_PH = 1941,
    1957             :     PRECR_QB_PH_MMR2    = 1942,
    1958             :     PRECR_SRA_PH_W      = 1943,
    1959             :     PRECR_SRA_PH_W_MMR2 = 1944,
    1960             :     PRECR_SRA_R_PH_W    = 1945,
    1961             :     PRECR_SRA_R_PH_W_MMR2       = 1946,
    1962             :     PREF        = 1947,
    1963             :     PREFE       = 1948,
    1964             :     PREFE_MM    = 1949,
    1965             :     PREFX_MM    = 1950,
    1966             :     PREF_MM     = 1951,
    1967             :     PREF_MMR6   = 1952,
    1968             :     PREF_R6     = 1953,
    1969             :     PREPEND     = 1954,
    1970             :     PREPEND_MMR2        = 1955,
    1971             :     PseudoCMPU_EQ_QB    = 1956,
    1972             :     PseudoCMPU_LE_QB    = 1957,
    1973             :     PseudoCMPU_LT_QB    = 1958,
    1974             :     PseudoCMP_EQ_PH     = 1959,
    1975             :     PseudoCMP_LE_PH     = 1960,
    1976             :     PseudoCMP_LT_PH     = 1961,
    1977             :     PseudoCVT_D32_W     = 1962,
    1978             :     PseudoCVT_D64_L     = 1963,
    1979             :     PseudoCVT_D64_W     = 1964,
    1980             :     PseudoCVT_S_L       = 1965,
    1981             :     PseudoCVT_S_W       = 1966,
    1982             :     PseudoDMULT = 1967,
    1983             :     PseudoDMULTu        = 1968,
    1984             :     PseudoDSDIV = 1969,
    1985             :     PseudoDUDIV = 1970,
    1986             :     PseudoIndirectBranch        = 1971,
    1987             :     PseudoIndirectBranch64      = 1972,
    1988             :     PseudoIndirectBranch64R6    = 1973,
    1989             :     PseudoIndirectBranchR6      = 1974,
    1990             :     PseudoIndirectBranch_MM     = 1975,
    1991             :     PseudoIndirectBranch_MMR6   = 1976,
    1992             :     PseudoIndirectHazardBranch  = 1977,
    1993             :     PseudoIndirectHazardBranch64        = 1978,
    1994             :     PseudoIndrectHazardBranch64R6       = 1979,
    1995             :     PseudoIndrectHazardBranchR6 = 1980,
    1996             :     PseudoMADD  = 1981,
    1997             :     PseudoMADDU = 1982,
    1998             :     PseudoMFHI  = 1983,
    1999             :     PseudoMFHI64        = 1984,
    2000             :     PseudoMFLO  = 1985,
    2001             :     PseudoMFLO64        = 1986,
    2002             :     PseudoMSUB  = 1987,
    2003             :     PseudoMSUBU = 1988,
    2004             :     PseudoMTLOHI        = 1989,
    2005             :     PseudoMTLOHI64      = 1990,
    2006             :     PseudoMTLOHI_DSP    = 1991,
    2007             :     PseudoMULT  = 1992,
    2008             :     PseudoMULTu = 1993,
    2009             :     PseudoPICK_PH       = 1994,
    2010             :     PseudoPICK_QB       = 1995,
    2011             :     PseudoReturn        = 1996,
    2012             :     PseudoReturn64      = 1997,
    2013             :     PseudoSDIV  = 1998,
    2014             :     PseudoSELECTFP_F_D32        = 1999,
    2015             :     PseudoSELECTFP_F_D64        = 2000,
    2016             :     PseudoSELECTFP_F_I  = 2001,
    2017             :     PseudoSELECTFP_F_I64        = 2002,
    2018             :     PseudoSELECTFP_F_S  = 2003,
    2019             :     PseudoSELECTFP_T_D32        = 2004,
    2020             :     PseudoSELECTFP_T_D64        = 2005,
    2021             :     PseudoSELECTFP_T_I  = 2006,
    2022             :     PseudoSELECTFP_T_I64        = 2007,
    2023             :     PseudoSELECTFP_T_S  = 2008,
    2024             :     PseudoSELECT_D32    = 2009,
    2025             :     PseudoSELECT_D64    = 2010,
    2026             :     PseudoSELECT_I      = 2011,
    2027             :     PseudoSELECT_I64    = 2012,
    2028             :     PseudoSELECT_S      = 2013,
    2029             :     PseudoTRUNC_W_D     = 2014,
    2030             :     PseudoTRUNC_W_D32   = 2015,
    2031             :     PseudoTRUNC_W_S     = 2016,
    2032             :     PseudoUDIV  = 2017,
    2033             :     RADDU_W_QB  = 2018,
    2034             :     RADDU_W_QB_MM       = 2019,
    2035             :     RDDSP       = 2020,
    2036             :     RDDSP_MM    = 2021,
    2037             :     RDHWR       = 2022,
    2038             :     RDHWR64     = 2023,
    2039             :     RDHWR_MM    = 2024,
    2040             :     RDHWR_MMR6  = 2025,
    2041             :     RDPGPR_MMR6 = 2026,
    2042             :     RECIP_D32   = 2027,
    2043             :     RECIP_D32_MM        = 2028,
    2044             :     RECIP_D64   = 2029,
    2045             :     RECIP_D64_MM        = 2030,
    2046             :     RECIP_S     = 2031,
    2047             :     RECIP_S_MM  = 2032,
    2048             :     REPLV_PH    = 2033,
    2049             :     REPLV_PH_MM = 2034,
    2050             :     REPLV_QB    = 2035,
    2051             :     REPLV_QB_MM = 2036,
    2052             :     REPL_PH     = 2037,
    2053             :     REPL_PH_MM  = 2038,
    2054             :     REPL_QB     = 2039,
    2055             :     REPL_QB_MM  = 2040,
    2056             :     RINT_D      = 2041,
    2057             :     RINT_D_MMR6 = 2042,
    2058             :     RINT_S      = 2043,
    2059             :     RINT_S_MMR6 = 2044,
    2060             :     ROL = 2045,
    2061             :     ROLImm      = 2046,
    2062             :     ROR = 2047,
    2063             :     RORImm      = 2048,
    2064             :     ROTR        = 2049,
    2065             :     ROTRV       = 2050,
    2066             :     ROTRV_MM    = 2051,
    2067             :     ROTR_MM     = 2052,
    2068             :     ROUND_L_D64 = 2053,
    2069             :     ROUND_L_D_MMR6      = 2054,
    2070             :     ROUND_L_S   = 2055,
    2071             :     ROUND_L_S_MMR6      = 2056,
    2072             :     ROUND_W_D32 = 2057,
    2073             :     ROUND_W_D64 = 2058,
    2074             :     ROUND_W_D_MMR6      = 2059,
    2075             :     ROUND_W_MM  = 2060,
    2076             :     ROUND_W_S   = 2061,
    2077             :     ROUND_W_S_MM        = 2062,
    2078             :     ROUND_W_S_MMR6      = 2063,
    2079             :     RSQRT_D32   = 2064,
    2080             :     RSQRT_D32_MM        = 2065,
    2081             :     RSQRT_D64   = 2066,
    2082             :     RSQRT_D64_MM        = 2067,
    2083             :     RSQRT_S     = 2068,
    2084             :     RSQRT_S_MM  = 2069,
    2085             :     Restore16   = 2070,
    2086             :     RestoreX16  = 2071,
    2087             :     RetRA       = 2072,
    2088             :     RetRA16     = 2073,
    2089             :     SAT_S_B     = 2074,
    2090             :     SAT_S_D     = 2075,
    2091             :     SAT_S_H     = 2076,
    2092             :     SAT_S_W     = 2077,
    2093             :     SAT_U_B     = 2078,
    2094             :     SAT_U_D     = 2079,
    2095             :     SAT_U_H     = 2080,
    2096             :     SAT_U_W     = 2081,
    2097             :     SB  = 2082,
    2098             :     SB16_MM     = 2083,
    2099             :     SB16_MMR6   = 2084,
    2100             :     SB64        = 2085,
    2101             :     SBE = 2086,
    2102             :     SBE_MM      = 2087,
    2103             :     SB_MM       = 2088,
    2104             :     SB_MMR6     = 2089,
    2105             :     SC  = 2090,
    2106             :     SC64        = 2091,
    2107             :     SC64_R6     = 2092,
    2108             :     SCD = 2093,
    2109             :     SCD_R6      = 2094,
    2110             :     SCE = 2095,
    2111             :     SCE_MM      = 2096,
    2112             :     SC_MM       = 2097,
    2113             :     SC_R6       = 2098,
    2114             :     SD  = 2099,
    2115             :     SDBBP       = 2100,
    2116             :     SDBBP16_MM  = 2101,
    2117             :     SDBBP16_MMR6        = 2102,
    2118             :     SDBBP_MM    = 2103,
    2119             :     SDBBP_MMR6  = 2104,
    2120             :     SDBBP_R6    = 2105,
    2121             :     SDC1        = 2106,
    2122             :     SDC164      = 2107,
    2123             :     SDC1_D64_MMR6       = 2108,
    2124             :     SDC1_MM     = 2109,
    2125             :     SDC2        = 2110,
    2126             :     SDC2_MMR6   = 2111,
    2127             :     SDC2_R6     = 2112,
    2128             :     SDC3        = 2113,
    2129             :     SDIV        = 2114,
    2130             :     SDIV_MM     = 2115,
    2131             :     SDIV_MM_Pseudo      = 2116,
    2132             :     SDL = 2117,
    2133             :     SDMacro     = 2118,
    2134             :     SDR = 2119,
    2135             :     SDXC1       = 2120,
    2136             :     SDXC164     = 2121,
    2137             :     SDivIMacro  = 2122,
    2138             :     SDivMacro   = 2123,
    2139             :     SEB = 2124,
    2140             :     SEB64       = 2125,
    2141             :     SEB_MM      = 2126,
    2142             :     SEH = 2127,
    2143             :     SEH64       = 2128,
    2144             :     SEH_MM      = 2129,
    2145             :     SELEQZ      = 2130,
    2146             :     SELEQZ64    = 2131,
    2147             :     SELEQZ_D    = 2132,
    2148             :     SELEQZ_D_MMR6       = 2133,
    2149             :     SELEQZ_MMR6 = 2134,
    2150             :     SELEQZ_S    = 2135,
    2151             :     SELEQZ_S_MMR6       = 2136,
    2152             :     SELNEZ      = 2137,
    2153             :     SELNEZ64    = 2138,
    2154             :     SELNEZ_D    = 2139,
    2155             :     SELNEZ_D_MMR6       = 2140,
    2156             :     SELNEZ_MMR6 = 2141,
    2157             :     SELNEZ_S    = 2142,
    2158             :     SELNEZ_S_MMR6       = 2143,
    2159             :     SEL_D       = 2144,
    2160             :     SEL_D_MMR6  = 2145,
    2161             :     SEL_S       = 2146,
    2162             :     SEL_S_MMR6  = 2147,
    2163             :     SEQ = 2148,
    2164             :     SEQIMacro   = 2149,
    2165             :     SEQMacro    = 2150,
    2166             :     SEQi        = 2151,
    2167             :     SH  = 2152,
    2168             :     SH16_MM     = 2153,
    2169             :     SH16_MMR6   = 2154,
    2170             :     SH64        = 2155,
    2171             :     SHE = 2156,
    2172             :     SHE_MM      = 2157,
    2173             :     SHF_B       = 2158,
    2174             :     SHF_H       = 2159,
    2175             :     SHF_W       = 2160,
    2176             :     SHILO       = 2161,
    2177             :     SHILOV      = 2162,
    2178             :     SHILOV_MM   = 2163,
    2179             :     SHILO_MM    = 2164,
    2180             :     SHLLV_PH    = 2165,
    2181             :     SHLLV_PH_MM = 2166,
    2182             :     SHLLV_QB    = 2167,
    2183             :     SHLLV_QB_MM = 2168,
    2184             :     SHLLV_S_PH  = 2169,
    2185             :     SHLLV_S_PH_MM       = 2170,
    2186             :     SHLLV_S_W   = 2171,
    2187             :     SHLLV_S_W_MM        = 2172,
    2188             :     SHLL_PH     = 2173,
    2189             :     SHLL_PH_MM  = 2174,
    2190             :     SHLL_QB     = 2175,
    2191             :     SHLL_QB_MM  = 2176,
    2192             :     SHLL_S_PH   = 2177,
    2193             :     SHLL_S_PH_MM        = 2178,
    2194             :     SHLL_S_W    = 2179,
    2195             :     SHLL_S_W_MM = 2180,
    2196             :     SHRAV_PH    = 2181,
    2197             :     SHRAV_PH_MM = 2182,
    2198             :     SHRAV_QB    = 2183,
    2199             :     SHRAV_QB_MMR2       = 2184,
    2200             :     SHRAV_R_PH  = 2185,
    2201             :     SHRAV_R_PH_MM       = 2186,
    2202             :     SHRAV_R_QB  = 2187,
    2203             :     SHRAV_R_QB_MMR2     = 2188,
    2204             :     SHRAV_R_W   = 2189,
    2205             :     SHRAV_R_W_MM        = 2190,
    2206             :     SHRA_PH     = 2191,
    2207             :     SHRA_PH_MM  = 2192,
    2208             :     SHRA_QB     = 2193,
    2209             :     SHRA_QB_MMR2        = 2194,
    2210             :     SHRA_R_PH   = 2195,
    2211             :     SHRA_R_PH_MM        = 2196,
    2212             :     SHRA_R_QB   = 2197,
    2213             :     SHRA_R_QB_MMR2      = 2198,
    2214             :     SHRA_R_W    = 2199,
    2215             :     SHRA_R_W_MM = 2200,
    2216             :     SHRLV_PH    = 2201,
    2217             :     SHRLV_PH_MMR2       = 2202,
    2218             :     SHRLV_QB    = 2203,
    2219             :     SHRLV_QB_MM = 2204,
    2220             :     SHRL_PH     = 2205,
    2221             :     SHRL_PH_MMR2        = 2206,
    2222             :     SHRL_QB     = 2207,
    2223             :     SHRL_QB_MM  = 2208,
    2224             :     SH_MM       = 2209,
    2225             :     SH_MMR6     = 2210,
    2226             :     SLDI_B      = 2211,
    2227             :     SLDI_D      = 2212,
    2228             :     SLDI_H      = 2213,
    2229             :     SLDI_W      = 2214,
    2230             :     SLD_B       = 2215,
    2231             :     SLD_D       = 2216,
    2232             :     SLD_H       = 2217,
    2233             :     SLD_W       = 2218,
    2234             :     SLL = 2219,
    2235             :     SLL16_MM    = 2220,
    2236             :     SLL16_MMR6  = 2221,
    2237             :     SLL64_32    = 2222,
    2238             :     SLL64_64    = 2223,
    2239             :     SLLI_B      = 2224,
    2240             :     SLLI_D      = 2225,
    2241             :     SLLI_H      = 2226,
    2242             :     SLLI_W      = 2227,
    2243             :     SLLV        = 2228,
    2244             :     SLLV_MM     = 2229,
    2245             :     SLL_B       = 2230,
    2246             :     SLL_D       = 2231,
    2247             :     SLL_H       = 2232,
    2248             :     SLL_MM      = 2233,
    2249             :     SLL_MMR6    = 2234,
    2250             :     SLL_W       = 2235,
    2251             :     SLT = 2236,
    2252             :     SLT64       = 2237,
    2253             :     SLTImm64    = 2238,
    2254             :     SLTUImm64   = 2239,
    2255             :     SLT_MM      = 2240,
    2256             :     SLTi        = 2241,
    2257             :     SLTi64      = 2242,
    2258             :     SLTi_MM     = 2243,
    2259             :     SLTiu       = 2244,
    2260             :     SLTiu64     = 2245,
    2261             :     SLTiu_MM    = 2246,
    2262             :     SLTu        = 2247,
    2263             :     SLTu64      = 2248,
    2264             :     SLTu_MM     = 2249,
    2265             :     SNE = 2250,
    2266             :     SNEi        = 2251,
    2267             :     SNZ_B_PSEUDO        = 2252,
    2268             :     SNZ_D_PSEUDO        = 2253,
    2269             :     SNZ_H_PSEUDO        = 2254,
    2270             :     SNZ_V_PSEUDO        = 2255,
    2271             :     SNZ_W_PSEUDO        = 2256,
    2272             :     SPLATI_B    = 2257,
    2273             :     SPLATI_D    = 2258,
    2274             :     SPLATI_H    = 2259,
    2275             :     SPLATI_W    = 2260,
    2276             :     SPLAT_B     = 2261,
    2277             :     SPLAT_D     = 2262,
    2278             :     SPLAT_H     = 2263,
    2279             :     SPLAT_W     = 2264,
    2280             :     SRA = 2265,
    2281             :     SRAI_B      = 2266,
    2282             :     SRAI_D      = 2267,
    2283             :     SRAI_H      = 2268,
    2284             :     SRAI_W      = 2269,
    2285             :     SRARI_B     = 2270,
    2286             :     SRARI_D     = 2271,
    2287             :     SRARI_H     = 2272,
    2288             :     SRARI_W     = 2273,
    2289             :     SRAR_B      = 2274,
    2290             :     SRAR_D      = 2275,
    2291             :     SRAR_H      = 2276,
    2292             :     SRAR_W      = 2277,
    2293             :     SRAV        = 2278,
    2294             :     SRAV_MM     = 2279,
    2295             :     SRA_B       = 2280,
    2296             :     SRA_D       = 2281,
    2297             :     SRA_H       = 2282,
    2298             :     SRA_MM      = 2283,
    2299             :     SRA_W       = 2284,
    2300             :     SRL = 2285,
    2301             :     SRL16_MM    = 2286,
    2302             :     SRL16_MMR6  = 2287,
    2303             :     SRLI_B      = 2288,
    2304             :     SRLI_D      = 2289,
    2305             :     SRLI_H      = 2290,
    2306             :     SRLI_W      = 2291,
    2307             :     SRLRI_B     = 2292,
    2308             :     SRLRI_D     = 2293,
    2309             :     SRLRI_H     = 2294,
    2310             :     SRLRI_W     = 2295,
    2311             :     SRLR_B      = 2296,
    2312             :     SRLR_D      = 2297,
    2313             :     SRLR_H      = 2298,
    2314             :     SRLR_W      = 2299,
    2315             :     SRLV        = 2300,
    2316             :     SRLV_MM     = 2301,
    2317             :     SRL_B       = 2302,
    2318             :     SRL_D       = 2303,
    2319             :     SRL_H       = 2304,
    2320             :     SRL_MM      = 2305,
    2321             :     SRL_W       = 2306,
    2322             :     SSNOP       = 2307,
    2323             :     SSNOP_MM    = 2308,
    2324             :     SSNOP_MMR6  = 2309,
    2325             :     STORE_ACC128        = 2310,
    2326             :     STORE_ACC64 = 2311,
    2327             :     STORE_ACC64DSP      = 2312,
    2328             :     STORE_CCOND_DSP     = 2313,
    2329             :     ST_B        = 2314,
    2330             :     ST_D        = 2315,
    2331             :     ST_F16      = 2316,
    2332             :     ST_H        = 2317,
    2333             :     ST_W        = 2318,
    2334             :     SUB = 2319,
    2335             :     SUBQH_PH    = 2320,
    2336             :     SUBQH_PH_MMR2       = 2321,
    2337             :     SUBQH_R_PH  = 2322,
    2338             :     SUBQH_R_PH_MMR2     = 2323,
    2339             :     SUBQH_R_W   = 2324,
    2340             :     SUBQH_R_W_MMR2      = 2325,
    2341             :     SUBQH_W     = 2326,
    2342             :     SUBQH_W_MMR2        = 2327,
    2343             :     SUBQ_PH     = 2328,
    2344             :     SUBQ_PH_MM  = 2329,
    2345             :     SUBQ_S_PH   = 2330,
    2346             :     SUBQ_S_PH_MM        = 2331,
    2347             :     SUBQ_S_W    = 2332,
    2348             :     SUBQ_S_W_MM = 2333,
    2349             :     SUBSUS_U_B  = 2334,
    2350             :     SUBSUS_U_D  = 2335,
    2351             :     SUBSUS_U_H  = 2336,
    2352             :     SUBSUS_U_W  = 2337,
    2353             :     SUBSUU_S_B  = 2338,
    2354             :     SUBSUU_S_D  = 2339,
    2355             :     SUBSUU_S_H  = 2340,
    2356             :     SUBSUU_S_W  = 2341,
    2357             :     SUBS_S_B    = 2342,
    2358             :     SUBS_S_D    = 2343,
    2359             :     SUBS_S_H    = 2344,
    2360             :     SUBS_S_W    = 2345,
    2361             :     SUBS_U_B    = 2346,
    2362             :     SUBS_U_D    = 2347,
    2363             :     SUBS_U_H    = 2348,
    2364             :     SUBS_U_W    = 2349,
    2365             :     SUBU16_MM   = 2350,
    2366             :     SUBU16_MMR6 = 2351,
    2367             :     SUBUH_QB    = 2352,
    2368             :     SUBUH_QB_MMR2       = 2353,
    2369             :     SUBUH_R_QB  = 2354,
    2370             :     SUBUH_R_QB_MMR2     = 2355,
    2371             :     SUBU_MMR6   = 2356,
    2372             :     SUBU_PH     = 2357,
    2373             :     SUBU_PH_MMR2        = 2358,
    2374             :     SUBU_QB     = 2359,
    2375             :     SUBU_QB_MM  = 2360,
    2376             :     SUBU_S_PH   = 2361,
    2377             :     SUBU_S_PH_MMR2      = 2362,
    2378             :     SUBU_S_QB   = 2363,
    2379             :     SUBU_S_QB_MM        = 2364,
    2380             :     SUBVI_B     = 2365,
    2381             :     SUBVI_D     = 2366,
    2382             :     SUBVI_H     = 2367,
    2383             :     SUBVI_W     = 2368,
    2384             :     SUBV_B      = 2369,
    2385             :     SUBV_D      = 2370,
    2386             :     SUBV_H      = 2371,
    2387             :     SUBV_W      = 2372,
    2388             :     SUB_MM      = 2373,
    2389             :     SUB_MMR6    = 2374,
    2390             :     SUBu        = 2375,
    2391             :     SUBu_MM     = 2376,
    2392             :     SUXC1       = 2377,
    2393             :     SUXC164     = 2378,
    2394             :     SUXC1_MM    = 2379,
    2395             :     SW  = 2380,
    2396             :     SW16_MM     = 2381,
    2397             :     SW16_MMR6   = 2382,
    2398             :     SW64        = 2383,
    2399             :     SWC1        = 2384,
    2400             :     SWC1_MM     = 2385,
    2401             :     SWC2        = 2386,
    2402             :     SWC2_MMR6   = 2387,
    2403             :     SWC2_R6     = 2388,
    2404             :     SWC3        = 2389,
    2405             :     SWDSP       = 2390,
    2406             :     SWDSP_MM    = 2391,
    2407             :     SWE = 2392,
    2408             :     SWE_MM      = 2393,
    2409             :     SWL = 2394,
    2410             :     SWL64       = 2395,
    2411             :     SWLE        = 2396,
    2412             :     SWLE_MM     = 2397,
    2413             :     SWL_MM      = 2398,
    2414             :     SWM16_MM    = 2399,
    2415             :     SWM16_MMR6  = 2400,
    2416             :     SWM32_MM    = 2401,
    2417             :     SWM_MM      = 2402,
    2418             :     SWP_MM      = 2403,
    2419             :     SWP_MMR6    = 2404,
    2420             :     SWR = 2405,
    2421             :     SWR64       = 2406,
    2422             :     SWRE        = 2407,
    2423             :     SWRE_MM     = 2408,
    2424             :     SWR_MM      = 2409,
    2425             :     SWSP_MM     = 2410,
    2426             :     SWSP_MMR6   = 2411,
    2427             :     SWXC1       = 2412,
    2428             :     SWXC1_MM    = 2413,
    2429             :     SW_MM       = 2414,
    2430             :     SW_MMR6     = 2415,
    2431             :     SYNC        = 2416,
    2432             :     SYNCI       = 2417,
    2433             :     SYNCI_MM    = 2418,
    2434             :     SYNCI_MMR6  = 2419,
    2435             :     SYNC_MM     = 2420,
    2436             :     SYNC_MMR6   = 2421,
    2437             :     SYSCALL     = 2422,
    2438             :     SYSCALL_MM  = 2423,
    2439             :     SZ_B_PSEUDO = 2424,
    2440             :     SZ_D_PSEUDO = 2425,
    2441             :     SZ_H_PSEUDO = 2426,
    2442             :     SZ_V_PSEUDO = 2427,
    2443             :     SZ_W_PSEUDO = 2428,
    2444             :     Save16      = 2429,
    2445             :     SaveX16     = 2430,
    2446             :     SbRxRyOffMemX16     = 2431,
    2447             :     SebRx16     = 2432,
    2448             :     SehRx16     = 2433,
    2449             :     SelBeqZ     = 2434,
    2450             :     SelBneZ     = 2435,
    2451             :     SelTBteqZCmp        = 2436,
    2452             :     SelTBteqZCmpi       = 2437,
    2453             :     SelTBteqZSlt        = 2438,
    2454             :     SelTBteqZSlti       = 2439,
    2455             :     SelTBteqZSltiu      = 2440,
    2456             :     SelTBteqZSltu       = 2441,
    2457             :     SelTBtneZCmp        = 2442,
    2458             :     SelTBtneZCmpi       = 2443,
    2459             :     SelTBtneZSlt        = 2444,
    2460             :     SelTBtneZSlti       = 2445,
    2461             :     SelTBtneZSltiu      = 2446,
    2462             :     SelTBtneZSltu       = 2447,
    2463             :     ShRxRyOffMemX16     = 2448,
    2464             :     SllX16      = 2449,
    2465             :     SllvRxRy16  = 2450,
    2466             :     SltCCRxRy16 = 2451,
    2467             :     SltRxRy16   = 2452,
    2468             :     SltiCCRxImmX16      = 2453,
    2469             :     SltiRxImm16 = 2454,
    2470             :     SltiRxImmX16        = 2455,
    2471             :     SltiuCCRxImmX16     = 2456,
    2472             :     SltiuRxImm16        = 2457,
    2473             :     SltiuRxImmX16       = 2458,
    2474             :     SltuCCRxRy16        = 2459,
    2475             :     SltuRxRy16  = 2460,
    2476             :     SltuRxRyRz16        = 2461,
    2477             :     SraX16      = 2462,
    2478             :     SravRxRy16  = 2463,
    2479             :     SrlX16      = 2464,
    2480             :     SrlvRxRy16  = 2465,
    2481             :     SubuRxRyRz16        = 2466,
    2482             :     SwRxRyOffMemX16     = 2467,
    2483             :     SwRxSpImmX16        = 2468,
    2484             :     TAILCALL    = 2469,
    2485             :     TAILCALL64R6REG     = 2470,
    2486             :     TAILCALLHB64R6REG   = 2471,
    2487             :     TAILCALLHBR6REG     = 2472,
    2488             :     TAILCALLR6REG       = 2473,
    2489             :     TAILCALLREG = 2474,
    2490             :     TAILCALLREG64       = 2475,
    2491             :     TAILCALLREGHB       = 2476,
    2492             :     TAILCALLREGHB64     = 2477,
    2493             :     TAILCALLREG_MM      = 2478,
    2494             :     TAILCALLREG_MMR6    = 2479,
    2495             :     TAILCALL_MM = 2480,
    2496             :     TAILCALL_MMR6       = 2481,
    2497             :     TEQ = 2482,
    2498             :     TEQI        = 2483,
    2499             :     TEQI_MM     = 2484,
    2500             :     TEQ_MM      = 2485,
    2501             :     TGE = 2486,
    2502             :     TGEI        = 2487,
    2503             :     TGEIU       = 2488,
    2504             :     TGEIU_MM    = 2489,
    2505             :     TGEI_MM     = 2490,
    2506             :     TGEU        = 2491,
    2507             :     TGEU_MM     = 2492,
    2508             :     TGE_MM      = 2493,
    2509             :     TLBGINV     = 2494,
    2510             :     TLBGINVF    = 2495,
    2511             :     TLBGINVF_MM = 2496,
    2512             :     TLBGINV_MM  = 2497,
    2513             :     TLBGP       = 2498,
    2514             :     TLBGP_MM    = 2499,
    2515             :     TLBGR       = 2500,
    2516             :     TLBGR_MM    = 2501,
    2517             :     TLBGWI      = 2502,
    2518             :     TLBGWI_MM   = 2503,
    2519             :     TLBGWR      = 2504,
    2520             :     TLBGWR_MM   = 2505,
    2521             :     TLBINV      = 2506,
    2522             :     TLBINVF     = 2507,
    2523             :     TLBINVF_MMR6        = 2508,
    2524             :     TLBINV_MMR6 = 2509,
    2525             :     TLBP        = 2510,
    2526             :     TLBP_MM     = 2511,
    2527             :     TLBR        = 2512,
    2528             :     TLBR_MM     = 2513,
    2529             :     TLBWI       = 2514,
    2530             :     TLBWI_MM    = 2515,
    2531             :     TLBWR       = 2516,
    2532             :     TLBWR_MM    = 2517,
    2533             :     TLT = 2518,
    2534             :     TLTI        = 2519,
    2535             :     TLTIU_MM    = 2520,
    2536             :     TLTI_MM     = 2521,
    2537             :     TLTU        = 2522,
    2538             :     TLTU_MM     = 2523,
    2539             :     TLT_MM      = 2524,
    2540             :     TNE = 2525,
    2541             :     TNEI        = 2526,
    2542             :     TNEI_MM     = 2527,
    2543             :     TNE_MM      = 2528,
    2544             :     TRAP        = 2529,
    2545             :     TRUNC_L_D64 = 2530,
    2546             :     TRUNC_L_D_MMR6      = 2531,
    2547             :     TRUNC_L_S   = 2532,
    2548             :     TRUNC_L_S_MMR6      = 2533,
    2549             :     TRUNC_W_D32 = 2534,
    2550             :     TRUNC_W_D64 = 2535,
    2551             :     TRUNC_W_D_MMR6      = 2536,
    2552             :     TRUNC_W_MM  = 2537,
    2553             :     TRUNC_W_S   = 2538,
    2554             :     TRUNC_W_S_MM        = 2539,
    2555             :     TRUNC_W_S_MMR6      = 2540,
    2556             :     TTLTIU      = 2541,
    2557             :     UDIV        = 2542,
    2558             :     UDIV_MM     = 2543,
    2559             :     UDIV_MM_Pseudo      = 2544,
    2560             :     UDivIMacro  = 2545,
    2561             :     UDivMacro   = 2546,
    2562             :     Ulh = 2547,
    2563             :     Ulhu        = 2548,
    2564             :     Ulw = 2549,
    2565             :     Ush = 2550,
    2566             :     Usw = 2551,
    2567             :     V3MULU      = 2552,
    2568             :     VMM0        = 2553,
    2569             :     VMULU       = 2554,
    2570             :     VSHF_B      = 2555,
    2571             :     VSHF_D      = 2556,
    2572             :     VSHF_H      = 2557,
    2573             :     VSHF_W      = 2558,
    2574             :     WAIT        = 2559,
    2575             :     WAIT_MM     = 2560,
    2576             :     WAIT_MMR6   = 2561,
    2577             :     WRDSP       = 2562,
    2578             :     WRDSP_MM    = 2563,
    2579             :     WRPGPR_MMR6 = 2564,
    2580             :     WSBH        = 2565,
    2581             :     WSBH_MM     = 2566,
    2582             :     WSBH_MMR6   = 2567,
    2583             :     XOR = 2568,
    2584             :     XOR16_MM    = 2569,
    2585             :     XOR16_MMR6  = 2570,
    2586             :     XOR64       = 2571,
    2587             :     XORI_B      = 2572,
    2588             :     XORI_MMR6   = 2573,
    2589             :     XOR_MM      = 2574,
    2590             :     XOR_MMR6    = 2575,
    2591             :     XOR_V       = 2576,
    2592             :     XOR_V_D_PSEUDO      = 2577,
    2593             :     XOR_V_H_PSEUDO      = 2578,
    2594             :     XOR_V_W_PSEUDO      = 2579,
    2595             :     XORi        = 2580,
    2596             :     XORi64      = 2581,
    2597             :     XORi_MM     = 2582,
    2598             :     XorRxRxRy16 = 2583,
    2599             :     YIELD       = 2584,
    2600             :     INSTRUCTION_LIST_END = 2585
    2601             :   };
    2602             : 
    2603             : } // end Mips namespace
    2604             : } // end llvm namespace
    2605             : #endif // GET_INSTRINFO_ENUM
    2606             : 
    2607             : #ifdef GET_INSTRINFO_SCHED_ENUM
    2608             : #undef GET_INSTRINFO_SCHED_ENUM
    2609             : namespace llvm {
    2610             : 
    2611             : namespace Mips {
    2612             : namespace Sched {
    2613             :   enum {
    2614             :     NoInstrModel        = 0,
    2615             :     IIPseudo    = 1,
    2616             :     II_ADD      = 2,
    2617             :     II_ADDIUPC  = 3,
    2618             :     II_ADDIU    = 4,
    2619             :     II_ADDU     = 5,
    2620             :     II_ADDI     = 6,
    2621             :     II_ALIGN    = 7,
    2622             :     II_ALUIPC   = 8,
    2623             :     II_AND      = 9,
    2624             :     II_ANDI     = 10,
    2625             :     II_AUI      = 11,
    2626             :     II_AUIPC    = 12,
    2627             :     IIM16Alu    = 13,
    2628             :     II_B        = 14,
    2629             :     II_BADDU    = 15,
    2630             :     II_BC       = 16,
    2631             :     II_BALC     = 17,
    2632             :     II_BCCZAL   = 18,
    2633             :     II_BBIT     = 19,
    2634             :     II_BC1CCZ   = 20,
    2635             :     II_BC1F     = 21,
    2636             :     II_BC1FL    = 22,
    2637             :     II_BC1T     = 23,
    2638             :     II_BC1TL    = 24,
    2639             :     II_BC2CCZ   = 25,
    2640             :     II_BCC      = 26,
    2641             :     II_BCCC     = 27,
    2642             :     II_BCCZ     = 28,
    2643             :     II_BCCZC    = 29,
    2644             :     II_BCCZALS  = 30,
    2645             :     II_BITSWAP  = 31,
    2646             :     II_BREAK    = 32,
    2647             :     II_MTC1     = 33,
    2648             :     II_CACHE    = 34,
    2649             :     II_CACHEE   = 35,
    2650             :     II_CEIL     = 36,
    2651             :     II_CFC1     = 37,
    2652             :     II_CFC2     = 38,
    2653             :     II_INS      = 39,
    2654             :     II_CLASS_D  = 40,
    2655             :     II_CLASS_S  = 41,
    2656             :     II_CLO      = 42,
    2657             :     II_CLZ      = 43,
    2658             :     II_CMP_CC_D = 44,
    2659             :     II_CMP_CC_S = 45,
    2660             :     II_CRC32B   = 46,
    2661             :     II_CRC32CB  = 47,
    2662             :     II_CRC32CD  = 48,
    2663             :     II_CRC32CH  = 49,
    2664             :     II_CRC32CW  = 50,
    2665             :     II_CRC32D   = 51,
    2666             :     II_CRC32H   = 52,
    2667             :     II_CRC32W   = 53,
    2668             :     II_CTC1     = 54,
    2669             :     II_CTC2     = 55,
    2670             :     II_CVT      = 56,
    2671             :     II_C_CC_D   = 57,
    2672             :     II_C_CC_S   = 58,
    2673             :     II_DADD     = 59,
    2674             :     II_DADDI    = 60,
    2675             :     II_DADDIU   = 61,
    2676             :     II_DADDU    = 62,
    2677             :     II_DAHI     = 63,
    2678             :     II_DALIGN   = 64,
    2679             :     II_DATI     = 65,
    2680             :     II_DAUI     = 66,
    2681             :     II_DBITSWAP = 67,
    2682             :     II_DCLO     = 68,
    2683             :     II_DCLZ     = 69,
    2684             :     II_DDIV     = 70,
    2685             :     II_DDIVU    = 71,
    2686             :     II_DERET    = 72,
    2687             :     II_EXT      = 73,
    2688             :     II_DI       = 74,
    2689             :     II_DIV      = 75,
    2690             :     II_DIVU     = 76,
    2691             :     II_DLSA     = 77,
    2692             :     II_DMFC0    = 78,
    2693             :     II_DMFC1    = 79,
    2694             :     II_DMFC2    = 80,
    2695             :     II_DMFGC0   = 81,
    2696             :     II_DMOD     = 82,
    2697             :     II_DMODU    = 83,
    2698             :     II_DMT      = 84,
    2699             :     II_DMTC0    = 85,
    2700             :     II_DMTC1    = 86,
    2701             :     II_DMTC2    = 87,
    2702             :     II_DMTGC0   = 88,
    2703             :     II_DMUH     = 89,
    2704             :     II_DMUHU    = 90,
    2705             :     II_DMUL     = 91,
    2706             :     II_DMULT    = 92,
    2707             :     II_DMULTU   = 93,
    2708             :     II_POP      = 94,
    2709             :     II_DROTR    = 95,
    2710             :     II_DROTR32  = 96,
    2711             :     II_DROTRV   = 97,
    2712             :     II_DSBH     = 98,
    2713             :     II_DSHD     = 99,
    2714             :     II_DSLL     = 100,
    2715             :     II_DSLL32   = 101,
    2716             :     II_DSLLV    = 102,
    2717             :     II_DSRA     = 103,
    2718             :     II_DSRA32   = 104,
    2719             :     II_DSRAV    = 105,
    2720             :     II_DSRL     = 106,
    2721             :     II_DSRL32   = 107,
    2722             :     II_DSRLV    = 108,
    2723             :     II_DSUB     = 109,
    2724             :     II_DSUBU    = 110,
    2725             :     II_DVP      = 111,
    2726             :     II_DVPE     = 112,
    2727             :     II_EHB      = 113,
    2728             :     II_EI       = 114,
    2729             :     II_EMT      = 115,
    2730             :     II_ERET     = 116,
    2731             :     II_ERETNC   = 117,
    2732             :     II_EVP      = 118,
    2733             :     II_EVPE     = 119,
    2734             :     II_MFC1     = 120,
    2735             :     II_ABS      = 121,
    2736             :     II_SQRT_D   = 122,
    2737             :     II_ADD_D    = 123,
    2738             :     II_ADD_S    = 124,
    2739             :     II_DIV_D    = 125,
    2740             :     II_DIV_S    = 126,
    2741             :     II_FLOOR    = 127,
    2742             :     II_MOV_D    = 128,
    2743             :     II_MOV_S    = 129,
    2744             :     II_MUL_D    = 130,
    2745             :     II_MUL_S    = 131,
    2746             :     II_NEG      = 132,
    2747             :     II_FORK     = 133,
    2748             :     II_SQRT_S   = 134,
    2749             :     II_SUB_D    = 135,
    2750             :     II_SUB_S    = 136,
    2751             :     II_GINVI    = 137,
    2752             :     II_GINVT    = 138,
    2753             :     II_HYPCALL  = 139,
    2754             :     II_J        = 140,
    2755             :     II_JAL      = 141,
    2756             :     II_JALR     = 142,
    2757             :     II_JALR_HB  = 143,
    2758             :     II_JALRC    = 144,
    2759             :     II_JALRS    = 145,
    2760             :     II_JALS     = 146,
    2761             :     II_JIALC    = 147,
    2762             :     II_JIC      = 148,
    2763             :     II_JR       = 149,
    2764             :     II_JRADDIUSP        = 150,
    2765             :     II_JRC      = 151,
    2766             :     II_JR_HB    = 152,
    2767             :     II_LB       = 153,
    2768             :     II_LBE      = 154,
    2769             :     II_LBU      = 155,
    2770             :     II_LBUE     = 156,
    2771             :     II_LD       = 157,
    2772             :     II_LDC1     = 158,
    2773             :     II_LDC2     = 159,
    2774             :     II_LDC3     = 160,
    2775             :     II_LDL      = 161,
    2776             :     II_LDPC     = 162,
    2777             :     II_LDR      = 163,
    2778             :     II_LDXC1    = 164,
    2779             :     II_LH       = 165,
    2780             :     II_LHE      = 166,
    2781             :     II_LHU      = 167,
    2782             :     II_LHUE     = 168,
    2783             :     II_LI       = 169,
    2784             :     II_LL       = 170,
    2785             :     II_LLD      = 171,
    2786             :     II_LLE      = 172,
    2787             :     II_LSA      = 173,
    2788             :     II_LUI      = 174,
    2789             :     II_LUXC1    = 175,
    2790             :     II_LW       = 176,
    2791             :     II_LWC1     = 177,
    2792             :     II_LWC2     = 178,
    2793             :     II_LWC3     = 179,
    2794             :     II_LWE      = 180,
    2795             :     II_LWL      = 181,
    2796             :     II_LWLE     = 182,
    2797             :     II_LWM      = 183,
    2798             :     II_LWPC     = 184,
    2799             :     II_LWP      = 185,
    2800             :     II_LWR      = 186,
    2801             :     II_LWRE     = 187,
    2802             :     II_LWUPC    = 188,
    2803             :     II_LWU      = 189,
    2804             :     II_LWXC1    = 190,
    2805             :     II_LWXS     = 191,
    2806             :     II_MADD     = 192,
    2807             :     II_MADDF_D  = 193,
    2808             :     II_MADDF_S  = 194,
    2809             :     II_MADDU    = 195,
    2810             :     II_MADD_D   = 196,
    2811             :     II_MADD_S   = 197,
    2812             :     II_MAX_D    = 198,
    2813             :     II_MAXA_D   = 199,
    2814             :     II_MAX_S    = 200,
    2815             :     II_MAXA_S   = 201,
    2816             :     II_MFC0     = 202,
    2817             :     II_MFC2     = 203,
    2818             :     II_MFGC0    = 204,
    2819             :     II_MFHC0    = 205,
    2820             :     II_MFHC1    = 206,
    2821             :     II_MFHGC0   = 207,
    2822             :     II_MFHI_MFLO        = 208,
    2823             :     II_MFTR     = 209,
    2824             :     II_MIN_S    = 210,
    2825             :     II_MINA_D   = 211,
    2826             :     II_MIN_D    = 212,
    2827             :     II_MINA_S   = 213,
    2828             :     II_MOD      = 214,
    2829             :     II_MODU     = 215,
    2830             :     II_MOVE     = 216,
    2831             :     II_MOVF_D   = 217,
    2832             :     II_MOVF     = 218,
    2833             :     II_MOVF_S   = 219,
    2834             :     II_MOVN_D   = 220,
    2835             :     II_MOVN     = 221,
    2836             :     II_MOVN_S   = 222,
    2837             :     II_MOVT_D   = 223,
    2838             :     II_MOVT     = 224,
    2839             :     II_MOVT_S   = 225,
    2840             :     II_MOVZ_D   = 226,
    2841             :     II_MOVZ     = 227,
    2842             :     II_MOVZ_S   = 228,
    2843             :     II_MSUB     = 229,
    2844             :     II_MSUBF_D  = 230,
    2845             :     II_MSUBF_S  = 231,
    2846             :     II_MSUBU    = 232,
    2847             :     II_MSUB_D   = 233,
    2848             :     II_MSUB_S   = 234,
    2849             :     II_MTC0     = 235,
    2850             :     II_MTC2     = 236,
    2851             :     II_MTGC0    = 237,
    2852             :     II_MTHC0    = 238,
    2853             :     II_MTHC1    = 239,
    2854             :     II_MTHGC0   = 240,
    2855             :     II_MTHI_MTLO        = 241,
    2856             :     II_MTTR     = 242,
    2857             :     II_MUH      = 243,
    2858             :     II_MUHU     = 244,
    2859             :     II_MUL      = 245,
    2860             :     II_MULT     = 246,
    2861             :     II_MULTU    = 247,
    2862             :     II_MULU     = 248,
    2863             :     II_NMADD_D  = 249,
    2864             :     II_NMADD_S  = 250,
    2865             :     II_NMSUB_D  = 251,
    2866             :     II_NMSUB_S  = 252,
    2867             :     II_NOR      = 253,
    2868             :     II_NOT      = 254,
    2869             :     II_OR       = 255,
    2870             :     II_ORI      = 256,
    2871             :     II_PAUSE    = 257,
    2872             :     II_PREF     = 258,
    2873             :     II_PREFE    = 259,
    2874             :     II_IndirectBranchPseudo     = 260,
    2875             :     II_ReturnPseudo     = 261,
    2876             :     II_RDHWR    = 262,
    2877             :     II_RDPGPR   = 263,
    2878             :     II_RECIP_D  = 264,
    2879             :     II_RECIP_S  = 265,
    2880             :     II_RINT_D   = 266,
    2881             :     II_RINT_S   = 267,
    2882             :     II_ROTR     = 268,
    2883             :     II_ROTRV    = 269,
    2884             :     II_ROUND    = 270,
    2885             :     II_RSQRT_D  = 271,
    2886             :     II_RSQRT_S  = 272,
    2887             :     II_RESTORE  = 273,
    2888             :     II_SB       = 274,
    2889             :     II_SBE      = 275,
    2890             :     II_SC       = 276,
    2891             :     II_SCD      = 277,
    2892             :     II_SCE      = 278,
    2893             :     II_SD       = 279,
    2894             :     II_SDBBP    = 280,
    2895             :     II_SDC1     = 281,
    2896             :     II_SDC2     = 282,
    2897             :     II_SDC3     = 283,
    2898             :     II_SDL      = 284,
    2899             :     II_SDR      = 285,
    2900             :     II_SDXC1    = 286,
    2901             :     II_SEB      = 287,
    2902             :     II_SEH      = 288,
    2903             :     II_SELCCZ   = 289,
    2904             :     II_SELCCZ_D = 290,
    2905             :     II_SELCCZ_S = 291,
    2906             :     II_SEL_D    = 292,
    2907             :     II_SEL_S    = 293,
    2908             :     II_SEQ_SNE  = 294,
    2909             :     II_SEQI_SNEI        = 295,
    2910             :     II_SH       = 296,
    2911             :     II_SHE      = 297,
    2912             :     II_SLL      = 298,
    2913             :     II_SLLV     = 299,
    2914             :     II_SLT_SLTU = 300,
    2915             :     II_SLTI_SLTIU       = 301,
    2916             :     II_SRA      = 302,
    2917             :     II_SRAV     = 303,
    2918             :     II_SRL      = 304,
    2919             :     II_SRLV     = 305,
    2920             :     II_SSNOP    = 306,
    2921             :     II_SUB      = 307,
    2922             :     II_SUBU     = 308,
    2923             :     II_SUXC1    = 309,
    2924             :     II_SW       = 310,
    2925             :     II_SWC1     = 311,
    2926             :     II_SWC2     = 312,
    2927             :     II_SWC3     = 313,
    2928             :     II_SWE      = 314,
    2929             :     II_SWL      = 315,
    2930             :     II_SWLE     = 316,
    2931             :     II_SWM      = 317,
    2932             :     II_SWP      = 318,
    2933             :     II_SWR      = 319,
    2934             :     II_SWRE     = 320,
    2935             :     II_SWXC1    = 321,
    2936             :     II_SYNC     = 322,
    2937             :     II_SYNCI    = 323,
    2938             :     II_SYSCALL  = 324,
    2939             :     II_SAVE     = 325,
    2940             :     II_TEQ      = 326,
    2941             :     II_TEQI     = 327,
    2942             :     II_TGE      = 328,
    2943             :     II_TGEI     = 329,
    2944             :     II_TGEIU    = 330,
    2945             :     II_TGEU     = 331,
    2946             :     II_TLBGINV  = 332,
    2947             :     II_TLBGINVF = 333,
    2948             :     II_TLBGP    = 334,
    2949             :     II_TLBGR    = 335,
    2950             :     II_TLBGWI   = 336,
    2951             :     II_TLBGWR   = 337,
    2952             :     II_TLBINV   = 338,
    2953             :     II_TLBINVF  = 339,
    2954             :     II_TLBP     = 340,
    2955             :     II_TLBR     = 341,
    2956             :     II_TLBWI    = 342,
    2957             :     II_TLBWR    = 343,
    2958             :     II_TLT      = 344,
    2959             :     II_TLTI     = 345,
    2960             :     II_TTLTIU   = 346,
    2961             :     II_TLTU     = 347,
    2962             :     II_TNE      = 348,
    2963             :     II_TNEI     = 349,
    2964             :     II_TRAP     = 350,
    2965             :     II_TRUNC    = 351,
    2966             :     II_WAIT     = 352,
    2967             :     II_WRPGPR   = 353,
    2968             :     II_WSBH     = 354,
    2969             :     II_XOR      = 355,
    2970             :     II_XORI     = 356,
    2971             :     II_YIELD    = 357,
    2972             :     COPY        = 358,
    2973             :     VSHF_B_VSHF_D_VSHF_H_VSHF_W = 359,
    2974             :     BINSLI_B_BINSLI_D_BINSLI_H_BINSLI_W_BINSL_B_BINSL_D_BINSL_H_BINSL_W = 360,
    2975             :     BINSRI_B_BINSRI_D_BINSRI_H_BINSRI_W_BINSR_B_BINSR_D_BINSR_H_BINSR_W = 361,
    2976             :     INSERT_B_INSERT_D_INSERT_H_INSERT_W = 362,
    2977             :     SLDI_B_SLDI_D_SLDI_H_SLDI_W_SLD_B_SLD_D_SLD_H_SLD_W = 363,
    2978             :     BSETI_B_BSETI_D_BSETI_H_BSETI_W_BSET_B_BSET_D_BSET_H_BSET_W = 364,
    2979             :     BCLRI_B_BCLRI_D_BCLRI_H_BCLRI_W_BCLR_B_BCLR_D_BCLR_H_BCLR_W = 365,
    2980             :     BNEGI_B_BNEGI_D_BNEGI_H_BNEGI_W_BNEG_B_BNEG_D_BNEG_H_BNEG_W = 366,
    2981             :     BSELI_B_BSEL_V      = 367,
    2982             :     BMNZI_B_BMNZ_V_BMZI_B_BMZ_V = 368,
    2983             :     PCNT_B_PCNT_D_PCNT_H_PCNT_W = 369,
    2984             :     SAT_S_B_SAT_S_D_SAT_S_H_SAT_S_W_SAT_U_B_SAT_U_D_SAT_U_H_SAT_U_W     = 370,
    2985             :     BNZ_B_BNZ_D_BNZ_H_BNZ_V_BNZ_W_BZ_B_BZ_D_BZ_H_BZ_V_BZ_W      = 371,
    2986             :     CFCMSA_CTCMSA       = 372,
    2987             :     ADD_A_B_ADD_A_D_ADD_A_H_ADD_A_W     = 373,
    2988             :     ADDS_A_B_ADDS_A_D_ADDS_A_H_ADDS_A_W_ADDS_S_B_ADDS_S_D_ADDS_S_H_ADDS_S_W_ADDS_U_B_ADDS_U_D_ADDS_U_H_ADDS_U_W = 374,
    2989             :     ADDVI_B_ADDVI_D_ADDVI_H_ADDVI_W_ADDV_B_ADDV_D_ADDV_H_ADDV_W = 375,
    2990             :     ASUB_S_B_ASUB_S_D_ASUB_S_H_ASUB_S_W_ASUB_U_B_ASUB_U_D_ASUB_U_H_ASUB_U_W     = 376,
    2991             :     AVER_S_B_AVER_S_D_AVER_S_H_AVER_S_W_AVER_U_B_AVER_U_D_AVER_U_H_AVER_U_W_AVE_S_B_AVE_S_D_AVE_S_H_AVE_S_W_AVE_U_B_AVE_U_D_AVE_U_H_AVE_U_W     = 377,
    2992             :     SHF_B_SHF_H_SHF_W   = 378,
    2993             :     FILL_B_FILL_D_FILL_H_FILL_W = 379,
    2994             :     SPLATI_B_SPLATI_D_SPLATI_H_SPLATI_W_SPLAT_B_SPLAT_D_SPLAT_H_SPLAT_W = 380,
    2995             :     MOVE_V      = 381,
    2996             :     LDI_B_LDI_D_LDI_H_LDI_W     = 382,
    2997             :     AND_V_NOR_V_OR_V_XOR_V      = 383,
    2998             :     ANDI_B_NORI_B_ORI_B_XORI_B  = 384,
    2999             :     FEXP2_D_FEXP2_W     = 385,
    3000             :     CLTI_S_B_CLTI_S_D_CLTI_S_H_CLTI_S_W_CLTI_U_B_CLTI_U_D_CLTI_U_H_CLTI_U_W_CLT_S_B_CLT_S_D_CLT_S_H_CLT_S_W_CLT_U_B_CLT_U_D_CLT_U_H_CLT_U_W     = 386,
    3001             :     CLEI_S_B_CLEI_S_D_CLEI_S_H_CLEI_S_W_CLEI_U_B_CLEI_U_D_CLEI_U_H_CLEI_U_W_CLE_S_B_CLE_S_D_CLE_S_H_CLE_S_W_CLE_U_B_CLE_U_D_CLE_U_H_CLE_U_W     = 387,
    3002             :     CEQI_B_CEQI_D_CEQI_H_CEQI_W_CEQ_B_CEQ_D_CEQ_H_CEQ_W = 388,
    3003             :     CMP_UN_D    = 389,
    3004             :     CMP_UN_S    = 390,
    3005             :     CMP_UEQ_D   = 391,
    3006             :     CMP_UEQ_S   = 392,
    3007             :     CMP_EQ_D    = 393,
    3008             :     CMP_EQ_S    = 394,
    3009             :     CMP_LT_D    = 395,
    3010             :     CMP_LT_S    = 396,
    3011             :     CMP_ULT_D   = 397,
    3012             :     CMP_ULT_S   = 398,
    3013             :     CMP_LE_D    = 399,
    3014             :     CMP_LE_S    = 400,
    3015             :     CMP_ULE_D   = 401,
    3016             :     CMP_ULE_S   = 402,
    3017             :     FSAF_D_FSAF_W_FSEQ_D_FSEQ_W_FSLE_D_FSLE_W_FSLT_D_FSLT_W_FSNE_D_FSNE_W_FSOR_D_FSOR_W = 403,
    3018             :     FSUEQ_D_FSUEQ_W     = 404,
    3019             :     FSULE_D_FSULE_W     = 405,
    3020             :     FSULT_D_FSULT_W     = 406,
    3021             :     FSUNE_D_FSUNE_W     = 407,
    3022             :     FSUN_D_FSUN_W       = 408,
    3023             :     FCAF_D_FCAF_W       = 409,
    3024             :     FCEQ_D_FCEQ_W       = 410,
    3025             :     FCLE_D_FCLE_W       = 411,
    3026             :     FCLT_D_FCLT_W       = 412,
    3027             :     FCNE_D_FCNE_W       = 413,
    3028             :     FCOR_D_FCOR_W       = 414,
    3029             :     FCUEQ_D_FCUEQ_W     = 415,
    3030             :     FCULE_D_FCULE_W     = 416,
    3031             :     FCULT_D_FCULT_W     = 417,
    3032             :     FCUNE_D_FCUNE_W     = 418,
    3033             :     FCUN_D_FCUN_W       = 419,
    3034             :     FABS_D_FABS_W       = 420,
    3035             :     FFINT_S_D_FFINT_S_W_FFINT_U_D_FFINT_U_W     = 421,
    3036             :     FFQL_D_FFQL_W       = 422,
    3037             :     FFQR_D_FFQR_W       = 423,
    3038             :     FTINT_S_D_FTINT_S_W_FTINT_U_D_FTINT_U_W     = 424,
    3039             :     FRINT_D_FRINT_W     = 425,
    3040             :     FTQ_H_FTQ_W = 426,
    3041             :     FTRUNC_S_D_FTRUNC_S_W_FTRUNC_U_D_FTRUNC_U_W = 427,
    3042             :     FEXDO_H_FEXDO_W     = 428,
    3043             :     FEXUPL_D_FEXUPL_W   = 429,
    3044             :     FEXUPR_D_FEXUPR_W   = 430,
    3045             :     FCLASS_D_FCLASS_W   = 431,
    3046             :     FMAX_A_D_FMAX_A_W   = 432,
    3047             :     FMAX_D_FMAX_W       = 433,
    3048             :     FMIN_A_D_FMIN_A_W   = 434,
    3049             :     FMIN_D_FMIN_W       = 435,
    3050             :     FLOG2_D_FLOG2_W     = 436,
    3051             :     ILVL_B_ILVL_D_ILVL_H_ILVL_W_ILVR_B_ILVR_D_ILVR_H_ILVR_W     = 437,
    3052             :     ILVEV_B_ILVEV_D_ILVEV_H_ILVEV_W_ILVOD_B_ILVOD_D_ILVOD_H_ILVOD_W     = 438,
    3053             :     INSVE_B_INSVE_D_INSVE_H_INSVE_W     = 439,
    3054             :     SUBS_S_B_SUBS_S_D_SUBS_S_H_SUBS_S_W_SUBS_U_B_SUBS_U_D_SUBS_U_H_SUBS_U_W     = 440,
    3055             :     SUBSUS_U_B_SUBSUS_U_D_SUBSUS_U_H_SUBSUS_U_W = 441,
    3056             :     SUBSUU_S_B_SUBSUU_S_D_SUBSUU_S_H_SUBSUU_S_W = 442,
    3057             :     SUBVI_B_SUBVI_D_SUBVI_H_SUBVI_W     = 443,
    3058             :     SUBV_B_SUBV_D_SUBV_H_SUBV_W = 444,
    3059             :     MOD_S_B_MOD_S_D_MOD_S_H_MOD_S_W_MOD_U_B_MOD_U_D_MOD_U_H_MOD_U_W     = 445,
    3060             :     DIV_S_B_DIV_S_D_DIV_S_H_DIV_S_W_DIV_U_B_DIV_U_D_DIV_U_H_DIV_U_W     = 446,
    3061             :     HADD_S_D_HADD_S_H_HADD_S_W_HADD_U_D_HADD_U_H_HADD_U_W       = 447,
    3062             :     HSUB_S_D_HSUB_S_H_HSUB_S_W_HSUB_U_D_HSUB_U_H_HSUB_U_W       = 448,
    3063             :     MAX_S_B_MAX_S_D_MAX_S_H_MAX_S_W_MIN_S_B_MIN_S_D_MIN_S_H_MIN_S_W     = 449,
    3064             :     MAX_U_B_MAX_U_D_MAX_U_H_MAX_U_W_MIN_U_B_MIN_U_D_MIN_U_H_MIN_U_W     = 450,
    3065             :     MAX_A_B_MAX_A_D_MAX_A_H_MAX_A_W_MIN_A_B_MIN_A_D_MIN_A_H_MIN_A_W     = 451,
    3066             :     MAXI_S_B_MAXI_S_D_MAXI_S_H_MAXI_S_W_MAXI_U_B_MAXI_U_D_MAXI_U_H_MAXI_U_W_MINI_S_B_MINI_S_D_MINI_S_H_MINI_S_W_MINI_U_B_MINI_U_D_MINI_U_H_MINI_U_W     = 452,
    3067             :     SRAI_B_SRAI_D_SRAI_H_SRAI_W_SRA_B_SRA_D_SRA_H_SRA_W = 453,
    3068             :     SRLI_B_SRLI_D_SRLI_H_SRLI_W_SRL_B_SRL_D_SRL_H_SRL_W = 454,
    3069             :     SRARI_B_SRARI_D_SRARI_H_SRARI_W_SRAR_B_SRAR_D_SRAR_H_SRAR_W = 455,
    3070             :     SRLRI_B_SRLRI_D_SRLRI_H_SRLRI_W_SRLR_B_SRLR_D_SRLR_H_SRLR_W = 456,
    3071             :     SLLI_B_SLLI_D_SLLI_H_SLLI_W_SLL_B_SLL_D_SLL_H_SLL_W = 457,
    3072             :     PCKEV_B_PCKEV_D_PCKEV_H_PCKEV_W_PCKOD_B_PCKOD_D_PCKOD_H_PCKOD_W     = 458,
    3073             :     NLOC_B_NLOC_D_NLOC_H_NLOC_W_NLZC_B_NLZC_D_NLZC_H_NLZC_W     = 459,
    3074             :     FRCP_D_FRCP_W       = 460,
    3075             :     FRSQRT_D_FRSQRT_W   = 461,
    3076             :     FMADD_D_FMADD_W     = 462,
    3077             :     FMSUB_D_FMSUB_W     = 463,
    3078             :     FDIV_W      = 464,
    3079             :     FDIV_D      = 465,
    3080             :     FSQRT_W     = 466,
    3081             :     FSQRT_D     = 467,
    3082             :     FMUL_D_FMUL_W       = 468,
    3083             :     FADD_D_FADD_W       = 469,
    3084             :     FSUB_D_FSUB_W       = 470,
    3085             :     DPADD_S_D_DPADD_S_H_DPADD_S_W_DPADD_U_D_DPADD_U_H_DPADD_U_W = 471,
    3086             :     DPSUB_S_D_DPSUB_S_H_DPSUB_S_W_DPSUB_U_D_DPSUB_U_H_DPSUB_U_W = 472,
    3087             :     DOTP_S_D_DOTP_S_H_DOTP_S_W_DOTP_U_D_DOTP_U_H_DOTP_U_W       = 473,
    3088             :     MSUBV_B_MSUBV_D_MSUBV_H_MSUBV_W     = 474,
    3089             :     MADDV_B_MADDV_D_MADDV_H_MADDV_W     = 475,
    3090             :     MULV_B_MULV_D_MULV_H_MULV_W = 476,
    3091             :     MADDR_Q_H_MADDR_Q_W = 477,
    3092             :     MADD_Q_H_MADD_Q_W   = 478,
    3093             :     MSUBR_Q_H_MSUBR_Q_W = 479,
    3094             :     MSUB_Q_H_MSUB_Q_W   = 480,
    3095             :     MULR_Q_H_MULR_Q_W   = 481,
    3096             :     MUL_Q_H_MUL_Q_W     = 482,
    3097             :     COPY_U_B_COPY_U_H_COPY_U_W  = 483,
    3098             :     COPY_S_B_COPY_S_D_COPY_S_H_COPY_S_W = 484,
    3099             :     ST_B_ST_D_ST_H_ST_W = 485,
    3100             :     LD_B_LD_D_LD_H_LD_W = 486,
    3101             :     EXTRV_RS_W  = 487,
    3102             :     EXTRV_R_W   = 488,
    3103             :     EXTRV_S_H   = 489,
    3104             :     EXTRV_W     = 490,
    3105             :     EXTR_RS_W   = 491,
    3106             :     EXTR_R_W    = 492,
    3107             :     EXTR_S_H    = 493,
    3108             :     EXTR_W      = 494,
    3109             :     INSV        = 495,
    3110             :     MTHLIP      = 496,
    3111             :     MTHI_DSP    = 497,
    3112             :     MTLO_DSP    = 498,
    3113             :     ABSQ_S_PH   = 499,
    3114             :     ABSQ_S_W    = 500,
    3115             :     ADDQ_PH     = 501,
    3116             :     ADDQ_S_PH   = 502,
    3117             :     ADDQ_S_W    = 503,
    3118             :     ADDSC       = 504,
    3119             :     ADDU_QB     = 505,
    3120             :     ADDU_S_QB   = 506,
    3121             :     ADDWC       = 507,
    3122             :     BITREV      = 508,
    3123             :     BPOSGE32    = 509,
    3124             :     CMPGU_EQ_QB = 510,
    3125             :     CMPGU_LE_QB = 511,
    3126             :     CMPGU_LT_QB = 512,
    3127             :     CMPU_EQ_QB  = 513,
    3128             :     CMPU_LE_QB  = 514,
    3129             :     CMPU_LT_QB  = 515,
    3130             :     CMP_EQ_PH   = 516,
    3131             :     CMP_LE_PH   = 517,
    3132             :     CMP_LT_PH   = 518,
    3133             :     DPAQ_SA_L_W = 519,
    3134             :     DPAQ_S_W_PH = 520,
    3135             :     DPAU_H_QBL  = 521,
    3136             :     DPAU_H_QBR  = 522,
    3137             :     DPSQ_SA_L_W = 523,
    3138             :     DPSQ_S_W_PH = 524,
    3139             :     DPSU_H_QBL  = 525,
    3140             :     DPSU_H_QBR  = 526,
    3141             :     EXTPDPV     = 527,
    3142             :     EXTPDP      = 528,
    3143             :     EXTPV       = 529,
    3144             :     EXTP        = 530,
    3145             :     LBUX        = 531,
    3146             :     LHX = 532,
    3147             :     LWX = 533,
    3148             :     MADDU_DSP   = 534,
    3149             :     MADD_DSP    = 535,
    3150             :     MAQ_SA_W_PHL        = 536,
    3151             :     MAQ_SA_W_PHR        = 537,
    3152             :     MAQ_S_W_PHL = 538,
    3153             :     MAQ_S_W_PHR = 539,
    3154             :     MFHI_DSP    = 540,
    3155             :     MFLO_DSP    = 541,
    3156             :     MODSUB      = 542,
    3157             :     MSUBU_DSP   = 543,
    3158             :     MSUB_DSP    = 544,
    3159             :     MULEQ_S_W_PHL       = 545,
    3160             :     MULEQ_S_W_PHR       = 546,
    3161             :     MULEU_S_PH_QBL      = 547,
    3162             :     MULEU_S_PH_QBR      = 548,
    3163             :     MULQ_RS_PH  = 549,
    3164             :     MULSAQ_S_W_PH       = 550,
    3165             :     MULTU_DSP   = 551,
    3166             :     MULT_DSP    = 552,
    3167             :     PACKRL_PH   = 553,
    3168             :     PICK_PH     = 554,
    3169             :     PICK_QB     = 555,
    3170             :     PRECEQU_PH_QBLA     = 556,
    3171             :     PRECEQU_PH_QBL      = 557,
    3172             :     PRECEQU_PH_QBRA     = 558,
    3173             :     PRECEQU_PH_QBR      = 559,
    3174             :     PRECEQ_W_PHL        = 560,
    3175             :     PRECEQ_W_PHR        = 561,
    3176             :     PRECEU_PH_QBLA      = 562,
    3177             :     PRECEU_PH_QBL       = 563,
    3178             :     PRECEU_PH_QBRA      = 564,
    3179             :     PRECEU_PH_QBR       = 565,
    3180             :     PRECRQU_S_QB_PH     = 566,
    3181             :     PRECRQ_PH_W = 567,
    3182             :     PRECRQ_QB_PH        = 568,
    3183             :     PRECRQ_RS_PH_W      = 569,
    3184             :     RADDU_W_QB  = 570,
    3185             :     RDDSP       = 571,
    3186             :     REPLV_PH    = 572,
    3187             :     REPLV_QB    = 573,
    3188             :     REPL_PH     = 574,
    3189             :     REPL_QB     = 575,
    3190             :     SHILOV      = 576,
    3191             :     SHILO       = 577,
    3192             :     SHLLV_PH    = 578,
    3193             :     SHLLV_QB    = 579,
    3194             :     SHLLV_S_PH  = 580,
    3195             :     SHLLV_S_W   = 581,
    3196             :     SHLL_PH     = 582,
    3197             :     SHLL_QB     = 583,
    3198             :     SHLL_S_PH   = 584,
    3199             :     SHLL_S_W    = 585,
    3200             :     SHRAV_PH    = 586,
    3201             :     SHRAV_R_PH  = 587,
    3202             :     SHRAV_R_W   = 588,
    3203             :     SHRA_PH     = 589,
    3204             :     SHRA_R_PH   = 590,
    3205             :     SHRA_R_W    = 591,
    3206             :     SHRLV_QB    = 592,
    3207             :     SHRL_QB     = 593,
    3208             :     SUBQ_PH     = 594,
    3209             :     SUBQ_S_PH   = 595,
    3210             :     SUBQ_S_W    = 596,
    3211             :     SUBU_QB     = 597,
    3212             :     SUBU_S_QB   = 598,
    3213             :     WRDSP       = 599,
    3214             :     ABSQ_S_QB   = 600,
    3215             :     ADDQH_PH    = 601,
    3216             :     ADDQH_R_PH  = 602,
    3217             :     ADDQH_R_W   = 603,
    3218             :     ADDQH_W     = 604,
    3219             :     ADDUH_QB    = 605,
    3220             :     ADDUH_R_QB  = 606,
    3221             :     ADDU_PH     = 607,
    3222             :     ADDU_S_PH   = 608,
    3223             :     APPEND      = 609,
    3224             :     BALIGN      = 610,
    3225             :     CMPGDU_EQ_QB        = 611,
    3226             :     CMPGDU_LE_QB        = 612,
    3227             :     CMPGDU_LT_QB        = 613,
    3228             :     DPA_W_PH    = 614,
    3229             :     DPAQX_SA_W_PH       = 615,
    3230             :     DPAQX_S_W_PH        = 616,
    3231             :     DPAX_W_PH   = 617,
    3232             :     DPS_W_PH    = 618,
    3233             :     DPSQX_S_W_PH        = 619,
    3234             :     DPSQX_SA_W_PH       = 620,
    3235             :     DPSX_W_PH   = 621,
    3236             :     MUL_PH      = 622,
    3237             :     MUL_S_PH    = 623,
    3238             :     MULQ_RS_W   = 624,
    3239             :     MULQ_S_PH   = 625,
    3240             :     MULQ_S_W    = 626,
    3241             :     MULSA_W_PH  = 627,
    3242             :     PRECR_QB_PH = 628,
    3243             :     PRECR_SRA_PH_W      = 629,
    3244             :     PRECR_SRA_R_PH_W    = 630,
    3245             :     PREPEND     = 631,
    3246             :     SHRA_QB     = 632,
    3247             :     SHRA_R_QB   = 633,
    3248             :     SHRAV_QB    = 634,
    3249             :     SHRAV_R_QB  = 635,
    3250             :     SHRL_PH     = 636,
    3251             :     SHRLV_PH    = 637,
    3252             :     SUBQH_PH    = 638,
    3253             :     SUBQH_R_PH  = 639,
    3254             :     SUBQH_W     = 640,
    3255             :     SUBQH_R_W   = 641,
    3256             :     SUBU_PH     = 642,
    3257             :     SUBU_S_PH   = 643,
    3258             :     SUBUH_QB    = 644,
    3259             :     SUBUH_R_QB  = 645,
    3260             :     ABSQ_S_PH_MM        = 646,
    3261             :     ABSQ_S_W_MM = 647,
    3262             :     ADDQ_PH_MM  = 648,
    3263             :     ADDQ_S_PH_MM        = 649,
    3264             :     ADDQ_S_W_MM = 650,
    3265             :     ADDSC_MM    = 651,
    3266             :     ADDU_QB_MM  = 652,
    3267             :     ADDU_S_QB_MM        = 653,
    3268             :     ADDWC_MM    = 654,
    3269             :     BITREV_MM   = 655,
    3270             :     BPOSGE32_MM = 656,
    3271             :     CMPGU_EQ_QB_MM      = 657,
    3272             :     CMPGU_LE_QB_MM      = 658,
    3273             :     CMPGU_LT_QB_MM      = 659,
    3274             :     CMPU_EQ_QB_MM       = 660,
    3275             :     CMPU_LE_QB_MM       = 661,
    3276             :     CMPU_LT_QB_MM       = 662,
    3277             :     CMP_EQ_PH_MM        = 663,
    3278             :     CMP_LE_PH_MM        = 664,
    3279             :     CMP_LT_PH_MM        = 665,
    3280             :     DPAQ_SA_L_W_MM      = 666,
    3281             :     DPAQ_S_W_PH_MM      = 667,
    3282             :     DPAU_H_QBL_MM       = 668,
    3283             :     DPAU_H_QBR_MM       = 669,
    3284             :     DPSQ_SA_L_W_MM      = 670,
    3285             :     DPSQ_S_W_PH_MM      = 671,
    3286             :     DPSU_H_QBL_MM       = 672,
    3287             :     DPSU_H_QBR_MM       = 673,
    3288             :     EXTPDPV_MM  = 674,
    3289             :     EXTPDP_MM   = 675,
    3290             :     EXTPV_MM    = 676,
    3291             :     EXTP_MM     = 677,
    3292             :     EXTRV_RS_W_MM       = 678,
    3293             :     EXTRV_R_W_MM        = 679,
    3294             :     EXTRV_S_H_MM        = 680,
    3295             :     EXTRV_W_MM  = 681,
    3296             :     EXTR_RS_W_MM        = 682,
    3297             :     EXTR_R_W_MM = 683,
    3298             :     EXTR_S_H_MM = 684,
    3299             :     EXTR_W_MM   = 685,
    3300             :     INSV_MM     = 686,
    3301             :     LBUX_MM     = 687,
    3302             :     LHX_MM      = 688,
    3303             :     LWX_MM      = 689,
    3304             :     MADDU_DSP_MM        = 690,
    3305             :     MADD_DSP_MM = 691,
    3306             :     MAQ_SA_W_PHL_MM     = 692,
    3307             :     MAQ_SA_W_PHR_MM     = 693,
    3308             :     MAQ_S_W_PHL_MM      = 694,
    3309             :     MAQ_S_W_PHR_MM      = 695,
    3310             :     MFHI_DSP_MM = 696,
    3311             :     MFLO_DSP_MM = 697,
    3312             :     MODSUB_MM   = 698,
    3313             :     MOVEP_MM    = 699,
    3314             :     MOVEP_MMR6  = 700,
    3315             :     MOVN_I_MM   = 701,
    3316             :     MOVZ_I_MM   = 702,
    3317             :     MSUBU_DSP_MM        = 703,
    3318             :     MSUB_DSP_MM = 704,
    3319             :     MTHI_DSP_MM = 705,
    3320             :     MTHLIP_MM   = 706,
    3321             :     MTLO_DSP_MM = 707,
    3322             :     MULEQ_S_W_PHL_MM    = 708,
    3323             :     MULEQ_S_W_PHR_MM    = 709,
    3324             :     MULEU_S_PH_QBL_MM   = 710,
    3325             :     MULEU_S_PH_QBR_MM   = 711,
    3326             :     MULQ_RS_PH_MM       = 712,
    3327             :     MULSAQ_S_W_PH_MM    = 713,
    3328             :     MULTU_DSP_MM        = 714,
    3329             :     MULT_DSP_MM = 715,
    3330             :     PACKRL_PH_MM        = 716,
    3331             :     PICK_PH_MM  = 717,
    3332             :     PICK_QB_MM  = 718,
    3333             :     PRECEQU_PH_QBLA_MM  = 719,
    3334             :     PRECEQU_PH_QBL_MM   = 720,
    3335             :     PRECEQU_PH_QBRA_MM  = 721,
    3336             :     PRECEQU_PH_QBR_MM   = 722,
    3337             :     PRECEQ_W_PHL_MM     = 723,
    3338             :     PRECEQ_W_PHR_MM     = 724,
    3339             :     PRECEU_PH_QBLA_MM   = 725,
    3340             :     PRECEU_PH_QBL_MM    = 726,
    3341             :     PRECEU_PH_QBRA_MM   = 727,
    3342             :     PRECEU_PH_QBR_MM    = 728,
    3343             :     PRECRQU_S_QB_PH_MM  = 729,
    3344             :     PRECRQ_PH_W_MM      = 730,
    3345             :     PRECRQ_QB_PH_MM     = 731,
    3346             :     PRECRQ_RS_PH_W_MM   = 732,
    3347             :     RADDU_W_QB_MM       = 733,
    3348             :     RDDSP_MM    = 734,
    3349             :     REPLV_PH_MM = 735,
    3350             :     REPLV_QB_MM = 736,
    3351             :     REPL_PH_MM  = 737,
    3352             :     REPL_QB_MM  = 738,
    3353             :     SHILOV_MM   = 739,
    3354             :     SHILO_MM    = 740,
    3355             :     SHLLV_PH_MM = 741,
    3356             :     SHLLV_QB_MM = 742,
    3357             :     SHLLV_S_PH_MM       = 743,
    3358             :     SHLLV_S_W_MM        = 744,
    3359             :     SHLL_PH_MM  = 745,
    3360             :     SHLL_QB_MM  = 746,
    3361             :     SHLL_S_PH_MM        = 747,
    3362             :     SHLL_S_W_MM = 748,
    3363             :     SHRAV_PH_MM = 749,
    3364             :     SHRAV_R_PH_MM       = 750,
    3365             :     SHRAV_R_W_MM        = 751,
    3366             :     SHRA_PH_MM  = 752,
    3367             :     SHRA_R_PH_MM        = 753,
    3368             :     SHRA_R_W_MM = 754,
    3369             :     SHRLV_QB_MM = 755,
    3370             :     SHRL_QB_MM  = 756,
    3371             :     SUBQ_PH_MM  = 757,
    3372             :     SUBQ_S_PH_MM        = 758,
    3373             :     SUBQ_S_W_MM = 759,
    3374             :     SUBU_QB_MM  = 760,
    3375             :     SUBU_S_QB_MM        = 761,
    3376             :     WRDSP_MM    = 762,
    3377             :     ABSQ_S_QB_MMR2      = 763,
    3378             :     ADDQH_PH_MMR2       = 764,
    3379             :     ADDQH_R_PH_MMR2     = 765,
    3380             :     ADDQH_R_W_MMR2      = 766,
    3381             :     ADDQH_W_MMR2        = 767,
    3382             :     ADDUH_QB_MMR2       = 768,
    3383             :     ADDUH_R_QB_MMR2     = 769,
    3384             :     ADDU_PH_MMR2        = 770,
    3385             :     ADDU_S_PH_MMR2      = 771,
    3386             :     APPEND_MMR2 = 772,
    3387             :     BALIGN_MMR2 = 773,
    3388             :     CMPGDU_EQ_QB_MMR2   = 774,
    3389             :     CMPGDU_LE_QB_MMR2   = 775,
    3390             :     CMPGDU_LT_QB_MMR2   = 776,
    3391             :     DPA_W_PH_MMR2       = 777,
    3392             :     DPAQX_SA_W_PH_MMR2  = 778,
    3393             :     DPAQX_S_W_PH_MMR2   = 779,
    3394             :     DPAX_W_PH_MMR2      = 780,
    3395             :     DPS_W_PH_MMR2       = 781,
    3396             :     DPSQX_S_W_PH_MMR2   = 782,
    3397             :     DPSQX_SA_W_PH_MMR2  = 783,
    3398             :     DPSX_W_PH_MMR2      = 784,
    3399             :     MUL_PH_MMR2 = 785,
    3400             :     MUL_S_PH_MMR2       = 786,
    3401             :     MULQ_RS_W_MMR2      = 787,
    3402             :     MULQ_S_PH_MMR2      = 788,
    3403             :     MULQ_S_W_MMR2       = 789,
    3404             :     MULSA_W_PH_MMR2     = 790,
    3405             :     PRECR_QB_PH_MMR2    = 791,
    3406             :     PRECR_SRA_PH_W_MMR2 = 792,
    3407             :     PRECR_SRA_R_PH_W_MMR2       = 793,
    3408             :     PREPEND_MMR2        = 794,
    3409             :     SHRA_QB_MMR2        = 795,
    3410             :     SHRA_R_QB_MMR2      = 796,
    3411             :     SHRAV_QB_MMR2       = 797,
    3412             :     SHRAV_R_QB_MMR2     = 798,
    3413             :     SHRL_PH_MMR2        = 799,
    3414             :     SHRLV_PH_MMR2       = 800,
    3415             :     SUBQH_PH_MMR2       = 801,
    3416             :     SUBQH_R_PH_MMR2     = 802,
    3417             :     SUBQH_W_MMR2        = 803,
    3418             :     SUBQH_R_W_MMR2      = 804,
    3419             :     SUBU_PH_MMR2        = 805,
    3420             :     SUBU_S_PH_MMR2      = 806,
    3421             :     SUBUH_QB_MMR2       = 807,
    3422             :     SUBUH_R_QB_MMR2     = 808,
    3423             :     BPOSGE32C_MMR3      = 809,
    3424             :     SCHED_LIST_END = 810
    3425             :   };
    3426             : } // end Sched namespace
    3427             : } // end Mips namespace
    3428             : } // end llvm namespace
    3429             : #endif // GET_INSTRINFO_SCHED_ENUM
    3430             : 
    3431             : #ifdef GET_INSTRINFO_MC_DESC
    3432             : #undef GET_INSTRINFO_MC_DESC
    3433             : namespace llvm {
    3434             : 
    3435             : static const MCPhysReg ImplicitList1[] = { Mips::DSPOutFlag20, 0 };
    3436             : static const MCPhysReg ImplicitList2[] = { Mips::DSPCarry, 0 };
    3437             : static const MCPhysReg ImplicitList3[] = { Mips::SP, 0 };
    3438             : static const MCPhysReg ImplicitList4[] = { Mips::AT, 0 };
    3439             : static const MCPhysReg ImplicitList5[] = { Mips::RA, 0 };
    3440             : static const MCPhysReg ImplicitList6[] = { Mips::DSPPos, 0 };
    3441             : static const MCPhysReg ImplicitList7[] = { Mips::T8, 0 };
    3442             : static const MCPhysReg ImplicitList8[] = { Mips::DSPCCond, 0 };
    3443             : static const MCPhysReg ImplicitList9[] = { Mips::HI0, Mips::LO0, Mips::P0, Mips::P1, Mips::P2, 0 };
    3444             : static const MCPhysReg ImplicitList10[] = { Mips::HI0_64, Mips::LO0_64, 0 };
    3445             : static const MCPhysReg ImplicitList11[] = { Mips::DSPOutFlag16_19, 0 };
    3446             : static const MCPhysReg ImplicitList12[] = { Mips::HI0, Mips::LO0, 0 };
    3447             : static const MCPhysReg ImplicitList13[] = { Mips::DSPEFI, 0 };
    3448             : static const MCPhysReg ImplicitList14[] = { Mips::DSPPos, Mips::DSPEFI, 0 };
    3449             : static const MCPhysReg ImplicitList15[] = { Mips::DSPOutFlag23, 0 };
    3450             : static const MCPhysReg ImplicitList16[] = { Mips::FCC0, 0 };
    3451             : static const MCPhysReg ImplicitList17[] = { Mips::DSPPos, Mips::DSPSCount, 0 };
    3452             : static const MCPhysReg ImplicitList18[] = { Mips::AC0, 0 };
    3453             : static const MCPhysReg ImplicitList19[] = { Mips::AC0_64, 0 };
    3454             : static const MCPhysReg ImplicitList20[] = { Mips::V0, Mips::V1, 0 };
    3455             : static const MCPhysReg ImplicitList21[] = { Mips::HI0, 0 };
    3456             : static const MCPhysReg ImplicitList22[] = { Mips::HI0_64, 0 };
    3457             : static const MCPhysReg ImplicitList23[] = { Mips::LO0, 0 };
    3458             : static const MCPhysReg ImplicitList24[] = { Mips::LO0_64, 0 };
    3459             : static const MCPhysReg ImplicitList25[] = { Mips::MPL0, Mips::P0, Mips::P1, Mips::P2, 0 };
    3460             : static const MCPhysReg ImplicitList26[] = { Mips::MPL1, Mips::P0, Mips::P1, Mips::P2, 0 };
    3461             : static const MCPhysReg ImplicitList27[] = { Mips::MPL2, Mips::P0, Mips::P1, Mips::P2, 0 };
    3462             : static const MCPhysReg ImplicitList28[] = { Mips::P0, 0 };
    3463             : static const MCPhysReg ImplicitList29[] = { Mips::P1, 0 };
    3464             : static const MCPhysReg ImplicitList30[] = { Mips::P2, 0 };
    3465             : static const MCPhysReg ImplicitList31[] = { Mips::DSPOutFlag21, 0 };
    3466             : static const MCPhysReg ImplicitList32[] = { Mips::DSPOutFlag22, 0 };
    3467             : static const MCPhysReg ImplicitList33[] = { Mips::P0, Mips::P1, Mips::P2, 0 };
    3468             : static const MCPhysReg ImplicitList34[] = { Mips::MPL1, Mips::MPL2, Mips::P0, Mips::P1, Mips::P2, 0 };
    3469             : 
    3470             : static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3471             : static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3472             : static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3473             : static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3474             : static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3475             : static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3476             : static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3477             : static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3478             : static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
    3479             : static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3480             : static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3481             : static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
    3482             : static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
    3483             : static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3484             : static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3485             : static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
    3486             : static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3487             : static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
    3488             : static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
    3489             : static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
    3490             : static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
    3491             : static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
    3492             : static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
    3493             : static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
    3494             : static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
    3495             : static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3496             : static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
    3497             : static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
    3498             : static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
    3499             : static const MCOperandInfo OperandInfo31[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3500             : static const MCOperandInfo OperandInfo32[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3501             : static const MCOperandInfo OperandInfo33[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3502             : static const MCOperandInfo OperandInfo34[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3503             : static const MCOperandInfo OperandInfo35[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3504             : static const MCOperandInfo OperandInfo36[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3505             : static const MCOperandInfo OperandInfo37[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3506             : static const MCOperandInfo OperandInfo38[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3507             : static const MCOperandInfo OperandInfo39[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3508             : static const MCOperandInfo OperandInfo40[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3509             : static const MCOperandInfo OperandInfo41[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3510             : static const MCOperandInfo OperandInfo42[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3511             : static const MCOperandInfo OperandInfo43[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3512             : static const MCOperandInfo OperandInfo44[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3513             : static const MCOperandInfo OperandInfo45[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3514             : static const MCOperandInfo OperandInfo46[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3515             : static const MCOperandInfo OperandInfo47[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3516             : static const MCOperandInfo OperandInfo48[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3517             : static const MCOperandInfo OperandInfo49[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3518             : static const MCOperandInfo OperandInfo50[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
    3519             : static const MCOperandInfo OperandInfo51[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3520             : static const MCOperandInfo OperandInfo52[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3521             : static const MCOperandInfo OperandInfo53[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
    3522             : static const MCOperandInfo OperandInfo54[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3523             : static const MCOperandInfo OperandInfo55[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3524             : static const MCOperandInfo OperandInfo56[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3525             : static const MCOperandInfo OperandInfo57[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3526             : static const MCOperandInfo OperandInfo58[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3527             : static const MCOperandInfo OperandInfo59[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3528             : static const MCOperandInfo OperandInfo60[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsPlusSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3529             : static const MCOperandInfo OperandInfo61[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3530             : static const MCOperandInfo OperandInfo62[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3531             : static const MCOperandInfo OperandInfo63[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
    3532             : static const MCOperandInfo OperandInfo64[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
    3533             : static const MCOperandInfo OperandInfo65[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
    3534             : static const MCOperandInfo OperandInfo66[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
    3535             : static const MCOperandInfo OperandInfo67[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
    3536             : static const MCOperandInfo OperandInfo68[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
    3537             : static const MCOperandInfo OperandInfo69[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
    3538             : static const MCOperandInfo OperandInfo70[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
    3539             : static const MCOperandInfo OperandInfo71[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
    3540             : static const MCOperandInfo OperandInfo72[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
    3541             : static const MCOperandInfo OperandInfo73[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
    3542             : static const MCOperandInfo OperandInfo74[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3543             : static const MCOperandInfo OperandInfo75[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3544             : static const MCOperandInfo OperandInfo76[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3545             : static const MCOperandInfo OperandInfo77[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3546             : static const MCOperandInfo OperandInfo78[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3547             : static const MCOperandInfo OperandInfo79[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3548             : static const MCOperandInfo OperandInfo80[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3549             : static const MCOperandInfo OperandInfo81[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3550             : static const MCOperandInfo OperandInfo82[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
    3551             : static const MCOperandInfo OperandInfo83[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
    3552             : static const MCOperandInfo OperandInfo84[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
    3553             : static const MCOperandInfo OperandInfo85[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
    3554             : static const MCOperandInfo OperandInfo86[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3555             : static const MCOperandInfo OperandInfo87[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
    3556             : static const MCOperandInfo OperandInfo88[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
    3557             : static const MCOperandInfo OperandInfo89[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
    3558             : static const MCOperandInfo OperandInfo90[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3559             : static const MCOperandInfo OperandInfo91[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3560             : static const MCOperandInfo OperandInfo92[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3561             : static const MCOperandInfo OperandInfo93[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3562             : static const MCOperandInfo OperandInfo94[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3563             : static const MCOperandInfo OperandInfo95[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3564             : static const MCOperandInfo OperandInfo96[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3565             : static const MCOperandInfo OperandInfo97[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3566             : static const MCOperandInfo OperandInfo98[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3567             : static const MCOperandInfo OperandInfo99[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3568             : static const MCOperandInfo OperandInfo100[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3569             : static const MCOperandInfo OperandInfo101[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3570             : static const MCOperandInfo OperandInfo102[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3571             : static const MCOperandInfo OperandInfo103[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3572             : static const MCOperandInfo OperandInfo104[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3573             : static const MCOperandInfo OperandInfo105[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3574             : static const MCOperandInfo OperandInfo106[] = { { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3575             : static const MCOperandInfo OperandInfo107[] = { { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3576             : static const MCOperandInfo OperandInfo108[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3577             : static const MCOperandInfo OperandInfo109[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3578             : static const MCOperandInfo OperandInfo110[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3579             : static const MCOperandInfo OperandInfo111[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3580             : static const MCOperandInfo OperandInfo112[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3581             : static const MCOperandInfo OperandInfo113[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3582             : static const MCOperandInfo OperandInfo114[] = { { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3583             : static const MCOperandInfo OperandInfo115[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3584             : static const MCOperandInfo OperandInfo116[] = { { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3585             : static const MCOperandInfo OperandInfo117[] = { { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3586             : static const MCOperandInfo OperandInfo118[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3587             : static const MCOperandInfo OperandInfo119[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3588             : static const MCOperandInfo OperandInfo120[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3589             : static const MCOperandInfo OperandInfo121[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3590             : static const MCOperandInfo OperandInfo122[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3591             : static const MCOperandInfo OperandInfo123[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3592             : static const MCOperandInfo OperandInfo124[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3593             : static const MCOperandInfo OperandInfo125[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3594             : static const MCOperandInfo OperandInfo126[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
    3595             : static const MCOperandInfo OperandInfo127[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3596             : static const MCOperandInfo OperandInfo128[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3597             : static const MCOperandInfo OperandInfo129[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3598             : static const MCOperandInfo OperandInfo130[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3599             : static const MCOperandInfo OperandInfo131[] = { { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3600             : static const MCOperandInfo OperandInfo132[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3601             : static const MCOperandInfo OperandInfo133[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3602             : static const MCOperandInfo OperandInfo134[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3603             : static const MCOperandInfo OperandInfo135[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3604             : static const MCOperandInfo OperandInfo136[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3605             : static const MCOperandInfo OperandInfo137[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3606             : static const MCOperandInfo OperandInfo138[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3607             : static const MCOperandInfo OperandInfo139[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3608             : static const MCOperandInfo OperandInfo140[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
    3609             : static const MCOperandInfo OperandInfo141[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3610             : static const MCOperandInfo OperandInfo142[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3611             : static const MCOperandInfo OperandInfo143[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3612             : static const MCOperandInfo OperandInfo144[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3613             : static const MCOperandInfo OperandInfo145[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3614             : static const MCOperandInfo OperandInfo146[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3615             : static const MCOperandInfo OperandInfo147[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3616             : static const MCOperandInfo OperandInfo148[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3617             : static const MCOperandInfo OperandInfo149[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3618             : static const MCOperandInfo OperandInfo150[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3619             : static const MCOperandInfo OperandInfo151[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3620             : static const MCOperandInfo OperandInfo152[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3621             : static const MCOperandInfo OperandInfo153[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3622             : static const MCOperandInfo OperandInfo154[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3623             : static const MCOperandInfo OperandInfo155[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3624             : static const MCOperandInfo OperandInfo156[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3625             : static const MCOperandInfo OperandInfo157[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3626             : static const MCOperandInfo OperandInfo158[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3627             : static const MCOperandInfo OperandInfo159[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3628             : static const MCOperandInfo OperandInfo160[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3629             : static const MCOperandInfo OperandInfo161[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3630             : static const MCOperandInfo OperandInfo162[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3631             : static const MCOperandInfo OperandInfo163[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3632             : static const MCOperandInfo OperandInfo164[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3633             : static const MCOperandInfo OperandInfo165[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3634             : static const MCOperandInfo OperandInfo166[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3635             : static const MCOperandInfo OperandInfo167[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
    3636             : static const MCOperandInfo OperandInfo168[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3637             : static const MCOperandInfo OperandInfo169[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3638             : static const MCOperandInfo OperandInfo170[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3639             : static const MCOperandInfo OperandInfo171[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3640             : static const MCOperandInfo OperandInfo172[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3641             : static const MCOperandInfo OperandInfo173[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3642             : static const MCOperandInfo OperandInfo174[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3643             : static const MCOperandInfo OperandInfo175[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3644             : static const MCOperandInfo OperandInfo176[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3645             : static const MCOperandInfo OperandInfo177[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3646             : static const MCOperandInfo OperandInfo178[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3647             : static const MCOperandInfo OperandInfo179[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3648             : static const MCOperandInfo OperandInfo180[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3649             : static const MCOperandInfo OperandInfo181[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3650             : static const MCOperandInfo OperandInfo182[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3651             : static const MCOperandInfo OperandInfo183[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3652             : static const MCOperandInfo OperandInfo184[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3653             : static const MCOperandInfo OperandInfo185[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3654             : static const MCOperandInfo OperandInfo186[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3655             : static const MCOperandInfo OperandInfo187[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3656             : static const MCOperandInfo OperandInfo188[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3657             : static const MCOperandInfo OperandInfo189[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3658             : static const MCOperandInfo OperandInfo190[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3659             : static const MCOperandInfo OperandInfo191[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3660             : static const MCOperandInfo OperandInfo192[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3661             : static const MCOperandInfo OperandInfo193[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
    3662             : static const MCOperandInfo OperandInfo194[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
    3663             : static const MCOperandInfo OperandInfo195[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
    3664             : static const MCOperandInfo OperandInfo196[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
    3665             : static const MCOperandInfo OperandInfo197[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
    3666             : static const MCOperandInfo OperandInfo198[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
    3667             : static const MCOperandInfo OperandInfo199[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
    3668             : static const MCOperandInfo OperandInfo200[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
    3669             : static const MCOperandInfo OperandInfo201[] = { { Mips::COP3RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
    3670             : static const MCOperandInfo OperandInfo202[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3671             : static const MCOperandInfo OperandInfo203[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3672             : static const MCOperandInfo OperandInfo204[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3673             : static const MCOperandInfo OperandInfo205[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3674             : static const MCOperandInfo OperandInfo206[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
    3675             : static const MCOperandInfo OperandInfo207[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
    3676             : static const MCOperandInfo OperandInfo208[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
    3677             : static const MCOperandInfo OperandInfo209[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
    3678             : static const MCOperandInfo OperandInfo210[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
    3679             : static const MCOperandInfo OperandInfo211[] = { { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
    3680             : static const MCOperandInfo OperandInfo212[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
    3681             : static const MCOperandInfo OperandInfo213[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
    3682             : static const MCOperandInfo OperandInfo214[] = { { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
    3683             : static const MCOperandInfo OperandInfo215[] = { { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
    3684             : static const MCOperandInfo OperandInfo216[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
    3685             : static const MCOperandInfo OperandInfo217[] = { { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
    3686             : static const MCOperandInfo OperandInfo218[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
    3687             : static const MCOperandInfo OperandInfo219[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
    3688             : static const MCOperandInfo OperandInfo220[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
    3689             : static const MCOperandInfo OperandInfo221[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
    3690             : static const MCOperandInfo OperandInfo222[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
    3691             : static const MCOperandInfo OperandInfo223[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 3, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
    3692             : static const MCOperandInfo OperandInfo224[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
    3693             : static const MCOperandInfo OperandInfo225[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 2, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
    3694             : static const MCOperandInfo OperandInfo226[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
    3695             : static const MCOperandInfo OperandInfo227[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
    3696             : static const MCOperandInfo OperandInfo228[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 2, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
    3697             : static const MCOperandInfo OperandInfo229[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
    3698             : static const MCOperandInfo OperandInfo230[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3699             : static const MCOperandInfo OperandInfo231[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3700             : static const MCOperandInfo OperandInfo232[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3701             : static const MCOperandInfo OperandInfo233[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3702             : static const MCOperandInfo OperandInfo234[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3703             : static const MCOperandInfo OperandInfo235[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3704             : static const MCOperandInfo OperandInfo236[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3705             : static const MCOperandInfo OperandInfo237[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3706             : static const MCOperandInfo OperandInfo238[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3707             : static const MCOperandInfo OperandInfo239[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3708             : static const MCOperandInfo OperandInfo240[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3709             : static const MCOperandInfo OperandInfo241[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3710             : static const MCOperandInfo OperandInfo242[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3711             : static const MCOperandInfo OperandInfo243[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3712             : static const MCOperandInfo OperandInfo244[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3713             : static const MCOperandInfo OperandInfo245[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3714             : static const MCOperandInfo OperandInfo246[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3715             : static const MCOperandInfo OperandInfo247[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3716             : static const MCOperandInfo OperandInfo248[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3717             : static const MCOperandInfo OperandInfo249[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3718             : static const MCOperandInfo OperandInfo250[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3719             : static const MCOperandInfo OperandInfo251[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
    3720             : static const MCOperandInfo OperandInfo252[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
    3721             : static const MCOperandInfo OperandInfo253[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
    3722             : static const MCOperandInfo OperandInfo254[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
    3723             : static const MCOperandInfo OperandInfo255[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
    3724             : static const MCOperandInfo OperandInfo256[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
    3725             : static const MCOperandInfo OperandInfo257[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
    3726             : static const MCOperandInfo OperandInfo258[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
    3727             : static const MCOperandInfo OperandInfo259[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
    3728             : static const MCOperandInfo OperandInfo260[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
    3729             : static const MCOperandInfo OperandInfo261[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
    3730             : static const MCOperandInfo OperandInfo262[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
    3731             : static const MCOperandInfo OperandInfo263[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
    3732             : static const MCOperandInfo OperandInfo264[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
    3733             : static const MCOperandInfo OperandInfo265[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3734             : static const MCOperandInfo OperandInfo266[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3735             : static const MCOperandInfo OperandInfo267[] = { { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3736             : static const MCOperandInfo OperandInfo268[] = { { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3737             : static const MCOperandInfo OperandInfo269[] = { { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3738             : static const MCOperandInfo OperandInfo270[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3739             : static const MCOperandInfo OperandInfo271[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3740             : static const MCOperandInfo OperandInfo272[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3741             : static const MCOperandInfo OperandInfo273[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3742             : static const MCOperandInfo OperandInfo274[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3743             : static const MCOperandInfo OperandInfo275[] = { { Mips::HI32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3744             : static const MCOperandInfo OperandInfo276[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
    3745             : static const MCOperandInfo OperandInfo277[] = { { Mips::LO32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3746             : static const MCOperandInfo OperandInfo278[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3747             : static const MCOperandInfo OperandInfo279[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3748             : static const MCOperandInfo OperandInfo280[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3749             : static const MCOperandInfo OperandInfo281[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3750             : static const MCOperandInfo OperandInfo282[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3751             : static const MCOperandInfo OperandInfo283[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3752             : static const MCOperandInfo OperandInfo284[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3753             : static const MCOperandInfo OperandInfo285[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3754             : static const MCOperandInfo OperandInfo286[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
    3755             : static const MCOperandInfo OperandInfo287[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3756             : static const MCOperandInfo OperandInfo288[] = { { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3757             : static const MCOperandInfo OperandInfo289[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3758             : static const MCOperandInfo OperandInfo290[] = { { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3759             : static const MCOperandInfo OperandInfo291[] = { { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
    3760             : static const MCOperandInfo OperandInfo292[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3761             : static const MCOperandInfo OperandInfo293[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3762             : static const MCOperandInfo OperandInfo294[] = { { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3763             : static const MCOperandInfo OperandInfo295[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3764             : static const MCOperandInfo OperandInfo296[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3765             : static const MCOperandInfo OperandInfo297[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3766             : static const MCOperandInfo OperandInfo298[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3767             : static const MCOperandInfo OperandInfo299[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3768             : static const MCOperandInfo OperandInfo300[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3769             : static const MCOperandInfo OperandInfo301[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3770             : static const MCOperandInfo OperandInfo302[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3771             : static const MCOperandInfo OperandInfo303[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3772             : static const MCOperandInfo OperandInfo304[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3773             : static const MCOperandInfo OperandInfo305[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3774             : static const MCOperandInfo OperandInfo306[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3775             : static const MCOperandInfo OperandInfo307[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3776             : static const MCOperandInfo OperandInfo308[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3777             : static const MCOperandInfo OperandInfo309[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3778             : static const MCOperandInfo OperandInfo310[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3779             : static const MCOperandInfo OperandInfo311[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3780             : static const MCOperandInfo OperandInfo312[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3781             : static const MCOperandInfo OperandInfo313[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3782             : static const MCOperandInfo OperandInfo314[] = { { Mips::GPRMM16ZeroRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
    3783             : static const MCOperandInfo OperandInfo315[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
    3784             : static const MCOperandInfo OperandInfo316[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
    3785             : static const MCOperandInfo OperandInfo317[] = { { Mips::GPR32NONZERORegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3786             : static const MCOperandInfo OperandInfo318[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3787             : static const MCOperandInfo OperandInfo319[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
    3788             : static const MCOperandInfo OperandInfo320[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3789             : static const MCOperandInfo OperandInfo321[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3790             : static const MCOperandInfo OperandInfo322[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3791             : static const MCOperandInfo OperandInfo323[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3792             : static const MCOperandInfo OperandInfo324[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3793             : static const MCOperandInfo OperandInfo325[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3794             : static const MCOperandInfo OperandInfo326[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3795             : static const MCOperandInfo OperandInfo327[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3796             : static const MCOperandInfo OperandInfo328[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3797             : static const MCOperandInfo OperandInfo329[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3798             : static const MCOperandInfo OperandInfo330[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3799             : static const MCOperandInfo OperandInfo331[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3800             : static const MCOperandInfo OperandInfo332[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3801             : static const MCOperandInfo OperandInfo333[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3802             : static const MCOperandInfo OperandInfo334[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3803             : static const MCOperandInfo OperandInfo335[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3804             : static const MCOperandInfo OperandInfo336[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
    3805             : static const MCOperandInfo OperandInfo337[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
    3806             : static const MCOperandInfo OperandInfo338[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3807             : static const MCOperandInfo OperandInfo339[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3808             : static const MCOperandInfo OperandInfo340[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3809             : static const MCOperandInfo OperandInfo341[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3810             : 
    3811             : extern const MCInstrDesc MipsInsts[] = {
    3812             :   { 0,  1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #0 = PHI
    3813             :   { 1,  0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
    3814             :   { 2,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #2 = CFI_INSTRUCTION
    3815             :   { 3,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #3 = EH_LABEL
    3816             :   { 4,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #4 = GC_LABEL
    3817             :   { 5,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #5 = ANNOTATION_LABEL
    3818             :   { 6,  0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #6 = KILL
    3819             :   { 7,  3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #7 = EXTRACT_SUBREG
    3820             :   { 8,  4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #8 = INSERT_SUBREG
    3821             :   { 9,  1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #9 = IMPLICIT_DEF
    3822             :   { 10, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #10 = SUBREG_TO_REG
    3823             :   { 11, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #11 = COPY_TO_REGCLASS
    3824             :   { 12, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #12 = DBG_VALUE
    3825             :   { 13, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #13 = DBG_LABEL
    3826             :   { 14, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #14 = REG_SEQUENCE
    3827             :   { 15, 2,      1,      0,      358,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #15 = COPY
    3828             :   { 16, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #16 = BUNDLE
    3829             :   { 17, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #17 = LIFETIME_START
    3830             :   { 18, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #18 = LIFETIME_END
    3831             :   { 19, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #19 = STACKMAP
    3832             :   { 20, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #20 = FENTRY_CALL
    3833             :   { 21, 6,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #21 = PATCHPOINT
    3834             :   { 22, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #22 = LOAD_STACK_GUARD
    3835             :   { 23, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #23 = STATEPOINT
    3836             :   { 24, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #24 = LOCAL_ESCAPE
    3837             :   { 25, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #25 = FAULTING_OP
    3838             :   { 26, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #26 = PATCHABLE_OP
    3839             :   { 27, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #27 = PATCHABLE_FUNCTION_ENTER
    3840             :   { 28, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #28 = PATCHABLE_RET
    3841             :   { 29, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #29 = PATCHABLE_FUNCTION_EXIT
    3842             :   { 30, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #30 = PATCHABLE_TAIL_CALL
    3843             :   { 31, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #31 = PATCHABLE_EVENT_CALL
    3844             :   { 32, 3,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #32 = PATCHABLE_TYPED_EVENT_CALL
    3845             :   { 33, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #33 = ICALL_BRANCH_FUNNEL
    3846             :   { 34, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #34 = G_ADD
    3847             :   { 35, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #35 = G_SUB
    3848             :   { 36, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #36 = G_MUL
    3849             :   { 37, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #37 = G_SDIV
    3850             :   { 38, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #38 = G_UDIV
    3851             :   { 39, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #39 = G_SREM
    3852             :   { 40, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #40 = G_UREM
    3853             :   { 41, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #41 = G_AND
    3854             :   { 42, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #42 = G_OR
    3855             :   { 43, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #43 = G_XOR
    3856             :   { 44, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #44 = G_IMPLICIT_DEF
    3857             :   { 45, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #45 = G_PHI
    3858             :   { 46, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #46 = G_FRAME_INDEX
    3859             :   { 47, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #47 = G_GLOBAL_VALUE
    3860             :   { 48, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #48 = G_EXTRACT
    3861             :   { 49, 2,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #49 = G_UNMERGE_VALUES
    3862             :   { 50, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #50 = G_INSERT
    3863             :   { 51, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #51 = G_MERGE_VALUES
    3864             :   { 52, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #52 = G_PTRTOINT
    3865             :   { 53, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #53 = G_INTTOPTR
    3866             :   { 54, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #54 = G_BITCAST
    3867             :   { 55, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #55 = G_LOAD
    3868             :   { 56, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #56 = G_SEXTLOAD
    3869             :   { 57, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #57 = G_ZEXTLOAD
    3870             :   { 58, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #58 = G_STORE
    3871             :   { 59, 5,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #59 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
    3872             :   { 60, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #60 = G_ATOMIC_CMPXCHG
    3873             :   { 61, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #61 = G_ATOMICRMW_XCHG
    3874             :   { 62, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #62 = G_ATOMICRMW_ADD
    3875             :   { 63, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #63 = G_ATOMICRMW_SUB
    3876             :   { 64, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #64 = G_ATOMICRMW_AND
    3877             :   { 65, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #65 = G_ATOMICRMW_NAND
    3878             :   { 66, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #66 = G_ATOMICRMW_OR
    3879             :   { 67, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #67 = G_ATOMICRMW_XOR
    3880             :   { 68, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #68 = G_ATOMICRMW_MAX
    3881             :   { 69, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #69 = G_ATOMICRMW_MIN
    3882             :   { 70, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #70 = G_ATOMICRMW_UMAX
    3883             :   { 71, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #71 = G_ATOMICRMW_UMIN
    3884             :   { 72, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #72 = G_BRCOND
    3885             :   { 73, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #73 = G_BRINDIRECT
    3886             :   { 74, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #74 = G_INTRINSIC
    3887             :   { 75, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #75 = G_INTRINSIC_W_SIDE_EFFECTS
    3888             :   { 76, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #76 = G_ANYEXT
    3889             :   { 77, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #77 = G_TRUNC
    3890             :   { 78, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #78 = G_CONSTANT
    3891             :   { 79, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #79 = G_FCONSTANT
    3892             :   { 80, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #80 = G_VASTART
    3893             :   { 81, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #81 = G_VAARG
    3894             :   { 82, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #82 = G_SEXT
    3895             :   { 83, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #83 = G_ZEXT
    3896             :   { 84, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #84 = G_SHL
    3897             :   { 85, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #85 = G_LSHR
    3898             :   { 86, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #86 = G_ASHR
    3899             :   { 87, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #87 = G_ICMP
    3900             :   { 88, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #88 = G_FCMP
    3901             :   { 89, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #89 = G_SELECT
    3902             :   { 90, 5,      2,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #90 = G_UADDE
    3903             :   { 91, 5,      2,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #91 = G_USUBE
    3904             :   { 92, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #92 = G_SADDO
    3905             :   { 93, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #93 = G_SSUBO
    3906             :   { 94, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #94 = G_UMULO
    3907             :   { 95, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #95 = G_SMULO
    3908             :   { 96, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #96 = G_UMULH
    3909             :   { 97, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #97 = G_SMULH
    3910             :   { 98, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #98 = G_FADD
    3911             :   { 99, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #99 = G_FSUB
    3912             :   { 100,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #100 = G_FMUL
    3913             :   { 101,        4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #101 = G_FMA
    3914             :   { 102,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #102 = G_FDIV
    3915             :   { 103,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #103 = G_FREM
    3916             :   { 104,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #104 = G_FPOW
    3917             :   { 105,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #105 = G_FEXP
    3918             :   { 106,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #106 = G_FEXP2
    3919             :   { 107,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #107 = G_FLOG
    3920             :   { 108,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #108 = G_FLOG2
    3921             :   { 109,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #109 = G_FNEG
    3922             :   { 110,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #110 = G_FPEXT
    3923             :   { 111,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #111 = G_FPTRUNC
    3924             :   { 112,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #112 = G_FPTOSI
    3925             :   { 113,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #113 = G_FPTOUI
    3926             :   { 114,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #114 = G_SITOFP
    3927             :   { 115,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #115 = G_UITOFP
    3928             :   { 116,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #116 = G_FABS
    3929             :   { 117,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #117 = G_GEP
    3930             :   { 118,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #118 = G_PTR_MASK
    3931             :   { 119,        1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #119 = G_BR
    3932             :   { 120,        4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #120 = G_INSERT_VECTOR_ELT
    3933             :   { 121,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #121 = G_EXTRACT_VECTOR_ELT
    3934             :   { 122,        4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #122 = G_SHUFFLE_VECTOR
    3935             :   { 123,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #123 = G_BSWAP
    3936             :   { 124,        2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #124 = ABSMacro
    3937             :   { 125,        2,      1,      4,      499,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #125 = ABSQ_S_PH
    3938             :   { 126,        2,      1,      4,      646,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #126 = ABSQ_S_PH_MM
    3939             :   { 127,        2,      1,      4,      600,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #127 = ABSQ_S_QB
    3940             :   { 128,        2,      1,      4,      763,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #128 = ABSQ_S_QB_MMR2
    3941             :   { 129,        2,      1,      4,      500,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #129 = ABSQ_S_W
    3942             :   { 130,        2,      1,      4,      647,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #130 = ABSQ_S_W_MM
    3943             :   { 131,        3,      1,      4,      2,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #131 = ADD
    3944             :   { 132,        2,      1,      4,      3,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #132 = ADDIUPC
    3945             :   { 133,        2,      1,      4,      4,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #133 = ADDIUPC_MM
    3946             :   { 134,        2,      1,      4,      3,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #134 = ADDIUPC_MMR6
    3947             :   { 135,        2,      1,      2,      4,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #135 = ADDIUR1SP_MM
    3948             :   { 136,        3,      1,      2,      4,      0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #136 = ADDIUR2_MM
    3949             :   { 137,        3,      1,      2,      4,      0, 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #137 = ADDIUS5_MM
    3950             :   { 138,        1,      0,      2,      4,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #138 = ADDIUSP_MM
    3951             :   { 139,        3,      1,      4,      4,      0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #139 = ADDIU_MMR6
    3952             :   { 140,        3,      1,      4,      601,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #140 = ADDQH_PH
    3953             :   { 141,        3,      1,      4,      764,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #141 = ADDQH_PH_MMR2
    3954             :   { 142,        3,      1,      4,      602,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #142 = ADDQH_R_PH
    3955             :   { 143,        3,      1,      4,      765,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #143 = ADDQH_R_PH_MMR2
    3956             :   { 144,        3,      1,      4,      603,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #144 = ADDQH_R_W
    3957             :   { 145,        3,      1,      4,      766,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #145 = ADDQH_R_W_MMR2
    3958             :   { 146,        3,      1,      4,      604,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #146 = ADDQH_W
    3959             :   { 147,        3,      1,      4,      767,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #147 = ADDQH_W_MMR2
    3960             :   { 148,        3,      1,      4,      501,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #148 = ADDQ_PH
    3961             :   { 149,        3,      1,      4,      648,    0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #149 = ADDQ_PH_MM
    3962             :   { 150,        3,      1,      4,      502,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #150 = ADDQ_S_PH
    3963             :   { 151,        3,      1,      4,      649,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #151 = ADDQ_S_PH_MM
    3964             :   { 152,        3,      1,      4,      503,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #152 = ADDQ_S_W
    3965             :   { 153,        3,      1,      4,      650,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #153 = ADDQ_S_W_MM
    3966             :   { 154,        3,      1,      4,      504,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo33, -1 ,nullptr },  // Inst #154 = ADDSC
    3967             :   { 155,        3,      1,      4,      651,    0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo33, -1 ,nullptr },  // Inst #155 = ADDSC_MM
    3968             :   { 156,        3,      1,      4,      374,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #156 = ADDS_A_B
    3969             :   { 157,        3,      1,      4,      374,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #157 = ADDS_A_D
    3970             :   { 158,        3,      1,      4,      374,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #158 = ADDS_A_H
    3971             :   { 159,        3,      1,      4,      374,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #159 = ADDS_A_W
    3972             :   { 160,        3,      1,      4,      374,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #160 = ADDS_S_B
    3973             :   { 161,        3,      1,      4,      374,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #161 = ADDS_S_D
    3974             :   { 162,        3,      1,      4,      374,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #162 = ADDS_S_H
    3975             :   { 163,        3,      1,      4,      374,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #163 = ADDS_S_W
    3976             :   { 164,        3,      1,      4,      374,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #164 = ADDS_U_B
    3977             :   { 165,        3,      1,      4,      374,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #165 = ADDS_U_D
    3978             :   { 166,        3,      1,      4,      374,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #166 = ADDS_U_H
    3979             :   { 167,        3,      1,      4,      374,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #167 = ADDS_U_W
    3980             :   { 168,        3,      1,      2,      5,      0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #168 = ADDU16_MM
    3981             :   { 169,        3,      1,      2,      5,      0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #169 = ADDU16_MMR6
    3982             :   { 170,        3,      1,      4,      605,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #170 = ADDUH_QB
    3983             :   { 171,        3,      1,      4,      768,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #171 = ADDUH_QB_MMR2
    3984             :   { 172,        3,      1,      4,      606,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #172 = ADDUH_R_QB
    3985             :   { 173,        3,      1,      4,      769,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #173 = ADDUH_R_QB_MMR2
    3986             :   { 174,        3,      1,      4,      5,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #174 = ADDU_MMR6
    3987             :   { 175,        3,      1,      4,      607,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #175 = ADDU_PH
    3988             :   { 176,        3,      1,      4,      770,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #176 = ADDU_PH_MMR2
    3989             :   { 177,        3,      1,      4,      505,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #177 = ADDU_QB
    3990             :   { 178,        3,      1,      4,      652,    0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #178 = ADDU_QB_MM
    3991             :   { 179,        3,      1,      4,      608,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #179 = ADDU_S_PH
    3992             :   { 180,        3,      1,      4,      771,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #180 = ADDU_S_PH_MMR2
    3993             :   { 181,        3,      1,      4,      506,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #181 = ADDU_S_QB
    3994             :   { 182,        3,      1,      4,      653,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #182 = ADDU_S_QB_MM
    3995             :   { 183,        3,      1,      4,      375,    0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #183 = ADDVI_B
    3996             :   { 184,        3,      1,      4,      375,    0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #184 = ADDVI_D
    3997             :   { 185,        3,      1,      4,      375,    0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #185 = ADDVI_H
    3998             :   { 186,        3,      1,      4,      375,    0, 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #186 = ADDVI_W
    3999             :   { 187,        3,      1,      4,      375,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #187 = ADDV_B
    4000             :   { 188,        3,      1,      4,      375,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #188 = ADDV_D
    4001             :   { 189,        3,      1,      4,      375,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #189 = ADDV_H
    4002             :   { 190,        3,      1,      4,      375,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #190 = ADDV_W
    4003             :   { 191,        3,      1,      4,      507,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #191 = ADDWC
    4004             :   { 192,        3,      1,      4,      654,    0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #192 = ADDWC_MM
    4005             :   { 193,        3,      1,      4,      373,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #193 = ADD_A_B
    4006             :   { 194,        3,      1,      4,      373,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #194 = ADD_A_D
    4007             :   { 195,        3,      1,      4,      373,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #195 = ADD_A_H
    4008             :   { 196,        3,      1,      4,      373,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #196 = ADD_A_W
    4009             :   { 197,        3,      1,      4,      2,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #197 = ADD_MM
    4010             :   { 198,        3,      1,      4,      2,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #198 = ADD_MMR6
    4011             :   { 199,        3,      1,      4,      6,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #199 = ADDi
    4012             :   { 200,        3,      1,      4,      6,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #200 = ADDi_MM
    4013             :   { 201,        3,      1,      4,      4,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #201 = ADDiu
    4014             :   { 202,        3,      1,      4,      4,      0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #202 = ADDiu_MM
    4015             :   { 203,        3,      1,      4,      5,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #203 = ADDu
    4016             :   { 204,        3,      1,      4,      5,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #204 = ADDu_MM
    4017             :   { 205,        2,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo8, -1 ,nullptr },  // Inst #205 = ADJCALLSTACKDOWN
    4018             :   { 206,        2,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo8, -1 ,nullptr },  // Inst #206 = ADJCALLSTACKUP
    4019             :   { 207,        4,      1,      4,      7,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #207 = ALIGN
    4020             :   { 208,        4,      1,      4,      7,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #208 = ALIGN_MMR6
    4021             :   { 209,        2,      1,      4,      8,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #209 = ALUIPC
    4022             :   { 210,        2,      1,      4,      8,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #210 = ALUIPC_MMR6
    4023             :   { 211,        3,      1,      4,      9,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #211 = AND
    4024             :   { 212,        3,      1,      2,      9,      0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #212 = AND16_MM
    4025             :   { 213,        3,      1,      2,      9,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #213 = AND16_MMR6
    4026             :   { 214,        3,      1,      4,      9,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #214 = AND64
    4027             :   { 215,        3,      1,      2,      9,      0, 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #215 = ANDI16_MM
    4028             :   { 216,        3,      1,      2,      9,      0, 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #216 = ANDI16_MMR6
    4029             :   { 217,        3,      1,      4,      384,    0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #217 = ANDI_B
    4030             :   { 218,        3,      1,      4,      10,     0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #218 = ANDI_MMR6
    4031             :   { 219,        3,      1,      4,      9,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #219 = AND_MM
    4032             :   { 220,        3,      1,      4,      9,      0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #220 = AND_MMR6
    4033             :   { 221,        3,      1,      4,      383,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #221 = AND_V
    4034             :   { 222,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #222 = AND_V_D_PSEUDO
    4035             :   { 223,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #223 = AND_V_H_PSEUDO
    4036             :   { 224,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #224 = AND_V_W_PSEUDO
    4037             :   { 225,        3,      1,      4,      10,     0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #225 = ANDi
    4038             :   { 226,        3,      1,      4,      9,      0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #226 = ANDi64
    4039             :   { 227,        3,      1,      4,      10,     0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #227 = ANDi_MM
    4040             :   { 228,        4,      1,      4,      609,    0, 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #228 = APPEND
    4041             :   { 229,        4,      1,      4,      772,    0, 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #229 = APPEND_MMR2
    4042             :   { 230,        3,      1,      4,      376,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #230 = ASUB_S_B
    4043             :   { 231,        3,      1,      4,      376,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #231 = ASUB_S_D
    4044             :   { 232,        3,      1,      4,      376,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #232 = ASUB_S_H
    4045             :   { 233,        3,      1,      4,      376,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #233 = ASUB_S_W
    4046             :   { 234,        3,      1,      4,      376,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #234 = ASUB_U_B
    4047             :   { 235,        3,      1,      4,      376,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #235 = ASUB_U_D
    4048             :   { 236,        3,      1,      4,      376,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #236 = ASUB_U_H
    4049             :   { 237,        3,      1,      4,      376,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #237 = ASUB_U_W
    4050             :   { 238,        4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #238 = ATOMIC_CMP_SWAP_I16
    4051             :   { 239,        4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #239 = ATOMIC_CMP_SWAP_I32
    4052             :   { 240,        4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #240 = ATOMIC_CMP_SWAP_I64
    4053             :   { 241,        4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #241 = ATOMIC_CMP_SWAP_I8
    4054             :   { 242,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #242 = ATOMIC_LOAD_ADD_I16
    4055             :   { 243,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #243 = ATOMIC_LOAD_ADD_I32
    4056             :   { 244,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #244 = ATOMIC_LOAD_ADD_I64
    4057             :   { 245,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #245 = ATOMIC_LOAD_ADD_I8
    4058             :   { 246,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #246 = ATOMIC_LOAD_AND_I16
    4059             :   { 247,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #247 = ATOMIC_LOAD_AND_I32
    4060             :   { 248,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #248 = ATOMIC_LOAD_AND_I64
    4061             :   { 249,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #249 = ATOMIC_LOAD_AND_I8
    4062             :   { 250,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #250 = ATOMIC_LOAD_NAND_I16
    4063             :   { 251,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #251 = ATOMIC_LOAD_NAND_I32
    4064             :   { 252,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #252 = ATOMIC_LOAD_NAND_I64
    4065             :   { 253,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #253 = ATOMIC_LOAD_NAND_I8
    4066             :   { 254,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #254 = ATOMIC_LOAD_OR_I16
    4067             :   { 255,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #255 = ATOMIC_LOAD_OR_I32
    4068             :   { 256,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #256 = ATOMIC_LOAD_OR_I64
    4069             :   { 257,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #257 = ATOMIC_LOAD_OR_I8
    4070             :   { 258,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #258 = ATOMIC_LOAD_SUB_I16
    4071             :   { 259,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #259 = ATOMIC_LOAD_SUB_I32
    4072             :   { 260,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #260 = ATOMIC_LOAD_SUB_I64
    4073             :   { 261,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #261 = ATOMIC_LOAD_SUB_I8
    4074             :   { 262,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #262 = ATOMIC_LOAD_XOR_I16
    4075             :   { 263,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #263 = ATOMIC_LOAD_XOR_I32
    4076             :   { 264,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #264 = ATOMIC_LOAD_XOR_I64
    4077             :   { 265,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #265 = ATOMIC_LOAD_XOR_I8
    4078             :   { 266,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #266 = ATOMIC_SWAP_I16
    4079             :   { 267,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #267 = ATOMIC_SWAP_I32
    4080             :   { 268,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #268 = ATOMIC_SWAP_I64
    4081             :   { 269,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #269 = ATOMIC_SWAP_I8
    4082             :   { 270,        3,      1,      4,      11,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #270 = AUI
    4083             :   { 271,        2,      1,      4,      12,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #271 = AUIPC
    4084             :   { 272,        2,      1,      4,      12,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #272 = AUIPC_MMR6
    4085             :   { 273,        3,      1,      4,      11,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #273 = AUI_MMR6
    4086             :   { 274,        3,      1,      4,      377,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #274 = AVER_S_B
    4087             :   { 275,        3,      1,      4,      377,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #275 = AVER_S_D
    4088             :   { 276,        3,      1,      4,      377,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #276 = AVER_S_H
    4089             :   { 277,        3,      1,      4,      377,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #277 = AVER_S_W
    4090             :   { 278,        3,      1,      4,      377,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #278 = AVER_U_B
    4091             :   { 279,        3,      1,      4,      377,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #279 = AVER_U_D
    4092             :   { 280,        3,      1,      4,      377,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #280 = AVER_U_H
    4093             :   { 281,        3,      1,      4,      377,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #281 = AVER_U_W
    4094             :   { 282,        3,      1,      4,      377,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #282 = AVE_S_B
    4095             :   { 283,        3,      1,      4,      377,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #283 = AVE_S_D
    4096             :   { 284,        3,      1,      4,      377,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #284 = AVE_S_H
    4097             :   { 285,        3,      1,      4,      377,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #285 = AVE_S_W
    4098             :   { 286,        3,      1,      4,      377,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #286 = AVE_U_B
    4099             :   { 287,        3,      1,      4,      377,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #287 = AVE_U_D
    4100             :   { 288,        3,      1,      4,      377,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #288 = AVE_U_H
    4101             :   { 289,        3,      1,      4,      377,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #289 = AVE_U_W
    4102             :   { 290,        2,      1,      4,      13,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #290 = AddiuRxImmX16
    4103             :   { 291,        2,      1,      4,      13,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #291 = AddiuRxPcImmX16
    4104             :   { 292,        3,      1,      2,      13,     0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #292 = AddiuRxRxImm16
    4105             :   { 293,        3,      1,      4,      13,     0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #293 = AddiuRxRxImmX16
    4106             :   { 294,        3,      1,      4,      13,     0, 0x0ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #294 = AddiuRxRyOffMemX16
    4107             :   { 295,        1,      0,      2,      13,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo2, -1 ,nullptr },  // Inst #295 = AddiuSpImm16
    4108             :   { 296,        1,      0,      4,      13,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo2, -1 ,nullptr },  // Inst #296 = AddiuSpImmX16
    4109             :   { 297,        3,      1,      2,      13,     0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #297 = AdduRxRyRz16
    4110             :   { 298,        3,      1,      2,      13,     0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr },  // Inst #298 = AndRxRxRy16
    4111             :   { 299,        1,      0,      4,      14,     0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, ImplicitList4, OperandInfo63, -1 ,nullptr },  // Inst #299 = B
    4112             :   { 300,        1,      0,      2,      14,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo63, -1 ,nullptr },  // Inst #300 = B16_MM
    4113             :   { 301,        3,      1,      4,      15,     0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #301 = BADDu
    4114             :   { 302,        1,      0,      4,      16,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList5, OperandInfo63, -1 ,nullptr },  // Inst #302 = BAL
    4115             :   { 303,        1,      0,      4,      17,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList5, OperandInfo63, -1 ,nullptr },  // Inst #303 = BALC
    4116             :   { 304,        1,      0,      4,      17,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList5, OperandInfo63, -1 ,nullptr },  // Inst #304 = BALC_MMR6
    4117             :   { 305,        4,      1,      4,      610,    0, 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #305 = BALIGN
    4118             :   { 306,        4,      1,      4,      773,    0, 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #306 = BALIGN_MMR2
    4119             :   { 307,        1,      0,      4,      18,     0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, ImplicitList5, OperandInfo63, -1 ,nullptr },  // Inst #307 = BAL_BR
    4120             :   { 308,        1,      0,      4,      18,     0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, ImplicitList5, OperandInfo63, -1 ,nullptr },  // Inst #308 = BAL_BR_MM
    4121             :   { 309,        3,      0,      4,      19,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList4, OperandInfo64, -1 ,nullptr },  // Inst #309 = BBIT0
    4122             :   { 310,        3,      0,      4,      19,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList4, OperandInfo64, -1 ,nullptr },  // Inst #310 = BBIT032
    4123             :   { 311,        3,      0,      4,      19,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList4, OperandInfo64, -1 ,nullptr },  // Inst #311 = BBIT1
    4124             :   { 312,        3,      0,      4,      19,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList4, OperandInfo64, -1 ,nullptr },  // Inst #312 = BBIT132
    4125             :   { 313,        1,      0,      4,      16,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #313 = BC
    4126             :   { 314,        1,      0,      2,      16,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo63, -1 ,nullptr },  // Inst #314 = BC16_MMR6
    4127             :   { 315,        2,      0,      4,      20,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr },  // Inst #315 = BC1EQZ
    4128             :   { 316,        2,      0,      4,      20,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList4, OperandInfo65, -1 ,nullptr },  // Inst #316 = BC1EQZC_MMR6
    4129             :   { 317,        2,      0,      4,      21,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x85ULL, nullptr, ImplicitList4, OperandInfo66, -1 ,nullptr },  // Inst #317 = BC1F
    4130             :   { 318,        2,      0,      4,      22,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x85ULL, nullptr, ImplicitList4, OperandInfo66, -1 ,nullptr },  // Inst #318 = BC1FL
    4131             :   { 319,        2,      0,      4,      21,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x85ULL, nullptr, ImplicitList4, OperandInfo66, -1 ,nullptr },  // Inst #319 = BC1F_MM
    4132             :   { 320,        2,      0,      4,      20,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr },  // Inst #320 = BC1NEZ
    4133             :   { 321,        2,      0,      4,      20,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList4, OperandInfo65, -1 ,nullptr },  // Inst #321 = BC1NEZC_MMR6
    4134             :   { 322,        2,      0,      4,      23,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x85ULL, nullptr, ImplicitList4, OperandInfo66, -1 ,nullptr },  // Inst #322 = BC1T
    4135             :   { 323,        2,      0,      4,      24,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x85ULL, nullptr, ImplicitList4, OperandInfo66, -1 ,nullptr },  // Inst #323 = BC1TL
    4136             :   { 324,        2,      0,      4,      23,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x85ULL, nullptr, ImplicitList4, OperandInfo66, -1 ,nullptr },  // Inst #324 = BC1T_MM
    4137             :   { 325,        2,      0,      4,      25,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #325 = BC2EQZ
    4138             :   { 326,        2,      0,      4,      25,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr },  // Inst #326 = BC2EQZC_MMR6
    4139             :   { 327,        2,      0,      4,      25,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #327 = BC2NEZ
    4140             :   { 328,        2,      0,      4,      25,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr },  // Inst #328 = BC2NEZC_MMR6
    4141             :   { 329,        3,      1,      4,      365,    0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #329 = BCLRI_B
    4142             :   { 330,        3,      1,      4,      365,    0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #330 = BCLRI_D
    4143             :   { 331,        3,      1,      4,      365,    0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #331 = BCLRI_H
    4144             :   { 332,        3,      1,      4,      365,    0, 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #332 = BCLRI_W
    4145             :   { 333,        3,      1,      4,      365,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #333 = BCLR_B
    4146             :   { 334,        3,      1,      4,      365,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #334 = BCLR_D
    4147             :   { 335,        3,      1,      4,      365,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #335 = BCLR_H
    4148             :   { 336,        3,      1,      4,      365,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #336 = BCLR_W
    4149             :   { 337,        1,      0,      4,      16,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x16ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #337 = BC_MMR6
    4150             :   { 338,        3,      0,      4,      26,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr },  // Inst #338 = BEQ
    4151             :   { 339,        3,      0,      4,      26,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList4, OperandInfo69, -1 ,nullptr },  // Inst #339 = BEQ64
    4152             :   { 340,        3,      0,      4,      27,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr },  // Inst #340 = BEQC
    4153             :   { 341,        3,      0,      4,      27,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList4, OperandInfo69, -1 ,nullptr },  // Inst #341 = BEQC64
    4154             :   { 342,        3,      0,      4,      27,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr },  // Inst #342 = BEQC_MMR6
    4155             :   { 343,        3,      0,      4,      26,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr },  // Inst #343 = BEQL
    4156             :   { 344,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #344 = BEQLImmMacro
    4157             :   { 345,        2,      0,      2,      28,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo71, -1 ,nullptr },  // Inst #345 = BEQZ16_MM
    4158             :   { 346,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList5, OperandInfo72, -1 ,nullptr },  // Inst #346 = BEQZALC
    4159             :   { 347,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList5, OperandInfo72, -1 ,nullptr },  // Inst #347 = BEQZALC_MMR6
    4160             :   { 348,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList4, OperandInfo72, -1 ,nullptr },  // Inst #348 = BEQZC
    4161             :   { 349,        2,      0,      2,      28,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo71, -1 ,nullptr },  // Inst #349 = BEQZC16_MMR6
    4162             :   { 350,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList4, OperandInfo73, -1 ,nullptr },  // Inst #350 = BEQZC64
    4163             :   { 351,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, ImplicitList4, OperandInfo72, -1 ,nullptr },  // Inst #351 = BEQZC_MM
    4164             :   { 352,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL, nullptr, ImplicitList4, OperandInfo72, -1 ,nullptr },  // Inst #352 = BEQZC_MMR6
    4165             :   { 353,        3,      0,      4,      26,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr },  // Inst #353 = BEQ_MM
    4166             :   { 354,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #354 = BGE
    4167             :   { 355,        3,      0,      4,      27,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr },  // Inst #355 = BGEC
    4168             :   { 356,        3,      0,      4,      27,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList4, OperandInfo69, -1 ,nullptr },  // Inst #356 = BGEC64
    4169             :   { 357,        3,      0,      4,      27,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr },  // Inst #357 = BGEC_MMR6
    4170             :   { 358,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #358 = BGEImmMacro
    4171             :   { 359,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #359 = BGEL
    4172             :   { 360,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #360 = BGELImmMacro
    4173             :   { 361,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #361 = BGEU
    4174             :   { 362,        3,      0,      4,      27,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr },  // Inst #362 = BGEUC
    4175             :   { 363,        3,      0,      4,      27,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList4, OperandInfo69, -1 ,nullptr },  // Inst #363 = BGEUC64
    4176             :   { 364,        3,      0,      4,      27,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr },  // Inst #364 = BGEUC_MMR6
    4177             :   { 365,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #365 = BGEUImmMacro
    4178             :   { 366,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #366 = BGEUL
    4179             :   { 367,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #367 = BGEULImmMacro
    4180             :   { 368,        2,      0,      4,      28,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList4, OperandInfo72, -1 ,nullptr },  // Inst #368 = BGEZ
    4181             :   { 369,        2,      0,      4,      28,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList4, OperandInfo73, -1 ,nullptr },  // Inst #369 = BGEZ64
    4182             :   { 370,        2,      0,      4,      18,     0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList5, OperandInfo72, -1 ,nullptr },  // Inst #370 = BGEZAL
    4183             :   { 371,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList5, OperandInfo72, -1 ,nullptr },  // Inst #371 = BGEZALC
    4184             :   { 372,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList5, OperandInfo72, -1 ,nullptr },  // Inst #372 = BGEZALC_MMR6
    4185             :   { 373,        2,      0,      4,      18,     0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList5, OperandInfo72, -1 ,nullptr },  // Inst #373 = BGEZALL
    4186             :   { 374,        2,      0,      4,      30,     0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, ImplicitList5, OperandInfo72, -1 ,nullptr },  // Inst #374 = BGEZALS_MM
    4187             :   { 375,        2,      0,      4,      18,     0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList5, OperandInfo72, -1 ,nullptr },  // Inst #375 = BGEZAL_MM
    4188             :   { 376,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList4, OperandInfo72, -1 ,nullptr },  // Inst #376 = BGEZC
    4189             :   { 377,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList4, OperandInfo73, -1 ,nullptr },  // Inst #377 = BGEZC64
    4190             :   { 378,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList4, OperandInfo72, -1 ,nullptr },  // Inst #378 = BGEZC_MMR6
    4191             :   { 379,        2,      0,      4,      28,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList4, OperandInfo72, -1 ,nullptr },  // Inst #379 = BGEZL
    4192             :   { 380,        2,      0,      4,      28,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList4, OperandInfo72, -1 ,nullptr },  // Inst #380 = BGEZ_MM
    4193             :   { 381,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #381 = BGT
    4194             :   { 382,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #382 = BGTImmMacro
    4195             :   { 383,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #383 = BGTL
    4196             :   { 384,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #384 = BGTLImmMacro
    4197             :   { 385,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #385 = BGTU
    4198             :   { 386,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #386 = BGTUImmMacro
    4199             :   { 387,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #387 = BGTUL
    4200             :   { 388,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #388 = BGTULImmMacro
    4201             :   { 389,        2,      0,      4,      28,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList4, OperandInfo72, -1 ,nullptr },  // Inst #389 = BGTZ
    4202             :   { 390,        2,      0,      4,      28,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList4, OperandInfo73, -1 ,nullptr },  // Inst #390 = BGTZ64
    4203             :   { 391,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList5, OperandInfo72, -1 ,nullptr },  // Inst #391 = BGTZALC
    4204             :   { 392,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList5, OperandInfo72, -1 ,nullptr },  // Inst #392 = BGTZALC_MMR6
    4205             :   { 393,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList4, OperandInfo72, -1 ,nullptr },  // Inst #393 = BGTZC
    4206             :   { 394,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList4, OperandInfo73, -1 ,nullptr },  // Inst #394 = BGTZC64
    4207             :   { 395,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList4, OperandInfo72, -1 ,nullptr },  // Inst #395 = BGTZC_MMR6
    4208             :   { 396,        2,      0,      4,      28,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList4, OperandInfo72, -1 ,nullptr },  // Inst #396 = BGTZL
    4209             :   { 397,        2,      0,      4,      28,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList4, OperandInfo72, -1 ,nullptr },  // Inst #397 = BGTZ_MM
    4210             :   { 398,        4,      1,      4,      360,    0, 0x6ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr },  // Inst #398 = BINSLI_B
    4211             :   { 399,        4,      1,      4,      360,    0, 0x6ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr },  // Inst #399 = BINSLI_D
    4212             :   { 400,        4,      1,      4,      360,    0, 0x6ULL, nullptr, nullptr, OperandInfo76, -1 ,nullptr },  // Inst #400 = BINSLI_H
    4213             :   { 401,        4,      1,      4,      360,    0, 0x6ULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr },  // Inst #401 = BINSLI_W
    4214             :   { 402,        4,      1,      4,      360,    0, 0x6ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr },  // Inst #402 = BINSL_B
    4215             :   { 403,        4,      1,      4,      360,    0, 0x6ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #403 = BINSL_D
    4216             :   { 404,        4,      1,      4,      360,    0, 0x6ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #404 = BINSL_H
    4217             :   { 405,        4,      1,      4,      360,    0, 0x6ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #405 = BINSL_W
    4218             :   { 406,        4,      1,      4,      361,    0, 0x6ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr },  // Inst #406 = BINSRI_B
    4219             :   { 407,        4,      1,      4,      361,    0, 0x6ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr },  // Inst #407 = BINSRI_D
    4220             :   { 408,        4,      1,      4,      361,    0, 0x6ULL, nullptr, nullptr, OperandInfo76, -1 ,nullptr },  // Inst #408 = BINSRI_H
    4221             :   { 409,        4,      1,      4,      361,    0, 0x6ULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr },  // Inst #409 = BINSRI_W
    4222             :   { 410,        4,      1,      4,      361,    0, 0x6ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr },  // Inst #410 = BINSR_B
    4223             :   { 411,        4,      1,      4,      361,    0, 0x6ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #411 = BINSR_D
    4224             :   { 412,        4,      1,      4,      361,    0, 0x6ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #412 = BINSR_H
    4225             :   { 413,        4,      1,      4,      361,    0, 0x6ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #413 = BINSR_W
    4226             :   { 414,        2,      1,      4,      508,    0, 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #414 = BITREV
    4227             :   { 415,        2,      1,      4,      655,    0, 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #415 = BITREV_MM
    4228             :   { 416,        2,      1,      4,      31,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #416 = BITSWAP
    4229             :   { 417,        2,      1,      4,      31,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #417 = BITSWAP_MMR6
    4230             :   { 418,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #418 = BLE
    4231             :   { 419,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #419 = BLEImmMacro
    4232             :   { 420,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #420 = BLEL
    4233             :   { 421,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #421 = BLELImmMacro
    4234             :   { 422,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #422 = BLEU
    4235             :   { 423,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #423 = BLEUImmMacro
    4236             :   { 424,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #424 = BLEUL
    4237             :   { 425,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #425 = BLEULImmMacro
    4238             :   { 426,        2,      0,      4,      28,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList4, OperandInfo72, -1 ,nullptr },  // Inst #426 = BLEZ
    4239             :   { 427,        2,      0,      4,      28,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList4, OperandInfo73, -1 ,nullptr },  // Inst #427 = BLEZ64
    4240             :   { 428,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList5, OperandInfo72, -1 ,nullptr },  // Inst #428 = BLEZALC
    4241             :   { 429,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList5, OperandInfo72, -1 ,nullptr },  // Inst #429 = BLEZALC_MMR6
    4242             :   { 430,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList4, OperandInfo72, -1 ,nullptr },  // Inst #430 = BLEZC
    4243             :   { 431,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList4, OperandInfo73, -1 ,nullptr },  // Inst #431 = BLEZC64
    4244             :   { 432,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList4, OperandInfo72, -1 ,nullptr },  // Inst #432 = BLEZC_MMR6
    4245             :   { 433,        2,      0,      4,      28,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList4, OperandInfo72, -1 ,nullptr },  // Inst #433 = BLEZL
    4246             :   { 434,        2,      0,      4,      28,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList4, OperandInfo72, -1 ,nullptr },  // Inst #434 = BLEZ_MM
    4247             :   { 435,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #435 = BLT
    4248             :   { 436,        3,      0,      4,      27,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr },  // Inst #436 = BLTC
    4249             :   { 437,        3,      0,      4,      27,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList4, OperandInfo69, -1 ,nullptr },  // Inst #437 = BLTC64
    4250             :   { 438,        3,      0,      4,      27,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr },  // Inst #438 = BLTC_MMR6
    4251             :   { 439,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #439 = BLTImmMacro
    4252             :   { 440,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #440 = BLTL
    4253             :   { 441,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #441 = BLTLImmMacro
    4254             :   { 442,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #442 = BLTU
    4255             :   { 443,        3,      0,      4,      27,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr },  // Inst #443 = BLTUC
    4256             :   { 444,        3,      0,      4,      27,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList4, OperandInfo69, -1 ,nullptr },  // Inst #444 = BLTUC64
    4257             :   { 445,        3,      0,      4,      27,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr },  // Inst #445 = BLTUC_MMR6
    4258             :   { 446,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #446 = BLTUImmMacro
    4259             :   { 447,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #447 = BLTUL
    4260             :   { 448,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #448 = BLTULImmMacro
    4261             :   { 449,        2,      0,      4,      28,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList4, OperandInfo72, -1 ,nullptr },  // Inst #449 = BLTZ
    4262             :   { 450,        2,      0,      4,      28,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList4, OperandInfo73, -1 ,nullptr },  // Inst #450 = BLTZ64
    4263             :   { 451,        2,      0,      4,      18,     0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList5, OperandInfo72, -1 ,nullptr },  // Inst #451 = BLTZAL
    4264             :   { 452,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList5, OperandInfo72, -1 ,nullptr },  // Inst #452 = BLTZALC
    4265             :   { 453,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList5, OperandInfo72, -1 ,nullptr },  // Inst #453 = BLTZALC_MMR6
    4266             :   { 454,        2,      0,      4,      18,     0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList5, OperandInfo72, -1 ,nullptr },  // Inst #454 = BLTZALL
    4267             :   { 455,        2,      0,      4,      30,     0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, ImplicitList5, OperandInfo72, -1 ,nullptr },  // Inst #455 = BLTZALS_MM
    4268             :   { 456,        2,      0,      4,      18,     0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList5, OperandInfo72, -1 ,nullptr },  // Inst #456 = BLTZAL_MM
    4269             :   { 457,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList4, OperandInfo72, -1 ,nullptr },  // Inst #457 = BLTZC
    4270             :   { 458,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList4, OperandInfo73, -1 ,nullptr },  // Inst #458 = BLTZC64
    4271             :   { 459,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList4, OperandInfo72, -1 ,nullptr },  // Inst #459 = BLTZC_MMR6
    4272             :   { 460,        2,      0,      4,      28,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList4, OperandInfo72, -1 ,nullptr },  // Inst #460 = BLTZL
    4273             :   { 461,        2,      0,      4,      28,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList4, OperandInfo72, -1 ,nullptr },  // Inst #461 = BLTZ_MM
    4274             :   { 462,        4,      1,      4,      368,    0, 0x6ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr },  // Inst #462 = BMNZI_B
    4275             :   { 463,        4,      1,      4,      368,    0, 0x6ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr },  // Inst #463 = BMNZ_V
    4276             :   { 464,        4,      1,      4,      368,    0, 0x6ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr },  // Inst #464 = BMZI_B
    4277             :   { 465,        4,      1,      4,      368,    0, 0x6ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr },  // Inst #465 = BMZ_V
    4278             :   { 466,        3,      0,      4,      26,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr },  // Inst #466 = BNE
    4279             :   { 467,        3,      0,      4,      26,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList4, OperandInfo69, -1 ,nullptr },  // Inst #467 = BNE64
    4280             :   { 468,        3,      0,      4,      27,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr },  // Inst #468 = BNEC
    4281             :   { 469,        3,      0,      4,      27,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList4, OperandInfo69, -1 ,nullptr },  // Inst #469 = BNEC64
    4282             :   { 470,        3,      0,      4,      27,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr },  // Inst #470 = BNEC_MMR6
    4283             :   { 471,        3,      1,      4,      366,    0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #471 = BNEGI_B
    4284             :   { 472,        3,      1,      4,      366,    0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #472 = BNEGI_D
    4285             :   { 473,        3,      1,      4,      366,    0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #473 = BNEGI_H
    4286             :   { 474,        3,      1,      4,      366,    0, 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #474 = BNEGI_W
    4287             :   { 475,        3,      1,      4,      366,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #475 = BNEG_B
    4288             :   { 476,        3,      1,      4,      366,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #476 = BNEG_D
    4289             :   { 477,        3,      1,      4,      366,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #477 = BNEG_H
    4290             :   { 478,        3,      1,      4,      366,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #478 = BNEG_W
    4291             :   { 479,        3,      0,      4,      26,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr },  // Inst #479 = BNEL
    4292             :   { 480,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #480 = BNELImmMacro
    4293             :   { 481,        2,      0,      2,      28,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo71, -1 ,nullptr },  // Inst #481 = BNEZ16_MM
    4294             :   { 482,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList5, OperandInfo72, -1 ,nullptr },  // Inst #482 = BNEZALC
    4295             :   { 483,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList5, OperandInfo72, -1 ,nullptr },  // Inst #483 = BNEZALC_MMR6
    4296             :   { 484,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList4, OperandInfo72, -1 ,nullptr },  // Inst #484 = BNEZC
    4297             :   { 485,        2,      0,      2,      28,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo71, -1 ,nullptr },  // Inst #485 = BNEZC16_MMR6
    4298             :   { 486,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList4, OperandInfo73, -1 ,nullptr },  // Inst #486 = BNEZC64
    4299             :   { 487,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, ImplicitList4, OperandInfo72, -1 ,nullptr },  // Inst #487 = BNEZC_MM
    4300             :   { 488,        2,      0,      4,      29,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL, nullptr, ImplicitList4, OperandInfo72, -1 ,nullptr },  // Inst #488 = BNEZC_MMR6
    4301             :   { 489,        3,      0,      4,      26,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr },  // Inst #489 = BNE_MM
    4302             :   { 490,        3,      0,      4,      27,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr },  // Inst #490 = BNVC
    4303             :   { 491,        3,      0,      4,      27,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr },  // Inst #491 = BNVC_MMR6
    4304             :   { 492,        2,      0,      4,      371,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList4, OperandInfo82, -1 ,nullptr },  // Inst #492 = BNZ_B
    4305             :   { 493,        2,      0,      4,      371,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList4, OperandInfo83, -1 ,nullptr },  // Inst #493 = BNZ_D
    4306             :   { 494,        2,      0,      4,      371,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList4, OperandInfo84, -1 ,nullptr },  // Inst #494 = BNZ_H
    4307             :   { 495,        2,      0,      4,      371,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList4, OperandInfo82, -1 ,nullptr },  // Inst #495 = BNZ_V
    4308             :   { 496,        2,      0,      4,      371,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList4, OperandInfo85, -1 ,nullptr },  // Inst #496 = BNZ_W
    4309             :   { 497,        3,      0,      4,      27,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr },  // Inst #497 = BOVC
    4310             :   { 498,        3,      0,      4,      27,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr },  // Inst #498 = BOVC_MMR6
    4311             :   { 499,        1,      0,      4,      509,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #499 = BPOSGE32
    4312             :   { 500,        1,      0,      4,      809,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #500 = BPOSGE32C_MMR3
    4313             :   { 501,        1,      0,      4,      656,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #501 = BPOSGE32_MM
    4314             :   { 502,        1,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList6, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #502 = BPOSGE32_PSEUDO
    4315             :   { 503,        2,      0,      4,      32,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #503 = BREAK
    4316             :   { 504,        1,      0,      2,      32,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #504 = BREAK16_MM
    4317             :   { 505,        1,      0,      2,      32,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #505 = BREAK16_MMR6
    4318             :   { 506,        2,      0,      4,      32,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #506 = BREAK_MM
    4319             :   { 507,        2,      0,      4,      32,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #507 = BREAK_MMR6
    4320             :   { 508,        4,      1,      4,      367,    0, 0x6ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr },  // Inst #508 = BSELI_B
    4321             :   { 509,        4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #509 = BSEL_D_PSEUDO
    4322             :   { 510,        4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #510 = BSEL_FD_PSEUDO
    4323             :   { 511,        4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #511 = BSEL_FW_PSEUDO
    4324             :   { 512,        4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #512 = BSEL_H_PSEUDO
    4325             :   { 513,        4,      1,      4,      367,    0, 0x6ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr },  // Inst #513 = BSEL_V
    4326             :   { 514,        4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #514 = BSEL_W_PSEUDO
    4327             :   { 515,        3,      1,      4,      364,    0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #515 = BSETI_B
    4328             :   { 516,        3,      1,      4,      364,    0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #516 = BSETI_D
    4329             :   { 517,        3,      1,      4,      364,    0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #517 = BSETI_H
    4330             :   { 518,        3,      1,      4,      364,    0, 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #518 = BSETI_W
    4331             :   { 519,        3,      1,      4,      364,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #519 = BSET_B
    4332             :   { 520,        3,      1,      4,      364,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #520 = BSET_D
    4333             :   { 521,        3,      1,      4,      364,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #521 = BSET_H
    4334             :   { 522,        3,      1,      4,      364,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #522 = BSET_W
    4335             :   { 523,        2,      0,      4,      371,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList4, OperandInfo82, -1 ,nullptr },  // Inst #523 = BZ_B
    4336             :   { 524,        2,      0,      4,      371,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList4, OperandInfo83, -1 ,nullptr },  // Inst #524 = BZ_D
    4337             :   { 525,        2,      0,      4,      371,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList4, OperandInfo84, -1 ,nullptr },  // Inst #525 = BZ_H
    4338             :   { 526,        2,      0,      4,      371,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList4, OperandInfo82, -1 ,nullptr },  // Inst #526 = BZ_V
    4339             :   { 527,        2,      0,      4,      371,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList4, OperandInfo85, -1 ,nullptr },  // Inst #527 = BZ_W
    4340             :   { 528,        1,      0,      4,      14,     0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, ImplicitList4, OperandInfo63, -1 ,nullptr },  // Inst #528 = B_MM
    4341             :   { 529,        1,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #529 = B_MMR6_Pseudo
    4342             :   { 530,        1,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #530 = B_MM_Pseudo
    4343             :   { 531,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #531 = BeqImm
    4344             :   { 532,        2,      0,      2,      13,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #532 = BeqzRxImm16
    4345             :   { 533,        2,      0,      4,      13,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #533 = BeqzRxImmX16
    4346             :   { 534,        1,      0,      2,      13,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #534 = Bimm16
    4347             :   { 535,        1,      0,      4,      13,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #535 = BimmX16
    4348             :   { 536,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #536 = BneImm
    4349             :   { 537,        2,      0,      2,      13,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #537 = BnezRxImm16
    4350             :   { 538,        2,      0,      4,      13,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #538 = BnezRxImmX16
    4351             :   { 539,        0,      0,      2,      13,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #539 = Break16
    4352             :   { 540,        1,      0,      2,      13,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #540 = Bteqz16
    4353             :   { 541,        3,      0,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr },  // Inst #541 = BteqzT8CmpX16
    4354             :   { 542,        3,      0,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr },  // Inst #542 = BteqzT8CmpiX16
    4355             :   { 543,        3,      0,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr },  // Inst #543 = BteqzT8SltX16
    4356             :   { 544,        3,      0,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr },  // Inst #544 = BteqzT8SltiX16
    4357             :   { 545,        3,      0,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr },  // Inst #545 = BteqzT8SltiuX16
    4358             :   { 546,        3,      0,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr },  // Inst #546 = BteqzT8SltuX16
    4359             :   { 547,        1,      0,      4,      13,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #547 = BteqzX16
    4360             :   { 548,        1,      0,      2,      13,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #548 = Btnez16
    4361             :   { 549,        3,      0,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr },  // Inst #549 = BtnezT8CmpX16
    4362             :   { 550,        3,      0,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr },  // Inst #550 = BtnezT8CmpiX16
    4363             :   { 551,        3,      0,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr },  // Inst #551 = BtnezT8SltX16
    4364             :   { 552,        3,      0,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr },  // Inst #552 = BtnezT8SltiX16
    4365             :   { 553,        3,      0,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr },  // Inst #553 = BtnezT8SltiuX16
    4366             :   { 554,        3,      0,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr },  // Inst #554 = BtnezT8SltuX16
    4367             :   { 555,        1,      0,      4,      13,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #555 = BtnezX16
    4368             :   { 556,        3,      1,      4,      33,     0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #556 = BuildPairF64
    4369             :   { 557,        3,      1,      4,      33,     0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #557 = BuildPairF64_64
    4370             :   { 558,        3,      0,      4,      34,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #558 = CACHE
    4371             :   { 559,        3,      0,      4,      35,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #559 = CACHEE
    4372             :   { 560,        3,      0,      4,      35,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #560 = CACHEE_MM
    4373             :   { 561,        3,      0,      4,      34,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #561 = CACHE_MM
    4374             :   { 562,        3,      0,      4,      34,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #562 = CACHE_MMR6
    4375             :   { 563,        3,      0,      4,      34,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #563 = CACHE_R6
    4376             :   { 564,        2,      1,      4,      36,     0, 0x4ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #564 = CEIL_L_D64
    4377             :   { 565,        2,      1,      4,      36,     0, 0x4ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #565 = CEIL_L_D_MMR6
    4378             :   { 566,        2,      1,      4,      36,     0, 0x4ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #566 = CEIL_L_S
    4379             :   { 567,        2,      1,      4,      36,     0, 0x4ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #567 = CEIL_L_S_MMR6
    4380             :   { 568,        2,      1,      4,      36,     0, 0x4ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #568 = CEIL_W_D32
    4381             :   { 569,        2,      1,      4,      36,     0, 0x4ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr },  // Inst #569 = CEIL_W_D64
    4382             :   { 570,        2,      1,      4,      36,     0, 0x4ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #570 = CEIL_W_D_MMR6
    4383             :   { 571,        2,      1,      4,      36,     0, 0x4ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #571 = CEIL_W_MM
    4384             :   { 572,        2,      1,      4,      36,     0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #572 = CEIL_W_S
    4385             :   { 573,        2,      1,      4,      36,     0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #573 = CEIL_W_S_MM
    4386             :   { 574,        2,      1,      4,      36,     0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #574 = CEIL_W_S_MMR6
    4387             :   { 575,        3,      1,      4,      388,    0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #575 = CEQI_B
    4388             :   { 576,        3,      1,      4,      388,    0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #576 = CEQI_D
    4389             :   { 577,        3,      1,      4,      388,    0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #577 = CEQI_H
    4390             :   { 578,        3,      1,      4,      388,    0, 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #578 = CEQI_W
    4391             :   { 579,        3,      1,      4,      388,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #579 = CEQ_B
    4392             :   { 580,        3,      1,      4,      388,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #580 = CEQ_D
    4393             :   { 581,        3,      1,      4,      388,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #581 = CEQ_H
    4394             :   { 582,        3,      1,      4,      388,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #582 = CEQ_W
    4395             :   { 583,        2,      1,      4,      37,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr },  // Inst #583 = CFC1
    4396             :   { 584,        2,      1,      4,      37,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr },  // Inst #584 = CFC1_MM
    4397             :   { 585,        2,      1,      4,      38,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr },  // Inst #585 = CFC2_MM
    4398             :   { 586,        2,      1,      4,      372,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #586 = CFCMSA
    4399             :   { 587,        2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #587 = CFTC1
    4400             :   { 588,        4,      1,      4,      39,     0, 0x1ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #588 = CINS
    4401             :   { 589,        4,      1,      4,      39,     0, 0x1ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #589 = CINS32
    4402             :   { 590,        4,      1,      4,      39,     0, 0x1ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr },  // Inst #590 = CINS64_32
    4403             :   { 591,        4,      1,      4,      39,     0, 0x1ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr },  // Inst #591 = CINS_i32
    4404             :   { 592,        2,      1,      4,      40,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #592 = CLASS_D
    4405             :   { 593,        2,      1,      4,      41,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #593 = CLASS_D_MMR6
    4406             :   { 594,        2,      1,      4,      41,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #594 = CLASS_S
    4407             :   { 595,        2,      1,      4,      41,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #595 = CLASS_S_MMR6
    4408             :   { 596,        3,      1,      4,      387,    0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #596 = CLEI_S_B
    4409             :   { 597,        3,      1,      4,      387,    0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #597 = CLEI_S_D
    4410             :   { 598,        3,      1,      4,      387,    0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #598 = CLEI_S_H
    4411             :   { 599,        3,      1,      4,      387,    0, 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #599 = CLEI_S_W
    4412             :   { 600,        3,      1,      4,      387,    0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #600 = CLEI_U_B
    4413             :   { 601,        3,      1,      4,      387,    0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #601 = CLEI_U_D
    4414             :   { 602,        3,      1,      4,      387,    0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #602 = CLEI_U_H
    4415             :   { 603,        3,      1,      4,      387,    0, 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #603 = CLEI_U_W
    4416             :   { 604,        3,      1,      4,      387,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #604 = CLE_S_B
    4417             :   { 605,        3,      1,      4,      387,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #605 = CLE_S_D
    4418             :   { 606,        3,      1,      4,      387,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #606 = CLE_S_H
    4419             :   { 607,        3,      1,      4,      387,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #607 = CLE_S_W
    4420             :   { 608,        3,      1,      4,      387,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #608 = CLE_U_B
    4421             :   { 609,        3,      1,      4,      387,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #609 = CLE_U_D
    4422             :   { 610,        3,      1,      4,      387,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #610 = CLE_U_H
    4423             :   { 611,        3,      1,      4,      387,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #611 = CLE_U_W
    4424             :   { 612,        2,      1,      4,      42,     0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #612 = CLO
    4425             :   { 613,        2,      1,      4,      42,     0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #613 = CLO_MM
    4426             :   { 614,        2,      1,      4,      42,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #614 = CLO_MMR6
    4427             :   { 615,        2,      1,      4,      42,     0, 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #615 = CLO_R6
    4428             :   { 616,        3,      1,      4,      386,    0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #616 = CLTI_S_B
    4429             :   { 617,        3,      1,      4,      386,    0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #617 = CLTI_S_D
    4430             :   { 618,        3,      1,      4,      386,    0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #618 = CLTI_S_H
    4431             :   { 619,        3,      1,      4,      386,    0, 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #619 = CLTI_S_W
    4432             :   { 620,        3,      1,      4,      386,    0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #620 = CLTI_U_B
    4433             :   { 621,        3,      1,      4,      386,    0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #621 = CLTI_U_D
    4434             :   { 622,        3,      1,      4,      386,    0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #622 = CLTI_U_H
    4435             :   { 623,        3,      1,      4,      386,    0, 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #623 = CLTI_U_W
    4436             :   { 624,        3,      1,      4,      386,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #624 = CLT_S_B
    4437             :   { 625,        3,      1,      4,      386,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #625 = CLT_S_D
    4438             :   { 626,        3,      1,      4,      386,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #626 = CLT_S_H
    4439             :   { 627,        3,      1,      4,      386,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #627 = CLT_S_W
    4440             :   { 628,        3,      1,      4,      386,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #628 = CLT_U_B
    4441             :   { 629,        3,      1,      4,      386,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #629 = CLT_U_D
    4442             :   { 630,        3,      1,      4,      386,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #630 = CLT_U_H
    4443             :   { 631,        3,      1,      4,      386,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #631 = CLT_U_W
    4444             :   { 632,        2,      1,      4,      43,     0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #632 = CLZ
    4445             :   { 633,        2,      1,      4,      43,     0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #633 = CLZ_MM
    4446             :   { 634,        2,      1,      4,      43,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #634 = CLZ_MMR6
    4447             :   { 635,        2,      1,      4,      43,     0, 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #635 = CLZ_R6
    4448             :   { 636,        3,      1,      4,      611,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo105, -1 ,nullptr },  // Inst #636 = CMPGDU_EQ_QB
    4449             :   { 637,        3,      1,      4,      774,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo105, -1 ,nullptr },  // Inst #637 = CMPGDU_EQ_QB_MMR2
    4450             :   { 638,        3,      1,      4,      612,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo105, -1 ,nullptr },  // Inst #638 = CMPGDU_LE_QB
    4451             :   { 639,        3,      1,      4,      775,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo105, -1 ,nullptr },  // Inst #639 = CMPGDU_LE_QB_MMR2
    4452             :   { 640,        3,      1,      4,      613,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo105, -1 ,nullptr },  // Inst #640 = CMPGDU_LT_QB
    4453             :   { 641,        3,      1,      4,      776,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo105, -1 ,nullptr },  // Inst #641 = CMPGDU_LT_QB_MMR2
    4454             :   { 642,        3,      1,      4,      510,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #642 = CMPGU_EQ_QB
    4455             :   { 643,        3,      1,      4,      657,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #643 = CMPGU_EQ_QB_MM
    4456             :   { 644,        3,      1,      4,      511,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #644 = CMPGU_LE_QB
    4457             :   { 645,        3,      1,      4,      658,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #645 = CMPGU_LE_QB_MM
    4458             :   { 646,        3,      1,      4,      512,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #646 = CMPGU_LT_QB
    4459             :   { 647,        3,      1,      4,      659,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #647 = CMPGU_LT_QB_MM
    4460             :   { 648,        2,      0,      4,      513,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo32, -1 ,nullptr },  // Inst #648 = CMPU_EQ_QB
    4461             :   { 649,        2,      0,      4,      660,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo32, -1 ,nullptr },  // Inst #649 = CMPU_EQ_QB_MM
    4462             :   { 650,        2,      0,      4,      514,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo32, -1 ,nullptr },  // Inst #650 = CMPU_LE_QB
    4463             :   { 651,        2,      0,      4,      661,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo32, -1 ,nullptr },  // Inst #651 = CMPU_LE_QB_MM
    4464             :   { 652,        2,      0,      4,      515,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo32, -1 ,nullptr },  // Inst #652 = CMPU_LT_QB
    4465             :   { 653,        2,      0,      4,      662,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo32, -1 ,nullptr },  // Inst #653 = CMPU_LT_QB_MM
    4466             :   { 654,        3,      1,      4,      44,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #654 = CMP_AF_D_MMR6
    4467             :   { 655,        3,      1,      4,      45,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #655 = CMP_AF_S_MMR6
    4468             :   { 656,        3,      1,      4,      393,    0, 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #656 = CMP_EQ_D
    4469             :   { 657,        3,      1,      4,      44,     0, 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #657 = CMP_EQ_D_MMR6
    4470             :   { 658,        2,      0,      4,      516,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo32, -1 ,nullptr },  // Inst #658 = CMP_EQ_PH
    4471             :   { 659,        2,      0,      4,      663,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo32, -1 ,nullptr },  // Inst #659 = CMP_EQ_PH_MM
    4472             :   { 660,        3,      1,      4,      394,    0, 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #660 = CMP_EQ_S
    4473             :   { 661,        3,      1,      4,      45,     0, 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #661 = CMP_EQ_S_MMR6
    4474             :   { 662,        3,      1,      4,      44,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #662 = CMP_F_D
    4475             :   { 663,        3,      1,      4,      45,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #663 = CMP_F_S
    4476             :   { 664,        3,      1,      4,      399,    0, 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #664 = CMP_LE_D
    4477             :   { 665,        3,      1,      4,      44,     0, 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #665 = CMP_LE_D_MMR6
    4478             :   { 666,        2,      0,      4,      517,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo32, -1 ,nullptr },  // Inst #666 = CMP_LE_PH
    4479             :   { 667,        2,      0,      4,      664,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo32, -1 ,nullptr },  // Inst #667 = CMP_LE_PH_MM
    4480             :   { 668,        3,      1,      4,      400,    0, 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #668 = CMP_LE_S
    4481             :   { 669,        3,      1,      4,      45,     0, 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #669 = CMP_LE_S_MMR6
    4482             :   { 670,        3,      1,      4,      395,    0, 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #670 = CMP_LT_D
    4483             :   { 671,        3,      1,      4,      44,     0, 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #671 = CMP_LT_D_MMR6
    4484             :   { 672,        2,      0,      4,      518,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo32, -1 ,nullptr },  // Inst #672 = CMP_LT_PH
    4485             :   { 673,        2,      0,      4,      665,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo32, -1 ,nullptr },  // Inst #673 = CMP_LT_PH_MM
    4486             :   { 674,        3,      1,      4,      396,    0, 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #674 = CMP_LT_S
    4487             :   { 675,        3,      1,      4,      45,     0, 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #675 = CMP_LT_S_MMR6
    4488             :   { 676,        3,      1,      4,      44,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #676 = CMP_SAF_D
    4489             :   { 677,        3,      1,      4,      44,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #677 = CMP_SAF_D_MMR6
    4490             :   { 678,        3,      1,      4,      45,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #678 = CMP_SAF_S
    4491             :   { 679,        3,      1,      4,      45,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #679 = CMP_SAF_S_MMR6
    4492             :   { 680,        3,      1,      4,      44,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #680 = CMP_SEQ_D
    4493             :   { 681,        3,      1,      4,      44,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #681 = CMP_SEQ_D_MMR6
    4494             :   { 682,        3,      1,      4,      45,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #682 = CMP_SEQ_S
    4495             :   { 683,        3,      1,      4,      45,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #683 = CMP_SEQ_S_MMR6
    4496             :   { 684,        3,      1,      4,      44,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #684 = CMP_SLE_D
    4497             :   { 685,        3,      1,      4,      44,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #685 = CMP_SLE_D_MMR6
    4498             :   { 686,        3,      1,      4,      45,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #686 = CMP_SLE_S
    4499             :   { 687,        3,      1,      4,      45,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #687 = CMP_SLE_S_MMR6
    4500             :   { 688,        3,      1,      4,      44,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #688 = CMP_SLT_D
    4501             :   { 689,        3,      1,      4,      44,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #689 = CMP_SLT_D_MMR6
    4502             :   { 690,        3,      1,      4,      45,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #690 = CMP_SLT_S
    4503             :   { 691,        3,      1,      4,      45,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #691 = CMP_SLT_S_MMR6
    4504             :   { 692,        3,      1,      4,      44,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #692 = CMP_SUEQ_D
    4505             :   { 693,        3,      1,      4,      44,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #693 = CMP_SUEQ_D_MMR6
    4506             :   { 694,        3,      1,      4,      45,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #694 = CMP_SUEQ_S
    4507             :   { 695,        3,      1,      4,      45,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #695 = CMP_SUEQ_S_MMR6
    4508             :   { 696,        3,      1,      4,      44,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #696 = CMP_SULE_D
    4509             :   { 697,        3,      1,      4,      44,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #697 = CMP_SULE_D_MMR6
    4510             :   { 698,        3,      1,      4,      45,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #698 = CMP_SULE_S
    4511             :   { 699,        3,      1,      4,      45,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #699 = CMP_SULE_S_MMR6
    4512             :   { 700,        3,      1,      4,      44,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #700 = CMP_SULT_D
    4513             :   { 701,        3,      1,      4,      44,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #701 = CMP_SULT_D_MMR6
    4514             :   { 702,        3,      1,      4,      45,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #702 = CMP_SULT_S
    4515             :   { 703,        3,      1,      4,      45,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #703 = CMP_SULT_S_MMR6
    4516             :   { 704,        3,      1,      4,      44,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #704 = CMP_SUN_D
    4517             :   { 705,        3,      1,      4,      44,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #705 = CMP_SUN_D_MMR6
    4518             :   { 706,        3,      1,      4,      45,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #706 = CMP_SUN_S
    4519             :   { 707,        3,      1,      4,      45,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #707 = CMP_SUN_S_MMR6
    4520             :   { 708,        3,      1,      4,      391,    0, 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #708 = CMP_UEQ_D
    4521             :   { 709,        3,      1,      4,      44,     0, 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #709 = CMP_UEQ_D_MMR6
    4522             :   { 710,        3,      1,      4,      392,    0, 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #710 = CMP_UEQ_S
    4523             :   { 711,        3,      1,      4,      45,     0, 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #711 = CMP_UEQ_S_MMR6
    4524             :   { 712,        3,      1,      4,      401,    0, 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #712 = CMP_ULE_D
    4525             :   { 713,        3,      1,      4,      44,     0, 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #713 = CMP_ULE_D_MMR6
    4526             :   { 714,        3,      1,      4,      402,    0, 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #714 = CMP_ULE_S
    4527             :   { 715,        3,      1,      4,      45,     0, 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #715 = CMP_ULE_S_MMR6
    4528             :   { 716,        3,      1,      4,      397,    0, 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #716 = CMP_ULT_D
    4529             :   { 717,        3,      1,      4,      44,     0, 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #717 = CMP_ULT_D_MMR6
    4530             :   { 718,        3,      1,      4,      398,    0, 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #718 = CMP_ULT_S
    4531             :   { 719,        3,      1,      4,      45,     0, 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #719 = CMP_ULT_S_MMR6
    4532             :   { 720,        3,      1,      4,      389,    0, 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #720 = CMP_UN_D
    4533             :   { 721,        3,      1,      4,      44,     0, 0x16ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #721 = CMP_UN_D_MMR6
    4534             :   { 722,        3,      1,      4,      390,    0, 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #722 = CMP_UN_S
    4535             :   { 723,        3,      1,      4,      45,     0, 0x16ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #723 = CMP_UN_S_MMR6
    4536             :   { 724,        3,      0,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #724 = CONSTPOOL_ENTRY
    4537             :   { 725,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #725 = COPY_FD_PSEUDO
    4538             :   { 726,        3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #726 = COPY_FW_PSEUDO
    4539             :   { 727,        3,      1,      4,      484,    0, 0x6ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr },  // Inst #727 = COPY_S_B
    4540             :   { 728,        3,      1,      4,      484,    0, 0x6ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #728 = COPY_S_D
    4541             :   { 729,        3,      1,      4,      484,    0, 0x6ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr },  // Inst #729 = COPY_S_H
    4542             :   { 730,        3,      1,      4,      484,    0, 0x6ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr },  // Inst #730 = COPY_S_W
    4543             :   { 731,        3,      1,      4,      483,    0, 0x6ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr },  // Inst #731 = COPY_U_B
    4544             :   { 732,        3,      1,      4,      483,    0, 0x6ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr },  // Inst #732 = COPY_U_H
    4545             :   { 733,        3,      1,      4,      483,    0, 0x6ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr },  // Inst #733 = COPY_U_W
    4546             :   { 734,        3,      1,      4,      46,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #734 = CRC32B
    4547             :   { 735,        3,      1,      4,      47,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #735 = CRC32CB
    4548             :   { 736,        3,      1,      4,      48,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #736 = CRC32CD
    4549             :   { 737,        3,      1,      4,      49,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #737 = CRC32CH
    4550             :   { 738,        3,      1,      4,      50,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #738 = CRC32CW
    4551             :   { 739,        3,      1,      4,      51,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #739 = CRC32D
    4552             :   { 740,        3,      1,      4,      52,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #740 = CRC32H
    4553             :   { 741,        3,      1,      4,      53,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #741 = CRC32W
    4554             :   { 742,        2,      1,      4,      54,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #742 = CTC1
    4555             :   { 743,        2,      1,      4,      54,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #743 = CTC1_MM
    4556             :   { 744,        2,      1,      4,      55,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #744 = CTC2_MM
    4557             :   { 745,        2,      0,      4,      372,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #745 = CTCMSA
    4558             :   { 746,        2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr },  // Inst #746 = CTTC1
    4559             :   { 747,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #747 = CVT_D32_S
    4560             :   { 748,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #748 = CVT_D32_S_MM
    4561             :   { 749,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #749 = CVT_D32_W
    4562             :   { 750,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #750 = CVT_D32_W_MM
    4563             :   { 751,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #751 = CVT_D64_L
    4564             :   { 752,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #752 = CVT_D64_S
    4565             :   { 753,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #753 = CVT_D64_S_MM
    4566             :   { 754,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #754 = CVT_D64_W
    4567             :   { 755,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #755 = CVT_D64_W_MM
    4568             :   { 756,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #756 = CVT_D_L_MMR6
    4569             :   { 757,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #757 = CVT_L_D64
    4570             :   { 758,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #758 = CVT_L_D64_MM
    4571             :   { 759,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #759 = CVT_L_D_MMR6
    4572             :   { 760,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #760 = CVT_L_S
    4573             :   { 761,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #761 = CVT_L_S_MM
    4574             :   { 762,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #762 = CVT_L_S_MMR6
    4575             :   { 763,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #763 = CVT_S_D32
    4576             :   { 764,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #764 = CVT_S_D32_MM
    4577             :   { 765,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr },  // Inst #765 = CVT_S_D64
    4578             :   { 766,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr },  // Inst #766 = CVT_S_D64_MM
    4579             :   { 767,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr },  // Inst #767 = CVT_S_L
    4580             :   { 768,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #768 = CVT_S_L_MMR6
    4581             :   { 769,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #769 = CVT_S_W
    4582             :   { 770,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #770 = CVT_S_W_MM
    4583             :   { 771,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #771 = CVT_S_W_MMR6
    4584             :   { 772,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #772 = CVT_W_D32
    4585             :   { 773,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #773 = CVT_W_D32_MM
    4586             :   { 774,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr },  // Inst #774 = CVT_W_D64
    4587             :   { 775,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr },  // Inst #775 = CVT_W_D64_MM
    4588             :   { 776,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #776 = CVT_W_S
    4589             :   { 777,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #777 = CVT_W_S_MM
    4590             :   { 778,        2,      1,      4,      56,     0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #778 = CVT_W_S_MMR6
    4591             :   { 779,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #779 = C_EQ_D32
    4592             :   { 780,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #780 = C_EQ_D32_MM
    4593             :   { 781,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #781 = C_EQ_D64
    4594             :   { 782,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #782 = C_EQ_D64_MM
    4595             :   { 783,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #783 = C_EQ_S
    4596             :   { 784,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #784 = C_EQ_S_MM
    4597             :   { 785,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #785 = C_F_D32
    4598             :   { 786,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #786 = C_F_D32_MM
    4599             :   { 787,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #787 = C_F_D64
    4600             :   { 788,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #788 = C_F_D64_MM
    4601             :   { 789,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #789 = C_F_S
    4602             :   { 790,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #790 = C_F_S_MM
    4603             :   { 791,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #791 = C_LE_D32
    4604             :   { 792,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #792 = C_LE_D32_MM
    4605             :   { 793,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #793 = C_LE_D64
    4606             :   { 794,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #794 = C_LE_D64_MM
    4607             :   { 795,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #795 = C_LE_S
    4608             :   { 796,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #796 = C_LE_S_MM
    4609             :   { 797,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #797 = C_LT_D32
    4610             :   { 798,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #798 = C_LT_D32_MM
    4611             :   { 799,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #799 = C_LT_D64
    4612             :   { 800,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #800 = C_LT_D64_MM
    4613             :   { 801,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #801 = C_LT_S
    4614             :   { 802,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #802 = C_LT_S_MM
    4615             :   { 803,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #803 = C_NGE_D32
    4616             :   { 804,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #804 = C_NGE_D32_MM
    4617             :   { 805,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #805 = C_NGE_D64
    4618             :   { 806,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #806 = C_NGE_D64_MM
    4619             :   { 807,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #807 = C_NGE_S
    4620             :   { 808,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #808 = C_NGE_S_MM
    4621             :   { 809,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #809 = C_NGLE_D32
    4622             :   { 810,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #810 = C_NGLE_D32_MM
    4623             :   { 811,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #811 = C_NGLE_D64
    4624             :   { 812,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #812 = C_NGLE_D64_MM
    4625             :   { 813,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #813 = C_NGLE_S
    4626             :   { 814,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #814 = C_NGLE_S_MM
    4627             :   { 815,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #815 = C_NGL_D32
    4628             :   { 816,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #816 = C_NGL_D32_MM
    4629             :   { 817,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #817 = C_NGL_D64
    4630             :   { 818,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #818 = C_NGL_D64_MM
    4631             :   { 819,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #819 = C_NGL_S
    4632             :   { 820,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #820 = C_NGL_S_MM
    4633             :   { 821,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #821 = C_NGT_D32
    4634             :   { 822,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #822 = C_NGT_D32_MM
    4635             :   { 823,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #823 = C_NGT_D64
    4636             :   { 824,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #824 = C_NGT_D64_MM
    4637             :   { 825,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #825 = C_NGT_S
    4638             :   { 826,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #826 = C_NGT_S_MM
    4639             :   { 827,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #827 = C_OLE_D32
    4640             :   { 828,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #828 = C_OLE_D32_MM
    4641             :   { 829,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #829 = C_OLE_D64
    4642             :   { 830,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #830 = C_OLE_D64_MM
    4643             :   { 831,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #831 = C_OLE_S
    4644             :   { 832,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #832 = C_OLE_S_MM
    4645             :   { 833,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #833 = C_OLT_D32
    4646             :   { 834,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #834 = C_OLT_D32_MM
    4647             :   { 835,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #835 = C_OLT_D64
    4648             :   { 836,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #836 = C_OLT_D64_MM
    4649             :   { 837,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #837 = C_OLT_S
    4650             :   { 838,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #838 = C_OLT_S_MM
    4651             :   { 839,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #839 = C_SEQ_D32
    4652             :   { 840,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #840 = C_SEQ_D32_MM
    4653             :   { 841,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #841 = C_SEQ_D64
    4654             :   { 842,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #842 = C_SEQ_D64_MM
    4655             :   { 843,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #843 = C_SEQ_S
    4656             :   { 844,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #844 = C_SEQ_S_MM
    4657             :   { 845,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #845 = C_SF_D32
    4658             :   { 846,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #846 = C_SF_D32_MM
    4659             :   { 847,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #847 = C_SF_D64
    4660             :   { 848,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #848 = C_SF_D64_MM
    4661             :   { 849,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #849 = C_SF_S
    4662             :   { 850,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #850 = C_SF_S_MM
    4663             :   { 851,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #851 = C_UEQ_D32
    4664             :   { 852,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #852 = C_UEQ_D32_MM
    4665             :   { 853,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #853 = C_UEQ_D64
    4666             :   { 854,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #854 = C_UEQ_D64_MM
    4667             :   { 855,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #855 = C_UEQ_S
    4668             :   { 856,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #856 = C_UEQ_S_MM
    4669             :   { 857,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #857 = C_ULE_D32
    4670             :   { 858,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #858 = C_ULE_D32_MM
    4671             :   { 859,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #859 = C_ULE_D64
    4672             :   { 860,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #860 = C_ULE_D64_MM
    4673             :   { 861,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #861 = C_ULE_S
    4674             :   { 862,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #862 = C_ULE_S_MM
    4675             :   { 863,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #863 = C_ULT_D32
    4676             :   { 864,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #864 = C_ULT_D32_MM
    4677             :   { 865,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #865 = C_ULT_D64
    4678             :   { 866,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #866 = C_ULT_D64_MM
    4679             :   { 867,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #867 = C_ULT_S
    4680             :   { 868,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #868 = C_ULT_S_MM
    4681             :   { 869,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #869 = C_UN_D32
    4682             :   { 870,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #870 = C_UN_D32_MM
    4683             :   { 871,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #871 = C_UN_D64
    4684             :   { 872,        3,      1,      4,      57,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #872 = C_UN_D64_MM
    4685             :   { 873,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #873 = C_UN_S
    4686             :   { 874,        3,      1,      4,      58,     0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #874 = C_UN_S_MM
    4687             :   { 875,        2,      0,      2,      13,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo122, -1 ,nullptr },  // Inst #875 = CmpRxRy16
    4688             :   { 876,        2,      0,      2,      13,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo58, -1 ,nullptr },  // Inst #876 = CmpiRxImm16
    4689             :   { 877,        2,      0,      4,      13,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo58, -1 ,nullptr },  // Inst #877 = CmpiRxImmX16
    4690             :   { 878,        1,      0,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #878 = Constant32
    4691             :   { 879,        3,      1,      4,      59,     0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #879 = DADD
    4692             :   { 880,        3,      1,      4,      60,     0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #880 = DADDi
    4693             :   { 881,        3,      1,      4,      61,     0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #881 = DADDiu
    4694             :   { 882,        3,      1,      4,      62,     0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #882 = DADDu
    4695             :   { 883,        3,      1,      4,      63,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #883 = DAHI
    4696             :   { 884,        4,      1,      4,      64,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr },  // Inst #884 = DALIGN
    4697             :   { 885,        3,      1,      4,      65,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #885 = DATI
    4698             :   { 886,        3,      1,      4,      66,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #886 = DAUI
    4699             :   { 887,        2,      1,      4,      67,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr },  // Inst #887 = DBITSWAP
    4700             :   { 888,        2,      1,      4,      68,     0, 0x1ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr },  // Inst #888 = DCLO
    4701             :   { 889,        2,      1,      4,      68,     0, 0x6ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr },  // Inst #889 = DCLO_R6
    4702             :   { 890,        2,      1,      4,      69,     0, 0x1ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr },  // Inst #890 = DCLZ
    4703             :   { 891,        2,      1,      4,      69,     0, 0x6ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr },  // Inst #891 = DCLZ_R6
    4704             :   { 892,        3,      1,      4,      70,     0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #892 = DDIV
    4705             :   { 893,        3,      1,      4,      71,     0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #893 = DDIVU
    4706             :   { 894,        0,      0,      4,      72,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #894 = DERET
    4707             :   { 895,        0,      0,      4,      72,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #895 = DERET_MM
    4708             :   { 896,        0,      0,      4,      72,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #896 = DERET_MMR6
    4709             :   { 897,        4,      1,      4,      73,     0, 0x1ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #897 = DEXT
    4710             :   { 898,        4,      1,      4,      73,     0, 0x1ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr },  // Inst #898 = DEXT64_32
    4711             :   { 899,        4,      1,      4,      73,     0, 0x1ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #899 = DEXTM
    4712             :   { 900,        4,      1,      4,      73,     0, 0x1ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #900 = DEXTU
    4713             :   { 901,        1,      1,      4,      74,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #901 = DI
    4714             :   { 902,        5,      1,      4,      39,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr },  // Inst #902 = DINS
    4715             :   { 903,        5,      1,      4,      39,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr },  // Inst #903 = DINSM
    4716             :   { 904,        5,      1,      4,      39,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr },  // Inst #904 = DINSU
    4717             :   { 905,        3,      1,      4,      75,     0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #905 = DIV
    4718             :   { 906,        3,      1,      4,      76,     0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #906 = DIVU
    4719             :   { 907,        3,      1,      4,      76,     0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #907 = DIVU_MMR6
    4720             :   { 908,        3,      1,      4,      75,     0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #908 = DIV_MMR6
    4721             :   { 909,        3,      1,      4,      446,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #909 = DIV_S_B
    4722             :   { 910,        3,      1,      4,      446,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #910 = DIV_S_D
    4723             :   { 911,        3,      1,      4,      446,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #911 = DIV_S_H
    4724             :   { 912,        3,      1,      4,      446,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #912 = DIV_S_W
    4725             :   { 913,        3,      1,      4,      446,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #913 = DIV_U_B
    4726             :   { 914,        3,      1,      4,      446,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #914 = DIV_U_D
    4727             :   { 915,        3,      1,      4,      446,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #915 = DIV_U_H
    4728             :   { 916,        3,      1,      4,      446,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #916 = DIV_U_W
    4729             :   { 917,        1,      1,      4,      74,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #917 = DI_MM
    4730             :   { 918,        1,      1,      4,      74,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #918 = DI_MMR6
    4731             :   { 919,        4,      1,      4,      77,     0, 0x6ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr },  // Inst #919 = DLSA
    4732             :   { 920,        4,      1,      4,      77,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr },  // Inst #920 = DLSA_R6
    4733             :   { 921,        3,      1,      4,      78,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr },  // Inst #921 = DMFC0
    4734             :   { 922,        2,      1,      4,      79,     0|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr },  // Inst #922 = DMFC1
    4735             :   { 923,        3,      1,      4,      80,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #923 = DMFC2
    4736             :   { 924,        2,      2,      4,      80,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr },  // Inst #924 = DMFC2_OCTEON
    4737             :   { 925,        3,      1,      4,      81,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr },  // Inst #925 = DMFGC0
    4738             :   { 926,        3,      1,      4,      82,     0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #926 = DMOD
    4739             :   { 927,        3,      1,      4,      83,     0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #927 = DMODU
    4740             :   { 928,        1,      1,      4,      84,     0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #928 = DMT
    4741             :   { 929,        3,      1,      4,      85,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #929 = DMTC0
    4742             :   { 930,        2,      1,      4,      86,     0|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr },  // Inst #930 = DMTC1
    4743             :   { 931,        3,      1,      4,      87,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr },  // Inst #931 = DMTC2
    4744             :   { 932,        2,      2,      4,      87,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr },  // Inst #932 = DMTC2_OCTEON
    4745             :   { 933,        3,      1,      4,      88,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #933 = DMTGC0
    4746             :   { 934,        3,      1,      4,      89,     0, 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #934 = DMUH
    4747             :   { 935,        3,      1,      4,      90,     0, 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #935 = DMUHU
    4748             :   { 936,        3,      1,      4,      91,     0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, ImplicitList9, OperandInfo51, -1 ,nullptr },  // Inst #936 = DMUL
    4749             :   { 937,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #937 = DMULImmMacro
    4750             :   { 938,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #938 = DMULMacro
    4751             :   { 939,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #939 = DMULOMacro
    4752             :   { 940,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #940 = DMULOUMacro
    4753             :   { 941,        2,      0,      4,      92,     0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList10, OperandInfo125, -1 ,nullptr },  // Inst #941 = DMULT
    4754             :   { 942,        2,      0,      4,      93,     0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList10, OperandInfo125, -1 ,nullptr },  // Inst #942 = DMULTu
    4755             :   { 943,        3,      1,      4,      91,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #943 = DMULU
    4756             :   { 944,        3,      1,      4,      91,     0, 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #944 = DMUL_R6
    4757             :   { 945,        3,      1,      4,      473,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #945 = DOTP_S_D
    4758             :   { 946,        3,      1,      4,      473,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #946 = DOTP_S_H
    4759             :   { 947,        3,      1,      4,      473,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #947 = DOTP_S_W
    4760             :   { 948,        3,      1,      4,      473,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #948 = DOTP_U_D
    4761             :   { 949,        3,      1,      4,      473,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #949 = DOTP_U_H
    4762             :   { 950,        3,      1,      4,      473,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #950 = DOTP_U_W
    4763             :   { 951,        4,      1,      4,      471,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #951 = DPADD_S_D
    4764             :   { 952,        4,      1,      4,      471,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr },  // Inst #952 = DPADD_S_H
    4765             :   { 953,        4,      1,      4,      471,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr },  // Inst #953 = DPADD_S_W
    4766             :   { 954,        4,      1,      4,      471,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #954 = DPADD_U_D
    4767             :   { 955,        4,      1,      4,      471,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr },  // Inst #955 = DPADD_U_H
    4768             :   { 956,        4,      1,      4,      471,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr },  // Inst #956 = DPADD_U_W
    4769             :   { 957,        4,      1,      4,      615,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList11, OperandInfo140, -1 ,nullptr },  // Inst #957 = DPAQX_SA_W_PH
    4770             :   { 958,        4,      1,      4,      778,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList11, OperandInfo140, -1 ,nullptr },  // Inst #958 = DPAQX_SA_W_PH_MMR2
    4771             :   { 959,        4,      1,      4,      616,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList11, OperandInfo140, -1 ,nullptr },  // Inst #959 = DPAQX_S_W_PH
    4772             :   { 960,        4,      1,      4,      779,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList11, OperandInfo140, -1 ,nullptr },  // Inst #960 = DPAQX_S_W_PH_MMR2
    4773             :   { 961,        4,      1,      4,      519,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList11, OperandInfo140, -1 ,nullptr },  // Inst #961 = DPAQ_SA_L_W
    4774             :   { 962,        4,      1,      4,      666,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList11, OperandInfo140, -1 ,nullptr },  // Inst #962 = DPAQ_SA_L_W_MM
    4775             :   { 963,        4,      1,      4,      520,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList11, OperandInfo140, -1 ,nullptr },  // Inst #963 = DPAQ_S_W_PH
    4776             :   { 964,        4,      1,      4,      667,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList11, OperandInfo140, -1 ,nullptr },  // Inst #964 = DPAQ_S_W_PH_MM
    4777             :   { 965,        4,      1,      4,      521,    0, 0x6ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #965 = DPAU_H_QBL
    4778             :   { 966,        4,      1,      4,      668,    0, 0x6ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #966 = DPAU_H_QBL_MM
    4779             :   { 967,        4,      1,      4,      522,    0, 0x6ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #967 = DPAU_H_QBR
    4780             :   { 968,        4,      1,      4,      669,    0, 0x6ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #968 = DPAU_H_QBR_MM
    4781             :   { 969,        4,      1,      4,      617,    0, 0x6ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #969 = DPAX_W_PH
    4782             :   { 970,        4,      1,      4,      780,    0, 0x6ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #970 = DPAX_W_PH_MMR2
    4783             :   { 971,        4,      1,      4,      614,    0, 0x6ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #971 = DPA_W_PH
    4784             :   { 972,        4,      1,      4,      777,    0, 0x6ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #972 = DPA_W_PH_MMR2
    4785             :   { 973,        2,      1,      4,      94,     0, 0x1ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr },  // Inst #973 = DPOP
    4786             :   { 974,        4,      1,      4,      620,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList11, OperandInfo140, -1 ,nullptr },  // Inst #974 = DPSQX_SA_W_PH
    4787             :   { 975,        4,      1,      4,      783,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList11, OperandInfo140, -1 ,nullptr },  // Inst #975 = DPSQX_SA_W_PH_MMR2
    4788             :   { 976,        4,      1,      4,      619,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList11, OperandInfo140, -1 ,nullptr },  // Inst #976 = DPSQX_S_W_PH
    4789             :   { 977,        4,      1,      4,      782,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList11, OperandInfo140, -1 ,nullptr },  // Inst #977 = DPSQX_S_W_PH_MMR2
    4790             :   { 978,        4,      1,      4,      523,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList11, OperandInfo140, -1 ,nullptr },  // Inst #978 = DPSQ_SA_L_W
    4791             :   { 979,        4,      1,      4,      670,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList11, OperandInfo140, -1 ,nullptr },  // Inst #979 = DPSQ_SA_L_W_MM
    4792             :   { 980,        4,      1,      4,      524,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList11, OperandInfo140, -1 ,nullptr },  // Inst #980 = DPSQ_S_W_PH
    4793             :   { 981,        4,      1,      4,      671,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList11, OperandInfo140, -1 ,nullptr },  // Inst #981 = DPSQ_S_W_PH_MM
    4794             :   { 982,        4,      1,      4,      472,    0, 0x6ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #982 = DPSUB_S_D
    4795             :   { 983,        4,      1,      4,      472,    0, 0x6ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr },  // Inst #983 = DPSUB_S_H
    4796             :   { 984,        4,      1,      4,      472,    0, 0x6ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr },  // Inst #984 = DPSUB_S_W
    4797             :   { 985,        4,      1,      4,      472,    0, 0x6ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #985 = DPSUB_U_D
    4798             :   { 986,        4,      1,      4,      472,    0, 0x6ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr },  // Inst #986 = DPSUB_U_H
    4799             :   { 987,        4,      1,      4,      472,    0, 0x6ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr },  // Inst #987 = DPSUB_U_W
    4800             :   { 988,        4,      1,      4,      525,    0, 0x6ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #988 = DPSU_H_QBL
    4801             :   { 989,        4,      1,      4,      672,    0, 0x6ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #989 = DPSU_H_QBL_MM
    4802             :   { 990,        4,      1,      4,      526,    0, 0x6ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #990 = DPSU_H_QBR
    4803             :   { 991,        4,      1,      4,      673,    0, 0x6ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #991 = DPSU_H_QBR_MM
    4804             :   { 992,        4,      1,      4,      621,    0, 0x6ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #992 = DPSX_W_PH
    4805             :   { 993,        4,      1,      4,      784,    0, 0x6ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #993 = DPSX_W_PH_MMR2
    4806             :   { 994,        4,      1,      4,      618,    0, 0x6ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #994 = DPS_W_PH
    4807             :   { 995,        4,      1,      4,      781,    0, 0x6ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #995 = DPS_W_PH_MMR2
    4808             :   { 996,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #996 = DROL
    4809             :   { 997,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #997 = DROLImm
    4810             :   { 998,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #998 = DROR
    4811             :   { 999,        3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #999 = DRORImm
    4812             :   { 1000,       3,      1,      4,      95,     0, 0x1ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #1000 = DROTR
    4813             :   { 1001,       3,      1,      4,      96,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #1001 = DROTR32
    4814             :   { 1002,       3,      1,      4,      97,     0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr },  // Inst #1002 = DROTRV
    4815             :   { 1003,       2,      1,      4,      98,     0, 0x1ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr },  // Inst #1003 = DSBH
    4816             :   { 1004,       2,      0,      4,      70,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList10, OperandInfo125, -1 ,nullptr },  // Inst #1004 = DSDIV
    4817             :   { 1005,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #1005 = DSDivIMacro
    4818             :   { 1006,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #1006 = DSDivMacro
    4819             :   { 1007,       2,      1,      4,      99,     0, 0x1ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr },  // Inst #1007 = DSHD
    4820             :   { 1008,       3,      1,      4,      100,    0, 0x1ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #1008 = DSLL
    4821             :   { 1009,       3,      1,      4,      101,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #1009 = DSLL32
    4822             :   { 1010,       2,      1,      4,      100,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr },  // Inst #1010 = DSLL64_32
    4823             :   { 1011,       3,      1,      4,      102,    0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr },  // Inst #1011 = DSLLV
    4824             :   { 1012,       3,      1,      4,      103,    0, 0x1ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #1012 = DSRA
    4825             :   { 1013,       3,      1,      4,      104,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #1013 = DSRA32
    4826             :   { 1014,       3,      1,      4,      105,    0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr },  // Inst #1014 = DSRAV
    4827             :   { 1015,       3,      1,      4,      106,    0, 0x1ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #1015 = DSRL
    4828             :   { 1016,       3,      1,      4,      107,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #1016 = DSRL32
    4829             :   { 1017,       3,      1,      4,      108,    0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr },  // Inst #1017 = DSRLV
    4830             :   { 1018,       3,      1,      4,      109,    0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #1018 = DSUB
    4831             :   { 1019,       3,      1,      4,      110,    0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #1019 = DSUBu
    4832             :   { 1020,       2,      0,      4,      71,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList10, OperandInfo125, -1 ,nullptr },  // Inst #1020 = DUDIV
    4833             :   { 1021,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #1021 = DUDivIMacro
    4834             :   { 1022,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #1022 = DUDivMacro
    4835             :   { 1023,       1,      1,      4,      111,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1023 = DVP
    4836             :   { 1024,       1,      1,      4,      112,    0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1024 = DVPE
    4837             :   { 1025,       1,      1,      4,      111,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1025 = DVP_MMR6
    4838             :   { 1026,       2,      0,      2,      13,     0, 0x0ULL, nullptr, ImplicitList12, OperandInfo122, -1 ,nullptr },  // Inst #1026 = DivRxRy16
    4839             :   { 1027,       2,      0,      2,      13,     0, 0x0ULL, nullptr, ImplicitList12, OperandInfo122, -1 ,nullptr },  // Inst #1027 = DivuRxRy16
    4840             :   { 1028,       0,      0,      4,      113,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1028 = EHB
    4841             :   { 1029,       0,      0,      4,      113,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1029 = EHB_MM
    4842             :   { 1030,       0,      0,      4,      113,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1030 = EHB_MMR6
    4843             :   { 1031,       1,      1,      4,      114,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1031 = EI
    4844             :   { 1032,       1,      1,      4,      114,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1032 = EI_MM
    4845             :   { 1033,       1,      1,      4,      114,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1033 = EI_MMR6
    4846             :   { 1034,       1,      1,      4,      115,    0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1034 = EMT
    4847             :   { 1035,       0,      0,      4,      116,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1035 = ERET
    4848             :   { 1036,       0,      0,      4,      117,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1036 = ERETNC
    4849             :   { 1037,       0,      0,      4,      117,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1037 = ERETNC_MMR6
    4850             :   { 1038,       0,      0,      4,      116,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1038 = ERET_MM
    4851             :   { 1039,       0,      0,      4,      116,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1039 = ERET_MMR6
    4852             :   { 1040,       0,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1040 = ERet
    4853             :   { 1041,       1,      1,      4,      118,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1041 = EVP
    4854             :   { 1042,       1,      1,      4,      119,    0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1042 = EVPE
    4855             :   { 1043,       1,      1,      4,      118,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1043 = EVP_MMR6
    4856             :   { 1044,       4,      1,      4,      73,     0, 0x1ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr },  // Inst #1044 = EXT
    4857             :   { 1045,       3,      1,      4,      530,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList6, ImplicitList13, OperandInfo143, -1 ,nullptr },  // Inst #1045 = EXTP
    4858             :   { 1046,       3,      1,      4,      528,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList6, ImplicitList14, OperandInfo143, -1 ,nullptr },  // Inst #1046 = EXTPDP
    4859             :   { 1047,       3,      1,      4,      527,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList6, ImplicitList14, OperandInfo144, -1 ,nullptr },  // Inst #1047 = EXTPDPV
    4860             :   { 1048,       3,      1,      4,      674,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList6, ImplicitList14, OperandInfo144, -1 ,nullptr },  // Inst #1048 = EXTPDPV_MM
    4861             :   { 1049,       3,      1,      4,      675,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList6, ImplicitList14, OperandInfo143, -1 ,nullptr },  // Inst #1049 = EXTPDP_MM
    4862             :   { 1050,       3,      1,      4,      529,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList6, ImplicitList13, OperandInfo144, -1 ,nullptr },  // Inst #1050 = EXTPV
    4863             :   { 1051,       3,      1,      4,      676,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList6, ImplicitList13, OperandInfo144, -1 ,nullptr },  // Inst #1051 = EXTPV_MM
    4864             :   { 1052,       3,      1,      4,      677,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList6, ImplicitList13, OperandInfo143, -1 ,nullptr },  // Inst #1052 = EXTP_MM
    4865             :   { 1053,       3,      1,      4,      487,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList15, OperandInfo144, -1 ,nullptr },  // Inst #1053 = EXTRV_RS_W
    4866             :   { 1054,       3,      1,      4,      678,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList15, OperandInfo144, -1 ,nullptr },  // Inst #1054 = EXTRV_RS_W_MM
    4867             :   { 1055,       3,      1,      4,      488,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList15, OperandInfo144, -1 ,nullptr },  // Inst #1055 = EXTRV_R_W
    4868             :   { 1056,       3,      1,      4,      679,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList15, OperandInfo144, -1 ,nullptr },  // Inst #1056 = EXTRV_R_W_MM
    4869             :   { 1057,       3,      1,      4,      489,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList15, OperandInfo144, -1 ,nullptr },  // Inst #1057 = EXTRV_S_H
    4870             :   { 1058,       3,      1,      4,      680,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList15, OperandInfo144, -1 ,nullptr },  // Inst #1058 = EXTRV_S_H_MM
    4871             :   { 1059,       3,      1,      4,      490,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList15, OperandInfo144, -1 ,nullptr },  // Inst #1059 = EXTRV_W
    4872             :   { 1060,       3,      1,      4,      681,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList15, OperandInfo144, -1 ,nullptr },  // Inst #1060 = EXTRV_W_MM
    4873             :   { 1061,       3,      1,      4,      491,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList15, OperandInfo143, -1 ,nullptr },  // Inst #1061 = EXTR_RS_W
    4874             :   { 1062,       3,      1,      4,      682,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList15, OperandInfo143, -1 ,nullptr },  // Inst #1062 = EXTR_RS_W_MM
    4875             :   { 1063,       3,      1,      4,      492,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList15, OperandInfo143, -1 ,nullptr },  // Inst #1063 = EXTR_R_W
    4876             :   { 1064,       3,      1,      4,      683,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList15, OperandInfo143, -1 ,nullptr },  // Inst #1064 = EXTR_R_W_MM
    4877             :   { 1065,       3,      1,      4,      493,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList15, OperandInfo143, -1 ,nullptr },  // Inst #1065 = EXTR_S_H
    4878             :   { 1066,       3,      1,      4,      684,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList15, OperandInfo143, -1 ,nullptr },  // Inst #1066 = EXTR_S_H_MM
    4879             :   { 1067,       3,      1,      4,      494,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList15, OperandInfo143, -1 ,nullptr },  // Inst #1067 = EXTR_W
    4880             :   { 1068,       3,      1,      4,      685,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList15, OperandInfo143, -1 ,nullptr },  // Inst #1068 = EXTR_W_MM
    4881             :   { 1069,       4,      1,      4,      73,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #1069 = EXTS
    4882             :   { 1070,       4,      1,      4,      73,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #1070 = EXTS32
    4883             :   { 1071,       4,      1,      4,      73,     0, 0x1ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr },  // Inst #1071 = EXT_MM
    4884             :   { 1072,       4,      1,      4,      73,     0, 0x1ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr },  // Inst #1072 = EXT_MMR6
    4885             :   { 1073,       3,      1,      4,      120,    0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #1073 = ExtractElementF64
    4886             :   { 1074,       3,      1,      4,      120,    0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #1074 = ExtractElementF64_64
    4887             :   { 1075,       2,      1,      4,      420,    0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #1075 = FABS_D
    4888             :   { 1076,       2,      1,      4,      121,    0, 0x4ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #1076 = FABS_D32
    4889             :   { 1077,       2,      1,      4,      122,    0, 0x4ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #1077 = FABS_D32_MM
    4890             :   { 1078,       2,      1,      4,      121,    0, 0x4ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #1078 = FABS_D64
    4891             :   { 1079,       2,      1,      4,      122,    0, 0x4ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #1079 = FABS_D64_MM
    4892             :   { 1080,       2,      1,      4,      121,    0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1080 = FABS_S
    4893             :   { 1081,       2,      1,      4,      121,    0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1081 = FABS_S_MM
    4894             :   { 1082,       2,      1,      4,      420,    0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #1082 = FABS_W
    4895             :   { 1083,       3,      1,      4,      469,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1083 = FADD_D
    4896             :   { 1084,       3,      1,      4,      123,    0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #1084 = FADD_D32
    4897             :   { 1085,       3,      1,      4,      123,    0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #1085 = FADD_D32_MM
    4898             :   { 1086,       3,      1,      4,      123,    0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #1086 = FADD_D64
    4899             :   { 1087,       3,      1,      4,      123,    0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #1087 = FADD_D64_MM
    4900             :   { 1088,       3,      1,      4,      124,    0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #1088 = FADD_S
    4901             :   { 1089,       3,      1,      4,      124,    0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #1089 = FADD_S_MM
    4902             :   { 1090,       3,      1,      4,      124,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #1090 = FADD_S_MMR6
    4903             :   { 1091,       3,      1,      4,      469,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1091 = FADD_W
    4904             :   { 1092,       3,      1,      4,      409,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1092 = FCAF_D
    4905             :   { 1093,       3,      1,      4,      409,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1093 = FCAF_W
    4906             :   { 1094,       3,      1,      4,      410,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1094 = FCEQ_D
    4907             :   { 1095,       3,      1,      4,      410,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1095 = FCEQ_W
    4908             :   { 1096,       2,      1,      4,      431,    0, 0x6ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #1096 = FCLASS_D
    4909             :   { 1097,       2,      1,      4,      431,    0, 0x6ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #1097 = FCLASS_W
    4910             :   { 1098,       3,      1,      4,      411,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1098 = FCLE_D
    4911             :   { 1099,       3,      1,      4,      411,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1099 = FCLE_W
    4912             :   { 1100,       3,      1,      4,      412,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1100 = FCLT_D
    4913             :   { 1101,       3,      1,      4,      412,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1101 = FCLT_W
    4914             :   { 1102,       3,      0,      4,      57,     0, 0x84ULL, nullptr, ImplicitList16, OperandInfo153, -1 ,nullptr },  // Inst #1102 = FCMP_D32
    4915             :   { 1103,       3,      0,      4,      57,     0, 0x84ULL, nullptr, ImplicitList16, OperandInfo153, -1 ,nullptr },  // Inst #1103 = FCMP_D32_MM
    4916             :   { 1104,       3,      0,      4,      57,     0, 0x84ULL, nullptr, ImplicitList16, OperandInfo154, -1 ,nullptr },  // Inst #1104 = FCMP_D64
    4917             :   { 1105,       3,      0,      4,      58,     0, 0x84ULL, nullptr, ImplicitList16, OperandInfo155, -1 ,nullptr },  // Inst #1105 = FCMP_S32
    4918             :   { 1106,       3,      0,      4,      58,     0, 0x84ULL, nullptr, ImplicitList16, OperandInfo155, -1 ,nullptr },  // Inst #1106 = FCMP_S32_MM
    4919             :   { 1107,       3,      1,      4,      413,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1107 = FCNE_D
    4920             :   { 1108,       3,      1,      4,      413,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1108 = FCNE_W
    4921             :   { 1109,       3,      1,      4,      414,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1109 = FCOR_D
    4922             :   { 1110,       3,      1,      4,      414,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1110 = FCOR_W
    4923             :   { 1111,       3,      1,      4,      415,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1111 = FCUEQ_D
    4924             :   { 1112,       3,      1,      4,      415,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1112 = FCUEQ_W
    4925             :   { 1113,       3,      1,      4,      416,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1113 = FCULE_D
    4926             :   { 1114,       3,      1,      4,      416,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1114 = FCULE_W
    4927             :   { 1115,       3,      1,      4,      417,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1115 = FCULT_D
    4928             :   { 1116,       3,      1,      4,      417,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1116 = FCULT_W
    4929             :   { 1117,       3,      1,      4,      418,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1117 = FCUNE_D
    4930             :   { 1118,       3,      1,      4,      418,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1118 = FCUNE_W
    4931             :   { 1119,       3,      1,      4,      419,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1119 = FCUN_D
    4932             :   { 1120,       3,      1,      4,      419,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1120 = FCUN_W
    4933             :   { 1121,       3,      1,      4,      465,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1121 = FDIV_D
    4934             :   { 1122,       3,      1,      4,      125,    0, 0x4ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #1122 = FDIV_D32
    4935             :   { 1123,       3,      1,      4,      125,    0, 0x4ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #1123 = FDIV_D32_MM
    4936             :   { 1124,       3,      1,      4,      125,    0, 0x4ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #1124 = FDIV_D64
    4937             :   { 1125,       3,      1,      4,      125,    0, 0x4ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #1125 = FDIV_D64_MM
    4938             :   { 1126,       3,      1,      4,      126,    0, 0x4ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #1126 = FDIV_S
    4939             :   { 1127,       3,      1,      4,      126,    0, 0x4ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #1127 = FDIV_S_MM
    4940             :   { 1128,       3,      1,      4,      126,    0, 0x6ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #1128 = FDIV_S_MMR6
    4941             :   { 1129,       3,      1,      4,      464,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1129 = FDIV_W
    4942             :   { 1130,       3,      1,      4,      428,    0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #1130 = FEXDO_H
    4943             :   { 1131,       3,      1,      4,      428,    0, 0x6ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr },  // Inst #1131 = FEXDO_W
    4944             :   { 1132,       3,      1,      4,      385,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1132 = FEXP2_D
    4945             :   { 1133,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #1133 = FEXP2_D_1_PSEUDO
    4946             :   { 1134,       3,      1,      4,      385,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1134 = FEXP2_W
    4947             :   { 1135,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #1135 = FEXP2_W_1_PSEUDO
    4948             :   { 1136,       2,      1,      4,      429,    0, 0x6ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr },  // Inst #1136 = FEXUPL_D
    4949             :   { 1137,       2,      1,      4,      429,    0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr },  // Inst #1137 = FEXUPL_W
    4950             :   { 1138,       2,      1,      4,      430,    0, 0x6ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr },  // Inst #1138 = FEXUPR_D
    4951             :   { 1139,       2,      1,      4,      430,    0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr },  // Inst #1139 = FEXUPR_W
    4952             :   { 1140,       2,      1,      4,      421,    0, 0x6ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #1140 = FFINT_S_D
    4953             :   { 1141,       2,      1,      4,      421,    0, 0x6ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #1141 = FFINT_S_W
    4954             :   { 1142,       2,      1,      4,      421,    0, 0x6ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #1142 = FFINT_U_D
    4955             :   { 1143,       2,      1,      4,      421,    0, 0x6ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #1143 = FFINT_U_W
    4956             :   { 1144,       2,      1,      4,      422,    0, 0x6ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr },  // Inst #1144 = FFQL_D
    4957             :   { 1145,       2,      1,      4,      422,    0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr },  // Inst #1145 = FFQL_W
    4958             :   { 1146,       2,      1,      4,      423,    0, 0x6ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr },  // Inst #1146 = FFQR_D
    4959             :   { 1147,       2,      1,      4,      423,    0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr },  // Inst #1147 = FFQR_W
    4960             :   { 1148,       2,      1,      4,      379,    0, 0x6ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr },  // Inst #1148 = FILL_B
    4961             :   { 1149,       2,      1,      4,      379,    0, 0x6ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #1149 = FILL_D
    4962             :   { 1150,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr },  // Inst #1150 = FILL_FD_PSEUDO
    4963             :   { 1151,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr },  // Inst #1151 = FILL_FW_PSEUDO
    4964             :   { 1152,       2,      1,      4,      379,    0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #1152 = FILL_H
    4965             :   { 1153,       2,      1,      4,      379,    0, 0x6ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr },  // Inst #1153 = FILL_W
    4966             :   { 1154,       2,      1,      4,      436,    0, 0x6ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #1154 = FLOG2_D
    4967             :   { 1155,       2,      1,      4,      436,    0, 0x6ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #1155 = FLOG2_W
    4968             :   { 1156,       2,      1,      4,      127,    0, 0x4ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #1156 = FLOOR_L_D64
    4969             :   { 1157,       2,      1,      4,      127,    0, 0x4ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #1157 = FLOOR_L_D_MMR6
    4970             :   { 1158,       2,      1,      4,      127,    0, 0x4ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #1158 = FLOOR_L_S
    4971             :   { 1159,       2,      1,      4,      127,    0, 0x4ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #1159 = FLOOR_L_S_MMR6
    4972             :   { 1160,       2,      1,      4,      127,    0, 0x4ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #1160 = FLOOR_W_D32
    4973             :   { 1161,       2,      1,      4,      127,    0, 0x4ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr },  // Inst #1161 = FLOOR_W_D64
    4974             :   { 1162,       2,      1,      4,      127,    0, 0x4ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #1162 = FLOOR_W_D_MMR6
    4975             :   { 1163,       2,      1,      4,      127,    0, 0x4ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #1163 = FLOOR_W_MM
    4976             :   { 1164,       2,      1,      4,      127,    0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1164 = FLOOR_W_S
    4977             :   { 1165,       2,      1,      4,      127,    0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1165 = FLOOR_W_S_MM
    4978             :   { 1166,       2,      1,      4,      127,    0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1166 = FLOOR_W_S_MMR6
    4979             :   { 1167,       4,      1,      4,      462,    0, 0x6ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #1167 = FMADD_D
    4980             :   { 1168,       4,      1,      4,      462,    0, 0x6ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #1168 = FMADD_W
    4981             :   { 1169,       3,      1,      4,      432,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1169 = FMAX_A_D
    4982             :   { 1170,       3,      1,      4,      432,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1170 = FMAX_A_W
    4983             :   { 1171,       3,      1,      4,      433,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1171 = FMAX_D
    4984             :   { 1172,       3,      1,      4,      433,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1172 = FMAX_W
    4985             :   { 1173,       3,      1,      4,      434,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1173 = FMIN_A_D
    4986             :   { 1174,       3,      1,      4,      434,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1174 = FMIN_A_W
    4987             :   { 1175,       3,      1,      4,      435,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1175 = FMIN_D
    4988             :   { 1176,       3,      1,      4,      435,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1176 = FMIN_W
    4989             :   { 1177,       2,      1,      4,      128,    0, 0x4ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #1177 = FMOV_D32
    4990             :   { 1178,       2,      1,      4,      128,    0, 0x4ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #1178 = FMOV_D32_MM
    4991             :   { 1179,       2,      1,      4,      128,    0, 0x4ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #1179 = FMOV_D64
    4992             :   { 1180,       2,      1,      4,      128,    0, 0x4ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #1180 = FMOV_D64_MM
    4993             :   { 1181,       2,      1,      4,      129,    0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1181 = FMOV_S
    4994             :   { 1182,       2,      1,      4,      129,    0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1182 = FMOV_S_MM
    4995             :   { 1183,       2,      1,      4,      129,    0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1183 = FMOV_S_MMR6
    4996             :   { 1184,       4,      1,      4,      463,    0, 0x6ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #1184 = FMSUB_D
    4997             :   { 1185,       4,      1,      4,      463,    0, 0x6ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #1185 = FMSUB_W
    4998             :   { 1186,       3,      1,      4,      468,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1186 = FMUL_D
    4999             :   { 1187,       3,      1,      4,      130,    0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #1187 = FMUL_D32
    5000             :   { 1188,       3,      1,      4,      130,    0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #1188 = FMUL_D32_MM
    5001             :   { 1189,       3,      1,      4,      130,    0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #1189 = FMUL_D64
    5002             :   { 1190,       3,      1,      4,      130,    0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #1190 = FMUL_D64_MM
    5003             :   { 1191,       3,      1,      4,      131,    0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #1191 = FMUL_S
    5004             :   { 1192,       3,      1,      4,      131,    0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #1192 = FMUL_S_MM
    5005             :   { 1193,       3,      1,      4,      131,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #1193 = FMUL_S_MMR6
    5006             :   { 1194,       3,      1,      4,      468,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1194 = FMUL_W
    5007             :   { 1195,       2,      1,      4,      132,    0, 0x4ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #1195 = FNEG_D32
    5008             :   { 1196,       2,      1,      4,      132,    0, 0x4ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #1196 = FNEG_D32_MM
    5009             :   { 1197,       2,      1,      4,      132,    0, 0x4ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #1197 = FNEG_D64
    5010             :   { 1198,       2,      1,      4,      132,    0, 0x4ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #1198 = FNEG_D64_MM
    5011             :   { 1199,       2,      1,      4,      132,    0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1199 = FNEG_S
    5012             :   { 1200,       2,      1,      4,      132,    0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1200 = FNEG_S_MM
    5013             :   { 1201,       2,      1,      4,      132,    0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1201 = FNEG_S_MMR6
    5014             :   { 1202,       3,      2,      4,      133,    0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1202 = FORK
    5015             :   { 1203,       2,      1,      4,      460,    0, 0x6ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #1203 = FRCP_D
    5016             :   { 1204,       2,      1,      4,      460,    0, 0x6ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #1204 = FRCP_W
    5017             :   { 1205,       2,      1,      4,      425,    0, 0x6ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #1205 = FRINT_D
    5018             :   { 1206,       2,      1,      4,      425,    0, 0x6ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #1206 = FRINT_W
    5019             :   { 1207,       2,      1,      4,      461,    0, 0x6ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #1207 = FRSQRT_D
    5020             :   { 1208,       2,      1,      4,      461,    0, 0x6ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #1208 = FRSQRT_W
    5021             :   { 1209,       3,      1,      4,      403,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1209 = FSAF_D
    5022             :   { 1210,       3,      1,      4,      403,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1210 = FSAF_W
    5023             :   { 1211,       3,      1,      4,      403,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1211 = FSEQ_D
    5024             :   { 1212,       3,      1,      4,      403,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1212 = FSEQ_W
    5025             :   { 1213,       3,      1,      4,      403,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1213 = FSLE_D
    5026             :   { 1214,       3,      1,      4,      403,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1214 = FSLE_W
    5027             :   { 1215,       3,      1,      4,      403,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1215 = FSLT_D
    5028             :   { 1216,       3,      1,      4,      403,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1216 = FSLT_W
    5029             :   { 1217,       3,      1,      4,      403,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1217 = FSNE_D
    5030             :   { 1218,       3,      1,      4,      403,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1218 = FSNE_W
    5031             :   { 1219,       3,      1,      4,      403,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1219 = FSOR_D
    5032             :   { 1220,       3,      1,      4,      403,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1220 = FSOR_W
    5033             :   { 1221,       2,      1,      4,      467,    0, 0x6ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #1221 = FSQRT_D
    5034             :   { 1222,       2,      1,      4,      122,    0, 0x4ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #1222 = FSQRT_D32
    5035             :   { 1223,       2,      1,      4,      122,    0, 0x4ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #1223 = FSQRT_D32_MM
    5036             :   { 1224,       2,      1,      4,      122,    0, 0x4ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #1224 = FSQRT_D64
    5037             :   { 1225,       2,      1,      4,      122,    0, 0x4ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #1225 = FSQRT_D64_MM
    5038             :   { 1226,       2,      1,      4,      134,    0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1226 = FSQRT_S
    5039             :   { 1227,       2,      1,      4,      134,    0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1227 = FSQRT_S_MM
    5040             :   { 1228,       2,      1,      4,      466,    0, 0x6ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #1228 = FSQRT_W
    5041             :   { 1229,       3,      1,      4,      470,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1229 = FSUB_D
    5042             :   { 1230,       3,      1,      4,      135,    0, 0x4ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #1230 = FSUB_D32
    5043             :   { 1231,       3,      1,      4,      135,    0, 0x4ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #1231 = FSUB_D32_MM
    5044             :   { 1232,       3,      1,      4,      135,    0, 0x4ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #1232 = FSUB_D64
    5045             :   { 1233,       3,      1,      4,      135,    0, 0x4ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #1233 = FSUB_D64_MM
    5046             :   { 1234,       3,      1,      4,      136,    0, 0x4ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #1234 = FSUB_S
    5047             :   { 1235,       3,      1,      4,      136,    0, 0x4ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #1235 = FSUB_S_MM
    5048             :   { 1236,       3,      1,      4,      136,    0, 0x6ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #1236 = FSUB_S_MMR6
    5049             :   { 1237,       3,      1,      4,      470,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1237 = FSUB_W
    5050             :   { 1238,       3,      1,      4,      404,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1238 = FSUEQ_D
    5051             :   { 1239,       3,      1,      4,      404,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1239 = FSUEQ_W
    5052             :   { 1240,       3,      1,      4,      405,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1240 = FSULE_D
    5053             :   { 1241,       3,      1,      4,      405,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1241 = FSULE_W
    5054             :   { 1242,       3,      1,      4,      406,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1242 = FSULT_D
    5055             :   { 1243,       3,      1,      4,      406,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1243 = FSULT_W
    5056             :   { 1244,       3,      1,      4,      407,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1244 = FSUNE_D
    5057             :   { 1245,       3,      1,      4,      407,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1245 = FSUNE_W
    5058             :   { 1246,       3,      1,      4,      408,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1246 = FSUN_D
    5059             :   { 1247,       3,      1,      4,      408,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1247 = FSUN_W
    5060             :   { 1248,       2,      1,      4,      424,    0, 0x6ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #1248 = FTINT_S_D
    5061             :   { 1249,       2,      1,      4,      424,    0, 0x6ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #1249 = FTINT_S_W
    5062             :   { 1250,       2,      1,      4,      424,    0, 0x6ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #1250 = FTINT_U_D
    5063             :   { 1251,       2,      1,      4,      424,    0, 0x6ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #1251 = FTINT_U_W
    5064             :   { 1252,       3,      1,      4,      426,    0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #1252 = FTQ_H
    5065             :   { 1253,       3,      1,      4,      426,    0, 0x6ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr },  // Inst #1253 = FTQ_W
    5066             :   { 1254,       2,      1,      4,      427,    0, 0x6ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #1254 = FTRUNC_S_D
    5067             :   { 1255,       2,      1,      4,      427,    0, 0x6ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #1255 = FTRUNC_S_W
    5068             :   { 1256,       2,      1,      4,      427,    0, 0x6ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #1256 = FTRUNC_U_D
    5069             :   { 1257,       2,      1,      4,      427,    0, 0x6ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #1257 = FTRUNC_U_W
    5070             :   { 1258,       1,      0,      4,      137,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1258 = GINVI
    5071             :   { 1259,       1,      0,      4,      137,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1259 = GINVI_MMR6
    5072             :   { 1260,       2,      0,      4,      138,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #1260 = GINVT
    5073             :   { 1261,       2,      0,      4,      138,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #1261 = GINVT_MMR6
    5074             :   { 1262,       4,      2,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr },  // Inst #1262 = GotPrologue16
    5075             :   { 1263,       3,      1,      4,      447,    0, 0x6ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1263 = HADD_S_D
    5076             :   { 1264,       3,      1,      4,      447,    0, 0x6ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1264 = HADD_S_H
    5077             :   { 1265,       3,      1,      4,      447,    0, 0x6ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #1265 = HADD_S_W
    5078             :   { 1266,       3,      1,      4,      447,    0, 0x6ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1266 = HADD_U_D
    5079             :   { 1267,       3,      1,      4,      447,    0, 0x6ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1267 = HADD_U_H
    5080             :   { 1268,       3,      1,      4,      447,    0, 0x6ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #1268 = HADD_U_W
    5081             :   { 1269,       3,      1,      4,      448,    0, 0x6ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1269 = HSUB_S_D
    5082             :   { 1270,       3,      1,      4,      448,    0, 0x6ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1270 = HSUB_S_H
    5083             :   { 1271,       3,      1,      4,      448,    0, 0x6ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #1271 = HSUB_S_W
    5084             :   { 1272,       3,      1,      4,      448,    0, 0x6ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1272 = HSUB_U_D
    5085             :   { 1273,       3,      1,      4,      448,    0, 0x6ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1273 = HSUB_U_H
    5086             :   { 1274,       3,      1,      4,      448,    0, 0x6ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #1274 = HSUB_U_W
    5087             :   { 1275,       1,      0,      4,      139,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #1275 = HYPCALL
    5088             :   { 1276,       1,      0,      4,      139,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #1276 = HYPCALL_MM
    5089             :   { 1277,       3,      1,      4,      438,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1277 = ILVEV_B
    5090             :   { 1278,       3,      1,      4,      438,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1278 = ILVEV_D
    5091             :   { 1279,       3,      1,      4,      438,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #1279 = ILVEV_H
    5092             :   { 1280,       3,      1,      4,      438,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1280 = ILVEV_W
    5093             :   { 1281,       3,      1,      4,      437,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1281 = ILVL_B
    5094             :   { 1282,       3,      1,      4,      437,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1282 = ILVL_D
    5095             :   { 1283,       3,      1,      4,      437,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #1283 = ILVL_H
    5096             :   { 1284,       3,      1,      4,      437,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1284 = ILVL_W
    5097             :   { 1285,       3,      1,      4,      438,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1285 = ILVOD_B
    5098             :   { 1286,       3,      1,      4,      438,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1286 = ILVOD_D
    5099             :   { 1287,       3,      1,      4,      438,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #1287 = ILVOD_H
    5100             :   { 1288,       3,      1,      4,      438,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1288 = ILVOD_W
    5101             :   { 1289,       3,      1,      4,      437,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1289 = ILVR_B
    5102             :   { 1290,       3,      1,      4,      437,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1290 = ILVR_D
    5103             :   { 1291,       3,      1,      4,      437,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #1291 = ILVR_H
    5104             :   { 1292,       3,      1,      4,      437,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1292 = ILVR_W
    5105             :   { 1293,       5,      1,      4,      39,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr },  // Inst #1293 = INS
    5106             :   { 1294,       4,      1,      4,      362,    0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr },  // Inst #1294 = INSERT_B
    5107             :   { 1295,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr },  // Inst #1295 = INSERT_B_VIDX64_PSEUDO
    5108             :   { 1296,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo170, -1 ,nullptr },  // Inst #1296 = INSERT_B_VIDX_PSEUDO
    5109             :   { 1297,       4,      1,      4,      362,    0, 0x6ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr },  // Inst #1297 = INSERT_D
    5110             :   { 1298,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1298 = INSERT_D_VIDX64_PSEUDO
    5111             :   { 1299,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1299 = INSERT_D_VIDX_PSEUDO
    5112             :   { 1300,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr },  // Inst #1300 = INSERT_FD_PSEUDO
    5113             :   { 1301,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1301 = INSERT_FD_VIDX64_PSEUDO
    5114             :   { 1302,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr },  // Inst #1302 = INSERT_FD_VIDX_PSEUDO
    5115             :   { 1303,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr },  // Inst #1303 = INSERT_FW_PSEUDO
    5116             :   { 1304,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr },  // Inst #1304 = INSERT_FW_VIDX64_PSEUDO
    5117             :   { 1305,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo179, -1 ,nullptr },  // Inst #1305 = INSERT_FW_VIDX_PSEUDO
    5118             :   { 1306,       4,      1,      4,      362,    0, 0x6ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr },  // Inst #1306 = INSERT_H
    5119             :   { 1307,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr },  // Inst #1307 = INSERT_H_VIDX64_PSEUDO
    5120             :   { 1308,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr },  // Inst #1308 = INSERT_H_VIDX_PSEUDO
    5121             :   { 1309,       4,      1,      4,      362,    0, 0x6ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1309 = INSERT_W
    5122             :   { 1310,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr },  // Inst #1310 = INSERT_W_VIDX64_PSEUDO
    5123             :   { 1311,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr },  // Inst #1311 = INSERT_W_VIDX_PSEUDO
    5124             :   { 1312,       3,      1,      4,      495,    0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList17, nullptr, OperandInfo186, -1 ,nullptr },  // Inst #1312 = INSV
    5125             :   { 1313,       5,      1,      4,      439,    0, 0x6ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr },  // Inst #1313 = INSVE_B
    5126             :   { 1314,       5,      1,      4,      439,    0, 0x6ULL, nullptr, nullptr, OperandInfo188, -1 ,nullptr },  // Inst #1314 = INSVE_D
    5127             :   { 1315,       5,      1,      4,      439,    0, 0x6ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr },  // Inst #1315 = INSVE_H
    5128             :   { 1316,       5,      1,      4,      439,    0, 0x6ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr },  // Inst #1316 = INSVE_W
    5129             :   { 1317,       3,      1,      4,      686,    0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList17, nullptr, OperandInfo186, -1 ,nullptr },  // Inst #1317 = INSV_MM
    5130             :   { 1318,       5,      1,      4,      39,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr },  // Inst #1318 = INS_MM
    5131             :   { 1319,       5,      1,      4,      39,     0, 0x1ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr },  // Inst #1319 = INS_MMR6
    5132             :   { 1320,       1,      0,      4,      140,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x13ULL, nullptr, ImplicitList4, OperandInfo2, -1 ,nullptr },  // Inst #1320 = J
    5133             :   { 1321,       1,      0,      4,      141,    0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, nullptr, ImplicitList5, OperandInfo2, -1 ,nullptr },  // Inst #1321 = JAL
    5134             :   { 1322,       2,      1,      4,      142,    0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, ImplicitList5, OperandInfo31, -1 ,nullptr },  // Inst #1322 = JALR
    5135             :   { 1323,       1,      0,      2,      142,    0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x0ULL, nullptr, ImplicitList5, OperandInfo86, -1 ,nullptr },  // Inst #1323 = JALR16_MM
    5136             :   { 1324,       2,      1,      4,      142,    0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, ImplicitList5, OperandInfo125, -1 ,nullptr },  // Inst #1324 = JALR64
    5137             :   { 1325,       1,      0,      4,      142,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x10ULL, nullptr, ImplicitList5, OperandInfo191, -1 ,nullptr },  // Inst #1325 = JALR64Pseudo
    5138             :   { 1326,       1,      0,      2,      142,    0|(1ULL<<MCID::Call), 0x0ULL, nullptr, ImplicitList5, OperandInfo86, -1 ,nullptr },  // Inst #1326 = JALRC16_MMR6
    5139             :   { 1327,       2,      1,      4,      143,    0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1327 = JALRC_HB_MMR6
    5140             :   { 1328,       2,      1,      4,      144,    0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList5, OperandInfo31, -1 ,nullptr },  // Inst #1328 = JALRC_MMR6
    5141             :   { 1329,       1,      0,      4,      142,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x10ULL, nullptr, ImplicitList5, OperandInfo191, -1 ,nullptr },  // Inst #1329 = JALRHB64Pseudo
    5142             :   { 1330,       1,      0,      4,      142,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x10ULL, nullptr, ImplicitList5, OperandInfo86, -1 ,nullptr },  // Inst #1330 = JALRHBPseudo
    5143             :   { 1331,       1,      0,      4,      142,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x10ULL, nullptr, ImplicitList5, OperandInfo86, -1 ,nullptr },  // Inst #1331 = JALRPseudo
    5144             :   { 1332,       1,      0,      2,      145,    0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList5, OperandInfo86, -1 ,nullptr },  // Inst #1332 = JALRS16_MM
    5145             :   { 1333,       2,      1,      4,      145,    0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList5, OperandInfo31, -1 ,nullptr },  // Inst #1333 = JALRS_MM
    5146             :   { 1334,       2,      1,      4,      143,    0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1334 = JALR_HB
    5147             :   { 1335,       2,      1,      4,      143,    0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr },  // Inst #1335 = JALR_HB64
    5148             :   { 1336,       2,      1,      4,      142,    0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, ImplicitList5, OperandInfo31, -1 ,nullptr },  // Inst #1336 = JALR_MM
    5149             :   { 1337,       1,      0,      4,      146,    0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL, nullptr, ImplicitList5, OperandInfo2, -1 ,nullptr },  // Inst #1337 = JALS_MM
    5150             :   { 1338,       1,      0,      4,      141,    0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, nullptr, ImplicitList5, OperandInfo2, -1 ,nullptr },  // Inst #1338 = JALX
    5151             :   { 1339,       1,      0,      4,      141,    0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, nullptr, ImplicitList5, OperandInfo2, -1 ,nullptr },  // Inst #1339 = JALX_MM
    5152             :   { 1340,       1,      0,      4,      141,    0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, nullptr, ImplicitList5, OperandInfo2, -1 ,nullptr },  // Inst #1340 = JAL_MM
    5153             :   { 1341,       2,      0,      4,      147,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList5, OperandInfo34, -1 ,nullptr },  // Inst #1341 = JIALC
    5154             :   { 1342,       2,      0,      4,      147,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList5, OperandInfo130, -1 ,nullptr },  // Inst #1342 = JIALC64
    5155             :   { 1343,       2,      0,      4,      147,    0|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList5, OperandInfo34, -1 ,nullptr },  // Inst #1343 = JIALC_MMR6
    5156             :   { 1344,       2,      0,      4,      147,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList4, OperandInfo34, -1 ,nullptr },  // Inst #1344 = JIC
    5157             :   { 1345,       2,      0,      4,      148,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList4, OperandInfo130, -1 ,nullptr },  // Inst #1345 = JIC64
    5158             :   { 1346,       2,      0,      4,      148,    0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList4, OperandInfo34, -1 ,nullptr },  // Inst #1346 = JIC_MMR6
    5159             :   { 1347,       1,      0,      4,      149,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1347 = JR
    5160             :   { 1348,       1,      0,      2,      149,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1348 = JR16_MM
    5161             :   { 1349,       1,      0,      4,      149,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr },  // Inst #1349 = JR64
    5162             :   { 1350,       1,      0,      2,      150,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #1350 = JRADDIUSP
    5163             :   { 1351,       1,      0,      2,      151,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1351 = JRC16_MM
    5164             :   { 1352,       1,      0,      2,      149,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1352 = JRC16_MMR6
    5165             :   { 1353,       1,      0,      2,      150,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #1353 = JRCADDIUSP_MMR6
    5166             :   { 1354,       1,      0,      4,      152,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1354 = JR_HB
    5167             :   { 1355,       1,      0,      4,      152,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr },  // Inst #1355 = JR_HB64
    5168             :   { 1356,       1,      0,      4,      152,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr },  // Inst #1356 = JR_HB64_R6
    5169             :   { 1357,       1,      0,      4,      152,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1357 = JR_HB_R6
    5170             :   { 1358,       1,      0,      4,      149,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1358 = JR_MM
    5171             :   { 1359,       1,      0,      4,      140,    0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x13ULL, nullptr, ImplicitList4, OperandInfo2, -1 ,nullptr },  // Inst #1359 = J_MM
    5172             :   { 1360,       1,      0,      6,      13,     0|(1ULL<<MCID::Call), 0x0ULL, nullptr, ImplicitList5, OperandInfo2, -1 ,nullptr },  // Inst #1360 = Jal16
    5173             :   { 1361,       1,      0,      6,      13,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList5, OperandInfo2, -1 ,nullptr },  // Inst #1361 = JalB16
    5174             :   { 1362,       1,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1362 = JalOneReg
    5175             :   { 1363,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1363 = JalTwoReg
    5176             :   { 1364,       0,      0,      2,      13,     0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1364 = JrRa16
    5177             :   { 1365,       0,      0,      2,      13,     0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1365 = JrcRa16
    5178             :   { 1366,       1,      0,      2,      13,     0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1366 = JrcRx16
    5179             :   { 1367,       1,      0,      2,      144,    0|(1ULL<<MCID::Call), 0x0ULL, nullptr, ImplicitList5, OperandInfo192, -1 ,nullptr },  // Inst #1367 = JumpLinkReg16
    5180             :   { 1368,       3,      1,      4,      153,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1368 = LB
    5181             :   { 1369,       3,      1,      4,      153,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #1369 = LB64
    5182             :   { 1370,       3,      1,      4,      154,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1370 = LBE
    5183             :   { 1371,       3,      1,      4,      154,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1371 = LBE_MM
    5184             :   { 1372,       3,      1,      2,      155,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1372 = LBU16_MM
    5185             :   { 1373,       3,      1,      4,      531,    0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr },  // Inst #1373 = LBUX
    5186             :   { 1374,       3,      1,      4,      687,    0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr },  // Inst #1374 = LBUX_MM
    5187             :   { 1375,       3,      1,      4,      155,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1375 = LBU_MMR6
    5188             :   { 1376,       3,      1,      4,      153,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1376 = LB_MM
    5189             :   { 1377,       3,      1,      4,      153,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1377 = LB_MMR6
    5190             :   { 1378,       3,      1,      4,      155,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1378 = LBu
    5191             :   { 1379,       3,      1,      4,      155,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #1379 = LBu64
    5192             :   { 1380,       3,      1,      4,      156,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1380 = LBuE
    5193             :   { 1381,       3,      1,      4,      156,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1381 = LBuE_MM
    5194             :   { 1382,       3,      1,      4,      155,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1382 = LBu_MM
    5195             :   { 1383,       3,      1,      4,      157,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #1383 = LD
    5196             :   { 1384,       3,      1,      4,      158,    0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr },  // Inst #1384 = LDC1
    5197             :   { 1385,       3,      1,      4,      158,    0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr },  // Inst #1385 = LDC164
    5198             :   { 1386,       3,      1,      4,      158,    0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr },  // Inst #1386 = LDC1_D64_MMR6
    5199             :   { 1387,       3,      1,      4,      158,    0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr },  // Inst #1387 = LDC1_MM
    5200             :   { 1388,       3,      1,      4,      159,    0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #1388 = LDC2
    5201             :   { 1389,       3,      1,      4,      159,    0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr },  // Inst #1389 = LDC2_MMR6
    5202             :   { 1390,       3,      1,      4,      159,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #1390 = LDC2_R6
    5203             :   { 1391,       3,      1,      4,      160,    0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr },  // Inst #1391 = LDC3
    5204             :   { 1392,       2,      1,      4,      382,    0, 0x6ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr },  // Inst #1392 = LDI_B
    5205             :   { 1393,       2,      1,      4,      382,    0, 0x6ULL, nullptr, nullptr, OperandInfo203, -1 ,nullptr },  // Inst #1393 = LDI_D
    5206             :   { 1394,       2,      1,      4,      382,    0, 0x6ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr },  // Inst #1394 = LDI_H
    5207             :   { 1395,       2,      1,      4,      382,    0, 0x6ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr },  // Inst #1395 = LDI_W
    5208             :   { 1396,       4,      1,      4,      161,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr },  // Inst #1396 = LDL
    5209             :   { 1397,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1397 = LDMacro
    5210             :   { 1398,       2,      1,      4,      162,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr },  // Inst #1398 = LDPC
    5211             :   { 1399,       4,      1,      4,      163,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr },  // Inst #1399 = LDR
    5212             :   { 1400,       3,      1,      4,      164,    0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr },  // Inst #1400 = LDXC1
    5213             :   { 1401,       3,      1,      4,      164,    0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr },  // Inst #1401 = LDXC164
    5214             :   { 1402,       3,      1,      4,      486,    0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr },  // Inst #1402 = LD_B
    5215             :   { 1403,       3,      1,      4,      486,    0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1403 = LD_D
    5216             :   { 1404,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1404 = LD_F16
    5217             :   { 1405,       3,      1,      4,      486,    0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo212, -1 ,nullptr },  // Inst #1405 = LD_H
    5218             :   { 1406,       3,      1,      4,      486,    0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo213, -1 ,nullptr },  // Inst #1406 = LD_W
    5219             :   { 1407,       3,      1,      4,      4,      0, 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1407 = LEA_ADDiu
    5220             :   { 1408,       3,      1,      4,      4,      0, 0x2ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #1408 = LEA_ADDiu64
    5221             :   { 1409,       3,      1,      4,      4,      0, 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1409 = LEA_ADDiu_MM
    5222             :   { 1410,       3,      1,      4,      165,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1410 = LH
    5223             :   { 1411,       3,      1,      4,      165,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #1411 = LH64
    5224             :   { 1412,       3,      1,      4,      166,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1412 = LHE
    5225             :   { 1413,       3,      1,      4,      166,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1413 = LHE_MM
    5226             :   { 1414,       3,      1,      2,      167,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1414 = LHU16_MM
    5227             :   { 1415,       3,      1,      4,      532,    0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr },  // Inst #1415 = LHX
    5228             :   { 1416,       3,      1,      4,      688,    0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr },  // Inst #1416 = LHX_MM
    5229             :   { 1417,       3,      1,      4,      165,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1417 = LH_MM
    5230             :   { 1418,       3,      1,      4,      167,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1418 = LHu
    5231             :   { 1419,       3,      1,      4,      167,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #1419 = LHu64
    5232             :   { 1420,       3,      1,      4,      168,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1420 = LHuE
    5233             :   { 1421,       3,      1,      4,      168,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1421 = LHuE_MM
    5234             :   { 1422,       3,      1,      4,      167,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1422 = LHu_MM
    5235             :   { 1423,       2,      1,      2,      169,    0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #1423 = LI16_MM
    5236             :   { 1424,       2,      1,      2,      169,    0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #1424 = LI16_MMR6
    5237             :   { 1425,       3,      1,      4,      170,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1425 = LL
    5238             :   { 1426,       3,      1,      4,      170,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1426 = LL64
    5239             :   { 1427,       3,      1,      4,      170,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1427 = LL64_R6
    5240             :   { 1428,       3,      1,      4,      170,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #1428 = LLD
    5241             :   { 1429,       3,      1,      4,      171,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #1429 = LLD_R6
    5242             :   { 1430,       3,      1,      4,      172,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1430 = LLE
    5243             :   { 1431,       3,      1,      4,      172,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1431 = LLE_MM
    5244             :   { 1432,       3,      1,      4,      170,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1432 = LL_MM
    5245             :   { 1433,       3,      1,      4,      170,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1433 = LL_R6
    5246             :   { 1434,       3,      1,      4,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo214, -1 ,nullptr },  // Inst #1434 = LOAD_ACC128
    5247             :   { 1435,       3,      1,      4,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo215, -1 ,nullptr },  // Inst #1435 = LOAD_ACC64
    5248             :   { 1436,       3,      1,      4,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr },  // Inst #1436 = LOAD_ACC64DSP
    5249             :   { 1437,       3,      1,      4,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr },  // Inst #1437 = LOAD_CCOND_DSP
    5250             :   { 1438,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr },  // Inst #1438 = LONG_BRANCH_ADDiu
    5251             :   { 1439,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo219, -1 ,nullptr },  // Inst #1439 = LONG_BRANCH_DADDiu
    5252             :   { 1440,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo220, -1 ,nullptr },  // Inst #1440 = LONG_BRANCH_LUi
    5253             :   { 1441,       4,      1,      4,      173,    0, 0x6ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #1441 = LSA
    5254             :   { 1442,       4,      1,      4,      173,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #1442 = LSA_MMR6
    5255             :   { 1443,       4,      1,      4,      173,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #1443 = LSA_R6
    5256             :   { 1444,       2,      1,      4,      174,    0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #1444 = LUI_MMR6
    5257             :   { 1445,       3,      1,      4,      175,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr },  // Inst #1445 = LUXC1
    5258             :   { 1446,       3,      1,      4,      175,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr },  // Inst #1446 = LUXC164
    5259             :   { 1447,       3,      1,      4,      175,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr },  // Inst #1447 = LUXC1_MM
    5260             :   { 1448,       2,      1,      4,      174,    0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #1448 = LUi
    5261             :   { 1449,       2,      1,      4,      174,    0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr },  // Inst #1449 = LUi64
    5262             :   { 1450,       2,      1,      4,      174,    0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #1450 = LUi_MM
    5263             :   { 1451,       3,      1,      4,      176,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1451 = LW
    5264             :   { 1452,       3,      1,      2,      176,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1452 = LW16_MM
    5265             :   { 1453,       3,      1,      4,      176,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #1453 = LW64
    5266             :   { 1454,       3,      1,      4,      177,    0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr },  // Inst #1454 = LWC1
    5267             :   { 1455,       3,      1,      4,      177,    0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr },  // Inst #1455 = LWC1_MM
    5268             :   { 1456,       3,      1,      4,      178,    0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #1456 = LWC2
    5269             :   { 1457,       3,      1,      4,      178,    0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr },  // Inst #1457 = LWC2_MMR6
    5270             :   { 1458,       3,      1,      4,      178,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #1458 = LWC2_R6
    5271             :   { 1459,       3,      1,      4,      179,    0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr },  // Inst #1459 = LWC3
    5272             :   { 1460,       3,      1,      4,      176,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr },  // Inst #1460 = LWDSP
    5273             :   { 1461,       3,      1,      4,      176,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr },  // Inst #1461 = LWDSP_MM
    5274             :   { 1462,       3,      1,      4,      180,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1462 = LWE
    5275             :   { 1463,       3,      1,      4,      180,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1463 = LWE_MM
    5276             :   { 1464,       3,      1,      2,      176,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr },  // Inst #1464 = LWGP_MM
    5277             :   { 1465,       4,      1,      4,      181,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr },  // Inst #1465 = LWL
    5278             :   { 1466,       4,      1,      4,      181,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr },  // Inst #1466 = LWL64
    5279             :   { 1467,       4,      1,      4,      182,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr },  // Inst #1467 = LWLE
    5280             :   { 1468,       4,      1,      4,      182,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr },  // Inst #1468 = LWLE_MM
    5281             :   { 1469,       4,      1,      4,      181,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr },  // Inst #1469 = LWL_MM
    5282             :   { 1470,       3,      1,      2,      183,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr },  // Inst #1470 = LWM16_MM
    5283             :   { 1471,       3,      1,      2,      183,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr },  // Inst #1471 = LWM16_MMR6
    5284             :   { 1472,       3,      1,      4,      183,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr },  // Inst #1472 = LWM32_MM
    5285             :   { 1473,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr },  // Inst #1473 = LWM_MM
    5286             :   { 1474,       2,      1,      4,      184,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #1474 = LWPC
    5287             :   { 1475,       2,      1,      4,      184,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #1475 = LWPC_MMR6
    5288             :   { 1476,       4,      1,      4,      185,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr },  // Inst #1476 = LWP_MM
    5289             :   { 1477,       4,      1,      4,      185,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr },  // Inst #1477 = LWP_MMR6
    5290             :   { 1478,       4,      1,      4,      186,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr },  // Inst #1478 = LWR
    5291             :   { 1479,       4,      1,      4,      186,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr },  // Inst #1479 = LWR64
    5292             :   { 1480,       4,      1,      4,      187,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr },  // Inst #1480 = LWRE
    5293             :   { 1481,       4,      1,      4,      187,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr },  // Inst #1481 = LWRE_MM
    5294             :   { 1482,       4,      1,      4,      186,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr },  // Inst #1482 = LWR_MM
    5295             :   { 1483,       3,      1,      2,      176,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr },  // Inst #1483 = LWSP_MM
    5296             :   { 1484,       2,      1,      4,      188,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #1484 = LWUPC
    5297             :   { 1485,       3,      1,      4,      189,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1485 = LWU_MM
    5298             :   { 1486,       3,      1,      4,      533,    0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr },  // Inst #1486 = LWX
    5299             :   { 1487,       3,      1,      4,      190,    0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr },  // Inst #1487 = LWXC1
    5300             :   { 1488,       3,      1,      4,      190,    0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr },  // Inst #1488 = LWXC1_MM
    5301             :   { 1489,       3,      1,      4,      191,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr },  // Inst #1489 = LWXS_MM
    5302             :   { 1490,       3,      1,      4,      689,    0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr },  // Inst #1490 = LWX_MM
    5303             :   { 1491,       3,      1,      4,      176,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1491 = LW_MM
    5304             :   { 1492,       3,      1,      4,      176,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1492 = LW_MMR6
    5305             :   { 1493,       3,      1,      4,      189,    0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #1493 = LWu
    5306             :   { 1494,       3,      1,      4,      153,    0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr },  // Inst #1494 = LbRxRyOffMemX16
    5307             :   { 1495,       3,      1,      4,      155,    0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr },  // Inst #1495 = LbuRxRyOffMemX16
    5308             :   { 1496,       3,      1,      4,      165,    0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr },  // Inst #1496 = LhRxRyOffMemX16
    5309             :   { 1497,       3,      1,      4,      167,    0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr },  // Inst #1497 = LhuRxRyOffMemX16
    5310             :   { 1498,       2,      1,      2,      13,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #1498 = LiRxImm16
    5311             :   { 1499,       2,      1,      4,      13,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #1499 = LiRxImmAlignX16
    5312             :   { 1500,       2,      1,      4,      13,     0, 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #1500 = LiRxImmX16
    5313             :   { 1501,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr },  // Inst #1501 = LoadAddrImm32
    5314             :   { 1502,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr },  // Inst #1502 = LoadAddrImm64
    5315             :   { 1503,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1503 = LoadAddrReg32
    5316             :   { 1504,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #1504 = LoadAddrReg64
    5317             :   { 1505,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #1505 = LoadImm32
    5318             :   { 1506,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr },  // Inst #1506 = LoadImm64
    5319             :   { 1507,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo232, -1 ,nullptr },  // Inst #1507 = LoadImmDoubleFGR
    5320             :   { 1508,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr },  // Inst #1508 = LoadImmDoubleFGR_32
    5321             :   { 1509,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #1509 = LoadImmDoubleGPR
    5322             :   { 1510,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr },  // Inst #1510 = LoadImmSingleFGR
    5323             :   { 1511,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #1511 = LoadImmSingleGPR
    5324             :   { 1512,       3,      1,      2,      1,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo235, -1 ,nullptr },  // Inst #1512 = LwConstant32
    5325             :   { 1513,       3,      1,      2,      176,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo236, -1 ,nullptr },  // Inst #1513 = LwRxPcTcp16
    5326             :   { 1514,       3,      1,      4,      176,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo236, -1 ,nullptr },  // Inst #1514 = LwRxPcTcpX16
    5327             :   { 1515,       3,      1,      4,      176,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr },  // Inst #1515 = LwRxRyOffMemX16
    5328             :   { 1516,       3,      1,      4,      176,    0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #1516 = LwRxSpImmX16
    5329             :   { 1517,       2,      0,      4,      192,    0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList12, ImplicitList12, OperandInfo31, -1 ,nullptr },  // Inst #1517 = MADD
    5330             :   { 1518,       4,      1,      4,      193,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo237, -1 ,nullptr },  // Inst #1518 = MADDF_D
    5331             :   { 1519,       4,      1,      4,      193,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo237, -1 ,nullptr },  // Inst #1519 = MADDF_D_MMR6
    5332             :   { 1520,       4,      1,      4,      194,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr },  // Inst #1520 = MADDF_S
    5333             :   { 1521,       4,      1,      4,      194,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr },  // Inst #1521 = MADDF_S_MMR6
    5334             :   { 1522,       4,      1,      4,      477,    0, 0x6ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #1522 = MADDR_Q_H
    5335             :   { 1523,       4,      1,      4,      477,    0, 0x6ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #1523 = MADDR_Q_W
    5336             :   { 1524,       2,      0,      4,      195,    0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList12, ImplicitList12, OperandInfo31, -1 ,nullptr },  // Inst #1524 = MADDU
    5337             :   { 1525,       4,      1,      4,      534,    0, 0x6ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #1525 = MADDU_DSP
    5338             :   { 1526,       4,      1,      4,      690,    0, 0x6ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #1526 = MADDU_DSP_MM
    5339             :   { 1527,       2,      0,      4,      195,    0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList12, ImplicitList12, OperandInfo31, -1 ,nullptr },  // Inst #1527 = MADDU_MM
    5340             :   { 1528,       4,      1,      4,      475,    0, 0x6ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr },  // Inst #1528 = MADDV_B
    5341             :   { 1529,       4,      1,      4,      475,    0, 0x6ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #1529 = MADDV_D
    5342             :   { 1530,       4,      1,      4,      475,    0, 0x6ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #1530 = MADDV_H
    5343             :   { 1531,       4,      1,      4,      475,    0, 0x6ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #1531 = MADDV_W
    5344             :   { 1532,       4,      1,      4,      196,    0, 0x4ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr },  // Inst #1532 = MADD_D32
    5345             :   { 1533,       4,      1,      4,      196,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr },  // Inst #1533 = MADD_D32_MM
    5346             :   { 1534,       4,      1,      4,      196,    0, 0x4ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr },  // Inst #1534 = MADD_D64
    5347             :   { 1535,       4,      1,      4,      535,    0, 0x6ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #1535 = MADD_DSP
    5348             :   { 1536,       4,      1,      4,      691,    0, 0x6ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #1536 = MADD_DSP_MM
    5349             :   { 1537,       2,      0,      4,      192,    0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList12, ImplicitList12, OperandInfo31, -1 ,nullptr },  // Inst #1537 = MADD_MM
    5350             :   { 1538,       4,      1,      4,      478,    0, 0x6ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #1538 = MADD_Q_H
    5351             :   { 1539,       4,      1,      4,      478,    0, 0x6ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #1539 = MADD_Q_W
    5352             :   { 1540,       4,      1,      4,      197,    0, 0x4ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr },  // Inst #1540 = MADD_S
    5353             :   { 1541,       4,      1,      4,      197,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr },  // Inst #1541 = MADD_S_MM
    5354             :   { 1542,       4,      1,      4,      536,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList11, OperandInfo140, -1 ,nullptr },  // Inst #1542 = MAQ_SA_W_PHL
    5355             :   { 1543,       4,      1,      4,      692,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList11, OperandInfo140, -1 ,nullptr },  // Inst #1543 = MAQ_SA_W_PHL_MM
    5356             :   { 1544,       4,      1,      4,      537,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList11, OperandInfo140, -1 ,nullptr },  // Inst #1544 = MAQ_SA_W_PHR
    5357             :   { 1545,       4,      1,      4,      693,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList11, OperandInfo140, -1 ,nullptr },  // Inst #1545 = MAQ_SA_W_PHR_MM
    5358             :   { 1546,       4,      1,      4,      538,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList11, OperandInfo140, -1 ,nullptr },  // Inst #1546 = MAQ_S_W_PHL
    5359             :   { 1547,       4,      1,      4,      694,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList11, OperandInfo140, -1 ,nullptr },  // Inst #1547 = MAQ_S_W_PHL_MM
    5360             :   { 1548,       4,      1,      4,      539,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList11, OperandInfo140, -1 ,nullptr },  // Inst #1548 = MAQ_S_W_PHR
    5361             :   { 1549,       4,      1,      4,      695,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList11, OperandInfo140, -1 ,nullptr },  // Inst #1549 = MAQ_S_W_PHR_MM
    5362             :   { 1550,       3,      1,      4,      198,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #1550 = MAXA_D
    5363             :   { 1551,       3,      1,      4,      199,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #1551 = MAXA_D_MMR6
    5364             :   { 1552,       3,      1,      4,      200,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #1552 = MAXA_S
    5365             :   { 1553,       3,      1,      4,      201,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #1553 = MAXA_S_MMR6
    5366             :   { 1554,       3,      1,      4,      452,    0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #1554 = MAXI_S_B
    5367             :   { 1555,       3,      1,      4,      452,    0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #1555 = MAXI_S_D
    5368             :   { 1556,       3,      1,      4,      452,    0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #1556 = MAXI_S_H
    5369             :   { 1557,       3,      1,      4,      452,    0, 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #1557 = MAXI_S_W
    5370             :   { 1558,       3,      1,      4,      452,    0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #1558 = MAXI_U_B
    5371             :   { 1559,       3,      1,      4,      452,    0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #1559 = MAXI_U_D
    5372             :   { 1560,       3,      1,      4,      452,    0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #1560 = MAXI_U_H
    5373             :   { 1561,       3,      1,      4,      452,    0, 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #1561 = MAXI_U_W
    5374             :   { 1562,       3,      1,      4,      451,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1562 = MAX_A_B
    5375             :   { 1563,       3,      1,      4,      451,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1563 = MAX_A_D
    5376             :   { 1564,       3,      1,      4,      451,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #1564 = MAX_A_H
    5377             :   { 1565,       3,      1,      4,      451,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1565 = MAX_A_W
    5378             :   { 1566,       3,      1,      4,      198,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #1566 = MAX_D
    5379             :   { 1567,       3,      1,      4,      198,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #1567 = MAX_D_MMR6
    5380             :   { 1568,       3,      1,      4,      200,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #1568 = MAX_S
    5381             :   { 1569,       3,      1,      4,      449,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1569 = MAX_S_B
    5382             :   { 1570,       3,      1,      4,      449,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1570 = MAX_S_D
    5383             :   { 1571,       3,      1,      4,      449,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #1571 = MAX_S_H
    5384             :   { 1572,       3,      1,      4,      200,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #1572 = MAX_S_MMR6
    5385             :   { 1573,       3,      1,      4,      449,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1573 = MAX_S_W
    5386             :   { 1574,       3,      1,      4,      450,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1574 = MAX_U_B
    5387             :   { 1575,       3,      1,      4,      450,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1575 = MAX_U_D
    5388             :   { 1576,       3,      1,      4,      450,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #1576 = MAX_U_H
    5389             :   { 1577,       3,      1,      4,      450,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1577 = MAX_U_W
    5390             :   { 1578,       3,      1,      4,      202,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr },  // Inst #1578 = MFC0
    5391             :   { 1579,       3,      1,      4,      202,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr },  // Inst #1579 = MFC0_MMR6
    5392             :   { 1580,       2,      1,      4,      120,    0|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr },  // Inst #1580 = MFC1
    5393             :   { 1581,       2,      1,      4,      120,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr },  // Inst #1581 = MFC1_D64
    5394             :   { 1582,       2,      1,      4,      120,    0|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr },  // Inst #1582 = MFC1_MM
    5395             :   { 1583,       2,      1,      4,      120,    0|(1ULL<<MCID::Bitcast), 0x6ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr },  // Inst #1583 = MFC1_MMR6
    5396             :   { 1584,       3,      1,      4,      203,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo245, -1 ,nullptr },  // Inst #1584 = MFC2
    5397             :   { 1585,       2,      1,      4,      203,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr },  // Inst #1585 = MFC2_MMR6
    5398             :   { 1586,       3,      1,      4,      204,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr },  // Inst #1586 = MFGC0
    5399             :   { 1587,       3,      1,      4,      204,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr },  // Inst #1587 = MFGC0_MM
    5400             :   { 1588,       3,      1,      4,      205,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr },  // Inst #1588 = MFHC0_MMR6
    5401             :   { 1589,       2,      1,      4,      206,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr },  // Inst #1589 = MFHC1_D32
    5402             :   { 1590,       2,      1,      4,      206,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr },  // Inst #1590 = MFHC1_D32_MM
    5403             :   { 1591,       2,      1,      4,      206,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr },  // Inst #1591 = MFHC1_D64
    5404             :   { 1592,       2,      1,      4,      206,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr },  // Inst #1592 = MFHC1_D64_MM
    5405             :   { 1593,       2,      1,      4,      203,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr },  // Inst #1593 = MFHC2_MMR6
    5406             :   { 1594,       3,      1,      4,      207,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr },  // Inst #1594 = MFHGC0
    5407             :   { 1595,       3,      1,      4,      207,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr },  // Inst #1595 = MFHGC0_MM
    5408             :   { 1596,       1,      1,      4,      208,    0, 0x1ULL, ImplicitList18, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1596 = MFHI
    5409             :   { 1597,       1,      1,      2,      208,    0, 0x0ULL, ImplicitList18, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1597 = MFHI16_MM
    5410             :   { 1598,       1,      1,      4,      208,    0, 0x1ULL, ImplicitList19, nullptr, OperandInfo191, -1 ,nullptr },  // Inst #1598 = MFHI64
    5411             :   { 1599,       2,      1,      4,      540,    0, 0x6ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr },  // Inst #1599 = MFHI_DSP
    5412             :   { 1600,       2,      1,      4,      696,    0, 0x6ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr },  // Inst #1600 = MFHI_DSP_MM
    5413             :   { 1601,       1,      1,      4,      208,    0, 0x1ULL, ImplicitList18, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1601 = MFHI_MM
    5414             :   { 1602,       1,      1,      4,      208,    0, 0x1ULL, ImplicitList18, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1602 = MFLO
    5415             :   { 1603,       1,      1,      2,      208,    0, 0x0ULL, ImplicitList18, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1603 = MFLO16_MM
    5416             :   { 1604,       1,      1,      4,      208,    0, 0x1ULL, ImplicitList19, nullptr, OperandInfo191, -1 ,nullptr },  // Inst #1604 = MFLO64
    5417             :   { 1605,       2,      1,      4,      541,    0, 0x6ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr },  // Inst #1605 = MFLO_DSP
    5418             :   { 1606,       2,      1,      4,      697,    0, 0x6ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr },  // Inst #1606 = MFLO_DSP_MM
    5419             :   { 1607,       1,      1,      4,      208,    0, 0x1ULL, ImplicitList18, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1607 = MFLO_MM
    5420             :   { 1608,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr },  // Inst #1608 = MFTACX
    5421             :   { 1609,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr },  // Inst #1609 = MFTC0
    5422             :   { 1610,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr },  // Inst #1610 = MFTC1
    5423             :   { 1611,       1,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1611 = MFTDSP
    5424             :   { 1612,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1612 = MFTGPR
    5425             :   { 1613,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr },  // Inst #1613 = MFTHC1
    5426             :   { 1614,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr },  // Inst #1614 = MFTHI
    5427             :   { 1615,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr },  // Inst #1615 = MFTLO
    5428             :   { 1616,       5,      1,      4,      209,    0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr },  // Inst #1616 = MFTR
    5429             :   { 1617,       3,      1,      4,      210,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #1617 = MINA_D
    5430             :   { 1618,       3,      1,      4,      211,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #1618 = MINA_D_MMR6
    5431             :   { 1619,       3,      1,      4,      212,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #1619 = MINA_S
    5432             :   { 1620,       3,      1,      4,      213,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #1620 = MINA_S_MMR6
    5433             :   { 1621,       3,      1,      4,      452,    0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #1621 = MINI_S_B
    5434             :   { 1622,       3,      1,      4,      452,    0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #1622 = MINI_S_D
    5435             :   { 1623,       3,      1,      4,      452,    0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #1623 = MINI_S_H
    5436             :   { 1624,       3,      1,      4,      452,    0, 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #1624 = MINI_S_W
    5437             :   { 1625,       3,      1,      4,      452,    0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #1625 = MINI_U_B
    5438             :   { 1626,       3,      1,      4,      452,    0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #1626 = MINI_U_D
    5439             :   { 1627,       3,      1,      4,      452,    0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #1627 = MINI_U_H
    5440             :   { 1628,       3,      1,      4,      452,    0, 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #1628 = MINI_U_W
    5441             :   { 1629,       3,      1,      4,      451,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1629 = MIN_A_B
    5442             :   { 1630,       3,      1,      4,      451,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1630 = MIN_A_D
    5443             :   { 1631,       3,      1,      4,      451,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #1631 = MIN_A_H
    5444             :   { 1632,       3,      1,      4,      451,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1632 = MIN_A_W
    5445             :   { 1633,       3,      1,      4,      212,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #1633 = MIN_D
    5446             :   { 1634,       3,      1,      4,      212,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #1634 = MIN_D_MMR6
    5447             :   { 1635,       3,      1,      4,      210,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #1635 = MIN_S
    5448             :   { 1636,       3,      1,      4,      449,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1636 = MIN_S_B
    5449             :   { 1637,       3,      1,      4,      449,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1637 = MIN_S_D
    5450             :   { 1638,       3,      1,      4,      449,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #1638 = MIN_S_H
    5451             :   { 1639,       3,      1,      4,      210,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #1639 = MIN_S_MMR6
    5452             :   { 1640,       3,      1,      4,      449,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1640 = MIN_S_W
    5453             :   { 1641,       3,      1,      4,      450,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1641 = MIN_U_B
    5454             :   { 1642,       3,      1,      4,      450,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1642 = MIN_U_D
    5455             :   { 1643,       3,      1,      4,      450,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #1643 = MIN_U_H
    5456             :   { 1644,       3,      1,      4,      450,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1644 = MIN_U_W
    5457             :   { 1645,       2,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL, ImplicitList20, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1645 = MIPSeh_return32
    5458             :   { 1646,       2,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL, ImplicitList20, nullptr, OperandInfo125, -1 ,nullptr },  // Inst #1646 = MIPSeh_return64
    5459             :   { 1647,       3,      1,      4,      214,    0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1647 = MOD
    5460             :   { 1648,       3,      1,      4,      542,    0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1648 = MODSUB
    5461             :   { 1649,       3,      1,      4,      698,    0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1649 = MODSUB_MM
    5462             :   { 1650,       3,      1,      4,      215,    0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1650 = MODU
    5463             :   { 1651,       3,      1,      4,      215,    0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1651 = MODU_MMR6
    5464             :   { 1652,       3,      1,      4,      214,    0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1652 = MOD_MMR6
    5465             :   { 1653,       3,      1,      4,      445,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1653 = MOD_S_B
    5466             :   { 1654,       3,      1,      4,      445,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1654 = MOD_S_D
    5467             :   { 1655,       3,      1,      4,      445,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #1655 = MOD_S_H
    5468             :   { 1656,       3,      1,      4,      445,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1656 = MOD_S_W
    5469             :   { 1657,       3,      1,      4,      445,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1657 = MOD_U_B
    5470             :   { 1658,       3,      1,      4,      445,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1658 = MOD_U_D
    5471             :   { 1659,       3,      1,      4,      445,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #1659 = MOD_U_H
    5472             :   { 1660,       3,      1,      4,      445,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1660 = MOD_U_W
    5473             :   { 1661,       2,      1,      2,      216,    0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1661 = MOVE16_MM
    5474             :   { 1662,       2,      1,      2,      216,    0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1662 = MOVE16_MMR6
    5475             :   { 1663,       4,      1,      2,      699,    0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo249, -1 ,nullptr },  // Inst #1663 = MOVEP_MM
    5476             :   { 1664,       4,      1,      2,      700,    0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo249, -1 ,nullptr },  // Inst #1664 = MOVEP_MMR6
    5477             :   { 1665,       2,      1,      4,      381,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr },  // Inst #1665 = MOVE_V
    5478             :   { 1666,       4,      1,      4,      217,    0, 0x4ULL, nullptr, nullptr, OperandInfo251, -1 ,nullptr },  // Inst #1666 = MOVF_D32
    5479             :   { 1667,       4,      1,      4,      217,    0, 0x4ULL, nullptr, nullptr, OperandInfo251, -1 ,nullptr },  // Inst #1667 = MOVF_D32_MM
    5480             :   { 1668,       4,      1,      4,      217,    0, 0x4ULL, nullptr, nullptr, OperandInfo252, -1 ,nullptr },  // Inst #1668 = MOVF_D64
    5481             :   { 1669,       4,      1,      4,      218,    0, 0x4ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr },  // Inst #1669 = MOVF_I
    5482             :   { 1670,       4,      1,      4,      218,    0, 0x4ULL, nullptr, nullptr, OperandInfo254, -1 ,nullptr },  // Inst #1670 = MOVF_I64
    5483             :   { 1671,       4,      1,      4,      218,    0, 0x4ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr },  // Inst #1671 = MOVF_I_MM
    5484             :   { 1672,       4,      1,      4,      219,    0, 0x4ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr },  // Inst #1672 = MOVF_S
    5485             :   { 1673,       4,      1,      4,      219,    0, 0x4ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr },  // Inst #1673 = MOVF_S_MM
    5486             :   { 1674,       4,      1,      4,      220,    0, 0x4ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr },  // Inst #1674 = MOVN_I64_D64
    5487             :   { 1675,       4,      1,      4,      221,    0, 0x4ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr },  // Inst #1675 = MOVN_I64_I
    5488             :   { 1676,       4,      1,      4,      221,    0, 0x4ULL, nullptr, nullptr, OperandInfo258, -1 ,nullptr },  // Inst #1676 = MOVN_I64_I64
    5489             :   { 1677,       4,      1,      4,      222,    0, 0x4ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr },  // Inst #1677 = MOVN_I64_S
    5490             :   { 1678,       4,      1,      4,      220,    0, 0x4ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr },  // Inst #1678 = MOVN_I_D32
    5491             :   { 1679,       4,      1,      4,      220,    0, 0x4ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr },  // Inst #1679 = MOVN_I_D32_MM
    5492             :   { 1680,       4,      1,      4,      220,    0, 0x4ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr },  // Inst #1680 = MOVN_I_D64
    5493             :   { 1681,       4,      1,      4,      221,    0, 0x4ULL, nullptr, nullptr, OperandInfo262, -1 ,nullptr },  // Inst #1681 = MOVN_I_I
    5494             :   { 1682,       4,      1,      4,      221,    0, 0x4ULL, nullptr, nullptr, OperandInfo263, -1 ,nullptr },  // Inst #1682 = MOVN_I_I64
    5495             :   { 1683,       4,      1,      4,      701,    0, 0x4ULL, nullptr, nullptr, OperandInfo262, -1 ,nullptr },  // Inst #1683 = MOVN_I_MM
    5496             :   { 1684,       4,      1,      4,      222,    0, 0x4ULL, nullptr, nullptr, OperandInfo264, -1 ,nullptr },  // Inst #1684 = MOVN_I_S
    5497             :   { 1685,       4,      1,      4,      222,    0, 0x4ULL, nullptr, nullptr, OperandInfo264, -1 ,nullptr },  // Inst #1685 = MOVN_I_S_MM
    5498             :   { 1686,       4,      1,      4,      223,    0, 0x4ULL, nullptr, nullptr, OperandInfo251, -1 ,nullptr },  // Inst #1686 = MOVT_D32
    5499             :   { 1687,       4,      1,      4,      223,    0, 0x4ULL, nullptr, nullptr, OperandInfo251, -1 ,nullptr },  // Inst #1687 = MOVT_D32_MM
    5500             :   { 1688,       4,      1,      4,      223,    0, 0x4ULL, nullptr, nullptr, OperandInfo252, -1 ,nullptr },  // Inst #1688 = MOVT_D64
    5501             :   { 1689,       4,      1,      4,      224,    0, 0x4ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr },  // Inst #1689 = MOVT_I
    5502             :   { 1690,       4,      1,      4,      224,    0, 0x4ULL, nullptr, nullptr, OperandInfo254, -1 ,nullptr },  // Inst #1690 = MOVT_I64
    5503             :   { 1691,       4,      1,      4,      224,    0, 0x4ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr },  // Inst #1691 = MOVT_I_MM
    5504             :   { 1692,       4,      1,      4,      225,    0, 0x4ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr },  // Inst #1692 = MOVT_S
    5505             :   { 1693,       4,      1,      4,      225,    0, 0x4ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr },  // Inst #1693 = MOVT_S_MM
    5506             :   { 1694,       4,      1,      4,      226,    0, 0x4ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr },  // Inst #1694 = MOVZ_I64_D64
    5507             :   { 1695,       4,      1,      4,      227,    0, 0x4ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr },  // Inst #1695 = MOVZ_I64_I
    5508             :   { 1696,       4,      1,      4,      227,    0, 0x4ULL, nullptr, nullptr, OperandInfo258, -1 ,nullptr },  // Inst #1696 = MOVZ_I64_I64
    5509             :   { 1697,       4,      1,      4,      228,    0, 0x4ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr },  // Inst #1697 = MOVZ_I64_S
    5510             :   { 1698,       4,      1,      4,      226,    0, 0x4ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr },  // Inst #1698 = MOVZ_I_D32
    5511             :   { 1699,       4,      1,      4,      226,    0, 0x4ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr },  // Inst #1699 = MOVZ_I_D32_MM
    5512             :   { 1700,       4,      1,      4,      226,    0, 0x4ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr },  // Inst #1700 = MOVZ_I_D64
    5513             :   { 1701,       4,      1,      4,      227,    0, 0x4ULL, nullptr, nullptr, OperandInfo262, -1 ,nullptr },  // Inst #1701 = MOVZ_I_I
    5514             :   { 1702,       4,      1,      4,      227,    0, 0x4ULL, nullptr, nullptr, OperandInfo263, -1 ,nullptr },  // Inst #1702 = MOVZ_I_I64
    5515             :   { 1703,       4,      1,      4,      702,    0, 0x4ULL, nullptr, nullptr, OperandInfo262, -1 ,nullptr },  // Inst #1703 = MOVZ_I_MM
    5516             :   { 1704,       4,      1,      4,      228,    0, 0x4ULL, nullptr, nullptr, OperandInfo264, -1 ,nullptr },  // Inst #1704 = MOVZ_I_S
    5517             :   { 1705,       4,      1,      4,      228,    0, 0x4ULL, nullptr, nullptr, OperandInfo264, -1 ,nullptr },  // Inst #1705 = MOVZ_I_S_MM
    5518             :   { 1706,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr },  // Inst #1706 = MSA_FP_EXTEND_D_PSEUDO
    5519             :   { 1707,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr },  // Inst #1707 = MSA_FP_EXTEND_W_PSEUDO
    5520             :   { 1708,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr },  // Inst #1708 = MSA_FP_ROUND_D_PSEUDO
    5521             :   { 1709,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr },  // Inst #1709 = MSA_FP_ROUND_W_PSEUDO
    5522             :   { 1710,       2,      0,      4,      229,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList12, ImplicitList12, OperandInfo31, -1 ,nullptr },  // Inst #1710 = MSUB
    5523             :   { 1711,       4,      1,      4,      230,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo237, -1 ,nullptr },  // Inst #1711 = MSUBF_D
    5524             :   { 1712,       4,      1,      4,      230,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo237, -1 ,nullptr },  // Inst #1712 = MSUBF_D_MMR6
    5525             :   { 1713,       4,      1,      4,      231,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr },  // Inst #1713 = MSUBF_S
    5526             :   { 1714,       4,      1,      4,      231,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr },  // Inst #1714 = MSUBF_S_MMR6
    5527             :   { 1715,       4,      1,      4,      479,    0, 0x6ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #1715 = MSUBR_Q_H
    5528             :   { 1716,       4,      1,      4,      479,    0, 0x6ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #1716 = MSUBR_Q_W
    5529             :   { 1717,       2,      0,      4,      232,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList12, ImplicitList12, OperandInfo31, -1 ,nullptr },  // Inst #1717 = MSUBU
    5530             :   { 1718,       4,      1,      4,      543,    0, 0x6ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #1718 = MSUBU_DSP
    5531             :   { 1719,       4,      1,      4,      703,    0, 0x6ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #1719 = MSUBU_DSP_MM
    5532             :   { 1720,       2,      0,      4,      232,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList12, ImplicitList12, OperandInfo31, -1 ,nullptr },  // Inst #1720 = MSUBU_MM
    5533             :   { 1721,       4,      1,      4,      474,    0, 0x6ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr },  // Inst #1721 = MSUBV_B
    5534             :   { 1722,       4,      1,      4,      474,    0, 0x6ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #1722 = MSUBV_D
    5535             :   { 1723,       4,      1,      4,      474,    0, 0x6ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #1723 = MSUBV_H
    5536             :   { 1724,       4,      1,      4,      474,    0, 0x6ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #1724 = MSUBV_W
    5537             :   { 1725,       4,      1,      4,      233,    0, 0x4ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr },  // Inst #1725 = MSUB_D32
    5538             :   { 1726,       4,      1,      4,      233,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr },  // Inst #1726 = MSUB_D32_MM
    5539             :   { 1727,       4,      1,      4,      233,    0, 0x4ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr },  // Inst #1727 = MSUB_D64
    5540             :   { 1728,       4,      1,      4,      544,    0, 0x6ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #1728 = MSUB_DSP
    5541             :   { 1729,       4,      1,      4,      704,    0, 0x6ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #1729 = MSUB_DSP_MM
    5542             :   { 1730,       2,      0,      4,      229,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList12, ImplicitList12, OperandInfo31, -1 ,nullptr },  // Inst #1730 = MSUB_MM
    5543             :   { 1731,       4,      1,      4,      480,    0, 0x6ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #1731 = MSUB_Q_H
    5544             :   { 1732,       4,      1,      4,      480,    0, 0x6ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #1732 = MSUB_Q_W
    5545             :   { 1733,       4,      1,      4,      234,    0, 0x4ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr },  // Inst #1733 = MSUB_S
    5546             :   { 1734,       4,      1,      4,      234,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr },  // Inst #1734 = MSUB_S_MM
    5547             :   { 1735,       3,      1,      4,      235,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo269, -1 ,nullptr },  // Inst #1735 = MTC0
    5548             :   { 1736,       3,      1,      4,      235,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo269, -1 ,nullptr },  // Inst #1736 = MTC0_MMR6
    5549             :   { 1737,       2,      1,      4,      33,     0|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr },  // Inst #1737 = MTC1
    5550             :   { 1738,       2,      1,      4,      33,     0, 0x4ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr },  // Inst #1738 = MTC1_D64
    5551             :   { 1739,       2,      1,      4,      33,     0|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr },  // Inst #1739 = MTC1_MM
    5552             :   { 1740,       2,      1,      4,      33,     0|(1ULL<<MCID::Bitcast), 0x6ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr },  // Inst #1740 = MTC1_MMR6
    5553             :   { 1741,       3,      1,      4,      236,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo272, -1 ,nullptr },  // Inst #1741 = MTC2
    5554             :   { 1742,       2,      1,      4,      236,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #1742 = MTC2_MMR6
    5555             :   { 1743,       3,      1,      4,      237,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo269, -1 ,nullptr },  // Inst #1743 = MTGC0
    5556             :   { 1744,       3,      1,      4,      237,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo269, -1 ,nullptr },  // Inst #1744 = MTGC0_MM
    5557             :   { 1745,       3,      1,      4,      238,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo269, -1 ,nullptr },  // Inst #1745 = MTHC0_MMR6
    5558             :   { 1746,       3,      1,      4,      239,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo273, -1 ,nullptr },  // Inst #1746 = MTHC1_D32
    5559             :   { 1747,       3,      1,      4,      239,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo273, -1 ,nullptr },  // Inst #1747 = MTHC1_D32_MM
    5560             :   { 1748,       3,      1,      4,      239,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr },  // Inst #1748 = MTHC1_D64
    5561             :   { 1749,       3,      1,      4,      239,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr },  // Inst #1749 = MTHC1_D64_MM
    5562             :   { 1750,       2,      1,      4,      236,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #1750 = MTHC2_MMR6
    5563             :   { 1751,       3,      1,      4,      240,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo269, -1 ,nullptr },  // Inst #1751 = MTHGC0
    5564             :   { 1752,       3,      1,      4,      240,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo269, -1 ,nullptr },  // Inst #1752 = MTHGC0_MM
    5565             :   { 1753,       1,      0,      4,      241,    0, 0x1ULL, nullptr, ImplicitList21, OperandInfo86, -1 ,nullptr },  // Inst #1753 = MTHI
    5566             :   { 1754,       1,      0,      4,      241,    0, 0x1ULL, nullptr, ImplicitList22, OperandInfo191, -1 ,nullptr },  // Inst #1754 = MTHI64
    5567             :   { 1755,       2,      1,      4,      497,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr },  // Inst #1755 = MTHI_DSP
    5568             :   { 1756,       2,      1,      4,      705,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr },  // Inst #1756 = MTHI_DSP_MM
    5569             :   { 1757,       1,      0,      4,      241,    0, 0x1ULL, nullptr, ImplicitList21, OperandInfo86, -1 ,nullptr },  // Inst #1757 = MTHI_MM
    5570             :   { 1758,       3,      1,      4,      496,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList6, OperandInfo276, -1 ,nullptr },  // Inst #1758 = MTHLIP
    5571             :   { 1759,       3,      1,      4,      706,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList6, OperandInfo276, -1 ,nullptr },  // Inst #1759 = MTHLIP_MM
    5572             :   { 1760,       1,      0,      4,      241,    0, 0x1ULL, nullptr, ImplicitList23, OperandInfo86, -1 ,nullptr },  // Inst #1760 = MTLO
    5573             :   { 1761,       1,      0,      4,      241,    0, 0x1ULL, nullptr, ImplicitList24, OperandInfo191, -1 ,nullptr },  // Inst #1761 = MTLO64
    5574             :   { 1762,       2,      1,      4,      498,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo277, -1 ,nullptr },  // Inst #1762 = MTLO_DSP
    5575             :   { 1763,       2,      1,      4,      707,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo277, -1 ,nullptr },  // Inst #1763 = MTLO_DSP_MM
    5576             :   { 1764,       1,      0,      4,      241,    0, 0x1ULL, nullptr, ImplicitList23, OperandInfo86, -1 ,nullptr },  // Inst #1764 = MTLO_MM
    5577             :   { 1765,       1,      0,      4,      241,    0, 0x1ULL, nullptr, ImplicitList25, OperandInfo191, -1 ,nullptr },  // Inst #1765 = MTM0
    5578             :   { 1766,       1,      0,      4,      241,    0, 0x1ULL, nullptr, ImplicitList26, OperandInfo191, -1 ,nullptr },  // Inst #1766 = MTM1
    5579             :   { 1767,       1,      0,      4,      241,    0, 0x1ULL, nullptr, ImplicitList27, OperandInfo191, -1 ,nullptr },  // Inst #1767 = MTM2
    5580             :   { 1768,       1,      0,      4,      241,    0, 0x1ULL, nullptr, ImplicitList28, OperandInfo191, -1 ,nullptr },  // Inst #1768 = MTP0
    5581             :   { 1769,       1,      0,      4,      241,    0, 0x1ULL, nullptr, ImplicitList29, OperandInfo191, -1 ,nullptr },  // Inst #1769 = MTP1
    5582             :   { 1770,       1,      0,      4,      241,    0, 0x1ULL, nullptr, ImplicitList30, OperandInfo191, -1 ,nullptr },  // Inst #1770 = MTP2
    5583             :   { 1771,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo278, -1 ,nullptr },  // Inst #1771 = MTTACX
    5584             :   { 1772,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo269, -1 ,nullptr },  // Inst #1772 = MTTC0
    5585             :   { 1773,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr },  // Inst #1773 = MTTC1
    5586             :   { 1774,       1,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1774 = MTTDSP
    5587             :   { 1775,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1775 = MTTGPR
    5588             :   { 1776,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr },  // Inst #1776 = MTTHC1
    5589             :   { 1777,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo278, -1 ,nullptr },  // Inst #1777 = MTTHI
    5590             :   { 1778,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo278, -1 ,nullptr },  // Inst #1778 = MTTLO
    5591             :   { 1779,       5,      1,      4,      242,    0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr },  // Inst #1779 = MTTR
    5592             :   { 1780,       3,      1,      4,      243,    0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1780 = MUH
    5593             :   { 1781,       3,      1,      4,      244,    0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1781 = MUHU
    5594             :   { 1782,       3,      1,      4,      244,    0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1782 = MUHU_MMR6
    5595             :   { 1783,       3,      1,      4,      243,    0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1783 = MUH_MMR6
    5596             :   { 1784,       3,      1,      4,      245,    0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, ImplicitList12, OperandInfo33, -1 ,nullptr },  // Inst #1784 = MUL
    5597             :   { 1785,       3,      1,      4,      545,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo105, -1 ,nullptr },  // Inst #1785 = MULEQ_S_W_PHL
    5598             :   { 1786,       3,      1,      4,      708,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo105, -1 ,nullptr },  // Inst #1786 = MULEQ_S_W_PHL_MM
    5599             :   { 1787,       3,      1,      4,      546,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo105, -1 ,nullptr },  // Inst #1787 = MULEQ_S_W_PHR
    5600             :   { 1788,       3,      1,      4,      709,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo105, -1 ,nullptr },  // Inst #1788 = MULEQ_S_W_PHR_MM
    5601             :   { 1789,       3,      1,      4,      547,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo39, -1 ,nullptr },  // Inst #1789 = MULEU_S_PH_QBL
    5602             :   { 1790,       3,      1,      4,      710,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo39, -1 ,nullptr },  // Inst #1790 = MULEU_S_PH_QBL_MM
    5603             :   { 1791,       3,      1,      4,      548,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo39, -1 ,nullptr },  // Inst #1791 = MULEU_S_PH_QBR
    5604             :   { 1792,       3,      1,      4,      711,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo39, -1 ,nullptr },  // Inst #1792 = MULEU_S_PH_QBR_MM
    5605             :   { 1793,       3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1793 = MULImmMacro
    5606             :   { 1794,       3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1794 = MULOMacro
    5607             :   { 1795,       3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1795 = MULOUMacro
    5608             :   { 1796,       3,      1,      4,      549,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo39, -1 ,nullptr },  // Inst #1796 = MULQ_RS_PH
    5609             :   { 1797,       3,      1,      4,      712,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo39, -1 ,nullptr },  // Inst #1797 = MULQ_RS_PH_MM
    5610             :   { 1798,       3,      1,      4,      624,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo33, -1 ,nullptr },  // Inst #1798 = MULQ_RS_W
    5611             :   { 1799,       3,      1,      4,      787,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo33, -1 ,nullptr },  // Inst #1799 = MULQ_RS_W_MMR2
    5612             :   { 1800,       3,      1,      4,      625,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo39, -1 ,nullptr },  // Inst #1800 = MULQ_S_PH
    5613             :   { 1801,       3,      1,      4,      788,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo39, -1 ,nullptr },  // Inst #1801 = MULQ_S_PH_MMR2
    5614             :   { 1802,       3,      1,      4,      626,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo33, -1 ,nullptr },  // Inst #1802 = MULQ_S_W
    5615             :   { 1803,       3,      1,      4,      789,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo33, -1 ,nullptr },  // Inst #1803 = MULQ_S_W_MMR2
    5616             :   { 1804,       3,      1,      4,      481,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #1804 = MULR_Q_H
    5617             :   { 1805,       3,      1,      4,      481,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1805 = MULR_Q_W
    5618             :   { 1806,       4,      1,      4,      550,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList11, OperandInfo140, -1 ,nullptr },  // Inst #1806 = MULSAQ_S_W_PH
    5619             :   { 1807,       4,      1,      4,      713,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList11, OperandInfo140, -1 ,nullptr },  // Inst #1807 = MULSAQ_S_W_PH_MM
    5620             :   { 1808,       4,      1,      4,      627,    0, 0x6ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #1808 = MULSA_W_PH
    5621             :   { 1809,       4,      1,      4,      790,    0, 0x6ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #1809 = MULSA_W_PH_MMR2
    5622             :   { 1810,       2,      0,      4,      246,    0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList12, OperandInfo31, -1 ,nullptr },  // Inst #1810 = MULT
    5623             :   { 1811,       3,      1,      4,      551,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo279, -1 ,nullptr },  // Inst #1811 = MULTU_DSP
    5624             :   { 1812,       3,      1,      4,      714,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo279, -1 ,nullptr },  // Inst #1812 = MULTU_DSP_MM
    5625             :   { 1813,       3,      1,      4,      552,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo279, -1 ,nullptr },  // Inst #1813 = MULT_DSP
    5626             :   { 1814,       3,      1,      4,      715,    0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo279, -1 ,nullptr },  // Inst #1814 = MULT_DSP_MM
    5627             :   { 1815,       2,      0,      4,      246,    0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList12, OperandInfo31, -1 ,nullptr },  // Inst #1815 = MULT_MM
    5628             :   { 1816,       2,      0,      4,      247,    0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList12, OperandInfo31, -1 ,nullptr },  // Inst #1816 = MULTu
    5629             :   { 1817,       2,      0,      4,      247,    0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList12, OperandInfo31, -1 ,nullptr },  // Inst #1817 = MULTu_MM
    5630             :   { 1818,       3,      1,      4,      248,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1818 = MULU
    5631             :   { 1819,       3,      1,      4,      248,    0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1819 = MULU_MMR6
    5632             :   { 1820,       3,      1,      4,      476,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1820 = MULV_B
    5633             :   { 1821,       3,      1,      4,      476,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1821 = MULV_D
    5634             :   { 1822,       3,      1,      4,      476,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #1822 = MULV_H
    5635             :   { 1823,       3,      1,      4,      476,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1823 = MULV_W
    5636             :   { 1824,       3,      1,      4,      245,    0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1824 = MUL_MM
    5637             :   { 1825,       3,      1,      4,      245,    0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1825 = MUL_MMR6
    5638             :   { 1826,       3,      1,      4,      622,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo39, -1 ,nullptr },  // Inst #1826 = MUL_PH
    5639             :   { 1827,       3,      1,      4,      785,    0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo39, -1 ,nullptr },  // Inst #1827 = MUL_PH_MMR2
    5640             :   { 1828,       3,      1,      4,      482,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #1828 = MUL_Q_H
    5641             :   { 1829,       3,      1,      4,      482,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1829 = MUL_Q_W
    5642             :   { 1830,       3,      1,      4,      245,    0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1830 = MUL_R6
    5643             :   { 1831,       3,      1,      4,      623,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo39, -1 ,nullptr },  // Inst #1831 = MUL_S_PH
    5644             :   { 1832,       3,      1,      4,      786,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo39, -1 ,nullptr },  // Inst #1832 = MUL_S_PH_MMR2
    5645             :   { 1833,       1,      1,      2,      13,     0, 0x0ULL, ImplicitList21, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1833 = Mfhi16
    5646             :   { 1834,       1,      1,      2,      13,     0, 0x0ULL, ImplicitList23, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1834 = Mflo16
    5647             :   { 1835,       2,      1,      2,      13,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo280, -1 ,nullptr },  // Inst #1835 = Move32R16
    5648             :   { 1836,       2,      1,      2,      13,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo281, -1 ,nullptr },  // Inst #1836 = MoveR3216
    5649             :   { 1837,       2,      0,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList12, OperandInfo122, -1 ,nullptr },  // Inst #1837 = MultRxRy16
    5650             :   { 1838,       3,      1,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList12, OperandInfo61, -1 ,nullptr },  // Inst #1838 = MultRxRyRz16
    5651             :   { 1839,       2,      0,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList12, OperandInfo122, -1 ,nullptr },  // Inst #1839 = MultuRxRy16
    5652             :   { 1840,       3,      1,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList12, OperandInfo61, -1 ,nullptr },  // Inst #1840 = MultuRxRyRz16
    5653             :   { 1841,       2,      1,      4,      459,    0, 0x6ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr },  // Inst #1841 = NLOC_B
    5654             :   { 1842,       2,      1,      4,      459,    0, 0x6ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #1842 = NLOC_D
    5655             :   { 1843,       2,      1,      4,      459,    0, 0x6ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr },  // Inst #1843 = NLOC_H
    5656             :   { 1844,       2,      1,      4,      459,    0, 0x6ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #1844 = NLOC_W
    5657             :   { 1845,       2,      1,      4,      459,    0, 0x6ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr },  // Inst #1845 = NLZC_B
    5658             :   { 1846,       2,      1,      4,      459,    0, 0x6ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #1846 = NLZC_D
    5659             :   { 1847,       2,      1,      4,      459,    0, 0x6ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr },  // Inst #1847 = NLZC_H
    5660             :   { 1848,       2,      1,      4,      459,    0, 0x6ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #1848 = NLZC_W
    5661             :   { 1849,       4,      1,      4,      249,    0, 0x4ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr },  // Inst #1849 = NMADD_D32
    5662             :   { 1850,       4,      1,      4,      249,    0, 0x4ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr },  // Inst #1850 = NMADD_D32_MM
    5663             :   { 1851,       4,      1,      4,      249,    0, 0x4ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr },  // Inst #1851 = NMADD_D64
    5664             :   { 1852,       4,      1,      4,      250,    0, 0x4ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr },  // Inst #1852 = NMADD_S
    5665             :   { 1853,       4,      1,      4,      250,    0, 0x4ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr },  // Inst #1853 = NMADD_S_MM
    5666             :   { 1854,       4,      1,      4,      251,    0, 0x4ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr },  // Inst #1854 = NMSUB_D32
    5667             :   { 1855,       4,      1,      4,      251,    0, 0x4ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr },  // Inst #1855 = NMSUB_D32_MM
    5668             :   { 1856,       4,      1,      4,      251,    0, 0x4ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr },  // Inst #1856 = NMSUB_D64
    5669             :   { 1857,       4,      1,      4,      252,    0, 0x4ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr },  // Inst #1857 = NMSUB_S
    5670             :   { 1858,       4,      1,      4,      252,    0, 0x4ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr },  // Inst #1858 = NMSUB_S_MM
    5671             :   { 1859,       0,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1859 = NOP
    5672             :   { 1860,       3,      1,      4,      253,    0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1860 = NOR
    5673             :   { 1861,       3,      1,      4,      253,    0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #1861 = NOR64
    5674             :   { 1862,       3,      1,      4,      384,    0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #1862 = NORI_B
    5675             :   { 1863,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1863 = NORImm
    5676             :   { 1864,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #1864 = NORImm64
    5677             :   { 1865,       3,      1,      4,      253,    0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1865 = NOR_MM
    5678             :   { 1866,       3,      1,      4,      253,    0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1866 = NOR_MMR6
    5679             :   { 1867,       3,      1,      4,      383,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1867 = NOR_V
    5680             :   { 1868,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1868 = NOR_V_D_PSEUDO
    5681             :   { 1869,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #1869 = NOR_V_H_PSEUDO
    5682             :   { 1870,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1870 = NOR_V_W_PSEUDO
    5683             :   { 1871,       2,      1,      2,      254,    0, 0x0ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr },  // Inst #1871 = NOT16_MM
    5684             :   { 1872,       2,      1,      2,      254,    0, 0x0ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr },  // Inst #1872 = NOT16_MMR6
    5685             :   { 1873,       2,      1,      2,      13,     0, 0x0ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #1873 = NegRxRy16
    5686             :   { 1874,       2,      1,      2,      13,     0, 0x0ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #1874 = NotRxRy16
    5687             :   { 1875,       3,      1,      4,      255,    0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1875 = OR
    5688             :   { 1876,       3,      1,      2,      255,    0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #1876 = OR16_MM
    5689             :   { 1877,       3,      1,      2,      255,    0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #1877 = OR16_MMR6
    5690             :   { 1878,       3,      1,      4,      255,    0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #1878 = OR64
    5691             :   { 1879,       3,      1,      4,      384,    0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #1879 = ORI_B
    5692             :   { 1880,       3,      1,      4,      256,    0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1880 = ORI_MMR6
    5693             :   { 1881,       3,      1,      4,      255,    0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1881 = OR_MM
    5694             :   { 1882,       3,      1,      4,      255,    0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1882 = OR_MMR6
    5695             :   { 1883,       3,      1,      4,      383,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1883 = OR_V
    5696             :   { 1884,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1884 = OR_V_D_PSEUDO
    5697             :   { 1885,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #1885 = OR_V_H_PSEUDO
    5698             :   { 1886,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1886 = OR_V_W_PSEUDO
    5699             :   { 1887,       3,      1,      4,      256,    0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1887 = ORi
    5700             :   { 1888,       3,      1,      4,      255,    0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #1888 = ORi64
    5701             :   { 1889,       3,      1,      4,      256,    0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1889 = ORi_MM
    5702             :   { 1890,       3,      1,      2,      13,     0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr },  // Inst #1890 = OrRxRxRy16
    5703             :   { 1891,       3,      1,      4,      553,    0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #1891 = PACKRL_PH
    5704             :   { 1892,       3,      1,      4,      716,    0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #1892 = PACKRL_PH_MM
    5705             :   { 1893,       0,      0,      4,      257,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1893 = PAUSE
    5706             :   { 1894,       0,      0,      4,      257,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1894 = PAUSE_MM
    5707             :   { 1895,       0,      0,      4,      257,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1895 = PAUSE_MMR6
    5708             :   { 1896,       3,      1,      4,      458,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1896 = PCKEV_B
    5709             :   { 1897,       3,      1,      4,      458,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1897 = PCKEV_D
    5710             :   { 1898,       3,      1,      4,      458,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #1898 = PCKEV_H
    5711             :   { 1899,       3,      1,      4,      458,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1899 = PCKEV_W
    5712             :   { 1900,       3,      1,      4,      458,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1900 = PCKOD_B
    5713             :   { 1901,       3,      1,      4,      458,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1901 = PCKOD_D
    5714             :   { 1902,       3,      1,      4,      458,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #1902 = PCKOD_H
    5715             :   { 1903,       3,      1,      4,      458,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #1903 = PCKOD_W
    5716             :   { 1904,       2,      1,      4,      369,    0, 0x6ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr },  // Inst #1904 = PCNT_B
    5717             :   { 1905,       2,      1,      4,      369,    0, 0x6ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #1905 = PCNT_D
    5718             :   { 1906,       2,      1,      4,      369,    0, 0x6ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr },  // Inst #1906 = PCNT_H
    5719             :   { 1907,       2,      1,      4,      369,    0, 0x6ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #1907 = PCNT_W
    5720             :   { 1908,       3,      1,      4,      554,    0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList8, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #1908 = PICK_PH
    5721             :   { 1909,       3,      1,      4,      717,    0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList8, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #1909 = PICK_PH_MM
    5722             :   { 1910,       3,      1,      4,      555,    0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList8, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #1910 = PICK_QB
    5723             :   { 1911,       3,      1,      4,      718,    0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList8, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #1911 = PICK_QB_MM
    5724             :   { 1912,       2,      1,      4,      94,     0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1912 = POP
    5725             :   { 1913,       2,      1,      4,      557,    0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1913 = PRECEQU_PH_QBL
    5726             :   { 1914,       2,      1,      4,      556,    0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1914 = PRECEQU_PH_QBLA
    5727             :   { 1915,       2,      1,      4,      719,    0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1915 = PRECEQU_PH_QBLA_MM
    5728             :   { 1916,       2,      1,      4,      720,    0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1916 = PRECEQU_PH_QBL_MM
    5729             :   { 1917,       2,      1,      4,      559,    0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1917 = PRECEQU_PH_QBR
    5730             :   { 1918,       2,      1,      4,      558,    0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1918 = PRECEQU_PH_QBRA
    5731             :   { 1919,       2,      1,      4,      721,    0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1919 = PRECEQU_PH_QBRA_MM
    5732             :   { 1920,       2,      1,      4,      722,    0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1920 = PRECEQU_PH_QBR_MM
    5733             :   { 1921,       2,      1,      4,      560,    0, 0x6ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr },  // Inst #1921 = PRECEQ_W_PHL
    5734             :   { 1922,       2,      1,      4,      723,    0, 0x6ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr },  // Inst #1922 = PRECEQ_W_PHL_MM
    5735             :   { 1923,       2,      1,      4,      561,    0, 0x6ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr },  // Inst #1923 = PRECEQ_W_PHR
    5736             :   { 1924,       2,      1,      4,      724,    0, 0x6ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr },  // Inst #1924 = PRECEQ_W_PHR_MM
    5737             :   { 1925,       2,      1,      4,      563,    0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1925 = PRECEU_PH_QBL
    5738             :   { 1926,       2,      1,      4,      562,    0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1926 = PRECEU_PH_QBLA
    5739             :   { 1927,       2,      1,      4,      725,    0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1927 = PRECEU_PH_QBLA_MM
    5740             :   { 1928,       2,      1,      4,      726,    0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1928 = PRECEU_PH_QBL_MM
    5741             :   { 1929,       2,      1,      4,      565,    0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1929 = PRECEU_PH_QBR
    5742             :   { 1930,       2,      1,      4,      564,    0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1930 = PRECEU_PH_QBRA
    5743             :   { 1931,       2,      1,      4,      727,    0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1931 = PRECEU_PH_QBRA_MM
    5744             :   { 1932,       2,      1,      4,      728,    0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1932 = PRECEU_PH_QBR_MM
    5745             :   { 1933,       3,      1,      4,      566,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo39, -1 ,nullptr },  // Inst #1933 = PRECRQU_S_QB_PH
    5746             :   { 1934,       3,      1,      4,      729,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo39, -1 ,nullptr },  // Inst #1934 = PRECRQU_S_QB_PH_MM
    5747             :   { 1935,       3,      1,      4,      567,    0, 0x6ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr },  // Inst #1935 = PRECRQ_PH_W
    5748             :   { 1936,       3,      1,      4,      730,    0, 0x6ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr },  // Inst #1936 = PRECRQ_PH_W_MM
    5749             :   { 1937,       3,      1,      4,      568,    0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #1937 = PRECRQ_QB_PH
    5750             :   { 1938,       3,      1,      4,      731,    0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #1938 = PRECRQ_QB_PH_MM
    5751             :   { 1939,       3,      1,      4,      569,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo285, -1 ,nullptr },  // Inst #1939 = PRECRQ_RS_PH_W
    5752             :   { 1940,       3,      1,      4,      732,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo285, -1 ,nullptr },  // Inst #1940 = PRECRQ_RS_PH_W_MM
    5753             :   { 1941,       3,      1,      4,      628,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #1941 = PRECR_QB_PH
    5754             :   { 1942,       3,      1,      4,      791,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #1942 = PRECR_QB_PH_MMR2
    5755             :   { 1943,       4,      1,      4,      629,    0, 0x6ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr },  // Inst #1943 = PRECR_SRA_PH_W
    5756             :   { 1944,       4,      1,      4,      792,    0, 0x6ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr },  // Inst #1944 = PRECR_SRA_PH_W_MMR2
    5757             :   { 1945,       4,      1,      4,      630,    0, 0x6ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr },  // Inst #1945 = PRECR_SRA_R_PH_W
    5758             :   { 1946,       4,      1,      4,      793,    0, 0x6ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr },  // Inst #1946 = PRECR_SRA_R_PH_W_MMR2
    5759             :   { 1947,       3,      0,      4,      258,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #1947 = PREF
    5760             :   { 1948,       3,      0,      4,      259,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #1948 = PREFE
    5761             :   { 1949,       3,      0,      4,      259,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #1949 = PREFE_MM
    5762             :   { 1950,       3,      0,      4,      258,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr },  // Inst #1950 = PREFX_MM
    5763             :   { 1951,       3,      0,      4,      258,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #1951 = PREF_MM
    5764             :   { 1952,       3,      0,      4,      258,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #1952 = PREF_MMR6
    5765             :   { 1953,       3,      0,      4,      258,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #1953 = PREF_R6
    5766             :   { 1954,       4,      1,      4,      631,    0, 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #1954 = PREPEND
    5767             :   { 1955,       4,      1,      4,      794,    0, 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #1955 = PREPEND_MMR2
    5768             :   { 1956,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo288, -1 ,nullptr },  // Inst #1956 = PseudoCMPU_EQ_QB
    5769             :   { 1957,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo288, -1 ,nullptr },  // Inst #1957 = PseudoCMPU_LE_QB
    5770             :   { 1958,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo288, -1 ,nullptr },  // Inst #1958 = PseudoCMPU_LT_QB
    5771             :   { 1959,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo288, -1 ,nullptr },  // Inst #1959 = PseudoCMP_EQ_PH
    5772             :   { 1960,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo288, -1 ,nullptr },  // Inst #1960 = PseudoCMP_LE_PH
    5773             :   { 1961,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo288, -1 ,nullptr },  // Inst #1961 = PseudoCMP_LT_PH
    5774             :   { 1962,       2,      1,      4,      56,     0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo289, -1 ,nullptr },  // Inst #1962 = PseudoCVT_D32_W
    5775             :   { 1963,       2,      1,      4,      56,     0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr },  // Inst #1963 = PseudoCVT_D64_L
    5776             :   { 1964,       2,      1,      4,      56,     0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr },  // Inst #1964 = PseudoCVT_D64_W
    5777             :   { 1965,       2,      1,      4,      56,     0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr },  // Inst #1965 = PseudoCVT_S_L
    5778             :   { 1966,       2,      1,      4,      56,     0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr },  // Inst #1966 = PseudoCVT_S_W
    5779             :   { 1967,       3,      1,      4,      92,     0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr },  // Inst #1967 = PseudoDMULT
    5780             :   { 1968,       3,      1,      4,      93,     0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr },  // Inst #1968 = PseudoDMULTu
    5781             :   { 1969,       3,      1,      4,      70,     0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr },  // Inst #1969 = PseudoDSDIV
    5782             :   { 1970,       3,      1,      4,      71,     0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr },  // Inst #1970 = PseudoDUDIV
    5783             :   { 1971,       1,      0,      4,      260,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1971 = PseudoIndirectBranch
    5784             :   { 1972,       1,      0,      4,      260,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr },  // Inst #1972 = PseudoIndirectBranch64
    5785             :   { 1973,       1,      0,      4,      260,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr },  // Inst #1973 = PseudoIndirectBranch64R6
    5786             :   { 1974,       1,      0,      4,      260,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1974 = PseudoIndirectBranchR6
    5787             :   { 1975,       1,      0,      4,      260,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1975 = PseudoIndirectBranch_MM
    5788             :   { 1976,       1,      0,      4,      260,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1976 = PseudoIndirectBranch_MMR6
    5789             :   { 1977,       1,      0,      4,      260,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1977 = PseudoIndirectHazardBranch
    5790             :   { 1978,       1,      0,      4,      260,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr },  // Inst #1978 = PseudoIndirectHazardBranch64
    5791             :   { 1979,       1,      0,      4,      260,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr },  // Inst #1979 = PseudoIndrectHazardBranch64R6
    5792             :   { 1980,       1,      0,      4,      260,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1980 = PseudoIndrectHazardBranchR6
    5793             :   { 1981,       4,      1,      4,      192,    0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr },  // Inst #1981 = PseudoMADD
    5794             :   { 1982,       4,      1,      4,      195,    0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr },  // Inst #1982 = PseudoMADDU
    5795             :   { 1983,       2,      1,      4,      208,    0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr },  // Inst #1983 = PseudoMFHI
    5796             :   { 1984,       2,      1,      4,      208,    0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo293, -1 ,nullptr },  // Inst #1984 = PseudoMFHI64
    5797             :   { 1985,       2,      1,      4,      208,    0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr },  // Inst #1985 = PseudoMFLO
    5798             :   { 1986,       2,      1,      4,      208,    0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo293, -1 ,nullptr },  // Inst #1986 = PseudoMFLO64
    5799             :   { 1987,       4,      1,      4,      229,    0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr },  // Inst #1987 = PseudoMSUB
    5800             :   { 1988,       4,      1,      4,      232,    0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr },  // Inst #1988 = PseudoMSUBU
    5801             :   { 1989,       3,      1,      4,      241,    0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr },  // Inst #1989 = PseudoMTLOHI
    5802             :   { 1990,       3,      1,      4,      241,    0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr },  // Inst #1990 = PseudoMTLOHI64
    5803             :   { 1991,       3,      1,      4,      241,    0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo279, -1 ,nullptr },  // Inst #1991 = PseudoMTLOHI_DSP
    5804             :   { 1992,       3,      1,      4,      246,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr },  // Inst #1992 = PseudoMULT
    5805             :   { 1993,       3,      1,      4,      247,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr },  // Inst #1993 = PseudoMULTu
    5806             :   { 1994,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr },  // Inst #1994 = PseudoPICK_PH
    5807             :   { 1995,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr },  // Inst #1995 = PseudoPICK_QB
    5808             :   { 1996,       1,      0,      4,      261,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1996 = PseudoReturn
    5809             :   { 1997,       1,      0,      4,      261,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr },  // Inst #1997 = PseudoReturn64
    5810             :   { 1998,       3,      1,      4,      75,     0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr },  // Inst #1998 = PseudoSDIV
    5811             :   { 1999,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr },  // Inst #1999 = PseudoSELECTFP_F_D32
    5812             :   { 2000,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr },  // Inst #2000 = PseudoSELECTFP_F_D64
    5813             :   { 2001,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo298, -1 ,nullptr },  // Inst #2001 = PseudoSELECTFP_F_I
    5814             :   { 2002,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo299, -1 ,nullptr },  // Inst #2002 = PseudoSELECTFP_F_I64
    5815             :   { 2003,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo300, -1 ,nullptr },  // Inst #2003 = PseudoSELECTFP_F_S
    5816             :   { 2004,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr },  // Inst #2004 = PseudoSELECTFP_T_D32
    5817             :   { 2005,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr },  // Inst #2005 = PseudoSELECTFP_T_D64
    5818             :   { 2006,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo298, -1 ,nullptr },  // Inst #2006 = PseudoSELECTFP_T_I
    5819             :   { 2007,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo299, -1 ,nullptr },  // Inst #2007 = PseudoSELECTFP_T_I64
    5820             :   { 2008,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo300, -1 ,nullptr },  // Inst #2008 = PseudoSELECTFP_T_S
    5821             :   { 2009,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo301, -1 ,nullptr },  // Inst #2009 = PseudoSELECT_D32
    5822             :   { 2010,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo302, -1 ,nullptr },  // Inst #2010 = PseudoSELECT_D64
    5823             :   { 2011,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr },  // Inst #2011 = PseudoSELECT_I
    5824             :   { 2012,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo304, -1 ,nullptr },  // Inst #2012 = PseudoSELECT_I64
    5825             :   { 2013,       4,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo305, -1 ,nullptr },  // Inst #2013 = PseudoSELECT_S
    5826             :   { 2014,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo306, -1 ,nullptr },  // Inst #2014 = PseudoTRUNC_W_D
    5827             :   { 2015,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo307, -1 ,nullptr },  // Inst #2015 = PseudoTRUNC_W_D32
    5828             :   { 2016,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo308, -1 ,nullptr },  // Inst #2016 = PseudoTRUNC_W_S
    5829             :   { 2017,       3,      1,      4,      76,     0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr },  // Inst #2017 = PseudoUDIV
    5830             :   { 2018,       2,      1,      4,      570,    0, 0x6ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr },  // Inst #2018 = RADDU_W_QB
    5831             :   { 2019,       2,      1,      4,      733,    0, 0x6ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr },  // Inst #2019 = RADDU_W_QB_MM
    5832             :   { 2020,       2,      1,      4,      571,    0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #2020 = RDDSP
    5833             :   { 2021,       2,      1,      4,      734,    0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #2021 = RDDSP_MM
    5834             :   { 2022,       2,      1,      4,      262,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo309, -1 ,nullptr },  // Inst #2022 = RDHWR
    5835             :   { 2023,       2,      1,      4,      262,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo310, -1 ,nullptr },  // Inst #2023 = RDHWR64
    5836             :   { 2024,       2,      1,      4,      262,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo309, -1 ,nullptr },  // Inst #2024 = RDHWR_MM
    5837             :   { 2025,       3,      1,      4,      262,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo311, -1 ,nullptr },  // Inst #2025 = RDHWR_MMR6
    5838             :   { 2026,       2,      1,      4,      263,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #2026 = RDPGPR_MMR6
    5839             :   { 2027,       2,      1,      4,      264,    0, 0x4ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #2027 = RECIP_D32
    5840             :   { 2028,       2,      1,      4,      264,    0, 0x4ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #2028 = RECIP_D32_MM
    5841             :   { 2029,       2,      1,      4,      264,    0, 0x4ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #2029 = RECIP_D64
    5842             :   { 2030,       2,      1,      4,      264,    0, 0x4ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #2030 = RECIP_D64_MM
    5843             :   { 2031,       2,      1,      4,      265,    0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #2031 = RECIP_S
    5844             :   { 2032,       2,      1,      4,      265,    0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #2032 = RECIP_S_MM
    5845             :   { 2033,       2,      1,      4,      572,    0, 0x6ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr },  // Inst #2033 = REPLV_PH
    5846             :   { 2034,       2,      1,      4,      735,    0, 0x6ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr },  // Inst #2034 = REPLV_PH_MM
    5847             :   { 2035,       2,      1,      4,      573,    0, 0x6ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr },  // Inst #2035 = REPLV_QB
    5848             :   { 2036,       2,      1,      4,      736,    0, 0x6ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr },  // Inst #2036 = REPLV_QB_MM
    5849             :   { 2037,       2,      1,      4,      574,    0, 0x6ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr },  // Inst #2037 = REPL_PH
    5850             :   { 2038,       2,      1,      4,      737,    0, 0x6ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr },  // Inst #2038 = REPL_PH_MM
    5851             :   { 2039,       2,      1,      4,      575,    0, 0x6ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr },  // Inst #2039 = REPL_QB
    5852             :   { 2040,       2,      1,      4,      738,    0, 0x6ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr },  // Inst #2040 = REPL_QB_MM
    5853             :   { 2041,       2,      1,      4,      266,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #2041 = RINT_D
    5854             :   { 2042,       2,      1,      4,      267,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #2042 = RINT_D_MMR6
    5855             :   { 2043,       2,      1,      4,      267,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #2043 = RINT_S
    5856             :   { 2044,       2,      1,      4,      267,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #2044 = RINT_S_MMR6
    5857             :   { 2045,       3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2045 = ROL
    5858             :   { 2046,       3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2046 = ROLImm
    5859             :   { 2047,       3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2047 = ROR
    5860             :   { 2048,       3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2048 = RORImm
    5861             :   { 2049,       3,      1,      4,      268,    0, 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2049 = ROTR
    5862             :   { 2050,       3,      1,      4,      269,    0, 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2050 = ROTRV
    5863             :   { 2051,       3,      1,      4,      269,    0, 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2051 = ROTRV_MM
    5864             :   { 2052,       3,      1,      4,      268,    0, 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2052 = ROTR_MM
    5865             :   { 2053,       2,      1,      4,      270,    0, 0x4ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #2053 = ROUND_L_D64
    5866             :   { 2054,       2,      1,      4,      270,    0, 0x4ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #2054 = ROUND_L_D_MMR6
    5867             :   { 2055,       2,      1,      4,      270,    0, 0x4ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #2055 = ROUND_L_S
    5868             :   { 2056,       2,      1,      4,      270,    0, 0x4ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #2056 = ROUND_L_S_MMR6
    5869             :   { 2057,       2,      1,      4,      270,    0, 0x4ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #2057 = ROUND_W_D32
    5870             :   { 2058,       2,      1,      4,      270,    0, 0x4ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr },  // Inst #2058 = ROUND_W_D64
    5871             :   { 2059,       2,      1,      4,      270,    0, 0x4ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #2059 = ROUND_W_D_MMR6
    5872             :   { 2060,       2,      1,      4,      270,    0, 0x4ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #2060 = ROUND_W_MM
    5873             :   { 2061,       2,      1,      4,      270,    0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #2061 = ROUND_W_S
    5874             :   { 2062,       2,      1,      4,      270,    0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #2062 = ROUND_W_S_MM
    5875             :   { 2063,       2,      1,      4,      270,    0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #2063 = ROUND_W_S_MMR6
    5876             :   { 2064,       2,      1,      4,      271,    0, 0x4ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #2064 = RSQRT_D32
    5877             :   { 2065,       2,      1,      4,      264,    0, 0x4ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #2065 = RSQRT_D32_MM
    5878             :   { 2066,       2,      1,      4,      271,    0, 0x4ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #2066 = RSQRT_D64
    5879             :   { 2067,       2,      1,      4,      264,    0, 0x4ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #2067 = RSQRT_D64_MM
    5880             :   { 2068,       2,      1,      4,      272,    0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #2068 = RSQRT_S
    5881             :   { 2069,       2,      1,      4,      265,    0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #2069 = RSQRT_S_MM
    5882             :   { 2070,       0,      0,      2,      273,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList3, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #2070 = Restore16
    5883             :   { 2071,       0,      0,      2,      273,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList3, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #2071 = RestoreX16
    5884             :   { 2072,       0,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2072 = RetRA
    5885             :   { 2073,       0,      0,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2073 = RetRA16
    5886             :   { 2074,       3,      1,      4,      370,    0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #2074 = SAT_S_B
    5887             :   { 2075,       3,      1,      4,      370,    0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #2075 = SAT_S_D
    5888             :   { 2076,       3,      1,      4,      370,    0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #2076 = SAT_S_H
    5889             :   { 2077,       3,      1,      4,      370,    0, 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #2077 = SAT_S_W
    5890             :   { 2078,       3,      1,      4,      370,    0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #2078 = SAT_U_B
    5891             :   { 2079,       3,      1,      4,      370,    0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #2079 = SAT_U_D
    5892             :   { 2080,       3,      1,      4,      370,    0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #2080 = SAT_U_H
    5893             :   { 2081,       3,      1,      4,      370,    0, 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #2081 = SAT_U_W
    5894             :   { 2082,       3,      0,      4,      274,    0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #2082 = SB
    5895             :   { 2083,       3,      0,      2,      274,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo314, -1 ,nullptr },  // Inst #2083 = SB16_MM
    5896             :   { 2084,       3,      0,      2,      274,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo314, -1 ,nullptr },  // Inst #2084 = SB16_MMR6
    5897             :   { 2085,       3,      0,      4,      274,    0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #2085 = SB64
    5898             :   { 2086,       3,      0,      4,      275,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #2086 = SBE
    5899             :   { 2087,       3,      0,      4,      275,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #2087 = SBE_MM
    5900             :   { 2088,       3,      0,      4,      274,    0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #2088 = SB_MM
    5901             :   { 2089,       3,      0,      4,      274,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #2089 = SB_MMR6
    5902             :   { 2090,       4,      1,      4,      276,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr },  // Inst #2090 = SC
    5903             :   { 2091,       4,      1,      4,      276,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr },  // Inst #2091 = SC64
    5904             :   { 2092,       4,      1,      4,      276,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr },  // Inst #2092 = SC64_R6
    5905             :   { 2093,       4,      1,      4,      276,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo316, -1 ,nullptr },  // Inst #2093 = SCD
    5906             :   { 2094,       4,      1,      4,      277,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo316, -1 ,nullptr },  // Inst #2094 = SCD_R6
    5907             :   { 2095,       4,      1,      4,      278,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr },  // Inst #2095 = SCE
    5908             :   { 2096,       4,      1,      4,      278,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr },  // Inst #2096 = SCE_MM
    5909             :   { 2097,       4,      1,      4,      276,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr },  // Inst #2097 = SC_MM
    5910             :   { 2098,       4,      1,      4,      276,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr },  // Inst #2098 = SC_R6
    5911             :   { 2099,       3,      0,      4,      279,    0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #2099 = SD
    5912             :   { 2100,       1,      0,      4,      280,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #2100 = SDBBP
    5913             :   { 2101,       1,      0,      2,      280,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #2101 = SDBBP16_MM
    5914             :   { 2102,       1,      0,      2,      280,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #2102 = SDBBP16_MMR6
    5915             :   { 2103,       1,      0,      4,      280,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #2103 = SDBBP_MM
    5916             :   { 2104,       1,      0,      4,      280,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #2104 = SDBBP_MMR6
    5917             :   { 2105,       1,      0,      4,      280,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #2105 = SDBBP_R6
    5918             :   { 2106,       3,      0,      4,      281,    0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr },  // Inst #2106 = SDC1
    5919             :   { 2107,       3,      0,      4,      281,    0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr },  // Inst #2107 = SDC164
    5920             :   { 2108,       3,      0,      4,      281,    0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr },  // Inst #2108 = SDC1_D64_MMR6
    5921             :   { 2109,       3,      0,      4,      281,    0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr },  // Inst #2109 = SDC1_MM
    5922             :   { 2110,       3,      0,      4,      282,    0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #2110 = SDC2
    5923             :   { 2111,       3,      0,      4,      282,    0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr },  // Inst #2111 = SDC2_MMR6
    5924             :   { 2112,       3,      0,      4,      282,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #2112 = SDC2_R6
    5925             :   { 2113,       3,      0,      4,      283,    0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr },  // Inst #2113 = SDC3
    5926             :   { 2114,       2,      0,      4,      75,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList12, OperandInfo31, -1 ,nullptr },  // Inst #2114 = SDIV
    5927             :   { 2115,       2,      0,      4,      75,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList12, OperandInfo31, -1 ,nullptr },  // Inst #2115 = SDIV_MM
    5928             :   { 2116,       3,      1,      4,      75,     0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr },  // Inst #2116 = SDIV_MM_Pseudo
    5929             :   { 2117,       3,      0,      4,      284,    0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #2117 = SDL
    5930             :   { 2118,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #2118 = SDMacro
    5931             :   { 2119,       3,      0,      4,      285,    0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #2119 = SDR
    5932             :   { 2120,       3,      0,      4,      286,    0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr },  // Inst #2120 = SDXC1
    5933             :   { 2121,       3,      0,      4,      286,    0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr },  // Inst #2121 = SDXC164
    5934             :   { 2122,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2122 = SDivIMacro
    5935             :   { 2123,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo317, -1 ,nullptr },  // Inst #2123 = SDivMacro
    5936             :   { 2124,       2,      1,      4,      287,    0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #2124 = SEB
    5937             :   { 2125,       2,      1,      4,      287,    0, 0x1ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr },  // Inst #2125 = SEB64
    5938             :   { 2126,       2,      1,      4,      287,    0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #2126 = SEB_MM
    5939             :   { 2127,       2,      1,      4,      288,    0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #2127 = SEH
    5940             :   { 2128,       2,      1,      4,      288,    0, 0x1ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr },  // Inst #2128 = SEH64
    5941             :   { 2129,       2,      1,      4,      288,    0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #2129 = SEH_MM
    5942             :   { 2130,       3,      1,      4,      289,    0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2130 = SELEQZ
    5943             :   { 2131,       3,      1,      4,      289,    0, 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #2131 = SELEQZ64
    5944             :   { 2132,       3,      1,      4,      290,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #2132 = SELEQZ_D
    5945             :   { 2133,       3,      1,      4,      290,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #2133 = SELEQZ_D_MMR6
    5946             :   { 2134,       3,      1,      4,      289,    0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2134 = SELEQZ_MMR6
    5947             :   { 2135,       3,      1,      4,      291,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #2135 = SELEQZ_S
    5948             :   { 2136,       3,      1,      4,      291,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #2136 = SELEQZ_S_MMR6
    5949             :   { 2137,       3,      1,      4,      289,    0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2137 = SELNEZ
    5950             :   { 2138,       3,      1,      4,      289,    0, 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #2138 = SELNEZ64
    5951             :   { 2139,       3,      1,      4,      290,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #2139 = SELNEZ_D
    5952             :   { 2140,       3,      1,      4,      290,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #2140 = SELNEZ_D_MMR6
    5953             :   { 2141,       3,      1,      4,      289,    0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2141 = SELNEZ_MMR6
    5954             :   { 2142,       3,      1,      4,      291,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #2142 = SELNEZ_S
    5955             :   { 2143,       3,      1,      4,      291,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #2143 = SELNEZ_S_MMR6
    5956             :   { 2144,       4,      1,      4,      292,    0, 0x6ULL, nullptr, nullptr, OperandInfo237, -1 ,nullptr },  // Inst #2144 = SEL_D
    5957             :   { 2145,       4,      1,      4,      292,    0, 0x6ULL, nullptr, nullptr, OperandInfo237, -1 ,nullptr },  // Inst #2145 = SEL_D_MMR6
    5958             :   { 2146,       4,      1,      4,      293,    0, 0x6ULL, nullptr, nullptr, OperandInfo318, -1 ,nullptr },  // Inst #2146 = SEL_S
    5959             :   { 2147,       4,      1,      4,      293,    0, 0x6ULL, nullptr, nullptr, OperandInfo318, -1 ,nullptr },  // Inst #2147 = SEL_S_MMR6
    5960             :   { 2148,       3,      1,      4,      294,    0, 0x1ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #2148 = SEQ
    5961             :   { 2149,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2149 = SEQIMacro
    5962             :   { 2150,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2150 = SEQMacro
    5963             :   { 2151,       3,      1,      4,      295,    0, 0x2ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #2151 = SEQi
    5964             :   { 2152,       3,      0,      4,      296,    0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #2152 = SH
    5965             :   { 2153,       3,      0,      2,      296,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo314, -1 ,nullptr },  // Inst #2153 = SH16_MM
    5966             :   { 2154,       3,      0,      2,      296,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo314, -1 ,nullptr },  // Inst #2154 = SH16_MMR6
    5967             :   { 2155,       3,      0,      4,      296,    0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #2155 = SH64
    5968             :   { 2156,       3,      0,      4,      297,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #2156 = SHE
    5969             :   { 2157,       3,      0,      4,      297,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #2157 = SHE_MM
    5970             :   { 2158,       3,      1,      4,      378,    0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #2158 = SHF_B
    5971             :   { 2159,       3,      1,      4,      378,    0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #2159 = SHF_H
    5972             :   { 2160,       3,      1,      4,      378,    0, 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #2160 = SHF_W
    5973             :   { 2161,       3,      1,      4,      577,    0, 0x6ULL, nullptr, nullptr, OperandInfo319, -1 ,nullptr },  // Inst #2161 = SHILO
    5974             :   { 2162,       3,      1,      4,      576,    0, 0x6ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr },  // Inst #2162 = SHILOV
    5975             :   { 2163,       3,      1,      4,      739,    0, 0x6ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr },  // Inst #2163 = SHILOV_MM
    5976             :   { 2164,       3,      1,      4,      740,    0, 0x6ULL, nullptr, nullptr, OperandInfo319, -1 ,nullptr },  // Inst #2164 = SHILO_MM
    5977             :   { 2165,       3,      1,      4,      578,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo320, -1 ,nullptr },  // Inst #2165 = SHLLV_PH
    5978             :   { 2166,       3,      1,      4,      741,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo320, -1 ,nullptr },  // Inst #2166 = SHLLV_PH_MM
    5979             :   { 2167,       3,      1,      4,      579,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo320, -1 ,nullptr },  // Inst #2167 = SHLLV_QB
    5980             :   { 2168,       3,      1,      4,      742,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo320, -1 ,nullptr },  // Inst #2168 = SHLLV_QB_MM
    5981             :   { 2169,       3,      1,      4,      580,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo320, -1 ,nullptr },  // Inst #2169 = SHLLV_S_PH
    5982             :   { 2170,       3,      1,      4,      743,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo320, -1 ,nullptr },  // Inst #2170 = SHLLV_S_PH_MM
    5983             :   { 2171,       3,      1,      4,      581,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo33, -1 ,nullptr },  // Inst #2171 = SHLLV_S_W
    5984             :   { 2172,       3,      1,      4,      744,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo33, -1 ,nullptr },  // Inst #2172 = SHLLV_S_W_MM
    5985             :   { 2173,       3,      1,      4,      582,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo321, -1 ,nullptr },  // Inst #2173 = SHLL_PH
    5986             :   { 2174,       3,      1,      4,      745,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo321, -1 ,nullptr },  // Inst #2174 = SHLL_PH_MM
    5987             :   { 2175,       3,      1,      4,      583,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo321, -1 ,nullptr },  // Inst #2175 = SHLL_QB
    5988             :   { 2176,       3,      1,      4,      746,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo321, -1 ,nullptr },  // Inst #2176 = SHLL_QB_MM
    5989             :   { 2177,       3,      1,      4,      584,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo321, -1 ,nullptr },  // Inst #2177 = SHLL_S_PH
    5990             :   { 2178,       3,      1,      4,      747,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo321, -1 ,nullptr },  // Inst #2178 = SHLL_S_PH_MM
    5991             :   { 2179,       3,      1,      4,      585,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo38, -1 ,nullptr },  // Inst #2179 = SHLL_S_W
    5992             :   { 2180,       3,      1,      4,      748,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo38, -1 ,nullptr },  // Inst #2180 = SHLL_S_W_MM
    5993             :   { 2181,       3,      1,      4,      586,    0, 0x6ULL, nullptr, nullptr, OperandInfo320, -1 ,nullptr },  // Inst #2181 = SHRAV_PH
    5994             :   { 2182,       3,      1,      4,      749,    0, 0x6ULL, nullptr, nullptr, OperandInfo320, -1 ,nullptr },  // Inst #2182 = SHRAV_PH_MM
    5995             :   { 2183,       3,      1,      4,      634,    0, 0x6ULL, nullptr, nullptr, OperandInfo320, -1 ,nullptr },  // Inst #2183 = SHRAV_QB
    5996             :   { 2184,       3,      1,      4,      797,    0, 0x6ULL, nullptr, nullptr, OperandInfo320, -1 ,nullptr },  // Inst #2184 = SHRAV_QB_MMR2
    5997             :   { 2185,       3,      1,      4,      587,    0, 0x6ULL, nullptr, nullptr, OperandInfo320, -1 ,nullptr },  // Inst #2185 = SHRAV_R_PH
    5998             :   { 2186,       3,      1,      4,      750,    0, 0x6ULL, nullptr, nullptr, OperandInfo320, -1 ,nullptr },  // Inst #2186 = SHRAV_R_PH_MM
    5999             :   { 2187,       3,      1,      4,      635,    0, 0x6ULL, nullptr, nullptr, OperandInfo320, -1 ,nullptr },  // Inst #2187 = SHRAV_R_QB
    6000             :   { 2188,       3,      1,      4,      798,    0, 0x6ULL, nullptr, nullptr, OperandInfo320, -1 ,nullptr },  // Inst #2188 = SHRAV_R_QB_MMR2
    6001             :   { 2189,       3,      1,      4,      588,    0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2189 = SHRAV_R_W
    6002             :   { 2190,       3,      1,      4,      751,    0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2190 = SHRAV_R_W_MM
    6003             :   { 2191,       3,      1,      4,      589,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr },  // Inst #2191 = SHRA_PH
    6004             :   { 2192,       3,      1,      4,      752,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr },  // Inst #2192 = SHRA_PH_MM
    6005             :   { 2193,       3,      1,      4,      632,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr },  // Inst #2193 = SHRA_QB
    6006             :   { 2194,       3,      1,      4,      795,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr },  // Inst #2194 = SHRA_QB_MMR2
    6007             :   { 2195,       3,      1,      4,      590,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr },  // Inst #2195 = SHRA_R_PH
    6008             :   { 2196,       3,      1,      4,      753,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr },  // Inst #2196 = SHRA_R_PH_MM
    6009             :   { 2197,       3,      1,      4,      633,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr },  // Inst #2197 = SHRA_R_QB
    6010             :   { 2198,       3,      1,      4,      796,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr },  // Inst #2198 = SHRA_R_QB_MMR2
    6011             :   { 2199,       3,      1,      4,      591,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2199 = SHRA_R_W
    6012             :   { 2200,       3,      1,      4,      754,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2200 = SHRA_R_W_MM
    6013             :   { 2201,       3,      1,      4,      637,    0, 0x6ULL, nullptr, nullptr, OperandInfo320, -1 ,nullptr },  // Inst #2201 = SHRLV_PH
    6014             :   { 2202,       3,      1,      4,      800,    0, 0x6ULL, nullptr, nullptr, OperandInfo320, -1 ,nullptr },  // Inst #2202 = SHRLV_PH_MMR2
    6015             :   { 2203,       3,      1,      4,      592,    0, 0x6ULL, nullptr, nullptr, OperandInfo320, -1 ,nullptr },  // Inst #2203 = SHRLV_QB
    6016             :   { 2204,       3,      1,      4,      755,    0, 0x6ULL, nullptr, nullptr, OperandInfo320, -1 ,nullptr },  // Inst #2204 = SHRLV_QB_MM
    6017             :   { 2205,       3,      1,      4,      636,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr },  // Inst #2205 = SHRL_PH
    6018             :   { 2206,       3,      1,      4,      799,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr },  // Inst #2206 = SHRL_PH_MMR2
    6019             :   { 2207,       3,      1,      4,      593,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr },  // Inst #2207 = SHRL_QB
    6020             :   { 2208,       3,      1,      4,      756,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr },  // Inst #2208 = SHRL_QB_MM
    6021             :   { 2209,       3,      0,      4,      296,    0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #2209 = SH_MM
    6022             :   { 2210,       3,      0,      4,      296,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #2210 = SH_MMR6
    6023             :   { 2211,       4,      1,      4,      363,    0, 0x6ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr },  // Inst #2211 = SLDI_B
    6024             :   { 2212,       4,      1,      4,      363,    0, 0x6ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr },  // Inst #2212 = SLDI_D
    6025             :   { 2213,       4,      1,      4,      363,    0, 0x6ULL, nullptr, nullptr, OperandInfo76, -1 ,nullptr },  // Inst #2213 = SLDI_H
    6026             :   { 2214,       4,      1,      4,      363,    0, 0x6ULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr },  // Inst #2214 = SLDI_W
    6027             :   { 2215,       4,      1,      4,      363,    0, 0x6ULL, nullptr, nullptr, OperandInfo322, -1 ,nullptr },  // Inst #2215 = SLD_B
    6028             :   { 2216,       4,      1,      4,      363,    0, 0x6ULL, nullptr, nullptr, OperandInfo323, -1 ,nullptr },  // Inst #2216 = SLD_D
    6029             :   { 2217,       4,      1,      4,      363,    0, 0x6ULL, nullptr, nullptr, OperandInfo324, -1 ,nullptr },  // Inst #2217 = SLD_H
    6030             :   { 2218,       4,      1,      4,      363,    0, 0x6ULL, nullptr, nullptr, OperandInfo325, -1 ,nullptr },  // Inst #2218 = SLD_W
    6031             :   { 2219,       3,      1,      4,      298,    0, 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2219 = SLL
    6032             :   { 2220,       3,      1,      2,      298,    0, 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #2220 = SLL16_MM
    6033             :   { 2221,       3,      1,      2,      298,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #2221 = SLL16_MMR6
    6034             :   { 2222,       2,      1,      4,      298,    0, 0x1ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr },  // Inst #2222 = SLL64_32
    6035             :   { 2223,       2,      1,      4,      298,    0, 0x1ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr },  // Inst #2223 = SLL64_64
    6036             :   { 2224,       3,      1,      4,      457,    0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #2224 = SLLI_B
    6037             :   { 2225,       3,      1,      4,      457,    0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #2225 = SLLI_D
    6038             :   { 2226,       3,      1,      4,      457,    0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #2226 = SLLI_H
    6039             :   { 2227,       3,      1,      4,      457,    0, 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #2227 = SLLI_W
    6040             :   { 2228,       3,      1,      4,      299,    0, 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2228 = SLLV
    6041             :   { 2229,       3,      1,      4,      299,    0, 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2229 = SLLV_MM
    6042             :   { 2230,       3,      1,      4,      457,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #2230 = SLL_B
    6043             :   { 2231,       3,      1,      4,      457,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #2231 = SLL_D
    6044             :   { 2232,       3,      1,      4,      457,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #2232 = SLL_H
    6045             :   { 2233,       3,      1,      4,      298,    0, 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2233 = SLL_MM
    6046             :   { 2234,       3,      1,      4,      298,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2234 = SLL_MMR6
    6047             :   { 2235,       3,      1,      4,      457,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #2235 = SLL_W
    6048             :   { 2236,       3,      1,      4,      300,    0, 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2236 = SLT
    6049             :   { 2237,       3,      1,      4,      300,    0, 0x1ULL, nullptr, nullptr, OperandInfo326, -1 ,nullptr },  // Inst #2237 = SLT64
    6050             :   { 2238,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #2238 = SLTImm64
    6051             :   { 2239,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #2239 = SLTUImm64
    6052             :   { 2240,       3,      1,      4,      300,    0, 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2240 = SLT_MM
    6053             :   { 2241,       3,      1,      4,      301,    0, 0x2ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2241 = SLTi
    6054             :   { 2242,       3,      1,      4,      301,    0, 0x2ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr },  // Inst #2242 = SLTi64
    6055             :   { 2243,       3,      1,      4,      301,    0, 0x2ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2243 = SLTi_MM
    6056             :   { 2244,       3,      1,      4,      301,    0, 0x2ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2244 = SLTiu
    6057             :   { 2245,       3,      1,      4,      301,    0, 0x2ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr },  // Inst #2245 = SLTiu64
    6058             :   { 2246,       3,      1,      4,      301,    0, 0x2ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2246 = SLTiu_MM
    6059             :   { 2247,       3,      1,      4,      300,    0, 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2247 = SLTu
    6060             :   { 2248,       3,      1,      4,      300,    0, 0x1ULL, nullptr, nullptr, OperandInfo326, -1 ,nullptr },  // Inst #2248 = SLTu64
    6061             :   { 2249,       3,      1,      4,      300,    0, 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2249 = SLTu_MM
    6062             :   { 2250,       3,      1,      4,      294,    0, 0x1ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #2250 = SNE
    6063             :   { 2251,       3,      1,      4,      295,    0, 0x2ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #2251 = SNEi
    6064             :   { 2252,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo328, -1 ,nullptr },  // Inst #2252 = SNZ_B_PSEUDO
    6065             :   { 2253,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr },  // Inst #2253 = SNZ_D_PSEUDO
    6066             :   { 2254,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr },  // Inst #2254 = SNZ_H_PSEUDO
    6067             :   { 2255,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo328, -1 ,nullptr },  // Inst #2255 = SNZ_V_PSEUDO
    6068             :   { 2256,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr },  // Inst #2256 = SNZ_W_PSEUDO
    6069             :   { 2257,       3,      1,      4,      380,    0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #2257 = SPLATI_B
    6070             :   { 2258,       3,      1,      4,      380,    0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #2258 = SPLATI_D
    6071             :   { 2259,       3,      1,      4,      380,    0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #2259 = SPLATI_H
    6072             :   { 2260,       3,      1,      4,      380,    0, 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #2260 = SPLATI_W
    6073             :   { 2261,       3,      1,      4,      380,    0, 0x6ULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr },  // Inst #2261 = SPLAT_B
    6074             :   { 2262,       3,      1,      4,      380,    0, 0x6ULL, nullptr, nullptr, OperandInfo333, -1 ,nullptr },  // Inst #2262 = SPLAT_D
    6075             :   { 2263,       3,      1,      4,      380,    0, 0x6ULL, nullptr, nullptr, OperandInfo334, -1 ,nullptr },  // Inst #2263 = SPLAT_H
    6076             :   { 2264,       3,      1,      4,      380,    0, 0x6ULL, nullptr, nullptr, OperandInfo335, -1 ,nullptr },  // Inst #2264 = SPLAT_W
    6077             :   { 2265,       3,      1,      4,      302,    0, 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2265 = SRA
    6078             :   { 2266,       3,      1,      4,      453,    0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #2266 = SRAI_B
    6079             :   { 2267,       3,      1,      4,      453,    0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #2267 = SRAI_D
    6080             :   { 2268,       3,      1,      4,      453,    0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #2268 = SRAI_H
    6081             :   { 2269,       3,      1,      4,      453,    0, 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #2269 = SRAI_W
    6082             :   { 2270,       3,      1,      4,      455,    0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #2270 = SRARI_B
    6083             :   { 2271,       3,      1,      4,      455,    0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #2271 = SRARI_D
    6084             :   { 2272,       3,      1,      4,      455,    0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #2272 = SRARI_H
    6085             :   { 2273,       3,      1,      4,      455,    0, 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #2273 = SRARI_W
    6086             :   { 2274,       3,      1,      4,      455,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #2274 = SRAR_B
    6087             :   { 2275,       3,      1,      4,      455,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #2275 = SRAR_D
    6088             :   { 2276,       3,      1,      4,      455,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #2276 = SRAR_H
    6089             :   { 2277,       3,      1,      4,      455,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #2277 = SRAR_W
    6090             :   { 2278,       3,      1,      4,      303,    0, 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2278 = SRAV
    6091             :   { 2279,       3,      1,      4,      303,    0, 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2279 = SRAV_MM
    6092             :   { 2280,       3,      1,      4,      453,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #2280 = SRA_B
    6093             :   { 2281,       3,      1,      4,      453,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #2281 = SRA_D
    6094             :   { 2282,       3,      1,      4,      453,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #2282 = SRA_H
    6095             :   { 2283,       3,      1,      4,      302,    0, 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2283 = SRA_MM
    6096             :   { 2284,       3,      1,      4,      453,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #2284 = SRA_W
    6097             :   { 2285,       3,      1,      4,      304,    0, 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2285 = SRL
    6098             :   { 2286,       3,      1,      2,      304,    0, 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #2286 = SRL16_MM
    6099             :   { 2287,       3,      1,      2,      304,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #2287 = SRL16_MMR6
    6100             :   { 2288,       3,      1,      4,      454,    0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #2288 = SRLI_B
    6101             :   { 2289,       3,      1,      4,      454,    0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #2289 = SRLI_D
    6102             :   { 2290,       3,      1,      4,      454,    0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #2290 = SRLI_H
    6103             :   { 2291,       3,      1,      4,      454,    0, 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #2291 = SRLI_W
    6104             :   { 2292,       3,      1,      4,      456,    0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #2292 = SRLRI_B
    6105             :   { 2293,       3,      1,      4,      456,    0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #2293 = SRLRI_D
    6106             :   { 2294,       3,      1,      4,      456,    0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #2294 = SRLRI_H
    6107             :   { 2295,       3,      1,      4,      456,    0, 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #2295 = SRLRI_W
    6108             :   { 2296,       3,      1,      4,      456,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #2296 = SRLR_B
    6109             :   { 2297,       3,      1,      4,      456,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #2297 = SRLR_D
    6110             :   { 2298,       3,      1,      4,      456,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #2298 = SRLR_H
    6111             :   { 2299,       3,      1,      4,      456,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #2299 = SRLR_W
    6112             :   { 2300,       3,      1,      4,      305,    0, 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2300 = SRLV
    6113             :   { 2301,       3,      1,      4,      305,    0, 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2301 = SRLV_MM
    6114             :   { 2302,       3,      1,      4,      454,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #2302 = SRL_B
    6115             :   { 2303,       3,      1,      4,      454,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #2303 = SRL_D
    6116             :   { 2304,       3,      1,      4,      454,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #2304 = SRL_H
    6117             :   { 2305,       3,      1,      4,      304,    0, 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2305 = SRL_MM
    6118             :   { 2306,       3,      1,      4,      454,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #2306 = SRL_W
    6119             :   { 2307,       0,      0,      4,      306,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2307 = SSNOP
    6120             :   { 2308,       0,      0,      4,      306,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2308 = SSNOP_MM
    6121             :   { 2309,       0,      0,      4,      306,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2309 = SSNOP_MMR6
    6122             :   { 2310,       3,      0,      4,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo214, -1 ,nullptr },  // Inst #2310 = STORE_ACC128
    6123             :   { 2311,       3,      0,      4,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo215, -1 ,nullptr },  // Inst #2311 = STORE_ACC64
    6124             :   { 2312,       3,      0,      4,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr },  // Inst #2312 = STORE_ACC64DSP
    6125             :   { 2313,       3,      0,      4,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr },  // Inst #2313 = STORE_CCOND_DSP
    6126             :   { 2314,       3,      0,      4,      485,    0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr },  // Inst #2314 = ST_B
    6127             :   { 2315,       3,      0,      4,      485,    0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #2315 = ST_D
    6128             :   { 2316,       3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #2316 = ST_F16
    6129             :   { 2317,       3,      0,      4,      485,    0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo212, -1 ,nullptr },  // Inst #2317 = ST_H
    6130             :   { 2318,       3,      0,      4,      485,    0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo213, -1 ,nullptr },  // Inst #2318 = ST_W
    6131             :   { 2319,       3,      1,      4,      307,    0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2319 = SUB
    6132             :   { 2320,       3,      1,      4,      638,    0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #2320 = SUBQH_PH
    6133             :   { 2321,       3,      1,      4,      801,    0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #2321 = SUBQH_PH_MMR2
    6134             :   { 2322,       3,      1,      4,      639,    0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #2322 = SUBQH_R_PH
    6135             :   { 2323,       3,      1,      4,      802,    0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #2323 = SUBQH_R_PH_MMR2
    6136             :   { 2324,       3,      1,      4,      641,    0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2324 = SUBQH_R_W
    6137             :   { 2325,       3,      1,      4,      804,    0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2325 = SUBQH_R_W_MMR2
    6138             :   { 2326,       3,      1,      4,      640,    0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2326 = SUBQH_W
    6139             :   { 2327,       3,      1,      4,      803,    0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2327 = SUBQH_W_MMR2
    6140             :   { 2328,       3,      1,      4,      594,    0, 0x6ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #2328 = SUBQ_PH
    6141             :   { 2329,       3,      1,      4,      757,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #2329 = SUBQ_PH_MM
    6142             :   { 2330,       3,      1,      4,      595,    0, 0x6ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #2330 = SUBQ_S_PH
    6143             :   { 2331,       3,      1,      4,      758,    0, 0x6ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #2331 = SUBQ_S_PH_MM
    6144             :   { 2332,       3,      1,      4,      596,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #2332 = SUBQ_S_W
    6145             :   { 2333,       3,      1,      4,      759,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #2333 = SUBQ_S_W_MM
    6146             :   { 2334,       3,      1,      4,      441,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #2334 = SUBSUS_U_B
    6147             :   { 2335,       3,      1,      4,      441,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #2335 = SUBSUS_U_D
    6148             :   { 2336,       3,      1,      4,      441,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #2336 = SUBSUS_U_H
    6149             :   { 2337,       3,      1,      4,      441,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #2337 = SUBSUS_U_W
    6150             :   { 2338,       3,      1,      4,      442,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #2338 = SUBSUU_S_B
    6151             :   { 2339,       3,      1,      4,      442,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #2339 = SUBSUU_S_D
    6152             :   { 2340,       3,      1,      4,      442,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #2340 = SUBSUU_S_H
    6153             :   { 2341,       3,      1,      4,      442,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #2341 = SUBSUU_S_W
    6154             :   { 2342,       3,      1,      4,      440,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #2342 = SUBS_S_B
    6155             :   { 2343,       3,      1,      4,      440,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #2343 = SUBS_S_D
    6156             :   { 2344,       3,      1,      4,      440,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #2344 = SUBS_S_H
    6157             :   { 2345,       3,      1,      4,      440,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #2345 = SUBS_S_W
    6158             :   { 2346,       3,      1,      4,      440,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #2346 = SUBS_U_B
    6159             :   { 2347,       3,      1,      4,      440,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #2347 = SUBS_U_D
    6160             :   { 2348,       3,      1,      4,      440,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #2348 = SUBS_U_H
    6161             :   { 2349,       3,      1,      4,      440,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #2349 = SUBS_U_W
    6162             :   { 2350,       3,      1,      2,      308,    0, 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #2350 = SUBU16_MM
    6163             :   { 2351,       3,      1,      2,      308,    0, 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #2351 = SUBU16_MMR6
    6164             :   { 2352,       3,      1,      4,      644,    0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #2352 = SUBUH_QB
    6165             :   { 2353,       3,      1,      4,      807,    0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #2353 = SUBUH_QB_MMR2
    6166             :   { 2354,       3,      1,      4,      645,    0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #2354 = SUBUH_R_QB
    6167             :   { 2355,       3,      1,      4,      808,    0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #2355 = SUBUH_R_QB_MMR2
    6168             :   { 2356,       3,      1,      4,      308,    0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2356 = SUBU_MMR6
    6169             :   { 2357,       3,      1,      4,      642,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #2357 = SUBU_PH
    6170             :   { 2358,       3,      1,      4,      805,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #2358 = SUBU_PH_MMR2
    6171             :   { 2359,       3,      1,      4,      597,    0, 0x6ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #2359 = SUBU_QB
    6172             :   { 2360,       3,      1,      4,      760,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #2360 = SUBU_QB_MM
    6173             :   { 2361,       3,      1,      4,      643,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #2361 = SUBU_S_PH
    6174             :   { 2362,       3,      1,      4,      806,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #2362 = SUBU_S_PH_MMR2
    6175             :   { 2363,       3,      1,      4,      598,    0, 0x6ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #2363 = SUBU_S_QB
    6176             :   { 2364,       3,      1,      4,      761,    0, 0x6ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #2364 = SUBU_S_QB_MM
    6177             :   { 2365,       3,      1,      4,      443,    0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #2365 = SUBVI_B
    6178             :   { 2366,       3,      1,      4,      443,    0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #2366 = SUBVI_D
    6179             :   { 2367,       3,      1,      4,      443,    0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #2367 = SUBVI_H
    6180             :   { 2368,       3,      1,      4,      443,    0, 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #2368 = SUBVI_W
    6181             :   { 2369,       3,      1,      4,      444,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #2369 = SUBV_B
    6182             :   { 2370,       3,      1,      4,      444,    0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #2370 = SUBV_D
    6183             :   { 2371,       3,      1,      4,      444,    0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #2371 = SUBV_H
    6184             :   { 2372,       3,      1,      4,      444,    0, 0x6ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #2372 = SUBV_W
    6185             :   { 2373,       3,      1,      4,      307,    0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2373 = SUB_MM
    6186             :   { 2374,       3,      1,      4,      307,    0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2374 = SUB_MMR6
    6187             :   { 2375,       3,      1,      4,      308,    0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2375 = SUBu
    6188             :   { 2376,       3,      1,      4,      308,    0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2376 = SUBu_MM
    6189             :   { 2377,       3,      0,      4,      309,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr },  // Inst #2377 = SUXC1
    6190             :   { 2378,       3,      0,      4,      309,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr },  // Inst #2378 = SUXC164
    6191             :   { 2379,       3,      0,      4,      309,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr },  // Inst #2379 = SUXC1_MM
    6192             :   { 2380,       3,      0,      4,      310,    0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #2380 = SW
    6193             :   { 2381,       3,      0,      2,      310,    0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo314, -1 ,nullptr },  // Inst #2381 = SW16_MM
    6194             :   { 2382,       3,      0,      2,      310,    0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo314, -1 ,nullptr },  // Inst #2382 = SW16_MMR6
    6195             :   { 2383,       3,      0,      4,      310,    0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #2383 = SW64
    6196             :   { 2384,       3,      0,      4,      311,    0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr },  // Inst #2384 = SWC1
    6197             :   { 2385,       3,      0,      4,      311,    0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr },  // Inst #2385 = SWC1_MM
    6198             :   { 2386,       3,      0,      4,      312,    0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #2386 = SWC2
    6199             :   { 2387,       3,      0,      4,      312,    0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr },  // Inst #2387 = SWC2_MMR6
    6200             :   { 2388,       3,      0,      4,      312,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #2388 = SWC2_R6
    6201             :   { 2389,       3,      0,      4,      313,    0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr },  // Inst #2389 = SWC3
    6202             :   { 2390,       3,      0,      4,      310,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr },  // Inst #2390 = SWDSP
    6203             :   { 2391,       3,      0,      4,      310,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr },  // Inst #2391 = SWDSP_MM
    6204             :   { 2392,       3,      0,      4,      314,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #2392 = SWE
    6205             :   { 2393,       3,      0,      4,      314,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #2393 = SWE_MM
    6206             :   { 2394,       3,      0,      4,      315,    0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #2394 = SWL
    6207             :   { 2395,       3,      0,      4,      315,    0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #2395 = SWL64
    6208             :   { 2396,       3,      0,      4,      316,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #2396 = SWLE
    6209             :   { 2397,       3,      0,      4,      316,    0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #2397 = SWLE_MM
    6210             :   { 2398,       3,      0,      4,      315,    0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #2398 = SWL_MM
    6211             :   { 2399,       3,      0,      2,      317,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr },  // Inst #2399 = SWM16_MM
    6212             :   { 2400,       3,      0,      2,      317,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr },  // Inst #2400 = SWM16_MMR6
    6213             :   { 2401,       3,      0,      4,      317,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr },  // Inst #2401 = SWM32_MM
    6214             :   { 2402,       3,      0,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr },  // Inst #2402 = SWM_MM
    6215             :   { 2403,       4,      0,      4,      318,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr },  // Inst #2403 = SWP_MM
    6216             :   { 2404,       4,      0,      4,      318,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr },  // Inst #2404 = SWP_MMR6
    6217             :   { 2405,       3,      0,      4,      319,    0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #2405 = SWR
    6218             :   { 2406,       3,      0,      4,      319,    0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #2406 = SWR64
    6219             :   { 2407,       3,      0,      4,      320,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #2407 = SWRE
    6220             :   { 2408,       3,      0,      4,      320,    0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #2408 = SWRE_MM
    6221             :   { 2409,       3,      0,      4,      319,    0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #2409 = SWR_MM
    6222             :   { 2410,       3,      0,      2,      310,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr },  // Inst #2410 = SWSP_MM
    6223             :   { 2411,       3,      0,      2,      310,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr },  // Inst #2411 = SWSP_MMR6
    6224             :   { 2412,       3,      0,      4,      321,    0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr },  // Inst #2412 = SWXC1
    6225             :   { 2413,       3,      0,      4,      321,    0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr },  // Inst #2413 = SWXC1_MM
    6226             :   { 2414,       3,      0,      4,      310,    0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #2414 = SW_MM
    6227             :   { 2415,       3,      0,      4,      310,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #2415 = SW_MMR6
    6228             :   { 2416,       1,      0,      4,      322,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #2416 = SYNC
    6229             :   { 2417,       2,      0,      4,      323,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo336, -1 ,nullptr },  // Inst #2417 = SYNCI
    6230             :   { 2418,       2,      0,      4,      323,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo336, -1 ,nullptr },  // Inst #2418 = SYNCI_MM
    6231             :   { 2419,       2,      0,      4,      323,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo336, -1 ,nullptr },  // Inst #2419 = SYNCI_MMR6
    6232             :   { 2420,       1,      0,      4,      322,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #2420 = SYNC_MM
    6233             :   { 2421,       1,      0,      4,      322,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #2421 = SYNC_MMR6
    6234             :   { 2422,       1,      0,      4,      324,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #2422 = SYSCALL
    6235             :   { 2423,       1,      0,      4,      324,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #2423 = SYSCALL_MM
    6236             :   { 2424,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo328, -1 ,nullptr },  // Inst #2424 = SZ_B_PSEUDO
    6237             :   { 2425,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr },  // Inst #2425 = SZ_D_PSEUDO
    6238             :   { 2426,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr },  // Inst #2426 = SZ_H_PSEUDO
    6239             :   { 2427,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo328, -1 ,nullptr },  // Inst #2427 = SZ_V_PSEUDO
    6240             :   { 2428,       2,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr },  // Inst #2428 = SZ_W_PSEUDO
    6241             :   { 2429,       0,      0,      2,      325,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList3, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #2429 = Save16
    6242             :   { 2430,       0,      0,      2,      325,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList3, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #2430 = SaveX16
    6243             :   { 2431,       3,      0,      4,      274,    0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr },  // Inst #2431 = SbRxRyOffMemX16
    6244             :   { 2432,       2,      1,      2,      13,     0, 0x0ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr },  // Inst #2432 = SebRx16
    6245             :   { 2433,       2,      1,      2,      13,     0, 0x0ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr },  // Inst #2433 = SehRx16
    6246             :   { 2434,       4,      1,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr },  // Inst #2434 = SelBeqZ
    6247             :   { 2435,       4,      1,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr },  // Inst #2435 = SelBneZ
    6248             :   { 2436,       5,      1,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo339, -1 ,nullptr },  // Inst #2436 = SelTBteqZCmp
    6249             :   { 2437,       5,      1,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo340, -1 ,nullptr },  // Inst #2437 = SelTBteqZCmpi
    6250             :   { 2438,       5,      1,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo339, -1 ,nullptr },  // Inst #2438 = SelTBteqZSlt
    6251             :   { 2439,       5,      1,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo340, -1 ,nullptr },  // Inst #2439 = SelTBteqZSlti
    6252             :   { 2440,       5,      1,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo340, -1 ,nullptr },  // Inst #2440 = SelTBteqZSltiu
    6253             :   { 2441,       5,      1,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo339, -1 ,nullptr },  // Inst #2441 = SelTBteqZSltu
    6254             :   { 2442,       5,      1,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo339, -1 ,nullptr },  // Inst #2442 = SelTBtneZCmp
    6255             :   { 2443,       5,      1,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo340, -1 ,nullptr },  // Inst #2443 = SelTBtneZCmpi
    6256             :   { 2444,       5,      1,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo339, -1 ,nullptr },  // Inst #2444 = SelTBtneZSlt
    6257             :   { 2445,       5,      1,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo340, -1 ,nullptr },  // Inst #2445 = SelTBtneZSlti
    6258             :   { 2446,       5,      1,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo340, -1 ,nullptr },  // Inst #2446 = SelTBtneZSltiu
    6259             :   { 2447,       5,      1,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo339, -1 ,nullptr },  // Inst #2447 = SelTBtneZSltu
    6260             :   { 2448,       3,      0,      4,      296,    0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr },  // Inst #2448 = ShRxRyOffMemX16
    6261             :   { 2449,       3,      1,      4,      13,     0, 0x0ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr },  // Inst #2449 = SllX16
    6262             :   { 2450,       3,      1,      2,      13,     0, 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr },  // Inst #2450 = SllvRxRy16
    6263             :   { 2451,       3,      1,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #2451 = SltCCRxRy16
    6264             :   { 2452,       2,      0,      2,      13,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo122, -1 ,nullptr },  // Inst #2452 = SltRxRy16
    6265             :   { 2453,       3,      1,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr },  // Inst #2453 = SltiCCRxImmX16
    6266             :   { 2454,       2,      0,      2,      13,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo58, -1 ,nullptr },  // Inst #2454 = SltiRxImm16
    6267             :   { 2455,       2,      0,      4,      13,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo58, -1 ,nullptr },  // Inst #2455 = SltiRxImmX16
    6268             :   { 2456,       3,      1,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr },  // Inst #2456 = SltiuCCRxImmX16
    6269             :   { 2457,       2,      0,      2,      13,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo58, -1 ,nullptr },  // Inst #2457 = SltiuRxImm16
    6270             :   { 2458,       2,      0,      4,      13,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo58, -1 ,nullptr },  // Inst #2458 = SltiuRxImmX16
    6271             :   { 2459,       3,      1,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #2459 = SltuCCRxRy16
    6272             :   { 2460,       2,      0,      2,      13,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo122, -1 ,nullptr },  // Inst #2460 = SltuRxRy16
    6273             :   { 2461,       3,      1,      2,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo61, -1 ,nullptr },  // Inst #2461 = SltuRxRyRz16
    6274             :   { 2462,       3,      1,      4,      13,     0, 0x0ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr },  // Inst #2462 = SraX16
    6275             :   { 2463,       3,      1,      2,      13,     0, 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr },  // Inst #2463 = SravRxRy16
    6276             :   { 2464,       3,      1,      4,      13,     0, 0x0ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr },  // Inst #2464 = SrlX16
    6277             :   { 2465,       3,      1,      2,      13,     0, 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr },  // Inst #2465 = SrlvRxRy16
    6278             :   { 2466,       3,      1,      2,      13,     0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #2466 = SubuRxRyRz16
    6279             :   { 2467,       3,      0,      4,      310,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr },  // Inst #2467 = SwRxRyOffMemX16
    6280             :   { 2468,       3,      0,      4,      310,    0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #2468 = SwRxSpImmX16
    6281             :   { 2469,       1,      0,      4,      140,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList4, OperandInfo2, -1 ,nullptr },  // Inst #2469 = TAILCALL
    6282             :   { 2470,       1,      0,      4,      149,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList4, OperandInfo191, -1 ,nullptr },  // Inst #2470 = TAILCALL64R6REG
    6283             :   { 2471,       1,      0,      4,      149,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList4, OperandInfo191, -1 ,nullptr },  // Inst #2471 = TAILCALLHB64R6REG
    6284             :   { 2472,       1,      0,      4,      149,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList4, OperandInfo86, -1 ,nullptr },  // Inst #2472 = TAILCALLHBR6REG
    6285             :   { 2473,       1,      0,      4,      149,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList4, OperandInfo86, -1 ,nullptr },  // Inst #2473 = TAILCALLR6REG
    6286             :   { 2474,       1,      0,      4,      149,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList4, OperandInfo86, -1 ,nullptr },  // Inst #2474 = TAILCALLREG
    6287             :   { 2475,       1,      0,      4,      149,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList4, OperandInfo191, -1 ,nullptr },  // Inst #2475 = TAILCALLREG64
    6288             :   { 2476,       1,      0,      4,      149,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList4, OperandInfo86, -1 ,nullptr },  // Inst #2476 = TAILCALLREGHB
    6289             :   { 2477,       1,      0,      4,      149,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList4, OperandInfo191, -1 ,nullptr },  // Inst #2477 = TAILCALLREGHB64
    6290             :   { 2478,       1,      0,      4,      149,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList4, OperandInfo86, -1 ,nullptr },  // Inst #2478 = TAILCALLREG_MM
    6291             :   { 2479,       1,      0,      4,      149,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList4, OperandInfo86, -1 ,nullptr },  // Inst #2479 = TAILCALLREG_MMR6
    6292             :   { 2480,       1,      0,      4,      140,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList4, OperandInfo2, -1 ,nullptr },  // Inst #2480 = TAILCALL_MM
    6293             :   { 2481,       1,      0,      4,      140,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList4, OperandInfo2, -1 ,nullptr },  // Inst #2481 = TAILCALL_MMR6
    6294             :   { 2482,       3,      0,      4,      326,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2482 = TEQ
    6295             :   { 2483,       2,      0,      4,      327,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #2483 = TEQI
    6296             :   { 2484,       2,      0,      4,      327,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #2484 = TEQI_MM
    6297             :   { 2485,       3,      0,      4,      326,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2485 = TEQ_MM
    6298             :   { 2486,       3,      0,      4,      328,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2486 = TGE
    6299             :   { 2487,       2,      0,      4,      329,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #2487 = TGEI
    6300             :   { 2488,       2,      0,      4,      330,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #2488 = TGEIU
    6301             :   { 2489,       2,      0,      4,      330,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #2489 = TGEIU_MM
    6302             :   { 2490,       2,      0,      4,      329,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #2490 = TGEI_MM
    6303             :   { 2491,       3,      0,      4,      331,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2491 = TGEU
    6304             :   { 2492,       3,      0,      4,      331,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2492 = TGEU_MM
    6305             :   { 2493,       3,      0,      4,      328,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2493 = TGE_MM
    6306             :   { 2494,       0,      0,      4,      332,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2494 = TLBGINV
    6307             :   { 2495,       0,      0,      4,      333,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2495 = TLBGINVF
    6308             :   { 2496,       0,      0,      4,      333,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2496 = TLBGINVF_MM
    6309             :   { 2497,       0,      0,      4,      332,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2497 = TLBGINV_MM
    6310             :   { 2498,       0,      0,      4,      334,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2498 = TLBGP
    6311             :   { 2499,       0,      0,      4,      334,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2499 = TLBGP_MM
    6312             :   { 2500,       0,      0,      4,      335,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2500 = TLBGR
    6313             :   { 2501,       0,      0,      4,      335,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2501 = TLBGR_MM
    6314             :   { 2502,       0,      0,      4,      336,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2502 = TLBGWI
    6315             :   { 2503,       0,      0,      4,      336,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2503 = TLBGWI_MM
    6316             :   { 2504,       0,      0,      4,      337,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2504 = TLBGWR
    6317             :   { 2505,       0,      0,      4,      337,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2505 = TLBGWR_MM
    6318             :   { 2506,       0,      0,      4,      338,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2506 = TLBINV
    6319             :   { 2507,       0,      0,      4,      339,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2507 = TLBINVF
    6320             :   { 2508,       0,      0,      4,      339,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2508 = TLBINVF_MMR6
    6321             :   { 2509,       0,      0,      4,      338,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2509 = TLBINV_MMR6
    6322             :   { 2510,       0,      0,      4,      340,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2510 = TLBP
    6323             :   { 2511,       0,      0,      4,      340,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2511 = TLBP_MM
    6324             :   { 2512,       0,      0,      4,      341,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2512 = TLBR
    6325             :   { 2513,       0,      0,      4,      341,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2513 = TLBR_MM
    6326             :   { 2514,       0,      0,      4,      342,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2514 = TLBWI
    6327             :   { 2515,       0,      0,      4,      342,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2515 = TLBWI_MM
    6328             :   { 2516,       0,      0,      4,      343,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2516 = TLBWR
    6329             :   { 2517,       0,      0,      4,      343,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2517 = TLBWR_MM
    6330             :   { 2518,       3,      0,      4,      344,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2518 = TLT
    6331             :   { 2519,       2,      0,      4,      345,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #2519 = TLTI
    6332             :   { 2520,       2,      0,      4,      346,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #2520 = TLTIU_MM
    6333             :   { 2521,       2,      0,      4,      345,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #2521 = TLTI_MM
    6334             :   { 2522,       3,      0,      4,      347,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2522 = TLTU
    6335             :   { 2523,       3,      0,      4,      347,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2523 = TLTU_MM
    6336             :   { 2524,       3,      0,      4,      344,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2524 = TLT_MM
    6337             :   { 2525,       3,      0,      4,      348,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2525 = TNE
    6338             :   { 2526,       2,      0,      4,      349,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #2526 = TNEI
    6339             :   { 2527,       2,      0,      4,      349,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #2527 = TNEI_MM
    6340             :   { 2528,       3,      0,      4,      348,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2528 = TNE_MM
    6341             :   { 2529,       0,      0,      4,      350,    0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2529 = TRAP
    6342             :   { 2530,       2,      1,      4,      351,    0, 0x4ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #2530 = TRUNC_L_D64
    6343             :   { 2531,       2,      1,      4,      351,    0, 0x4ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #2531 = TRUNC_L_D_MMR6
    6344             :   { 2532,       2,      1,      4,      351,    0, 0x4ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #2532 = TRUNC_L_S
    6345             :   { 2533,       2,      1,      4,      351,    0, 0x4ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #2533 = TRUNC_L_S_MMR6
    6346             :   { 2534,       2,      1,      4,      351,    0, 0x4ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #2534 = TRUNC_W_D32
    6347             :   { 2535,       2,      1,      4,      351,    0, 0x4ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr },  // Inst #2535 = TRUNC_W_D64
    6348             :   { 2536,       2,      1,      4,      351,    0, 0x4ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #2536 = TRUNC_W_D_MMR6
    6349             :   { 2537,       2,      1,      4,      351,    0, 0x4ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #2537 = TRUNC_W_MM
    6350             :   { 2538,       2,      1,      4,      351,    0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #2538 = TRUNC_W_S
    6351             :   { 2539,       2,      1,      4,      351,    0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #2539 = TRUNC_W_S_MM
    6352             :   { 2540,       2,      1,      4,      351,    0, 0x4ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #2540 = TRUNC_W_S_MMR6
    6353             :   { 2541,       2,      0,      4,      346,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #2541 = TTLTIU
    6354             :   { 2542,       2,      0,      4,      76,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList12, OperandInfo31, -1 ,nullptr },  // Inst #2542 = UDIV
    6355             :   { 2543,       2,      0,      4,      76,     0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList12, OperandInfo31, -1 ,nullptr },  // Inst #2543 = UDIV_MM
    6356             :   { 2544,       3,      1,      4,      76,     0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr },  // Inst #2544 = UDIV_MM_Pseudo
    6357             :   { 2545,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2545 = UDivIMacro
    6358             :   { 2546,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2546 = UDivMacro
    6359             :   { 2547,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #2547 = Ulh
    6360             :   { 2548,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #2548 = Ulhu
    6361             :   { 2549,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #2549 = Ulw
    6362             :   { 2550,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #2550 = Ush
    6363             :   { 2551,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #2551 = Usw
    6364             :   { 2552,       3,      1,      4,      91,     0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList33, OperandInfo51, -1 ,nullptr },  // Inst #2552 = V3MULU
    6365             :   { 2553,       3,      1,      4,      91,     0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList25, OperandInfo51, -1 ,nullptr },  // Inst #2553 = VMM0
    6366             :   { 2554,       3,      1,      4,      91,     0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList34, OperandInfo51, -1 ,nullptr },  // Inst #2554 = VMULU
    6367             :   { 2555,       4,      1,      4,      359,    0, 0x6ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr },  // Inst #2555 = VSHF_B
    6368             :   { 2556,       4,      1,      4,      359,    0, 0x6ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #2556 = VSHF_D
    6369             :   { 2557,       4,      1,      4,      359,    0, 0x6ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #2557 = VSHF_H
    6370             :   { 2558,       4,      1,      4,      359,    0, 0x6ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #2558 = VSHF_W
    6371             :   { 2559,       0,      0,      4,      352,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2559 = WAIT
    6372             :   { 2560,       1,      0,      4,      352,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #2560 = WAIT_MM
    6373             :   { 2561,       1,      0,      4,      352,    0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #2561 = WAIT_MMR6
    6374             :   { 2562,       2,      0,      4,      599,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #2562 = WRDSP
    6375             :   { 2563,       2,      0,      4,      762,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #2563 = WRDSP_MM
    6376             :   { 2564,       2,      1,      4,      353,    0, 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #2564 = WRPGPR_MMR6
    6377             :   { 2565,       2,      1,      4,      354,    0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #2565 = WSBH
    6378             :   { 2566,       2,      1,      4,      354,    0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #2566 = WSBH_MM
    6379             :   { 2567,       2,      1,      4,      354,    0, 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #2567 = WSBH_MMR6
    6380             :   { 2568,       3,      1,      4,      355,    0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2568 = XOR
    6381             :   { 2569,       3,      1,      2,      355,    0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #2569 = XOR16_MM
    6382             :   { 2570,       3,      1,      2,      355,    0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #2570 = XOR16_MMR6
    6383             :   { 2571,       3,      1,      4,      355,    0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #2571 = XOR64
    6384             :   { 2572,       3,      1,      4,      384,    0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #2572 = XORI_B
    6385             :   { 2573,       3,      1,      4,      356,    0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2573 = XORI_MMR6
    6386             :   { 2574,       3,      1,      4,      355,    0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2574 = XOR_MM
    6387             :   { 2575,       3,      1,      4,      355,    0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2575 = XOR_MMR6
    6388             :   { 2576,       3,      1,      4,      383,    0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #2576 = XOR_V
    6389             :   { 2577,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #2577 = XOR_V_D_PSEUDO
    6390             :   { 2578,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #2578 = XOR_V_H_PSEUDO
    6391             :   { 2579,       3,      1,      4,      1,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #2579 = XOR_V_W_PSEUDO
    6392             :   { 2580,       3,      1,      4,      356,    0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2580 = XORi
    6393             :   { 2581,       3,      1,      4,      355,    0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #2581 = XORi64
    6394             :   { 2582,       3,      1,      4,      356,    0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2582 = XORi_MM
    6395             :   { 2583,       3,      1,      2,      13,     0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr },  // Inst #2583 = XorRxRxRy16
    6396             :   { 2584,       2,      1,      4,      357,    0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #2584 = YIELD
    6397             : };
    6398             : 
    6399             : extern const char MipsInstrNameData[] = {
    6400             :   /* 0 */ 'D', 'M', 'F', 'C', '0', 0,
    6401             :   /* 6 */ 'D', 'M', 'F', 'G', 'C', '0', 0,
    6402             :   /* 13 */ 'M', 'F', 'H', 'G', 'C', '0', 0,
    6403             :   /* 20 */ 'M', 'T', 'H', 'G', 'C', '0', 0,
    6404             :   /* 27 */ 'D', 'M', 'T', 'G', 'C', '0', 0,
    6405             :   /* 34 */ 'M', 'F', 'T', 'C', '0', 0,
    6406             :   /* 40 */ 'D', 'M', 'T', 'C', '0', 0,
    6407             :   /* 46 */ 'M', 'T', 'T', 'C', '0', 0,
    6408             :   /* 52 */ 'V', 'M', 'M', '0', 0,
    6409             :   /* 57 */ 'M', 'T', 'M', '0', 0,
    6410             :   /* 62 */ 'M', 'T', 'P', '0', 0,
    6411             :   /* 67 */ 'B', 'B', 'I', 'T', '0', 0,
    6412             :   /* 73 */ 'L', 'D', 'C', '1', 0,
    6413             :   /* 78 */ 'S', 'D', 'C', '1', 0,
    6414             :   /* 83 */ 'C', 'F', 'C', '1', 0,
    6415             :   /* 88 */ 'D', 'M', 'F', 'C', '1', 0,
    6416             :   /* 94 */ 'M', 'F', 'T', 'H', 'C', '1', 0,
    6417             :   /* 101 */ 'M', 'T', 'T', 'H', 'C', '1', 0,
    6418             :   /* 108 */ 'C', 'T', 'C', '1', 0,
    6419             :   /* 113 */ 'C', 'F', 'T', 'C', '1', 0,
    6420             :   /* 119 */ 'M', 'F', 'T', 'C', '1', 0,
    6421             :   /* 125 */ 'D', 'M', 'T', 'C', '1', 0,
    6422             :   /* 131 */ 'C', 'T', 'T', 'C', '1', 0,
    6423             :   /* 137 */ 'M', 'T', 'T', 'C', '1', 0,
    6424             :   /* 143 */ 'L', 'W', 'C', '1', 0,
    6425             :   /* 148 */ 'S', 'W', 'C', '1', 0,
    6426             :   /* 153 */ 'L', 'D', 'X', 'C', '1', 0,
    6427             :   /* 159 */ 'S', 'D', 'X', 'C', '1', 0,
    6428             :   /* 165 */ 'L', 'U', 'X', 'C', '1', 0,
    6429             :   /* 171 */ 'S', 'U', 'X', 'C', '1', 0,
    6430             :   /* 177 */ 'L', 'W', 'X', 'C', '1', 0,
    6431             :   /* 183 */ 'S', 'W', 'X', 'C', '1', 0,
    6432             :   /* 189 */ 'M', 'T', 'M', '1', 0,
    6433             :   /* 194 */ 'M', 'T', 'P', '1', 0,
    6434             :   /* 199 */ 'B', 'B', 'I', 'T', '1', 0,
    6435             :   /* 205 */ 'B', 'B', 'I', 'T', '0', '3', '2', 0,
    6436             :   /* 213 */ 'B', 'B', 'I', 'T', '1', '3', '2', 0,
    6437             :   /* 221 */ 'D', 'S', 'R', 'A', '3', '2', 0,
    6438             :   /* 228 */ 'M', 'F', 'H', 'C', '1', '_', 'D', '3', '2', 0,
    6439             :   /* 238 */ 'M', 'T', 'H', 'C', '1', '_', 'D', '3', '2', 0,
    6440             :   /* 248 */ 'F', 'S', 'U', 'B', '_', 'D', '3', '2', 0,
    6441             :   /* 257 */ 'N', 'M', 'S', 'U', 'B', '_', 'D', '3', '2', 0,
    6442             :   /* 267 */ 'F', 'A', 'D', 'D', '_', 'D', '3', '2', 0,
    6443             :   /* 276 */ 'N', 'M', 'A', 'D', 'D', '_', 'D', '3', '2', 0,
    6444             :   /* 286 */ 'C', '_', 'N', 'G', 'E', '_', 'D', '3', '2', 0,
    6445             :   /* 296 */ 'C', '_', 'N', 'G', 'L', 'E', '_', 'D', '3', '2', 0,
    6446             :   /* 307 */ 'C', '_', 'O', 'L', 'E', '_', 'D', '3', '2', 0,
    6447             :   /* 317 */ 'C', '_', 'U', 'L', 'E', '_', 'D', '3', '2', 0,
    6448             :   /* 327 */ 'C', '_', 'L', 'E', '_', 'D', '3', '2', 0,
    6449             :   /* 336 */ 'C', '_', 'S', 'F', '_', 'D', '3', '2', 0,
    6450             :   /* 345 */ 'M', 'O', 'V', 'F', '_', 'D', '3', '2', 0,
    6451             :   /* 354 */ 'C', '_', 'F', '_', 'D', '3', '2', 0,
    6452             :   /* 362 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'F', '_', 'D', '3', '2', 0,
    6453             :   /* 383 */ 'F', 'N', 'E', 'G', '_', 'D', '3', '2', 0,
    6454             :   /* 392 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'D', '3', '2', 0,
    6455             :   /* 403 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'D', '3', '2', 0,
    6456             :   /* 414 */ 'C', '_', 'N', 'G', 'L', '_', 'D', '3', '2', 0,
    6457             :   /* 424 */ 'F', 'M', 'U', 'L', '_', 'D', '3', '2', 0,
    6458             :   /* 433 */ 'C', '_', 'U', 'N', '_', 'D', '3', '2', 0,
    6459             :   /* 442 */ 'R', 'E', 'C', 'I', 'P', '_', 'D', '3', '2', 0,
    6460             :   /* 452 */ 'F', 'C', 'M', 'P', '_', 'D', '3', '2', 0,
    6461             :   /* 461 */ 'C', '_', 'S', 'E', 'Q', '_', 'D', '3', '2', 0,
    6462             :   /* 471 */ 'C', '_', 'U', 'E', 'Q', '_', 'D', '3', '2', 0,
    6463             :   /* 481 */ 'C', '_', 'E', 'Q', '_', 'D', '3', '2', 0,
    6464             :   /* 490 */ 'F', 'A', 'B', 'S', '_', 'D', '3', '2', 0,
    6465             :   /* 499 */ 'C', 'V', 'T', '_', 'S', '_', 'D', '3', '2', 0,
    6466             :   /* 509 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'D', '3', '2', 0,
    6467             :   /* 526 */ 'C', '_', 'N', 'G', 'T', '_', 'D', '3', '2', 0,
    6468             :   /* 536 */ 'C', '_', 'O', 'L', 'T', '_', 'D', '3', '2', 0,
    6469             :   /* 546 */ 'C', '_', 'U', 'L', 'T', '_', 'D', '3', '2', 0,
    6470             :   /* 556 */ 'C', '_', 'L', 'T', '_', 'D', '3', '2', 0,
    6471             :   /* 565 */ 'F', 'S', 'Q', 'R', 'T', '_', 'D', '3', '2', 0,
    6472             :   /* 575 */ 'R', 'S', 'Q', 'R', 'T', '_', 'D', '3', '2', 0,
    6473             :   /* 585 */ 'M', 'O', 'V', 'T', '_', 'D', '3', '2', 0,
    6474             :   /* 594 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'T', '_', 'D', '3', '2', 0,
    6475             :   /* 615 */ 'F', 'D', 'I', 'V', '_', 'D', '3', '2', 0,
    6476             :   /* 624 */ 'F', 'M', 'O', 'V', '_', 'D', '3', '2', 0,
    6477             :   /* 633 */ 'P', 's', 'e', 'u', 'd', 'o', 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'D', '3', '2', 0,
    6478             :   /* 651 */ 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'D', '3', '2', 0,
    6479             :   /* 663 */ 'C', 'E', 'I', 'L', '_', 'W', '_', 'D', '3', '2', 0,
    6480             :   /* 674 */ 'F', 'L', 'O', 'O', 'R', '_', 'W', '_', 'D', '3', '2', 0,
    6481             :   /* 686 */ 'C', 'V', 'T', '_', 'W', '_', 'D', '3', '2', 0,
    6482             :   /* 696 */ 'B', 'P', 'O', 'S', 'G', 'E', '3', '2', 0,
    6483             :   /* 705 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '3', '2', 0,
    6484             :   /* 725 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '3', '2', 0,
    6485             :   /* 745 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '3', '2', 0,
    6486             :   /* 766 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '3', '2', 0,
    6487             :   /* 786 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '3', '2', 0,
    6488             :   /* 802 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '3', '2', 0,
    6489             :   /* 822 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '3', '2', 0,
    6490             :   /* 842 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '3', '2', 0,
    6491             :   /* 861 */ 'D', 'S', 'L', 'L', '3', '2', 0,
    6492             :   /* 868 */ 'D', 'S', 'R', 'L', '3', '2', 0,
    6493             :   /* 875 */ 'D', 'R', 'O', 'T', 'R', '3', '2', 0,
    6494             :   /* 883 */ 'C', 'I', 'N', 'S', '3', '2', 0,
    6495             :   /* 890 */ 'E', 'X', 'T', 'S', '3', '2', 0,
    6496             :   /* 897 */ 'F', 'C', 'M', 'P', '_', 'S', '3', '2', 0,
    6497             :   /* 906 */ 'D', 'S', 'L', 'L', '6', '4', '_', '3', '2', 0,
    6498             :   /* 916 */ 'C', 'I', 'N', 'S', '6', '4', '_', '3', '2', 0,
    6499             :   /* 926 */ 'D', 'E', 'X', 'T', '6', '4', '_', '3', '2', 0,
    6500             :   /* 936 */ 'L', 'o', 'a', 'd', 'I', 'm', 'm', 'D', 'o', 'u', 'b', 'l', 'e', 'F', 'G', 'R', '_', '3', '2', 0,
    6501             :   /* 956 */ 'L', 'o', 'a', 'd', 'A', 'd', 'd', 'r', 'R', 'e', 'g', '3', '2', 0,
    6502             :   /* 970 */ 'C', 'I', 'N', 'S', '_', 'i', '3', '2', 0,
    6503             :   /* 979 */ 'L', 'o', 'a', 'd', 'I', 'm', 'm', '3', '2', 0,
    6504             :   /* 989 */ 'L', 'o', 'a', 'd', 'A', 'd', 'd', 'r', 'I', 'm', 'm', '3', '2', 0,
    6505             :   /* 1003 */ 'M', 'I', 'P', 'S', 'e', 'h', '_', 'r', 'e', 't', 'u', 'r', 'n', '3', '2', 0,
    6506             :   /* 1019 */ 'L', 'w', 'C', 'o', 'n', 's', 't', 'a', 'n', 't', '3', '2', 0,
    6507             :   /* 1032 */ 'L', 'D', 'C', '2', 0,
    6508             :   /* 1037 */ 'S', 'D', 'C', '2', 0,
    6509             :   /* 1042 */ 'D', 'M', 'F', 'C', '2', 0,
    6510             :   /* 1048 */ 'D', 'M', 'T', 'C', '2', 0,
    6511             :   /* 1054 */ 'L', 'W', 'C', '2', 0,
    6512             :   /* 1059 */ 'S', 'W', 'C', '2', 0,
    6513             :   /* 1064 */ 'G', '_', 'F', 'L', 'O', 'G', '2', 0,
    6514             :   /* 1072 */ 'M', 'T', 'M', '2', 0,
    6515             :   /* 1077 */ 'M', 'T', 'P', '2', 0,
    6516             :   /* 1082 */ 'G', '_', 'F', 'E', 'X', 'P', '2', 0,
    6517             :   /* 1090 */ 'S', 'H', 'R', 'A', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
    6518             :   /* 1103 */ 'C', 'M', 'P', 'G', 'D', 'U', '_', 'L', 'E', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
    6519             :   /* 1121 */ 'S', 'U', 'B', 'U', 'H', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
    6520             :   /* 1135 */ 'A', 'D', 'D', 'U', 'H', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
    6521             :   /* 1149 */ 'C', 'M', 'P', 'G', 'D', 'U', '_', 'E', 'Q', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
    6522             :   /* 1167 */ 'S', 'H', 'R', 'A', '_', 'R', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
    6523             :   /* 1182 */ 'S', 'U', 'B', 'U', 'H', '_', 'R', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
    6524             :   /* 1198 */ 'A', 'D', 'D', 'U', 'H', '_', 'R', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
    6525             :   /* 1214 */ 'S', 'H', 'R', 'A', 'V', '_', 'R', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
    6526             :   /* 1230 */ 'A', 'B', 'S', 'Q', '_', 'S', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
    6527             :   /* 1245 */ 'C', 'M', 'P', 'G', 'D', 'U', '_', 'L', 'T', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
    6528             :   /* 1263 */ 'S', 'H', 'R', 'A', 'V', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
    6529             :   /* 1277 */ 'P', 'R', 'E', 'P', 'E', 'N', 'D', '_', 'M', 'M', 'R', '2', 0,
    6530             :   /* 1290 */ 'A', 'P', 'P', 'E', 'N', 'D', '_', 'M', 'M', 'R', '2', 0,
    6531             :   /* 1302 */ 'P', 'R', 'E', 'C', 'R', '_', 'Q', 'B', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
    6532             :   /* 1319 */ 'S', 'U', 'B', 'Q', 'H', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
    6533             :   /* 1333 */ 'A', 'D', 'D', 'Q', 'H', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
    6534             :   /* 1347 */ 'S', 'H', 'R', 'L', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
    6535             :   /* 1360 */ 'M', 'U', 'L', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
    6536             :   /* 1372 */ 'S', 'U', 'B', 'Q', 'H', '_', 'R', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
    6537             :   /* 1388 */ 'A', 'D', 'D', 'Q', 'H', '_', 'R', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
    6538             :   /* 1404 */ 'M', 'U', 'L', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
    6539             :   /* 1418 */ 'M', 'U', 'L', 'Q', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
    6540             :   /* 1433 */ 'S', 'U', 'B', 'U', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
    6541             :   /* 1448 */ 'A', 'D', 'D', 'U', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
    6542             :   /* 1463 */ 'S', 'U', 'B', 'U', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
    6543             :   /* 1476 */ 'A', 'D', 'D', 'U', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
    6544             :   /* 1489 */ 'S', 'H', 'R', 'L', 'V', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
    6545             :   /* 1503 */ 'D', 'P', 'A', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
    6546             :   /* 1517 */ 'M', 'U', 'L', 'S', 'A', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
    6547             :   /* 1533 */ 'D', 'P', 'A', 'Q', 'X', '_', 'S', 'A', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
    6548             :   /* 1552 */ 'D', 'P', 'S', 'Q', 'X', '_', 'S', 'A', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
    6549             :   /* 1571 */ 'D', 'P', 'S', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
    6550             :   /* 1585 */ 'D', 'P', 'A', 'Q', 'X', '_', 'S', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
    6551             :   /* 1603 */ 'D', 'P', 'S', 'Q', 'X', '_', 'S', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
    6552             :   /* 1621 */ 'D', 'P', 'A', 'X', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
    6553             :   /* 1636 */ 'D', 'P', 'S', 'X', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
    6554             :   /* 1651 */ 'B', 'A', 'L', 'I', 'G', 'N', '_', 'M', 'M', 'R', '2', 0,
    6555             :   /* 1663 */ 'P', 'R', 'E', 'C', 'R', '_', 'S', 'R', 'A', '_', 'P', 'H', '_', 'W', '_', 'M', 'M', 'R', '2', 0,
    6556             :   /* 1683 */ 'P', 'R', 'E', 'C', 'R', '_', 'S', 'R', 'A', '_', 'R', '_', 'P', 'H', '_', 'W', '_', 'M', 'M', 'R', '2', 0,
    6557             :   /* 1705 */ 'S', 'U', 'B', 'Q', 'H', '_', 'W', '_', 'M', 'M', 'R', '2', 0,
    6558             :   /* 1718 */ 'A', 'D', 'D', 'Q', 'H', '_', 'W', '_', 'M', 'M', 'R', '2', 0,
    6559             :   /* 1731 */ 'S', 'U', 'B', 'Q', 'H', '_', 'R', '_', 'W', '_', 'M', 'M', 'R', '2', 0,
    6560             :   /* 1746 */ 'A', 'D', 'D', 'Q', 'H', '_', 'R', '_', 'W', '_', 'M', 'M', 'R', '2', 0,
    6561             :   /* 1761 */ 'M', 'U', 'L', 'Q', '_', 'R', 'S', '_', 'W', '_', 'M', 'M', 'R', '2', 0,
    6562             :   /* 1776 */ 'M', 'U', 'L', 'Q', '_', 'S', '_', 'W', '_', 'M', 'M', 'R', '2', 0,
    6563             :   /* 1790 */ 'L', 'D', 'C', '3', 0,
    6564             :   /* 1795 */ 'S', 'D', 'C', '3', 0,
    6565             :   /* 1800 */ 'L', 'W', 'C', '3', 0,
    6566             :   /* 1805 */ 'S', 'W', 'C', '3', 0,
    6567             :   /* 1810 */ 'B', 'P', 'O', 'S', 'G', 'E', '3', '2', 'C', '_', 'M', 'M', 'R', '3', 0,
    6568             :   /* 1825 */ 'L', 'D', 'C', '1', '6', '4', 0,
    6569             :   /* 1832 */ 'S', 'D', 'C', '1', '6', '4', 0,
    6570             :   /* 1839 */ 'L', 'D', 'X', 'C', '1', '6', '4', 0,
    6571             :   /* 1847 */ 'S', 'D', 'X', 'C', '1', '6', '4', 0,
    6572             :   /* 1855 */ 'L', 'U', 'X', 'C', '1', '6', '4', 0,
    6573             :   /* 1863 */ 'S', 'U', 'X', 'C', '1', '6', '4', 0,
    6574             :   /* 1871 */ 'S', 'E', 'B', '6', '4', 0,
    6575             :   /* 1877 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'R', 'E', 'G', 'H', 'B', '6', '4', 0,
    6576             :   /* 1893 */ 'J', 'R', '_', 'H', 'B', '6', '4', 0,
    6577             :   /* 1901 */ 'J', 'A', 'L', 'R', '_', 'H', 'B', '6', '4', 0,
    6578             :   /* 1911 */ 'L', 'B', '6', '4', 0,
    6579             :   /* 1916 */ 'S', 'B', '6', '4', 0,
    6580             :   /* 1921 */ 'L', 'O', 'A', 'D', '_', 'A', 'C', 'C', '6', '4', 0,
    6581             :   /* 1932 */ 'S', 'T', 'O', 'R', 'E', '_', 'A', 'C', 'C', '6', '4', 0,
    6582             :   /* 1944 */ 'B', 'G', 'E', 'C', '6', '4', 0,
    6583             :   /* 1951 */ 'B', 'N', 'E', 'C', '6', '4', 0,
    6584             :   /* 1958 */ 'J', 'I', 'C', '6', '4', 0,
    6585             :   /* 1964 */ 'J', 'I', 'A', 'L', 'C', '6', '4', 0,
    6586             :   /* 1972 */ 'B', 'E', 'Q', 'C', '6', '4', 0,
    6587             :   /* 1979 */ 'S', 'C', '6', '4', 0,
    6588             :   /* 1984 */ 'B', 'L', 'T', 'C', '6', '4', 0,
    6589             :   /* 1991 */ 'B', 'G', 'E', 'U', 'C', '6', '4', 0,
    6590             :   /* 1999 */ 'B', 'L', 'T', 'U', 'C', '6', '4', 0,
    6591             :   /* 2007 */ 'B', 'G', 'E', 'Z', 'C', '6', '4', 0,
    6592             :   /* 2015 */ 'B', 'L', 'E', 'Z', 'C', '6', '4', 0,
    6593             :   /* 2023 */ 'B', 'N', 'E', 'Z', 'C', '6', '4', 0,
    6594             :   /* 2031 */ 'B', 'E', 'Q', 'Z', 'C', '6', '4', 0,
    6595             :   /* 2039 */ 'B', 'G', 'T', 'Z', 'C', '6', '4', 0,
    6596             :   /* 2047 */ 'B', 'L', 'T', 'Z', 'C', '6', '4', 0,
    6597             :   /* 2055 */ 'A', 'N', 'D', '6', '4', 0,
    6598             :   /* 2061 */ 'M', 'F', 'C', '1', '_', 'D', '6', '4', 0,
    6599             :   /* 2070 */ 'M', 'F', 'H', 'C', '1', '_', 'D', '6', '4', 0,
    6600             :   /* 2080 */ 'M', 'T', 'H', 'C', '1', '_', 'D', '6', '4', 0,
    6601             :   /* 2090 */ 'M', 'T', 'C', '1', '_', 'D', '6', '4', 0,
    6602             :   /* 2099 */ 'M', 'O', 'V', 'N', '_', 'I', '6', '4', '_', 'D', '6', '4', 0,
    6603             :   /* 2112 */ 'M', 'O', 'V', 'Z', '_', 'I', '6', '4', '_', 'D', '6', '4', 0,
    6604             :   /* 2125 */ 'F', 'S', 'U', 'B', '_', 'D', '6', '4', 0,
    6605             :   /* 2134 */ 'N', 'M', 'S', 'U', 'B', '_', 'D', '6', '4', 0,
    6606             :   /* 2144 */ 'F', 'A', 'D', 'D', '_', 'D', '6', '4', 0,
    6607             :   /* 2153 */ 'N', 'M', 'A', 'D', 'D', '_', 'D', '6', '4', 0,
    6608             :   /* 2163 */ 'C', '_', 'N', 'G', 'E', '_', 'D', '6', '4', 0,
    6609             :   /* 2173 */ 'C', '_', 'N', 'G', 'L', 'E', '_', 'D', '6', '4', 0,
    6610             :   /* 2184 */ 'C', '_', 'O', 'L', 'E', '_', 'D', '6', '4', 0,
    6611             :   /* 2194 */ 'C', '_', 'U', 'L', 'E', '_', 'D', '6', '4', 0,
    6612             :   /* 2204 */ 'C', '_', 'L', 'E', '_', 'D', '6', '4', 0,
    6613             :   /* 2213 */ 'C', '_', 'S', 'F', '_', 'D', '6', '4', 0,
    6614             :   /* 2222 */ 'M', 'O', 'V', 'F', '_', 'D', '6', '4', 0,
    6615             :   /* 2231 */ 'C', '_', 'F', '_', 'D', '6', '4', 0,
    6616             :   /* 2239 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'F', '_', 'D', '6', '4', 0,
    6617             :   /* 2260 */ 'F', 'N', 'E', 'G', '_', 'D', '6', '4', 0,
    6618             :   /* 2269 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'D', '6', '4', 0,
    6619             :   /* 2280 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'D', '6', '4', 0,
    6620             :   /* 2291 */ 'C', '_', 'N', 'G', 'L', '_', 'D', '6', '4', 0,
    6621             :   /* 2301 */ 'F', 'M', 'U', 'L', '_', 'D', '6', '4', 0,
    6622             :   /* 2310 */ 'T', 'R', 'U', 'N', 'C', '_', 'L', '_', 'D', '6', '4', 0,
    6623             :   /* 2322 */ 'R', 'O', 'U', 'N', 'D', '_', 'L', '_', 'D', '6', '4', 0,
    6624             :   /* 2334 */ 'C', 'E', 'I', 'L', '_', 'L', '_', 'D', '6', '4', 0,
    6625             :   /* 2345 */ 'F', 'L', 'O', 'O', 'R', '_', 'L', '_', 'D', '6', '4', 0,
    6626             :   /* 2357 */ 'C', 'V', 'T', '_', 'L', '_', 'D', '6', '4', 0,
    6627             :   /* 2367 */ 'C', '_', 'U', 'N', '_', 'D', '6', '4', 0,
    6628             :   /* 2376 */ 'R', 'E', 'C', 'I', 'P', '_', 'D', '6', '4', 0,
    6629             :   /* 2386 */ 'F', 'C', 'M', 'P', '_', 'D', '6', '4', 0,
    6630             :   /* 2395 */ 'C', '_', 'S', 'E', 'Q', '_', 'D', '6', '4', 0,
    6631             :   /* 2405 */ 'C', '_', 'U', 'E', 'Q', '_', 'D', '6', '4', 0,
    6632             :   /* 2415 */ 'C', '_', 'E', 'Q', '_', 'D', '6', '4', 0,
    6633             :   /* 2424 */ 'F', 'A', 'B', 'S', '_', 'D', '6', '4', 0,
    6634             :   /* 2433 */ 'C', 'V', 'T', '_', 'S', '_', 'D', '6', '4', 0,
    6635             :   /* 2443 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'D', '6', '4', 0,
    6636             :   /* 2460 */ 'C', '_', 'N', 'G', 'T', '_', 'D', '6', '4', 0,
    6637             :   /* 2470 */ 'C', '_', 'O', 'L', 'T', '_', 'D', '6', '4', 0,
    6638             :   /* 2480 */ 'C', '_', 'U', 'L', 'T', '_', 'D', '6', '4', 0,
    6639             :   /* 2490 */ 'C', '_', 'L', 'T', '_', 'D', '6', '4', 0,
    6640             :   /* 2499 */ 'F', 'S', 'Q', 'R', 'T', '_', 'D', '6', '4', 0,
    6641             :   /* 2509 */ 'R', 'S', 'Q', 'R', 'T', '_', 'D', '6', '4', 0,
    6642             :   /* 2519 */ 'M', 'O', 'V', 'T', '_', 'D', '6', '4', 0,
    6643             :   /* 2528 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'T', '_', 'D', '6', '4', 0,
    6644             :   /* 2549 */ 'F', 'D', 'I', 'V', '_', 'D', '6', '4', 0,
    6645             :   /* 2558 */ 'F', 'M', 'O', 'V', '_', 'D', '6', '4', 0,
    6646             :   /* 2567 */ 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'D', '6', '4', 0,
    6647             :   /* 2579 */ 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'D', '6', '4', 0,
    6648             :   /* 2591 */ 'C', 'E', 'I', 'L', '_', 'W', '_', 'D', '6', '4', 0,
    6649             :   /* 2602 */ 'F', 'L', 'O', 'O', 'R', '_', 'W', '_', 'D', '6', '4', 0,
    6650             :   /* 2614 */ 'C', 'V', 'T', '_', 'W', '_', 'D', '6', '4', 0,
    6651             :   /* 2624 */ 'B', 'N', 'E', '6', '4', 0,
    6652             :   /* 2630 */ 'B', 'u', 'i', 'l', 'd', 'P', 'a', 'i', 'r', 'F', '6', '4', 0,
    6653             :   /* 2643 */ 'E', 'x', 't', 'r', 'a', 'c', 't', 'E', 'l', 'e', 'm', 'e', 'n', 't', 'F', '6', '4', 0,
    6654             :   /* 2661 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'R', 'E', 'G', '6', '4', 0,
    6655             :   /* 2675 */ 'S', 'E', 'H', '6', '4', 0,
    6656             :   /* 2681 */ 'L', 'H', '6', '4', 0,
    6657             :   /* 2686 */ 'S', 'H', '6', '4', 0,
    6658             :   /* 2691 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'F', 'H', 'I', '6', '4', 0,
    6659             :   /* 2704 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'T', 'L', 'O', 'H', 'I', '6', '4', 0,
    6660             :   /* 2719 */ 'M', 'T', 'H', 'I', '6', '4', 0,
    6661             :   /* 2726 */ 'M', 'O', 'V', 'N', '_', 'I', '6', '4', '_', 'I', '6', '4', 0,
    6662             :   /* 2739 */ 'M', 'O', 'V', 'Z', '_', 'I', '6', '4', '_', 'I', '6', '4', 0,
    6663             :   /* 2752 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '6', '4', 0,
    6664             :   /* 2772 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '6', '4', 0,
    6665             :   /* 2792 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '6', '4', 0,
    6666             :   /* 2813 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '6', '4', 0,
    6667             :   /* 2833 */ 'M', 'O', 'V', 'F', '_', 'I', '6', '4', 0,
    6668             :   /* 2842 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'F', '_', 'I', '6', '4', 0,
    6669             :   /* 2863 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'I', '6', '4', 0,
    6670             :   /* 2874 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'I', '6', '4', 0,
    6671             :   /* 2885 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '6', '4', 0,
    6672             :   /* 2901 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '6', '4', 0,
    6673             :   /* 2921 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '6', '4', 0,
    6674             :   /* 2941 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '6', '4', 0,
    6675             :   /* 2960 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'I', '6', '4', 0,
    6676             :   /* 2977 */ 'M', 'O', 'V', 'T', '_', 'I', '6', '4', 0,
    6677             :   /* 2986 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'T', '_', 'I', '6', '4', 0,
    6678             :   /* 3007 */ 'L', 'L', '6', '4', 0,
    6679             :   /* 3012 */ 'L', 'W', 'L', '6', '4', 0,
    6680             :   /* 3018 */ 'S', 'W', 'L', '6', '4', 0,
    6681             :   /* 3024 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'F', 'L', 'O', '6', '4', 0,
    6682             :   /* 3037 */ 'M', 'T', 'L', 'O', '6', '4', 0,
    6683             :   /* 3044 */ 'B', 'E', 'Q', '6', '4', 0,
    6684             :   /* 3050 */ 'J', 'R', '6', '4', 0,
    6685             :   /* 3055 */ 'J', 'A', 'L', 'R', '6', '4', 0,
    6686             :   /* 3062 */ 'N', 'O', 'R', '6', '4', 0,
    6687             :   /* 3068 */ 'X', 'O', 'R', '6', '4', 0,
    6688             :   /* 3074 */ 'R', 'D', 'H', 'W', 'R', '6', '4', 0,
    6689             :   /* 3082 */ 'L', 'W', 'R', '6', '4', 0,
    6690             :   /* 3088 */ 'S', 'W', 'R', '6', '4', 0,
    6691             :   /* 3094 */ 'S', 'L', 'T', '6', '4', 0,
    6692             :   /* 3100 */ 'L', 'W', '6', '4', 0,
    6693             :   /* 3105 */ 'S', 'W', '6', '4', 0,
    6694             :   /* 3110 */ 'B', 'G', 'E', 'Z', '6', '4', 0,
    6695             :   /* 3117 */ 'B', 'L', 'E', 'Z', '6', '4', 0,
    6696             :   /* 3124 */ 'S', 'E', 'L', 'N', 'E', 'Z', '6', '4', 0,
    6697             :   /* 3133 */ 'S', 'E', 'L', 'E', 'Q', 'Z', '6', '4', 0,
    6698             :   /* 3142 */ 'B', 'G', 'T', 'Z', '6', '4', 0,
    6699             :   /* 3149 */ 'B', 'L', 'T', 'Z', '6', '4', 0,
    6700             :   /* 3156 */ 'B', 'u', 'i', 'l', 'd', 'P', 'a', 'i', 'r', 'F', '6', '4', '_', '6', '4', 0,
    6701             :   /* 3172 */ 'E', 'x', 't', 'r', 'a', 'c', 't', 'E', 'l', 'e', 'm', 'e', 'n', 't', 'F', '6', '4', '_', '6', '4', 0,
    6702             :   /* 3193 */ 'S', 'L', 'L', '6', '4', '_', '6', '4', 0,
    6703             :   /* 3202 */ 'L', 'o', 'a', 'd', 'A', 'd', 'd', 'r', 'R', 'e', 'g', '6', '4', 0,
    6704             :   /* 3216 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'H', 'a', 'z', 'a', 'r', 'd', 'B', 'r', 'a', 'n', 'c', 'h', '6', '4', 0,
    6705             :   /* 3245 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'B', 'r', 'a', 'n', 'c', 'h', '6', '4', 0,
    6706             :   /* 3268 */ 'A', 'N', 'D', 'i', '6', '4', 0,
    6707             :   /* 3275 */ 'X', 'O', 'R', 'i', '6', '4', 0,
    6708             :   /* 3282 */ 'S', 'L', 'T', 'i', '6', '4', 0,
    6709             :   /* 3289 */ 'L', 'U', 'i', '6', '4', 0,
    6710             :   /* 3295 */ 'N', 'O', 'R', 'I', 'm', 'm', '6', '4', 0,
    6711             :   /* 3304 */ 'S', 'L', 'T', 'I', 'm', 'm', '6', '4', 0,
    6712             :   /* 3313 */ 'S', 'L', 'T', 'U', 'I', 'm', 'm', '6', '4', 0,
    6713             :   /* 3323 */ 'L', 'o', 'a', 'd', 'I', 'm', 'm', '6', '4', 0,
    6714             :   /* 3333 */ 'L', 'o', 'a', 'd', 'A', 'd', 'd', 'r', 'I', 'm', 'm', '6', '4', 0,
    6715             :   /* 3347 */ 'P', 's', 'e', 'u', 'd', 'o', 'R', 'e', 't', 'u', 'r', 'n', '6', '4', 0,
    6716             :   /* 3362 */ 'M', 'I', 'P', 'S', 'e', 'h', '_', 'r', 'e', 't', 'u', 'r', 'n', '6', '4', 0,
    6717             :   /* 3378 */ 'L', 'B', 'u', '6', '4', 0,
    6718             :   /* 3384 */ 'L', 'H', 'u', '6', '4', 0,
    6719             :   /* 3390 */ 'S', 'L', 'T', 'u', '6', '4', 0,
    6720             :   /* 3397 */ 'L', 'E', 'A', '_', 'A', 'D', 'D', 'i', 'u', '6', '4', 0,
    6721             :   /* 3409 */ 'S', 'L', 'T', 'i', 'u', '6', '4', 0,
    6722             :   /* 3417 */ 'M', 'o', 'v', 'e', 'R', '3', '2', '1', '6', 0,
    6723             :   /* 3427 */ 'R', 'e', 't', 'R', 'A', '1', '6', 0,
    6724             :   /* 3435 */ 'J', 'a', 'l', 'B', '1', '6', 0,
    6725             :   /* 3442 */ 'L', 'D', '_', 'F', '1', '6', 0,
    6726             :   /* 3449 */ 'S', 'T', '_', 'F', '1', '6', 0,
    6727             :   /* 3456 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '1', '6', 0,
    6728             :   /* 3476 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '1', '6', 0,
    6729             :   /* 3496 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '1', '6', 0,
    6730             :   /* 3517 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '1', '6', 0,
    6731             :   /* 3537 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '1', '6', 0,
    6732             :   /* 3553 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '1', '6', 0,
    6733             :   /* 3573 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '1', '6', 0,
    6734             :   /* 3593 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '1', '6', 0,
    6735             :   /* 3612 */ 'M', 'o', 'v', 'e', '3', '2', 'R', '1', '6', 0,
    6736             :   /* 3622 */ 'S', 'r', 'a', 'X', '1', '6', 0,
    6737             :   /* 3629 */ 'R', 'e', 's', 't', 'o', 'r', 'e', 'X', '1', '6', 0,
    6738             :   /* 3640 */ 'S', 'a', 'v', 'e', 'X', '1', '6', 0,
    6739             :   /* 3648 */ 'B', 't', 'n', 'e', 'z', 'T', '8', 'C', 'm', 'p', 'i', 'X', '1', '6', 0,
    6740             :   /* 3663 */ 'B', 't', 'e', 'q', 'z', 'T', '8', 'C', 'm', 'p', 'i', 'X', '1', '6', 0,
    6741             :   /* 3678 */ 'B', 't', 'n', 'e', 'z', 'T', '8', 'S', 'l', 't', 'i', 'X', '1', '6', 0,
    6742             :   /* 3693 */ 'B', 't', 'e', 'q', 'z', 'T', '8', 'S', 'l', 't', 'i', 'X', '1', '6', 0,
    6743             :   /* 3708 */ 'S', 'l', 'l', 'X', '1', '6', 0,
    6744             :   /* 3715 */ 'S', 'r', 'l', 'X', '1', '6', 0,
    6745             :   /* 3722 */ 'L', 'b', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0,
    6746             :   /* 3738 */ 'S', 'b', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0,
    6747             :   /* 3754 */ 'L', 'h', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0,
    6748             :   /* 3770 */ 'S', 'h', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0,
    6749             :   /* 3786 */ 'L', 'b', 'u', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0,
    6750             :   /* 3803 */ 'L', 'h', 'u', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0,
    6751             :   /* 3820 */ 'A', 'd', 'd', 'i', 'u', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0,
    6752             :   /* 3839 */ 'L', 'w', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0,
    6753             :   /* 3855 */ 'S', 'w', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0,
    6754             :   /* 3871 */ 'A', 'd', 'd', 'i', 'u', 'R', 'x', 'P', 'c', 'I', 'm', 'm', 'X', '1', '6', 0,
    6755             :   /* 3887 */ 'A', 'd', 'd', 'i', 'u', 'S', 'p', 'I', 'm', 'm', 'X', '1', '6', 0,
    6756             :   /* 3901 */ 'L', 'w', 'R', 'x', 'S', 'p', 'I', 'm', 'm', 'X', '1', '6', 0,
    6757             :   /* 3914 */ 'S', 'w', 'R', 'x', 'S', 'p', 'I', 'm', 'm', 'X', '1', '6', 0,
    6758             :   /* 3927 */ 'S', 'l', 't', 'i', 'C', 'C', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0,
    6759             :   /* 3942 */ 'S', 'l', 't', 'i', 'u', 'C', 'C', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0,
    6760             :   /* 3958 */ 'L', 'i', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0,
    6761             :   /* 3969 */ 'C', 'm', 'p', 'i', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0,
    6762             :   /* 3982 */ 'S', 'l', 't', 'i', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0,
    6763             :   /* 3995 */ 'A', 'd', 'd', 'i', 'u', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0,
    6764             :   /* 4009 */ 'S', 'l', 't', 'i', 'u', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0,
    6765             :   /* 4023 */ 'A', 'd', 'd', 'i', 'u', 'R', 'x', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0,
    6766             :   /* 4039 */ 'B', 'n', 'e', 'z', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0,
    6767             :   /* 4052 */ 'B', 'e', 'q', 'z', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0,
    6768             :   /* 4065 */ 'B', 'i', 'm', 'm', 'X', '1', '6', 0,
    6769             :   /* 4073 */ 'L', 'i', 'R', 'x', 'I', 'm', 'm', 'A', 'l', 'i', 'g', 'n', 'X', '1', '6', 0,
    6770             :   /* 4089 */ 'L', 'w', 'R', 'x', 'P', 'c', 'T', 'c', 'p', 'X', '1', '6', 0,
    6771             :   /* 4102 */ 'B', 't', 'n', 'e', 'z', 'T', '8', 'C', 'm', 'p', 'X', '1', '6', 0,
    6772             :   /* 4116 */ 'B', 't', 'e', 'q', 'z', 'T', '8', 'C', 'm', 'p', 'X', '1', '6', 0,
    6773             :   /* 4130 */ 'B', 't', 'n', 'e', 'z', 'T', '8', 'S', 'l', 't', 'X', '1', '6', 0,
    6774             :   /* 4144 */ 'B', 't', 'e', 'q', 'z', 'T', '8', 'S', 'l', 't', 'X', '1', '6', 0,
    6775             :   /* 4158 */ 'B', 't', 'n', 'e', 'z', 'T', '8', 'S', 'l', 't', 'i', 'u', 'X', '1', '6', 0,
    6776             :   /* 4174 */ 'B', 't', 'e', 'q', 'z', 'T', '8', 'S', 'l', 't', 'i', 'u', 'X', '1', '6', 0,
    6777             :   /* 4190 */ 'B', 't', 'n', 'e', 'z', 'T', '8', 'S', 'l', 't', 'u', 'X', '1', '6', 0,
    6778             :   /* 4205 */ 'B', 't', 'e', 'q', 'z', 'T', '8', 'S', 'l', 't', 'u', 'X', '1', '6', 0,
    6779             :   /* 4220 */ 'B', 't', 'n', 'e', 'z', 'X', '1', '6', 0,
    6780             :   /* 4229 */ 'B', 't', 'e', 'q', 'z', 'X', '1', '6', 0,
    6781             :   /* 4238 */ 'J', 'r', 'c', 'R', 'a', '1', '6', 0,
    6782             :   /* 4246 */ 'J', 'r', 'R', 'a', '1', '6', 0,
    6783             :   /* 4253 */ 'R', 'e', 's', 't', 'o', 'r', 'e', '1', '6', 0,
    6784             :   /* 4263 */ 'G', 'o', 't', 'P', 'r', 'o', 'l', 'o', 'g', 'u', 'e', '1', '6', 0,
    6785             :   /* 4277 */ 'S', 'a', 'v', 'e', '1', '6', 0,
    6786             :   /* 4284 */ 'J', 'u', 'm', 'p', 'L', 'i', 'n', 'k', 'R', 'e', 'g', '1', '6', 0,
    6787             :   /* 4298 */ 'M', 'f', 'h', 'i', '1', '6', 0,
    6788             :   /* 4305 */ 'B', 'r', 'e', 'a', 'k', '1', '6', 0,
    6789             :   /* 4313 */ 'J', 'a', 'l', '1', '6', 0,
    6790             :   /* 4319 */ 'A', 'd', 'd', 'i', 'u', 'S', 'p', 'I', 'm', 'm', '1', '6', 0,
    6791             :   /* 4332 */ 'L', 'i', 'R', 'x', 'I', 'm', 'm', '1', '6', 0,
    6792             :   /* 4342 */ 'C', 'm', 'p', 'i', 'R', 'x', 'I', 'm', 'm', '1', '6', 0,
    6793             :   /* 4354 */ 'S', 'l', 't', 'i', 'R', 'x', 'I', 'm', 'm', '1', '6', 0,
    6794             :   /* 4366 */ 'S', 'l', 't', 'i', 'u', 'R', 'x', 'I', 'm', 'm', '1', '6', 0,
    6795             :   /* 4379 */ 'A', 'd', 'd', 'i', 'u', 'R', 'x', 'R', 'x', 'I', 'm', 'm', '1', '6', 0,
    6796             :   /* 4394 */ 'B', 'n', 'e', 'z', 'R', 'x', 'I', 'm', 'm', '1', '6', 0,
    6797             :   /* 4406 */ 'B', 'e', 'q', 'z', 'R', 'x', 'I', 'm', 'm', '1', '6', 0,
    6798             :   /* 4418 */ 'B', 'i', 'm', 'm', '1', '6', 0,
    6799             :   /* 4425 */ 'M', 'f', 'l', 'o', '1', '6', 0,
    6800             :   /* 4432 */ 'L', 'w', 'R', 'x', 'P', 'c', 'T', 'c', 'p', '1', '6', 0,
    6801             :   /* 4444 */ 'S', 'e', 'b', 'R', 'x', '1', '6', 0,
    6802             :   /* 4452 */ 'J', 'r', 'c', 'R', 'x', '1', '6', 0,
    6803             :   /* 4460 */ 'S', 'e', 'h', 'R', 'x', '1', '6', 0,
    6804             :   /* 4468 */ 'S', 'l', 't', 'C', 'C', 'R', 'x', 'R', 'y', '1', '6', 0,
    6805             :   /* 4480 */ 'S', 'l', 't', 'u', 'C', 'C', 'R', 'x', 'R', 'y', '1', '6', 0,
    6806             :   /* 4493 */ 'N', 'e', 'g', 'R', 'x', 'R', 'y', '1', '6', 0,
    6807             :   /* 4503 */ 'C', 'm', 'p', 'R', 'x', 'R', 'y', '1', '6', 0,
    6808             :   /* 4513 */ 'S', 'l', 't', 'R', 'x', 'R', 'y', '1', '6', 0,
    6809             :   /* 4523 */ 'M', 'u', 'l', 't', 'R', 'x', 'R', 'y', '1', '6', 0,
    6810             :   /* 4534 */ 'N', 'o', 't', 'R', 'x', 'R', 'y', '1', '6', 0,
    6811             :   /* 4544 */ 'S', 'l', 't', 'u', 'R', 'x', 'R', 'y', '1', '6', 0,
    6812             :   /* 4555 */ 'M', 'u', 'l', 't', 'u', 'R', 'x', 'R', 'y', '1', '6', 0,
    6813             :   /* 4567 */ 'D', 'i', 'v', 'u', 'R', 'x', 'R', 'y', '1', '6', 0,
    6814             :   /* 4578 */ 'S', 'r', 'a', 'v', 'R', 'x', 'R', 'y', '1', '6', 0,
    6815             :   /* 4589 */ 'D', 'i', 'v', 'R', 'x', 'R', 'y', '1', '6', 0,
    6816             :   /* 4599 */ 'S', 'l', 'l', 'v', 'R', 'x', 'R', 'y', '1', '6', 0,
    6817             :   /* 4610 */ 'S', 'r', 'l', 'v', 'R', 'x', 'R', 'y', '1', '6', 0,
    6818             :   /* 4621 */ 'A', 'n', 'd', 'R', 'x', 'R', 'x', 'R', 'y', '1', '6', 0,
    6819             :   /* 4633 */ 'O', 'r', 'R', 'x', 'R', 'x', 'R', 'y', '1', '6', 0,
    6820             :   /* 4644 */ 'X', 'o', 'r', 'R', 'x', 'R', 'x', 'R', 'y', '1', '6', 0,
    6821             :   /* 4656 */ 'M', 'u', 'l', 't', 'R', 'x', 'R', 'y', 'R', 'z', '1', '6', 0,
    6822             :   /* 4669 */ 'S', 'u', 'b', 'u', 'R', 'x', 'R', 'y', 'R', 'z', '1', '6', 0,
    6823             :   /* 4682 */ 'A', 'd', 'd', 'u', 'R', 'x', 'R', 'y', 'R', 'z', '1', '6', 0,
    6824             :   /* 4695 */ 'S', 'l', 't', 'u', 'R', 'x', 'R', 'y', 'R', 'z', '1', '6', 0,
    6825             :   /* 4708 */ 'M', 'u', 'l', 't', 'u', 'R', 'x', 'R', 'y', 'R', 'z', '1', '6', 0,
    6826             :   /* 4722 */ 'B', 't', 'n', 'e', 'z', '1', '6', 0,
    6827             :   /* 4730 */ 'B', 't', 'e', 'q', 'z', '1', '6', 0,
    6828             :   /* 4738 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'r', 'e', 'c', 't', 'H', 'a', 'z', 'a', 'r', 'd', 'B', 'r', 'a', 'n', 'c', 'h', '6', '4', 'R', '6', 0,
    6829             :   /* 4768 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'B', 'r', 'a', 'n', 'c', 'h', '6', '4', 'R', '6', 0,
    6830             :   /* 4793 */ 'M', 'F', 'C', '0', '_', 'M', 'M', 'R', '6', 0,
    6831             :   /* 4803 */ 'M', 'F', 'H', 'C', '0', '_', 'M', 'M', 'R', '6', 0,
    6832             :   /* 4814 */ 'M', 'T', 'H', 'C', '0', '_', 'M', 'M', 'R', '6', 0,
    6833             :   /* 4825 */ 'M', 'T', 'C', '0', '_', 'M', 'M', 'R', '6', 0,
    6834             :   /* 4835 */ 'M', 'F', 'C', '1', '_', 'M', 'M', 'R', '6', 0,
    6835             :   /* 4845 */ 'M', 'T', 'C', '1', '_', 'M', 'M', 'R', '6', 0,
    6836             :   /* 4855 */ 'L', 'D', 'C', '2', '_', 'M', 'M', 'R', '6', 0,
    6837             :   /* 4865 */ 'S', 'D', 'C', '2', '_', 'M', 'M', 'R', '6', 0,
    6838             :   /* 4875 */ 'M', 'F', 'C', '2', '_', 'M', 'M', 'R', '6', 0,
    6839             :   /* 4885 */ 'M', 'F', 'H', 'C', '2', '_', 'M', 'M', 'R', '6', 0,
    6840             :   /* 4896 */ 'M', 'T', 'H', 'C', '2', '_', 'M', 'M', 'R', '6', 0,
    6841             :   /* 4907 */ 'M', 'T', 'C', '2', '_', 'M', 'M', 'R', '6', 0,
    6842             :   /* 4917 */ 'L', 'W', 'C', '2', '_', 'M', 'M', 'R', '6', 0,
    6843             :   /* 4927 */ 'S', 'W', 'C', '2', '_', 'M', 'M', 'R', '6', 0,
    6844             :   /* 4937 */ 'L', 'D', 'C', '1', '_', 'D', '6', '4', '_', 'M', 'M', 'R', '6', 0,
    6845             :   /* 4951 */ 'S', 'D', 'C', '1', '_', 'D', '6', '4', '_', 'M', 'M', 'R', '6', 0,
    6846             :   /* 4965 */ 'S', 'B', '1', '6', '_', 'M', 'M', 'R', '6', 0,
    6847             :   /* 4975 */ 'B', 'C', '1', '6', '_', 'M', 'M', 'R', '6', 0,
    6848             :   /* 4985 */ 'J', 'R', 'C', '1', '6', '_', 'M', 'M', 'R', '6', 0,
    6849             :   /* 4996 */ 'J', 'A', 'L', 'R', 'C', '1', '6', '_', 'M', 'M', 'R', '6', 0,
    6850             :   /* 5009 */ 'B', 'N', 'E', 'Z', 'C', '1', '6', '_', 'M', 'M', 'R', '6', 0,
    6851             :   /* 5022 */ 'B', 'E', 'Q', 'Z', 'C', '1', '6', '_', 'M', 'M', 'R', '6', 0,
    6852             :   /* 5035 */ 'A', 'N', 'D', '1', '6', '_', 'M', 'M', 'R', '6', 0,
    6853             :   /* 5046 */ 'M', 'O', 'V', 'E', '1', '6', '_', 'M', 'M', 'R', '6', 0,
    6854             :   /* 5058 */ 'S', 'H', '1', '6', '_', 'M', 'M', 'R', '6', 0,
    6855             :   /* 5068 */ 'A', 'N', 'D', 'I', '1', '6', '_', 'M', 'M', 'R', '6', 0,
    6856             :   /* 5080 */ 'L', 'I', '1', '6', '_', 'M', 'M', 'R', '6', 0,
    6857             :   /* 5090 */ 'B', 'R', 'E', 'A', 'K', '1', '6', '_', 'M', 'M', 'R', '6', 0,
    6858             :   /* 5103 */ 'S', 'L', 'L', '1', '6', '_', 'M', 'M', 'R', '6', 0,
    6859             :   /* 5114 */ 'S', 'R', 'L', '1', '6', '_', 'M', 'M', 'R', '6', 0,
    6860             :   /* 5125 */ 'L', 'W', 'M', '1', '6', '_', 'M', 'M', 'R', '6', 0,
    6861             :   /* 5136 */ 'S', 'W', 'M', '1', '6', '_', 'M', 'M', 'R', '6', 0,
    6862             :   /* 5147 */ 'S', 'D', 'B', 'B', 'P', '1', '6', '_', 'M', 'M', 'R', '6', 0,
    6863             :   /* 5160 */ 'X', 'O', 'R', '1', '6', '_', 'M', 'M', 'R', '6', 0,
    6864             :   /* 5171 */ 'N', 'O', 'T', '1', '6', '_', 'M', 'M', 'R', '6', 0,
    6865             :   /* 5182 */ 'S', 'U', 'B', 'U', '1', '6', '_', 'M', 'M', 'R', '6', 0,
    6866             :   /* 5194 */ 'A', 'D', 'D', 'U', '1', '6', '_', 'M', 'M', 'R', '6', 0,
    6867             :   /* 5206 */ 'S', 'W', '1', '6', '_', 'M', 'M', 'R', '6', 0,
    6868             :   /* 5216 */ 'L', 'S', 'A', '_', 'M', 'M', 'R', '6', 0,
    6869             :   /* 5225 */ 'E', 'H', 'B', '_', 'M', 'M', 'R', '6', 0,
    6870             :   /* 5234 */ 'J', 'A', 'L', 'R', 'C', '_', 'H', 'B', '_', 'M', 'M', 'R', '6', 0,
    6871             :   /* 5248 */ 'L', 'B', '_', 'M', 'M', 'R', '6', 0,
    6872             :   /* 5256 */ 'S', 'B', '_', 'M', 'M', 'R', '6', 0,
    6873             :   /* 5264 */ 'S', 'U', 'B', '_', 'M', 'M', 'R', '6', 0,
    6874             :   /* 5273 */ 'B', 'C', '_', 'M', 'M', 'R', '6', 0,
    6875             :   /* 5281 */ 'B', 'G', 'E', 'C', '_', 'M', 'M', 'R', '6', 0,
    6876             :   /* 5291 */ 'B', 'N', 'E', 'C', '_', 'M', 'M', 'R', '6', 0,
    6877             :   /* 5301 */ 'J', 'I', 'C', '_', 'M', 'M', 'R', '6', 0,
    6878             :   /* 5310 */ 'B', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0,
    6879             :   /* 5320 */ 'J', 'I', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0,
    6880             :   /* 5331 */ 'B', 'G', 'E', 'Z', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0,
    6881             :   /* 5344 */ 'B', 'L', 'E', 'Z', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0,
    6882             :   /* 5357 */ 'B', 'N', 'E', 'Z', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0,
    6883             :   /* 5370 */ 'B', 'E', 'Q', 'Z', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0,
    6884             :   /* 5383 */ 'B', 'G', 'T', 'Z', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0,
    6885             :   /* 5396 */ 'B', 'L', 'T', 'Z', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0,
    6886             :   /* 5409 */ 'E', 'R', 'E', 'T', 'N', 'C', '_', 'M', 'M', 'R', '6', 0,
    6887             :   /* 5421 */ 'S', 'Y', 'N', 'C', '_', 'M', 'M', 'R', '6', 0,
    6888             :   /* 5431 */ 'A', 'U', 'I', 'P', 'C', '_', 'M', 'M', 'R', '6', 0,
    6889             :   /* 5442 */ 'A', 'L', 'U', 'I', 'P', 'C', '_', 'M', 'M', 'R', '6', 0,
    6890             :   /* 5454 */ 'A', 'D', 'D', 'I', 'U', 'P', 'C', '_', 'M', 'M', 'R', '6', 0,
    6891             :   /* 5467 */ 'L', 'W', 'P', 'C', '_', 'M', 'M', 'R', '6', 0,
    6892             :   /* 5477 */ 'B', 'E', 'Q', 'C', '_', 'M', 'M', 'R', '6', 0,
    6893             :   /* 5487 */ 'J', 'A', 'L', 'R', 'C', '_', 'M', 'M', 'R', '6', 0,
    6894             :   /* 5498 */ 'B', 'L', 'T', 'C', '_', 'M', 'M', 'R', '6', 0,
    6895             :   /* 5508 */ 'B', 'G', 'E', 'U', 'C', '_', 'M', 'M', 'R', '6', 0,
    6896             :   /* 5519 */ 'B', 'L', 'T', 'U', 'C', '_', 'M', 'M', 'R', '6', 0,
    6897             :   /* 5530 */ 'B', 'N', 'V', 'C', '_', 'M', 'M', 'R', '6', 0,
    6898             :   /* 5540 */ 'B', 'O', 'V', 'C', '_', 'M', 'M', 'R', '6', 0,
    6899             :   /* 5550 */ 'B', 'G', 'E', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0,
    6900             :   /* 5561 */ 'B', 'L', 'E', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0,
    6901             :   /* 5572 */ 'B', 'C', '1', 'N', 'E', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0,
    6902             :   /* 5585 */ 'B', 'C', '2', 'N', 'E', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0,
    6903             :   /* 5598 */ 'B', 'N', 'E', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0,
    6904             :   /* 5609 */ 'B', 'C', '1', 'E', 'Q', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0,
    6905             :   /* 5622 */ 'B', 'C', '2', 'E', 'Q', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0,
    6906             :   /* 5635 */ 'B', 'E', 'Q', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0,
    6907             :   /* 5646 */ 'B', 'G', 'T', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0,
    6908             :   /* 5657 */ 'B', 'L', 'T', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0,
    6909             :   /* 5668 */ 'A', 'D', 'D', '_', 'M', 'M', 'R', '6', 0,
    6910             :   /* 5677 */ 'A', 'N', 'D', '_', 'M', 'M', 'R', '6', 0,
    6911             :   /* 5686 */ 'M', 'O', 'D', '_', 'M', 'M', 'R', '6', 0,
    6912             :   /* 5695 */ 'M', 'I', 'N', 'A', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6913             :   /* 5707 */ 'M', 'A', 'X', 'A', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6914             :   /* 5719 */ 'C', 'M', 'P', '_', 'S', 'L', 'E', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6915             :   /* 5734 */ 'C', 'M', 'P', '_', 'S', 'U', 'L', 'E', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6916             :   /* 5750 */ 'C', 'M', 'P', '_', 'U', 'L', 'E', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6917             :   /* 5765 */ 'C', 'M', 'P', '_', 'L', 'E', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6918             :   /* 5779 */ 'C', 'M', 'P', '_', 'S', 'A', 'F', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6919             :   /* 5794 */ 'C', 'M', 'P', '_', 'A', 'F', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6920             :   /* 5808 */ 'M', 'S', 'U', 'B', 'F', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6921             :   /* 5821 */ 'M', 'A', 'D', 'D', 'F', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6922             :   /* 5834 */ 'S', 'E', 'L', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6923             :   /* 5845 */ 'T', 'R', 'U', 'N', 'C', '_', 'L', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6924             :   /* 5860 */ 'R', 'O', 'U', 'N', 'D', '_', 'L', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6925             :   /* 5875 */ 'C', 'E', 'I', 'L', '_', 'L', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6926             :   /* 5889 */ 'F', 'L', 'O', 'O', 'R', '_', 'L', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6927             :   /* 5904 */ 'C', 'V', 'T', '_', 'L', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6928             :   /* 5917 */ 'M', 'I', 'N', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6929             :   /* 5928 */ 'C', 'M', 'P', '_', 'S', 'U', 'N', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6930             :   /* 5943 */ 'C', 'M', 'P', '_', 'U', 'N', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6931             :   /* 5957 */ 'C', 'M', 'P', '_', 'S', 'E', 'Q', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6932             :   /* 5972 */ 'C', 'M', 'P', '_', 'S', 'U', 'E', 'Q', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6933             :   /* 5988 */ 'C', 'M', 'P', '_', 'U', 'E', 'Q', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6934             :   /* 6003 */ 'C', 'M', 'P', '_', 'E', 'Q', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6935             :   /* 6017 */ 'C', 'L', 'A', 'S', 'S', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6936             :   /* 6030 */ 'C', 'M', 'P', '_', 'S', 'L', 'T', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6937             :   /* 6045 */ 'C', 'M', 'P', '_', 'S', 'U', 'L', 'T', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6938             :   /* 6061 */ 'C', 'M', 'P', '_', 'U', 'L', 'T', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6939             :   /* 6076 */ 'C', 'M', 'P', '_', 'L', 'T', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6940             :   /* 6090 */ 'R', 'I', 'N', 'T', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6941             :   /* 6102 */ 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6942             :   /* 6117 */ 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6943             :   /* 6132 */ 'C', 'E', 'I', 'L', '_', 'W', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6944             :   /* 6146 */ 'F', 'L', 'O', 'O', 'R', '_', 'W', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6945             :   /* 6161 */ 'M', 'A', 'X', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6946             :   /* 6172 */ 'S', 'E', 'L', 'N', 'E', 'Z', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6947             :   /* 6186 */ 'S', 'E', 'L', 'E', 'Q', 'Z', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
    6948             :   /* 6200 */ 'C', 'A', 'C', 'H', 'E', '_', 'M', 'M', 'R', '6', 0,
    6949             :   /* 6211 */ 'P', 'A', 'U', 'S', 'E', '_', 'M', 'M', 'R', '6', 0,
    6950             :   /* 6222 */ 'P', 'R', 'E', 'F', '_', 'M', 'M', 'R', '6', 0,
    6951             :   /* 6232 */ 'T', 'L', 'B', 'I', 'N', 'V', 'F', '_', 'M', 'M', 'R', '6', 0,
    6952             :   /* 6245 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'R', 'E', 'G', '_', 'M', 'M', 'R', '6', 0,
    6953             :   /* 6262 */ 'W', 'S', 'B', 'H', '_', 'M', 'M', 'R', '6', 0,
    6954             :   /* 6272 */ 'S', 'H', '_', 'M', 'M', 'R', '6', 0,
    6955             :   /* 6280 */ 'M', 'U', 'H', '_', 'M', 'M', 'R', '6', 0,
    6956             :   /* 6289 */ 'S', 'Y', 'N', 'C', 'I', '_', 'M', 'M', 'R', '6', 0,
    6957             :   /* 6300 */ 'A', 'N', 'D', 'I', '_', 'M', 'M', 'R', '6', 0,
    6958             :   /* 6310 */ 'E', 'I', '_', 'M', 'M', 'R', '6', 0,
    6959             :   /* 6318 */ 'X', 'O', 'R', 'I', '_', 'M', 'M', 'R', '6', 0,
    6960             :   /* 6328 */ 'A', 'U', 'I', '_', 'M', 'M', 'R', '6', 0,
    6961             :   /* 6337 */ 'L', 'U', 'I', '_', 'M', 'M', 'R', '6', 0,
    6962             :   /* 6346 */ 'G', 'I', 'N', 'V', 'I', '_', 'M', 'M', 'R', '6', 0,
    6963             :   /* 6357 */ 'B', 'R', 'E', 'A', 'K', '_', 'M', 'M', 'R', '6', 0,
    6964             :   /* 6368 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', '_', 'M', 'M', 'R', '6', 0,
    6965             :   /* 6382 */ 'S', 'L', 'L', '_', 'M', 'M', 'R', '6', 0,
    6966             :   /* 6391 */ 'M', 'U', 'L', '_', 'M', 'M', 'R', '6', 0,
    6967             :   /* 6400 */ 'C', 'V', 'T', '_', 'D', '_', 'L', '_', 'M', 'M', 'R', '6', 0,
    6968             :   /* 6413 */ 'C', 'V', 'T', '_', 'S', '_', 'L', '_', 'M', 'M', 'R', '6', 0,
    6969             :   /* 6426 */ 'A', 'L', 'I', 'G', 'N', '_', 'M', 'M', 'R', '6', 0,
    6970             :   /* 6437 */ 'C', 'L', 'O', '_', 'M', 'M', 'R', '6', 0,
    6971             :   /* 6446 */ 'B', 'I', 'T', 'S', 'W', 'A', 'P', '_', 'M', 'M', 'R', '6', 0,
    6972             :   /* 6459 */ 'S', 'D', 'B', 'B', 'P', '_', 'M', 'M', 'R', '6', 0,
    6973             :   /* 6470 */ 'M', 'O', 'V', 'E', 'P', '_', 'M', 'M', 'R', '6', 0,
    6974             :   /* 6481 */ 'S', 'S', 'N', 'O', 'P', '_', 'M', 'M', 'R', '6', 0,
    6975             :   /* 6492 */ 'J', 'R', 'C', 'A', 'D', 'D', 'I', 'U', 'S', 'P', '_', 'M', 'M', 'R', '6', 0,
    6976             :   /* 6508 */ 'S', 'W', 'S', 'P', '_', 'M', 'M', 'R', '6', 0,
    6977             :   /* 6518 */ 'D', 'V', 'P', '_', 'M', 'M', 'R', '6', 0,
    6978             :   /* 6527 */ 'E', 'V', 'P', '_', 'M', 'M', 'R', '6', 0,
    6979             :   /* 6536 */ 'L', 'W', 'P', '_', 'M', 'M', 'R', '6', 0,
    6980             :   /* 6545 */ 'S', 'W', 'P', '_', 'M', 'M', 'R', '6', 0,
    6981             :   /* 6554 */ 'N', 'O', 'R', '_', 'M', 'M', 'R', '6', 0,
    6982             :   /* 6563 */ 'X', 'O', 'R', '_', 'M', 'M', 'R', '6', 0,
    6983             :   /* 6572 */ 'R', 'D', 'P', 'G', 'P', 'R', '_', 'M', 'M', 'R', '6', 0,
    6984             :   /* 6584 */ 'W', 'R', 'P', 'G', 'P', 'R', '_', 'M', 'M', 'R', '6', 0,
    6985             :   /* 6596 */ 'R', 'D', 'H', 'W', 'R', '_', 'M', 'M', 'R', '6', 0,
    6986             :   /* 6607 */ 'I', 'N', 'S', '_', 'M', 'M', 'R', '6', 0,
    6987             :   /* 6616 */ 'M', 'I', 'N', 'A', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    6988             :   /* 6628 */ 'M', 'A', 'X', 'A', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    6989             :   /* 6640 */ 'F', 'S', 'U', 'B', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    6990             :   /* 6652 */ 'F', 'A', 'D', 'D', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    6991             :   /* 6664 */ 'C', 'M', 'P', '_', 'S', 'L', 'E', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    6992             :   /* 6679 */ 'C', 'M', 'P', '_', 'S', 'U', 'L', 'E', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    6993             :   /* 6695 */ 'C', 'M', 'P', '_', 'U', 'L', 'E', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    6994             :   /* 6710 */ 'C', 'M', 'P', '_', 'L', 'E', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    6995             :   /* 6724 */ 'C', 'M', 'P', '_', 'S', 'A', 'F', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    6996             :   /* 6739 */ 'C', 'M', 'P', '_', 'A', 'F', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    6997             :   /* 6753 */ 'M', 'S', 'U', 'B', 'F', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    6998             :   /* 6766 */ 'M', 'A', 'D', 'D', 'F', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    6999             :   /* 6779 */ 'F', 'N', 'E', 'G', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7000             :   /* 6791 */ 'S', 'E', 'L', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7001             :   /* 6802 */ 'F', 'M', 'U', 'L', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7002             :   /* 6814 */ 'T', 'R', 'U', 'N', 'C', '_', 'L', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7003             :   /* 6829 */ 'R', 'O', 'U', 'N', 'D', '_', 'L', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7004             :   /* 6844 */ 'C', 'E', 'I', 'L', '_', 'L', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7005             :   /* 6858 */ 'F', 'L', 'O', 'O', 'R', '_', 'L', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7006             :   /* 6873 */ 'C', 'V', 'T', '_', 'L', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7007             :   /* 6886 */ 'M', 'I', 'N', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7008             :   /* 6897 */ 'C', 'M', 'P', '_', 'S', 'U', 'N', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7009             :   /* 6912 */ 'C', 'M', 'P', '_', 'U', 'N', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7010             :   /* 6926 */ 'C', 'M', 'P', '_', 'S', 'E', 'Q', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7011             :   /* 6941 */ 'C', 'M', 'P', '_', 'S', 'U', 'E', 'Q', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7012             :   /* 6957 */ 'C', 'M', 'P', '_', 'U', 'E', 'Q', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7013             :   /* 6972 */ 'C', 'M', 'P', '_', 'E', 'Q', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7014             :   /* 6986 */ 'C', 'L', 'A', 'S', 'S', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7015             :   /* 6999 */ 'C', 'M', 'P', '_', 'S', 'L', 'T', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7016             :   /* 7014 */ 'C', 'M', 'P', '_', 'S', 'U', 'L', 'T', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7017             :   /* 7030 */ 'C', 'M', 'P', '_', 'U', 'L', 'T', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7018             :   /* 7045 */ 'C', 'M', 'P', '_', 'L', 'T', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7019             :   /* 7059 */ 'R', 'I', 'N', 'T', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7020             :   /* 7071 */ 'F', 'D', 'I', 'V', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7021             :   /* 7083 */ 'F', 'M', 'O', 'V', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7022             :   /* 7095 */ 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7023             :   /* 7110 */ 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7024             :   /* 7125 */ 'C', 'E', 'I', 'L', '_', 'W', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7025             :   /* 7139 */ 'F', 'L', 'O', 'O', 'R', '_', 'W', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7026             :   /* 7154 */ 'C', 'V', 'T', '_', 'W', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7027             :   /* 7167 */ 'M', 'A', 'X', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7028             :   /* 7178 */ 'S', 'E', 'L', 'N', 'E', 'Z', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7029             :   /* 7192 */ 'S', 'E', 'L', 'E', 'Q', 'Z', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
    7030             :   /* 7206 */ 'D', 'E', 'R', 'E', 'T', '_', 'M', 'M', 'R', '6', 0,
    7031             :   /* 7217 */ 'W', 'A', 'I', 'T', '_', 'M', 'M', 'R', '6', 0,
    7032             :   /* 7227 */ 'G', 'I', 'N', 'V', 'T', '_', 'M', 'M', 'R', '6', 0,
    7033             :   /* 7238 */ 'E', 'X', 'T', '_', 'M', 'M', 'R', '6', 0,
    7034             :   /* 7247 */ 'L', 'B', 'U', '_', 'M', 'M', 'R', '6', 0,
    7035             :   /* 7256 */ 'S', 'U', 'B', 'U', '_', 'M', 'M', 'R', '6', 0,
    7036             :   /* 7266 */ 'A', 'D', 'D', 'U', '_', 'M', 'M', 'R', '6', 0,
    7037             :   /* 7276 */ 'M', 'O', 'D', 'U', '_', 'M', 'M', 'R', '6', 0,
    7038             :   /* 7286 */ 'M', 'U', 'H', 'U', '_', 'M', 'M', 'R', '6', 0,
    7039             :   /* 7296 */ 'A', 'D', 'D', 'I', 'U', '_', 'M', 'M', 'R', '6', 0,
    7040             :   /* 7307 */ 'M', 'U', 'L', 'U', '_', 'M', 'M', 'R', '6', 0,
    7041             :   /* 7317 */ 'D', 'I', 'V', 'U', '_', 'M', 'M', 'R', '6', 0,
    7042             :   /* 7327 */ 'D', 'I', 'V', '_', 'M', 'M', 'R', '6', 0,
    7043             :   /* 7336 */ 'T', 'L', 'B', 'I', 'N', 'V', '_', 'M', 'M', 'R', '6', 0,
    7044             :   /* 7348 */ 'L', 'W', '_', 'M', 'M', 'R', '6', 0,
    7045             :   /* 7356 */ 'S', 'W', '_', 'M', 'M', 'R', '6', 0,
    7046             :   /* 7364 */ 'C', 'V', 'T', '_', 'S', '_', 'W', '_', 'M', 'M', 'R', '6', 0,
    7047             :   /* 7377 */ 'S', 'E', 'L', 'N', 'E', 'Z', '_', 'M', 'M', 'R', '6', 0,
    7048             :   /* 7389 */ 'C', 'L', 'Z', '_', 'M', 'M', 'R', '6', 0,
    7049             :   /* 7398 */ 'S', 'E', 'L', 'E', 'Q', 'Z', '_', 'M', 'M', 'R', '6', 0,
    7050             :   /* 7410 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'B', 'r', 'a', 'n', 'c', 'h', '_', 'M', 'M', 'R', '6', 0,
    7051             :   /* 7436 */ 'L', 'D', 'C', '2', '_', 'R', '6', 0,
    7052             :   /* 7444 */ 'S', 'D', 'C', '2', '_', 'R', '6', 0,
    7053             :   /* 7452 */ 'L', 'W', 'C', '2', '_', 'R', '6', 0,
    7054             :   /* 7460 */ 'S', 'W', 'C', '2', '_', 'R', '6', 0,
    7055             :   /* 7468 */ 'J', 'R', '_', 'H', 'B', '6', '4', '_', 'R', '6', 0,
    7056             :   /* 7479 */ 'S', 'C', '6', '4', '_', 'R', '6', 0,
    7057             :   /* 7487 */ 'L', 'L', '6', '4', '_', 'R', '6', 0,
    7058             :   /* 7495 */ 'D', 'L', 'S', 'A', '_', 'R', '6', 0,
    7059             :   /* 7503 */ 'J', 'R', '_', 'H', 'B', '_', 'R', '6', 0,
    7060             :   /* 7512 */ 'S', 'C', '_', 'R', '6', 0,
    7061             :   /* 7518 */ 'S', 'C', 'D', '_', 'R', '6', 0,
    7062             :   /* 7525 */ 'L', 'L', 'D', '_', 'R', '6', 0,
    7063             :   /* 7532 */ 'C', 'A', 'C', 'H', 'E', '_', 'R', '6', 0,
    7064             :   /* 7541 */ 'P', 'R', 'E', 'F', '_', 'R', '6', 0,
    7065             :   /* 7549 */ 'L', 'L', '_', 'R', '6', 0,
    7066             :   /* 7555 */ 'D', 'M', 'U', 'L', '_', 'R', '6', 0,
    7067             :   /* 7563 */ 'D', 'C', 'L', 'O', '_', 'R', '6', 0,
    7068             :   /* 7571 */ 'S', 'D', 'B', 'B', 'P', '_', 'R', '6', 0,
    7069             :   /* 7580 */ 'D', 'C', 'L', 'Z', '_', 'R', '6', 0,
    7070             :   /* 7588 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'r', 'e', 'c', 't', 'H', 'a', 'z', 'a', 'r', 'd', 'B', 'r', 'a', 'n', 'c', 'h', 'R', '6', 0,
    7071             :   /* 7616 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'B', 'r', 'a', 'n', 'c', 'h', 'R', '6', 0,
    7072             :   /* 7639 */ 'L', 'O', 'A', 'D', '_', 'A', 'C', 'C', '1', '2', '8', 0,
    7073             :   /* 7651 */ 'S', 'T', 'O', 'R', 'E', '_', 'A', 'C', 'C', '1', '2', '8', 0,
    7074             :   /* 7664 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '8', 0,
    7075             :   /* 7683 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '8', 0,
    7076             :   /* 7702 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '8', 0,
    7077             :   /* 7722 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '8', 0,
    7078             :   /* 7741 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '8', 0,
    7079             :   /* 7756 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '8', 0,
    7080             :   /* 7775 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '8', 0,
    7081             :   /* 7794 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '8', 0,
    7082             :   /* 7812 */ 'P', 'R', 'E', 'C', 'E', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'L', 'A', 0,
    7083             :   /* 7827 */ 'P', 'R', 'E', 'C', 'E', 'Q', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'L', 'A', 0,
    7084             :   /* 7843 */ 'G', '_', 'F', 'M', 'A', 0,
    7085             :   /* 7849 */ 'P', 'R', 'E', 'C', 'E', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'R', 'A', 0,
    7086             :   /* 7864 */ 'P', 'R', 'E', 'C', 'E', 'Q', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'R', 'A', 0,
    7087             :   /* 7880 */ 'D', 'S', 'R', 'A', 0,
    7088             :   /* 7885 */ 'R', 'e', 't', 'R', 'A', 0,
    7089             :   /* 7891 */ 'D', 'L', 'S', 'A', 0,
    7090             :   /* 7896 */ 'C', 'F', 'C', 'M', 'S', 'A', 0,
    7091             :   /* 7903 */ 'C', 'T', 'C', 'M', 'S', 'A', 0,
    7092             :   /* 7910 */ 'C', 'R', 'C', '3', '2', 'B', 0,
    7093             :   /* 7917 */ 'C', 'R', 'C', '3', '2', 'C', 'B', 0,
    7094             :   /* 7925 */ 'S', 'E', 'B', 0,
    7095             :   /* 7929 */ 'E', 'H', 'B', 0,
    7096             :   /* 7933 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'R', 'E', 'G', 'H', 'B', 0,
    7097             :   /* 7947 */ 'J', 'R', '_', 'H', 'B', 0,
    7098             :   /* 7953 */ 'J', 'A', 'L', 'R', '_', 'H', 'B', 0,
    7099             :   /* 7961 */ 'L', 'B', 0,
    7100             :   /* 7964 */ 'S', 'H', 'R', 'A', '_', 'Q', 'B', 0,
    7101             :   /* 7972 */ 'C', 'M', 'P', 'G', 'D', 'U', '_', 'L', 'E', '_', 'Q', 'B', 0,
    7102             :   /* 7985 */ 'C', 'M', 'P', 'G', 'U', '_', 'L', 'E', '_', 'Q', 'B', 0,
    7103             :   /* 7997 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'M', 'P', 'U', '_', 'L', 'E', '_', 'Q', 'B', 0,
    7104             :   /* 8014 */ 'S', 'U', 'B', 'U', 'H', '_', 'Q', 'B', 0,
    7105             :   /* 8023 */ 'A', 'D', 'D', 'U', 'H', '_', 'Q', 'B', 0,
    7106             :   /* 8032 */ 'P', 's', 'e', 'u', 'd', 'o', 'P', 'I', 'C', 'K', '_', 'Q', 'B', 0,
    7107             :   /* 8046 */ 'S', 'H', 'L', 'L', '_', 'Q', 'B', 0,
    7108             :   /* 8054 */ 'R', 'E', 'P', 'L', '_', 'Q', 'B', 0,
    7109             :   /* 8062 */ 'S', 'H', 'R', 'L', '_', 'Q', 'B', 0,
    7110             :   /* 8070 */ 'C', 'M', 'P', 'G', 'D', 'U', '_', 'E', 'Q', '_', 'Q', 'B', 0,
    7111             :   /* 8083 */ 'C', 'M', 'P', 'G', 'U', '_', 'E', 'Q', '_', 'Q', 'B', 0,
    7112             :   /* 8095 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'M', 'P', 'U', '_', 'E', 'Q', '_', 'Q', 'B', 0,
    7113             :   /* 8112 */ 'S', 'H', 'R', 'A', '_', 'R', '_', 'Q', 'B', 0,
    7114             :   /* 8122 */ 'S', 'U', 'B', 'U', 'H', '_', 'R', '_', 'Q', 'B', 0,
    7115             :   /* 8133 */ 'A', 'D', 'D', 'U', 'H', '_', 'R', '_', 'Q', 'B', 0,
    7116             :   /* 8144 */ 'S', 'H', 'R', 'A', 'V', '_', 'R', '_', 'Q', 'B', 0,
    7117             :   /* 8155 */ 'A', 'B', 'S', 'Q', '_', 'S', '_', 'Q', 'B', 0,
    7118             :   /* 8165 */ 'S', 'U', 'B', 'U', '_', 'S', '_', 'Q', 'B', 0,
    7119             :   /* 8175 */ 'A', 'D', 'D', 'U', '_', 'S', '_', 'Q', 'B', 0,
    7120             :   /* 8185 */ 'C', 'M', 'P', 'G', 'D', 'U', '_', 'L', 'T', '_', 'Q', 'B', 0,
    7121             :   /* 8198 */ 'C', 'M', 'P', 'G', 'U', '_', 'L', 'T', '_', 'Q', 'B', 0,
    7122             :   /* 8210 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'M', 'P', 'U', '_', 'L', 'T', '_', 'Q', 'B', 0,
    7123 <