LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/NVPTX - NVPTXGenInstrInfo.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 6 6 100.0 %
Date: 2017-09-14 15:23:50 Functions: 1 3 33.3 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Target Instruction Enum Values and Descriptors                             *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : #ifdef GET_INSTRINFO_ENUM
      10             : #undef GET_INSTRINFO_ENUM
      11             : namespace llvm {
      12             : 
      13             : namespace NVPTX {
      14             :   enum {
      15             :     PHI = 0,
      16             :     INLINEASM   = 1,
      17             :     CFI_INSTRUCTION     = 2,
      18             :     EH_LABEL    = 3,
      19             :     GC_LABEL    = 4,
      20             :     ANNOTATION_LABEL    = 5,
      21             :     KILL        = 6,
      22             :     EXTRACT_SUBREG      = 7,
      23             :     INSERT_SUBREG       = 8,
      24             :     IMPLICIT_DEF        = 9,
      25             :     SUBREG_TO_REG       = 10,
      26             :     COPY_TO_REGCLASS    = 11,
      27             :     DBG_VALUE   = 12,
      28             :     REG_SEQUENCE        = 13,
      29             :     COPY        = 14,
      30             :     BUNDLE      = 15,
      31             :     LIFETIME_START      = 16,
      32             :     LIFETIME_END        = 17,
      33             :     STACKMAP    = 18,
      34             :     FENTRY_CALL = 19,
      35             :     PATCHPOINT  = 20,
      36             :     LOAD_STACK_GUARD    = 21,
      37             :     STATEPOINT  = 22,
      38             :     LOCAL_ESCAPE        = 23,
      39             :     FAULTING_OP = 24,
      40             :     PATCHABLE_OP        = 25,
      41             :     PATCHABLE_FUNCTION_ENTER    = 26,
      42             :     PATCHABLE_RET       = 27,
      43             :     PATCHABLE_FUNCTION_EXIT     = 28,
      44             :     PATCHABLE_TAIL_CALL = 29,
      45             :     PATCHABLE_EVENT_CALL        = 30,
      46             :     G_ADD       = 31,
      47             :     G_SUB       = 32,
      48             :     G_MUL       = 33,
      49             :     G_SDIV      = 34,
      50             :     G_UDIV      = 35,
      51             :     G_SREM      = 36,
      52             :     G_UREM      = 37,
      53             :     G_AND       = 38,
      54             :     G_OR        = 39,
      55             :     G_XOR       = 40,
      56             :     G_IMPLICIT_DEF      = 41,
      57             :     G_PHI       = 42,
      58             :     G_FRAME_INDEX       = 43,
      59             :     G_GLOBAL_VALUE      = 44,
      60             :     G_EXTRACT   = 45,
      61             :     G_UNMERGE_VALUES    = 46,
      62             :     G_INSERT    = 47,
      63             :     G_MERGE_VALUES      = 48,
      64             :     G_PTRTOINT  = 49,
      65             :     G_INTTOPTR  = 50,
      66             :     G_BITCAST   = 51,
      67             :     G_LOAD      = 52,
      68             :     G_STORE     = 53,
      69             :     G_BRCOND    = 54,
      70             :     G_BRINDIRECT        = 55,
      71             :     G_INTRINSIC = 56,
      72             :     G_INTRINSIC_W_SIDE_EFFECTS  = 57,
      73             :     G_ANYEXT    = 58,
      74             :     G_TRUNC     = 59,
      75             :     G_CONSTANT  = 60,
      76             :     G_FCONSTANT = 61,
      77             :     G_VASTART   = 62,
      78             :     G_VAARG     = 63,
      79             :     G_SEXT      = 64,
      80             :     G_ZEXT      = 65,
      81             :     G_SHL       = 66,
      82             :     G_LSHR      = 67,
      83             :     G_ASHR      = 68,
      84             :     G_ICMP      = 69,
      85             :     G_FCMP      = 70,
      86             :     G_SELECT    = 71,
      87             :     G_UADDE     = 72,
      88             :     G_USUBE     = 73,
      89             :     G_SADDO     = 74,
      90             :     G_SSUBO     = 75,
      91             :     G_UMULO     = 76,
      92             :     G_SMULO     = 77,
      93             :     G_UMULH     = 78,
      94             :     G_SMULH     = 79,
      95             :     G_FADD      = 80,
      96             :     G_FSUB      = 81,
      97             :     G_FMUL      = 82,
      98             :     G_FMA       = 83,
      99             :     G_FDIV      = 84,
     100             :     G_FREM      = 85,
     101             :     G_FPOW      = 86,
     102             :     G_FEXP      = 87,
     103             :     G_FEXP2     = 88,
     104             :     G_FLOG      = 89,
     105             :     G_FLOG2     = 90,
     106             :     G_FNEG      = 91,
     107             :     G_FPEXT     = 92,
     108             :     G_FPTRUNC   = 93,
     109             :     G_FPTOSI    = 94,
     110             :     G_FPTOUI    = 95,
     111             :     G_SITOFP    = 96,
     112             :     G_UITOFP    = 97,
     113             :     G_GEP       = 98,
     114             :     G_PTR_MASK  = 99,
     115             :     G_BR        = 100,
     116             :     G_INSERT_VECTOR_ELT = 101,
     117             :     G_EXTRACT_VECTOR_ELT        = 102,
     118             :     G_SHUFFLE_VECTOR    = 103,
     119             :     ABS_16anonymous_636 = 104,
     120             :     ABS_32anonymous_636 = 105,
     121             :     ABS_64anonymous_636 = 106,
     122             :     ADDCCCi32ri = 107,
     123             :     ADDCCCi32rr = 108,
     124             :     ADDCCi32ri  = 109,
     125             :     ADDCCi32rr  = 110,
     126             :     ADD_i1_ri   = 111,
     127             :     ADD_i1_rr   = 112,
     128             :     ADDi16ri    = 113,
     129             :     ADDi16rr    = 114,
     130             :     ADDi32ri    = 115,
     131             :     ADDi32rr    = 116,
     132             :     ADDi64ri    = 117,
     133             :     ADDi64rr    = 118,
     134             :     ANDb16ri    = 119,
     135             :     ANDb16rr    = 120,
     136             :     ANDb1ri     = 121,
     137             :     ANDb1rr     = 122,
     138             :     ANDb32ri    = 123,
     139             :     ANDb32rr    = 124,
     140             :     ANDb64ri    = 125,
     141             :     ANDb64rr    = 126,
     142             :     BFE_S32rii  = 127,
     143             :     BFE_S32rri  = 128,
     144             :     BFE_S32rrr  = 129,
     145             :     BFE_S64rii  = 130,
     146             :     BFE_S64rri  = 131,
     147             :     BFE_S64rrr  = 132,
     148             :     BFE_U32rii  = 133,
     149             :     BFE_U32rri  = 134,
     150             :     BFE_U32rrr  = 135,
     151             :     BFE_U64rii  = 136,
     152             :     BFE_U64rri  = 137,
     153             :     BFE_U64rrr  = 138,
     154             :     BITCONVERT_16_F2I   = 139,
     155             :     BITCONVERT_16_I2F   = 140,
     156             :     BITCONVERT_32_F16x22I       = 141,
     157             :     BITCONVERT_32_F2I   = 142,
     158             :     BITCONVERT_32_I2F   = 143,
     159             :     BITCONVERT_32_I2F16x2       = 144,
     160             :     BITCONVERT_64_F2I   = 145,
     161             :     BITCONVERT_64_I2F   = 146,
     162             :     BREV32      = 147,
     163             :     BREV64      = 148,
     164             :     BuildF16x2  = 149,
     165             :     BuildF16x2i = 150,
     166             :     CALL        = 151,
     167             :     CALL_PROTOTYPE      = 152,
     168             :     CBranch     = 153,
     169             :     CBranchOther        = 154,
     170             :     CLZr32      = 155,
     171             :     CLZr64      = 156,
     172             :     COSF        = 157,
     173             :     CVT_INREG_s16_s8    = 158,
     174             :     CVT_INREG_s32_s16   = 159,
     175             :     CVT_INREG_s32_s8    = 160,
     176             :     CVT_INREG_s64_s16   = 161,
     177             :     CVT_INREG_s64_s32   = 162,
     178             :     CVT_INREG_s64_s8    = 163,
     179             :     CVT_f16_f16 = 164,
     180             :     CVT_f16_f32 = 165,
     181             :     CVT_f16_f64 = 166,
     182             :     CVT_f16_s16 = 167,
     183             :     CVT_f16_s32 = 168,
     184             :     CVT_f16_s64 = 169,
     185             :     CVT_f16_s8  = 170,
     186             :     CVT_f16_u16 = 171,
     187             :     CVT_f16_u32 = 172,
     188             :     CVT_f16_u64 = 173,
     189             :     CVT_f16_u8  = 174,
     190             :     CVT_f32_f16 = 175,
     191             :     CVT_f32_f32 = 176,
     192             :     CVT_f32_f64 = 177,
     193             :     CVT_f32_s16 = 178,
     194             :     CVT_f32_s32 = 179,
     195             :     CVT_f32_s64 = 180,
     196             :     CVT_f32_s8  = 181,
     197             :     CVT_f32_u16 = 182,
     198             :     CVT_f32_u32 = 183,
     199             :     CVT_f32_u64 = 184,
     200             :     CVT_f32_u8  = 185,
     201             :     CVT_f64_f16 = 186,
     202             :     CVT_f64_f32 = 187,
     203             :     CVT_f64_f64 = 188,
     204             :     CVT_f64_s16 = 189,
     205             :     CVT_f64_s32 = 190,
     206             :     CVT_f64_s64 = 191,
     207             :     CVT_f64_s8  = 192,
     208             :     CVT_f64_u16 = 193,
     209             :     CVT_f64_u32 = 194,
     210             :     CVT_f64_u64 = 195,
     211             :     CVT_f64_u8  = 196,
     212             :     CVT_s16_f16 = 197,
     213             :     CVT_s16_f32 = 198,
     214             :     CVT_s16_f64 = 199,
     215             :     CVT_s16_s16 = 200,
     216             :     CVT_s16_s32 = 201,
     217             :     CVT_s16_s64 = 202,
     218             :     CVT_s16_s8  = 203,
     219             :     CVT_s16_u16 = 204,
     220             :     CVT_s16_u32 = 205,
     221             :     CVT_s16_u64 = 206,
     222             :     CVT_s16_u8  = 207,
     223             :     CVT_s32_f16 = 208,
     224             :     CVT_s32_f32 = 209,
     225             :     CVT_s32_f64 = 210,
     226             :     CVT_s32_s16 = 211,
     227             :     CVT_s32_s32 = 212,
     228             :     CVT_s32_s64 = 213,
     229             :     CVT_s32_s8  = 214,
     230             :     CVT_s32_u16 = 215,
     231             :     CVT_s32_u32 = 216,
     232             :     CVT_s32_u64 = 217,
     233             :     CVT_s32_u8  = 218,
     234             :     CVT_s64_f16 = 219,
     235             :     CVT_s64_f32 = 220,
     236             :     CVT_s64_f64 = 221,
     237             :     CVT_s64_s16 = 222,
     238             :     CVT_s64_s32 = 223,
     239             :     CVT_s64_s64 = 224,
     240             :     CVT_s64_s8  = 225,
     241             :     CVT_s64_u16 = 226,
     242             :     CVT_s64_u32 = 227,
     243             :     CVT_s64_u64 = 228,
     244             :     CVT_s64_u8  = 229,
     245             :     CVT_s8_f16  = 230,
     246             :     CVT_s8_f32  = 231,
     247             :     CVT_s8_f64  = 232,
     248             :     CVT_s8_s16  = 233,
     249             :     CVT_s8_s32  = 234,
     250             :     CVT_s8_s64  = 235,
     251             :     CVT_s8_s8   = 236,
     252             :     CVT_s8_u16  = 237,
     253             :     CVT_s8_u32  = 238,
     254             :     CVT_s8_u64  = 239,
     255             :     CVT_s8_u8   = 240,
     256             :     CVT_u16_f16 = 241,
     257             :     CVT_u16_f32 = 242,
     258             :     CVT_u16_f64 = 243,
     259             :     CVT_u16_s16 = 244,
     260             :     CVT_u16_s32 = 245,
     261             :     CVT_u16_s64 = 246,
     262             :     CVT_u16_s8  = 247,
     263             :     CVT_u16_u16 = 248,
     264             :     CVT_u16_u32 = 249,
     265             :     CVT_u16_u64 = 250,
     266             :     CVT_u16_u8  = 251,
     267             :     CVT_u32_f16 = 252,
     268             :     CVT_u32_f32 = 253,
     269             :     CVT_u32_f64 = 254,
     270             :     CVT_u32_s16 = 255,
     271             :     CVT_u32_s32 = 256,
     272             :     CVT_u32_s64 = 257,
     273             :     CVT_u32_s8  = 258,
     274             :     CVT_u32_u16 = 259,
     275             :     CVT_u32_u32 = 260,
     276             :     CVT_u32_u64 = 261,
     277             :     CVT_u32_u8  = 262,
     278             :     CVT_u64_f16 = 263,
     279             :     CVT_u64_f32 = 264,
     280             :     CVT_u64_f64 = 265,
     281             :     CVT_u64_s16 = 266,
     282             :     CVT_u64_s32 = 267,
     283             :     CVT_u64_s64 = 268,
     284             :     CVT_u64_s8  = 269,
     285             :     CVT_u64_u16 = 270,
     286             :     CVT_u64_u32 = 271,
     287             :     CVT_u64_u64 = 272,
     288             :     CVT_u64_u8  = 273,
     289             :     CVT_u8_f16  = 274,
     290             :     CVT_u8_f32  = 275,
     291             :     CVT_u8_f64  = 276,
     292             :     CVT_u8_s16  = 277,
     293             :     CVT_u8_s32  = 278,
     294             :     CVT_u8_s64  = 279,
     295             :     CVT_u8_s8   = 280,
     296             :     CVT_u8_u16  = 281,
     297             :     CVT_u8_u32  = 282,
     298             :     CVT_u8_u64  = 283,
     299             :     CVT_u8_u8   = 284,
     300             :     CallArgBeginInst    = 285,
     301             :     CallArgEndInst0     = 286,
     302             :     CallArgEndInst1     = 287,
     303             :     CallArgF32  = 288,
     304             :     CallArgF64  = 289,
     305             :     CallArgI16  = 290,
     306             :     CallArgI32  = 291,
     307             :     CallArgI32imm       = 292,
     308             :     CallArgI64  = 293,
     309             :     CallArgParam        = 294,
     310             :     CallPrintCallNoRetInst      = 295,
     311             :     CallPrintCallRetInst1       = 296,
     312             :     CallPrintCallRetInst2       = 297,
     313             :     CallPrintCallRetInst3       = 298,
     314             :     CallPrintCallRetInst4       = 299,
     315             :     CallPrintCallRetInst5       = 300,
     316             :     CallPrintCallRetInst6       = 301,
     317             :     CallPrintCallRetInst7       = 302,
     318             :     CallPrintCallRetInst8       = 303,
     319             :     CallUniPrintCallNoRetInst   = 304,
     320             :     CallUniPrintCallRetInst1    = 305,
     321             :     CallUniPrintCallRetInst2    = 306,
     322             :     CallUniPrintCallRetInst3    = 307,
     323             :     CallUniPrintCallRetInst4    = 308,
     324             :     CallUniPrintCallRetInst5    = 309,
     325             :     CallUniPrintCallRetInst6    = 310,
     326             :     CallUniPrintCallRetInst7    = 311,
     327             :     CallUniPrintCallRetInst8    = 312,
     328             :     CallVoidInst        = 313,
     329             :     CallVoidInstReg     = 314,
     330             :     CallVoidInstReg64   = 315,
     331             :     Callseq_End = 316,
     332             :     Callseq_Start       = 317,
     333             :     ConvergentCallPrintCallNoRetInst    = 318,
     334             :     ConvergentCallPrintCallRetInst1     = 319,
     335             :     ConvergentCallPrintCallRetInst2     = 320,
     336             :     ConvergentCallPrintCallRetInst3     = 321,
     337             :     ConvergentCallPrintCallRetInst4     = 322,
     338             :     ConvergentCallPrintCallRetInst5     = 323,
     339             :     ConvergentCallPrintCallRetInst6     = 324,
     340             :     ConvergentCallPrintCallRetInst7     = 325,
     341             :     ConvergentCallPrintCallRetInst8     = 326,
     342             :     ConvergentCallUniPrintCallNoRetInst = 327,
     343             :     ConvergentCallUniPrintCallRetInst1  = 328,
     344             :     ConvergentCallUniPrintCallRetInst2  = 329,
     345             :     ConvergentCallUniPrintCallRetInst3  = 330,
     346             :     ConvergentCallUniPrintCallRetInst4  = 331,
     347             :     ConvergentCallUniPrintCallRetInst5  = 332,
     348             :     ConvergentCallUniPrintCallRetInst6  = 333,
     349             :     ConvergentCallUniPrintCallRetInst7  = 334,
     350             :     ConvergentCallUniPrintCallRetInst8  = 335,
     351             :     DeclareParamInst    = 336,
     352             :     DeclareRetMemInst   = 337,
     353             :     DeclareRetRegInst   = 338,
     354             :     DeclareRetScalarInst        = 339,
     355             :     DeclareScalarParamInst      = 340,
     356             :     DeclareScalarRegInst        = 341,
     357             :     F16x2toF16_0        = 342,
     358             :     F16x2toF16_1        = 343,
     359             :     F64toV2F32  = 344,
     360             :     FABSf32     = 345,
     361             :     FABSf32_ftz = 346,
     362             :     FABSf64     = 347,
     363             :     FADD_rnf16rr        = 348,
     364             :     FADD_rnf16rr_ftz    = 349,
     365             :     FADD_rnf16x2rr      = 350,
     366             :     FADD_rnf16x2rr_ftz  = 351,
     367             :     FADD_rnf32ri        = 352,
     368             :     FADD_rnf32ri_ftz    = 353,
     369             :     FADD_rnf32rr        = 354,
     370             :     FADD_rnf32rr_ftz    = 355,
     371             :     FADD_rnf64ri        = 356,
     372             :     FADD_rnf64rr        = 357,
     373             :     FADDf16rr   = 358,
     374             :     FADDf16rr_ftz       = 359,
     375             :     FADDf16x2rr = 360,
     376             :     FADDf16x2rr_ftz     = 361,
     377             :     FADDf32ri   = 362,
     378             :     FADDf32ri_ftz       = 363,
     379             :     FADDf32rr   = 364,
     380             :     FADDf32rr_ftz       = 365,
     381             :     FADDf64ri   = 366,
     382             :     FADDf64rr   = 367,
     383             :     FDIV321r    = 368,
     384             :     FDIV321r_approx     = 369,
     385             :     FDIV321r_approx_ftz = 370,
     386             :     FDIV321r_ftz        = 371,
     387             :     FDIV321r_prec       = 372,
     388             :     FDIV321r_prec_ftz   = 373,
     389             :     FDIV32approxri      = 374,
     390             :     FDIV32approxri_ftz  = 375,
     391             :     FDIV32approxrr      = 376,
     392             :     FDIV32approxrr_ftz  = 377,
     393             :     FDIV32ri    = 378,
     394             :     FDIV32ri_ftz        = 379,
     395             :     FDIV32ri_prec       = 380,
     396             :     FDIV32ri_prec_ftz   = 381,
     397             :     FDIV32rr    = 382,
     398             :     FDIV32rr_ftz        = 383,
     399             :     FDIV32rr_prec       = 384,
     400             :     FDIV32rr_prec_ftz   = 385,
     401             :     FDIV641r    = 386,
     402             :     FDIV64ri    = 387,
     403             :     FDIV64rr    = 388,
     404             :     FMA16_ftzrrr        = 389,
     405             :     FMA16rrr    = 390,
     406             :     FMA16x2_ftzrrr      = 391,
     407             :     FMA16x2rrr  = 392,
     408             :     FMA32_ftzrii        = 393,
     409             :     FMA32_ftzrir        = 394,
     410             :     FMA32_ftzrri        = 395,
     411             :     FMA32_ftzrrr        = 396,
     412             :     FMA32rii    = 397,
     413             :     FMA32rir    = 398,
     414             :     FMA32rri    = 399,
     415             :     FMA32rrr    = 400,
     416             :     FMA64rii    = 401,
     417             :     FMA64rir    = 402,
     418             :     FMA64rri    = 403,
     419             :     FMA64rrr    = 404,
     420             :     FMAXf32ri   = 405,
     421             :     FMAXf32ri_ftz       = 406,
     422             :     FMAXf32rr   = 407,
     423             :     FMAXf32rr_ftz       = 408,
     424             :     FMAXf64ri   = 409,
     425             :     FMAXf64rr   = 410,
     426             :     FMINf32ri   = 411,
     427             :     FMINf32ri_ftz       = 412,
     428             :     FMINf32rr   = 413,
     429             :     FMINf32rr_ftz       = 414,
     430             :     FMINf64ri   = 415,
     431             :     FMINf64rr   = 416,
     432             :     FMOV16rr    = 417,
     433             :     FMOV32ri    = 418,
     434             :     FMOV32rr    = 419,
     435             :     FMOV64ri    = 420,
     436             :     FMOV64rr    = 421,
     437             :     FMUL_rnf16rr        = 422,
     438             :     FMUL_rnf16rr_ftz    = 423,
     439             :     FMUL_rnf16x2rr      = 424,
     440             :     FMUL_rnf16x2rr_ftz  = 425,
     441             :     FMUL_rnf32ri        = 426,
     442             :     FMUL_rnf32ri_ftz    = 427,
     443             :     FMUL_rnf32rr        = 428,
     444             :     FMUL_rnf32rr_ftz    = 429,
     445             :     FMUL_rnf64ri        = 430,
     446             :     FMUL_rnf64rr        = 431,
     447             :     FMULf16rr   = 432,
     448             :     FMULf16rr_ftz       = 433,
     449             :     FMULf16x2rr = 434,
     450             :     FMULf16x2rr_ftz     = 435,
     451             :     FMULf32ri   = 436,
     452             :     FMULf32ri_ftz       = 437,
     453             :     FMULf32rr   = 438,
     454             :     FMULf32rr_ftz       = 439,
     455             :     FMULf64ri   = 440,
     456             :     FMULf64rr   = 441,
     457             :     FNEGf32     = 442,
     458             :     FNEGf32_ftz = 443,
     459             :     FNEGf64     = 444,
     460             :     FSQRTf32    = 445,
     461             :     FSQRTf32_ftz        = 446,
     462             :     FSQRTf64    = 447,
     463             :     FSUB_rnf16rr        = 448,
     464             :     FSUB_rnf16rr_ftz    = 449,
     465             :     FSUB_rnf16x2rr      = 450,
     466             :     FSUB_rnf16x2rr_ftz  = 451,
     467             :     FSUB_rnf32ri        = 452,
     468             :     FSUB_rnf32ri_ftz    = 453,
     469             :     FSUB_rnf32rr        = 454,
     470             :     FSUB_rnf32rr_ftz    = 455,
     471             :     FSUB_rnf64ri        = 456,
     472             :     FSUB_rnf64rr        = 457,
     473             :     FSUBf16rr   = 458,
     474             :     FSUBf16rr_ftz       = 459,
     475             :     FSUBf16x2rr = 460,
     476             :     FSUBf16x2rr_ftz     = 461,
     477             :     FSUBf32ri   = 462,
     478             :     FSUBf32ri_ftz       = 463,
     479             :     FSUBf32rr   = 464,
     480             :     FSUBf32rr_ftz       = 465,
     481             :     FSUBf64ri   = 466,
     482             :     FSUBf64rr   = 467,
     483             :     FUNSHFLCLAMP        = 468,
     484             :     FUNSHFRCLAMP        = 469,
     485             :     GET_HI_INT64        = 470,
     486             :     GET_LO_INT64        = 471,
     487             :     GOTO        = 472,
     488             :     I32toV2I16  = 473,
     489             :     I64toV2I32  = 474,
     490             :     I64toV4I16  = 475,
     491             :     IMOV16ri    = 476,
     492             :     IMOV16rr    = 477,
     493             :     IMOV1ri     = 478,
     494             :     IMOV1rr     = 479,
     495             :     IMOV32ri    = 480,
     496             :     IMOV32rr    = 481,
     497             :     IMOV64i     = 482,
     498             :     IMOV64rr    = 483,
     499             :     INEG16      = 484,
     500             :     INEG32      = 485,
     501             :     INEG64      = 486,
     502             :     INT_BARRIER = 487,
     503             :     INT_BARRIER0        = 488,
     504             :     INT_BARRIER0_AND    = 489,
     505             :     INT_BARRIER0_OR     = 490,
     506             :     INT_BARRIER0_POPC   = 491,
     507             :     INT_BARRIERN        = 492,
     508             :     INT_BAR_SYNC        = 493,
     509             :     INT_MEMBAR_CTA      = 494,
     510             :     INT_MEMBAR_GL       = 495,
     511             :     INT_MEMBAR_SYS      = 496,
     512             :     INT_NVVM_ADD_RM_D   = 497,
     513             :     INT_NVVM_ADD_RM_F   = 498,
     514             :     INT_NVVM_ADD_RM_FTZ_F       = 499,
     515             :     INT_NVVM_ADD_RN_D   = 500,
     516             :     INT_NVVM_ADD_RN_F   = 501,
     517             :     INT_NVVM_ADD_RN_FTZ_F       = 502,
     518             :     INT_NVVM_ADD_RP_D   = 503,
     519             :     INT_NVVM_ADD_RP_F   = 504,
     520             :     INT_NVVM_ADD_RP_FTZ_F       = 505,
     521             :     INT_NVVM_ADD_RZ_D   = 506,
     522             :     INT_NVVM_ADD_RZ_F   = 507,
     523             :     INT_NVVM_ADD_RZ_FTZ_F       = 508,
     524             :     INT_NVVM_BITCAST_D2LL       = 509,
     525             :     INT_NVVM_BITCAST_F2I        = 510,
     526             :     INT_NVVM_BITCAST_I2F        = 511,
     527             :     INT_NVVM_BITCAST_LL2D       = 512,
     528             :     INT_NVVM_COMPILER_ERROR_32  = 513,
     529             :     INT_NVVM_COMPILER_ERROR_64  = 514,
     530             :     INT_NVVM_COMPILER_WARN_32   = 515,
     531             :     INT_NVVM_COMPILER_WARN_64   = 516,
     532             :     INT_NVVM_COS_APPROX_F       = 517,
     533             :     INT_NVVM_COS_APPROX_FTZ_F   = 518,
     534             :     INT_NVVM_D2I_HI     = 519,
     535             :     INT_NVVM_D2I_LO     = 520,
     536             :     INT_NVVM_DIV_APPROX_F       = 521,
     537             :     INT_NVVM_DIV_APPROX_FTZ_F   = 522,
     538             :     INT_NVVM_DIV_RM_D   = 523,
     539             :     INT_NVVM_DIV_RM_F   = 524,
     540             :     INT_NVVM_DIV_RM_FTZ_F       = 525,
     541             :     INT_NVVM_DIV_RN_D   = 526,
     542             :     INT_NVVM_DIV_RN_F   = 527,
     543             :     INT_NVVM_DIV_RN_FTZ_F       = 528,
     544             :     INT_NVVM_DIV_RP_D   = 529,
     545             :     INT_NVVM_DIV_RP_F   = 530,
     546             :     INT_NVVM_DIV_RP_FTZ_F       = 531,
     547             :     INT_NVVM_DIV_RZ_D   = 532,
     548             :     INT_NVVM_DIV_RZ_F   = 533,
     549             :     INT_NVVM_DIV_RZ_FTZ_F       = 534,
     550             :     INT_NVVM_EX2_APPROX_D       = 535,
     551             :     INT_NVVM_EX2_APPROX_F       = 536,
     552             :     INT_NVVM_EX2_APPROX_FTZ_F   = 537,
     553             :     INT_NVVM_FABS_D     = 538,
     554             :     INT_NVVM_FABS_F     = 539,
     555             :     INT_NVVM_FABS_FTZ_F = 540,
     556             :     INT_NVVM_FMAX_D     = 541,
     557             :     INT_NVVM_FMAX_F     = 542,
     558             :     INT_NVVM_FMAX_FTZ_F = 543,
     559             :     INT_NVVM_FMA_RM_D   = 544,
     560             :     INT_NVVM_FMA_RM_F   = 545,
     561             :     INT_NVVM_FMA_RM_FTZ_F       = 546,
     562             :     INT_NVVM_FMA_RN_D   = 547,
     563             :     INT_NVVM_FMA_RN_F   = 548,
     564             :     INT_NVVM_FMA_RN_FTZ_F       = 549,
     565             :     INT_NVVM_FMA_RP_D   = 550,
     566             :     INT_NVVM_FMA_RP_F   = 551,
     567             :     INT_NVVM_FMA_RP_FTZ_F       = 552,
     568             :     INT_NVVM_FMA_RZ_D   = 553,
     569             :     INT_NVVM_FMA_RZ_F   = 554,
     570             :     INT_NVVM_FMA_RZ_FTZ_F       = 555,
     571             :     INT_NVVM_FMIN_D     = 556,
     572             :     INT_NVVM_FMIN_F     = 557,
     573             :     INT_NVVM_FMIN_FTZ_F = 558,
     574             :     INT_NVVM_LG2_APPROX_D       = 559,
     575             :     INT_NVVM_LG2_APPROX_F       = 560,
     576             :     INT_NVVM_LG2_APPROX_FTZ_F   = 561,
     577             :     INT_NVVM_LOHI_I2D   = 562,
     578             :     INT_NVVM_MUL24_I    = 563,
     579             :     INT_NVVM_MUL24_UI   = 564,
     580             :     INT_NVVM_MULHI_I    = 565,
     581             :     INT_NVVM_MULHI_LL   = 566,
     582             :     INT_NVVM_MULHI_UI   = 567,
     583             :     INT_NVVM_MULHI_ULL  = 568,
     584             :     INT_NVVM_MUL_RM_D   = 569,
     585             :     INT_NVVM_MUL_RM_F   = 570,
     586             :     INT_NVVM_MUL_RM_FTZ_F       = 571,
     587             :     INT_NVVM_MUL_RN_D   = 572,
     588             :     INT_NVVM_MUL_RN_F   = 573,
     589             :     INT_NVVM_MUL_RN_FTZ_F       = 574,
     590             :     INT_NVVM_MUL_RP_D   = 575,
     591             :     INT_NVVM_MUL_RP_F   = 576,
     592             :     INT_NVVM_MUL_RP_FTZ_F       = 577,
     593             :     INT_NVVM_MUL_RZ_D   = 578,
     594             :     INT_NVVM_MUL_RZ_F   = 579,
     595             :     INT_NVVM_MUL_RZ_FTZ_F       = 580,
     596             :     INT_NVVM_PRMT       = 581,
     597             :     INT_NVVM_RCP_APPROX_FTZ_D   = 582,
     598             :     INT_NVVM_RCP_RM_D   = 583,
     599             :     INT_NVVM_RCP_RM_F   = 584,
     600             :     INT_NVVM_RCP_RM_FTZ_F       = 585,
     601             :     INT_NVVM_RCP_RN_D   = 586,
     602             :     INT_NVVM_RCP_RN_F   = 587,
     603             :     INT_NVVM_RCP_RN_FTZ_F       = 588,
     604             :     INT_NVVM_RCP_RP_D   = 589,
     605             :     INT_NVVM_RCP_RP_F   = 590,
     606             :     INT_NVVM_RCP_RP_FTZ_F       = 591,
     607             :     INT_NVVM_RCP_RZ_D   = 592,
     608             :     INT_NVVM_RCP_RZ_F   = 593,
     609             :     INT_NVVM_RCP_RZ_FTZ_F       = 594,
     610             :     INT_NVVM_RSQRT_APPROX_D     = 595,
     611             :     INT_NVVM_RSQRT_APPROX_F     = 596,
     612             :     INT_NVVM_RSQRT_APPROX_FTZ_F = 597,
     613             :     INT_NVVM_SAD_I      = 598,
     614             :     INT_NVVM_SAD_UI     = 599,
     615             :     INT_NVVM_SIN_APPROX_F       = 600,
     616             :     INT_NVVM_SIN_APPROX_FTZ_F   = 601,
     617             :     INT_NVVM_SQRT_APPROX_F      = 602,
     618             :     INT_NVVM_SQRT_APPROX_FTZ_F  = 603,
     619             :     INT_NVVM_SQRT_RM_D  = 604,
     620             :     INT_NVVM_SQRT_RM_F  = 605,
     621             :     INT_NVVM_SQRT_RM_FTZ_F      = 606,
     622             :     INT_NVVM_SQRT_RN_D  = 607,
     623             :     INT_NVVM_SQRT_RN_F  = 608,
     624             :     INT_NVVM_SQRT_RN_FTZ_F      = 609,
     625             :     INT_NVVM_SQRT_RP_D  = 610,
     626             :     INT_NVVM_SQRT_RP_F  = 611,
     627             :     INT_NVVM_SQRT_RP_FTZ_F      = 612,
     628             :     INT_NVVM_SQRT_RZ_D  = 613,
     629             :     INT_NVVM_SQRT_RZ_F  = 614,
     630             :     INT_NVVM_SQRT_RZ_FTZ_F      = 615,
     631             :     INT_PTX_ATOM_ADD_GEN_32_USE_Gp32imm = 616,
     632             :     INT_PTX_ATOM_ADD_GEN_32_USE_Gp32reg = 617,
     633             :     INT_PTX_ATOM_ADD_GEN_32_USE_Gp64imm = 618,
     634             :     INT_PTX_ATOM_ADD_GEN_32_USE_Gp64reg = 619,
     635             :     INT_PTX_ATOM_ADD_GEN_32p32imm       = 620,
     636             :     INT_PTX_ATOM_ADD_GEN_32p32reg       = 621,
     637             :     INT_PTX_ATOM_ADD_GEN_32p64imm       = 622,
     638             :     INT_PTX_ATOM_ADD_GEN_32p64reg       = 623,
     639             :     INT_PTX_ATOM_ADD_GEN_64_USE_Gp32imm = 624,
     640             :     INT_PTX_ATOM_ADD_GEN_64_USE_Gp32reg = 625,
     641             :     INT_PTX_ATOM_ADD_GEN_64_USE_Gp64imm = 626,
     642             :     INT_PTX_ATOM_ADD_GEN_64_USE_Gp64reg = 627,
     643             :     INT_PTX_ATOM_ADD_GEN_64p32imm       = 628,
     644             :     INT_PTX_ATOM_ADD_GEN_64p32reg       = 629,
     645             :     INT_PTX_ATOM_ADD_GEN_64p64imm       = 630,
     646             :     INT_PTX_ATOM_ADD_GEN_64p64reg       = 631,
     647             :     INT_PTX_ATOM_ADD_GEN_F32p32imm      = 632,
     648             :     INT_PTX_ATOM_ADD_GEN_F32p32reg      = 633,
     649             :     INT_PTX_ATOM_ADD_GEN_F32p64imm      = 634,
     650             :     INT_PTX_ATOM_ADD_GEN_F32p64reg      = 635,
     651             :     INT_PTX_ATOM_ADD_G_32p32imm = 636,
     652             :     INT_PTX_ATOM_ADD_G_32p32reg = 637,
     653             :     INT_PTX_ATOM_ADD_G_32p64imm = 638,
     654             :     INT_PTX_ATOM_ADD_G_32p64reg = 639,
     655             :     INT_PTX_ATOM_ADD_G_64p32imm = 640,
     656             :     INT_PTX_ATOM_ADD_G_64p32reg = 641,
     657             :     INT_PTX_ATOM_ADD_G_64p64imm = 642,
     658             :     INT_PTX_ATOM_ADD_G_64p64reg = 643,
     659             :     INT_PTX_ATOM_ADD_G_F32p32imm        = 644,
     660             :     INT_PTX_ATOM_ADD_G_F32p32reg        = 645,
     661             :     INT_PTX_ATOM_ADD_G_F32p64imm        = 646,
     662             :     INT_PTX_ATOM_ADD_G_F32p64reg        = 647,
     663             :     INT_PTX_ATOM_ADD_S_32p32imm = 648,
     664             :     INT_PTX_ATOM_ADD_S_32p32reg = 649,
     665             :     INT_PTX_ATOM_ADD_S_32p64imm = 650,
     666             :     INT_PTX_ATOM_ADD_S_32p64reg = 651,
     667             :     INT_PTX_ATOM_ADD_S_64p32imm = 652,
     668             :     INT_PTX_ATOM_ADD_S_64p32reg = 653,
     669             :     INT_PTX_ATOM_ADD_S_64p64imm = 654,
     670             :     INT_PTX_ATOM_ADD_S_64p64reg = 655,
     671             :     INT_PTX_ATOM_ADD_S_F32p32imm        = 656,
     672             :     INT_PTX_ATOM_ADD_S_F32p32reg        = 657,
     673             :     INT_PTX_ATOM_ADD_S_F32p64imm        = 658,
     674             :     INT_PTX_ATOM_ADD_S_F32p64reg        = 659,
     675             :     INT_PTX_ATOM_AND_GEN_32_USE_Gp32imm = 660,
     676             :     INT_PTX_ATOM_AND_GEN_32_USE_Gp32reg = 661,
     677             :     INT_PTX_ATOM_AND_GEN_32_USE_Gp64imm = 662,
     678             :     INT_PTX_ATOM_AND_GEN_32_USE_Gp64reg = 663,
     679             :     INT_PTX_ATOM_AND_GEN_32p32imm       = 664,
     680             :     INT_PTX_ATOM_AND_GEN_32p32reg       = 665,
     681             :     INT_PTX_ATOM_AND_GEN_32p64imm       = 666,
     682             :     INT_PTX_ATOM_AND_GEN_32p64reg       = 667,
     683             :     INT_PTX_ATOM_AND_GEN_64_USE_Gp32imm = 668,
     684             :     INT_PTX_ATOM_AND_GEN_64_USE_Gp32reg = 669,
     685             :     INT_PTX_ATOM_AND_GEN_64_USE_Gp64imm = 670,
     686             :     INT_PTX_ATOM_AND_GEN_64_USE_Gp64reg = 671,
     687             :     INT_PTX_ATOM_AND_GEN_64p32imm       = 672,
     688             :     INT_PTX_ATOM_AND_GEN_64p32reg       = 673,
     689             :     INT_PTX_ATOM_AND_GEN_64p64imm       = 674,
     690             :     INT_PTX_ATOM_AND_GEN_64p64reg       = 675,
     691             :     INT_PTX_ATOM_AND_G_32p32imm = 676,
     692             :     INT_PTX_ATOM_AND_G_32p32reg = 677,
     693             :     INT_PTX_ATOM_AND_G_32p64imm = 678,
     694             :     INT_PTX_ATOM_AND_G_32p64reg = 679,
     695             :     INT_PTX_ATOM_AND_G_64p32imm = 680,
     696             :     INT_PTX_ATOM_AND_G_64p32reg = 681,
     697             :     INT_PTX_ATOM_AND_G_64p64imm = 682,
     698             :     INT_PTX_ATOM_AND_G_64p64reg = 683,
     699             :     INT_PTX_ATOM_AND_S_32p32imm = 684,
     700             :     INT_PTX_ATOM_AND_S_32p32reg = 685,
     701             :     INT_PTX_ATOM_AND_S_32p64imm = 686,
     702             :     INT_PTX_ATOM_AND_S_32p64reg = 687,
     703             :     INT_PTX_ATOM_AND_S_64p32imm = 688,
     704             :     INT_PTX_ATOM_AND_S_64p32reg = 689,
     705             :     INT_PTX_ATOM_AND_S_64p64imm = 690,
     706             :     INT_PTX_ATOM_AND_S_64p64reg = 691,
     707             :     INT_PTX_ATOM_CAS_GEN_32_USE_Gp32imm1        = 692,
     708             :     INT_PTX_ATOM_CAS_GEN_32_USE_Gp32imm2        = 693,
     709             :     INT_PTX_ATOM_CAS_GEN_32_USE_Gp32imm3        = 694,
     710             :     INT_PTX_ATOM_CAS_GEN_32_USE_Gp32reg = 695,
     711             :     INT_PTX_ATOM_CAS_GEN_32_USE_Gp64imm1        = 696,
     712             :     INT_PTX_ATOM_CAS_GEN_32_USE_Gp64imm2        = 697,
     713             :     INT_PTX_ATOM_CAS_GEN_32_USE_Gp64imm3        = 698,
     714             :     INT_PTX_ATOM_CAS_GEN_32_USE_Gp64reg = 699,
     715             :     INT_PTX_ATOM_CAS_GEN_32p32imm1      = 700,
     716             :     INT_PTX_ATOM_CAS_GEN_32p32imm2      = 701,
     717             :     INT_PTX_ATOM_CAS_GEN_32p32imm3      = 702,
     718             :     INT_PTX_ATOM_CAS_GEN_32p32reg       = 703,
     719             :     INT_PTX_ATOM_CAS_GEN_32p64imm1      = 704,
     720             :     INT_PTX_ATOM_CAS_GEN_32p64imm2      = 705,
     721             :     INT_PTX_ATOM_CAS_GEN_32p64imm3      = 706,
     722             :     INT_PTX_ATOM_CAS_GEN_32p64reg       = 707,
     723             :     INT_PTX_ATOM_CAS_GEN_64_USE_Gp32imm1        = 708,
     724             :     INT_PTX_ATOM_CAS_GEN_64_USE_Gp32imm2        = 709,
     725             :     INT_PTX_ATOM_CAS_GEN_64_USE_Gp32imm3        = 710,
     726             :     INT_PTX_ATOM_CAS_GEN_64_USE_Gp32reg = 711,
     727             :     INT_PTX_ATOM_CAS_GEN_64_USE_Gp64imm1        = 712,
     728             :     INT_PTX_ATOM_CAS_GEN_64_USE_Gp64imm2        = 713,
     729             :     INT_PTX_ATOM_CAS_GEN_64_USE_Gp64imm3        = 714,
     730             :     INT_PTX_ATOM_CAS_GEN_64_USE_Gp64reg = 715,
     731             :     INT_PTX_ATOM_CAS_GEN_64p32imm1      = 716,
     732             :     INT_PTX_ATOM_CAS_GEN_64p32imm2      = 717,
     733             :     INT_PTX_ATOM_CAS_GEN_64p32imm3      = 718,
     734             :     INT_PTX_ATOM_CAS_GEN_64p32reg       = 719,
     735             :     INT_PTX_ATOM_CAS_GEN_64p64imm1      = 720,
     736             :     INT_PTX_ATOM_CAS_GEN_64p64imm2      = 721,
     737             :     INT_PTX_ATOM_CAS_GEN_64p64imm3      = 722,
     738             :     INT_PTX_ATOM_CAS_GEN_64p64reg       = 723,
     739             :     INT_PTX_ATOM_CAS_G_32p32imm1        = 724,
     740             :     INT_PTX_ATOM_CAS_G_32p32imm2        = 725,
     741             :     INT_PTX_ATOM_CAS_G_32p32imm3        = 726,
     742             :     INT_PTX_ATOM_CAS_G_32p32reg = 727,
     743             :     INT_PTX_ATOM_CAS_G_32p64imm1        = 728,
     744             :     INT_PTX_ATOM_CAS_G_32p64imm2        = 729,
     745             :     INT_PTX_ATOM_CAS_G_32p64imm3        = 730,
     746             :     INT_PTX_ATOM_CAS_G_32p64reg = 731,
     747             :     INT_PTX_ATOM_CAS_G_64p32imm1        = 732,
     748             :     INT_PTX_ATOM_CAS_G_64p32imm2        = 733,
     749             :     INT_PTX_ATOM_CAS_G_64p32imm3        = 734,
     750             :     INT_PTX_ATOM_CAS_G_64p32reg = 735,
     751             :     INT_PTX_ATOM_CAS_G_64p64imm1        = 736,
     752             :     INT_PTX_ATOM_CAS_G_64p64imm2        = 737,
     753             :     INT_PTX_ATOM_CAS_G_64p64imm3        = 738,
     754             :     INT_PTX_ATOM_CAS_G_64p64reg = 739,
     755             :     INT_PTX_ATOM_CAS_S_32p32imm1        = 740,
     756             :     INT_PTX_ATOM_CAS_S_32p32imm2        = 741,
     757             :     INT_PTX_ATOM_CAS_S_32p32imm3        = 742,
     758             :     INT_PTX_ATOM_CAS_S_32p32reg = 743,
     759             :     INT_PTX_ATOM_CAS_S_32p64imm1        = 744,
     760             :     INT_PTX_ATOM_CAS_S_32p64imm2        = 745,
     761             :     INT_PTX_ATOM_CAS_S_32p64imm3        = 746,
     762             :     INT_PTX_ATOM_CAS_S_32p64reg = 747,
     763             :     INT_PTX_ATOM_CAS_S_64p32imm1        = 748,
     764             :     INT_PTX_ATOM_CAS_S_64p32imm2        = 749,
     765             :     INT_PTX_ATOM_CAS_S_64p32imm3        = 750,
     766             :     INT_PTX_ATOM_CAS_S_64p32reg = 751,
     767             :     INT_PTX_ATOM_CAS_S_64p64imm1        = 752,
     768             :     INT_PTX_ATOM_CAS_S_64p64imm2        = 753,
     769             :     INT_PTX_ATOM_CAS_S_64p64imm3        = 754,
     770             :     INT_PTX_ATOM_CAS_S_64p64reg = 755,
     771             :     INT_PTX_ATOM_DEC_GEN_32_USE_Gp32imm = 756,
     772             :     INT_PTX_ATOM_DEC_GEN_32_USE_Gp32reg = 757,
     773             :     INT_PTX_ATOM_DEC_GEN_32_USE_Gp64imm = 758,
     774             :     INT_PTX_ATOM_DEC_GEN_32_USE_Gp64reg = 759,
     775             :     INT_PTX_ATOM_DEC_GEN_32p32imm       = 760,
     776             :     INT_PTX_ATOM_DEC_GEN_32p32reg       = 761,
     777             :     INT_PTX_ATOM_DEC_GEN_32p64imm       = 762,
     778             :     INT_PTX_ATOM_DEC_GEN_32p64reg       = 763,
     779             :     INT_PTX_ATOM_DEC_G_32p32imm = 764,
     780             :     INT_PTX_ATOM_DEC_G_32p32reg = 765,
     781             :     INT_PTX_ATOM_DEC_G_32p64imm = 766,
     782             :     INT_PTX_ATOM_DEC_G_32p64reg = 767,
     783             :     INT_PTX_ATOM_DEC_S_32p32imm = 768,
     784             :     INT_PTX_ATOM_DEC_S_32p32reg = 769,
     785             :     INT_PTX_ATOM_DEC_S_32p64imm = 770,
     786             :     INT_PTX_ATOM_DEC_S_32p64reg = 771,
     787             :     INT_PTX_ATOM_INC_GEN_32_USE_Gp32imm = 772,
     788             :     INT_PTX_ATOM_INC_GEN_32_USE_Gp32reg = 773,
     789             :     INT_PTX_ATOM_INC_GEN_32_USE_Gp64imm = 774,
     790             :     INT_PTX_ATOM_INC_GEN_32_USE_Gp64reg = 775,
     791             :     INT_PTX_ATOM_INC_GEN_32p32imm       = 776,
     792             :     INT_PTX_ATOM_INC_GEN_32p32reg       = 777,
     793             :     INT_PTX_ATOM_INC_GEN_32p64imm       = 778,
     794             :     INT_PTX_ATOM_INC_GEN_32p64reg       = 779,
     795             :     INT_PTX_ATOM_INC_G_32p32imm = 780,
     796             :     INT_PTX_ATOM_INC_G_32p32reg = 781,
     797             :     INT_PTX_ATOM_INC_G_32p64imm = 782,
     798             :     INT_PTX_ATOM_INC_G_32p64reg = 783,
     799             :     INT_PTX_ATOM_INC_S_32p32imm = 784,
     800             :     INT_PTX_ATOM_INC_S_32p32reg = 785,
     801             :     INT_PTX_ATOM_INC_S_32p64imm = 786,
     802             :     INT_PTX_ATOM_INC_S_32p64reg = 787,
     803             :     INT_PTX_ATOM_LOAD_MAX_GEN_32_USE_Gp32imm    = 788,
     804             :     INT_PTX_ATOM_LOAD_MAX_GEN_32_USE_Gp32reg    = 789,
     805             :     INT_PTX_ATOM_LOAD_MAX_GEN_32_USE_Gp64imm    = 790,
     806             :     INT_PTX_ATOM_LOAD_MAX_GEN_32_USE_Gp64reg    = 791,
     807             :     INT_PTX_ATOM_LOAD_MAX_GEN_32p32imm  = 792,
     808             :     INT_PTX_ATOM_LOAD_MAX_GEN_32p32reg  = 793,
     809             :     INT_PTX_ATOM_LOAD_MAX_GEN_32p64imm  = 794,
     810             :     INT_PTX_ATOM_LOAD_MAX_GEN_32p64reg  = 795,
     811             :     INT_PTX_ATOM_LOAD_MAX_GEN_64_USE_Gp32imm    = 796,
     812             :     INT_PTX_ATOM_LOAD_MAX_GEN_64_USE_Gp32reg    = 797,
     813             :     INT_PTX_ATOM_LOAD_MAX_GEN_64_USE_Gp64imm    = 798,
     814             :     INT_PTX_ATOM_LOAD_MAX_GEN_64_USE_Gp64reg    = 799,
     815             :     INT_PTX_ATOM_LOAD_MAX_GEN_64p32imm  = 800,
     816             :     INT_PTX_ATOM_LOAD_MAX_GEN_64p32reg  = 801,
     817             :     INT_PTX_ATOM_LOAD_MAX_GEN_64p64imm  = 802,
     818             :     INT_PTX_ATOM_LOAD_MAX_GEN_64p64reg  = 803,
     819             :     INT_PTX_ATOM_LOAD_MAX_G_32p32imm    = 804,
     820             :     INT_PTX_ATOM_LOAD_MAX_G_32p32reg    = 805,
     821             :     INT_PTX_ATOM_LOAD_MAX_G_32p64imm    = 806,
     822             :     INT_PTX_ATOM_LOAD_MAX_G_32p64reg    = 807,
     823             :     INT_PTX_ATOM_LOAD_MAX_G_64p32imm    = 808,
     824             :     INT_PTX_ATOM_LOAD_MAX_G_64p32reg    = 809,
     825             :     INT_PTX_ATOM_LOAD_MAX_G_64p64imm    = 810,
     826             :     INT_PTX_ATOM_LOAD_MAX_G_64p64reg    = 811,
     827             :     INT_PTX_ATOM_LOAD_MAX_S_32p32imm    = 812,
     828             :     INT_PTX_ATOM_LOAD_MAX_S_32p32reg    = 813,
     829             :     INT_PTX_ATOM_LOAD_MAX_S_32p64imm    = 814,
     830             :     INT_PTX_ATOM_LOAD_MAX_S_32p64reg    = 815,
     831             :     INT_PTX_ATOM_LOAD_MAX_S_64p32imm    = 816,
     832             :     INT_PTX_ATOM_LOAD_MAX_S_64p32reg    = 817,
     833             :     INT_PTX_ATOM_LOAD_MAX_S_64p64imm    = 818,
     834             :     INT_PTX_ATOM_LOAD_MAX_S_64p64reg    = 819,
     835             :     INT_PTX_ATOM_LOAD_MIN_GEN_32_USE_Gp32imm    = 820,
     836             :     INT_PTX_ATOM_LOAD_MIN_GEN_32_USE_Gp32reg    = 821,
     837             :     INT_PTX_ATOM_LOAD_MIN_GEN_32_USE_Gp64imm    = 822,
     838             :     INT_PTX_ATOM_LOAD_MIN_GEN_32_USE_Gp64reg    = 823,
     839             :     INT_PTX_ATOM_LOAD_MIN_GEN_32p32imm  = 824,
     840             :     INT_PTX_ATOM_LOAD_MIN_GEN_32p32reg  = 825,
     841             :     INT_PTX_ATOM_LOAD_MIN_GEN_32p64imm  = 826,
     842             :     INT_PTX_ATOM_LOAD_MIN_GEN_32p64reg  = 827,
     843             :     INT_PTX_ATOM_LOAD_MIN_GEN_64_USE_Gp32imm    = 828,
     844             :     INT_PTX_ATOM_LOAD_MIN_GEN_64_USE_Gp32reg    = 829,
     845             :     INT_PTX_ATOM_LOAD_MIN_GEN_64_USE_Gp64imm    = 830,
     846             :     INT_PTX_ATOM_LOAD_MIN_GEN_64_USE_Gp64reg    = 831,
     847             :     INT_PTX_ATOM_LOAD_MIN_GEN_64p32imm  = 832,
     848             :     INT_PTX_ATOM_LOAD_MIN_GEN_64p32reg  = 833,
     849             :     INT_PTX_ATOM_LOAD_MIN_GEN_64p64imm  = 834,
     850             :     INT_PTX_ATOM_LOAD_MIN_GEN_64p64reg  = 835,
     851             :     INT_PTX_ATOM_LOAD_MIN_G_32p32imm    = 836,
     852             :     INT_PTX_ATOM_LOAD_MIN_G_32p32reg    = 837,
     853             :     INT_PTX_ATOM_LOAD_MIN_G_32p64imm    = 838,
     854             :     INT_PTX_ATOM_LOAD_MIN_G_32p64reg    = 839,
     855             :     INT_PTX_ATOM_LOAD_MIN_G_64p32imm    = 840,
     856             :     INT_PTX_ATOM_LOAD_MIN_G_64p32reg    = 841,
     857             :     INT_PTX_ATOM_LOAD_MIN_G_64p64imm    = 842,
     858             :     INT_PTX_ATOM_LOAD_MIN_G_64p64reg    = 843,
     859             :     INT_PTX_ATOM_LOAD_MIN_S_32p32imm    = 844,
     860             :     INT_PTX_ATOM_LOAD_MIN_S_32p32reg    = 845,
     861             :     INT_PTX_ATOM_LOAD_MIN_S_32p64imm    = 846,
     862             :     INT_PTX_ATOM_LOAD_MIN_S_32p64reg    = 847,
     863             :     INT_PTX_ATOM_LOAD_MIN_S_64p32imm    = 848,
     864             :     INT_PTX_ATOM_LOAD_MIN_S_64p32reg    = 849,
     865             :     INT_PTX_ATOM_LOAD_MIN_S_64p64imm    = 850,
     866             :     INT_PTX_ATOM_LOAD_MIN_S_64p64reg    = 851,
     867             :     INT_PTX_ATOM_LOAD_UMAX_GEN_32_USE_Gp32imm   = 852,
     868             :     INT_PTX_ATOM_LOAD_UMAX_GEN_32_USE_Gp32reg   = 853,
     869             :     INT_PTX_ATOM_LOAD_UMAX_GEN_32_USE_Gp64imm   = 854,
     870             :     INT_PTX_ATOM_LOAD_UMAX_GEN_32_USE_Gp64reg   = 855,
     871             :     INT_PTX_ATOM_LOAD_UMAX_GEN_32p32imm = 856,
     872             :     INT_PTX_ATOM_LOAD_UMAX_GEN_32p32reg = 857,
     873             :     INT_PTX_ATOM_LOAD_UMAX_GEN_32p64imm = 858,
     874             :     INT_PTX_ATOM_LOAD_UMAX_GEN_32p64reg = 859,
     875             :     INT_PTX_ATOM_LOAD_UMAX_GEN_64_USE_Gp32imm   = 860,
     876             :     INT_PTX_ATOM_LOAD_UMAX_GEN_64_USE_Gp32reg   = 861,
     877             :     INT_PTX_ATOM_LOAD_UMAX_GEN_64_USE_Gp64imm   = 862,
     878             :     INT_PTX_ATOM_LOAD_UMAX_GEN_64_USE_Gp64reg   = 863,
     879             :     INT_PTX_ATOM_LOAD_UMAX_GEN_64p32imm = 864,
     880             :     INT_PTX_ATOM_LOAD_UMAX_GEN_64p32reg = 865,
     881             :     INT_PTX_ATOM_LOAD_UMAX_GEN_64p64imm = 866,
     882             :     INT_PTX_ATOM_LOAD_UMAX_GEN_64p64reg = 867,
     883             :     INT_PTX_ATOM_LOAD_UMAX_G_32p32imm   = 868,
     884             :     INT_PTX_ATOM_LOAD_UMAX_G_32p32reg   = 869,
     885             :     INT_PTX_ATOM_LOAD_UMAX_G_32p64imm   = 870,
     886             :     INT_PTX_ATOM_LOAD_UMAX_G_32p64reg   = 871,
     887             :     INT_PTX_ATOM_LOAD_UMAX_G_64p32imm   = 872,
     888             :     INT_PTX_ATOM_LOAD_UMAX_G_64p32reg   = 873,
     889             :     INT_PTX_ATOM_LOAD_UMAX_G_64p64imm   = 874,
     890             :     INT_PTX_ATOM_LOAD_UMAX_G_64p64reg   = 875,
     891             :     INT_PTX_ATOM_LOAD_UMAX_S_32p32imm   = 876,
     892             :     INT_PTX_ATOM_LOAD_UMAX_S_32p32reg   = 877,
     893             :     INT_PTX_ATOM_LOAD_UMAX_S_32p64imm   = 878,
     894             :     INT_PTX_ATOM_LOAD_UMAX_S_32p64reg   = 879,
     895             :     INT_PTX_ATOM_LOAD_UMAX_S_64p32imm   = 880,
     896             :     INT_PTX_ATOM_LOAD_UMAX_S_64p32reg   = 881,
     897             :     INT_PTX_ATOM_LOAD_UMAX_S_64p64imm   = 882,
     898             :     INT_PTX_ATOM_LOAD_UMAX_S_64p64reg   = 883,
     899             :     INT_PTX_ATOM_LOAD_UMIN_GEN_32_USE_Gp32imm   = 884,
     900             :     INT_PTX_ATOM_LOAD_UMIN_GEN_32_USE_Gp32reg   = 885,
     901             :     INT_PTX_ATOM_LOAD_UMIN_GEN_32_USE_Gp64imm   = 886,
     902             :     INT_PTX_ATOM_LOAD_UMIN_GEN_32_USE_Gp64reg   = 887,
     903             :     INT_PTX_ATOM_LOAD_UMIN_GEN_32p32imm = 888,
     904             :     INT_PTX_ATOM_LOAD_UMIN_GEN_32p32reg = 889,
     905             :     INT_PTX_ATOM_LOAD_UMIN_GEN_32p64imm = 890,
     906             :     INT_PTX_ATOM_LOAD_UMIN_GEN_32p64reg = 891,
     907             :     INT_PTX_ATOM_LOAD_UMIN_GEN_64_USE_Gp32imm   = 892,
     908             :     INT_PTX_ATOM_LOAD_UMIN_GEN_64_USE_Gp32reg   = 893,
     909             :     INT_PTX_ATOM_LOAD_UMIN_GEN_64_USE_Gp64imm   = 894,
     910             :     INT_PTX_ATOM_LOAD_UMIN_GEN_64_USE_Gp64reg   = 895,
     911             :     INT_PTX_ATOM_LOAD_UMIN_GEN_64p32imm = 896,
     912             :     INT_PTX_ATOM_LOAD_UMIN_GEN_64p32reg = 897,
     913             :     INT_PTX_ATOM_LOAD_UMIN_GEN_64p64imm = 898,
     914             :     INT_PTX_ATOM_LOAD_UMIN_GEN_64p64reg = 899,
     915             :     INT_PTX_ATOM_LOAD_UMIN_G_32p32imm   = 900,
     916             :     INT_PTX_ATOM_LOAD_UMIN_G_32p32reg   = 901,
     917             :     INT_PTX_ATOM_LOAD_UMIN_G_32p64imm   = 902,
     918             :     INT_PTX_ATOM_LOAD_UMIN_G_32p64reg   = 903,
     919             :     INT_PTX_ATOM_LOAD_UMIN_G_64p32imm   = 904,
     920             :     INT_PTX_ATOM_LOAD_UMIN_G_64p32reg   = 905,
     921             :     INT_PTX_ATOM_LOAD_UMIN_G_64p64imm   = 906,
     922             :     INT_PTX_ATOM_LOAD_UMIN_G_64p64reg   = 907,
     923             :     INT_PTX_ATOM_LOAD_UMIN_S_32p32imm   = 908,
     924             :     INT_PTX_ATOM_LOAD_UMIN_S_32p32reg   = 909,
     925             :     INT_PTX_ATOM_LOAD_UMIN_S_32p64imm   = 910,
     926             :     INT_PTX_ATOM_LOAD_UMIN_S_32p64reg   = 911,
     927             :     INT_PTX_ATOM_LOAD_UMIN_S_64p32imm   = 912,
     928             :     INT_PTX_ATOM_LOAD_UMIN_S_64p32reg   = 913,
     929             :     INT_PTX_ATOM_LOAD_UMIN_S_64p64imm   = 914,
     930             :     INT_PTX_ATOM_LOAD_UMIN_S_64p64reg   = 915,
     931             :     INT_PTX_ATOM_OR_GEN_32_USE_Gp32imm  = 916,
     932             :     INT_PTX_ATOM_OR_GEN_32_USE_Gp32reg  = 917,
     933             :     INT_PTX_ATOM_OR_GEN_32_USE_Gp64imm  = 918,
     934             :     INT_PTX_ATOM_OR_GEN_32_USE_Gp64reg  = 919,
     935             :     INT_PTX_ATOM_OR_GEN_32p32imm        = 920,
     936             :     INT_PTX_ATOM_OR_GEN_32p32reg        = 921,
     937             :     INT_PTX_ATOM_OR_GEN_32p64imm        = 922,
     938             :     INT_PTX_ATOM_OR_GEN_32p64reg        = 923,
     939             :     INT_PTX_ATOM_OR_GEN_64_USE_Gp32imm  = 924,
     940             :     INT_PTX_ATOM_OR_GEN_64_USE_Gp32reg  = 925,
     941             :     INT_PTX_ATOM_OR_GEN_64_USE_Gp64imm  = 926,
     942             :     INT_PTX_ATOM_OR_GEN_64_USE_Gp64reg  = 927,
     943             :     INT_PTX_ATOM_OR_GEN_64p32imm        = 928,
     944             :     INT_PTX_ATOM_OR_GEN_64p32reg        = 929,
     945             :     INT_PTX_ATOM_OR_GEN_64p64imm        = 930,
     946             :     INT_PTX_ATOM_OR_GEN_64p64reg        = 931,
     947             :     INT_PTX_ATOM_OR_G_32p32imm  = 932,
     948             :     INT_PTX_ATOM_OR_G_32p32reg  = 933,
     949             :     INT_PTX_ATOM_OR_G_32p64imm  = 934,
     950             :     INT_PTX_ATOM_OR_G_32p64reg  = 935,
     951             :     INT_PTX_ATOM_OR_G_64p32imm  = 936,
     952             :     INT_PTX_ATOM_OR_G_64p32reg  = 937,
     953             :     INT_PTX_ATOM_OR_G_64p64imm  = 938,
     954             :     INT_PTX_ATOM_OR_G_64p64reg  = 939,
     955             :     INT_PTX_ATOM_OR_S_32p32imm  = 940,
     956             :     INT_PTX_ATOM_OR_S_32p32reg  = 941,
     957             :     INT_PTX_ATOM_OR_S_32p64imm  = 942,
     958             :     INT_PTX_ATOM_OR_S_32p64reg  = 943,
     959             :     INT_PTX_ATOM_OR_S_64p32imm  = 944,
     960             :     INT_PTX_ATOM_OR_S_64p32reg  = 945,
     961             :     INT_PTX_ATOM_OR_S_64p64imm  = 946,
     962             :     INT_PTX_ATOM_OR_S_64p64reg  = 947,
     963             :     INT_PTX_ATOM_SUB_GEN_32_USE_Gp32reg = 948,
     964             :     INT_PTX_ATOM_SUB_GEN_32_USE_Gp64reg = 949,
     965             :     INT_PTX_ATOM_SUB_GEN_32p32reg       = 950,
     966             :     INT_PTX_ATOM_SUB_GEN_32p64reg       = 951,
     967             :     INT_PTX_ATOM_SUB_GEN_64_USE_Gp32reg = 952,
     968             :     INT_PTX_ATOM_SUB_GEN_64_USE_Gp64reg = 953,
     969             :     INT_PTX_ATOM_SUB_GEN_64p32reg       = 954,
     970             :     INT_PTX_ATOM_SUB_GEN_64p64reg       = 955,
     971             :     INT_PTX_ATOM_SUB_G_32p32reg = 956,
     972             :     INT_PTX_ATOM_SUB_G_32p64reg = 957,
     973             :     INT_PTX_ATOM_SUB_G_64p32reg = 958,
     974             :     INT_PTX_ATOM_SUB_G_64p64reg = 959,
     975             :     INT_PTX_ATOM_SUB_S_32p32reg = 960,
     976             :     INT_PTX_ATOM_SUB_S_32p64reg = 961,
     977             :     INT_PTX_ATOM_SUB_S_64p32reg = 962,
     978             :     INT_PTX_ATOM_SUB_S_64p64reg = 963,
     979             :     INT_PTX_ATOM_SWAP_GEN_32_USE_Gp32imm        = 964,
     980             :     INT_PTX_ATOM_SWAP_GEN_32_USE_Gp32reg        = 965,
     981             :     INT_PTX_ATOM_SWAP_GEN_32_USE_Gp64imm        = 966,
     982             :     INT_PTX_ATOM_SWAP_GEN_32_USE_Gp64reg        = 967,
     983             :     INT_PTX_ATOM_SWAP_GEN_32p32imm      = 968,
     984             :     INT_PTX_ATOM_SWAP_GEN_32p32reg      = 969,
     985             :     INT_PTX_ATOM_SWAP_GEN_32p64imm      = 970,
     986             :     INT_PTX_ATOM_SWAP_GEN_32p64reg      = 971,
     987             :     INT_PTX_ATOM_SWAP_GEN_64_USE_Gp32imm        = 972,
     988             :     INT_PTX_ATOM_SWAP_GEN_64_USE_Gp32reg        = 973,
     989             :     INT_PTX_ATOM_SWAP_GEN_64_USE_Gp64imm        = 974,
     990             :     INT_PTX_ATOM_SWAP_GEN_64_USE_Gp64reg        = 975,
     991             :     INT_PTX_ATOM_SWAP_GEN_64p32imm      = 976,
     992             :     INT_PTX_ATOM_SWAP_GEN_64p32reg      = 977,
     993             :     INT_PTX_ATOM_SWAP_GEN_64p64imm      = 978,
     994             :     INT_PTX_ATOM_SWAP_GEN_64p64reg      = 979,
     995             :     INT_PTX_ATOM_SWAP_G_32p32imm        = 980,
     996             :     INT_PTX_ATOM_SWAP_G_32p32reg        = 981,
     997             :     INT_PTX_ATOM_SWAP_G_32p64imm        = 982,
     998             :     INT_PTX_ATOM_SWAP_G_32p64reg        = 983,
     999             :     INT_PTX_ATOM_SWAP_G_64p32imm        = 984,
    1000             :     INT_PTX_ATOM_SWAP_G_64p32reg        = 985,
    1001             :     INT_PTX_ATOM_SWAP_G_64p64imm        = 986,
    1002             :     INT_PTX_ATOM_SWAP_G_64p64reg        = 987,
    1003             :     INT_PTX_ATOM_SWAP_S_32p32imm        = 988,
    1004             :     INT_PTX_ATOM_SWAP_S_32p32reg        = 989,
    1005             :     INT_PTX_ATOM_SWAP_S_32p64imm        = 990,
    1006             :     INT_PTX_ATOM_SWAP_S_32p64reg        = 991,
    1007             :     INT_PTX_ATOM_SWAP_S_64p32imm        = 992,
    1008             :     INT_PTX_ATOM_SWAP_S_64p32reg        = 993,
    1009             :     INT_PTX_ATOM_SWAP_S_64p64imm        = 994,
    1010             :     INT_PTX_ATOM_SWAP_S_64p64reg        = 995,
    1011             :     INT_PTX_ATOM_XOR_GEN_32_USE_Gp32imm = 996,
    1012             :     INT_PTX_ATOM_XOR_GEN_32_USE_Gp32reg = 997,
    1013             :     INT_PTX_ATOM_XOR_GEN_32_USE_Gp64imm = 998,
    1014             :     INT_PTX_ATOM_XOR_GEN_32_USE_Gp64reg = 999,
    1015             :     INT_PTX_ATOM_XOR_GEN_32p32imm       = 1000,
    1016             :     INT_PTX_ATOM_XOR_GEN_32p32reg       = 1001,
    1017             :     INT_PTX_ATOM_XOR_GEN_32p64imm       = 1002,
    1018             :     INT_PTX_ATOM_XOR_GEN_32p64reg       = 1003,
    1019             :     INT_PTX_ATOM_XOR_GEN_64_USE_Gp32imm = 1004,
    1020             :     INT_PTX_ATOM_XOR_GEN_64_USE_Gp32reg = 1005,
    1021             :     INT_PTX_ATOM_XOR_GEN_64_USE_Gp64imm = 1006,
    1022             :     INT_PTX_ATOM_XOR_GEN_64_USE_Gp64reg = 1007,
    1023             :     INT_PTX_ATOM_XOR_GEN_64p32imm       = 1008,
    1024             :     INT_PTX_ATOM_XOR_GEN_64p32reg       = 1009,
    1025             :     INT_PTX_ATOM_XOR_GEN_64p64imm       = 1010,
    1026             :     INT_PTX_ATOM_XOR_GEN_64p64reg       = 1011,
    1027             :     INT_PTX_ATOM_XOR_G_32p32imm = 1012,
    1028             :     INT_PTX_ATOM_XOR_G_32p32reg = 1013,
    1029             :     INT_PTX_ATOM_XOR_G_32p64imm = 1014,
    1030             :     INT_PTX_ATOM_XOR_G_32p64reg = 1015,
    1031             :     INT_PTX_ATOM_XOR_G_64p32imm = 1016,
    1032             :     INT_PTX_ATOM_XOR_G_64p32reg = 1017,
    1033             :     INT_PTX_ATOM_XOR_G_64p64imm = 1018,
    1034             :     INT_PTX_ATOM_XOR_G_64p64reg = 1019,
    1035             :     INT_PTX_ATOM_XOR_S_32p32imm = 1020,
    1036             :     INT_PTX_ATOM_XOR_S_32p32reg = 1021,
    1037             :     INT_PTX_ATOM_XOR_S_32p64imm = 1022,
    1038             :     INT_PTX_ATOM_XOR_S_32p64reg = 1023,
    1039             :     INT_PTX_ATOM_XOR_S_64p32imm = 1024,
    1040             :     INT_PTX_ATOM_XOR_S_64p32reg = 1025,
    1041             :     INT_PTX_ATOM_XOR_S_64p64imm = 1026,
    1042             :     INT_PTX_ATOM_XOR_S_64p64reg = 1027,
    1043             :     INT_PTX_LDG_GLOBAL_f16areg  = 1028,
    1044             :     INT_PTX_LDG_GLOBAL_f16areg64        = 1029,
    1045             :     INT_PTX_LDG_GLOBAL_f16ari   = 1030,
    1046             :     INT_PTX_LDG_GLOBAL_f16ari64 = 1031,
    1047             :     INT_PTX_LDG_GLOBAL_f16avar  = 1032,
    1048             :     INT_PTX_LDG_GLOBAL_f16x2areg        = 1033,
    1049             :     INT_PTX_LDG_GLOBAL_f16x2areg64      = 1034,
    1050             :     INT_PTX_LDG_GLOBAL_f16x2ari = 1035,
    1051             :     INT_PTX_LDG_GLOBAL_f16x2ari64       = 1036,
    1052             :     INT_PTX_LDG_GLOBAL_f16x2avar        = 1037,
    1053             :     INT_PTX_LDG_GLOBAL_f32areg  = 1038,
    1054             :     INT_PTX_LDG_GLOBAL_f32areg64        = 1039,
    1055             :     INT_PTX_LDG_GLOBAL_f32ari   = 1040,
    1056             :     INT_PTX_LDG_GLOBAL_f32ari64 = 1041,
    1057             :     INT_PTX_LDG_GLOBAL_f32avar  = 1042,
    1058             :     INT_PTX_LDG_GLOBAL_f64areg  = 1043,
    1059             :     INT_PTX_LDG_GLOBAL_f64areg64        = 1044,
    1060             :     INT_PTX_LDG_GLOBAL_f64ari   = 1045,
    1061             :     INT_PTX_LDG_GLOBAL_f64ari64 = 1046,
    1062             :     INT_PTX_LDG_GLOBAL_f64avar  = 1047,
    1063             :     INT_PTX_LDG_GLOBAL_i16areg  = 1048,
    1064             :     INT_PTX_LDG_GLOBAL_i16areg64        = 1049,
    1065             :     INT_PTX_LDG_GLOBAL_i16ari   = 1050,
    1066             :     INT_PTX_LDG_GLOBAL_i16ari64 = 1051,
    1067             :     INT_PTX_LDG_GLOBAL_i16avar  = 1052,
    1068             :     INT_PTX_LDG_GLOBAL_i32areg  = 1053,
    1069             :     INT_PTX_LDG_GLOBAL_i32areg64        = 1054,
    1070             :     INT_PTX_LDG_GLOBAL_i32ari   = 1055,
    1071             :     INT_PTX_LDG_GLOBAL_i32ari64 = 1056,
    1072             :     INT_PTX_LDG_GLOBAL_i32avar  = 1057,
    1073             :     INT_PTX_LDG_GLOBAL_i64areg  = 1058,
    1074             :     INT_PTX_LDG_GLOBAL_i64areg64        = 1059,
    1075             :     INT_PTX_LDG_GLOBAL_i64ari   = 1060,
    1076             :     INT_PTX_LDG_GLOBAL_i64ari64 = 1061,
    1077             :     INT_PTX_LDG_GLOBAL_i64avar  = 1062,
    1078             :     INT_PTX_LDG_GLOBAL_i8areg   = 1063,
    1079             :     INT_PTX_LDG_GLOBAL_i8areg64 = 1064,
    1080             :     INT_PTX_LDG_GLOBAL_i8ari    = 1065,
    1081             :     INT_PTX_LDG_GLOBAL_i8ari64  = 1066,
    1082             :     INT_PTX_LDG_GLOBAL_i8avar   = 1067,
    1083             :     INT_PTX_LDG_GLOBAL_p32areg  = 1068,
    1084             :     INT_PTX_LDG_GLOBAL_p32areg64        = 1069,
    1085             :     INT_PTX_LDG_GLOBAL_p32ari   = 1070,
    1086             :     INT_PTX_LDG_GLOBAL_p32ari64 = 1071,
    1087             :     INT_PTX_LDG_GLOBAL_p32avar  = 1072,
    1088             :     INT_PTX_LDG_GLOBAL_p64areg  = 1073,
    1089             :     INT_PTX_LDG_GLOBAL_p64areg64        = 1074,
    1090             :     INT_PTX_LDG_GLOBAL_p64ari   = 1075,
    1091             :     INT_PTX_LDG_GLOBAL_p64ari64 = 1076,
    1092             :     INT_PTX_LDG_GLOBAL_p64avar  = 1077,
    1093             :     INT_PTX_LDG_G_v2f16_ELE_areg32      = 1078,
    1094             :     INT_PTX_LDG_G_v2f16_ELE_areg64      = 1079,
    1095             :     INT_PTX_LDG_G_v2f16_ELE_ari32       = 1080,
    1096             :     INT_PTX_LDG_G_v2f16_ELE_ari64       = 1081,
    1097             :     INT_PTX_LDG_G_v2f16_ELE_avar        = 1082,
    1098             :     INT_PTX_LDG_G_v2f16x2_ELE_areg32    = 1083,
    1099             :     INT_PTX_LDG_G_v2f16x2_ELE_areg64    = 1084,
    1100             :     INT_PTX_LDG_G_v2f16x2_ELE_ari32     = 1085,
    1101             :     INT_PTX_LDG_G_v2f16x2_ELE_ari64     = 1086,
    1102             :     INT_PTX_LDG_G_v2f16x2_ELE_avar      = 1087,
    1103             :     INT_PTX_LDG_G_v2f32_ELE_areg32      = 1088,
    1104             :     INT_PTX_LDG_G_v2f32_ELE_areg64      = 1089,
    1105             :     INT_PTX_LDG_G_v2f32_ELE_ari32       = 1090,
    1106             :     INT_PTX_LDG_G_v2f32_ELE_ari64       = 1091,
    1107             :     INT_PTX_LDG_G_v2f32_ELE_avar        = 1092,
    1108             :     INT_PTX_LDG_G_v2f64_ELE_areg32      = 1093,
    1109             :     INT_PTX_LDG_G_v2f64_ELE_areg64      = 1094,
    1110             :     INT_PTX_LDG_G_v2f64_ELE_ari32       = 1095,
    1111             :     INT_PTX_LDG_G_v2f64_ELE_ari64       = 1096,
    1112             :     INT_PTX_LDG_G_v2f64_ELE_avar        = 1097,
    1113             :     INT_PTX_LDG_G_v2i16_ELE_areg32      = 1098,
    1114             :     INT_PTX_LDG_G_v2i16_ELE_areg64      = 1099,
    1115             :     INT_PTX_LDG_G_v2i16_ELE_ari32       = 1100,
    1116             :     INT_PTX_LDG_G_v2i16_ELE_ari64       = 1101,
    1117             :     INT_PTX_LDG_G_v2i16_ELE_avar        = 1102,
    1118             :     INT_PTX_LDG_G_v2i32_ELE_areg32      = 1103,
    1119             :     INT_PTX_LDG_G_v2i32_ELE_areg64      = 1104,
    1120             :     INT_PTX_LDG_G_v2i32_ELE_ari32       = 1105,
    1121             :     INT_PTX_LDG_G_v2i32_ELE_ari64       = 1106,
    1122             :     INT_PTX_LDG_G_v2i32_ELE_avar        = 1107,
    1123             :     INT_PTX_LDG_G_v2i64_ELE_areg32      = 1108,
    1124             :     INT_PTX_LDG_G_v2i64_ELE_areg64      = 1109,
    1125             :     INT_PTX_LDG_G_v2i64_ELE_ari32       = 1110,
    1126             :     INT_PTX_LDG_G_v2i64_ELE_ari64       = 1111,
    1127             :     INT_PTX_LDG_G_v2i64_ELE_avar        = 1112,
    1128             :     INT_PTX_LDG_G_v2i8_ELE_areg32       = 1113,
    1129             :     INT_PTX_LDG_G_v2i8_ELE_areg64       = 1114,
    1130             :     INT_PTX_LDG_G_v2i8_ELE_ari32        = 1115,
    1131             :     INT_PTX_LDG_G_v2i8_ELE_ari64        = 1116,
    1132             :     INT_PTX_LDG_G_v2i8_ELE_avar = 1117,
    1133             :     INT_PTX_LDG_G_v4f16_ELE_areg32      = 1118,
    1134             :     INT_PTX_LDG_G_v4f16_ELE_areg64      = 1119,
    1135             :     INT_PTX_LDG_G_v4f16_ELE_ari32       = 1120,
    1136             :     INT_PTX_LDG_G_v4f16_ELE_ari64       = 1121,
    1137             :     INT_PTX_LDG_G_v4f16_ELE_avar        = 1122,
    1138             :     INT_PTX_LDG_G_v4f16x2_ELE_areg32    = 1123,
    1139             :     INT_PTX_LDG_G_v4f16x2_ELE_areg64    = 1124,
    1140             :     INT_PTX_LDG_G_v4f16x2_ELE_ari32     = 1125,
    1141             :     INT_PTX_LDG_G_v4f16x2_ELE_ari64     = 1126,
    1142             :     INT_PTX_LDG_G_v4f16x2_ELE_avar      = 1127,
    1143             :     INT_PTX_LDG_G_v4f32_ELE_areg32      = 1128,
    1144             :     INT_PTX_LDG_G_v4f32_ELE_areg64      = 1129,
    1145             :     INT_PTX_LDG_G_v4f32_ELE_ari32       = 1130,
    1146             :     INT_PTX_LDG_G_v4f32_ELE_ari64       = 1131,
    1147             :     INT_PTX_LDG_G_v4f32_ELE_avar        = 1132,
    1148             :     INT_PTX_LDG_G_v4i16_ELE_areg32      = 1133,
    1149             :     INT_PTX_LDG_G_v4i16_ELE_areg64      = 1134,
    1150             :     INT_PTX_LDG_G_v4i16_ELE_ari32       = 1135,
    1151             :     INT_PTX_LDG_G_v4i16_ELE_ari64       = 1136,
    1152             :     INT_PTX_LDG_G_v4i16_ELE_avar        = 1137,
    1153             :     INT_PTX_LDG_G_v4i32_ELE_areg32      = 1138,
    1154             :     INT_PTX_LDG_G_v4i32_ELE_areg64      = 1139,
    1155             :     INT_PTX_LDG_G_v4i32_ELE_ari32       = 1140,
    1156             :     INT_PTX_LDG_G_v4i32_ELE_ari64       = 1141,
    1157             :     INT_PTX_LDG_G_v4i32_ELE_avar        = 1142,
    1158             :     INT_PTX_LDG_G_v4i8_ELE_areg32       = 1143,
    1159             :     INT_PTX_LDG_G_v4i8_ELE_areg64       = 1144,
    1160             :     INT_PTX_LDG_G_v4i8_ELE_ari32        = 1145,
    1161             :     INT_PTX_LDG_G_v4i8_ELE_ari64        = 1146,
    1162             :     INT_PTX_LDG_G_v4i8_ELE_avar = 1147,
    1163             :     INT_PTX_LDU_GLOBAL_f16areg  = 1148,
    1164             :     INT_PTX_LDU_GLOBAL_f16areg64        = 1149,
    1165             :     INT_PTX_LDU_GLOBAL_f16ari   = 1150,
    1166             :     INT_PTX_LDU_GLOBAL_f16ari64 = 1151,
    1167             :     INT_PTX_LDU_GLOBAL_f16avar  = 1152,
    1168             :     INT_PTX_LDU_GLOBAL_f16x2areg        = 1153,
    1169             :     INT_PTX_LDU_GLOBAL_f16x2areg64      = 1154,
    1170             :     INT_PTX_LDU_GLOBAL_f16x2ari = 1155,
    1171             :     INT_PTX_LDU_GLOBAL_f16x2ari64       = 1156,
    1172             :     INT_PTX_LDU_GLOBAL_f16x2avar        = 1157,
    1173             :     INT_PTX_LDU_GLOBAL_f32areg  = 1158,
    1174             :     INT_PTX_LDU_GLOBAL_f32areg64        = 1159,
    1175             :     INT_PTX_LDU_GLOBAL_f32ari   = 1160,
    1176             :     INT_PTX_LDU_GLOBAL_f32ari64 = 1161,
    1177             :     INT_PTX_LDU_GLOBAL_f32avar  = 1162,
    1178             :     INT_PTX_LDU_GLOBAL_f64areg  = 1163,
    1179             :     INT_PTX_LDU_GLOBAL_f64areg64        = 1164,
    1180             :     INT_PTX_LDU_GLOBAL_f64ari   = 1165,
    1181             :     INT_PTX_LDU_GLOBAL_f64ari64 = 1166,
    1182             :     INT_PTX_LDU_GLOBAL_f64avar  = 1167,
    1183             :     INT_PTX_LDU_GLOBAL_i16areg  = 1168,
    1184             :     INT_PTX_LDU_GLOBAL_i16areg64        = 1169,
    1185             :     INT_PTX_LDU_GLOBAL_i16ari   = 1170,
    1186             :     INT_PTX_LDU_GLOBAL_i16ari64 = 1171,
    1187             :     INT_PTX_LDU_GLOBAL_i16avar  = 1172,
    1188             :     INT_PTX_LDU_GLOBAL_i32areg  = 1173,
    1189             :     INT_PTX_LDU_GLOBAL_i32areg64        = 1174,
    1190             :     INT_PTX_LDU_GLOBAL_i32ari   = 1175,
    1191             :     INT_PTX_LDU_GLOBAL_i32ari64 = 1176,
    1192             :     INT_PTX_LDU_GLOBAL_i32avar  = 1177,
    1193             :     INT_PTX_LDU_GLOBAL_i64areg  = 1178,
    1194             :     INT_PTX_LDU_GLOBAL_i64areg64        = 1179,
    1195             :     INT_PTX_LDU_GLOBAL_i64ari   = 1180,
    1196             :     INT_PTX_LDU_GLOBAL_i64ari64 = 1181,
    1197             :     INT_PTX_LDU_GLOBAL_i64avar  = 1182,
    1198             :     INT_PTX_LDU_GLOBAL_i8areg   = 1183,
    1199             :     INT_PTX_LDU_GLOBAL_i8areg64 = 1184,
    1200             :     INT_PTX_LDU_GLOBAL_i8ari    = 1185,
    1201             :     INT_PTX_LDU_GLOBAL_i8ari64  = 1186,
    1202             :     INT_PTX_LDU_GLOBAL_i8avar   = 1187,
    1203             :     INT_PTX_LDU_GLOBAL_p32areg  = 1188,
    1204             :     INT_PTX_LDU_GLOBAL_p32areg64        = 1189,
    1205             :     INT_PTX_LDU_GLOBAL_p32ari   = 1190,
    1206             :     INT_PTX_LDU_GLOBAL_p32ari64 = 1191,
    1207             :     INT_PTX_LDU_GLOBAL_p32avar  = 1192,
    1208             :     INT_PTX_LDU_GLOBAL_p64areg  = 1193,
    1209             :     INT_PTX_LDU_GLOBAL_p64areg64        = 1194,
    1210             :     INT_PTX_LDU_GLOBAL_p64ari   = 1195,
    1211             :     INT_PTX_LDU_GLOBAL_p64ari64 = 1196,
    1212             :     INT_PTX_LDU_GLOBAL_p64avar  = 1197,
    1213             :     INT_PTX_LDU_G_v2f16_ELE_areg32      = 1198,
    1214             :     INT_PTX_LDU_G_v2f16_ELE_areg64      = 1199,
    1215             :     INT_PTX_LDU_G_v2f16_ELE_ari32       = 1200,
    1216             :     INT_PTX_LDU_G_v2f16_ELE_ari64       = 1201,
    1217             :     INT_PTX_LDU_G_v2f16_ELE_avar        = 1202,
    1218             :     INT_PTX_LDU_G_v2f16x2_ELE_areg32    = 1203,
    1219             :     INT_PTX_LDU_G_v2f16x2_ELE_areg64    = 1204,
    1220             :     INT_PTX_LDU_G_v2f16x2_ELE_ari32     = 1205,
    1221             :     INT_PTX_LDU_G_v2f16x2_ELE_ari64     = 1206,
    1222             :     INT_PTX_LDU_G_v2f16x2_ELE_avar      = 1207,
    1223             :     INT_PTX_LDU_G_v2f32_ELE_areg32      = 1208,
    1224             :     INT_PTX_LDU_G_v2f32_ELE_areg64      = 1209,
    1225             :     INT_PTX_LDU_G_v2f32_ELE_ari32       = 1210,
    1226             :     INT_PTX_LDU_G_v2f32_ELE_ari64       = 1211,
    1227             :     INT_PTX_LDU_G_v2f32_ELE_avar        = 1212,
    1228             :     INT_PTX_LDU_G_v2f64_ELE_areg32      = 1213,
    1229             :     INT_PTX_LDU_G_v2f64_ELE_areg64      = 1214,
    1230             :     INT_PTX_LDU_G_v2f64_ELE_ari32       = 1215,
    1231             :     INT_PTX_LDU_G_v2f64_ELE_ari64       = 1216,
    1232             :     INT_PTX_LDU_G_v2f64_ELE_avar        = 1217,
    1233             :     INT_PTX_LDU_G_v2i16_ELE_areg32      = 1218,
    1234             :     INT_PTX_LDU_G_v2i16_ELE_areg64      = 1219,
    1235             :     INT_PTX_LDU_G_v2i16_ELE_ari32       = 1220,
    1236             :     INT_PTX_LDU_G_v2i16_ELE_ari64       = 1221,
    1237             :     INT_PTX_LDU_G_v2i16_ELE_avar        = 1222,
    1238             :     INT_PTX_LDU_G_v2i32_ELE_areg32      = 1223,
    1239             :     INT_PTX_LDU_G_v2i32_ELE_areg64      = 1224,
    1240             :     INT_PTX_LDU_G_v2i32_ELE_ari32       = 1225,
    1241             :     INT_PTX_LDU_G_v2i32_ELE_ari64       = 1226,
    1242             :     INT_PTX_LDU_G_v2i32_ELE_avar        = 1227,
    1243             :     INT_PTX_LDU_G_v2i64_ELE_areg32      = 1228,
    1244             :     INT_PTX_LDU_G_v2i64_ELE_areg64      = 1229,
    1245             :     INT_PTX_LDU_G_v2i64_ELE_ari32       = 1230,
    1246             :     INT_PTX_LDU_G_v2i64_ELE_ari64       = 1231,
    1247             :     INT_PTX_LDU_G_v2i64_ELE_avar        = 1232,
    1248             :     INT_PTX_LDU_G_v2i8_ELE_areg32       = 1233,
    1249             :     INT_PTX_LDU_G_v2i8_ELE_areg64       = 1234,
    1250             :     INT_PTX_LDU_G_v2i8_ELE_ari32        = 1235,
    1251             :     INT_PTX_LDU_G_v2i8_ELE_ari64        = 1236,
    1252             :     INT_PTX_LDU_G_v2i8_ELE_avar = 1237,
    1253             :     INT_PTX_LDU_G_v4f16_ELE_areg32      = 1238,
    1254             :     INT_PTX_LDU_G_v4f16_ELE_areg64      = 1239,
    1255             :     INT_PTX_LDU_G_v4f16_ELE_ari32       = 1240,
    1256             :     INT_PTX_LDU_G_v4f16_ELE_ari64       = 1241,
    1257             :     INT_PTX_LDU_G_v4f16_ELE_avar        = 1242,
    1258             :     INT_PTX_LDU_G_v4f16x2_ELE_areg32    = 1243,
    1259             :     INT_PTX_LDU_G_v4f16x2_ELE_areg64    = 1244,
    1260             :     INT_PTX_LDU_G_v4f16x2_ELE_ari32     = 1245,
    1261             :     INT_PTX_LDU_G_v4f16x2_ELE_ari64     = 1246,
    1262             :     INT_PTX_LDU_G_v4f16x2_ELE_avar      = 1247,
    1263             :     INT_PTX_LDU_G_v4f32_ELE_areg32      = 1248,
    1264             :     INT_PTX_LDU_G_v4f32_ELE_areg64      = 1249,
    1265             :     INT_PTX_LDU_G_v4f32_ELE_ari32       = 1250,
    1266             :     INT_PTX_LDU_G_v4f32_ELE_ari64       = 1251,
    1267             :     INT_PTX_LDU_G_v4f32_ELE_avar        = 1252,
    1268             :     INT_PTX_LDU_G_v4i16_ELE_areg32      = 1253,
    1269             :     INT_PTX_LDU_G_v4i16_ELE_areg64      = 1254,
    1270             :     INT_PTX_LDU_G_v4i16_ELE_ari32       = 1255,
    1271             :     INT_PTX_LDU_G_v4i16_ELE_ari64       = 1256,
    1272             :     INT_PTX_LDU_G_v4i16_ELE_avar        = 1257,
    1273             :     INT_PTX_LDU_G_v4i32_ELE_areg32      = 1258,
    1274             :     INT_PTX_LDU_G_v4i32_ELE_areg64      = 1259,
    1275             :     INT_PTX_LDU_G_v4i32_ELE_ari32       = 1260,
    1276             :     INT_PTX_LDU_G_v4i32_ELE_ari64       = 1261,
    1277             :     INT_PTX_LDU_G_v4i32_ELE_avar        = 1262,
    1278             :     INT_PTX_LDU_G_v4i8_ELE_areg32       = 1263,
    1279             :     INT_PTX_LDU_G_v4i8_ELE_areg64       = 1264,
    1280             :     INT_PTX_LDU_G_v4i8_ELE_ari32        = 1265,
    1281             :     INT_PTX_LDU_G_v4i8_ELE_ari64        = 1266,
    1282             :     INT_PTX_LDU_G_v4i8_ELE_avar = 1267,
    1283             :     INT_PTX_SATOM_ADD_f32_cta_gen_anonymous_1062anonymous_1050  = 1268,
    1284             :     INT_PTX_SATOM_ADD_f32_cta_gen_anonymous_1062anonymous_1051  = 1269,
    1285             :     INT_PTX_SATOM_ADD_f32_cta_gen_anonymous_1062anonymous_1052  = 1270,
    1286             :     INT_PTX_SATOM_ADD_f32_cta_gen_anonymous_1062anonymous_1053  = 1271,
    1287             :     INT_PTX_SATOM_ADD_f32_sys_gen_anonymous_1062anonymous_1050  = 1272,
    1288             :     INT_PTX_SATOM_ADD_f32_sys_gen_anonymous_1062anonymous_1051  = 1273,
    1289             :     INT_PTX_SATOM_ADD_f32_sys_gen_anonymous_1062anonymous_1052  = 1274,
    1290             :     INT_PTX_SATOM_ADD_f32_sys_gen_anonymous_1062anonymous_1053  = 1275,
    1291             :     INT_PTX_SATOM_ADD_f64_cta_gen_anonymous_1062anonymous_1050  = 1276,
    1292             :     INT_PTX_SATOM_ADD_f64_cta_gen_anonymous_1062anonymous_1051  = 1277,
    1293             :     INT_PTX_SATOM_ADD_f64_cta_gen_anonymous_1062anonymous_1052  = 1278,
    1294             :     INT_PTX_SATOM_ADD_f64_cta_gen_anonymous_1062anonymous_1053  = 1279,
    1295             :     INT_PTX_SATOM_ADD_f64_sys_gen_anonymous_1062anonymous_1050  = 1280,
    1296             :     INT_PTX_SATOM_ADD_f64_sys_gen_anonymous_1062anonymous_1051  = 1281,
    1297             :     INT_PTX_SATOM_ADD_f64_sys_gen_anonymous_1062anonymous_1052  = 1282,
    1298             :     INT_PTX_SATOM_ADD_f64_sys_gen_anonymous_1062anonymous_1053  = 1283,
    1299             :     INT_PTX_SATOM_ADD_s32_cta_gen_anonymous_1062anonymous_1050  = 1284,
    1300             :     INT_PTX_SATOM_ADD_s32_cta_gen_anonymous_1062anonymous_1051  = 1285,
    1301             :     INT_PTX_SATOM_ADD_s32_cta_gen_anonymous_1062anonymous_1052  = 1286,
    1302             :     INT_PTX_SATOM_ADD_s32_cta_gen_anonymous_1062anonymous_1053  = 1287,
    1303             :     INT_PTX_SATOM_ADD_s32_sys_gen_anonymous_1062anonymous_1050  = 1288,
    1304             :     INT_PTX_SATOM_ADD_s32_sys_gen_anonymous_1062anonymous_1051  = 1289,
    1305             :     INT_PTX_SATOM_ADD_s32_sys_gen_anonymous_1062anonymous_1052  = 1290,
    1306             :     INT_PTX_SATOM_ADD_s32_sys_gen_anonymous_1062anonymous_1053  = 1291,
    1307             :     INT_PTX_SATOM_ADD_u32_cta_gen_anonymous_1062anonymous_1050  = 1292,
    1308             :     INT_PTX_SATOM_ADD_u32_cta_gen_anonymous_1062anonymous_1051  = 1293,
    1309             :     INT_PTX_SATOM_ADD_u32_cta_gen_anonymous_1062anonymous_1052  = 1294,
    1310             :     INT_PTX_SATOM_ADD_u32_cta_gen_anonymous_1062anonymous_1053  = 1295,
    1311             :     INT_PTX_SATOM_ADD_u32_sys_gen_anonymous_1062anonymous_1050  = 1296,
    1312             :     INT_PTX_SATOM_ADD_u32_sys_gen_anonymous_1062anonymous_1051  = 1297,
    1313             :     INT_PTX_SATOM_ADD_u32_sys_gen_anonymous_1062anonymous_1052  = 1298,
    1314             :     INT_PTX_SATOM_ADD_u32_sys_gen_anonymous_1062anonymous_1053  = 1299,
    1315             :     INT_PTX_SATOM_ADD_u64_cta_gen_anonymous_1062anonymous_1050  = 1300,
    1316             :     INT_PTX_SATOM_ADD_u64_cta_gen_anonymous_1062anonymous_1051  = 1301,
    1317             :     INT_PTX_SATOM_ADD_u64_cta_gen_anonymous_1062anonymous_1052  = 1302,
    1318             :     INT_PTX_SATOM_ADD_u64_cta_gen_anonymous_1062anonymous_1053  = 1303,
    1319             :     INT_PTX_SATOM_ADD_u64_sys_gen_anonymous_1062anonymous_1050  = 1304,
    1320             :     INT_PTX_SATOM_ADD_u64_sys_gen_anonymous_1062anonymous_1051  = 1305,
    1321             :     INT_PTX_SATOM_ADD_u64_sys_gen_anonymous_1062anonymous_1052  = 1306,
    1322             :     INT_PTX_SATOM_ADD_u64_sys_gen_anonymous_1062anonymous_1053  = 1307,
    1323             :     INT_PTX_SATOM_AND_b32_cta_gen_anonymous_1062anonymous_1050  = 1308,
    1324             :     INT_PTX_SATOM_AND_b32_cta_gen_anonymous_1062anonymous_1051  = 1309,
    1325             :     INT_PTX_SATOM_AND_b32_cta_gen_anonymous_1062anonymous_1052  = 1310,
    1326             :     INT_PTX_SATOM_AND_b32_cta_gen_anonymous_1062anonymous_1053  = 1311,
    1327             :     INT_PTX_SATOM_AND_b32_sys_gen_anonymous_1062anonymous_1050  = 1312,
    1328             :     INT_PTX_SATOM_AND_b32_sys_gen_anonymous_1062anonymous_1051  = 1313,
    1329             :     INT_PTX_SATOM_AND_b32_sys_gen_anonymous_1062anonymous_1052  = 1314,
    1330             :     INT_PTX_SATOM_AND_b32_sys_gen_anonymous_1062anonymous_1053  = 1315,
    1331             :     INT_PTX_SATOM_AND_b64_cta_gen_anonymous_1062anonymous_1050  = 1316,
    1332             :     INT_PTX_SATOM_AND_b64_cta_gen_anonymous_1062anonymous_1051  = 1317,
    1333             :     INT_PTX_SATOM_AND_b64_cta_gen_anonymous_1062anonymous_1052  = 1318,
    1334             :     INT_PTX_SATOM_AND_b64_cta_gen_anonymous_1062anonymous_1053  = 1319,
    1335             :     INT_PTX_SATOM_AND_b64_sys_gen_anonymous_1062anonymous_1050  = 1320,
    1336             :     INT_PTX_SATOM_AND_b64_sys_gen_anonymous_1062anonymous_1051  = 1321,
    1337             :     INT_PTX_SATOM_AND_b64_sys_gen_anonymous_1062anonymous_1052  = 1322,
    1338             :     INT_PTX_SATOM_AND_b64_sys_gen_anonymous_1062anonymous_1053  = 1323,
    1339             :     INT_PTX_SATOM_CAS_b32_cta_gen_anonymous_1063anonymous_1054  = 1324,
    1340             :     INT_PTX_SATOM_CAS_b32_cta_gen_anonymous_1063anonymous_1055  = 1325,
    1341             :     INT_PTX_SATOM_CAS_b32_cta_gen_anonymous_1063anonymous_1056  = 1326,
    1342             :     INT_PTX_SATOM_CAS_b32_cta_gen_anonymous_1063anonymous_1057  = 1327,
    1343             :     INT_PTX_SATOM_CAS_b32_cta_gen_anonymous_1063anonymous_1058  = 1328,
    1344             :     INT_PTX_SATOM_CAS_b32_cta_gen_anonymous_1063anonymous_1059  = 1329,
    1345             :     INT_PTX_SATOM_CAS_b32_cta_gen_anonymous_1063anonymous_1060  = 1330,
    1346             :     INT_PTX_SATOM_CAS_b32_cta_gen_anonymous_1063anonymous_1061  = 1331,
    1347             :     INT_PTX_SATOM_CAS_b32_sys_gen_anonymous_1063anonymous_1054  = 1332,
    1348             :     INT_PTX_SATOM_CAS_b32_sys_gen_anonymous_1063anonymous_1055  = 1333,
    1349             :     INT_PTX_SATOM_CAS_b32_sys_gen_anonymous_1063anonymous_1056  = 1334,
    1350             :     INT_PTX_SATOM_CAS_b32_sys_gen_anonymous_1063anonymous_1057  = 1335,
    1351             :     INT_PTX_SATOM_CAS_b32_sys_gen_anonymous_1063anonymous_1058  = 1336,
    1352             :     INT_PTX_SATOM_CAS_b32_sys_gen_anonymous_1063anonymous_1059  = 1337,
    1353             :     INT_PTX_SATOM_CAS_b32_sys_gen_anonymous_1063anonymous_1060  = 1338,
    1354             :     INT_PTX_SATOM_CAS_b32_sys_gen_anonymous_1063anonymous_1061  = 1339,
    1355             :     INT_PTX_SATOM_CAS_b64_cta_gen_anonymous_1063anonymous_1054  = 1340,
    1356             :     INT_PTX_SATOM_CAS_b64_cta_gen_anonymous_1063anonymous_1055  = 1341,
    1357             :     INT_PTX_SATOM_CAS_b64_cta_gen_anonymous_1063anonymous_1056  = 1342,
    1358             :     INT_PTX_SATOM_CAS_b64_cta_gen_anonymous_1063anonymous_1057  = 1343,
    1359             :     INT_PTX_SATOM_CAS_b64_cta_gen_anonymous_1063anonymous_1058  = 1344,
    1360             :     INT_PTX_SATOM_CAS_b64_cta_gen_anonymous_1063anonymous_1059  = 1345,
    1361             :     INT_PTX_SATOM_CAS_b64_cta_gen_anonymous_1063anonymous_1060  = 1346,
    1362             :     INT_PTX_SATOM_CAS_b64_cta_gen_anonymous_1063anonymous_1061  = 1347,
    1363             :     INT_PTX_SATOM_CAS_b64_sys_gen_anonymous_1063anonymous_1054  = 1348,
    1364             :     INT_PTX_SATOM_CAS_b64_sys_gen_anonymous_1063anonymous_1055  = 1349,
    1365             :     INT_PTX_SATOM_CAS_b64_sys_gen_anonymous_1063anonymous_1056  = 1350,
    1366             :     INT_PTX_SATOM_CAS_b64_sys_gen_anonymous_1063anonymous_1057  = 1351,
    1367             :     INT_PTX_SATOM_CAS_b64_sys_gen_anonymous_1063anonymous_1058  = 1352,
    1368             :     INT_PTX_SATOM_CAS_b64_sys_gen_anonymous_1063anonymous_1059  = 1353,
    1369             :     INT_PTX_SATOM_CAS_b64_sys_gen_anonymous_1063anonymous_1060  = 1354,
    1370             :     INT_PTX_SATOM_CAS_b64_sys_gen_anonymous_1063anonymous_1061  = 1355,
    1371             :     INT_PTX_SATOM_DEC_u32_cta_gen_anonymous_1062anonymous_1050  = 1356,
    1372             :     INT_PTX_SATOM_DEC_u32_cta_gen_anonymous_1062anonymous_1051  = 1357,
    1373             :     INT_PTX_SATOM_DEC_u32_cta_gen_anonymous_1062anonymous_1052  = 1358,
    1374             :     INT_PTX_SATOM_DEC_u32_cta_gen_anonymous_1062anonymous_1053  = 1359,
    1375             :     INT_PTX_SATOM_DEC_u32_sys_gen_anonymous_1062anonymous_1050  = 1360,
    1376             :     INT_PTX_SATOM_DEC_u32_sys_gen_anonymous_1062anonymous_1051  = 1361,
    1377             :     INT_PTX_SATOM_DEC_u32_sys_gen_anonymous_1062anonymous_1052  = 1362,
    1378             :     INT_PTX_SATOM_DEC_u32_sys_gen_anonymous_1062anonymous_1053  = 1363,
    1379             :     INT_PTX_SATOM_EXCH_b32_cta_gen_anonymous_1062anonymous_1050 = 1364,
    1380             :     INT_PTX_SATOM_EXCH_b32_cta_gen_anonymous_1062anonymous_1051 = 1365,
    1381             :     INT_PTX_SATOM_EXCH_b32_cta_gen_anonymous_1062anonymous_1052 = 1366,
    1382             :     INT_PTX_SATOM_EXCH_b32_cta_gen_anonymous_1062anonymous_1053 = 1367,
    1383             :     INT_PTX_SATOM_EXCH_b32_sys_gen_anonymous_1062anonymous_1050 = 1368,
    1384             :     INT_PTX_SATOM_EXCH_b32_sys_gen_anonymous_1062anonymous_1051 = 1369,
    1385             :     INT_PTX_SATOM_EXCH_b32_sys_gen_anonymous_1062anonymous_1052 = 1370,
    1386             :     INT_PTX_SATOM_EXCH_b32_sys_gen_anonymous_1062anonymous_1053 = 1371,
    1387             :     INT_PTX_SATOM_EXCH_b64_cta_gen_anonymous_1062anonymous_1050 = 1372,
    1388             :     INT_PTX_SATOM_EXCH_b64_cta_gen_anonymous_1062anonymous_1051 = 1373,
    1389             :     INT_PTX_SATOM_EXCH_b64_cta_gen_anonymous_1062anonymous_1052 = 1374,
    1390             :     INT_PTX_SATOM_EXCH_b64_cta_gen_anonymous_1062anonymous_1053 = 1375,
    1391             :     INT_PTX_SATOM_EXCH_b64_sys_gen_anonymous_1062anonymous_1050 = 1376,
    1392             :     INT_PTX_SATOM_EXCH_b64_sys_gen_anonymous_1062anonymous_1051 = 1377,
    1393             :     INT_PTX_SATOM_EXCH_b64_sys_gen_anonymous_1062anonymous_1052 = 1378,
    1394             :     INT_PTX_SATOM_EXCH_b64_sys_gen_anonymous_1062anonymous_1053 = 1379,
    1395             :     INT_PTX_SATOM_INC_u32_cta_gen_anonymous_1062anonymous_1050  = 1380,
    1396             :     INT_PTX_SATOM_INC_u32_cta_gen_anonymous_1062anonymous_1051  = 1381,
    1397             :     INT_PTX_SATOM_INC_u32_cta_gen_anonymous_1062anonymous_1052  = 1382,
    1398             :     INT_PTX_SATOM_INC_u32_cta_gen_anonymous_1062anonymous_1053  = 1383,
    1399             :     INT_PTX_SATOM_INC_u32_sys_gen_anonymous_1062anonymous_1050  = 1384,
    1400             :     INT_PTX_SATOM_INC_u32_sys_gen_anonymous_1062anonymous_1051  = 1385,
    1401             :     INT_PTX_SATOM_INC_u32_sys_gen_anonymous_1062anonymous_1052  = 1386,
    1402             :     INT_PTX_SATOM_INC_u32_sys_gen_anonymous_1062anonymous_1053  = 1387,
    1403             :     INT_PTX_SATOM_MAX_s32_cta_gen_anonymous_1062anonymous_1050  = 1388,
    1404             :     INT_PTX_SATOM_MAX_s32_cta_gen_anonymous_1062anonymous_1051  = 1389,
    1405             :     INT_PTX_SATOM_MAX_s32_cta_gen_anonymous_1062anonymous_1052  = 1390,
    1406             :     INT_PTX_SATOM_MAX_s32_cta_gen_anonymous_1062anonymous_1053  = 1391,
    1407             :     INT_PTX_SATOM_MAX_s32_sys_gen_anonymous_1062anonymous_1050  = 1392,
    1408             :     INT_PTX_SATOM_MAX_s32_sys_gen_anonymous_1062anonymous_1051  = 1393,
    1409             :     INT_PTX_SATOM_MAX_s32_sys_gen_anonymous_1062anonymous_1052  = 1394,
    1410             :     INT_PTX_SATOM_MAX_s32_sys_gen_anonymous_1062anonymous_1053  = 1395,
    1411             :     INT_PTX_SATOM_MAX_s64_cta_gen_anonymous_1062anonymous_1050  = 1396,
    1412             :     INT_PTX_SATOM_MAX_s64_cta_gen_anonymous_1062anonymous_1051  = 1397,
    1413             :     INT_PTX_SATOM_MAX_s64_cta_gen_anonymous_1062anonymous_1052  = 1398,
    1414             :     INT_PTX_SATOM_MAX_s64_cta_gen_anonymous_1062anonymous_1053  = 1399,
    1415             :     INT_PTX_SATOM_MAX_s64_sys_gen_anonymous_1062anonymous_1050  = 1400,
    1416             :     INT_PTX_SATOM_MAX_s64_sys_gen_anonymous_1062anonymous_1051  = 1401,
    1417             :     INT_PTX_SATOM_MAX_s64_sys_gen_anonymous_1062anonymous_1052  = 1402,
    1418             :     INT_PTX_SATOM_MAX_s64_sys_gen_anonymous_1062anonymous_1053  = 1403,
    1419             :     INT_PTX_SATOM_MAX_u32_cta_gen_anonymous_1062anonymous_1050  = 1404,
    1420             :     INT_PTX_SATOM_MAX_u32_cta_gen_anonymous_1062anonymous_1051  = 1405,
    1421             :     INT_PTX_SATOM_MAX_u32_cta_gen_anonymous_1062anonymous_1052  = 1406,
    1422             :     INT_PTX_SATOM_MAX_u32_cta_gen_anonymous_1062anonymous_1053  = 1407,
    1423             :     INT_PTX_SATOM_MAX_u32_sys_gen_anonymous_1062anonymous_1050  = 1408,
    1424             :     INT_PTX_SATOM_MAX_u32_sys_gen_anonymous_1062anonymous_1051  = 1409,
    1425             :     INT_PTX_SATOM_MAX_u32_sys_gen_anonymous_1062anonymous_1052  = 1410,
    1426             :     INT_PTX_SATOM_MAX_u32_sys_gen_anonymous_1062anonymous_1053  = 1411,
    1427             :     INT_PTX_SATOM_MAX_u64_cta_gen_anonymous_1062anonymous_1050  = 1412,
    1428             :     INT_PTX_SATOM_MAX_u64_cta_gen_anonymous_1062anonymous_1051  = 1413,
    1429             :     INT_PTX_SATOM_MAX_u64_cta_gen_anonymous_1062anonymous_1052  = 1414,
    1430             :     INT_PTX_SATOM_MAX_u64_cta_gen_anonymous_1062anonymous_1053  = 1415,
    1431             :     INT_PTX_SATOM_MAX_u64_sys_gen_anonymous_1062anonymous_1050  = 1416,
    1432             :     INT_PTX_SATOM_MAX_u64_sys_gen_anonymous_1062anonymous_1051  = 1417,
    1433             :     INT_PTX_SATOM_MAX_u64_sys_gen_anonymous_1062anonymous_1052  = 1418,
    1434             :     INT_PTX_SATOM_MAX_u64_sys_gen_anonymous_1062anonymous_1053  = 1419,
    1435             :     INT_PTX_SATOM_MIN_s32_cta_gen_anonymous_1062anonymous_1050  = 1420,
    1436             :     INT_PTX_SATOM_MIN_s32_cta_gen_anonymous_1062anonymous_1051  = 1421,
    1437             :     INT_PTX_SATOM_MIN_s32_cta_gen_anonymous_1062anonymous_1052  = 1422,
    1438             :     INT_PTX_SATOM_MIN_s32_cta_gen_anonymous_1062anonymous_1053  = 1423,
    1439             :     INT_PTX_SATOM_MIN_s32_sys_gen_anonymous_1062anonymous_1050  = 1424,
    1440             :     INT_PTX_SATOM_MIN_s32_sys_gen_anonymous_1062anonymous_1051  = 1425,
    1441             :     INT_PTX_SATOM_MIN_s32_sys_gen_anonymous_1062anonymous_1052  = 1426,
    1442             :     INT_PTX_SATOM_MIN_s32_sys_gen_anonymous_1062anonymous_1053  = 1427,
    1443             :     INT_PTX_SATOM_MIN_s64_cta_gen_anonymous_1062anonymous_1050  = 1428,
    1444             :     INT_PTX_SATOM_MIN_s64_cta_gen_anonymous_1062anonymous_1051  = 1429,
    1445             :     INT_PTX_SATOM_MIN_s64_cta_gen_anonymous_1062anonymous_1052  = 1430,
    1446             :     INT_PTX_SATOM_MIN_s64_cta_gen_anonymous_1062anonymous_1053  = 1431,
    1447             :     INT_PTX_SATOM_MIN_s64_sys_gen_anonymous_1062anonymous_1050  = 1432,
    1448             :     INT_PTX_SATOM_MIN_s64_sys_gen_anonymous_1062anonymous_1051  = 1433,
    1449             :     INT_PTX_SATOM_MIN_s64_sys_gen_anonymous_1062anonymous_1052  = 1434,
    1450             :     INT_PTX_SATOM_MIN_s64_sys_gen_anonymous_1062anonymous_1053  = 1435,
    1451             :     INT_PTX_SATOM_MIN_u32_cta_gen_anonymous_1062anonymous_1050  = 1436,
    1452             :     INT_PTX_SATOM_MIN_u32_cta_gen_anonymous_1062anonymous_1051  = 1437,
    1453             :     INT_PTX_SATOM_MIN_u32_cta_gen_anonymous_1062anonymous_1052  = 1438,
    1454             :     INT_PTX_SATOM_MIN_u32_cta_gen_anonymous_1062anonymous_1053  = 1439,
    1455             :     INT_PTX_SATOM_MIN_u32_sys_gen_anonymous_1062anonymous_1050  = 1440,
    1456             :     INT_PTX_SATOM_MIN_u32_sys_gen_anonymous_1062anonymous_1051  = 1441,
    1457             :     INT_PTX_SATOM_MIN_u32_sys_gen_anonymous_1062anonymous_1052  = 1442,
    1458             :     INT_PTX_SATOM_MIN_u32_sys_gen_anonymous_1062anonymous_1053  = 1443,
    1459             :     INT_PTX_SATOM_MIN_u64_cta_gen_anonymous_1062anonymous_1050  = 1444,
    1460             :     INT_PTX_SATOM_MIN_u64_cta_gen_anonymous_1062anonymous_1051  = 1445,
    1461             :     INT_PTX_SATOM_MIN_u64_cta_gen_anonymous_1062anonymous_1052  = 1446,
    1462             :     INT_PTX_SATOM_MIN_u64_cta_gen_anonymous_1062anonymous_1053  = 1447,
    1463             :     INT_PTX_SATOM_MIN_u64_sys_gen_anonymous_1062anonymous_1050  = 1448,
    1464             :     INT_PTX_SATOM_MIN_u64_sys_gen_anonymous_1062anonymous_1051  = 1449,
    1465             :     INT_PTX_SATOM_MIN_u64_sys_gen_anonymous_1062anonymous_1052  = 1450,
    1466             :     INT_PTX_SATOM_MIN_u64_sys_gen_anonymous_1062anonymous_1053  = 1451,
    1467             :     INT_PTX_SATOM_OR_b32_cta_gen_anonymous_1062anonymous_1050   = 1452,
    1468             :     INT_PTX_SATOM_OR_b32_cta_gen_anonymous_1062anonymous_1051   = 1453,
    1469             :     INT_PTX_SATOM_OR_b32_cta_gen_anonymous_1062anonymous_1052   = 1454,
    1470             :     INT_PTX_SATOM_OR_b32_cta_gen_anonymous_1062anonymous_1053   = 1455,
    1471             :     INT_PTX_SATOM_OR_b32_sys_gen_anonymous_1062anonymous_1050   = 1456,
    1472             :     INT_PTX_SATOM_OR_b32_sys_gen_anonymous_1062anonymous_1051   = 1457,
    1473             :     INT_PTX_SATOM_OR_b32_sys_gen_anonymous_1062anonymous_1052   = 1458,
    1474             :     INT_PTX_SATOM_OR_b32_sys_gen_anonymous_1062anonymous_1053   = 1459,
    1475             :     INT_PTX_SATOM_OR_b64_cta_gen_anonymous_1062anonymous_1050   = 1460,
    1476             :     INT_PTX_SATOM_OR_b64_cta_gen_anonymous_1062anonymous_1051   = 1461,
    1477             :     INT_PTX_SATOM_OR_b64_cta_gen_anonymous_1062anonymous_1052   = 1462,
    1478             :     INT_PTX_SATOM_OR_b64_cta_gen_anonymous_1062anonymous_1053   = 1463,
    1479             :     INT_PTX_SATOM_OR_b64_sys_gen_anonymous_1062anonymous_1050   = 1464,
    1480             :     INT_PTX_SATOM_OR_b64_sys_gen_anonymous_1062anonymous_1051   = 1465,
    1481             :     INT_PTX_SATOM_OR_b64_sys_gen_anonymous_1062anonymous_1052   = 1466,
    1482             :     INT_PTX_SATOM_OR_b64_sys_gen_anonymous_1062anonymous_1053   = 1467,
    1483             :     INT_PTX_SATOM_XOR_b32_cta_gen_anonymous_1062anonymous_1050  = 1468,
    1484             :     INT_PTX_SATOM_XOR_b32_cta_gen_anonymous_1062anonymous_1051  = 1469,
    1485             :     INT_PTX_SATOM_XOR_b32_cta_gen_anonymous_1062anonymous_1052  = 1470,
    1486             :     INT_PTX_SATOM_XOR_b32_cta_gen_anonymous_1062anonymous_1053  = 1471,
    1487             :     INT_PTX_SATOM_XOR_b32_sys_gen_anonymous_1062anonymous_1050  = 1472,
    1488             :     INT_PTX_SATOM_XOR_b32_sys_gen_anonymous_1062anonymous_1051  = 1473,
    1489             :     INT_PTX_SATOM_XOR_b32_sys_gen_anonymous_1062anonymous_1052  = 1474,
    1490             :     INT_PTX_SATOM_XOR_b32_sys_gen_anonymous_1062anonymous_1053  = 1475,
    1491             :     INT_PTX_SATOM_XOR_b64_cta_gen_anonymous_1062anonymous_1050  = 1476,
    1492             :     INT_PTX_SATOM_XOR_b64_cta_gen_anonymous_1062anonymous_1051  = 1477,
    1493             :     INT_PTX_SATOM_XOR_b64_cta_gen_anonymous_1062anonymous_1052  = 1478,
    1494             :     INT_PTX_SATOM_XOR_b64_cta_gen_anonymous_1062anonymous_1053  = 1479,
    1495             :     INT_PTX_SATOM_XOR_b64_sys_gen_anonymous_1062anonymous_1050  = 1480,
    1496             :     INT_PTX_SATOM_XOR_b64_sys_gen_anonymous_1062anonymous_1051  = 1481,
    1497             :     INT_PTX_SATOM_XOR_b64_sys_gen_anonymous_1062anonymous_1052  = 1482,
    1498             :     INT_PTX_SATOM_XOR_b64_sys_gen_anonymous_1062anonymous_1053  = 1483,
    1499             :     INT_PTX_SREG_CLOCK  = 1484,
    1500             :     INT_PTX_SREG_CLOCK64        = 1485,
    1501             :     INT_PTX_SREG_CTAID_W        = 1486,
    1502             :     INT_PTX_SREG_CTAID_X        = 1487,
    1503             :     INT_PTX_SREG_CTAID_Y        = 1488,
    1504             :     INT_PTX_SREG_CTAID_Z        = 1489,
    1505             :     INT_PTX_SREG_GRIDID = 1490,
    1506             :     INT_PTX_SREG_LANEID = 1491,
    1507             :     INT_PTX_SREG_LANEMASK_EQ    = 1492,
    1508             :     INT_PTX_SREG_LANEMASK_GE    = 1493,
    1509             :     INT_PTX_SREG_LANEMASK_GT    = 1494,
    1510             :     INT_PTX_SREG_LANEMASK_LE    = 1495,
    1511             :     INT_PTX_SREG_LANEMASK_LT    = 1496,
    1512             :     INT_PTX_SREG_NCTAID_W       = 1497,
    1513             :     INT_PTX_SREG_NCTAID_X       = 1498,
    1514             :     INT_PTX_SREG_NCTAID_Y       = 1499,
    1515             :     INT_PTX_SREG_NCTAID_Z       = 1500,
    1516             :     INT_PTX_SREG_NSMID  = 1501,
    1517             :     INT_PTX_SREG_NTID_W = 1502,
    1518             :     INT_PTX_SREG_NTID_X = 1503,
    1519             :     INT_PTX_SREG_NTID_Y = 1504,
    1520             :     INT_PTX_SREG_NTID_Z = 1505,
    1521             :     INT_PTX_SREG_NWARPID        = 1506,
    1522             :     INT_PTX_SREG_PM0    = 1507,
    1523             :     INT_PTX_SREG_PM1    = 1508,
    1524             :     INT_PTX_SREG_PM2    = 1509,
    1525             :     INT_PTX_SREG_PM3    = 1510,
    1526             :     INT_PTX_SREG_SMID   = 1511,
    1527             :     INT_PTX_SREG_TID_W  = 1512,
    1528             :     INT_PTX_SREG_TID_X  = 1513,
    1529             :     INT_PTX_SREG_TID_Y  = 1514,
    1530             :     INT_PTX_SREG_TID_Z  = 1515,
    1531             :     INT_PTX_SREG_WARPID = 1516,
    1532             :     INT_PTX_SREG_WARPSIZE       = 1517,
    1533             :     INT_SHFL_BFLY_F32imm1       = 1518,
    1534             :     INT_SHFL_BFLY_F32imm2       = 1519,
    1535             :     INT_SHFL_BFLY_F32imm3       = 1520,
    1536             :     INT_SHFL_BFLY_F32reg        = 1521,
    1537             :     INT_SHFL_BFLY_I32imm1       = 1522,
    1538             :     INT_SHFL_BFLY_I32imm2       = 1523,
    1539             :     INT_SHFL_BFLY_I32imm3       = 1524,
    1540             :     INT_SHFL_BFLY_I32reg        = 1525,
    1541             :     INT_SHFL_DOWN_F32imm1       = 1526,
    1542             :     INT_SHFL_DOWN_F32imm2       = 1527,
    1543             :     INT_SHFL_DOWN_F32imm3       = 1528,
    1544             :     INT_SHFL_DOWN_F32reg        = 1529,
    1545             :     INT_SHFL_DOWN_I32imm1       = 1530,
    1546             :     INT_SHFL_DOWN_I32imm2       = 1531,
    1547             :     INT_SHFL_DOWN_I32imm3       = 1532,
    1548             :     INT_SHFL_DOWN_I32reg        = 1533,
    1549             :     INT_SHFL_IDX_F32imm1        = 1534,
    1550             :     INT_SHFL_IDX_F32imm2        = 1535,
    1551             :     INT_SHFL_IDX_F32imm3        = 1536,
    1552             :     INT_SHFL_IDX_F32reg = 1537,
    1553             :     INT_SHFL_IDX_I32imm1        = 1538,
    1554             :     INT_SHFL_IDX_I32imm2        = 1539,
    1555             :     INT_SHFL_IDX_I32imm3        = 1540,
    1556             :     INT_SHFL_IDX_I32reg = 1541,
    1557             :     INT_SHFL_UP_F32imm1 = 1542,
    1558             :     INT_SHFL_UP_F32imm2 = 1543,
    1559             :     INT_SHFL_UP_F32imm3 = 1544,
    1560             :     INT_SHFL_UP_F32reg  = 1545,
    1561             :     INT_SHFL_UP_I32imm1 = 1546,
    1562             :     INT_SHFL_UP_I32imm2 = 1547,
    1563             :     INT_SHFL_UP_I32imm3 = 1548,
    1564             :     INT_SHFL_UP_I32reg  = 1549,
    1565             :     ISSPACEP_CONST_32   = 1550,
    1566             :     ISSPACEP_CONST_64   = 1551,
    1567             :     ISSPACEP_GLOBAL_32  = 1552,
    1568             :     ISSPACEP_GLOBAL_64  = 1553,
    1569             :     ISSPACEP_LOCAL_32   = 1554,
    1570             :     ISSPACEP_LOCAL_64   = 1555,
    1571             :     ISSPACEP_SHARED_32  = 1556,
    1572             :     ISSPACEP_SHARED_64  = 1557,
    1573             :     ISTYPEP_SAMPLER     = 1558,
    1574             :     ISTYPEP_SURFACE     = 1559,
    1575             :     ISTYPEP_TEXTURE     = 1560,
    1576             :     LDV_f16_v2_areg     = 1561,
    1577             :     LDV_f16_v2_areg_64  = 1562,
    1578             :     LDV_f16_v2_ari      = 1563,
    1579             :     LDV_f16_v2_ari_64   = 1564,
    1580             :     LDV_f16_v2_asi      = 1565,
    1581             :     LDV_f16_v2_avar     = 1566,
    1582             :     LDV_f16_v4_areg     = 1567,
    1583             :     LDV_f16_v4_areg_64  = 1568,
    1584             :     LDV_f16_v4_ari      = 1569,
    1585             :     LDV_f16_v4_ari_64   = 1570,
    1586             :     LDV_f16_v4_asi      = 1571,
    1587             :     LDV_f16_v4_avar     = 1572,
    1588             :     LDV_f16x2_v2_areg   = 1573,
    1589             :     LDV_f16x2_v2_areg_64        = 1574,
    1590             :     LDV_f16x2_v2_ari    = 1575,
    1591             :     LDV_f16x2_v2_ari_64 = 1576,
    1592             :     LDV_f16x2_v2_asi    = 1577,
    1593             :     LDV_f16x2_v2_avar   = 1578,
    1594             :     LDV_f16x2_v4_areg   = 1579,
    1595             :     LDV_f16x2_v4_areg_64        = 1580,
    1596             :     LDV_f16x2_v4_ari    = 1581,
    1597             :     LDV_f16x2_v4_ari_64 = 1582,
    1598             :     LDV_f16x2_v4_asi    = 1583,
    1599             :     LDV_f16x2_v4_avar   = 1584,
    1600             :     LDV_f32_v2_areg     = 1585,
    1601             :     LDV_f32_v2_areg_64  = 1586,
    1602             :     LDV_f32_v2_ari      = 1587,
    1603             :     LDV_f32_v2_ari_64   = 1588,
    1604             :     LDV_f32_v2_asi      = 1589,
    1605             :     LDV_f32_v2_avar     = 1590,
    1606             :     LDV_f32_v4_areg     = 1591,
    1607             :     LDV_f32_v4_areg_64  = 1592,
    1608             :     LDV_f32_v4_ari      = 1593,
    1609             :     LDV_f32_v4_ari_64   = 1594,
    1610             :     LDV_f32_v4_asi      = 1595,
    1611             :     LDV_f32_v4_avar     = 1596,
    1612             :     LDV_f64_v2_areg     = 1597,
    1613             :     LDV_f64_v2_areg_64  = 1598,
    1614             :     LDV_f64_v2_ari      = 1599,
    1615             :     LDV_f64_v2_ari_64   = 1600,
    1616             :     LDV_f64_v2_asi      = 1601,
    1617             :     LDV_f64_v2_avar     = 1602,
    1618             :     LDV_f64_v4_areg     = 1603,
    1619             :     LDV_f64_v4_areg_64  = 1604,
    1620             :     LDV_f64_v4_ari      = 1605,
    1621             :     LDV_f64_v4_ari_64   = 1606,
    1622             :     LDV_f64_v4_asi      = 1607,
    1623             :     LDV_f64_v4_avar     = 1608,
    1624             :     LDV_i16_v2_areg     = 1609,
    1625             :     LDV_i16_v2_areg_64  = 1610,
    1626             :     LDV_i16_v2_ari      = 1611,
    1627             :     LDV_i16_v2_ari_64   = 1612,
    1628             :     LDV_i16_v2_asi      = 1613,
    1629             :     LDV_i16_v2_avar     = 1614,
    1630             :     LDV_i16_v4_areg     = 1615,
    1631             :     LDV_i16_v4_areg_64  = 1616,
    1632             :     LDV_i16_v4_ari      = 1617,
    1633             :     LDV_i16_v4_ari_64   = 1618,
    1634             :     LDV_i16_v4_asi      = 1619,
    1635             :     LDV_i16_v4_avar     = 1620,
    1636             :     LDV_i32_v2_areg     = 1621,
    1637             :     LDV_i32_v2_areg_64  = 1622,
    1638             :     LDV_i32_v2_ari      = 1623,
    1639             :     LDV_i32_v2_ari_64   = 1624,
    1640             :     LDV_i32_v2_asi      = 1625,
    1641             :     LDV_i32_v2_avar     = 1626,
    1642             :     LDV_i32_v4_areg     = 1627,
    1643             :     LDV_i32_v4_areg_64  = 1628,
    1644             :     LDV_i32_v4_ari      = 1629,
    1645             :     LDV_i32_v4_ari_64   = 1630,
    1646             :     LDV_i32_v4_asi      = 1631,
    1647             :     LDV_i32_v4_avar     = 1632,
    1648             :     LDV_i64_v2_areg     = 1633,
    1649             :     LDV_i64_v2_areg_64  = 1634,
    1650             :     LDV_i64_v2_ari      = 1635,
    1651             :     LDV_i64_v2_ari_64   = 1636,
    1652             :     LDV_i64_v2_asi      = 1637,
    1653             :     LDV_i64_v2_avar     = 1638,
    1654             :     LDV_i64_v4_areg     = 1639,
    1655             :     LDV_i64_v4_areg_64  = 1640,
    1656             :     LDV_i64_v4_ari      = 1641,
    1657             :     LDV_i64_v4_ari_64   = 1642,
    1658             :     LDV_i64_v4_asi      = 1643,
    1659             :     LDV_i64_v4_avar     = 1644,
    1660             :     LDV_i8_v2_areg      = 1645,
    1661             :     LDV_i8_v2_areg_64   = 1646,
    1662             :     LDV_i8_v2_ari       = 1647,
    1663             :     LDV_i8_v2_ari_64    = 1648,
    1664             :     LDV_i8_v2_asi       = 1649,
    1665             :     LDV_i8_v2_avar      = 1650,
    1666             :     LDV_i8_v4_areg      = 1651,
    1667             :     LDV_i8_v4_areg_64   = 1652,
    1668             :     LDV_i8_v4_ari       = 1653,
    1669             :     LDV_i8_v4_ari_64    = 1654,
    1670             :     LDV_i8_v4_asi       = 1655,
    1671             :     LDV_i8_v4_avar      = 1656,
    1672             :     LD_f16_areg = 1657,
    1673             :     LD_f16_areg_64      = 1658,
    1674             :     LD_f16_ari  = 1659,
    1675             :     LD_f16_ari_64       = 1660,
    1676             :     LD_f16_asi  = 1661,
    1677             :     LD_f16_avar = 1662,
    1678             :     LD_f16x2_areg       = 1663,
    1679             :     LD_f16x2_areg_64    = 1664,
    1680             :     LD_f16x2_ari        = 1665,
    1681             :     LD_f16x2_ari_64     = 1666,
    1682             :     LD_f16x2_asi        = 1667,
    1683             :     LD_f16x2_avar       = 1668,
    1684             :     LD_f32_areg = 1669,
    1685             :     LD_f32_areg_64      = 1670,
    1686             :     LD_f32_ari  = 1671,
    1687             :     LD_f32_ari_64       = 1672,
    1688             :     LD_f32_asi  = 1673,
    1689             :     LD_f32_avar = 1674,
    1690             :     LD_f64_areg = 1675,
    1691             :     LD_f64_areg_64      = 1676,
    1692             :     LD_f64_ari  = 1677,
    1693             :     LD_f64_ari_64       = 1678,
    1694             :     LD_f64_asi  = 1679,
    1695             :     LD_f64_avar = 1680,
    1696             :     LD_i16_areg = 1681,
    1697             :     LD_i16_areg_64      = 1682,
    1698             :     LD_i16_ari  = 1683,
    1699             :     LD_i16_ari_64       = 1684,
    1700             :     LD_i16_asi  = 1685,
    1701             :     LD_i16_avar = 1686,
    1702             :     LD_i32_areg = 1687,
    1703             :     LD_i32_areg_64      = 1688,
    1704             :     LD_i32_ari  = 1689,
    1705             :     LD_i32_ari_64       = 1690,
    1706             :     LD_i32_asi  = 1691,
    1707             :     LD_i32_avar = 1692,
    1708             :     LD_i64_areg = 1693,
    1709             :     LD_i64_areg_64      = 1694,
    1710             :     LD_i64_ari  = 1695,
    1711             :     LD_i64_ari_64       = 1696,
    1712             :     LD_i64_asi  = 1697,
    1713             :     LD_i64_avar = 1698,
    1714             :     LD_i8_areg  = 1699,
    1715             :     LD_i8_areg_64       = 1700,
    1716             :     LD_i8_ari   = 1701,
    1717             :     LD_i8_ari_64        = 1702,
    1718             :     LD_i8_asi   = 1703,
    1719             :     LD_i8_avar  = 1704,
    1720             :     LEA_ADDRi   = 1705,
    1721             :     LEA_ADDRi64 = 1706,
    1722             :     LOAD_CONST_F16      = 1707,
    1723             :     LastCallArgF32      = 1708,
    1724             :     LastCallArgF64      = 1709,
    1725             :     LastCallArgI16      = 1710,
    1726             :     LastCallArgI32      = 1711,
    1727             :     LastCallArgI32imm   = 1712,
    1728             :     LastCallArgI64      = 1713,
    1729             :     LastCallArgParam    = 1714,
    1730             :     LoadParamMemF16     = 1715,
    1731             :     LoadParamMemF16x2   = 1716,
    1732             :     LoadParamMemF32     = 1717,
    1733             :     LoadParamMemF64     = 1718,
    1734             :     LoadParamMemI16     = 1719,
    1735             :     LoadParamMemI32     = 1720,
    1736             :     LoadParamMemI64     = 1721,
    1737             :     LoadParamMemI8      = 1722,
    1738             :     LoadParamMemV2F16   = 1723,
    1739             :     LoadParamMemV2F16x2 = 1724,
    1740             :     LoadParamMemV2F32   = 1725,
    1741             :     LoadParamMemV2F64   = 1726,
    1742             :     LoadParamMemV2I16   = 1727,
    1743             :     LoadParamMemV2I32   = 1728,
    1744             :     LoadParamMemV2I64   = 1729,
    1745             :     LoadParamMemV2I8    = 1730,
    1746             :     LoadParamMemV4F16   = 1731,
    1747             :     LoadParamMemV4F16x2 = 1732,
    1748             :     LoadParamMemV4F32   = 1733,
    1749             :     LoadParamMemV4I16   = 1734,
    1750             :     LoadParamMemV4I32   = 1735,
    1751             :     LoadParamMemV4I8    = 1736,
    1752             :     MAD16rii    = 1737,
    1753             :     MAD16rir    = 1738,
    1754             :     MAD16rri    = 1739,
    1755             :     MAD16rrr    = 1740,
    1756             :     MAD32rii    = 1741,
    1757             :     MAD32rir    = 1742,
    1758             :     MAD32rri    = 1743,
    1759             :     MAD32rrr    = 1744,
    1760             :     MAD64rii    = 1745,
    1761             :     MAD64rir    = 1746,
    1762             :     MAD64rri    = 1747,
    1763             :     MAD64rrr    = 1748,
    1764             :     MOV_ADDR    = 1749,
    1765             :     MOV_ADDR64  = 1750,
    1766             :     MOV_DEPOT_ADDR      = 1751,
    1767             :     MOV_DEPOT_ADDR_64   = 1752,
    1768             :     MOV_SPECIAL = 1753,
    1769             :     MULTHSi16ri = 1754,
    1770             :     MULTHSi16rr = 1755,
    1771             :     MULTHSi32ri = 1756,
    1772             :     MULTHSi32rr = 1757,
    1773             :     MULTHSi64ri = 1758,
    1774             :     MULTHSi64rr = 1759,
    1775             :     MULTHUi16ri = 1760,
    1776             :     MULTHUi16rr = 1761,
    1777             :     MULTHUi32ri = 1762,
    1778             :     MULTHUi32rr = 1763,
    1779             :     MULTHUi64ri = 1764,
    1780             :     MULTHUi64rr = 1765,
    1781             :     MULTi16ri   = 1766,
    1782             :     MULTi16rr   = 1767,
    1783             :     MULTi32ri   = 1768,
    1784             :     MULTi32rr   = 1769,
    1785             :     MULTi64ri   = 1770,
    1786             :     MULTi64rr   = 1771,
    1787             :     MULWIDES32  = 1772,
    1788             :     MULWIDES32Imm       = 1773,
    1789             :     MULWIDES32Imm32     = 1774,
    1790             :     MULWIDES64  = 1775,
    1791             :     MULWIDES64Imm       = 1776,
    1792             :     MULWIDES64Imm64     = 1777,
    1793             :     MULWIDEU32  = 1778,
    1794             :     MULWIDEU32Imm       = 1779,
    1795             :     MULWIDEU32Imm32     = 1780,
    1796             :     MULWIDEU64  = 1781,
    1797             :     MULWIDEU64Imm       = 1782,
    1798             :     MULWIDEU64Imm64     = 1783,
    1799             :     MoveParamF16        = 1784,
    1800             :     MoveParamF32        = 1785,
    1801             :     MoveParamF64        = 1786,
    1802             :     MoveParamI16        = 1787,
    1803             :     MoveParamI32        = 1788,
    1804             :     MoveParamI64        = 1789,
    1805             :     NOP = 1790,
    1806             :     NOT1        = 1791,
    1807             :     NOT16       = 1792,
    1808             :     NOT32       = 1793,
    1809             :     NOT64       = 1794,
    1810             :     ORb16ri     = 1795,
    1811             :     ORb16rr     = 1796,
    1812             :     ORb1ri      = 1797,
    1813             :     ORb1rr      = 1798,
    1814             :     ORb32ri     = 1799,
    1815             :     ORb32rr     = 1800,
    1816             :     ORb64ri     = 1801,
    1817             :     ORb64rr     = 1802,
    1818             :     PACK_TWO_INT32      = 1803,
    1819             :     POPCr32     = 1804,
    1820             :     POPCr64     = 1805,
    1821             :     PrototypeInst       = 1806,
    1822             :     PseudoUseParamF32   = 1807,
    1823             :     PseudoUseParamF64   = 1808,
    1824             :     PseudoUseParamI16   = 1809,
    1825             :     PseudoUseParamI32   = 1810,
    1826             :     PseudoUseParamI64   = 1811,
    1827             :     RETURNInst  = 1812,
    1828             :     ROT32imm_sw = 1813,
    1829             :     ROT64imm_sw = 1814,
    1830             :     ROTATE_B32_HW_IMM   = 1815,
    1831             :     ROTATE_B32_HW_REG   = 1816,
    1832             :     ROTL32imm_hw        = 1817,
    1833             :     ROTL32reg_hw        = 1818,
    1834             :     ROTL32reg_sw        = 1819,
    1835             :     ROTL64reg_sw        = 1820,
    1836             :     ROTR32imm_hw        = 1821,
    1837             :     ROTR32reg_hw        = 1822,
    1838             :     ROTR32reg_sw        = 1823,
    1839             :     ROTR64reg_sw        = 1824,
    1840             :     Return      = 1825,
    1841             :     SDIVi16ri   = 1826,
    1842             :     SDIVi16rr   = 1827,
    1843             :     SDIVi32ri   = 1828,
    1844             :     SDIVi32rr   = 1829,
    1845             :     SDIVi64ri   = 1830,
    1846             :     SDIVi64rr   = 1831,
    1847             :     SELP_b16ii  = 1832,
    1848             :     SELP_b16ir  = 1833,
    1849             :     SELP_b16ri  = 1834,
    1850             :     SELP_b16rr  = 1835,
    1851             :     SELP_b32ii  = 1836,
    1852             :     SELP_b32ir  = 1837,
    1853             :     SELP_b32ri  = 1838,
    1854             :     SELP_b32rr  = 1839,
    1855             :     SELP_b64ii  = 1840,
    1856             :     SELP_b64ir  = 1841,
    1857             :     SELP_b64ri  = 1842,
    1858             :     SELP_b64rr  = 1843,
    1859             :     SELP_f16ii  = 1844,
    1860             :     SELP_f16ir  = 1845,
    1861             :     SELP_f16ri  = 1846,
    1862             :     SELP_f16rr  = 1847,
    1863             :     SELP_f16x2rr        = 1848,
    1864             :     SELP_f32ii  = 1849,
    1865             :     SELP_f32ir  = 1850,
    1866             :     SELP_f32ri  = 1851,
    1867             :     SELP_f32rr  = 1852,
    1868             :     SELP_f64ii  = 1853,
    1869             :     SELP_f64ir  = 1854,
    1870             :     SELP_f64ri  = 1855,
    1871             :     SELP_f64rr  = 1856,
    1872             :     SELP_s16ii  = 1857,
    1873             :     SELP_s16ir  = 1858,
    1874             :     SELP_s16ri  = 1859,
    1875             :     SELP_s16rr  = 1860,
    1876             :     SELP_s32ii  = 1861,
    1877             :     SELP_s32ir  = 1862,
    1878             :     SELP_s32ri  = 1863,
    1879             :     SELP_s32rr  = 1864,
    1880             :     SELP_s64ii  = 1865,
    1881             :     SELP_s64ir  = 1866,
    1882             :     SELP_s64ri  = 1867,
    1883             :     SELP_s64rr  = 1868,
    1884             :     SELP_u16ii  = 1869,
    1885             :     SELP_u16ir  = 1870,
    1886             :     SELP_u16ri  = 1871,
    1887             :     SELP_u16rr  = 1872,
    1888             :     SELP_u32ii  = 1873,
    1889             :     SELP_u32ir  = 1874,
    1890             :     SELP_u32ri  = 1875,
    1891             :     SELP_u32rr  = 1876,
    1892             :     SELP_u64ii  = 1877,
    1893             :     SELP_u64ir  = 1878,
    1894             :     SELP_u64ri  = 1879,
    1895             :     SELP_u64rr  = 1880,
    1896             :     SETP_b16ir  = 1881,
    1897             :     SETP_b16ri  = 1882,
    1898             :     SETP_b16rr  = 1883,
    1899             :     SETP_b32ir  = 1884,
    1900             :     SETP_b32ri  = 1885,
    1901             :     SETP_b32rr  = 1886,
    1902             :     SETP_b64ir  = 1887,
    1903             :     SETP_b64ri  = 1888,
    1904             :     SETP_b64rr  = 1889,
    1905             :     SETP_f16rr  = 1890,
    1906             :     SETP_f16x2rr        = 1891,
    1907             :     SETP_f32ir  = 1892,
    1908             :     SETP_f32ri  = 1893,
    1909             :     SETP_f32rr  = 1894,
    1910             :     SETP_f64ir  = 1895,
    1911             :     SETP_f64ri  = 1896,
    1912             :     SETP_f64rr  = 1897,
    1913             :     SETP_s16ir  = 1898,
    1914             :     SETP_s16ri  = 1899,
    1915             :     SETP_s16rr  = 1900,
    1916             :     SETP_s32ir  = 1901,
    1917             :     SETP_s32ri  = 1902,
    1918             :     SETP_s32rr  = 1903,
    1919             :     SETP_s64ir  = 1904,
    1920             :     SETP_s64ri  = 1905,
    1921             :     SETP_s64rr  = 1906,
    1922             :     SETP_u16ir  = 1907,
    1923             :     SETP_u16ri  = 1908,
    1924             :     SETP_u16rr  = 1909,
    1925             :     SETP_u32ir  = 1910,
    1926             :     SETP_u32ri  = 1911,
    1927             :     SETP_u32rr  = 1912,
    1928             :     SETP_u64ir  = 1913,
    1929             :     SETP_u64ri  = 1914,
    1930             :     SETP_u64rr  = 1915,
    1931             :     SET_b16ir   = 1916,
    1932             :     SET_b16ri   = 1917,
    1933             :     SET_b16rr   = 1918,
    1934             :     SET_b32ir   = 1919,
    1935             :     SET_b32ri   = 1920,
    1936             :     SET_b32rr   = 1921,
    1937             :     SET_b64ir   = 1922,
    1938             :     SET_b64ri   = 1923,
    1939             :     SET_b64rr   = 1924,
    1940             :     SET_f16ir   = 1925,
    1941             :     SET_f16ri   = 1926,
    1942             :     SET_f16rr   = 1927,
    1943             :     SET_f32ir   = 1928,
    1944             :     SET_f32ri   = 1929,
    1945             :     SET_f32rr   = 1930,
    1946             :     SET_f64ir   = 1931,
    1947             :     SET_f64ri   = 1932,
    1948             :     SET_f64rr   = 1933,
    1949             :     SET_s16ir   = 1934,
    1950             :     SET_s16ri   = 1935,
    1951             :     SET_s16rr   = 1936,
    1952             :     SET_s32ir   = 1937,
    1953             :     SET_s32ri   = 1938,
    1954             :     SET_s32rr   = 1939,
    1955             :     SET_s64ir   = 1940,
    1956             :     SET_s64ri   = 1941,
    1957             :     SET_s64rr   = 1942,
    1958             :     SET_u16ir   = 1943,
    1959             :     SET_u16ri   = 1944,
    1960             :     SET_u16rr   = 1945,
    1961             :     SET_u32ir   = 1946,
    1962             :     SET_u32ri   = 1947,
    1963             :     SET_u32rr   = 1948,
    1964             :     SET_u64ir   = 1949,
    1965             :     SET_u64ri   = 1950,
    1966             :     SET_u64rr   = 1951,
    1967             :     SHF_L_WRAP_B32_IMM  = 1952,
    1968             :     SHF_L_WRAP_B32_REG  = 1953,
    1969             :     SHF_R_WRAP_B32_IMM  = 1954,
    1970             :     SHF_R_WRAP_B32_REG  = 1955,
    1971             :     SHLi16ri    = 1956,
    1972             :     SHLi16rr    = 1957,
    1973             :     SHLi32ii    = 1958,
    1974             :     SHLi32ri    = 1959,
    1975             :     SHLi32rr    = 1960,
    1976             :     SHLi64ri    = 1961,
    1977             :     SHLi64rr    = 1962,
    1978             :     SINF        = 1963,
    1979             :     SMAXi16ri   = 1964,
    1980             :     SMAXi16rr   = 1965,
    1981             :     SMAXi32ri   = 1966,
    1982             :     SMAXi32rr   = 1967,
    1983             :     SMAXi64ri   = 1968,
    1984             :     SMAXi64rr   = 1969,
    1985             :     SMINi16ri   = 1970,
    1986             :     SMINi16rr   = 1971,
    1987             :     SMINi32ri   = 1972,
    1988             :     SMINi32rr   = 1973,
    1989             :     SMINi64ri   = 1974,
    1990             :     SMINi64rr   = 1975,
    1991             :     SRAi16ri    = 1976,
    1992             :     SRAi16rr    = 1977,
    1993             :     SRAi32ii    = 1978,
    1994             :     SRAi32ri    = 1979,
    1995             :     SRAi32rr    = 1980,
    1996             :     SRAi64ri    = 1981,
    1997             :     SRAi64rr    = 1982,
    1998             :     SREMi16ri   = 1983,
    1999             :     SREMi16rr   = 1984,
    2000             :     SREMi32ri   = 1985,
    2001             :     SREMi32rr   = 1986,
    2002             :     SREMi64ri   = 1987,
    2003             :     SREMi64rr   = 1988,
    2004             :     SRLi16ri    = 1989,
    2005             :     SRLi16rr    = 1990,
    2006             :     SRLi32ii    = 1991,
    2007             :     SRLi32ri    = 1992,
    2008             :     SRLi32rr    = 1993,
    2009             :     SRLi64ri    = 1994,
    2010             :     SRLi64rr    = 1995,
    2011             :     STV_f16_v2_areg     = 1996,
    2012             :     STV_f16_v2_areg_64  = 1997,
    2013             :     STV_f16_v2_ari      = 1998,
    2014             :     STV_f16_v2_ari_64   = 1999,
    2015             :     STV_f16_v2_asi      = 2000,
    2016             :     STV_f16_v2_avar     = 2001,
    2017             :     STV_f16_v4_areg     = 2002,
    2018             :     STV_f16_v4_areg_64  = 2003,
    2019             :     STV_f16_v4_ari      = 2004,
    2020             :     STV_f16_v4_ari_64   = 2005,
    2021             :     STV_f16_v4_asi      = 2006,
    2022             :     STV_f16_v4_avar     = 2007,
    2023             :     STV_f16x2_v2_areg   = 2008,
    2024             :     STV_f16x2_v2_areg_64        = 2009,
    2025             :     STV_f16x2_v2_ari    = 2010,
    2026             :     STV_f16x2_v2_ari_64 = 2011,
    2027             :     STV_f16x2_v2_asi    = 2012,
    2028             :     STV_f16x2_v2_avar   = 2013,
    2029             :     STV_f16x2_v4_areg   = 2014,
    2030             :     STV_f16x2_v4_areg_64        = 2015,
    2031             :     STV_f16x2_v4_ari    = 2016,
    2032             :     STV_f16x2_v4_ari_64 = 2017,
    2033             :     STV_f16x2_v4_asi    = 2018,
    2034             :     STV_f16x2_v4_avar   = 2019,
    2035             :     STV_f32_v2_areg     = 2020,
    2036             :     STV_f32_v2_areg_64  = 2021,
    2037             :     STV_f32_v2_ari      = 2022,
    2038             :     STV_f32_v2_ari_64   = 2023,
    2039             :     STV_f32_v2_asi      = 2024,
    2040             :     STV_f32_v2_avar     = 2025,
    2041             :     STV_f32_v4_areg     = 2026,
    2042             :     STV_f32_v4_areg_64  = 2027,
    2043             :     STV_f32_v4_ari      = 2028,
    2044             :     STV_f32_v4_ari_64   = 2029,
    2045             :     STV_f32_v4_asi      = 2030,
    2046             :     STV_f32_v4_avar     = 2031,
    2047             :     STV_f64_v2_areg     = 2032,
    2048             :     STV_f64_v2_areg_64  = 2033,
    2049             :     STV_f64_v2_ari      = 2034,
    2050             :     STV_f64_v2_ari_64   = 2035,
    2051             :     STV_f64_v2_asi      = 2036,
    2052             :     STV_f64_v2_avar     = 2037,
    2053             :     STV_f64_v4_areg     = 2038,
    2054             :     STV_f64_v4_areg_64  = 2039,
    2055             :     STV_f64_v4_ari      = 2040,
    2056             :     STV_f64_v4_ari_64   = 2041,
    2057             :     STV_f64_v4_asi      = 2042,
    2058             :     STV_f64_v4_avar     = 2043,
    2059             :     STV_i16_v2_areg     = 2044,
    2060             :     STV_i16_v2_areg_64  = 2045,
    2061             :     STV_i16_v2_ari      = 2046,
    2062             :     STV_i16_v2_ari_64   = 2047,
    2063             :     STV_i16_v2_asi      = 2048,
    2064             :     STV_i16_v2_avar     = 2049,
    2065             :     STV_i16_v4_areg     = 2050,
    2066             :     STV_i16_v4_areg_64  = 2051,
    2067             :     STV_i16_v4_ari      = 2052,
    2068             :     STV_i16_v4_ari_64   = 2053,
    2069             :     STV_i16_v4_asi      = 2054,
    2070             :     STV_i16_v4_avar     = 2055,
    2071             :     STV_i32_v2_areg     = 2056,
    2072             :     STV_i32_v2_areg_64  = 2057,
    2073             :     STV_i32_v2_ari      = 2058,
    2074             :     STV_i32_v2_ari_64   = 2059,
    2075             :     STV_i32_v2_asi      = 2060,
    2076             :     STV_i32_v2_avar     = 2061,
    2077             :     STV_i32_v4_areg     = 2062,
    2078             :     STV_i32_v4_areg_64  = 2063,
    2079             :     STV_i32_v4_ari      = 2064,
    2080             :     STV_i32_v4_ari_64   = 2065,
    2081             :     STV_i32_v4_asi      = 2066,
    2082             :     STV_i32_v4_avar     = 2067,
    2083             :     STV_i64_v2_areg     = 2068,
    2084             :     STV_i64_v2_areg_64  = 2069,
    2085             :     STV_i64_v2_ari      = 2070,
    2086             :     STV_i64_v2_ari_64   = 2071,
    2087             :     STV_i64_v2_asi      = 2072,
    2088             :     STV_i64_v2_avar     = 2073,
    2089             :     STV_i64_v4_areg     = 2074,
    2090             :     STV_i64_v4_areg_64  = 2075,
    2091             :     STV_i64_v4_ari      = 2076,
    2092             :     STV_i64_v4_ari_64   = 2077,
    2093             :     STV_i64_v4_asi      = 2078,
    2094             :     STV_i64_v4_avar     = 2079,
    2095             :     STV_i8_v2_areg      = 2080,
    2096             :     STV_i8_v2_areg_64   = 2081,
    2097             :     STV_i8_v2_ari       = 2082,
    2098             :     STV_i8_v2_ari_64    = 2083,
    2099             :     STV_i8_v2_asi       = 2084,
    2100             :     STV_i8_v2_avar      = 2085,
    2101             :     STV_i8_v4_areg      = 2086,
    2102             :     STV_i8_v4_areg_64   = 2087,
    2103             :     STV_i8_v4_ari       = 2088,
    2104             :     STV_i8_v4_ari_64    = 2089,
    2105             :     STV_i8_v4_asi       = 2090,
    2106             :     STV_i8_v4_avar      = 2091,
    2107             :     ST_f16_areg = 2092,
    2108             :     ST_f16_areg_64      = 2093,
    2109             :     ST_f16_ari  = 2094,
    2110             :     ST_f16_ari_64       = 2095,
    2111             :     ST_f16_asi  = 2096,
    2112             :     ST_f16_avar = 2097,
    2113             :     ST_f16x2_areg       = 2098,
    2114             :     ST_f16x2_areg_64    = 2099,
    2115             :     ST_f16x2_ari        = 2100,
    2116             :     ST_f16x2_ari_64     = 2101,
    2117             :     ST_f16x2_asi        = 2102,
    2118             :     ST_f16x2_avar       = 2103,
    2119             :     ST_f32_areg = 2104,
    2120             :     ST_f32_areg_64      = 2105,
    2121             :     ST_f32_ari  = 2106,
    2122             :     ST_f32_ari_64       = 2107,
    2123             :     ST_f32_asi  = 2108,
    2124             :     ST_f32_avar = 2109,
    2125             :     ST_f64_areg = 2110,
    2126             :     ST_f64_areg_64      = 2111,
    2127             :     ST_f64_ari  = 2112,
    2128             :     ST_f64_ari_64       = 2113,
    2129             :     ST_f64_asi  = 2114,
    2130             :     ST_f64_avar = 2115,
    2131             :     ST_i16_areg = 2116,
    2132             :     ST_i16_areg_64      = 2117,
    2133             :     ST_i16_ari  = 2118,
    2134             :     ST_i16_ari_64       = 2119,
    2135             :     ST_i16_asi  = 2120,
    2136             :     ST_i16_avar = 2121,
    2137             :     ST_i32_areg = 2122,
    2138             :     ST_i32_areg_64      = 2123,
    2139             :     ST_i32_ari  = 2124,
    2140             :     ST_i32_ari_64       = 2125,
    2141             :     ST_i32_asi  = 2126,
    2142             :     ST_i32_avar = 2127,
    2143             :     ST_i64_areg = 2128,
    2144             :     ST_i64_areg_64      = 2129,
    2145             :     ST_i64_ari  = 2130,
    2146             :     ST_i64_ari_64       = 2131,
    2147             :     ST_i64_asi  = 2132,
    2148             :     ST_i64_avar = 2133,
    2149             :     ST_i8_areg  = 2134,
    2150             :     ST_i8_areg_64       = 2135,
    2151             :     ST_i8_ari   = 2136,
    2152             :     ST_i8_ari_64        = 2137,
    2153             :     ST_i8_asi   = 2138,
    2154             :     ST_i8_avar  = 2139,
    2155             :     SUBCCCi32ri = 2140,
    2156             :     SUBCCCi32rr = 2141,
    2157             :     SUBCCi32ri  = 2142,
    2158             :     SUBCCi32rr  = 2143,
    2159             :     SUB_i1_ri   = 2144,
    2160             :     SUB_i1_rr   = 2145,
    2161             :     SUBi16ri    = 2146,
    2162             :     SUBi16rr    = 2147,
    2163             :     SUBi32ri    = 2148,
    2164             :     SUBi32rr    = 2149,
    2165             :     SUBi64ri    = 2150,
    2166             :     SUBi64rr    = 2151,
    2167             :     SULD_1D_ARRAY_I16_CLAMP     = 2152,
    2168             :     SULD_1D_ARRAY_I16_TRAP      = 2153,
    2169             :     SULD_1D_ARRAY_I16_ZERO      = 2154,
    2170             :     SULD_1D_ARRAY_I32_CLAMP     = 2155,
    2171             :     SULD_1D_ARRAY_I32_TRAP      = 2156,
    2172             :     SULD_1D_ARRAY_I32_ZERO      = 2157,
    2173             :     SULD_1D_ARRAY_I64_CLAMP     = 2158,
    2174             :     SULD_1D_ARRAY_I64_TRAP      = 2159,
    2175             :     SULD_1D_ARRAY_I64_ZERO      = 2160,
    2176             :     SULD_1D_ARRAY_I8_CLAMP      = 2161,
    2177             :     SULD_1D_ARRAY_I8_TRAP       = 2162,
    2178             :     SULD_1D_ARRAY_I8_ZERO       = 2163,
    2179             :     SULD_1D_ARRAY_V2I16_CLAMP   = 2164,
    2180             :     SULD_1D_ARRAY_V2I16_TRAP    = 2165,
    2181             :     SULD_1D_ARRAY_V2I16_ZERO    = 2166,
    2182             :     SULD_1D_ARRAY_V2I32_CLAMP   = 2167,
    2183             :     SULD_1D_ARRAY_V2I32_TRAP    = 2168,
    2184             :     SULD_1D_ARRAY_V2I32_ZERO    = 2169,
    2185             :     SULD_1D_ARRAY_V2I64_CLAMP   = 2170,
    2186             :     SULD_1D_ARRAY_V2I64_TRAP    = 2171,
    2187             :     SULD_1D_ARRAY_V2I64_ZERO    = 2172,
    2188             :     SULD_1D_ARRAY_V2I8_CLAMP    = 2173,
    2189             :     SULD_1D_ARRAY_V2I8_TRAP     = 2174,
    2190             :     SULD_1D_ARRAY_V2I8_ZERO     = 2175,
    2191             :     SULD_1D_ARRAY_V4I16_CLAMP   = 2176,
    2192             :     SULD_1D_ARRAY_V4I16_TRAP    = 2177,
    2193             :     SULD_1D_ARRAY_V4I16_ZERO    = 2178,
    2194             :     SULD_1D_ARRAY_V4I32_CLAMP   = 2179,
    2195             :     SULD_1D_ARRAY_V4I32_TRAP    = 2180,
    2196             :     SULD_1D_ARRAY_V4I32_ZERO    = 2181,
    2197             :     SULD_1D_ARRAY_V4I8_CLAMP    = 2182,
    2198             :     SULD_1D_ARRAY_V4I8_TRAP     = 2183,
    2199             :     SULD_1D_ARRAY_V4I8_ZERO     = 2184,
    2200             :     SULD_1D_I16_CLAMP   = 2185,
    2201             :     SULD_1D_I16_TRAP    = 2186,
    2202             :     SULD_1D_I16_ZERO    = 2187,
    2203             :     SULD_1D_I32_CLAMP   = 2188,
    2204             :     SULD_1D_I32_TRAP    = 2189,
    2205             :     SULD_1D_I32_ZERO    = 2190,
    2206             :     SULD_1D_I64_CLAMP   = 2191,
    2207             :     SULD_1D_I64_TRAP    = 2192,
    2208             :     SULD_1D_I64_ZERO    = 2193,
    2209             :     SULD_1D_I8_CLAMP    = 2194,
    2210             :     SULD_1D_I8_TRAP     = 2195,
    2211             :     SULD_1D_I8_ZERO     = 2196,
    2212             :     SULD_1D_V2I16_CLAMP = 2197,
    2213             :     SULD_1D_V2I16_TRAP  = 2198,
    2214             :     SULD_1D_V2I16_ZERO  = 2199,
    2215             :     SULD_1D_V2I32_CLAMP = 2200,
    2216             :     SULD_1D_V2I32_TRAP  = 2201,
    2217             :     SULD_1D_V2I32_ZERO  = 2202,
    2218             :     SULD_1D_V2I64_CLAMP = 2203,
    2219             :     SULD_1D_V2I64_TRAP  = 2204,
    2220             :     SULD_1D_V2I64_ZERO  = 2205,
    2221             :     SULD_1D_V2I8_CLAMP  = 2206,
    2222             :     SULD_1D_V2I8_TRAP   = 2207,
    2223             :     SULD_1D_V2I8_ZERO   = 2208,
    2224             :     SULD_1D_V4I16_CLAMP = 2209,
    2225             :     SULD_1D_V4I16_TRAP  = 2210,
    2226             :     SULD_1D_V4I16_ZERO  = 2211,
    2227             :     SULD_1D_V4I32_CLAMP = 2212,
    2228             :     SULD_1D_V4I32_TRAP  = 2213,
    2229             :     SULD_1D_V4I32_ZERO  = 2214,
    2230             :     SULD_1D_V4I8_CLAMP  = 2215,
    2231             :     SULD_1D_V4I8_TRAP   = 2216,
    2232             :     SULD_1D_V4I8_ZERO   = 2217,
    2233             :     SULD_2D_ARRAY_I16_CLAMP     = 2218,
    2234             :     SULD_2D_ARRAY_I16_TRAP      = 2219,
    2235             :     SULD_2D_ARRAY_I16_ZERO      = 2220,
    2236             :     SULD_2D_ARRAY_I32_CLAMP     = 2221,
    2237             :     SULD_2D_ARRAY_I32_TRAP      = 2222,
    2238             :     SULD_2D_ARRAY_I32_ZERO      = 2223,
    2239             :     SULD_2D_ARRAY_I64_CLAMP     = 2224,
    2240             :     SULD_2D_ARRAY_I64_TRAP      = 2225,
    2241             :     SULD_2D_ARRAY_I64_ZERO      = 2226,
    2242             :     SULD_2D_ARRAY_I8_CLAMP      = 2227,
    2243             :     SULD_2D_ARRAY_I8_TRAP       = 2228,
    2244             :     SULD_2D_ARRAY_I8_ZERO       = 2229,
    2245             :     SULD_2D_ARRAY_V2I16_CLAMP   = 2230,
    2246             :     SULD_2D_ARRAY_V2I16_TRAP    = 2231,
    2247             :     SULD_2D_ARRAY_V2I16_ZERO    = 2232,
    2248             :     SULD_2D_ARRAY_V2I32_CLAMP   = 2233,
    2249             :     SULD_2D_ARRAY_V2I32_TRAP    = 2234,
    2250             :     SULD_2D_ARRAY_V2I32_ZERO    = 2235,
    2251             :     SULD_2D_ARRAY_V2I64_CLAMP   = 2236,
    2252             :     SULD_2D_ARRAY_V2I64_TRAP    = 2237,
    2253             :     SULD_2D_ARRAY_V2I64_ZERO    = 2238,
    2254             :     SULD_2D_ARRAY_V2I8_CLAMP    = 2239,
    2255             :     SULD_2D_ARRAY_V2I8_TRAP     = 2240,
    2256             :     SULD_2D_ARRAY_V2I8_ZERO     = 2241,
    2257             :     SULD_2D_ARRAY_V4I16_CLAMP   = 2242,
    2258             :     SULD_2D_ARRAY_V4I16_TRAP    = 2243,
    2259             :     SULD_2D_ARRAY_V4I16_ZERO    = 2244,
    2260             :     SULD_2D_ARRAY_V4I32_CLAMP   = 2245,
    2261             :     SULD_2D_ARRAY_V4I32_TRAP    = 2246,
    2262             :     SULD_2D_ARRAY_V4I32_ZERO    = 2247,
    2263             :     SULD_2D_ARRAY_V4I8_CLAMP    = 2248,
    2264             :     SULD_2D_ARRAY_V4I8_TRAP     = 2249,
    2265             :     SULD_2D_ARRAY_V4I8_ZERO     = 2250,
    2266             :     SULD_2D_I16_CLAMP   = 2251,
    2267             :     SULD_2D_I16_TRAP    = 2252,
    2268             :     SULD_2D_I16_ZERO    = 2253,
    2269             :     SULD_2D_I32_CLAMP   = 2254,
    2270             :     SULD_2D_I32_TRAP    = 2255,
    2271             :     SULD_2D_I32_ZERO    = 2256,
    2272             :     SULD_2D_I64_CLAMP   = 2257,
    2273             :     SULD_2D_I64_TRAP    = 2258,
    2274             :     SULD_2D_I64_ZERO    = 2259,
    2275             :     SULD_2D_I8_CLAMP    = 2260,
    2276             :     SULD_2D_I8_TRAP     = 2261,
    2277             :     SULD_2D_I8_ZERO     = 2262,
    2278             :     SULD_2D_V2I16_CLAMP = 2263,
    2279             :     SULD_2D_V2I16_TRAP  = 2264,
    2280             :     SULD_2D_V2I16_ZERO  = 2265,
    2281             :     SULD_2D_V2I32_CLAMP = 2266,
    2282             :     SULD_2D_V2I32_TRAP  = 2267,
    2283             :     SULD_2D_V2I32_ZERO  = 2268,
    2284             :     SULD_2D_V2I64_CLAMP = 2269,
    2285             :     SULD_2D_V2I64_TRAP  = 2270,
    2286             :     SULD_2D_V2I64_ZERO  = 2271,
    2287             :     SULD_2D_V2I8_CLAMP  = 2272,
    2288             :     SULD_2D_V2I8_TRAP   = 2273,
    2289             :     SULD_2D_V2I8_ZERO   = 2274,
    2290             :     SULD_2D_V4I16_CLAMP = 2275,
    2291             :     SULD_2D_V4I16_TRAP  = 2276,
    2292             :     SULD_2D_V4I16_ZERO  = 2277,
    2293             :     SULD_2D_V4I32_CLAMP = 2278,
    2294             :     SULD_2D_V4I32_TRAP  = 2279,
    2295             :     SULD_2D_V4I32_ZERO  = 2280,
    2296             :     SULD_2D_V4I8_CLAMP  = 2281,
    2297             :     SULD_2D_V4I8_TRAP   = 2282,
    2298             :     SULD_2D_V4I8_ZERO   = 2283,
    2299             :     SULD_3D_I16_CLAMP   = 2284,
    2300             :     SULD_3D_I16_TRAP    = 2285,
    2301             :     SULD_3D_I16_ZERO    = 2286,
    2302             :     SULD_3D_I32_CLAMP   = 2287,
    2303             :     SULD_3D_I32_TRAP    = 2288,
    2304             :     SULD_3D_I32_ZERO    = 2289,
    2305             :     SULD_3D_I64_CLAMP   = 2290,
    2306             :     SULD_3D_I64_TRAP    = 2291,
    2307             :     SULD_3D_I64_ZERO    = 2292,
    2308             :     SULD_3D_I8_CLAMP    = 2293,
    2309             :     SULD_3D_I8_TRAP     = 2294,
    2310             :     SULD_3D_I8_ZERO     = 2295,
    2311             :     SULD_3D_V2I16_CLAMP = 2296,
    2312             :     SULD_3D_V2I16_TRAP  = 2297,
    2313             :     SULD_3D_V2I16_ZERO  = 2298,
    2314             :     SULD_3D_V2I32_CLAMP = 2299,
    2315             :     SULD_3D_V2I32_TRAP  = 2300,
    2316             :     SULD_3D_V2I32_ZERO  = 2301,
    2317             :     SULD_3D_V2I64_CLAMP = 2302,
    2318             :     SULD_3D_V2I64_TRAP  = 2303,
    2319             :     SULD_3D_V2I64_ZERO  = 2304,
    2320             :     SULD_3D_V2I8_CLAMP  = 2305,
    2321             :     SULD_3D_V2I8_TRAP   = 2306,
    2322             :     SULD_3D_V2I8_ZERO   = 2307,
    2323             :     SULD_3D_V4I16_CLAMP = 2308,
    2324             :     SULD_3D_V4I16_TRAP  = 2309,
    2325             :     SULD_3D_V4I16_ZERO  = 2310,
    2326             :     SULD_3D_V4I32_CLAMP = 2311,
    2327             :     SULD_3D_V4I32_TRAP  = 2312,
    2328             :     SULD_3D_V4I32_ZERO  = 2313,
    2329             :     SULD_3D_V4I8_CLAMP  = 2314,
    2330             :     SULD_3D_V4I8_TRAP   = 2315,
    2331             :     SULD_3D_V4I8_ZERO   = 2316,
    2332             :     SUQ_ARRAY_SIZE      = 2317,
    2333             :     SUQ_CHANNEL_DATA_TYPE       = 2318,
    2334             :     SUQ_CHANNEL_ORDER   = 2319,
    2335             :     SUQ_DEPTH   = 2320,
    2336             :     SUQ_HEIGHT  = 2321,
    2337             :     SUQ_WIDTH   = 2322,
    2338             :     SUST_B_1D_ARRAY_B16_CLAMP   = 2323,
    2339             :     SUST_B_1D_ARRAY_B16_TRAP    = 2324,
    2340             :     SUST_B_1D_ARRAY_B16_ZERO    = 2325,
    2341             :     SUST_B_1D_ARRAY_B32_CLAMP   = 2326,
    2342             :     SUST_B_1D_ARRAY_B32_TRAP    = 2327,
    2343             :     SUST_B_1D_ARRAY_B32_ZERO    = 2328,
    2344             :     SUST_B_1D_ARRAY_B64_CLAMP   = 2329,
    2345             :     SUST_B_1D_ARRAY_B64_TRAP    = 2330,
    2346             :     SUST_B_1D_ARRAY_B64_ZERO    = 2331,
    2347             :     SUST_B_1D_ARRAY_B8_CLAMP    = 2332,
    2348             :     SUST_B_1D_ARRAY_B8_TRAP     = 2333,
    2349             :     SUST_B_1D_ARRAY_B8_ZERO     = 2334,
    2350             :     SUST_B_1D_ARRAY_V2B16_CLAMP = 2335,
    2351             :     SUST_B_1D_ARRAY_V2B16_TRAP  = 2336,
    2352             :     SUST_B_1D_ARRAY_V2B16_ZERO  = 2337,
    2353             :     SUST_B_1D_ARRAY_V2B32_CLAMP = 2338,
    2354             :     SUST_B_1D_ARRAY_V2B32_TRAP  = 2339,
    2355             :     SUST_B_1D_ARRAY_V2B32_ZERO  = 2340,
    2356             :     SUST_B_1D_ARRAY_V2B64_CLAMP = 2341,
    2357             :     SUST_B_1D_ARRAY_V2B64_TRAP  = 2342,
    2358             :     SUST_B_1D_ARRAY_V2B64_ZERO  = 2343,
    2359             :     SUST_B_1D_ARRAY_V2B8_CLAMP  = 2344,
    2360             :     SUST_B_1D_ARRAY_V2B8_TRAP   = 2345,
    2361             :     SUST_B_1D_ARRAY_V2B8_ZERO   = 2346,
    2362             :     SUST_B_1D_ARRAY_V4B16_CLAMP = 2347,
    2363             :     SUST_B_1D_ARRAY_V4B16_TRAP  = 2348,
    2364             :     SUST_B_1D_ARRAY_V4B16_ZERO  = 2349,
    2365             :     SUST_B_1D_ARRAY_V4B32_CLAMP = 2350,
    2366             :     SUST_B_1D_ARRAY_V4B32_TRAP  = 2351,
    2367             :     SUST_B_1D_ARRAY_V4B32_ZERO  = 2352,
    2368             :     SUST_B_1D_ARRAY_V4B8_CLAMP  = 2353,
    2369             :     SUST_B_1D_ARRAY_V4B8_TRAP   = 2354,
    2370             :     SUST_B_1D_ARRAY_V4B8_ZERO   = 2355,
    2371             :     SUST_B_1D_B16_CLAMP = 2356,
    2372             :     SUST_B_1D_B16_TRAP  = 2357,
    2373             :     SUST_B_1D_B16_ZERO  = 2358,
    2374             :     SUST_B_1D_B32_CLAMP = 2359,
    2375             :     SUST_B_1D_B32_TRAP  = 2360,
    2376             :     SUST_B_1D_B32_ZERO  = 2361,
    2377             :     SUST_B_1D_B64_CLAMP = 2362,
    2378             :     SUST_B_1D_B64_TRAP  = 2363,
    2379             :     SUST_B_1D_B64_ZERO  = 2364,
    2380             :     SUST_B_1D_B8_CLAMP  = 2365,
    2381             :     SUST_B_1D_B8_TRAP   = 2366,
    2382             :     SUST_B_1D_B8_ZERO   = 2367,
    2383             :     SUST_B_1D_V2B16_CLAMP       = 2368,
    2384             :     SUST_B_1D_V2B16_TRAP        = 2369,
    2385             :     SUST_B_1D_V2B16_ZERO        = 2370,
    2386             :     SUST_B_1D_V2B32_CLAMP       = 2371,
    2387             :     SUST_B_1D_V2B32_TRAP        = 2372,
    2388             :     SUST_B_1D_V2B32_ZERO        = 2373,
    2389             :     SUST_B_1D_V2B64_CLAMP       = 2374,
    2390             :     SUST_B_1D_V2B64_TRAP        = 2375,
    2391             :     SUST_B_1D_V2B64_ZERO        = 2376,
    2392             :     SUST_B_1D_V2B8_CLAMP        = 2377,
    2393             :     SUST_B_1D_V2B8_TRAP = 2378,
    2394             :     SUST_B_1D_V2B8_ZERO = 2379,
    2395             :     SUST_B_1D_V4B16_CLAMP       = 2380,
    2396             :     SUST_B_1D_V4B16_TRAP        = 2381,
    2397             :     SUST_B_1D_V4B16_ZERO        = 2382,
    2398             :     SUST_B_1D_V4B32_CLAMP       = 2383,
    2399             :     SUST_B_1D_V4B32_TRAP        = 2384,
    2400             :     SUST_B_1D_V4B32_ZERO        = 2385,
    2401             :     SUST_B_1D_V4B8_CLAMP        = 2386,
    2402             :     SUST_B_1D_V4B8_TRAP = 2387,
    2403             :     SUST_B_1D_V4B8_ZERO = 2388,
    2404             :     SUST_B_2D_ARRAY_B16_CLAMP   = 2389,
    2405             :     SUST_B_2D_ARRAY_B16_TRAP    = 2390,
    2406             :     SUST_B_2D_ARRAY_B16_ZERO    = 2391,
    2407             :     SUST_B_2D_ARRAY_B32_CLAMP   = 2392,
    2408             :     SUST_B_2D_ARRAY_B32_TRAP    = 2393,
    2409             :     SUST_B_2D_ARRAY_B32_ZERO    = 2394,
    2410             :     SUST_B_2D_ARRAY_B64_CLAMP   = 2395,
    2411             :     SUST_B_2D_ARRAY_B64_TRAP    = 2396,
    2412             :     SUST_B_2D_ARRAY_B64_ZERO    = 2397,
    2413             :     SUST_B_2D_ARRAY_B8_CLAMP    = 2398,
    2414             :     SUST_B_2D_ARRAY_B8_TRAP     = 2399,
    2415             :     SUST_B_2D_ARRAY_B8_ZERO     = 2400,
    2416             :     SUST_B_2D_ARRAY_V2B16_CLAMP = 2401,
    2417             :     SUST_B_2D_ARRAY_V2B16_TRAP  = 2402,
    2418             :     SUST_B_2D_ARRAY_V2B16_ZERO  = 2403,
    2419             :     SUST_B_2D_ARRAY_V2B32_CLAMP = 2404,
    2420             :     SUST_B_2D_ARRAY_V2B32_TRAP  = 2405,
    2421             :     SUST_B_2D_ARRAY_V2B32_ZERO  = 2406,
    2422             :     SUST_B_2D_ARRAY_V2B64_CLAMP = 2407,
    2423             :     SUST_B_2D_ARRAY_V2B64_TRAP  = 2408,
    2424             :     SUST_B_2D_ARRAY_V2B64_ZERO  = 2409,
    2425             :     SUST_B_2D_ARRAY_V2B8_CLAMP  = 2410,
    2426             :     SUST_B_2D_ARRAY_V2B8_TRAP   = 2411,
    2427             :     SUST_B_2D_ARRAY_V2B8_ZERO   = 2412,
    2428             :     SUST_B_2D_ARRAY_V4B16_CLAMP = 2413,
    2429             :     SUST_B_2D_ARRAY_V4B16_TRAP  = 2414,
    2430             :     SUST_B_2D_ARRAY_V4B16_ZERO  = 2415,
    2431             :     SUST_B_2D_ARRAY_V4B32_CLAMP = 2416,
    2432             :     SUST_B_2D_ARRAY_V4B32_TRAP  = 2417,
    2433             :     SUST_B_2D_ARRAY_V4B32_ZERO  = 2418,
    2434             :     SUST_B_2D_ARRAY_V4B8_CLAMP  = 2419,
    2435             :     SUST_B_2D_ARRAY_V4B8_TRAP   = 2420,
    2436             :     SUST_B_2D_ARRAY_V4B8_ZERO   = 2421,
    2437             :     SUST_B_2D_B16_CLAMP = 2422,
    2438             :     SUST_B_2D_B16_TRAP  = 2423,
    2439             :     SUST_B_2D_B16_ZERO  = 2424,
    2440             :     SUST_B_2D_B32_CLAMP = 2425,
    2441             :     SUST_B_2D_B32_TRAP  = 2426,
    2442             :     SUST_B_2D_B32_ZERO  = 2427,
    2443             :     SUST_B_2D_B64_CLAMP = 2428,
    2444             :     SUST_B_2D_B64_TRAP  = 2429,
    2445             :     SUST_B_2D_B64_ZERO  = 2430,
    2446             :     SUST_B_2D_B8_CLAMP  = 2431,
    2447             :     SUST_B_2D_B8_TRAP   = 2432,
    2448             :     SUST_B_2D_B8_ZERO   = 2433,
    2449             :     SUST_B_2D_V2B16_CLAMP       = 2434,
    2450             :     SUST_B_2D_V2B16_TRAP        = 2435,
    2451             :     SUST_B_2D_V2B16_ZERO        = 2436,
    2452             :     SUST_B_2D_V2B32_CLAMP       = 2437,
    2453             :     SUST_B_2D_V2B32_TRAP        = 2438,
    2454             :     SUST_B_2D_V2B32_ZERO        = 2439,
    2455             :     SUST_B_2D_V2B64_CLAMP       = 2440,
    2456             :     SUST_B_2D_V2B64_TRAP        = 2441,
    2457             :     SUST_B_2D_V2B64_ZERO        = 2442,
    2458             :     SUST_B_2D_V2B8_CLAMP        = 2443,
    2459             :     SUST_B_2D_V2B8_TRAP = 2444,
    2460             :     SUST_B_2D_V2B8_ZERO = 2445,
    2461             :     SUST_B_2D_V4B16_CLAMP       = 2446,
    2462             :     SUST_B_2D_V4B16_TRAP        = 2447,
    2463             :     SUST_B_2D_V4B16_ZERO        = 2448,
    2464             :     SUST_B_2D_V4B32_CLAMP       = 2449,
    2465             :     SUST_B_2D_V4B32_TRAP        = 2450,
    2466             :     SUST_B_2D_V4B32_ZERO        = 2451,
    2467             :     SUST_B_2D_V4B8_CLAMP        = 2452,
    2468             :     SUST_B_2D_V4B8_TRAP = 2453,
    2469             :     SUST_B_2D_V4B8_ZERO = 2454,
    2470             :     SUST_B_3D_B16_CLAMP = 2455,
    2471             :     SUST_B_3D_B16_TRAP  = 2456,
    2472             :     SUST_B_3D_B16_ZERO  = 2457,
    2473             :     SUST_B_3D_B32_CLAMP = 2458,
    2474             :     SUST_B_3D_B32_TRAP  = 2459,
    2475             :     SUST_B_3D_B32_ZERO  = 2460,
    2476             :     SUST_B_3D_B64_CLAMP = 2461,
    2477             :     SUST_B_3D_B64_TRAP  = 2462,
    2478             :     SUST_B_3D_B64_ZERO  = 2463,
    2479             :     SUST_B_3D_B8_CLAMP  = 2464,
    2480             :     SUST_B_3D_B8_TRAP   = 2465,
    2481             :     SUST_B_3D_B8_ZERO   = 2466,
    2482             :     SUST_B_3D_V2B16_CLAMP       = 2467,
    2483             :     SUST_B_3D_V2B16_TRAP        = 2468,
    2484             :     SUST_B_3D_V2B16_ZERO        = 2469,
    2485             :     SUST_B_3D_V2B32_CLAMP       = 2470,
    2486             :     SUST_B_3D_V2B32_TRAP        = 2471,
    2487             :     SUST_B_3D_V2B32_ZERO        = 2472,
    2488             :     SUST_B_3D_V2B64_CLAMP       = 2473,
    2489             :     SUST_B_3D_V2B64_TRAP        = 2474,
    2490             :     SUST_B_3D_V2B64_ZERO        = 2475,
    2491             :     SUST_B_3D_V2B8_CLAMP        = 2476,
    2492             :     SUST_B_3D_V2B8_TRAP = 2477,
    2493             :     SUST_B_3D_V2B8_ZERO = 2478,
    2494             :     SUST_B_3D_V4B16_CLAMP       = 2479,
    2495             :     SUST_B_3D_V4B16_TRAP        = 2480,
    2496             :     SUST_B_3D_V4B16_ZERO        = 2481,
    2497             :     SUST_B_3D_V4B32_CLAMP       = 2482,
    2498             :     SUST_B_3D_V4B32_TRAP        = 2483,
    2499             :     SUST_B_3D_V4B32_ZERO        = 2484,
    2500             :     SUST_B_3D_V4B8_CLAMP        = 2485,
    2501             :     SUST_B_3D_V4B8_TRAP = 2486,
    2502             :     SUST_B_3D_V4B8_ZERO = 2487,
    2503             :     SUST_P_1D_ARRAY_B16_TRAP    = 2488,
    2504             :     SUST_P_1D_ARRAY_B32_TRAP    = 2489,
    2505             :     SUST_P_1D_ARRAY_B8_TRAP     = 2490,
    2506             :     SUST_P_1D_ARRAY_V2B16_TRAP  = 2491,
    2507             :     SUST_P_1D_ARRAY_V2B32_TRAP  = 2492,
    2508             :     SUST_P_1D_ARRAY_V2B8_TRAP   = 2493,
    2509             :     SUST_P_1D_ARRAY_V4B16_TRAP  = 2494,
    2510             :     SUST_P_1D_ARRAY_V4B32_TRAP  = 2495,
    2511             :     SUST_P_1D_ARRAY_V4B8_TRAP   = 2496,
    2512             :     SUST_P_1D_B16_TRAP  = 2497,
    2513             :     SUST_P_1D_B32_TRAP  = 2498,
    2514             :     SUST_P_1D_B8_TRAP   = 2499,
    2515             :     SUST_P_1D_V2B16_TRAP        = 2500,
    2516             :     SUST_P_1D_V2B32_TRAP        = 2501,
    2517             :     SUST_P_1D_V2B8_TRAP = 2502,
    2518             :     SUST_P_1D_V4B16_TRAP        = 2503,
    2519             :     SUST_P_1D_V4B32_TRAP        = 2504,
    2520             :     SUST_P_1D_V4B8_TRAP = 2505,
    2521             :     SUST_P_2D_ARRAY_B16_TRAP    = 2506,
    2522             :     SUST_P_2D_ARRAY_B32_TRAP    = 2507,
    2523             :     SUST_P_2D_ARRAY_B8_TRAP     = 2508,
    2524             :     SUST_P_2D_ARRAY_V2B16_TRAP  = 2509,
    2525             :     SUST_P_2D_ARRAY_V2B32_TRAP  = 2510,
    2526             :     SUST_P_2D_ARRAY_V2B8_TRAP   = 2511,
    2527             :     SUST_P_2D_ARRAY_V4B16_TRAP  = 2512,
    2528             :     SUST_P_2D_ARRAY_V4B32_TRAP  = 2513,
    2529             :     SUST_P_2D_ARRAY_V4B8_TRAP   = 2514,
    2530             :     SUST_P_2D_B16_TRAP  = 2515,
    2531             :     SUST_P_2D_B32_TRAP  = 2516,
    2532             :     SUST_P_2D_B8_TRAP   = 2517,
    2533             :     SUST_P_2D_V2B16_TRAP        = 2518,
    2534             :     SUST_P_2D_V2B32_TRAP        = 2519,
    2535             :     SUST_P_2D_V2B8_TRAP = 2520,
    2536             :     SUST_P_2D_V4B16_TRAP        = 2521,
    2537             :     SUST_P_2D_V4B32_TRAP        = 2522,
    2538             :     SUST_P_2D_V4B8_TRAP = 2523,
    2539             :     SUST_P_3D_B16_TRAP  = 2524,
    2540             :     SUST_P_3D_B32_TRAP  = 2525,
    2541             :     SUST_P_3D_B8_TRAP   = 2526,
    2542             :     SUST_P_3D_V2B16_TRAP        = 2527,
    2543             :     SUST_P_3D_V2B32_TRAP        = 2528,
    2544             :     SUST_P_3D_V2B8_TRAP = 2529,
    2545             :     SUST_P_3D_V4B16_TRAP        = 2530,
    2546             :     SUST_P_3D_V4B32_TRAP        = 2531,
    2547             :     SUST_P_3D_V4B8_TRAP = 2532,
    2548             :     SplitF16x2  = 2533,
    2549             :     SplitI32toF16x2     = 2534,
    2550             :     StoreParamF16       = 2535,
    2551             :     StoreParamF16x2     = 2536,
    2552             :     StoreParamF32       = 2537,
    2553             :     StoreParamF64       = 2538,
    2554             :     StoreParamI16       = 2539,
    2555             :     StoreParamI32       = 2540,
    2556             :     StoreParamI64       = 2541,
    2557             :     StoreParamI8        = 2542,
    2558             :     StoreParamV2F16     = 2543,
    2559             :     StoreParamV2F16x2   = 2544,
    2560             :     StoreParamV2F32     = 2545,
    2561             :     StoreParamV2F64     = 2546,
    2562             :     StoreParamV2I16     = 2547,
    2563             :     StoreParamV2I32     = 2548,
    2564             :     StoreParamV2I64     = 2549,
    2565             :     StoreParamV2I8      = 2550,
    2566             :     StoreParamV4F16     = 2551,
    2567             :     StoreParamV4F16x2   = 2552,
    2568             :     StoreParamV4F32     = 2553,
    2569             :     StoreParamV4I16     = 2554,
    2570             :     StoreParamV4I32     = 2555,
    2571             :     StoreParamV4I8      = 2556,
    2572             :     StoreRetvalF16      = 2557,
    2573             :     StoreRetvalF16x2    = 2558,
    2574             :     StoreRetvalF32      = 2559,
    2575             :     StoreRetvalF64      = 2560,
    2576             :     StoreRetvalI16      = 2561,
    2577             :     StoreRetvalI32      = 2562,
    2578             :     StoreRetvalI64      = 2563,
    2579             :     StoreRetvalI8       = 2564,
    2580             :     StoreRetvalV2F16    = 2565,
    2581             :     StoreRetvalV2F16x2  = 2566,
    2582             :     StoreRetvalV2F32    = 2567,
    2583             :     StoreRetvalV2F64    = 2568,
    2584             :     StoreRetvalV2I16    = 2569,
    2585             :     StoreRetvalV2I32    = 2570,
    2586             :     StoreRetvalV2I64    = 2571,
    2587             :     StoreRetvalV2I8     = 2572,
    2588             :     StoreRetvalV4F16    = 2573,
    2589             :     StoreRetvalV4F16x2  = 2574,
    2590             :     StoreRetvalV4F32    = 2575,
    2591             :     StoreRetvalV4I16    = 2576,
    2592             :     StoreRetvalV4I32    = 2577,
    2593             :     StoreRetvalV4I8     = 2578,
    2594             :     TEX_1D_ARRAY_F32_F32        = 2579,
    2595             :     TEX_1D_ARRAY_F32_F32_GRAD   = 2580,
    2596             :     TEX_1D_ARRAY_F32_F32_LEVEL  = 2581,
    2597             :     TEX_1D_ARRAY_F32_S32        = 2582,
    2598             :     TEX_1D_ARRAY_S32_F32        = 2583,
    2599             :     TEX_1D_ARRAY_S32_F32_GRAD   = 2584,
    2600             :     TEX_1D_ARRAY_S32_F32_LEVEL  = 2585,
    2601             :     TEX_1D_ARRAY_S32_S32        = 2586,
    2602             :     TEX_1D_ARRAY_U32_F32        = 2587,
    2603             :     TEX_1D_ARRAY_U32_F32_GRAD   = 2588,
    2604             :     TEX_1D_ARRAY_U32_F32_LEVEL  = 2589,
    2605             :     TEX_1D_ARRAY_U32_S32        = 2590,
    2606             :     TEX_1D_F32_F32      = 2591,
    2607             :     TEX_1D_F32_F32_GRAD = 2592,
    2608             :     TEX_1D_F32_F32_LEVEL        = 2593,
    2609             :     TEX_1D_F32_S32      = 2594,
    2610             :     TEX_1D_S32_F32      = 2595,
    2611             :     TEX_1D_S32_F32_GRAD = 2596,
    2612             :     TEX_1D_S32_F32_LEVEL        = 2597,
    2613             :     TEX_1D_S32_S32      = 2598,
    2614             :     TEX_1D_U32_F32      = 2599,
    2615             :     TEX_1D_U32_F32_GRAD = 2600,
    2616             :     TEX_1D_U32_F32_LEVEL        = 2601,
    2617             :     TEX_1D_U32_S32      = 2602,
    2618             :     TEX_2D_ARRAY_F32_F32        = 2603,
    2619             :     TEX_2D_ARRAY_F32_F32_GRAD   = 2604,
    2620             :     TEX_2D_ARRAY_F32_F32_LEVEL  = 2605,
    2621             :     TEX_2D_ARRAY_F32_S32        = 2606,
    2622             :     TEX_2D_ARRAY_S32_F32        = 2607,
    2623             :     TEX_2D_ARRAY_S32_F32_GRAD   = 2608,
    2624             :     TEX_2D_ARRAY_S32_F32_LEVEL  = 2609,
    2625             :     TEX_2D_ARRAY_S32_S32        = 2610,
    2626             :     TEX_2D_ARRAY_U32_F32        = 2611,
    2627             :     TEX_2D_ARRAY_U32_F32_GRAD   = 2612,
    2628             :     TEX_2D_ARRAY_U32_F32_LEVEL  = 2613,
    2629             :     TEX_2D_ARRAY_U32_S32        = 2614,
    2630             :     TEX_2D_F32_F32      = 2615,
    2631             :     TEX_2D_F32_F32_GRAD = 2616,
    2632             :     TEX_2D_F32_F32_LEVEL        = 2617,
    2633             :     TEX_2D_F32_S32      = 2618,
    2634             :     TEX_2D_S32_F32      = 2619,
    2635             :     TEX_2D_S32_F32_GRAD = 2620,
    2636             :     TEX_2D_S32_F32_LEVEL        = 2621,
    2637             :     TEX_2D_S32_S32      = 2622,
    2638             :     TEX_2D_U32_F32      = 2623,
    2639             :     TEX_2D_U32_F32_GRAD = 2624,
    2640             :     TEX_2D_U32_F32_LEVEL        = 2625,
    2641             :     TEX_2D_U32_S32      = 2626,
    2642             :     TEX_3D_F32_F32      = 2627,
    2643             :     TEX_3D_F32_F32_GRAD = 2628,
    2644             :     TEX_3D_F32_F32_LEVEL        = 2629,
    2645             :     TEX_3D_F32_S32      = 2630,
    2646             :     TEX_3D_S32_F32      = 2631,
    2647             :     TEX_3D_S32_F32_GRAD = 2632,
    2648             :     TEX_3D_S32_F32_LEVEL        = 2633,
    2649             :     TEX_3D_S32_S32      = 2634,
    2650             :     TEX_3D_U32_F32      = 2635,
    2651             :     TEX_3D_U32_F32_GRAD = 2636,
    2652             :     TEX_3D_U32_F32_LEVEL        = 2637,
    2653             :     TEX_3D_U32_S32      = 2638,
    2654             :     TEX_CUBE_ARRAY_F32_F32      = 2639,
    2655             :     TEX_CUBE_ARRAY_F32_F32_LEVEL        = 2640,
    2656             :     TEX_CUBE_ARRAY_S32_F32      = 2641,
    2657             :     TEX_CUBE_ARRAY_S32_F32_LEVEL        = 2642,
    2658             :     TEX_CUBE_ARRAY_U32_F32      = 2643,
    2659             :     TEX_CUBE_ARRAY_U32_F32_LEVEL        = 2644,
    2660             :     TEX_CUBE_F32_F32    = 2645,
    2661             :     TEX_CUBE_F32_F32_LEVEL      = 2646,
    2662             :     TEX_CUBE_S32_F32    = 2647,
    2663             :     TEX_CUBE_S32_F32_LEVEL      = 2648,
    2664             :     TEX_CUBE_U32_F32    = 2649,
    2665             :     TEX_CUBE_U32_F32_LEVEL      = 2650,
    2666             :     TEX_UNIFIED_1D_ARRAY_F32_F32        = 2651,
    2667             :     TEX_UNIFIED_1D_ARRAY_F32_F32_GRAD   = 2652,
    2668             :     TEX_UNIFIED_1D_ARRAY_F32_F32_LEVEL  = 2653,
    2669             :     TEX_UNIFIED_1D_ARRAY_F32_S32        = 2654,
    2670             :     TEX_UNIFIED_1D_ARRAY_S32_F32        = 2655,
    2671             :     TEX_UNIFIED_1D_ARRAY_S32_F32_GRAD   = 2656,
    2672             :     TEX_UNIFIED_1D_ARRAY_S32_F32_LEVEL  = 2657,
    2673             :     TEX_UNIFIED_1D_ARRAY_S32_S32        = 2658,
    2674             :     TEX_UNIFIED_1D_ARRAY_U32_F32        = 2659,
    2675             :     TEX_UNIFIED_1D_ARRAY_U32_F32_GRAD   = 2660,
    2676             :     TEX_UNIFIED_1D_ARRAY_U32_F32_LEVEL  = 2661,
    2677             :     TEX_UNIFIED_1D_ARRAY_U32_S32        = 2662,
    2678             :     TEX_UNIFIED_1D_F32_F32      = 2663,
    2679             :     TEX_UNIFIED_1D_F32_F32_GRAD = 2664,
    2680             :     TEX_UNIFIED_1D_F32_F32_LEVEL        = 2665,
    2681             :     TEX_UNIFIED_1D_F32_S32      = 2666,
    2682             :     TEX_UNIFIED_1D_S32_F32      = 2667,
    2683             :     TEX_UNIFIED_1D_S32_F32_GRAD = 2668,
    2684             :     TEX_UNIFIED_1D_S32_F32_LEVEL        = 2669,
    2685             :     TEX_UNIFIED_1D_S32_S32      = 2670,
    2686             :     TEX_UNIFIED_1D_U32_F32      = 2671,
    2687             :     TEX_UNIFIED_1D_U32_F32_GRAD = 2672,
    2688             :     TEX_UNIFIED_1D_U32_F32_LEVEL        = 2673,
    2689             :     TEX_UNIFIED_1D_U32_S32      = 2674,
    2690             :     TEX_UNIFIED_2D_ARRAY_F32_F32        = 2675,
    2691             :     TEX_UNIFIED_2D_ARRAY_F32_F32_GRAD   = 2676,
    2692             :     TEX_UNIFIED_2D_ARRAY_F32_F32_LEVEL  = 2677,
    2693             :     TEX_UNIFIED_2D_ARRAY_F32_S32        = 2678,
    2694             :     TEX_UNIFIED_2D_ARRAY_S32_F32        = 2679,
    2695             :     TEX_UNIFIED_2D_ARRAY_S32_F32_GRAD   = 2680,
    2696             :     TEX_UNIFIED_2D_ARRAY_S32_F32_LEVEL  = 2681,
    2697             :     TEX_UNIFIED_2D_ARRAY_S32_S32        = 2682,
    2698             :     TEX_UNIFIED_2D_ARRAY_U32_F32        = 2683,
    2699             :     TEX_UNIFIED_2D_ARRAY_U32_F32_GRAD   = 2684,
    2700             :     TEX_UNIFIED_2D_ARRAY_U32_F32_LEVEL  = 2685,
    2701             :     TEX_UNIFIED_2D_ARRAY_U32_S32        = 2686,
    2702             :     TEX_UNIFIED_2D_F32_F32      = 2687,
    2703             :     TEX_UNIFIED_2D_F32_F32_GRAD = 2688,
    2704             :     TEX_UNIFIED_2D_F32_F32_LEVEL        = 2689,
    2705             :     TEX_UNIFIED_2D_F32_S32      = 2690,
    2706             :     TEX_UNIFIED_2D_S32_F32      = 2691,
    2707             :     TEX_UNIFIED_2D_S32_F32_GRAD = 2692,
    2708             :     TEX_UNIFIED_2D_S32_F32_LEVEL        = 2693,
    2709             :     TEX_UNIFIED_2D_S32_S32      = 2694,
    2710             :     TEX_UNIFIED_2D_U32_F32      = 2695,
    2711             :     TEX_UNIFIED_2D_U32_F32_GRAD = 2696,
    2712             :     TEX_UNIFIED_2D_U32_F32_LEVEL        = 2697,
    2713             :     TEX_UNIFIED_2D_U32_S32      = 2698,
    2714             :     TEX_UNIFIED_3D_F32_F32      = 2699,
    2715             :     TEX_UNIFIED_3D_F32_F32_GRAD = 2700,
    2716             :     TEX_UNIFIED_3D_F32_F32_LEVEL        = 2701,
    2717             :     TEX_UNIFIED_3D_F32_S32      = 2702,
    2718             :     TEX_UNIFIED_3D_S32_F32      = 2703,
    2719             :     TEX_UNIFIED_3D_S32_F32_GRAD = 2704,
    2720             :     TEX_UNIFIED_3D_S32_F32_LEVEL        = 2705,
    2721             :     TEX_UNIFIED_3D_S32_S32      = 2706,
    2722             :     TEX_UNIFIED_3D_U32_F32      = 2707,
    2723             :     TEX_UNIFIED_3D_U32_F32_GRAD = 2708,
    2724             :     TEX_UNIFIED_3D_U32_F32_LEVEL        = 2709,
    2725             :     TEX_UNIFIED_3D_U32_S32      = 2710,
    2726             :     TEX_UNIFIED_CUBE_ARRAY_F32_F32      = 2711,
    2727             :     TEX_UNIFIED_CUBE_ARRAY_F32_F32_LEVEL        = 2712,
    2728             :     TEX_UNIFIED_CUBE_ARRAY_S32_F32      = 2713,
    2729             :     TEX_UNIFIED_CUBE_ARRAY_S32_F32_LEVEL        = 2714,
    2730             :     TEX_UNIFIED_CUBE_ARRAY_U32_F32      = 2715,
    2731             :     TEX_UNIFIED_CUBE_ARRAY_U32_F32_LEVEL        = 2716,
    2732             :     TEX_UNIFIED_CUBE_F32_F32    = 2717,
    2733             :     TEX_UNIFIED_CUBE_F32_F32_LEVEL      = 2718,
    2734             :     TEX_UNIFIED_CUBE_S32_F32    = 2719,
    2735             :     TEX_UNIFIED_CUBE_S32_F32_LEVEL      = 2720,
    2736             :     TEX_UNIFIED_CUBE_U32_F32    = 2721,
    2737             :     TEX_UNIFIED_CUBE_U32_F32_LEVEL      = 2722,
    2738             :     TLD4_A_2D_F32_F32   = 2723,
    2739             :     TLD4_A_2D_S32_F32   = 2724,
    2740             :     TLD4_A_2D_U32_F32   = 2725,
    2741             :     TLD4_B_2D_F32_F32   = 2726,
    2742             :     TLD4_B_2D_S32_F32   = 2727,
    2743             :     TLD4_B_2D_U32_F32   = 2728,
    2744             :     TLD4_G_2D_F32_F32   = 2729,
    2745             :     TLD4_G_2D_S32_F32   = 2730,
    2746             :     TLD4_G_2D_U32_F32   = 2731,
    2747             :     TLD4_R_2D_F32_F32   = 2732,
    2748             :     TLD4_R_2D_S32_F32   = 2733,
    2749             :     TLD4_R_2D_U32_F32   = 2734,
    2750             :     TLD4_UNIFIED_A_2D_F32_F32   = 2735,
    2751             :     TLD4_UNIFIED_A_2D_S32_F32   = 2736,
    2752             :     TLD4_UNIFIED_A_2D_U32_F32   = 2737,
    2753             :     TLD4_UNIFIED_B_2D_F32_F32   = 2738,
    2754             :     TLD4_UNIFIED_B_2D_S32_F32   = 2739,
    2755             :     TLD4_UNIFIED_B_2D_U32_F32   = 2740,
    2756             :     TLD4_UNIFIED_G_2D_F32_F32   = 2741,
    2757             :     TLD4_UNIFIED_G_2D_S32_F32   = 2742,
    2758             :     TLD4_UNIFIED_G_2D_U32_F32   = 2743,
    2759             :     TLD4_UNIFIED_R_2D_F32_F32   = 2744,
    2760             :     TLD4_UNIFIED_R_2D_S32_F32   = 2745,
    2761             :     TLD4_UNIFIED_R_2D_U32_F32   = 2746,
    2762             :     TXQ_ARRAY_SIZE      = 2747,
    2763             :     TXQ_CHANNEL_DATA_TYPE       = 2748,
    2764             :     TXQ_CHANNEL_ORDER   = 2749,
    2765             :     TXQ_DEPTH   = 2750,
    2766             :     TXQ_HEIGHT  = 2751,
    2767             :     TXQ_NUM_MIPMAP_LEVELS       = 2752,
    2768             :     TXQ_NUM_SAMPLES     = 2753,
    2769             :     TXQ_WIDTH   = 2754,
    2770             :     UDIVi16ri   = 2755,
    2771             :     UDIVi16rr   = 2756,
    2772             :     UDIVi32ri   = 2757,
    2773             :     UDIVi32rr   = 2758,
    2774             :     UDIVi64ri   = 2759,
    2775             :     UDIVi64rr   = 2760,
    2776             :     UMAXi16ri   = 2761,
    2777             :     UMAXi16rr   = 2762,
    2778             :     UMAXi32ri   = 2763,
    2779             :     UMAXi32rr   = 2764,
    2780             :     UMAXi64ri   = 2765,
    2781             :     UMAXi64rr   = 2766,
    2782             :     UMINi16ri   = 2767,
    2783             :     UMINi16rr   = 2768,
    2784             :     UMINi32ri   = 2769,
    2785             :     UMINi32rr   = 2770,
    2786             :     UMINi64ri   = 2771,
    2787             :     UMINi64rr   = 2772,
    2788             :     UREMi16ri   = 2773,
    2789             :     UREMi16rr   = 2774,
    2790             :     UREMi32ri   = 2775,
    2791             :     UREMi32rr   = 2776,
    2792             :     UREMi64ri   = 2777,
    2793             :     UREMi64rr   = 2778,
    2794             :     V2F32toF64  = 2779,
    2795             :     V2I16toI32  = 2780,
    2796             :     V2I32toI64  = 2781,
    2797             :     V4I16toI64  = 2782,
    2798             :     XORb16ri    = 2783,
    2799             :     XORb16rr    = 2784,
    2800             :     XORb1ri     = 2785,
    2801             :     XORb1rr     = 2786,
    2802             :     XORb32ri    = 2787,
    2803             :     XORb32rr    = 2788,
    2804             :     XORb64ri    = 2789,
    2805             :     XORb64rr    = 2790,
    2806             :     cvta_const_no       = 2791,
    2807             :     cvta_const_no_64    = 2792,
    2808             :     cvta_const_yes      = 2793,
    2809             :     cvta_const_yes_64   = 2794,
    2810             :     cvta_global_no      = 2795,
    2811             :     cvta_global_no_64   = 2796,
    2812             :     cvta_global_yes     = 2797,
    2813             :     cvta_global_yes_64  = 2798,
    2814             :     cvta_local_no       = 2799,
    2815             :     cvta_local_no_64    = 2800,
    2816             :     cvta_local_yes      = 2801,
    2817             :     cvta_local_yes_64   = 2802,
    2818             :     cvta_shared_no      = 2803,
    2819             :     cvta_shared_no_64   = 2804,
    2820             :     cvta_shared_yes     = 2805,
    2821             :     cvta_shared_yes_64  = 2806,
    2822             :     cvta_to_const_no    = 2807,
    2823             :     cvta_to_const_no_64 = 2808,
    2824             :     cvta_to_const_yes   = 2809,
    2825             :     cvta_to_const_yes_64        = 2810,
    2826             :     cvta_to_global_no   = 2811,
    2827             :     cvta_to_global_no_64        = 2812,
    2828             :     cvta_to_global_yes  = 2813,
    2829             :     cvta_to_global_yes_64       = 2814,
    2830             :     cvta_to_local_no    = 2815,
    2831             :     cvta_to_local_no_64 = 2816,
    2832             :     cvta_to_local_yes   = 2817,
    2833             :     cvta_to_local_yes_64        = 2818,
    2834             :     cvta_to_shared_no   = 2819,
    2835             :     cvta_to_shared_no_64        = 2820,
    2836             :     cvta_to_shared_yes  = 2821,
    2837             :     cvta_to_shared_yes_64       = 2822,
    2838             :     nvvm_move_double    = 2823,
    2839             :     nvvm_move_float     = 2824,
    2840             :     nvvm_move_i16       = 2825,
    2841             :     nvvm_move_i32       = 2826,
    2842             :     nvvm_move_i64       = 2827,
    2843             :     nvvm_move_ptr32     = 2828,
    2844             :     nvvm_move_ptr64     = 2829,
    2845             :     nvvm_ptr_gen_to_param       = 2830,
    2846             :     nvvm_ptr_gen_to_param_64    = 2831,
    2847             :     texsurf_handles     = 2832,
    2848             :     trapinst    = 2833,
    2849             :     INSTRUCTION_LIST_END = 2834
    2850             :   };
    2851             : 
    2852             : namespace Sched {
    2853             :   enum {
    2854             :     NoInstrModel        = 0,
    2855             :     SCHED_LIST_END = 1
    2856             :   };
    2857             : } // end Sched namespace
    2858             : } // end NVPTX namespace
    2859             : } // end llvm namespace
    2860             : #endif // GET_INSTRINFO_ENUM
    2861             : 
    2862             : #ifdef GET_INSTRINFO_MC_DESC
    2863             : #undef GET_INSTRINFO_MC_DESC
    2864             : namespace llvm {
    2865             : 
    2866             : 
    2867             : static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2868             : static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    2869             : static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    2870             : static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    2871             : static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    2872             : static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2873             : static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    2874             : static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    2875             : static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
    2876             : static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    2877             : static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
    2878             : static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
    2879             : static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2880             : static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2881             : static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2882             : static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
    2883             : static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
    2884             : static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
    2885             : static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
    2886             : static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
    2887             : static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
    2888             : static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
    2889             : static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2890             : static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
    2891             : static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
    2892             : static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
    2893             : static const MCOperandInfo OperandInfo28[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2894             : static const MCOperandInfo OperandInfo29[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2895             : static const MCOperandInfo OperandInfo30[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2896             : static const MCOperandInfo OperandInfo31[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    2897             : static const MCOperandInfo OperandInfo32[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2898             : static const MCOperandInfo OperandInfo33[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    2899             : static const MCOperandInfo OperandInfo34[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2900             : static const MCOperandInfo OperandInfo35[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    2901             : static const MCOperandInfo OperandInfo36[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2902             : static const MCOperandInfo OperandInfo37[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    2903             : static const MCOperandInfo OperandInfo38[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2904             : static const MCOperandInfo OperandInfo39[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    2905             : static const MCOperandInfo OperandInfo40[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    2906             : static const MCOperandInfo OperandInfo41[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2907             : static const MCOperandInfo OperandInfo42[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    2908             : static const MCOperandInfo OperandInfo43[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    2909             : static const MCOperandInfo OperandInfo44[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2910             : static const MCOperandInfo OperandInfo45[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2911             : static const MCOperandInfo OperandInfo46[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2912             : static const MCOperandInfo OperandInfo47[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2913             : static const MCOperandInfo OperandInfo48[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2914             : static const MCOperandInfo OperandInfo49[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2915             : static const MCOperandInfo OperandInfo50[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2916             : static const MCOperandInfo OperandInfo51[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2917             : static const MCOperandInfo OperandInfo52[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2918             : static const MCOperandInfo OperandInfo53[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2919             : static const MCOperandInfo OperandInfo54[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    2920             : static const MCOperandInfo OperandInfo55[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2921             : static const MCOperandInfo OperandInfo56[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2922             : static const MCOperandInfo OperandInfo57[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2923             : static const MCOperandInfo OperandInfo58[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2924             : static const MCOperandInfo OperandInfo59[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2925             : static const MCOperandInfo OperandInfo60[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2926             : static const MCOperandInfo OperandInfo61[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2927             : static const MCOperandInfo OperandInfo62[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2928             : static const MCOperandInfo OperandInfo63[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2929             : static const MCOperandInfo OperandInfo64[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2930             : static const MCOperandInfo OperandInfo65[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2931             : static const MCOperandInfo OperandInfo66[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2932             : static const MCOperandInfo OperandInfo67[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2933             : static const MCOperandInfo OperandInfo68[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2934             : static const MCOperandInfo OperandInfo69[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2935             : static const MCOperandInfo OperandInfo70[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2936             : static const MCOperandInfo OperandInfo71[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2937             : static const MCOperandInfo OperandInfo72[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2938             : static const MCOperandInfo OperandInfo73[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2939             : static const MCOperandInfo OperandInfo74[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2940             : static const MCOperandInfo OperandInfo75[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2941             : static const MCOperandInfo OperandInfo76[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2942             : static const MCOperandInfo OperandInfo77[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2943             : static const MCOperandInfo OperandInfo78[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2944             : static const MCOperandInfo OperandInfo79[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2945             : static const MCOperandInfo OperandInfo80[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2946             : static const MCOperandInfo OperandInfo81[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2947             : static const MCOperandInfo OperandInfo82[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2948             : static const MCOperandInfo OperandInfo83[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2949             : static const MCOperandInfo OperandInfo84[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2950             : static const MCOperandInfo OperandInfo85[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2951             : static const MCOperandInfo OperandInfo86[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2952             : static const MCOperandInfo OperandInfo87[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2953             : static const MCOperandInfo OperandInfo88[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2954             : static const MCOperandInfo OperandInfo89[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2955             : static const MCOperandInfo OperandInfo90[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2956             : static const MCOperandInfo OperandInfo91[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2957             : static const MCOperandInfo OperandInfo92[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2958             : static const MCOperandInfo OperandInfo93[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    2959             : static const MCOperandInfo OperandInfo94[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2960             : static const MCOperandInfo OperandInfo95[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2961             : static const MCOperandInfo OperandInfo96[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2962             : static const MCOperandInfo OperandInfo97[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2963             : static const MCOperandInfo OperandInfo98[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2964             : static const MCOperandInfo OperandInfo99[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    2965             : static const MCOperandInfo OperandInfo100[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2966             : static const MCOperandInfo OperandInfo101[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2967             : static const MCOperandInfo OperandInfo102[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2968             : static const MCOperandInfo OperandInfo103[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2969             : static const MCOperandInfo OperandInfo104[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2970             : static const MCOperandInfo OperandInfo105[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    2971             : static const MCOperandInfo OperandInfo106[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2972             : static const MCOperandInfo OperandInfo107[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    2973             : static const MCOperandInfo OperandInfo108[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2974             : static const MCOperandInfo OperandInfo109[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2975             : static const MCOperandInfo OperandInfo110[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2976             : static const MCOperandInfo OperandInfo111[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2977             : static const MCOperandInfo OperandInfo112[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2978             : static const MCOperandInfo OperandInfo113[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    2979             : static const MCOperandInfo OperandInfo114[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2980             : static const MCOperandInfo OperandInfo115[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    2981             : static const MCOperandInfo OperandInfo116[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2982             : static const MCOperandInfo OperandInfo117[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    2983             : static const MCOperandInfo OperandInfo118[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2984             : static const MCOperandInfo OperandInfo119[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    2985             : static const MCOperandInfo OperandInfo120[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2986             : static const MCOperandInfo OperandInfo121[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2987             : static const MCOperandInfo OperandInfo122[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    2988             : static const MCOperandInfo OperandInfo123[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    2989             : static const MCOperandInfo OperandInfo124[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2990             : static const MCOperandInfo OperandInfo125[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2991             : static const MCOperandInfo OperandInfo126[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2992             : static const MCOperandInfo OperandInfo127[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    2993             : static const MCOperandInfo OperandInfo128[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    2994             : static const MCOperandInfo OperandInfo129[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2995             : static const MCOperandInfo OperandInfo130[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    2996             : static const MCOperandInfo OperandInfo131[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    2997             : static const MCOperandInfo OperandInfo132[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2998             : static const MCOperandInfo OperandInfo133[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    2999             : static const MCOperandInfo OperandInfo134[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3000             : static const MCOperandInfo OperandInfo135[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3001             : static const MCOperandInfo OperandInfo136[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3002             : static const MCOperandInfo OperandInfo137[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3003             : static const MCOperandInfo OperandInfo138[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3004             : static const MCOperandInfo OperandInfo139[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3005             : static const MCOperandInfo OperandInfo140[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3006             : static const MCOperandInfo OperandInfo141[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3007             : static const MCOperandInfo OperandInfo142[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3008             : static const MCOperandInfo OperandInfo143[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3009             : static const MCOperandInfo OperandInfo144[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3010             : static const MCOperandInfo OperandInfo145[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3011             : static const MCOperandInfo OperandInfo146[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3012             : static const MCOperandInfo OperandInfo147[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3013             : static const MCOperandInfo OperandInfo148[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3014             : static const MCOperandInfo OperandInfo149[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3015             : static const MCOperandInfo OperandInfo150[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3016             : static const MCOperandInfo OperandInfo151[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3017             : static const MCOperandInfo OperandInfo152[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3018             : static const MCOperandInfo OperandInfo153[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3019             : static const MCOperandInfo OperandInfo154[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3020             : static const MCOperandInfo OperandInfo155[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3021             : static const MCOperandInfo OperandInfo156[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3022             : static const MCOperandInfo OperandInfo157[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3023             : static const MCOperandInfo OperandInfo158[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3024             : static const MCOperandInfo OperandInfo159[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3025             : static const MCOperandInfo OperandInfo160[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3026             : static const MCOperandInfo OperandInfo161[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3027             : static const MCOperandInfo OperandInfo162[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3028             : static const MCOperandInfo OperandInfo163[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3029             : static const MCOperandInfo OperandInfo164[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3030             : static const MCOperandInfo OperandInfo165[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3031             : static const MCOperandInfo OperandInfo166[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3032             : static const MCOperandInfo OperandInfo167[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3033             : static const MCOperandInfo OperandInfo168[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3034             : static const MCOperandInfo OperandInfo169[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3035             : static const MCOperandInfo OperandInfo170[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3036             : static const MCOperandInfo OperandInfo171[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3037             : static const MCOperandInfo OperandInfo172[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3038             : static const MCOperandInfo OperandInfo173[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3039             : static const MCOperandInfo OperandInfo174[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3040             : static const MCOperandInfo OperandInfo175[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3041             : static const MCOperandInfo OperandInfo176[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3042             : static const MCOperandInfo OperandInfo177[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3043             : static const MCOperandInfo OperandInfo178[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3044             : static const MCOperandInfo OperandInfo179[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3045             : static const MCOperandInfo OperandInfo180[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3046             : static const MCOperandInfo OperandInfo181[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3047             : static const MCOperandInfo OperandInfo182[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3048             : static const MCOperandInfo OperandInfo183[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3049             : static const MCOperandInfo OperandInfo184[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3050             : static const MCOperandInfo OperandInfo185[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3051             : static const MCOperandInfo OperandInfo186[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3052             : static const MCOperandInfo OperandInfo187[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3053             : static const MCOperandInfo OperandInfo188[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3054             : static const MCOperandInfo OperandInfo189[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3055             : static const MCOperandInfo OperandInfo190[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3056             : static const MCOperandInfo OperandInfo191[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3057             : static const MCOperandInfo OperandInfo192[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3058             : static const MCOperandInfo OperandInfo193[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3059             : static const MCOperandInfo OperandInfo194[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3060             : static const MCOperandInfo OperandInfo195[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3061             : static const MCOperandInfo OperandInfo196[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3062             : static const MCOperandInfo OperandInfo197[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3063             : static const MCOperandInfo OperandInfo198[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3064             : static const MCOperandInfo OperandInfo199[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3065             : static const MCOperandInfo OperandInfo200[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3066             : static const MCOperandInfo OperandInfo201[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3067             : static const MCOperandInfo OperandInfo202[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3068             : static const MCOperandInfo OperandInfo203[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3069             : static const MCOperandInfo OperandInfo204[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3070             : static const MCOperandInfo OperandInfo205[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3071             : static const MCOperandInfo OperandInfo206[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3072             : static const MCOperandInfo OperandInfo207[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3073             : static const MCOperandInfo OperandInfo208[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3074             : static const MCOperandInfo OperandInfo209[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3075             : static const MCOperandInfo OperandInfo210[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3076             : static const MCOperandInfo OperandInfo211[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3077             : static const MCOperandInfo OperandInfo212[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3078             : static const MCOperandInfo OperandInfo213[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3079             : static const MCOperandInfo OperandInfo214[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3080             : static const MCOperandInfo OperandInfo215[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3081             : static const MCOperandInfo OperandInfo216[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3082             : static const MCOperandInfo OperandInfo217[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3083             : static const MCOperandInfo OperandInfo218[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3084             : static const MCOperandInfo OperandInfo219[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3085             : static const MCOperandInfo OperandInfo220[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3086             : static const MCOperandInfo OperandInfo221[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3087             : static const MCOperandInfo OperandInfo222[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3088             : static const MCOperandInfo OperandInfo223[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3089             : static const MCOperandInfo OperandInfo224[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3090             : static const MCOperandInfo OperandInfo225[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3091             : static const MCOperandInfo OperandInfo226[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3092             : static const MCOperandInfo OperandInfo227[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3093             : static const MCOperandInfo OperandInfo228[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3094             : static const MCOperandInfo OperandInfo229[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3095             : static const MCOperandInfo OperandInfo230[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3096             : static const MCOperandInfo OperandInfo231[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3097             : static const MCOperandInfo OperandInfo232[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3098             : static const MCOperandInfo OperandInfo233[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3099             : static const MCOperandInfo OperandInfo234[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3100             : static const MCOperandInfo OperandInfo235[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3101             : static const MCOperandInfo OperandInfo236[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3102             : static const MCOperandInfo OperandInfo237[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3103             : static const MCOperandInfo OperandInfo238[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3104             : static const MCOperandInfo OperandInfo239[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3105             : static const MCOperandInfo OperandInfo240[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3106             : static const MCOperandInfo OperandInfo241[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3107             : static const MCOperandInfo OperandInfo242[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3108             : static const MCOperandInfo OperandInfo243[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3109             : static const MCOperandInfo OperandInfo244[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3110             : static const MCOperandInfo OperandInfo245[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3111             : static const MCOperandInfo OperandInfo246[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3112             : static const MCOperandInfo OperandInfo247[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3113             : static const MCOperandInfo OperandInfo248[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3114             : static const MCOperandInfo OperandInfo249[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3115             : static const MCOperandInfo OperandInfo250[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3116             : static const MCOperandInfo OperandInfo251[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3117             : static const MCOperandInfo OperandInfo252[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3118             : static const MCOperandInfo OperandInfo253[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3119             : static const MCOperandInfo OperandInfo254[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3120             : static const MCOperandInfo OperandInfo255[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3121             : static const MCOperandInfo OperandInfo256[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3122             : static const MCOperandInfo OperandInfo257[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3123             : static const MCOperandInfo OperandInfo258[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3124             : static const MCOperandInfo OperandInfo259[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3125             : static const MCOperandInfo OperandInfo260[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3126             : static const MCOperandInfo OperandInfo261[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3127             : static const MCOperandInfo OperandInfo262[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3128             : static const MCOperandInfo OperandInfo263[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3129             : static const MCOperandInfo OperandInfo264[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3130             : static const MCOperandInfo OperandInfo265[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3131             : static const MCOperandInfo OperandInfo266[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3132             : static const MCOperandInfo OperandInfo267[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3133             : static const MCOperandInfo OperandInfo268[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3134             : static const MCOperandInfo OperandInfo269[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3135             : static const MCOperandInfo OperandInfo270[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3136             : static const MCOperandInfo OperandInfo271[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3137             : static const MCOperandInfo OperandInfo272[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3138             : static const MCOperandInfo OperandInfo273[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3139             : static const MCOperandInfo OperandInfo274[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3140             : static const MCOperandInfo OperandInfo275[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3141             : static const MCOperandInfo OperandInfo276[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3142             : static const MCOperandInfo OperandInfo277[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3143             : static const MCOperandInfo OperandInfo278[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3144             : static const MCOperandInfo OperandInfo279[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3145             : static const MCOperandInfo OperandInfo280[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3146             : static const MCOperandInfo OperandInfo281[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3147             : static const MCOperandInfo OperandInfo282[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3148             : static const MCOperandInfo OperandInfo283[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3149             : static const MCOperandInfo OperandInfo284[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3150             : static const MCOperandInfo OperandInfo285[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3151             : static const MCOperandInfo OperandInfo286[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3152             : static const MCOperandInfo OperandInfo287[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3153             : static const MCOperandInfo OperandInfo288[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3154             : static const MCOperandInfo OperandInfo289[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3155             : static const MCOperandInfo OperandInfo290[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3156             : static const MCOperandInfo OperandInfo291[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3157             : static const MCOperandInfo OperandInfo292[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3158             : static const MCOperandInfo OperandInfo293[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3159             : static const MCOperandInfo OperandInfo294[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3160             : static const MCOperandInfo OperandInfo295[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3161             : static const MCOperandInfo OperandInfo296[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3162             : static const MCOperandInfo OperandInfo297[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3163             : static const MCOperandInfo OperandInfo298[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3164             : static const MCOperandInfo OperandInfo299[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3165             : static const MCOperandInfo OperandInfo300[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3166             : static const MCOperandInfo OperandInfo301[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3167             : static const MCOperandInfo OperandInfo302[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3168             : static const MCOperandInfo OperandInfo303[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3169             : static const MCOperandInfo OperandInfo304[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3170             : static const MCOperandInfo OperandInfo305[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3171             : static const MCOperandInfo OperandInfo306[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3172             : static const MCOperandInfo OperandInfo307[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3173             : static const MCOperandInfo OperandInfo308[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3174             : static const MCOperandInfo OperandInfo309[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3175             : static const MCOperandInfo OperandInfo310[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3176             : static const MCOperandInfo OperandInfo311[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3177             : static const MCOperandInfo OperandInfo312[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3178             : static const MCOperandInfo OperandInfo313[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3179             : static const MCOperandInfo OperandInfo314[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3180             : static const MCOperandInfo OperandInfo315[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3181             : static const MCOperandInfo OperandInfo316[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3182             : static const MCOperandInfo OperandInfo317[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3183             : static const MCOperandInfo OperandInfo318[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3184             : static const MCOperandInfo OperandInfo319[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3185             : static const MCOperandInfo OperandInfo320[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3186             : static const MCOperandInfo OperandInfo321[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3187             : static const MCOperandInfo OperandInfo322[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3188             : static const MCOperandInfo OperandInfo323[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3189             : static const MCOperandInfo OperandInfo324[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3190             : static const MCOperandInfo OperandInfo325[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3191             : static const MCOperandInfo OperandInfo326[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3192             : static const MCOperandInfo OperandInfo327[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3193             : static const MCOperandInfo OperandInfo328[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3194             : static const MCOperandInfo OperandInfo329[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3195             : static const MCOperandInfo OperandInfo330[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3196             : static const MCOperandInfo OperandInfo331[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3197             : static const MCOperandInfo OperandInfo332[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3198             : static const MCOperandInfo OperandInfo333[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3199             : static const MCOperandInfo OperandInfo334[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3200             : static const MCOperandInfo OperandInfo335[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3201             : static const MCOperandInfo OperandInfo336[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3202             : static const MCOperandInfo OperandInfo337[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3203             : static const MCOperandInfo OperandInfo338[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3204             : static const MCOperandInfo OperandInfo339[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3205             : static const MCOperandInfo OperandInfo340[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3206             : static const MCOperandInfo OperandInfo341[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3207             : static const MCOperandInfo OperandInfo342[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3208             : static const MCOperandInfo OperandInfo343[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3209             : static const MCOperandInfo OperandInfo344[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3210             : static const MCOperandInfo OperandInfo345[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3211             : static const MCOperandInfo OperandInfo346[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3212             : static const MCOperandInfo OperandInfo347[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3213             : static const MCOperandInfo OperandInfo348[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3214             : static const MCOperandInfo OperandInfo349[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3215             : static const MCOperandInfo OperandInfo350[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3216             : static const MCOperandInfo OperandInfo351[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3217             : static const MCOperandInfo OperandInfo352[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3218             : static const MCOperandInfo OperandInfo353[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3219             : static const MCOperandInfo OperandInfo354[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3220             : static const MCOperandInfo OperandInfo355[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3221             : static const MCOperandInfo OperandInfo356[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3222             : static const MCOperandInfo OperandInfo357[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3223             : static const MCOperandInfo OperandInfo358[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3224             : static const MCOperandInfo OperandInfo359[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3225             : static const MCOperandInfo OperandInfo360[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3226             : static const MCOperandInfo OperandInfo361[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3227             : static const MCOperandInfo OperandInfo362[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3228             : static const MCOperandInfo OperandInfo363[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3229             : static const MCOperandInfo OperandInfo364[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3230             : static const MCOperandInfo OperandInfo365[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3231             : static const MCOperandInfo OperandInfo366[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3232             : static const MCOperandInfo OperandInfo367[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3233             : static const MCOperandInfo OperandInfo368[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3234             : static const MCOperandInfo OperandInfo369[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3235             : static const MCOperandInfo OperandInfo370[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3236             : static const MCOperandInfo OperandInfo371[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3237             : static const MCOperandInfo OperandInfo372[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3238             : static const MCOperandInfo OperandInfo373[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3239             : static const MCOperandInfo OperandInfo374[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3240             : static const MCOperandInfo OperandInfo375[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3241             : static const MCOperandInfo OperandInfo376[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3242             : static const MCOperandInfo OperandInfo377[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3243             : static const MCOperandInfo OperandInfo378[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3244             : static const MCOperandInfo OperandInfo379[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::SpecialRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3245             : static const MCOperandInfo OperandInfo380[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3246             : static const MCOperandInfo OperandInfo381[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3247             : static const MCOperandInfo OperandInfo382[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3248             : static const MCOperandInfo OperandInfo383[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3249             : static const MCOperandInfo OperandInfo384[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3250             : static const MCOperandInfo OperandInfo385[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3251             : static const MCOperandInfo OperandInfo386[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3252             : static const MCOperandInfo OperandInfo387[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3253             : static const MCOperandInfo OperandInfo388[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3254             : static const MCOperandInfo OperandInfo389[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3255             : static const MCOperandInfo OperandInfo390[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3256             : static const MCOperandInfo OperandInfo391[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3257             : static const MCOperandInfo OperandInfo392[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3258             : static const MCOperandInfo OperandInfo393[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3259             : static const MCOperandInfo OperandInfo394[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3260             : static const MCOperandInfo OperandInfo395[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3261             : static const MCOperandInfo OperandInfo396[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3262             : static const MCOperandInfo OperandInfo397[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3263             : static const MCOperandInfo OperandInfo398[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3264             : static const MCOperandInfo OperandInfo399[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3265             : static const MCOperandInfo OperandInfo400[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3266             : static const MCOperandInfo OperandInfo401[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3267             : static const MCOperandInfo OperandInfo402[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3268             : static const MCOperandInfo OperandInfo403[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3269             : static const MCOperandInfo OperandInfo404[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3270             : static const MCOperandInfo OperandInfo405[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3271             : static const MCOperandInfo OperandInfo406[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3272             : static const MCOperandInfo OperandInfo407[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3273             : static const MCOperandInfo OperandInfo408[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3274             : static const MCOperandInfo OperandInfo409[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3275             : static const MCOperandInfo OperandInfo410[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3276             : static const MCOperandInfo OperandInfo411[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3277             : static const MCOperandInfo OperandInfo412[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3278             : static const MCOperandInfo OperandInfo413[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3279             : static const MCOperandInfo OperandInfo414[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3280             : static const MCOperandInfo OperandInfo415[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3281             : static const MCOperandInfo OperandInfo416[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3282             : static const MCOperandInfo OperandInfo417[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3283             : static const MCOperandInfo OperandInfo418[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3284             : static const MCOperandInfo OperandInfo419[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3285             : static const MCOperandInfo OperandInfo420[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3286             : static const MCOperandInfo OperandInfo421[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3287             : static const MCOperandInfo OperandInfo422[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3288             : static const MCOperandInfo OperandInfo423[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3289             : static const MCOperandInfo OperandInfo424[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3290             : static const MCOperandInfo OperandInfo425[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3291             : static const MCOperandInfo OperandInfo426[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3292             : static const MCOperandInfo OperandInfo427[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3293             : static const MCOperandInfo OperandInfo428[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3294             : static const MCOperandInfo OperandInfo429[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3295             : static const MCOperandInfo OperandInfo430[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3296             : static const MCOperandInfo OperandInfo431[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3297             : static const MCOperandInfo OperandInfo432[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3298             : static const MCOperandInfo OperandInfo433[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3299             : static const MCOperandInfo OperandInfo434[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3300             : static const MCOperandInfo OperandInfo435[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3301             : static const MCOperandInfo OperandInfo436[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3302             : static const MCOperandInfo OperandInfo437[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3303             : static const MCOperandInfo OperandInfo438[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3304             : static const MCOperandInfo OperandInfo439[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3305             : static const MCOperandInfo OperandInfo440[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3306             : static const MCOperandInfo OperandInfo441[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3307             : static const MCOperandInfo OperandInfo442[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    3308             : static const MCOperandInfo OperandInfo443[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3309             : static const MCOperandInfo OperandInfo444[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3310             : static const MCOperandInfo OperandInfo445[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3311             : static const MCOperandInfo OperandInfo446[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3312             : static const MCOperandInfo OperandInfo447[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3313             : static const MCOperandInfo OperandInfo448[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3314             : static const MCOperandInfo OperandInfo449[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3315             : static const MCOperandInfo OperandInfo450[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3316             : static const MCOperandInfo OperandInfo451[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3317             : static const MCOperandInfo OperandInfo452[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3318             : static const MCOperandInfo OperandInfo453[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3319             : static const MCOperandInfo OperandInfo454[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3320             : static const MCOperandInfo OperandInfo455[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3321             : static const MCOperandInfo OperandInfo456[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3322             : static const MCOperandInfo OperandInfo457[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3323             : static const MCOperandInfo OperandInfo458[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3324             : static const MCOperandInfo OperandInfo459[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3325             : static const MCOperandInfo OperandInfo460[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3326             : static const MCOperandInfo OperandInfo461[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3327             : static const MCOperandInfo OperandInfo462[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3328             : static const MCOperandInfo OperandInfo463[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3329             : static const MCOperandInfo OperandInfo464[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3330             : static const MCOperandInfo OperandInfo465[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3331             : static const MCOperandInfo OperandInfo466[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3332             : static const MCOperandInfo OperandInfo467[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3333             : static const MCOperandInfo OperandInfo468[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3334             : static const MCOperandInfo OperandInfo469[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3335             : static const MCOperandInfo OperandInfo470[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3336             : static const MCOperandInfo OperandInfo471[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3337             : static const MCOperandInfo OperandInfo472[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3338             : static const MCOperandInfo OperandInfo473[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3339             : static const MCOperandInfo OperandInfo474[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3340             : static const MCOperandInfo OperandInfo475[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3341             : static const MCOperandInfo OperandInfo476[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3342             : static const MCOperandInfo OperandInfo477[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3343             : static const MCOperandInfo OperandInfo478[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3344             : static const MCOperandInfo OperandInfo479[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3345             : static const MCOperandInfo OperandInfo480[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3346             : static const MCOperandInfo OperandInfo481[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3347             : static const MCOperandInfo OperandInfo482[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3348             : static const MCOperandInfo OperandInfo483[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3349             : static const MCOperandInfo OperandInfo484[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3350             : static const MCOperandInfo OperandInfo485[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3351             : static const MCOperandInfo OperandInfo486[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3352             : static const MCOperandInfo OperandInfo487[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3353             : static const MCOperandInfo OperandInfo488[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3354             : static const MCOperandInfo OperandInfo489[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3355             : static const MCOperandInfo OperandInfo490[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3356             : static const MCOperandInfo OperandInfo491[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3357             : static const MCOperandInfo OperandInfo492[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3358             : static const MCOperandInfo OperandInfo493[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3359             : static const MCOperandInfo OperandInfo494[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3360             : static const MCOperandInfo OperandInfo495[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    3361             : static const MCOperandInfo OperandInfo496[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3362             : static const MCOperandInfo OperandInfo497[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3363             : static const MCOperandInfo OperandInfo498[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3364             : static const MCOperandInfo OperandInfo499[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3365             : static const MCOperandInfo OperandInfo500[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3366             : static const MCOperandInfo OperandInfo501[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3367             : static const MCOperandInfo OperandInfo502[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3368             : static const MCOperandInfo OperandInfo503[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3369             : static const MCOperandInfo OperandInfo504[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3370             : static const MCOperandInfo OperandInfo505[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3371             : static const MCOperandInfo OperandInfo506[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3372             : static const MCOperandInfo OperandInfo507[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3373             : static const MCOperandInfo OperandInfo508[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3374             : static const MCOperandInfo OperandInfo509[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3375             : static const MCOperandInfo OperandInfo510[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3376             : static const MCOperandInfo OperandInfo511[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3377             : static const MCOperandInfo OperandInfo512[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3378             : static const MCOperandInfo OperandInfo513[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3379             : static const MCOperandInfo OperandInfo514[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3380             : static const MCOperandInfo OperandInfo515[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3381             : static const MCOperandInfo OperandInfo516[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3382             : static const MCOperandInfo OperandInfo517[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3383             : static const MCOperandInfo OperandInfo518[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3384             : static const MCOperandInfo OperandInfo519[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3385             : static const MCOperandInfo OperandInfo520[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3386             : static const MCOperandInfo OperandInfo521[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3387             : static const MCOperandInfo OperandInfo522[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3388             : static const MCOperandInfo OperandInfo523[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3389             : static const MCOperandInfo OperandInfo524[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3390             : static const MCOperandInfo OperandInfo525[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3391             : static const MCOperandInfo OperandInfo526[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3392             : static const MCOperandInfo OperandInfo527[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3393             : static const MCOperandInfo OperandInfo528[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3394             : static const MCOperandInfo OperandInfo529[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3395             : static const MCOperandInfo OperandInfo530[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3396             : static const MCOperandInfo OperandInfo531[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3397             : static const MCOperandInfo OperandInfo532[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3398             : static const MCOperandInfo OperandInfo533[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3399             : static const MCOperandInfo OperandInfo534[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3400             : static const MCOperandInfo OperandInfo535[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3401             : static const MCOperandInfo OperandInfo536[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3402             : static const MCOperandInfo OperandInfo537[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3403             : static const MCOperandInfo OperandInfo538[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3404             : static const MCOperandInfo OperandInfo539[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3405             : static const MCOperandInfo OperandInfo540[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3406             : static const MCOperandInfo OperandInfo541[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3407             : static const MCOperandInfo OperandInfo542[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3408             : static const MCOperandInfo OperandInfo543[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3409             : static const MCOperandInfo OperandInfo544[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3410             : static const MCOperandInfo OperandInfo545[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3411             : static const MCOperandInfo OperandInfo546[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3412             : static const MCOperandInfo OperandInfo547[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3413             : static const MCOperandInfo OperandInfo548[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3414             : static const MCOperandInfo OperandInfo549[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3415             : static const MCOperandInfo OperandInfo550[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    3416             : 
    3417             : extern const MCInstrDesc NVPTXInsts[] = {
    3418             :   { 0,  1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #0 = PHI
    3419             :   { 1,  0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
    3420             :   { 2,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #2 = CFI_INSTRUCTION
    3421             :   { 3,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #3 = EH_LABEL
    3422             :   { 4,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #4 = GC_LABEL
    3423             :   { 5,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #5 = ANNOTATION_LABEL
    3424             :   { 6,  0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #6 = KILL
    3425             :   { 7,  3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #7 = EXTRACT_SUBREG
    3426             :   { 8,  4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #8 = INSERT_SUBREG
    3427             :   { 9,  1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #9 = IMPLICIT_DEF
    3428             :   { 10, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #10 = SUBREG_TO_REG
    3429             :   { 11, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #11 = COPY_TO_REGCLASS
    3430             :   { 12, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #12 = DBG_VALUE
    3431             :   { 13, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #13 = REG_SEQUENCE
    3432             :   { 14, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #14 = COPY
    3433             :   { 15, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #15 = BUNDLE
    3434             :   { 16, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #16 = LIFETIME_START
    3435             :   { 17, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #17 = LIFETIME_END
    3436             :   { 18, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #18 = STACKMAP
    3437             :   { 19, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #19 = FENTRY_CALL
    3438             :   { 20, 6,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #20 = PATCHPOINT
    3439             :   { 21, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #21 = LOAD_STACK_GUARD
    3440             :   { 22, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #22 = STATEPOINT
    3441             :   { 23, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #23 = LOCAL_ESCAPE
    3442             :   { 24, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #24 = FAULTING_OP
    3443             :   { 25, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #25 = PATCHABLE_OP
    3444             :   { 26, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #26 = PATCHABLE_FUNCTION_ENTER
    3445             :   { 27, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #27 = PATCHABLE_RET
    3446             :   { 28, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #28 = PATCHABLE_FUNCTION_EXIT
    3447             :   { 29, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #29 = PATCHABLE_TAIL_CALL
    3448             :   { 30, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #30 = PATCHABLE_EVENT_CALL
    3449             :   { 31, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #31 = G_ADD
    3450             :   { 32, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #32 = G_SUB
    3451             :   { 33, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #33 = G_MUL
    3452             :   { 34, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #34 = G_SDIV
    3453             :   { 35, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #35 = G_UDIV
    3454             :   { 36, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #36 = G_SREM
    3455             :   { 37, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #37 = G_UREM
    3456             :   { 38, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #38 = G_AND
    3457             :   { 39, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #39 = G_OR
    3458             :   { 40, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #40 = G_XOR
    3459             :   { 41, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #41 = G_IMPLICIT_DEF
    3460             :   { 42, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #42 = G_PHI
    3461             :   { 43, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #43 = G_FRAME_INDEX
    3462             :   { 44, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #44 = G_GLOBAL_VALUE
    3463             :   { 45, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #45 = G_EXTRACT
    3464             :   { 46, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #46 = G_UNMERGE_VALUES
    3465             :   { 47, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #47 = G_INSERT
    3466             :   { 48, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #48 = G_MERGE_VALUES
    3467             :   { 49, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #49 = G_PTRTOINT
    3468             :   { 50, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #50 = G_INTTOPTR
    3469             :   { 51, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #51 = G_BITCAST
    3470             :   { 52, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #52 = G_LOAD
    3471             :   { 53, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #53 = G_STORE
    3472             :   { 54, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #54 = G_BRCOND
    3473             :   { 55, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #55 = G_BRINDIRECT
    3474             :   { 56, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #56 = G_INTRINSIC
    3475             :   { 57, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #57 = G_INTRINSIC_W_SIDE_EFFECTS
    3476             :   { 58, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #58 = G_ANYEXT
    3477             :   { 59, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #59 = G_TRUNC
    3478             :   { 60, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #60 = G_CONSTANT
    3479             :   { 61, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #61 = G_FCONSTANT
    3480             :   { 62, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #62 = G_VASTART
    3481             :   { 63, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #63 = G_VAARG
    3482             :   { 64, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #64 = G_SEXT
    3483             :   { 65, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #65 = G_ZEXT
    3484             :   { 66, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #66 = G_SHL
    3485             :   { 67, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #67 = G_LSHR
    3486             :   { 68, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #68 = G_ASHR
    3487             :   { 69, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #69 = G_ICMP
    3488             :   { 70, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #70 = G_FCMP
    3489             :   { 71, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #71 = G_SELECT
    3490             :   { 72, 5,      2,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #72 = G_UADDE
    3491             :   { 73, 5,      2,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #73 = G_USUBE
    3492             :   { 74, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #74 = G_SADDO
    3493             :   { 75, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #75 = G_SSUBO
    3494             :   { 76, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #76 = G_UMULO
    3495             :   { 77, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #77 = G_SMULO
    3496             :   { 78, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #78 = G_UMULH
    3497             :   { 79, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #79 = G_SMULH
    3498             :   { 80, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #80 = G_FADD
    3499             :   { 81, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #81 = G_FSUB
    3500             :   { 82, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #82 = G_FMUL
    3501             :   { 83, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #83 = G_FMA
    3502             :   { 84, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #84 = G_FDIV
    3503             :   { 85, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #85 = G_FREM
    3504             :   { 86, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #86 = G_FPOW
    3505             :   { 87, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #87 = G_FEXP
    3506             :   { 88, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #88 = G_FEXP2
    3507             :   { 89, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #89 = G_FLOG
    3508             :   { 90, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #90 = G_FLOG2
    3509             :   { 91, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #91 = G_FNEG
    3510             :   { 92, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #92 = G_FPEXT
    3511             :   { 93, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #93 = G_FPTRUNC
    3512             :   { 94, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #94 = G_FPTOSI
    3513             :   { 95, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #95 = G_FPTOUI
    3514             :   { 96, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #96 = G_SITOFP
    3515             :   { 97, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #97 = G_UITOFP
    3516             :   { 98, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #98 = G_GEP
    3517             :   { 99, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #99 = G_PTR_MASK
    3518             :   { 100,        1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #100 = G_BR
    3519             :   { 101,        4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #101 = G_INSERT_VECTOR_ELT
    3520             :   { 102,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #102 = G_EXTRACT_VECTOR_ELT
    3521             :   { 103,        4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #103 = G_SHUFFLE_VECTOR
    3522             :   { 104,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #104 = ABS_16anonymous_636
    3523             :   { 105,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #105 = ABS_32anonymous_636
    3524             :   { 106,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #106 = ABS_64anonymous_636
    3525             :   { 107,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #107 = ADDCCCi32ri
    3526             :   { 108,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #108 = ADDCCCi32rr
    3527             :   { 109,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #109 = ADDCCi32ri
    3528             :   { 110,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #110 = ADDCCi32rr
    3529             :   { 111,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #111 = ADD_i1_ri
    3530             :   { 112,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #112 = ADD_i1_rr
    3531             :   { 113,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #113 = ADDi16ri
    3532             :   { 114,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #114 = ADDi16rr
    3533             :   { 115,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #115 = ADDi32ri
    3534             :   { 116,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #116 = ADDi32rr
    3535             :   { 117,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #117 = ADDi64ri
    3536             :   { 118,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #118 = ADDi64rr
    3537             :   { 119,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #119 = ANDb16ri
    3538             :   { 120,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #120 = ANDb16rr
    3539             :   { 121,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #121 = ANDb1ri
    3540             :   { 122,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #122 = ANDb1rr
    3541             :   { 123,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #123 = ANDb32ri
    3542             :   { 124,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #124 = ANDb32rr
    3543             :   { 125,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #125 = ANDb64ri
    3544             :   { 126,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #126 = ANDb64rr
    3545             :   { 127,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #127 = BFE_S32rii
    3546             :   { 128,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #128 = BFE_S32rri
    3547             :   { 129,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #129 = BFE_S32rrr
    3548             :   { 130,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #130 = BFE_S64rii
    3549             :   { 131,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #131 = BFE_S64rri
    3550             :   { 132,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #132 = BFE_S64rrr
    3551             :   { 133,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #133 = BFE_U32rii
    3552             :   { 134,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #134 = BFE_U32rri
    3553             :   { 135,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #135 = BFE_U32rrr
    3554             :   { 136,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #136 = BFE_U64rii
    3555             :   { 137,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #137 = BFE_U64rri
    3556             :   { 138,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #138 = BFE_U64rrr
    3557             :   { 139,        2,      1,      0,      0,      0|(1ULL<<MCID::Bitcast), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #139 = BITCONVERT_16_F2I
    3558             :   { 140,        2,      1,      0,      0,      0|(1ULL<<MCID::Bitcast), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #140 = BITCONVERT_16_I2F
    3559             :   { 141,        2,      1,      0,      0,      0|(1ULL<<MCID::Bitcast), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #141 = BITCONVERT_32_F16x22I
    3560             :   { 142,        2,      1,      0,      0,      0|(1ULL<<MCID::Bitcast), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #142 = BITCONVERT_32_F2I
    3561             :   { 143,        2,      1,      0,      0,      0|(1ULL<<MCID::Bitcast), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #143 = BITCONVERT_32_I2F
    3562             :   { 144,        2,      1,      0,      0,      0|(1ULL<<MCID::Bitcast), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #144 = BITCONVERT_32_I2F16x2
    3563             :   { 145,        2,      1,      0,      0,      0|(1ULL<<MCID::Bitcast), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #145 = BITCONVERT_64_F2I
    3564             :   { 146,        2,      1,      0,      0,      0|(1ULL<<MCID::Bitcast), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #146 = BITCONVERT_64_I2F
    3565             :   { 147,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #147 = BREV32
    3566             :   { 148,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #148 = BREV64
    3567             :   { 149,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #149 = BuildF16x2
    3568             :   { 150,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #150 = BuildF16x2i
    3569             :   { 151,        1,      0,      0,      0,      0|(1ULL<<MCID::Call), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #151 = CALL
    3570             :   { 152,        1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #152 = CALL_PROTOTYPE
    3571             :   { 153,        2,      0,      0,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #153 = CBranch
    3572             :   { 154,        2,      0,      0,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #154 = CBranchOther
    3573             :   { 155,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #155 = CLZr32
    3574             :   { 156,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #156 = CLZr64
    3575             :   { 157,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #157 = COSF
    3576             :   { 158,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #158 = CVT_INREG_s16_s8
    3577             :   { 159,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #159 = CVT_INREG_s32_s16
    3578             :   { 160,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #160 = CVT_INREG_s32_s8
    3579             :   { 161,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #161 = CVT_INREG_s64_s16
    3580             :   { 162,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #162 = CVT_INREG_s64_s32
    3581             :   { 163,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #163 = CVT_INREG_s64_s8
    3582             :   { 164,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #164 = CVT_f16_f16
    3583             :   { 165,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #165 = CVT_f16_f32
    3584             :   { 166,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #166 = CVT_f16_f64
    3585             :   { 167,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #167 = CVT_f16_s16
    3586             :   { 168,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr },  // Inst #168 = CVT_f16_s32
    3587             :   { 169,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #169 = CVT_f16_s64
    3588             :   { 170,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #170 = CVT_f16_s8
    3589             :   { 171,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #171 = CVT_f16_u16
    3590             :   { 172,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr },  // Inst #172 = CVT_f16_u32
    3591             :   { 173,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #173 = CVT_f16_u64
    3592             :   { 174,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #174 = CVT_f16_u8
    3593             :   { 175,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr },  // Inst #175 = CVT_f32_f16
    3594             :   { 176,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr },  // Inst #176 = CVT_f32_f32
    3595             :   { 177,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #177 = CVT_f32_f64
    3596             :   { 178,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #178 = CVT_f32_s16
    3597             :   { 179,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #179 = CVT_f32_s32
    3598             :   { 180,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #180 = CVT_f32_s64
    3599             :   { 181,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #181 = CVT_f32_s8
    3600             :   { 182,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #182 = CVT_f32_u16
    3601             :   { 183,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #183 = CVT_f32_u32
    3602             :   { 184,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #184 = CVT_f32_u64
    3603             :   { 185,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #185 = CVT_f32_u8
    3604             :   { 186,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #186 = CVT_f64_f16
    3605             :   { 187,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr },  // Inst #187 = CVT_f64_f32
    3606             :   { 188,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr },  // Inst #188 = CVT_f64_f64
    3607             :   { 189,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr },  // Inst #189 = CVT_f64_s16
    3608             :   { 190,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr },  // Inst #190 = CVT_f64_s32
    3609             :   { 191,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr },  // Inst #191 = CVT_f64_s64
    3610             :   { 192,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr },  // Inst #192 = CVT_f64_s8
    3611             :   { 193,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr },  // Inst #193 = CVT_f64_u16
    3612             :   { 194,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr },  // Inst #194 = CVT_f64_u32
    3613             :   { 195,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr },  // Inst #195 = CVT_f64_u64
    3614             :   { 196,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr },  // Inst #196 = CVT_f64_u8
    3615             :   { 197,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo76, -1 ,nullptr },  // Inst #197 = CVT_s16_f16
    3616             :   { 198,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr },  // Inst #198 = CVT_s16_f32
    3617             :   { 199,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr },  // Inst #199 = CVT_s16_f64
    3618             :   { 200,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #200 = CVT_s16_s16
    3619             :   { 201,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #201 = CVT_s16_s32
    3620             :   { 202,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #202 = CVT_s16_s64
    3621             :   { 203,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #203 = CVT_s16_s8
    3622             :   { 204,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #204 = CVT_s16_u16
    3623             :   { 205,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #205 = CVT_s16_u32
    3624             :   { 206,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #206 = CVT_s16_u64
    3625             :   { 207,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #207 = CVT_s16_u8
    3626             :   { 208,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #208 = CVT_s32_f16
    3627             :   { 209,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr },  // Inst #209 = CVT_s32_f32
    3628             :   { 210,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr },  // Inst #210 = CVT_s32_f64
    3629             :   { 211,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr },  // Inst #211 = CVT_s32_s16
    3630             :   { 212,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #212 = CVT_s32_s32
    3631             :   { 213,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #213 = CVT_s32_s64
    3632             :   { 214,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr },  // Inst #214 = CVT_s32_s8
    3633             :   { 215,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr },  // Inst #215 = CVT_s32_u16
    3634             :   { 216,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #216 = CVT_s32_u32
    3635             :   { 217,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #217 = CVT_s32_u64
    3636             :   { 218,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr },  // Inst #218 = CVT_s32_u8
    3637             :   { 219,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr },  // Inst #219 = CVT_s64_f16
    3638             :   { 220,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr },  // Inst #220 = CVT_s64_f32
    3639             :   { 221,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #221 = CVT_s64_f64
    3640             :   { 222,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #222 = CVT_s64_s16
    3641             :   { 223,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #223 = CVT_s64_s32
    3642             :   { 224,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #224 = CVT_s64_s64
    3643             :   { 225,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #225 = CVT_s64_s8
    3644             :   { 226,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #226 = CVT_s64_u16
    3645             :   { 227,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #227 = CVT_s64_u32
    3646             :   { 228,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #228 = CVT_s64_u64
    3647             :   { 229,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #229 = CVT_s64_u8
    3648             :   { 230,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo76, -1 ,nullptr },  // Inst #230 = CVT_s8_f16
    3649             :   { 231,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr },  // Inst #231 = CVT_s8_f32
    3650             :   { 232,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr },  // Inst #232 = CVT_s8_f64
    3651             :   { 233,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #233 = CVT_s8_s16
    3652             :   { 234,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #234 = CVT_s8_s32
    3653             :   { 235,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #235 = CVT_s8_s64
    3654             :   { 236,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #236 = CVT_s8_s8
    3655             :   { 237,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #237 = CVT_s8_u16
    3656             :   { 238,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #238 = CVT_s8_u32
    3657             :   { 239,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #239 = CVT_s8_u64
    3658             :   { 240,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #240 = CVT_s8_u8
    3659             :   { 241,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo76, -1 ,nullptr },  // Inst #241 = CVT_u16_f16
    3660             :   { 242,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr },  // Inst #242 = CVT_u16_f32
    3661             :   { 243,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr },  // Inst #243 = CVT_u16_f64
    3662             :   { 244,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #244 = CVT_u16_s16
    3663             :   { 245,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #245 = CVT_u16_s32
    3664             :   { 246,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #246 = CVT_u16_s64
    3665             :   { 247,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #247 = CVT_u16_s8
    3666             :   { 248,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #248 = CVT_u16_u16
    3667             :   { 249,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #249 = CVT_u16_u32
    3668             :   { 250,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #250 = CVT_u16_u64
    3669             :   { 251,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #251 = CVT_u16_u8
    3670             :   { 252,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #252 = CVT_u32_f16
    3671             :   { 253,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr },  // Inst #253 = CVT_u32_f32
    3672             :   { 254,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr },  // Inst #254 = CVT_u32_f64
    3673             :   { 255,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr },  // Inst #255 = CVT_u32_s16
    3674             :   { 256,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #256 = CVT_u32_s32
    3675             :   { 257,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #257 = CVT_u32_s64
    3676             :   { 258,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr },  // Inst #258 = CVT_u32_s8
    3677             :   { 259,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr },  // Inst #259 = CVT_u32_u16
    3678             :   { 260,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #260 = CVT_u32_u32
    3679             :   { 261,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #261 = CVT_u32_u64
    3680             :   { 262,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr },  // Inst #262 = CVT_u32_u8
    3681             :   { 263,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr },  // Inst #263 = CVT_u64_f16
    3682             :   { 264,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr },  // Inst #264 = CVT_u64_f32
    3683             :   { 265,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #265 = CVT_u64_f64
    3684             :   { 266,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #266 = CVT_u64_s16
    3685             :   { 267,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #267 = CVT_u64_s32
    3686             :   { 268,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #268 = CVT_u64_s64
    3687             :   { 269,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #269 = CVT_u64_s8
    3688             :   { 270,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #270 = CVT_u64_u16
    3689             :   { 271,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #271 = CVT_u64_u32
    3690             :   { 272,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #272 = CVT_u64_u64
    3691             :   { 273,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #273 = CVT_u64_u8
    3692             :   { 274,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo76, -1 ,nullptr },  // Inst #274 = CVT_u8_f16
    3693             :   { 275,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr },  // Inst #275 = CVT_u8_f32
    3694             :   { 276,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr },  // Inst #276 = CVT_u8_f64
    3695             :   { 277,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #277 = CVT_u8_s16
    3696             :   { 278,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #278 = CVT_u8_s32
    3697             :   { 279,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #279 = CVT_u8_s64
    3698             :   { 280,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #280 = CVT_u8_s8
    3699             :   { 281,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #281 = CVT_u8_u16
    3700             :   { 282,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #282 = CVT_u8_u32
    3701             :   { 283,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #283 = CVT_u8_u64
    3702             :   { 284,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #284 = CVT_u8_u8
    3703             :   { 285,        0,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #285 = CallArgBeginInst
    3704             :   { 286,        0,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #286 = CallArgEndInst0
    3705             :   { 287,        0,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #287 = CallArgEndInst1
    3706             :   { 288,        1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #288 = CallArgF32
    3707             :   { 289,        1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #289 = CallArgF64
    3708             :   { 290,        1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr },  // Inst #290 = CallArgI16
    3709             :   { 291,        1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #291 = CallArgI32
    3710             :   { 292,        1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #292 = CallArgI32imm
    3711             :   { 293,        1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr },  // Inst #293 = CallArgI64
    3712             :   { 294,        1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #294 = CallArgParam
    3713             :   { 295,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #295 = CallPrintCallNoRetInst
    3714             :   { 296,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #296 = CallPrintCallRetInst1
    3715             :   { 297,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #297 = CallPrintCallRetInst2
    3716             :   { 298,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #298 = CallPrintCallRetInst3
    3717             :   { 299,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #299 = CallPrintCallRetInst4
    3718             :   { 300,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #300 = CallPrintCallRetInst5
    3719             :   { 301,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #301 = CallPrintCallRetInst6
    3720             :   { 302,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #302 = CallPrintCallRetInst7
    3721             :   { 303,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #303 = CallPrintCallRetInst8
    3722             :   { 304,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #304 = CallUniPrintCallNoRetInst
    3723             :   { 305,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #305 = CallUniPrintCallRetInst1
    3724             :   { 306,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #306 = CallUniPrintCallRetInst2
    3725             :   { 307,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #307 = CallUniPrintCallRetInst3
    3726             :   { 308,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #308 = CallUniPrintCallRetInst4
    3727             :   { 309,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #309 = CallUniPrintCallRetInst5
    3728             :   { 310,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #310 = CallUniPrintCallRetInst6
    3729             :   { 311,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #311 = CallUniPrintCallRetInst7
    3730             :   { 312,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #312 = CallUniPrintCallRetInst8
    3731             :   { 313,        1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #313 = CallVoidInst
    3732             :   { 314,        1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #314 = CallVoidInstReg
    3733             :   { 315,        1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr },  // Inst #315 = CallVoidInstReg64
    3734             :   { 316,        2,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #316 = Callseq_End
    3735             :   { 317,        2,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #317 = Callseq_Start
    3736             :   { 318,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #318 = ConvergentCallPrintCallNoRetInst
    3737             :   { 319,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #319 = ConvergentCallPrintCallRetInst1
    3738             :   { 320,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #320 = ConvergentCallPrintCallRetInst2
    3739             :   { 321,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #321 = ConvergentCallPrintCallRetInst3
    3740             :   { 322,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #322 = ConvergentCallPrintCallRetInst4
    3741             :   { 323,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #323 = ConvergentCallPrintCallRetInst5
    3742             :   { 324,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #324 = ConvergentCallPrintCallRetInst6
    3743             :   { 325,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #325 = ConvergentCallPrintCallRetInst7
    3744             :   { 326,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #326 = ConvergentCallPrintCallRetInst8
    3745             :   { 327,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #327 = ConvergentCallUniPrintCallNoRetInst
    3746             :   { 328,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #328 = ConvergentCallUniPrintCallRetInst1
    3747             :   { 329,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #329 = ConvergentCallUniPrintCallRetInst2
    3748             :   { 330,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #330 = ConvergentCallUniPrintCallRetInst3
    3749             :   { 331,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #331 = ConvergentCallUniPrintCallRetInst4
    3750             :   { 332,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #332 = ConvergentCallUniPrintCallRetInst5
    3751             :   { 333,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #333 = ConvergentCallUniPrintCallRetInst6
    3752             :   { 334,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #334 = ConvergentCallUniPrintCallRetInst7
    3753             :   { 335,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #335 = ConvergentCallUniPrintCallRetInst8
    3754             :   { 336,        3,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr },  // Inst #336 = DeclareParamInst
    3755             :   { 337,        3,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr },  // Inst #337 = DeclareRetMemInst
    3756             :   { 338,        2,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #338 = DeclareRetRegInst
    3757             :   { 339,        2,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #339 = DeclareRetScalarInst
    3758             :   { 340,        2,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #340 = DeclareScalarParamInst
    3759             :   { 341,        2,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #341 = DeclareScalarRegInst
    3760             :   { 342,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #342 = F16x2toF16_0
    3761             :   { 343,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #343 = F16x2toF16_1
    3762             :   { 344,        3,      2,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #344 = F64toV2F32
    3763             :   { 345,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #345 = FABSf32
    3764             :   { 346,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #346 = FABSf32_ftz
    3765             :   { 347,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #347 = FABSf64
    3766             :   { 348,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr },  // Inst #348 = FADD_rnf16rr
    3767             :   { 349,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr },  // Inst #349 = FADD_rnf16rr_ftz
    3768             :   { 350,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr },  // Inst #350 = FADD_rnf16x2rr
    3769             :   { 351,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr },  // Inst #351 = FADD_rnf16x2rr_ftz
    3770             :   { 352,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #352 = FADD_rnf32ri
    3771             :   { 353,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #353 = FADD_rnf32ri_ftz
    3772             :   { 354,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #354 = FADD_rnf32rr
    3773             :   { 355,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #355 = FADD_rnf32rr_ftz
    3774             :   { 356,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #356 = FADD_rnf64ri
    3775             :   { 357,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #357 = FADD_rnf64rr
    3776             :   { 358,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr },  // Inst #358 = FADDf16rr
    3777             :   { 359,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr },  // Inst #359 = FADDf16rr_ftz
    3778             :   { 360,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr },  // Inst #360 = FADDf16x2rr
    3779             :   { 361,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr },  // Inst #361 = FADDf16x2rr_ftz
    3780             :   { 362,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #362 = FADDf32ri
    3781             :   { 363,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #363 = FADDf32ri_ftz
    3782             :   { 364,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #364 = FADDf32rr
    3783             :   { 365,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #365 = FADDf32rr_ftz
    3784             :   { 366,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #366 = FADDf64ri
    3785             :   { 367,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #367 = FADDf64rr
    3786             :   { 368,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #368 = FDIV321r
    3787             :   { 369,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #369 = FDIV321r_approx
    3788             :   { 370,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #370 = FDIV321r_approx_ftz
    3789             :   { 371,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #371 = FDIV321r_ftz
    3790             :   { 372,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #372 = FDIV321r_prec
    3791             :   { 373,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #373 = FDIV321r_prec_ftz
    3792             :   { 374,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #374 = FDIV32approxri
    3793             :   { 375,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #375 = FDIV32approxri_ftz
    3794             :   { 376,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #376 = FDIV32approxrr
    3795             :   { 377,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #377 = FDIV32approxrr_ftz
    3796             :   { 378,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #378 = FDIV32ri
    3797             :   { 379,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #379 = FDIV32ri_ftz
    3798             :   { 380,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #380 = FDIV32ri_prec
    3799             :   { 381,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #381 = FDIV32ri_prec_ftz
    3800             :   { 382,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #382 = FDIV32rr
    3801             :   { 383,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #383 = FDIV32rr_ftz
    3802             :   { 384,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #384 = FDIV32rr_prec
    3803             :   { 385,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #385 = FDIV32rr_prec_ftz
    3804             :   { 386,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr },  // Inst #386 = FDIV641r
    3805             :   { 387,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #387 = FDIV64ri
    3806             :   { 388,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #388 = FDIV64rr
    3807             :   { 389,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #389 = FMA16_ftzrrr
    3808             :   { 390,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #390 = FMA16rrr
    3809             :   { 391,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr },  // Inst #391 = FMA16x2_ftzrrr
    3810             :   { 392,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr },  // Inst #392 = FMA16x2rrr
    3811             :   { 393,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr },  // Inst #393 = FMA32_ftzrii
    3812             :   { 394,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #394 = FMA32_ftzrir
    3813             :   { 395,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #395 = FMA32_ftzrri
    3814             :   { 396,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #396 = FMA32_ftzrrr
    3815             :   { 397,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr },  // Inst #397 = FMA32rii
    3816             :   { 398,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #398 = FMA32rir
    3817             :   { 399,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #399 = FMA32rri
    3818             :   { 400,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #400 = FMA32rrr
    3819             :   { 401,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr },  // Inst #401 = FMA64rii
    3820             :   { 402,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #402 = FMA64rir
    3821             :   { 403,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #403 = FMA64rri
    3822             :   { 404,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #404 = FMA64rrr
    3823             :   { 405,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #405 = FMAXf32ri
    3824             :   { 406,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #406 = FMAXf32ri_ftz
    3825             :   { 407,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #407 = FMAXf32rr
    3826             :   { 408,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #408 = FMAXf32rr_ftz
    3827             :   { 409,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #409 = FMAXf64ri
    3828             :   { 410,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #410 = FMAXf64rr
    3829             :   { 411,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #411 = FMINf32ri
    3830             :   { 412,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #412 = FMINf32ri_ftz
    3831             :   { 413,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #413 = FMINf32rr
    3832             :   { 414,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #414 = FMINf32rr_ftz
    3833             :   { 415,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #415 = FMINf64ri
    3834             :   { 416,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #416 = FMINf64rr
    3835             :   { 417,        2,      1,      0,      0,      0, 0x10ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #417 = FMOV16rr
    3836             :   { 418,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #418 = FMOV32ri
    3837             :   { 419,        2,      1,      0,      0,      0, 0x10ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #419 = FMOV32rr
    3838             :   { 420,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #420 = FMOV64ri
    3839             :   { 421,        2,      1,      0,      0,      0, 0x10ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #421 = FMOV64rr
    3840             :   { 422,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr },  // Inst #422 = FMUL_rnf16rr
    3841             :   { 423,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr },  // Inst #423 = FMUL_rnf16rr_ftz
    3842             :   { 424,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr },  // Inst #424 = FMUL_rnf16x2rr
    3843             :   { 425,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr },  // Inst #425 = FMUL_rnf16x2rr_ftz
    3844             :   { 426,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #426 = FMUL_rnf32ri
    3845             :   { 427,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #427 = FMUL_rnf32ri_ftz
    3846             :   { 428,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #428 = FMUL_rnf32rr
    3847             :   { 429,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #429 = FMUL_rnf32rr_ftz
    3848             :   { 430,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #430 = FMUL_rnf64ri
    3849             :   { 431,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #431 = FMUL_rnf64rr
    3850             :   { 432,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr },  // Inst #432 = FMULf16rr
    3851             :   { 433,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr },  // Inst #433 = FMULf16rr_ftz
    3852             :   { 434,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr },  // Inst #434 = FMULf16x2rr
    3853             :   { 435,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr },  // Inst #435 = FMULf16x2rr_ftz
    3854             :   { 436,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #436 = FMULf32ri
    3855             :   { 437,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #437 = FMULf32ri_ftz
    3856             :   { 438,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #438 = FMULf32rr
    3857             :   { 439,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #439 = FMULf32rr_ftz
    3858             :   { 440,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #440 = FMULf64ri
    3859             :   { 441,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #441 = FMULf64rr
    3860             :   { 442,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #442 = FNEGf32
    3861             :   { 443,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #443 = FNEGf32_ftz
    3862             :   { 444,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #444 = FNEGf64
    3863             :   { 445,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #445 = FSQRTf32
    3864             :   { 446,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #446 = FSQRTf32_ftz
    3865             :   { 447,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #447 = FSQRTf64
    3866             :   { 448,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr },  // Inst #448 = FSUB_rnf16rr
    3867             :   { 449,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr },  // Inst #449 = FSUB_rnf16rr_ftz
    3868             :   { 450,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr },  // Inst #450 = FSUB_rnf16x2rr
    3869             :   { 451,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr },  // Inst #451 = FSUB_rnf16x2rr_ftz
    3870             :   { 452,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #452 = FSUB_rnf32ri
    3871             :   { 453,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #453 = FSUB_rnf32ri_ftz
    3872             :   { 454,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #454 = FSUB_rnf32rr
    3873             :   { 455,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #455 = FSUB_rnf32rr_ftz
    3874             :   { 456,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #456 = FSUB_rnf64ri
    3875             :   { 457,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #457 = FSUB_rnf64rr
    3876             :   { 458,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr },  // Inst #458 = FSUBf16rr
    3877             :   { 459,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr },  // Inst #459 = FSUBf16rr_ftz
    3878             :   { 460,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr },  // Inst #460 = FSUBf16x2rr
    3879             :   { 461,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr },  // Inst #461 = FSUBf16x2rr_ftz
    3880             :   { 462,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #462 = FSUBf32ri
    3881             :   { 463,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #463 = FSUBf32ri_ftz
    3882             :   { 464,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #464 = FSUBf32rr
    3883             :   { 465,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #465 = FSUBf32rr_ftz
    3884             :   { 466,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #466 = FSUBf64ri
    3885             :   { 467,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #467 = FSUBf64rr
    3886             :   { 468,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #468 = FUNSHFLCLAMP
    3887             :   { 469,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #469 = FUNSHFRCLAMP
    3888             :   { 470,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #470 = GET_HI_INT64
    3889             :   { 471,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #471 = GET_LO_INT64
    3890             :   { 472,        1,      0,      0,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #472 = GOTO
    3891             :   { 473,        3,      2,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr },  // Inst #473 = I32toV2I16
    3892             :   { 474,        3,      2,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr },  // Inst #474 = I64toV2I32
    3893             :   { 475,        5,      4,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr },  // Inst #475 = I64toV4I16
    3894             :   { 476,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr },  // Inst #476 = IMOV16ri
    3895             :   { 477,        2,      1,      0,      0,      0, 0x10ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #477 = IMOV16rr
    3896             :   { 478,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr },  // Inst #478 = IMOV1ri
    3897             :   { 479,        2,      1,      0,      0,      0, 0x10ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #479 = IMOV1rr
    3898             :   { 480,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr },  // Inst #480 = IMOV32ri
    3899             :   { 481,        2,      1,      0,      0,      0, 0x10ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #481 = IMOV32rr
    3900             :   { 482,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #482 = IMOV64i
    3901             :   { 483,        2,      1,      0,      0,      0, 0x10ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #483 = IMOV64rr
    3902             :   { 484,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #484 = INEG16
    3903             :   { 485,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #485 = INEG32
    3904             :   { 486,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #486 = INEG64
    3905             :   { 487,        2,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #487 = INT_BARRIER
    3906             :   { 488,        0,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #488 = INT_BARRIER0
    3907             :   { 489,        2,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #489 = INT_BARRIER0_AND
    3908             :   { 490,        2,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #490 = INT_BARRIER0_OR
    3909             :   { 491,        2,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #491 = INT_BARRIER0_POPC
    3910             :   { 492,        1,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #492 = INT_BARRIERN
    3911             :   { 493,        1,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #493 = INT_BAR_SYNC
    3912             :   { 494,        0,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #494 = INT_MEMBAR_CTA
    3913             :   { 495,        0,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #495 = INT_MEMBAR_GL
    3914             :   { 496,        0,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #496 = INT_MEMBAR_SYS
    3915             :   { 497,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #497 = INT_NVVM_ADD_RM_D
    3916             :   { 498,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #498 = INT_NVVM_ADD_RM_F
    3917             :   { 499,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #499 = INT_NVVM_ADD_RM_FTZ_F
    3918             :   { 500,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #500 = INT_NVVM_ADD_RN_D
    3919             :   { 501,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #501 = INT_NVVM_ADD_RN_F
    3920             :   { 502,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #502 = INT_NVVM_ADD_RN_FTZ_F
    3921             :   { 503,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #503 = INT_NVVM_ADD_RP_D
    3922             :   { 504,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #504 = INT_NVVM_ADD_RP_F
    3923             :   { 505,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #505 = INT_NVVM_ADD_RP_FTZ_F
    3924             :   { 506,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #506 = INT_NVVM_ADD_RZ_D
    3925             :   { 507,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #507 = INT_NVVM_ADD_RZ_F
    3926             :   { 508,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #508 = INT_NVVM_ADD_RZ_FTZ_F
    3927             :   { 509,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #509 = INT_NVVM_BITCAST_D2LL
    3928             :   { 510,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #510 = INT_NVVM_BITCAST_F2I
    3929             :   { 511,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #511 = INT_NVVM_BITCAST_I2F
    3930             :   { 512,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #512 = INT_NVVM_BITCAST_LL2D
    3931             :   { 513,        1,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #513 = INT_NVVM_COMPILER_ERROR_32
    3932             :   { 514,        1,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr },  // Inst #514 = INT_NVVM_COMPILER_ERROR_64
    3933             :   { 515,        1,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #515 = INT_NVVM_COMPILER_WARN_32
    3934             :   { 516,        1,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr },  // Inst #516 = INT_NVVM_COMPILER_WARN_64
    3935             :   { 517,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #517 = INT_NVVM_COS_APPROX_F
    3936             :   { 518,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #518 = INT_NVVM_COS_APPROX_FTZ_F
    3937             :   { 519,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr },  // Inst #519 = INT_NVVM_D2I_HI
    3938             :   { 520,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr },  // Inst #520 = INT_NVVM_D2I_LO
    3939             :   { 521,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #521 = INT_NVVM_DIV_APPROX_F
    3940             :   { 522,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #522 = INT_NVVM_DIV_APPROX_FTZ_F
    3941             :   { 523,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #523 = INT_NVVM_DIV_RM_D
    3942             :   { 524,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #524 = INT_NVVM_DIV_RM_F
    3943             :   { 525,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #525 = INT_NVVM_DIV_RM_FTZ_F
    3944             :   { 526,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #526 = INT_NVVM_DIV_RN_D
    3945             :   { 527,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #527 = INT_NVVM_DIV_RN_F
    3946             :   { 528,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #528 = INT_NVVM_DIV_RN_FTZ_F
    3947             :   { 529,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #529 = INT_NVVM_DIV_RP_D
    3948             :   { 530,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #530 = INT_NVVM_DIV_RP_F
    3949             :   { 531,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #531 = INT_NVVM_DIV_RP_FTZ_F
    3950             :   { 532,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #532 = INT_NVVM_DIV_RZ_D
    3951             :   { 533,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #533 = INT_NVVM_DIV_RZ_F
    3952             :   { 534,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #534 = INT_NVVM_DIV_RZ_FTZ_F
    3953             :   { 535,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #535 = INT_NVVM_EX2_APPROX_D
    3954             :   { 536,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #536 = INT_NVVM_EX2_APPROX_F
    3955             :   { 537,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #537 = INT_NVVM_EX2_APPROX_FTZ_F
    3956             :   { 538,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #538 = INT_NVVM_FABS_D
    3957             :   { 539,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #539 = INT_NVVM_FABS_F
    3958             :   { 540,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #540 = INT_NVVM_FABS_FTZ_F
    3959             :   { 541,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #541 = INT_NVVM_FMAX_D
    3960             :   { 542,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #542 = INT_NVVM_FMAX_F
    3961             :   { 543,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #543 = INT_NVVM_FMAX_FTZ_F
    3962             :   { 544,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #544 = INT_NVVM_FMA_RM_D
    3963             :   { 545,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #545 = INT_NVVM_FMA_RM_F
    3964             :   { 546,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #546 = INT_NVVM_FMA_RM_FTZ_F
    3965             :   { 547,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #547 = INT_NVVM_FMA_RN_D
    3966             :   { 548,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #548 = INT_NVVM_FMA_RN_F
    3967             :   { 549,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #549 = INT_NVVM_FMA_RN_FTZ_F
    3968             :   { 550,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #550 = INT_NVVM_FMA_RP_D
    3969             :   { 551,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #551 = INT_NVVM_FMA_RP_F
    3970             :   { 552,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #552 = INT_NVVM_FMA_RP_FTZ_F
    3971             :   { 553,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #553 = INT_NVVM_FMA_RZ_D
    3972             :   { 554,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #554 = INT_NVVM_FMA_RZ_F
    3973             :   { 555,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #555 = INT_NVVM_FMA_RZ_FTZ_F
    3974             :   { 556,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #556 = INT_NVVM_FMIN_D
    3975             :   { 557,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #557 = INT_NVVM_FMIN_F
    3976             :   { 558,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #558 = INT_NVVM_FMIN_FTZ_F
    3977             :   { 559,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #559 = INT_NVVM_LG2_APPROX_D
    3978             :   { 560,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #560 = INT_NVVM_LG2_APPROX_F
    3979             :   { 561,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #561 = INT_NVVM_LG2_APPROX_FTZ_F
    3980             :   { 562,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr },  // Inst #562 = INT_NVVM_LOHI_I2D
    3981             :   { 563,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #563 = INT_NVVM_MUL24_I
    3982             :   { 564,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #564 = INT_NVVM_MUL24_UI
    3983             :   { 565,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #565 = INT_NVVM_MULHI_I
    3984             :   { 566,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #566 = INT_NVVM_MULHI_LL
    3985             :   { 567,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #567 = INT_NVVM_MULHI_UI
    3986             :   { 568,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #568 = INT_NVVM_MULHI_ULL
    3987             :   { 569,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #569 = INT_NVVM_MUL_RM_D
    3988             :   { 570,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #570 = INT_NVVM_MUL_RM_F
    3989             :   { 571,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #571 = INT_NVVM_MUL_RM_FTZ_F
    3990             :   { 572,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #572 = INT_NVVM_MUL_RN_D
    3991             :   { 573,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #573 = INT_NVVM_MUL_RN_F
    3992             :   { 574,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #574 = INT_NVVM_MUL_RN_FTZ_F
    3993             :   { 575,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #575 = INT_NVVM_MUL_RP_D
    3994             :   { 576,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #576 = INT_NVVM_MUL_RP_F
    3995             :   { 577,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #577 = INT_NVVM_MUL_RP_FTZ_F
    3996             :   { 578,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #578 = INT_NVVM_MUL_RZ_D
    3997             :   { 579,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #579 = INT_NVVM_MUL_RZ_F
    3998             :   { 580,        3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #580 = INT_NVVM_MUL_RZ_FTZ_F
    3999             :   { 581,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #581 = INT_NVVM_PRMT
    4000             :   { 582,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #582 = INT_NVVM_RCP_APPROX_FTZ_D
    4001             :   { 583,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #583 = INT_NVVM_RCP_RM_D
    4002             :   { 584,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #584 = INT_NVVM_RCP_RM_F
    4003             :   { 585,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #585 = INT_NVVM_RCP_RM_FTZ_F
    4004             :   { 586,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #586 = INT_NVVM_RCP_RN_D
    4005             :   { 587,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #587 = INT_NVVM_RCP_RN_F
    4006             :   { 588,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #588 = INT_NVVM_RCP_RN_FTZ_F
    4007             :   { 589,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #589 = INT_NVVM_RCP_RP_D
    4008             :   { 590,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #590 = INT_NVVM_RCP_RP_F
    4009             :   { 591,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #591 = INT_NVVM_RCP_RP_FTZ_F
    4010             :   { 592,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #592 = INT_NVVM_RCP_RZ_D
    4011             :   { 593,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #593 = INT_NVVM_RCP_RZ_F
    4012             :   { 594,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #594 = INT_NVVM_RCP_RZ_FTZ_F
    4013             :   { 595,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #595 = INT_NVVM_RSQRT_APPROX_D
    4014             :   { 596,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #596 = INT_NVVM_RSQRT_APPROX_F
    4015             :   { 597,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #597 = INT_NVVM_RSQRT_APPROX_FTZ_F
    4016             :   { 598,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #598 = INT_NVVM_SAD_I
    4017             :   { 599,        4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #599 = INT_NVVM_SAD_UI
    4018             :   { 600,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #600 = INT_NVVM_SIN_APPROX_F
    4019             :   { 601,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #601 = INT_NVVM_SIN_APPROX_FTZ_F
    4020             :   { 602,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #602 = INT_NVVM_SQRT_APPROX_F
    4021             :   { 603,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #603 = INT_NVVM_SQRT_APPROX_FTZ_F
    4022             :   { 604,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #604 = INT_NVVM_SQRT_RM_D
    4023             :   { 605,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #605 = INT_NVVM_SQRT_RM_F
    4024             :   { 606,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #606 = INT_NVVM_SQRT_RM_FTZ_F
    4025             :   { 607,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #607 = INT_NVVM_SQRT_RN_D
    4026             :   { 608,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #608 = INT_NVVM_SQRT_RN_F
    4027             :   { 609,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #609 = INT_NVVM_SQRT_RN_FTZ_F
    4028             :   { 610,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #610 = INT_NVVM_SQRT_RP_D
    4029             :   { 611,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #611 = INT_NVVM_SQRT_RP_F
    4030             :   { 612,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #612 = INT_NVVM_SQRT_RP_FTZ_F
    4031             :   { 613,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #613 = INT_NVVM_SQRT_RZ_D
    4032             :   { 614,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #614 = INT_NVVM_SQRT_RZ_F
    4033             :   { 615,        2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #615 = INT_NVVM_SQRT_RZ_FTZ_F
    4034             :   { 616,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #616 = INT_PTX_ATOM_ADD_GEN_32_USE_Gp32imm
    4035             :   { 617,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #617 = INT_PTX_ATOM_ADD_GEN_32_USE_Gp32reg
    4036             :   { 618,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #618 = INT_PTX_ATOM_ADD_GEN_32_USE_Gp64imm
    4037             :   { 619,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #619 = INT_PTX_ATOM_ADD_GEN_32_USE_Gp64reg
    4038             :   { 620,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #620 = INT_PTX_ATOM_ADD_GEN_32p32imm
    4039             :   { 621,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #621 = INT_PTX_ATOM_ADD_GEN_32p32reg
    4040             :   { 622,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #622 = INT_PTX_ATOM_ADD_GEN_32p64imm
    4041             :   { 623,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #623 = INT_PTX_ATOM_ADD_GEN_32p64reg
    4042             :   { 624,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #624 = INT_PTX_ATOM_ADD_GEN_64_USE_Gp32imm
    4043             :   { 625,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #625 = INT_PTX_ATOM_ADD_GEN_64_USE_Gp32reg
    4044             :   { 626,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #626 = INT_PTX_ATOM_ADD_GEN_64_USE_Gp64imm
    4045             :   { 627,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #627 = INT_PTX_ATOM_ADD_GEN_64_USE_Gp64reg
    4046             :   { 628,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #628 = INT_PTX_ATOM_ADD_GEN_64p32imm
    4047             :   { 629,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #629 = INT_PTX_ATOM_ADD_GEN_64p32reg
    4048             :   { 630,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #630 = INT_PTX_ATOM_ADD_GEN_64p64imm
    4049             :   { 631,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #631 = INT_PTX_ATOM_ADD_GEN_64p64reg
    4050             :   { 632,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr },  // Inst #632 = INT_PTX_ATOM_ADD_GEN_F32p32imm
    4051             :   { 633,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr },  // Inst #633 = INT_PTX_ATOM_ADD_GEN_F32p32reg
    4052             :   { 634,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #634 = INT_PTX_ATOM_ADD_GEN_F32p64imm
    4053             :   { 635,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr },  // Inst #635 = INT_PTX_ATOM_ADD_GEN_F32p64reg
    4054             :   { 636,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #636 = INT_PTX_ATOM_ADD_G_32p32imm
    4055             :   { 637,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #637 = INT_PTX_ATOM_ADD_G_32p32reg
    4056             :   { 638,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #638 = INT_PTX_ATOM_ADD_G_32p64imm
    4057             :   { 639,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #639 = INT_PTX_ATOM_ADD_G_32p64reg
    4058             :   { 640,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #640 = INT_PTX_ATOM_ADD_G_64p32imm
    4059             :   { 641,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #641 = INT_PTX_ATOM_ADD_G_64p32reg
    4060             :   { 642,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #642 = INT_PTX_ATOM_ADD_G_64p64imm
    4061             :   { 643,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #643 = INT_PTX_ATOM_ADD_G_64p64reg
    4062             :   { 644,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr },  // Inst #644 = INT_PTX_ATOM_ADD_G_F32p32imm
    4063             :   { 645,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr },  // Inst #645 = INT_PTX_ATOM_ADD_G_F32p32reg
    4064             :   { 646,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #646 = INT_PTX_ATOM_ADD_G_F32p64imm
    4065             :   { 647,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr },  // Inst #647 = INT_PTX_ATOM_ADD_G_F32p64reg
    4066             :   { 648,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #648 = INT_PTX_ATOM_ADD_S_32p32imm
    4067             :   { 649,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #649 = INT_PTX_ATOM_ADD_S_32p32reg
    4068             :   { 650,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #650 = INT_PTX_ATOM_ADD_S_32p64imm
    4069             :   { 651,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #651 = INT_PTX_ATOM_ADD_S_32p64reg
    4070             :   { 652,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #652 = INT_PTX_ATOM_ADD_S_64p32imm
    4071             :   { 653,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #653 = INT_PTX_ATOM_ADD_S_64p32reg
    4072             :   { 654,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #654 = INT_PTX_ATOM_ADD_S_64p64imm
    4073             :   { 655,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #655 = INT_PTX_ATOM_ADD_S_64p64reg
    4074             :   { 656,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr },  // Inst #656 = INT_PTX_ATOM_ADD_S_F32p32imm
    4075             :   { 657,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr },  // Inst #657 = INT_PTX_ATOM_ADD_S_F32p32reg
    4076             :   { 658,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #658 = INT_PTX_ATOM_ADD_S_F32p64imm
    4077             :   { 659,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr },  // Inst #659 = INT_PTX_ATOM_ADD_S_F32p64reg
    4078             :   { 660,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #660 = INT_PTX_ATOM_AND_GEN_32_USE_Gp32imm
    4079             :   { 661,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #661 = INT_PTX_ATOM_AND_GEN_32_USE_Gp32reg
    4080             :   { 662,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #662 = INT_PTX_ATOM_AND_GEN_32_USE_Gp64imm
    4081             :   { 663,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #663 = INT_PTX_ATOM_AND_GEN_32_USE_Gp64reg
    4082             :   { 664,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #664 = INT_PTX_ATOM_AND_GEN_32p32imm
    4083             :   { 665,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #665 = INT_PTX_ATOM_AND_GEN_32p32reg
    4084             :   { 666,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #666 = INT_PTX_ATOM_AND_GEN_32p64imm
    4085             :   { 667,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #667 = INT_PTX_ATOM_AND_GEN_32p64reg
    4086             :   { 668,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #668 = INT_PTX_ATOM_AND_GEN_64_USE_Gp32imm
    4087             :   { 669,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #669 = INT_PTX_ATOM_AND_GEN_64_USE_Gp32reg
    4088             :   { 670,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #670 = INT_PTX_ATOM_AND_GEN_64_USE_Gp64imm
    4089             :   { 671,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #671 = INT_PTX_ATOM_AND_GEN_64_USE_Gp64reg
    4090             :   { 672,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #672 = INT_PTX_ATOM_AND_GEN_64p32imm
    4091             :   { 673,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #673 = INT_PTX_ATOM_AND_GEN_64p32reg
    4092             :   { 674,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #674 = INT_PTX_ATOM_AND_GEN_64p64imm
    4093             :   { 675,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #675 = INT_PTX_ATOM_AND_GEN_64p64reg
    4094             :   { 676,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #676 = INT_PTX_ATOM_AND_G_32p32imm
    4095             :   { 677,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #677 = INT_PTX_ATOM_AND_G_32p32reg
    4096             :   { 678,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #678 = INT_PTX_ATOM_AND_G_32p64imm
    4097             :   { 679,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #679 = INT_PTX_ATOM_AND_G_32p64reg
    4098             :   { 680,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #680 = INT_PTX_ATOM_AND_G_64p32imm
    4099             :   { 681,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #681 = INT_PTX_ATOM_AND_G_64p32reg
    4100             :   { 682,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #682 = INT_PTX_ATOM_AND_G_64p64imm
    4101             :   { 683,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #683 = INT_PTX_ATOM_AND_G_64p64reg
    4102             :   { 684,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #684 = INT_PTX_ATOM_AND_S_32p32imm
    4103             :   { 685,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #685 = INT_PTX_ATOM_AND_S_32p32reg
    4104             :   { 686,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #686 = INT_PTX_ATOM_AND_S_32p64imm
    4105             :   { 687,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #687 = INT_PTX_ATOM_AND_S_32p64reg
    4106             :   { 688,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #688 = INT_PTX_ATOM_AND_S_64p32imm
    4107             :   { 689,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #689 = INT_PTX_ATOM_AND_S_64p32reg
    4108             :   { 690,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #690 = INT_PTX_ATOM_AND_S_64p64imm
    4109             :   { 691,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #691 = INT_PTX_ATOM_AND_S_64p64reg
    4110             :   { 692,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr },  // Inst #692 = INT_PTX_ATOM_CAS_GEN_32_USE_Gp32imm1
    4111             :   { 693,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #693 = INT_PTX_ATOM_CAS_GEN_32_USE_Gp32imm2
    4112             :   { 694,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #694 = INT_PTX_ATOM_CAS_GEN_32_USE_Gp32imm3
    4113             :   { 695,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #695 = INT_PTX_ATOM_CAS_GEN_32_USE_Gp32reg
    4114             :   { 696,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #696 = INT_PTX_ATOM_CAS_GEN_32_USE_Gp64imm1
    4115             :   { 697,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #697 = INT_PTX_ATOM_CAS_GEN_32_USE_Gp64imm2
    4116             :   { 698,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #698 = INT_PTX_ATOM_CAS_GEN_32_USE_Gp64imm3
    4117             :   { 699,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #699 = INT_PTX_ATOM_CAS_GEN_32_USE_Gp64reg
    4118             :   { 700,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr },  // Inst #700 = INT_PTX_ATOM_CAS_GEN_32p32imm1
    4119             :   { 701,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #701 = INT_PTX_ATOM_CAS_GEN_32p32imm2
    4120             :   { 702,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #702 = INT_PTX_ATOM_CAS_GEN_32p32imm3
    4121             :   { 703,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #703 = INT_PTX_ATOM_CAS_GEN_32p32reg
    4122             :   { 704,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #704 = INT_PTX_ATOM_CAS_GEN_32p64imm1
    4123             :   { 705,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #705 = INT_PTX_ATOM_CAS_GEN_32p64imm2
    4124             :   { 706,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #706 = INT_PTX_ATOM_CAS_GEN_32p64imm3
    4125             :   { 707,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #707 = INT_PTX_ATOM_CAS_GEN_32p64reg
    4126             :   { 708,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #708 = INT_PTX_ATOM_CAS_GEN_64_USE_Gp32imm1
    4127             :   { 709,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #709 = INT_PTX_ATOM_CAS_GEN_64_USE_Gp32imm2
    4128             :   { 710,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #710 = INT_PTX_ATOM_CAS_GEN_64_USE_Gp32imm3
    4129             :   { 711,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #711 = INT_PTX_ATOM_CAS_GEN_64_USE_Gp32reg
    4130             :   { 712,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #712 = INT_PTX_ATOM_CAS_GEN_64_USE_Gp64imm1
    4131             :   { 713,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #713 = INT_PTX_ATOM_CAS_GEN_64_USE_Gp64imm2
    4132             :   { 714,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #714 = INT_PTX_ATOM_CAS_GEN_64_USE_Gp64imm3
    4133             :   { 715,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #715 = INT_PTX_ATOM_CAS_GEN_64_USE_Gp64reg
    4134             :   { 716,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #716 = INT_PTX_ATOM_CAS_GEN_64p32imm1
    4135             :   { 717,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #717 = INT_PTX_ATOM_CAS_GEN_64p32imm2
    4136             :   { 718,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #718 = INT_PTX_ATOM_CAS_GEN_64p32imm3
    4137             :   { 719,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #719 = INT_PTX_ATOM_CAS_GEN_64p32reg
    4138             :   { 720,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #720 = INT_PTX_ATOM_CAS_GEN_64p64imm1
    4139             :   { 721,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #721 = INT_PTX_ATOM_CAS_GEN_64p64imm2
    4140             :   { 722,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #722 = INT_PTX_ATOM_CAS_GEN_64p64imm3
    4141             :   { 723,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #723 = INT_PTX_ATOM_CAS_GEN_64p64reg
    4142             :   { 724,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr },  // Inst #724 = INT_PTX_ATOM_CAS_G_32p32imm1
    4143             :   { 725,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #725 = INT_PTX_ATOM_CAS_G_32p32imm2
    4144             :   { 726,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #726 = INT_PTX_ATOM_CAS_G_32p32imm3
    4145             :   { 727,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #727 = INT_PTX_ATOM_CAS_G_32p32reg
    4146             :   { 728,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #728 = INT_PTX_ATOM_CAS_G_32p64imm1
    4147             :   { 729,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #729 = INT_PTX_ATOM_CAS_G_32p64imm2
    4148             :   { 730,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #730 = INT_PTX_ATOM_CAS_G_32p64imm3
    4149             :   { 731,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #731 = INT_PTX_ATOM_CAS_G_32p64reg
    4150             :   { 732,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #732 = INT_PTX_ATOM_CAS_G_64p32imm1
    4151             :   { 733,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #733 = INT_PTX_ATOM_CAS_G_64p32imm2
    4152             :   { 734,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #734 = INT_PTX_ATOM_CAS_G_64p32imm3
    4153             :   { 735,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #735 = INT_PTX_ATOM_CAS_G_64p32reg
    4154             :   { 736,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #736 = INT_PTX_ATOM_CAS_G_64p64imm1
    4155             :   { 737,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #737 = INT_PTX_ATOM_CAS_G_64p64imm2
    4156             :   { 738,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #738 = INT_PTX_ATOM_CAS_G_64p64imm3
    4157             :   { 739,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #739 = INT_PTX_ATOM_CAS_G_64p64reg
    4158             :   { 740,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr },  // Inst #740 = INT_PTX_ATOM_CAS_S_32p32imm1
    4159             :   { 741,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #741 = INT_PTX_ATOM_CAS_S_32p32imm2
    4160             :   { 742,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #742 = INT_PTX_ATOM_CAS_S_32p32imm3
    4161             :   { 743,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #743 = INT_PTX_ATOM_CAS_S_32p32reg
    4162             :   { 744,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #744 = INT_PTX_ATOM_CAS_S_32p64imm1
    4163             :   { 745,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #745 = INT_PTX_ATOM_CAS_S_32p64imm2
    4164             :   { 746,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #746 = INT_PTX_ATOM_CAS_S_32p64imm3
    4165             :   { 747,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #747 = INT_PTX_ATOM_CAS_S_32p64reg
    4166             :   { 748,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #748 = INT_PTX_ATOM_CAS_S_64p32imm1
    4167             :   { 749,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #749 = INT_PTX_ATOM_CAS_S_64p32imm2
    4168             :   { 750,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #750 = INT_PTX_ATOM_CAS_S_64p32imm3
    4169             :   { 751,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #751 = INT_PTX_ATOM_CAS_S_64p32reg
    4170             :   { 752,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #752 = INT_PTX_ATOM_CAS_S_64p64imm1
    4171             :   { 753,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #753 = INT_PTX_ATOM_CAS_S_64p64imm2
    4172             :   { 754,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #754 = INT_PTX_ATOM_CAS_S_64p64imm3
    4173             :   { 755,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #755 = INT_PTX_ATOM_CAS_S_64p64reg
    4174             :   { 756,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #756 = INT_PTX_ATOM_DEC_GEN_32_USE_Gp32imm
    4175             :   { 757,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #757 = INT_PTX_ATOM_DEC_GEN_32_USE_Gp32reg
    4176             :   { 758,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #758 = INT_PTX_ATOM_DEC_GEN_32_USE_Gp64imm
    4177             :   { 759,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #759 = INT_PTX_ATOM_DEC_GEN_32_USE_Gp64reg
    4178             :   { 760,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #760 = INT_PTX_ATOM_DEC_GEN_32p32imm
    4179             :   { 761,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #761 = INT_PTX_ATOM_DEC_GEN_32p32reg
    4180             :   { 762,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #762 = INT_PTX_ATOM_DEC_GEN_32p64imm
    4181             :   { 763,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #763 = INT_PTX_ATOM_DEC_GEN_32p64reg
    4182             :   { 764,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #764 = INT_PTX_ATOM_DEC_G_32p32imm
    4183             :   { 765,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #765 = INT_PTX_ATOM_DEC_G_32p32reg
    4184             :   { 766,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #766 = INT_PTX_ATOM_DEC_G_32p64imm
    4185             :   { 767,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #767 = INT_PTX_ATOM_DEC_G_32p64reg
    4186             :   { 768,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #768 = INT_PTX_ATOM_DEC_S_32p32imm
    4187             :   { 769,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #769 = INT_PTX_ATOM_DEC_S_32p32reg
    4188             :   { 770,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #770 = INT_PTX_ATOM_DEC_S_32p64imm
    4189             :   { 771,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #771 = INT_PTX_ATOM_DEC_S_32p64reg
    4190             :   { 772,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #772 = INT_PTX_ATOM_INC_GEN_32_USE_Gp32imm
    4191             :   { 773,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #773 = INT_PTX_ATOM_INC_GEN_32_USE_Gp32reg
    4192             :   { 774,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #774 = INT_PTX_ATOM_INC_GEN_32_USE_Gp64imm
    4193             :   { 775,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #775 = INT_PTX_ATOM_INC_GEN_32_USE_Gp64reg
    4194             :   { 776,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #776 = INT_PTX_ATOM_INC_GEN_32p32imm
    4195             :   { 777,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #777 = INT_PTX_ATOM_INC_GEN_32p32reg
    4196             :   { 778,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #778 = INT_PTX_ATOM_INC_GEN_32p64imm
    4197             :   { 779,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #779 = INT_PTX_ATOM_INC_GEN_32p64reg
    4198             :   { 780,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #780 = INT_PTX_ATOM_INC_G_32p32imm
    4199             :   { 781,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #781 = INT_PTX_ATOM_INC_G_32p32reg
    4200             :   { 782,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #782 = INT_PTX_ATOM_INC_G_32p64imm
    4201             :   { 783,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #783 = INT_PTX_ATOM_INC_G_32p64reg
    4202             :   { 784,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #784 = INT_PTX_ATOM_INC_S_32p32imm
    4203             :   { 785,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #785 = INT_PTX_ATOM_INC_S_32p32reg
    4204             :   { 786,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #786 = INT_PTX_ATOM_INC_S_32p64imm
    4205             :   { 787,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #787 = INT_PTX_ATOM_INC_S_32p64reg
    4206             :   { 788,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #788 = INT_PTX_ATOM_LOAD_MAX_GEN_32_USE_Gp32imm
    4207             :   { 789,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #789 = INT_PTX_ATOM_LOAD_MAX_GEN_32_USE_Gp32reg
    4208             :   { 790,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #790 = INT_PTX_ATOM_LOAD_MAX_GEN_32_USE_Gp64imm
    4209             :   { 791,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #791 = INT_PTX_ATOM_LOAD_MAX_GEN_32_USE_Gp64reg
    4210             :   { 792,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #792 = INT_PTX_ATOM_LOAD_MAX_GEN_32p32imm
    4211             :   { 793,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #793 = INT_PTX_ATOM_LOAD_MAX_GEN_32p32reg
    4212             :   { 794,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #794 = INT_PTX_ATOM_LOAD_MAX_GEN_32p64imm
    4213             :   { 795,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #795 = INT_PTX_ATOM_LOAD_MAX_GEN_32p64reg
    4214             :   { 796,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #796 = INT_PTX_ATOM_LOAD_MAX_GEN_64_USE_Gp32imm
    4215             :   { 797,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #797 = INT_PTX_ATOM_LOAD_MAX_GEN_64_USE_Gp32reg
    4216             :   { 798,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #798 = INT_PTX_ATOM_LOAD_MAX_GEN_64_USE_Gp64imm
    4217             :   { 799,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #799 = INT_PTX_ATOM_LOAD_MAX_GEN_64_USE_Gp64reg
    4218             :   { 800,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #800 = INT_PTX_ATOM_LOAD_MAX_GEN_64p32imm
    4219             :   { 801,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #801 = INT_PTX_ATOM_LOAD_MAX_GEN_64p32reg
    4220             :   { 802,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #802 = INT_PTX_ATOM_LOAD_MAX_GEN_64p64imm
    4221             :   { 803,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #803 = INT_PTX_ATOM_LOAD_MAX_GEN_64p64reg
    4222             :   { 804,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #804 = INT_PTX_ATOM_LOAD_MAX_G_32p32imm
    4223             :   { 805,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #805 = INT_PTX_ATOM_LOAD_MAX_G_32p32reg
    4224             :   { 806,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #806 = INT_PTX_ATOM_LOAD_MAX_G_32p64imm
    4225             :   { 807,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #807 = INT_PTX_ATOM_LOAD_MAX_G_32p64reg
    4226             :   { 808,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #808 = INT_PTX_ATOM_LOAD_MAX_G_64p32imm
    4227             :   { 809,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #809 = INT_PTX_ATOM_LOAD_MAX_G_64p32reg
    4228             :   { 810,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #810 = INT_PTX_ATOM_LOAD_MAX_G_64p64imm
    4229             :   { 811,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #811 = INT_PTX_ATOM_LOAD_MAX_G_64p64reg
    4230             :   { 812,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #812 = INT_PTX_ATOM_LOAD_MAX_S_32p32imm
    4231             :   { 813,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #813 = INT_PTX_ATOM_LOAD_MAX_S_32p32reg
    4232             :   { 814,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #814 = INT_PTX_ATOM_LOAD_MAX_S_32p64imm
    4233             :   { 815,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #815 = INT_PTX_ATOM_LOAD_MAX_S_32p64reg
    4234             :   { 816,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #816 = INT_PTX_ATOM_LOAD_MAX_S_64p32imm
    4235             :   { 817,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #817 = INT_PTX_ATOM_LOAD_MAX_S_64p32reg
    4236             :   { 818,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #818 = INT_PTX_ATOM_LOAD_MAX_S_64p64imm
    4237             :   { 819,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #819 = INT_PTX_ATOM_LOAD_MAX_S_64p64reg
    4238             :   { 820,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #820 = INT_PTX_ATOM_LOAD_MIN_GEN_32_USE_Gp32imm
    4239             :   { 821,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #821 = INT_PTX_ATOM_LOAD_MIN_GEN_32_USE_Gp32reg
    4240             :   { 822,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #822 = INT_PTX_ATOM_LOAD_MIN_GEN_32_USE_Gp64imm
    4241             :   { 823,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #823 = INT_PTX_ATOM_LOAD_MIN_GEN_32_USE_Gp64reg
    4242             :   { 824,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #824 = INT_PTX_ATOM_LOAD_MIN_GEN_32p32imm
    4243             :   { 825,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #825 = INT_PTX_ATOM_LOAD_MIN_GEN_32p32reg
    4244             :   { 826,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #826 = INT_PTX_ATOM_LOAD_MIN_GEN_32p64imm
    4245             :   { 827,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #827 = INT_PTX_ATOM_LOAD_MIN_GEN_32p64reg
    4246             :   { 828,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #828 = INT_PTX_ATOM_LOAD_MIN_GEN_64_USE_Gp32imm
    4247             :   { 829,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #829 = INT_PTX_ATOM_LOAD_MIN_GEN_64_USE_Gp32reg
    4248             :   { 830,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #830 = INT_PTX_ATOM_LOAD_MIN_GEN_64_USE_Gp64imm
    4249             :   { 831,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #831 = INT_PTX_ATOM_LOAD_MIN_GEN_64_USE_Gp64reg
    4250             :   { 832,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #832 = INT_PTX_ATOM_LOAD_MIN_GEN_64p32imm
    4251             :   { 833,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #833 = INT_PTX_ATOM_LOAD_MIN_GEN_64p32reg
    4252             :   { 834,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #834 = INT_PTX_ATOM_LOAD_MIN_GEN_64p64imm
    4253             :   { 835,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #835 = INT_PTX_ATOM_LOAD_MIN_GEN_64p64reg
    4254             :   { 836,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #836 = INT_PTX_ATOM_LOAD_MIN_G_32p32imm
    4255             :   { 837,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #837 = INT_PTX_ATOM_LOAD_MIN_G_32p32reg
    4256             :   { 838,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #838 = INT_PTX_ATOM_LOAD_MIN_G_32p64imm
    4257             :   { 839,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #839 = INT_PTX_ATOM_LOAD_MIN_G_32p64reg
    4258             :   { 840,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #840 = INT_PTX_ATOM_LOAD_MIN_G_64p32imm
    4259             :   { 841,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #841 = INT_PTX_ATOM_LOAD_MIN_G_64p32reg
    4260             :   { 842,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #842 = INT_PTX_ATOM_LOAD_MIN_G_64p64imm
    4261             :   { 843,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #843 = INT_PTX_ATOM_LOAD_MIN_G_64p64reg
    4262             :   { 844,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #844 = INT_PTX_ATOM_LOAD_MIN_S_32p32imm
    4263             :   { 845,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #845 = INT_PTX_ATOM_LOAD_MIN_S_32p32reg
    4264             :   { 846,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #846 = INT_PTX_ATOM_LOAD_MIN_S_32p64imm
    4265             :   { 847,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #847 = INT_PTX_ATOM_LOAD_MIN_S_32p64reg
    4266             :   { 848,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #848 = INT_PTX_ATOM_LOAD_MIN_S_64p32imm
    4267             :   { 849,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #849 = INT_PTX_ATOM_LOAD_MIN_S_64p32reg
    4268             :   { 850,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #850 = INT_PTX_ATOM_LOAD_MIN_S_64p64imm
    4269             :   { 851,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #851 = INT_PTX_ATOM_LOAD_MIN_S_64p64reg
    4270             :   { 852,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #852 = INT_PTX_ATOM_LOAD_UMAX_GEN_32_USE_Gp32imm
    4271             :   { 853,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #853 = INT_PTX_ATOM_LOAD_UMAX_GEN_32_USE_Gp32reg
    4272             :   { 854,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #854 = INT_PTX_ATOM_LOAD_UMAX_GEN_32_USE_Gp64imm
    4273             :   { 855,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #855 = INT_PTX_ATOM_LOAD_UMAX_GEN_32_USE_Gp64reg
    4274             :   { 856,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #856 = INT_PTX_ATOM_LOAD_UMAX_GEN_32p32imm
    4275             :   { 857,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #857 = INT_PTX_ATOM_LOAD_UMAX_GEN_32p32reg
    4276             :   { 858,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #858 = INT_PTX_ATOM_LOAD_UMAX_GEN_32p64imm
    4277             :   { 859,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #859 = INT_PTX_ATOM_LOAD_UMAX_GEN_32p64reg
    4278             :   { 860,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #860 = INT_PTX_ATOM_LOAD_UMAX_GEN_64_USE_Gp32imm
    4279             :   { 861,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #861 = INT_PTX_ATOM_LOAD_UMAX_GEN_64_USE_Gp32reg
    4280             :   { 862,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #862 = INT_PTX_ATOM_LOAD_UMAX_GEN_64_USE_Gp64imm
    4281             :   { 863,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #863 = INT_PTX_ATOM_LOAD_UMAX_GEN_64_USE_Gp64reg
    4282             :   { 864,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #864 = INT_PTX_ATOM_LOAD_UMAX_GEN_64p32imm
    4283             :   { 865,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #865 = INT_PTX_ATOM_LOAD_UMAX_GEN_64p32reg
    4284             :   { 866,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #866 = INT_PTX_ATOM_LOAD_UMAX_GEN_64p64imm
    4285             :   { 867,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #867 = INT_PTX_ATOM_LOAD_UMAX_GEN_64p64reg
    4286             :   { 868,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #868 = INT_PTX_ATOM_LOAD_UMAX_G_32p32imm
    4287             :   { 869,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #869 = INT_PTX_ATOM_LOAD_UMAX_G_32p32reg
    4288             :   { 870,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #870 = INT_PTX_ATOM_LOAD_UMAX_G_32p64imm
    4289             :   { 871,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #871 = INT_PTX_ATOM_LOAD_UMAX_G_32p64reg
    4290             :   { 872,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #872 = INT_PTX_ATOM_LOAD_UMAX_G_64p32imm
    4291             :   { 873,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #873 = INT_PTX_ATOM_LOAD_UMAX_G_64p32reg
    4292             :   { 874,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #874 = INT_PTX_ATOM_LOAD_UMAX_G_64p64imm
    4293             :   { 875,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #875 = INT_PTX_ATOM_LOAD_UMAX_G_64p64reg
    4294             :   { 876,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #876 = INT_PTX_ATOM_LOAD_UMAX_S_32p32imm
    4295             :   { 877,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #877 = INT_PTX_ATOM_LOAD_UMAX_S_32p32reg
    4296             :   { 878,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #878 = INT_PTX_ATOM_LOAD_UMAX_S_32p64imm
    4297             :   { 879,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #879 = INT_PTX_ATOM_LOAD_UMAX_S_32p64reg
    4298             :   { 880,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #880 = INT_PTX_ATOM_LOAD_UMAX_S_64p32imm
    4299             :   { 881,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #881 = INT_PTX_ATOM_LOAD_UMAX_S_64p32reg
    4300             :   { 882,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #882 = INT_PTX_ATOM_LOAD_UMAX_S_64p64imm
    4301             :   { 883,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #883 = INT_PTX_ATOM_LOAD_UMAX_S_64p64reg
    4302             :   { 884,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #884 = INT_PTX_ATOM_LOAD_UMIN_GEN_32_USE_Gp32imm
    4303             :   { 885,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #885 = INT_PTX_ATOM_LOAD_UMIN_GEN_32_USE_Gp32reg
    4304             :   { 886,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #886 = INT_PTX_ATOM_LOAD_UMIN_GEN_32_USE_Gp64imm
    4305             :   { 887,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #887 = INT_PTX_ATOM_LOAD_UMIN_GEN_32_USE_Gp64reg
    4306             :   { 888,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #888 = INT_PTX_ATOM_LOAD_UMIN_GEN_32p32imm
    4307             :   { 889,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #889 = INT_PTX_ATOM_LOAD_UMIN_GEN_32p32reg
    4308             :   { 890,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #890 = INT_PTX_ATOM_LOAD_UMIN_GEN_32p64imm
    4309             :   { 891,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #891 = INT_PTX_ATOM_LOAD_UMIN_GEN_32p64reg
    4310             :   { 892,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #892 = INT_PTX_ATOM_LOAD_UMIN_GEN_64_USE_Gp32imm
    4311             :   { 893,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #893 = INT_PTX_ATOM_LOAD_UMIN_GEN_64_USE_Gp32reg
    4312             :   { 894,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #894 = INT_PTX_ATOM_LOAD_UMIN_GEN_64_USE_Gp64imm
    4313             :   { 895,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #895 = INT_PTX_ATOM_LOAD_UMIN_GEN_64_USE_Gp64reg
    4314             :   { 896,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #896 = INT_PTX_ATOM_LOAD_UMIN_GEN_64p32imm
    4315             :   { 897,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #897 = INT_PTX_ATOM_LOAD_UMIN_GEN_64p32reg
    4316             :   { 898,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #898 = INT_PTX_ATOM_LOAD_UMIN_GEN_64p64imm
    4317             :   { 899,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #899 = INT_PTX_ATOM_LOAD_UMIN_GEN_64p64reg
    4318             :   { 900,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #900 = INT_PTX_ATOM_LOAD_UMIN_G_32p32imm
    4319             :   { 901,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #901 = INT_PTX_ATOM_LOAD_UMIN_G_32p32reg
    4320             :   { 902,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #902 = INT_PTX_ATOM_LOAD_UMIN_G_32p64imm
    4321             :   { 903,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #903 = INT_PTX_ATOM_LOAD_UMIN_G_32p64reg
    4322             :   { 904,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #904 = INT_PTX_ATOM_LOAD_UMIN_G_64p32imm
    4323             :   { 905,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #905 = INT_PTX_ATOM_LOAD_UMIN_G_64p32reg
    4324             :   { 906,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #906 = INT_PTX_ATOM_LOAD_UMIN_G_64p64imm
    4325             :   { 907,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #907 = INT_PTX_ATOM_LOAD_UMIN_G_64p64reg
    4326             :   { 908,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #908 = INT_PTX_ATOM_LOAD_UMIN_S_32p32imm
    4327             :   { 909,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #909 = INT_PTX_ATOM_LOAD_UMIN_S_32p32reg
    4328             :   { 910,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #910 = INT_PTX_ATOM_LOAD_UMIN_S_32p64imm
    4329             :   { 911,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #911 = INT_PTX_ATOM_LOAD_UMIN_S_32p64reg
    4330             :   { 912,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #912 = INT_PTX_ATOM_LOAD_UMIN_S_64p32imm
    4331             :   { 913,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #913 = INT_PTX_ATOM_LOAD_UMIN_S_64p32reg
    4332             :   { 914,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #914 = INT_PTX_ATOM_LOAD_UMIN_S_64p64imm
    4333             :   { 915,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #915 = INT_PTX_ATOM_LOAD_UMIN_S_64p64reg
    4334             :   { 916,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #916 = INT_PTX_ATOM_OR_GEN_32_USE_Gp32imm
    4335             :   { 917,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #917 = INT_PTX_ATOM_OR_GEN_32_USE_Gp32reg
    4336             :   { 918,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #918 = INT_PTX_ATOM_OR_GEN_32_USE_Gp64imm
    4337             :   { 919,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #919 = INT_PTX_ATOM_OR_GEN_32_USE_Gp64reg
    4338             :   { 920,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #920 = INT_PTX_ATOM_OR_GEN_32p32imm
    4339             :   { 921,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #921 = INT_PTX_ATOM_OR_GEN_32p32reg
    4340             :   { 922,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #922 = INT_PTX_ATOM_OR_GEN_32p64imm
    4341             :   { 923,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #923 = INT_PTX_ATOM_OR_GEN_32p64reg
    4342             :   { 924,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #924 = INT_PTX_ATOM_OR_GEN_64_USE_Gp32imm
    4343             :   { 925,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #925 = INT_PTX_ATOM_OR_GEN_64_USE_Gp32reg
    4344             :   { 926,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #926 = INT_PTX_ATOM_OR_GEN_64_USE_Gp64imm
    4345             :   { 927,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #927 = INT_PTX_ATOM_OR_GEN_64_USE_Gp64reg
    4346             :   { 928,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #928 = INT_PTX_ATOM_OR_GEN_64p32imm
    4347             :   { 929,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #929 = INT_PTX_ATOM_OR_GEN_64p32reg
    4348             :   { 930,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #930 = INT_PTX_ATOM_OR_GEN_64p64imm
    4349             :   { 931,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #931 = INT_PTX_ATOM_OR_GEN_64p64reg
    4350             :   { 932,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #932 = INT_PTX_ATOM_OR_G_32p32imm
    4351             :   { 933,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #933 = INT_PTX_ATOM_OR_G_32p32reg
    4352             :   { 934,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #934 = INT_PTX_ATOM_OR_G_32p64imm
    4353             :   { 935,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #935 = INT_PTX_ATOM_OR_G_32p64reg
    4354             :   { 936,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #936 = INT_PTX_ATOM_OR_G_64p32imm
    4355             :   { 937,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #937 = INT_PTX_ATOM_OR_G_64p32reg
    4356             :   { 938,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #938 = INT_PTX_ATOM_OR_G_64p64imm
    4357             :   { 939,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #939 = INT_PTX_ATOM_OR_G_64p64reg
    4358             :   { 940,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #940 = INT_PTX_ATOM_OR_S_32p32imm
    4359             :   { 941,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #941 = INT_PTX_ATOM_OR_S_32p32reg
    4360             :   { 942,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #942 = INT_PTX_ATOM_OR_S_32p64imm
    4361             :   { 943,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #943 = INT_PTX_ATOM_OR_S_32p64reg
    4362             :   { 944,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #944 = INT_PTX_ATOM_OR_S_64p32imm
    4363             :   { 945,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #945 = INT_PTX_ATOM_OR_S_64p32reg
    4364             :   { 946,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #946 = INT_PTX_ATOM_OR_S_64p64imm
    4365             :   { 947,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #947 = INT_PTX_ATOM_OR_S_64p64reg
    4366             :   { 948,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #948 = INT_PTX_ATOM_SUB_GEN_32_USE_Gp32reg
    4367             :   { 949,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #949 = INT_PTX_ATOM_SUB_GEN_32_USE_Gp64reg
    4368             :   { 950,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #950 = INT_PTX_ATOM_SUB_GEN_32p32reg
    4369             :   { 951,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #951 = INT_PTX_ATOM_SUB_GEN_32p64reg
    4370             :   { 952,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #952 = INT_PTX_ATOM_SUB_GEN_64_USE_Gp32reg
    4371             :   { 953,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #953 = INT_PTX_ATOM_SUB_GEN_64_USE_Gp64reg
    4372             :   { 954,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #954 = INT_PTX_ATOM_SUB_GEN_64p32reg
    4373             :   { 955,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #955 = INT_PTX_ATOM_SUB_GEN_64p64reg
    4374             :   { 956,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #956 = INT_PTX_ATOM_SUB_G_32p32reg
    4375             :   { 957,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #957 = INT_PTX_ATOM_SUB_G_32p64reg
    4376             :   { 958,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #958 = INT_PTX_ATOM_SUB_G_64p32reg
    4377             :   { 959,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #959 = INT_PTX_ATOM_SUB_G_64p64reg
    4378             :   { 960,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #960 = INT_PTX_ATOM_SUB_S_32p32reg
    4379             :   { 961,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #961 = INT_PTX_ATOM_SUB_S_32p64reg
    4380             :   { 962,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #962 = INT_PTX_ATOM_SUB_S_64p32reg
    4381             :   { 963,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #963 = INT_PTX_ATOM_SUB_S_64p64reg
    4382             :   { 964,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #964 = INT_PTX_ATOM_SWAP_GEN_32_USE_Gp32imm
    4383             :   { 965,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #965 = INT_PTX_ATOM_SWAP_GEN_32_USE_Gp32reg
    4384             :   { 966,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #966 = INT_PTX_ATOM_SWAP_GEN_32_USE_Gp64imm
    4385             :   { 967,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #967 = INT_PTX_ATOM_SWAP_GEN_32_USE_Gp64reg
    4386             :   { 968,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #968 = INT_PTX_ATOM_SWAP_GEN_32p32imm
    4387             :   { 969,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #969 = INT_PTX_ATOM_SWAP_GEN_32p32reg
    4388             :   { 970,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #970 = INT_PTX_ATOM_SWAP_GEN_32p64imm
    4389             :   { 971,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #971 = INT_PTX_ATOM_SWAP_GEN_32p64reg
    4390             :   { 972,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #972 = INT_PTX_ATOM_SWAP_GEN_64_USE_Gp32imm
    4391             :   { 973,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #973 = INT_PTX_ATOM_SWAP_GEN_64_USE_Gp32reg
    4392             :   { 974,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #974 = INT_PTX_ATOM_SWAP_GEN_64_USE_Gp64imm
    4393             :   { 975,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #975 = INT_PTX_ATOM_SWAP_GEN_64_USE_Gp64reg
    4394             :   { 976,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #976 = INT_PTX_ATOM_SWAP_GEN_64p32imm
    4395             :   { 977,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #977 = INT_PTX_ATOM_SWAP_GEN_64p32reg
    4396             :   { 978,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #978 = INT_PTX_ATOM_SWAP_GEN_64p64imm
    4397             :   { 979,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #979 = INT_PTX_ATOM_SWAP_GEN_64p64reg
    4398             :   { 980,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #980 = INT_PTX_ATOM_SWAP_G_32p32imm
    4399             :   { 981,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #981 = INT_PTX_ATOM_SWAP_G_32p32reg
    4400             :   { 982,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #982 = INT_PTX_ATOM_SWAP_G_32p64imm
    4401             :   { 983,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #983 = INT_PTX_ATOM_SWAP_G_32p64reg
    4402             :   { 984,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #984 = INT_PTX_ATOM_SWAP_G_64p32imm
    4403             :   { 985,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #985 = INT_PTX_ATOM_SWAP_G_64p32reg
    4404             :   { 986,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #986 = INT_PTX_ATOM_SWAP_G_64p64imm
    4405             :   { 987,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #987 = INT_PTX_ATOM_SWAP_G_64p64reg
    4406             :   { 988,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #988 = INT_PTX_ATOM_SWAP_S_32p32imm
    4407             :   { 989,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #989 = INT_PTX_ATOM_SWAP_S_32p32reg
    4408             :   { 990,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #990 = INT_PTX_ATOM_SWAP_S_32p64imm
    4409             :   { 991,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #991 = INT_PTX_ATOM_SWAP_S_32p64reg
    4410             :   { 992,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #992 = INT_PTX_ATOM_SWAP_S_64p32imm
    4411             :   { 993,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #993 = INT_PTX_ATOM_SWAP_S_64p32reg
    4412             :   { 994,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #994 = INT_PTX_ATOM_SWAP_S_64p64imm
    4413             :   { 995,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #995 = INT_PTX_ATOM_SWAP_S_64p64reg
    4414             :   { 996,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #996 = INT_PTX_ATOM_XOR_GEN_32_USE_Gp32imm
    4415             :   { 997,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #997 = INT_PTX_ATOM_XOR_GEN_32_USE_Gp32reg
    4416             :   { 998,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #998 = INT_PTX_ATOM_XOR_GEN_32_USE_Gp64imm
    4417             :   { 999,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #999 = INT_PTX_ATOM_XOR_GEN_32_USE_Gp64reg
    4418             :   { 1000,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1000 = INT_PTX_ATOM_XOR_GEN_32p32imm
    4419             :   { 1001,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1001 = INT_PTX_ATOM_XOR_GEN_32p32reg
    4420             :   { 1002,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1002 = INT_PTX_ATOM_XOR_GEN_32p64imm
    4421             :   { 1003,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1003 = INT_PTX_ATOM_XOR_GEN_32p64reg
    4422             :   { 1004,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #1004 = INT_PTX_ATOM_XOR_GEN_64_USE_Gp32imm
    4423             :   { 1005,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #1005 = INT_PTX_ATOM_XOR_GEN_64_USE_Gp32reg
    4424             :   { 1006,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1006 = INT_PTX_ATOM_XOR_GEN_64_USE_Gp64imm
    4425             :   { 1007,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1007 = INT_PTX_ATOM_XOR_GEN_64_USE_Gp64reg
    4426             :   { 1008,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #1008 = INT_PTX_ATOM_XOR_GEN_64p32imm
    4427             :   { 1009,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #1009 = INT_PTX_ATOM_XOR_GEN_64p32reg
    4428             :   { 1010,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1010 = INT_PTX_ATOM_XOR_GEN_64p64imm
    4429             :   { 1011,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1011 = INT_PTX_ATOM_XOR_GEN_64p64reg
    4430             :   { 1012,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1012 = INT_PTX_ATOM_XOR_G_32p32imm
    4431             :   { 1013,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1013 = INT_PTX_ATOM_XOR_G_32p32reg
    4432             :   { 1014,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1014 = INT_PTX_ATOM_XOR_G_32p64imm
    4433             :   { 1015,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1015 = INT_PTX_ATOM_XOR_G_32p64reg
    4434             :   { 1016,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #1016 = INT_PTX_ATOM_XOR_G_64p32imm
    4435             :   { 1017,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #1017 = INT_PTX_ATOM_XOR_G_64p32reg
    4436             :   { 1018,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1018 = INT_PTX_ATOM_XOR_G_64p64imm
    4437             :   { 1019,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1019 = INT_PTX_ATOM_XOR_G_64p64reg
    4438             :   { 1020,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1020 = INT_PTX_ATOM_XOR_S_32p32imm
    4439             :   { 1021,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1021 = INT_PTX_ATOM_XOR_S_32p32reg
    4440             :   { 1022,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1022 = INT_PTX_ATOM_XOR_S_32p64imm
    4441             :   { 1023,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1023 = INT_PTX_ATOM_XOR_S_32p64reg
    4442             :   { 1024,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #1024 = INT_PTX_ATOM_XOR_S_64p32imm
    4443             :   { 1025,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #1025 = INT_PTX_ATOM_XOR_S_64p32reg
    4444             :   { 1026,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1026 = INT_PTX_ATOM_XOR_S_64p64imm
    4445             :   { 1027,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1027 = INT_PTX_ATOM_XOR_S_64p64reg
    4446             :   { 1028,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr },  // Inst #1028 = INT_PTX_LDG_GLOBAL_f16areg
    4447             :   { 1029,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr },  // Inst #1029 = INT_PTX_LDG_GLOBAL_f16areg64
    4448             :   { 1030,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #1030 = INT_PTX_LDG_GLOBAL_f16ari
    4449             :   { 1031,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr },  // Inst #1031 = INT_PTX_LDG_GLOBAL_f16ari64
    4450             :   { 1032,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr },  // Inst #1032 = INT_PTX_LDG_GLOBAL_f16avar
    4451             :   { 1033,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #1033 = INT_PTX_LDG_GLOBAL_f16x2areg
    4452             :   { 1034,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr },  // Inst #1034 = INT_PTX_LDG_GLOBAL_f16x2areg64
    4453             :   { 1035,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr },  // Inst #1035 = INT_PTX_LDG_GLOBAL_f16x2ari
    4454             :   { 1036,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #1036 = INT_PTX_LDG_GLOBAL_f16x2ari64
    4455             :   { 1037,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr },  // Inst #1037 = INT_PTX_LDG_GLOBAL_f16x2avar
    4456             :   { 1038,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #1038 = INT_PTX_LDG_GLOBAL_f32areg
    4457             :   { 1039,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr },  // Inst #1039 = INT_PTX_LDG_GLOBAL_f32areg64
    4458             :   { 1040,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #1040 = INT_PTX_LDG_GLOBAL_f32ari
    4459             :   { 1041,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr },  // Inst #1041 = INT_PTX_LDG_GLOBAL_f32ari64
    4460             :   { 1042,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr },  // Inst #1042 = INT_PTX_LDG_GLOBAL_f32avar
    4461             :   { 1043,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr },  // Inst #1043 = INT_PTX_LDG_GLOBAL_f64areg
    4462             :   { 1044,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #1044 = INT_PTX_LDG_GLOBAL_f64areg64
    4463             :   { 1045,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr },  // Inst #1045 = INT_PTX_LDG_GLOBAL_f64ari
    4464             :   { 1046,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr },  // Inst #1046 = INT_PTX_LDG_GLOBAL_f64ari64
    4465             :   { 1047,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo170, -1 ,nullptr },  // Inst #1047 = INT_PTX_LDG_GLOBAL_f64avar
    4466             :   { 1048,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr },  // Inst #1048 = INT_PTX_LDG_GLOBAL_i16areg
    4467             :   { 1049,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1049 = INT_PTX_LDG_GLOBAL_i16areg64
    4468             :   { 1050,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1050 = INT_PTX_LDG_GLOBAL_i16ari
    4469             :   { 1051,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr },  // Inst #1051 = INT_PTX_LDG_GLOBAL_i16ari64
    4470             :   { 1052,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1052 = INT_PTX_LDG_GLOBAL_i16avar
    4471             :   { 1053,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #1053 = INT_PTX_LDG_GLOBAL_i32areg
    4472             :   { 1054,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #1054 = INT_PTX_LDG_GLOBAL_i32areg64
    4473             :   { 1055,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr },  // Inst #1055 = INT_PTX_LDG_GLOBAL_i32ari
    4474             :   { 1056,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr },  // Inst #1056 = INT_PTX_LDG_GLOBAL_i32ari64
    4475             :   { 1057,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr },  // Inst #1057 = INT_PTX_LDG_GLOBAL_i32avar
    4476             :   { 1058,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo179, -1 ,nullptr },  // Inst #1058 = INT_PTX_LDG_GLOBAL_i64areg
    4477             :   { 1059,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #1059 = INT_PTX_LDG_GLOBAL_i64areg64
    4478             :   { 1060,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr },  // Inst #1060 = INT_PTX_LDG_GLOBAL_i64ari
    4479             :   { 1061,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr },  // Inst #1061 = INT_PTX_LDG_GLOBAL_i64ari64
    4480             :   { 1062,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr },  // Inst #1062 = INT_PTX_LDG_GLOBAL_i64avar
    4481             :   { 1063,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr },  // Inst #1063 = INT_PTX_LDG_GLOBAL_i8areg
    4482             :   { 1064,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1064 = INT_PTX_LDG_GLOBAL_i8areg64
    4483             :   { 1065,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1065 = INT_PTX_LDG_GLOBAL_i8ari
    4484             :   { 1066,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr },  // Inst #1066 = INT_PTX_LDG_GLOBAL_i8ari64
    4485             :   { 1067,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1067 = INT_PTX_LDG_GLOBAL_i8avar
    4486             :   { 1068,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #1068 = INT_PTX_LDG_GLOBAL_p32areg
    4487             :   { 1069,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #1069 = INT_PTX_LDG_GLOBAL_p32areg64
    4488             :   { 1070,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr },  // Inst #1070 = INT_PTX_LDG_GLOBAL_p32ari
    4489             :   { 1071,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr },  // Inst #1071 = INT_PTX_LDG_GLOBAL_p32ari64
    4490             :   { 1072,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr },  // Inst #1072 = INT_PTX_LDG_GLOBAL_p32avar
    4491             :   { 1073,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo179, -1 ,nullptr },  // Inst #1073 = INT_PTX_LDG_GLOBAL_p64areg
    4492             :   { 1074,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #1074 = INT_PTX_LDG_GLOBAL_p64areg64
    4493             :   { 1075,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr },  // Inst #1075 = INT_PTX_LDG_GLOBAL_p64ari
    4494             :   { 1076,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr },  // Inst #1076 = INT_PTX_LDG_GLOBAL_p64ari64
    4495             :   { 1077,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr },  // Inst #1077 = INT_PTX_LDG_GLOBAL_p64avar
    4496             :   { 1078,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1078 = INT_PTX_LDG_G_v2f16_ELE_areg32
    4497             :   { 1079,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr },  // Inst #1079 = INT_PTX_LDG_G_v2f16_ELE_areg64
    4498             :   { 1080,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr },  // Inst #1080 = INT_PTX_LDG_G_v2f16_ELE_ari32
    4499             :   { 1081,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr },  // Inst #1081 = INT_PTX_LDG_G_v2f16_ELE_ari64
    4500             :   { 1082,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #1082 = INT_PTX_LDG_G_v2f16_ELE_avar
    4501             :   { 1083,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr },  // Inst #1083 = INT_PTX_LDG_G_v2f16x2_ELE_areg32
    4502             :   { 1084,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo188, -1 ,nullptr },  // Inst #1084 = INT_PTX_LDG_G_v2f16x2_ELE_areg64
    4503             :   { 1085,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr },  // Inst #1085 = INT_PTX_LDG_G_v2f16x2_ELE_ari32
    4504             :   { 1086,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr },  // Inst #1086 = INT_PTX_LDG_G_v2f16x2_ELE_ari64
    4505             :   { 1087,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr },  // Inst #1087 = INT_PTX_LDG_G_v2f16x2_ELE_avar
    4506             :   { 1088,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1088 = INT_PTX_LDG_G_v2f32_ELE_areg32
    4507             :   { 1089,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1089 = INT_PTX_LDG_G_v2f32_ELE_areg64
    4508             :   { 1090,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #1090 = INT_PTX_LDG_G_v2f32_ELE_ari32
    4509             :   { 1091,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1091 = INT_PTX_LDG_G_v2f32_ELE_ari64
    4510             :   { 1092,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr },  // Inst #1092 = INT_PTX_LDG_G_v2f32_ELE_avar
    4511             :   { 1093,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr },  // Inst #1093 = INT_PTX_LDG_G_v2f64_ELE_areg32
    4512             :   { 1094,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr },  // Inst #1094 = INT_PTX_LDG_G_v2f64_ELE_areg64
    4513             :   { 1095,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr },  // Inst #1095 = INT_PTX_LDG_G_v2f64_ELE_ari32
    4514             :   { 1096,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #1096 = INT_PTX_LDG_G_v2f64_ELE_ari64
    4515             :   { 1097,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr },  // Inst #1097 = INT_PTX_LDG_G_v2f64_ELE_avar
    4516             :   { 1098,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr },  // Inst #1098 = INT_PTX_LDG_G_v2i16_ELE_areg32
    4517             :   { 1099,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr },  // Inst #1099 = INT_PTX_LDG_G_v2i16_ELE_areg64
    4518             :   { 1100,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr },  // Inst #1100 = INT_PTX_LDG_G_v2i16_ELE_ari32
    4519             :   { 1101,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr },  // Inst #1101 = INT_PTX_LDG_G_v2i16_ELE_ari64
    4520             :   { 1102,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #1102 = INT_PTX_LDG_G_v2i16_ELE_avar
    4521             :   { 1103,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1103 = INT_PTX_LDG_G_v2i32_ELE_areg32
    4522             :   { 1104,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr },  // Inst #1104 = INT_PTX_LDG_G_v2i32_ELE_areg64
    4523             :   { 1105,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo203, -1 ,nullptr },  // Inst #1105 = INT_PTX_LDG_G_v2i32_ELE_ari32
    4524             :   { 1106,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr },  // Inst #1106 = INT_PTX_LDG_G_v2i32_ELE_ari64
    4525             :   { 1107,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1107 = INT_PTX_LDG_G_v2i32_ELE_avar
    4526             :   { 1108,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr },  // Inst #1108 = INT_PTX_LDG_G_v2i64_ELE_areg32
    4527             :   { 1109,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1109 = INT_PTX_LDG_G_v2i64_ELE_areg64
    4528             :   { 1110,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr },  // Inst #1110 = INT_PTX_LDG_G_v2i64_ELE_ari32
    4529             :   { 1111,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr },  // Inst #1111 = INT_PTX_LDG_G_v2i64_ELE_ari64
    4530             :   { 1112,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #1112 = INT_PTX_LDG_G_v2i64_ELE_avar
    4531             :   { 1113,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr },  // Inst #1113 = INT_PTX_LDG_G_v2i8_ELE_areg32
    4532             :   { 1114,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr },  // Inst #1114 = INT_PTX_LDG_G_v2i8_ELE_areg64
    4533             :   { 1115,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr },  // Inst #1115 = INT_PTX_LDG_G_v2i8_ELE_ari32
    4534             :   { 1116,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr },  // Inst #1116 = INT_PTX_LDG_G_v2i8_ELE_ari64
    4535             :   { 1117,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #1117 = INT_PTX_LDG_G_v2i8_ELE_avar
    4536             :   { 1118,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr },  // Inst #1118 = INT_PTX_LDG_G_v4f16_ELE_areg32
    4537             :   { 1119,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr },  // Inst #1119 = INT_PTX_LDG_G_v4f16_ELE_areg64
    4538             :   { 1120,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1120 = INT_PTX_LDG_G_v4f16_ELE_ari32
    4539             :   { 1121,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1121 = INT_PTX_LDG_G_v4f16_ELE_ari64
    4540             :   { 1122,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo212, -1 ,nullptr },  // Inst #1122 = INT_PTX_LDG_G_v4f16_ELE_avar
    4541             :   { 1123,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo213, -1 ,nullptr },  // Inst #1123 = INT_PTX_LDG_G_v4f16x2_ELE_areg32
    4542             :   { 1124,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo214, -1 ,nullptr },  // Inst #1124 = INT_PTX_LDG_G_v4f16x2_ELE_areg64
    4543             :   { 1125,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo215, -1 ,nullptr },  // Inst #1125 = INT_PTX_LDG_G_v4f16x2_ELE_ari32
    4544             :   { 1126,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr },  // Inst #1126 = INT_PTX_LDG_G_v4f16x2_ELE_ari64
    4545             :   { 1127,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr },  // Inst #1127 = INT_PTX_LDG_G_v4f16x2_ELE_avar
    4546             :   { 1128,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr },  // Inst #1128 = INT_PTX_LDG_G_v4f32_ELE_areg32
    4547             :   { 1129,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo219, -1 ,nullptr },  // Inst #1129 = INT_PTX_LDG_G_v4f32_ELE_areg64
    4548             :   { 1130,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo220, -1 ,nullptr },  // Inst #1130 = INT_PTX_LDG_G_v4f32_ELE_ari32
    4549             :   { 1131,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr },  // Inst #1131 = INT_PTX_LDG_G_v4f32_ELE_ari64
    4550             :   { 1132,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr },  // Inst #1132 = INT_PTX_LDG_G_v4f32_ELE_avar
    4551             :   { 1133,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr },  // Inst #1133 = INT_PTX_LDG_G_v4i16_ELE_areg32
    4552             :   { 1134,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr },  // Inst #1134 = INT_PTX_LDG_G_v4i16_ELE_areg64
    4553             :   { 1135,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr },  // Inst #1135 = INT_PTX_LDG_G_v4i16_ELE_ari32
    4554             :   { 1136,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr },  // Inst #1136 = INT_PTX_LDG_G_v4i16_ELE_ari64
    4555             :   { 1137,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr },  // Inst #1137 = INT_PTX_LDG_G_v4i16_ELE_avar
    4556             :   { 1138,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr },  // Inst #1138 = INT_PTX_LDG_G_v4i32_ELE_areg32
    4557             :   { 1139,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr },  // Inst #1139 = INT_PTX_LDG_G_v4i32_ELE_areg64
    4558             :   { 1140,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr },  // Inst #1140 = INT_PTX_LDG_G_v4i32_ELE_ari32
    4559             :   { 1141,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr },  // Inst #1141 = INT_PTX_LDG_G_v4i32_ELE_ari64
    4560             :   { 1142,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr },  // Inst #1142 = INT_PTX_LDG_G_v4i32_ELE_avar
    4561             :   { 1143,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr },  // Inst #1143 = INT_PTX_LDG_G_v4i8_ELE_areg32
    4562             :   { 1144,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr },  // Inst #1144 = INT_PTX_LDG_G_v4i8_ELE_areg64
    4563             :   { 1145,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr },  // Inst #1145 = INT_PTX_LDG_G_v4i8_ELE_ari32
    4564             :   { 1146,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr },  // Inst #1146 = INT_PTX_LDG_G_v4i8_ELE_ari64
    4565             :   { 1147,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr },  // Inst #1147 = INT_PTX_LDG_G_v4i8_ELE_avar
    4566             :   { 1148,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr },  // Inst #1148 = INT_PTX_LDU_GLOBAL_f16areg
    4567             :   { 1149,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr },  // Inst #1149 = INT_PTX_LDU_GLOBAL_f16areg64
    4568             :   { 1150,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #1150 = INT_PTX_LDU_GLOBAL_f16ari
    4569             :   { 1151,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr },  // Inst #1151 = INT_PTX_LDU_GLOBAL_f16ari64
    4570             :   { 1152,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr },  // Inst #1152 = INT_PTX_LDU_GLOBAL_f16avar
    4571             :   { 1153,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #1153 = INT_PTX_LDU_GLOBAL_f16x2areg
    4572             :   { 1154,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr },  // Inst #1154 = INT_PTX_LDU_GLOBAL_f16x2areg64
    4573             :   { 1155,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr },  // Inst #1155 = INT_PTX_LDU_GLOBAL_f16x2ari
    4574             :   { 1156,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #1156 = INT_PTX_LDU_GLOBAL_f16x2ari64
    4575             :   { 1157,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr },  // Inst #1157 = INT_PTX_LDU_GLOBAL_f16x2avar
    4576             :   { 1158,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #1158 = INT_PTX_LDU_GLOBAL_f32areg
    4577             :   { 1159,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr },  // Inst #1159 = INT_PTX_LDU_GLOBAL_f32areg64
    4578             :   { 1160,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #1160 = INT_PTX_LDU_GLOBAL_f32ari
    4579             :   { 1161,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr },  // Inst #1161 = INT_PTX_LDU_GLOBAL_f32ari64
    4580             :   { 1162,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr },  // Inst #1162 = INT_PTX_LDU_GLOBAL_f32avar
    4581             :   { 1163,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr },  // Inst #1163 = INT_PTX_LDU_GLOBAL_f64areg
    4582             :   { 1164,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #1164 = INT_PTX_LDU_GLOBAL_f64areg64
    4583             :   { 1165,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr },  // Inst #1165 = INT_PTX_LDU_GLOBAL_f64ari
    4584             :   { 1166,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr },  // Inst #1166 = INT_PTX_LDU_GLOBAL_f64ari64
    4585             :   { 1167,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo170, -1 ,nullptr },  // Inst #1167 = INT_PTX_LDU_GLOBAL_f64avar
    4586             :   { 1168,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr },  // Inst #1168 = INT_PTX_LDU_GLOBAL_i16areg
    4587             :   { 1169,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1169 = INT_PTX_LDU_GLOBAL_i16areg64
    4588             :   { 1170,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1170 = INT_PTX_LDU_GLOBAL_i16ari
    4589             :   { 1171,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr },  // Inst #1171 = INT_PTX_LDU_GLOBAL_i16ari64
    4590             :   { 1172,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1172 = INT_PTX_LDU_GLOBAL_i16avar
    4591             :   { 1173,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #1173 = INT_PTX_LDU_GLOBAL_i32areg
    4592             :   { 1174,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #1174 = INT_PTX_LDU_GLOBAL_i32areg64
    4593             :   { 1175,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr },  // Inst #1175 = INT_PTX_LDU_GLOBAL_i32ari
    4594             :   { 1176,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr },  // Inst #1176 = INT_PTX_LDU_GLOBAL_i32ari64
    4595             :   { 1177,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr },  // Inst #1177 = INT_PTX_LDU_GLOBAL_i32avar
    4596             :   { 1178,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo179, -1 ,nullptr },  // Inst #1178 = INT_PTX_LDU_GLOBAL_i64areg
    4597             :   { 1179,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #1179 = INT_PTX_LDU_GLOBAL_i64areg64
    4598             :   { 1180,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr },  // Inst #1180 = INT_PTX_LDU_GLOBAL_i64ari
    4599             :   { 1181,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr },  // Inst #1181 = INT_PTX_LDU_GLOBAL_i64ari64
    4600             :   { 1182,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr },  // Inst #1182 = INT_PTX_LDU_GLOBAL_i64avar
    4601             :   { 1183,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr },  // Inst #1183 = INT_PTX_LDU_GLOBAL_i8areg
    4602             :   { 1184,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1184 = INT_PTX_LDU_GLOBAL_i8areg64
    4603             :   { 1185,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1185 = INT_PTX_LDU_GLOBAL_i8ari
    4604             :   { 1186,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr },  // Inst #1186 = INT_PTX_LDU_GLOBAL_i8ari64
    4605             :   { 1187,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1187 = INT_PTX_LDU_GLOBAL_i8avar
    4606             :   { 1188,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #1188 = INT_PTX_LDU_GLOBAL_p32areg
    4607             :   { 1189,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #1189 = INT_PTX_LDU_GLOBAL_p32areg64
    4608             :   { 1190,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr },  // Inst #1190 = INT_PTX_LDU_GLOBAL_p32ari
    4609             :   { 1191,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr },  // Inst #1191 = INT_PTX_LDU_GLOBAL_p32ari64
    4610             :   { 1192,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr },  // Inst #1192 = INT_PTX_LDU_GLOBAL_p32avar
    4611             :   { 1193,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo179, -1 ,nullptr },  // Inst #1193 = INT_PTX_LDU_GLOBAL_p64areg
    4612             :   { 1194,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #1194 = INT_PTX_LDU_GLOBAL_p64areg64
    4613             :   { 1195,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr },  // Inst #1195 = INT_PTX_LDU_GLOBAL_p64ari
    4614             :   { 1196,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr },  // Inst #1196 = INT_PTX_LDU_GLOBAL_p64ari64
    4615             :   { 1197,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr },  // Inst #1197 = INT_PTX_LDU_GLOBAL_p64avar
    4616             :   { 1198,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1198 = INT_PTX_LDU_G_v2f16_ELE_areg32
    4617             :   { 1199,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr },  // Inst #1199 = INT_PTX_LDU_G_v2f16_ELE_areg64
    4618             :   { 1200,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr },  // Inst #1200 = INT_PTX_LDU_G_v2f16_ELE_ari32
    4619             :   { 1201,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr },  // Inst #1201 = INT_PTX_LDU_G_v2f16_ELE_ari64
    4620             :   { 1202,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #1202 = INT_PTX_LDU_G_v2f16_ELE_avar
    4621             :   { 1203,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr },  // Inst #1203 = INT_PTX_LDU_G_v2f16x2_ELE_areg32
    4622             :   { 1204,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo188, -1 ,nullptr },  // Inst #1204 = INT_PTX_LDU_G_v2f16x2_ELE_areg64
    4623             :   { 1205,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr },  // Inst #1205 = INT_PTX_LDU_G_v2f16x2_ELE_ari32
    4624             :   { 1206,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr },  // Inst #1206 = INT_PTX_LDU_G_v2f16x2_ELE_ari64
    4625             :   { 1207,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr },  // Inst #1207 = INT_PTX_LDU_G_v2f16x2_ELE_avar
    4626             :   { 1208,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1208 = INT_PTX_LDU_G_v2f32_ELE_areg32
    4627             :   { 1209,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1209 = INT_PTX_LDU_G_v2f32_ELE_areg64
    4628             :   { 1210,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #1210 = INT_PTX_LDU_G_v2f32_ELE_ari32
    4629             :   { 1211,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1211 = INT_PTX_LDU_G_v2f32_ELE_ari64
    4630             :   { 1212,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr },  // Inst #1212 = INT_PTX_LDU_G_v2f32_ELE_avar
    4631             :   { 1213,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr },  // Inst #1213 = INT_PTX_LDU_G_v2f64_ELE_areg32
    4632             :   { 1214,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr },  // Inst #1214 = INT_PTX_LDU_G_v2f64_ELE_areg64
    4633             :   { 1215,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr },  // Inst #1215 = INT_PTX_LDU_G_v2f64_ELE_ari32
    4634             :   { 1216,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #1216 = INT_PTX_LDU_G_v2f64_ELE_ari64
    4635             :   { 1217,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr },  // Inst #1217 = INT_PTX_LDU_G_v2f64_ELE_avar
    4636             :   { 1218,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr },  // Inst #1218 = INT_PTX_LDU_G_v2i16_ELE_areg32
    4637             :   { 1219,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr },  // Inst #1219 = INT_PTX_LDU_G_v2i16_ELE_areg64
    4638             :   { 1220,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr },  // Inst #1220 = INT_PTX_LDU_G_v2i16_ELE_ari32
    4639             :   { 1221,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr },  // Inst #1221 = INT_PTX_LDU_G_v2i16_ELE_ari64
    4640             :   { 1222,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #1222 = INT_PTX_LDU_G_v2i16_ELE_avar
    4641             :   { 1223,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1223 = INT_PTX_LDU_G_v2i32_ELE_areg32
    4642             :   { 1224,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr },  // Inst #1224 = INT_PTX_LDU_G_v2i32_ELE_areg64
    4643             :   { 1225,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo203, -1 ,nullptr },  // Inst #1225 = INT_PTX_LDU_G_v2i32_ELE_ari32
    4644             :   { 1226,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr },  // Inst #1226 = INT_PTX_LDU_G_v2i32_ELE_ari64
    4645             :   { 1227,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1227 = INT_PTX_LDU_G_v2i32_ELE_avar
    4646             :   { 1228,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr },  // Inst #1228 = INT_PTX_LDU_G_v2i64_ELE_areg32
    4647             :   { 1229,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1229 = INT_PTX_LDU_G_v2i64_ELE_areg64
    4648             :   { 1230,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr },  // Inst #1230 = INT_PTX_LDU_G_v2i64_ELE_ari32
    4649             :   { 1231,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr },  // Inst #1231 = INT_PTX_LDU_G_v2i64_ELE_ari64
    4650             :   { 1232,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #1232 = INT_PTX_LDU_G_v2i64_ELE_avar
    4651             :   { 1233,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr },  // Inst #1233 = INT_PTX_LDU_G_v2i8_ELE_areg32
    4652             :   { 1234,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr },  // Inst #1234 = INT_PTX_LDU_G_v2i8_ELE_areg64
    4653             :   { 1235,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr },  // Inst #1235 = INT_PTX_LDU_G_v2i8_ELE_ari32
    4654             :   { 1236,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr },  // Inst #1236 = INT_PTX_LDU_G_v2i8_ELE_ari64
    4655             :   { 1237,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #1237 = INT_PTX_LDU_G_v2i8_ELE_avar
    4656             :   { 1238,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr },  // Inst #1238 = INT_PTX_LDU_G_v4f16_ELE_areg32
    4657             :   { 1239,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr },  // Inst #1239 = INT_PTX_LDU_G_v4f16_ELE_areg64
    4658             :   { 1240,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1240 = INT_PTX_LDU_G_v4f16_ELE_ari32
    4659             :   { 1241,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1241 = INT_PTX_LDU_G_v4f16_ELE_ari64
    4660             :   { 1242,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo212, -1 ,nullptr },  // Inst #1242 = INT_PTX_LDU_G_v4f16_ELE_avar
    4661             :   { 1243,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo213, -1 ,nullptr },  // Inst #1243 = INT_PTX_LDU_G_v4f16x2_ELE_areg32
    4662             :   { 1244,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo214, -1 ,nullptr },  // Inst #1244 = INT_PTX_LDU_G_v4f16x2_ELE_areg64
    4663             :   { 1245,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo215, -1 ,nullptr },  // Inst #1245 = INT_PTX_LDU_G_v4f16x2_ELE_ari32
    4664             :   { 1246,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr },  // Inst #1246 = INT_PTX_LDU_G_v4f16x2_ELE_ari64
    4665             :   { 1247,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr },  // Inst #1247 = INT_PTX_LDU_G_v4f16x2_ELE_avar
    4666             :   { 1248,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr },  // Inst #1248 = INT_PTX_LDU_G_v4f32_ELE_areg32
    4667             :   { 1249,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo219, -1 ,nullptr },  // Inst #1249 = INT_PTX_LDU_G_v4f32_ELE_areg64
    4668             :   { 1250,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo220, -1 ,nullptr },  // Inst #1250 = INT_PTX_LDU_G_v4f32_ELE_ari32
    4669             :   { 1251,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr },  // Inst #1251 = INT_PTX_LDU_G_v4f32_ELE_ari64
    4670             :   { 1252,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr },  // Inst #1252 = INT_PTX_LDU_G_v4f32_ELE_avar
    4671             :   { 1253,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr },  // Inst #1253 = INT_PTX_LDU_G_v4i16_ELE_areg32
    4672             :   { 1254,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr },  // Inst #1254 = INT_PTX_LDU_G_v4i16_ELE_areg64
    4673             :   { 1255,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr },  // Inst #1255 = INT_PTX_LDU_G_v4i16_ELE_ari32
    4674             :   { 1256,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr },  // Inst #1256 = INT_PTX_LDU_G_v4i16_ELE_ari64
    4675             :   { 1257,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr },  // Inst #1257 = INT_PTX_LDU_G_v4i16_ELE_avar
    4676             :   { 1258,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr },  // Inst #1258 = INT_PTX_LDU_G_v4i32_ELE_areg32
    4677             :   { 1259,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr },  // Inst #1259 = INT_PTX_LDU_G_v4i32_ELE_areg64
    4678             :   { 1260,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr },  // Inst #1260 = INT_PTX_LDU_G_v4i32_ELE_ari32
    4679             :   { 1261,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr },  // Inst #1261 = INT_PTX_LDU_G_v4i32_ELE_ari64
    4680             :   { 1262,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr },  // Inst #1262 = INT_PTX_LDU_G_v4i32_ELE_avar
    4681             :   { 1263,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr },  // Inst #1263 = INT_PTX_LDU_G_v4i8_ELE_areg32
    4682             :   { 1264,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr },  // Inst #1264 = INT_PTX_LDU_G_v4i8_ELE_areg64
    4683             :   { 1265,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr },  // Inst #1265 = INT_PTX_LDU_G_v4i8_ELE_ari32
    4684             :   { 1266,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr },  // Inst #1266 = INT_PTX_LDU_G_v4i8_ELE_ari64
    4685             :   { 1267,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr },  // Inst #1267 = INT_PTX_LDU_G_v4i8_ELE_avar
    4686             :   { 1268,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr },  // Inst #1268 = INT_PTX_SATOM_ADD_f32_cta_gen_anonymous_1062anonymous_1050
    4687             :   { 1269,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr },  // Inst #1269 = INT_PTX_SATOM_ADD_f32_cta_gen_anonymous_1062anonymous_1051
    4688             :   { 1270,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr },  // Inst #1270 = INT_PTX_SATOM_ADD_f32_cta_gen_anonymous_1062anonymous_1052
    4689             :   { 1271,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #1271 = INT_PTX_SATOM_ADD_f32_cta_gen_anonymous_1062anonymous_1053
    4690             :   { 1272,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr },  // Inst #1272 = INT_PTX_SATOM_ADD_f32_sys_gen_anonymous_1062anonymous_1050
    4691             :   { 1273,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr },  // Inst #1273 = INT_PTX_SATOM_ADD_f32_sys_gen_anonymous_1062anonymous_1051
    4692             :   { 1274,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr },  // Inst #1274 = INT_PTX_SATOM_ADD_f32_sys_gen_anonymous_1062anonymous_1052
    4693             :   { 1275,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #1275 = INT_PTX_SATOM_ADD_f32_sys_gen_anonymous_1062anonymous_1053
    4694             :   { 1276,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo232, -1 ,nullptr },  // Inst #1276 = INT_PTX_SATOM_ADD_f64_cta_gen_anonymous_1062anonymous_1050
    4695             :   { 1277,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr },  // Inst #1277 = INT_PTX_SATOM_ADD_f64_cta_gen_anonymous_1062anonymous_1051
    4696             :   { 1278,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr },  // Inst #1278 = INT_PTX_SATOM_ADD_f64_cta_gen_anonymous_1062anonymous_1052
    4697             :   { 1279,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo235, -1 ,nullptr },  // Inst #1279 = INT_PTX_SATOM_ADD_f64_cta_gen_anonymous_1062anonymous_1053
    4698             :   { 1280,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo232, -1 ,nullptr },  // Inst #1280 = INT_PTX_SATOM_ADD_f64_sys_gen_anonymous_1062anonymous_1050
    4699             :   { 1281,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr },  // Inst #1281 = INT_PTX_SATOM_ADD_f64_sys_gen_anonymous_1062anonymous_1051
    4700             :   { 1282,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr },  // Inst #1282 = INT_PTX_SATOM_ADD_f64_sys_gen_anonymous_1062anonymous_1052
    4701             :   { 1283,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo235, -1 ,nullptr },  // Inst #1283 = INT_PTX_SATOM_ADD_f64_sys_gen_anonymous_1062anonymous_1053
    4702             :   { 1284,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1284 = INT_PTX_SATOM_ADD_s32_cta_gen_anonymous_1062anonymous_1050
    4703             :   { 1285,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1285 = INT_PTX_SATOM_ADD_s32_cta_gen_anonymous_1062anonymous_1051
    4704             :   { 1286,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1286 = INT_PTX_SATOM_ADD_s32_cta_gen_anonymous_1062anonymous_1052
    4705             :   { 1287,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1287 = INT_PTX_SATOM_ADD_s32_cta_gen_anonymous_1062anonymous_1053
    4706             :   { 1288,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1288 = INT_PTX_SATOM_ADD_s32_sys_gen_anonymous_1062anonymous_1050
    4707             :   { 1289,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1289 = INT_PTX_SATOM_ADD_s32_sys_gen_anonymous_1062anonymous_1051
    4708             :   { 1290,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1290 = INT_PTX_SATOM_ADD_s32_sys_gen_anonymous_1062anonymous_1052
    4709             :   { 1291,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1291 = INT_PTX_SATOM_ADD_s32_sys_gen_anonymous_1062anonymous_1053
    4710             :   { 1292,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1292 = INT_PTX_SATOM_ADD_u32_cta_gen_anonymous_1062anonymous_1050
    4711             :   { 1293,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1293 = INT_PTX_SATOM_ADD_u32_cta_gen_anonymous_1062anonymous_1051
    4712             :   { 1294,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1294 = INT_PTX_SATOM_ADD_u32_cta_gen_anonymous_1062anonymous_1052
    4713             :   { 1295,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1295 = INT_PTX_SATOM_ADD_u32_cta_gen_anonymous_1062anonymous_1053
    4714             :   { 1296,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1296 = INT_PTX_SATOM_ADD_u32_sys_gen_anonymous_1062anonymous_1050
    4715             :   { 1297,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1297 = INT_PTX_SATOM_ADD_u32_sys_gen_anonymous_1062anonymous_1051
    4716             :   { 1298,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1298 = INT_PTX_SATOM_ADD_u32_sys_gen_anonymous_1062anonymous_1052
    4717             :   { 1299,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1299 = INT_PTX_SATOM_ADD_u32_sys_gen_anonymous_1062anonymous_1053
    4718             :   { 1300,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #1300 = INT_PTX_SATOM_ADD_u64_cta_gen_anonymous_1062anonymous_1050
    4719             :   { 1301,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1301 = INT_PTX_SATOM_ADD_u64_cta_gen_anonymous_1062anonymous_1051
    4720             :   { 1302,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #1302 = INT_PTX_SATOM_ADD_u64_cta_gen_anonymous_1062anonymous_1052
    4721             :   { 1303,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1303 = INT_PTX_SATOM_ADD_u64_cta_gen_anonymous_1062anonymous_1053
    4722             :   { 1304,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #1304 = INT_PTX_SATOM_ADD_u64_sys_gen_anonymous_1062anonymous_1050
    4723             :   { 1305,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1305 = INT_PTX_SATOM_ADD_u64_sys_gen_anonymous_1062anonymous_1051
    4724             :   { 1306,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #1306 = INT_PTX_SATOM_ADD_u64_sys_gen_anonymous_1062anonymous_1052
    4725             :   { 1307,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1307 = INT_PTX_SATOM_ADD_u64_sys_gen_anonymous_1062anonymous_1053
    4726             :   { 1308,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1308 = INT_PTX_SATOM_AND_b32_cta_gen_anonymous_1062anonymous_1050
    4727             :   { 1309,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1309 = INT_PTX_SATOM_AND_b32_cta_gen_anonymous_1062anonymous_1051
    4728             :   { 1310,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1310 = INT_PTX_SATOM_AND_b32_cta_gen_anonymous_1062anonymous_1052
    4729             :   { 1311,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1311 = INT_PTX_SATOM_AND_b32_cta_gen_anonymous_1062anonymous_1053
    4730             :   { 1312,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1312 = INT_PTX_SATOM_AND_b32_sys_gen_anonymous_1062anonymous_1050
    4731             :   { 1313,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1313 = INT_PTX_SATOM_AND_b32_sys_gen_anonymous_1062anonymous_1051
    4732             :   { 1314,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1314 = INT_PTX_SATOM_AND_b32_sys_gen_anonymous_1062anonymous_1052
    4733             :   { 1315,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1315 = INT_PTX_SATOM_AND_b32_sys_gen_anonymous_1062anonymous_1053
    4734             :   { 1316,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #1316 = INT_PTX_SATOM_AND_b64_cta_gen_anonymous_1062anonymous_1050
    4735             :   { 1317,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1317 = INT_PTX_SATOM_AND_b64_cta_gen_anonymous_1062anonymous_1051
    4736             :   { 1318,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #1318 = INT_PTX_SATOM_AND_b64_cta_gen_anonymous_1062anonymous_1052
    4737             :   { 1319,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1319 = INT_PTX_SATOM_AND_b64_cta_gen_anonymous_1062anonymous_1053
    4738             :   { 1320,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #1320 = INT_PTX_SATOM_AND_b64_sys_gen_anonymous_1062anonymous_1050
    4739             :   { 1321,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1321 = INT_PTX_SATOM_AND_b64_sys_gen_anonymous_1062anonymous_1051
    4740             :   { 1322,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #1322 = INT_PTX_SATOM_AND_b64_sys_gen_anonymous_1062anonymous_1052
    4741             :   { 1323,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1323 = INT_PTX_SATOM_AND_b64_sys_gen_anonymous_1062anonymous_1053
    4742             :   { 1324,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1324 = INT_PTX_SATOM_CAS_b32_cta_gen_anonymous_1063anonymous_1054
    4743             :   { 1325,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #1325 = INT_PTX_SATOM_CAS_b32_cta_gen_anonymous_1063anonymous_1055
    4744             :   { 1326,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr },  // Inst #1326 = INT_PTX_SATOM_CAS_b32_cta_gen_anonymous_1063anonymous_1056
    4745             :   { 1327,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #1327 = INT_PTX_SATOM_CAS_b32_cta_gen_anonymous_1063anonymous_1057
    4746             :   { 1328,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1328 = INT_PTX_SATOM_CAS_b32_cta_gen_anonymous_1063anonymous_1058
    4747             :   { 1329,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #1329 = INT_PTX_SATOM_CAS_b32_cta_gen_anonymous_1063anonymous_1059
    4748             :   { 1330,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #1330 = INT_PTX_SATOM_CAS_b32_cta_gen_anonymous_1063anonymous_1060
    4749             :   { 1331,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #1331 = INT_PTX_SATOM_CAS_b32_cta_gen_anonymous_1063anonymous_1061
    4750             :   { 1332,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1332 = INT_PTX_SATOM_CAS_b32_sys_gen_anonymous_1063anonymous_1054
    4751             :   { 1333,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #1333 = INT_PTX_SATOM_CAS_b32_sys_gen_anonymous_1063anonymous_1055
    4752             :   { 1334,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr },  // Inst #1334 = INT_PTX_SATOM_CAS_b32_sys_gen_anonymous_1063anonymous_1056
    4753             :   { 1335,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #1335 = INT_PTX_SATOM_CAS_b32_sys_gen_anonymous_1063anonymous_1057
    4754             :   { 1336,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1336 = INT_PTX_SATOM_CAS_b32_sys_gen_anonymous_1063anonymous_1058
    4755             :   { 1337,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #1337 = INT_PTX_SATOM_CAS_b32_sys_gen_anonymous_1063anonymous_1059
    4756             :   { 1338,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #1338 = INT_PTX_SATOM_CAS_b32_sys_gen_anonymous_1063anonymous_1060
    4757             :   { 1339,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #1339 = INT_PTX_SATOM_CAS_b32_sys_gen_anonymous_1063anonymous_1061
    4758             :   { 1340,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #1340 = INT_PTX_SATOM_CAS_b64_cta_gen_anonymous_1063anonymous_1054
    4759             :   { 1341,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #1341 = INT_PTX_SATOM_CAS_b64_cta_gen_anonymous_1063anonymous_1055
    4760             :   { 1342,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #1342 = INT_PTX_SATOM_CAS_b64_cta_gen_anonymous_1063anonymous_1056
    4761             :   { 1343,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #1343 = INT_PTX_SATOM_CAS_b64_cta_gen_anonymous_1063anonymous_1057
    4762             :   { 1344,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #1344 = INT_PTX_SATOM_CAS_b64_cta_gen_anonymous_1063anonymous_1058
    4763             :   { 1345,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #1345 = INT_PTX_SATOM_CAS_b64_cta_gen_anonymous_1063anonymous_1059
    4764             :   { 1346,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #1346 = INT_PTX_SATOM_CAS_b64_cta_gen_anonymous_1063anonymous_1060
    4765             :   { 1347,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #1347 = INT_PTX_SATOM_CAS_b64_cta_gen_anonymous_1063anonymous_1061
    4766             :   { 1348,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #1348 = INT_PTX_SATOM_CAS_b64_sys_gen_anonymous_1063anonymous_1054
    4767             :   { 1349,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #1349 = INT_PTX_SATOM_CAS_b64_sys_gen_anonymous_1063anonymous_1055
    4768             :   { 1350,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #1350 = INT_PTX_SATOM_CAS_b64_sys_gen_anonymous_1063anonymous_1056
    4769             :   { 1351,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #1351 = INT_PTX_SATOM_CAS_b64_sys_gen_anonymous_1063anonymous_1057
    4770             :   { 1352,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #1352 = INT_PTX_SATOM_CAS_b64_sys_gen_anonymous_1063anonymous_1058
    4771             :   { 1353,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #1353 = INT_PTX_SATOM_CAS_b64_sys_gen_anonymous_1063anonymous_1059
    4772             :   { 1354,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #1354 = INT_PTX_SATOM_CAS_b64_sys_gen_anonymous_1063anonymous_1060
    4773             :   { 1355,       4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #1355 = INT_PTX_SATOM_CAS_b64_sys_gen_anonymous_1063anonymous_1061
    4774             :   { 1356,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1356 = INT_PTX_SATOM_DEC_u32_cta_gen_anonymous_1062anonymous_1050
    4775             :   { 1357,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1357 = INT_PTX_SATOM_DEC_u32_cta_gen_anonymous_1062anonymous_1051
    4776             :   { 1358,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1358 = INT_PTX_SATOM_DEC_u32_cta_gen_anonymous_1062anonymous_1052
    4777             :   { 1359,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1359 = INT_PTX_SATOM_DEC_u32_cta_gen_anonymous_1062anonymous_1053
    4778             :   { 1360,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1360 = INT_PTX_SATOM_DEC_u32_sys_gen_anonymous_1062anonymous_1050
    4779             :   { 1361,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1361 = INT_PTX_SATOM_DEC_u32_sys_gen_anonymous_1062anonymous_1051
    4780             :   { 1362,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1362 = INT_PTX_SATOM_DEC_u32_sys_gen_anonymous_1062anonymous_1052
    4781             :   { 1363,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1363 = INT_PTX_SATOM_DEC_u32_sys_gen_anonymous_1062anonymous_1053
    4782             :   { 1364,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1364 = INT_PTX_SATOM_EXCH_b32_cta_gen_anonymous_1062anonymous_1050
    4783             :   { 1365,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1365 = INT_PTX_SATOM_EXCH_b32_cta_gen_anonymous_1062anonymous_1051
    4784             :   { 1366,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1366 = INT_PTX_SATOM_EXCH_b32_cta_gen_anonymous_1062anonymous_1052
    4785             :   { 1367,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1367 = INT_PTX_SATOM_EXCH_b32_cta_gen_anonymous_1062anonymous_1053
    4786             :   { 1368,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1368 = INT_PTX_SATOM_EXCH_b32_sys_gen_anonymous_1062anonymous_1050
    4787             :   { 1369,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1369 = INT_PTX_SATOM_EXCH_b32_sys_gen_anonymous_1062anonymous_1051
    4788             :   { 1370,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1370 = INT_PTX_SATOM_EXCH_b32_sys_gen_anonymous_1062anonymous_1052
    4789             :   { 1371,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1371 = INT_PTX_SATOM_EXCH_b32_sys_gen_anonymous_1062anonymous_1053
    4790             :   { 1372,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #1372 = INT_PTX_SATOM_EXCH_b64_cta_gen_anonymous_1062anonymous_1050
    4791             :   { 1373,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1373 = INT_PTX_SATOM_EXCH_b64_cta_gen_anonymous_1062anonymous_1051
    4792             :   { 1374,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #1374 = INT_PTX_SATOM_EXCH_b64_cta_gen_anonymous_1062anonymous_1052
    4793             :   { 1375,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1375 = INT_PTX_SATOM_EXCH_b64_cta_gen_anonymous_1062anonymous_1053
    4794             :   { 1376,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #1376 = INT_PTX_SATOM_EXCH_b64_sys_gen_anonymous_1062anonymous_1050
    4795             :   { 1377,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1377 = INT_PTX_SATOM_EXCH_b64_sys_gen_anonymous_1062anonymous_1051
    4796             :   { 1378,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #1378 = INT_PTX_SATOM_EXCH_b64_sys_gen_anonymous_1062anonymous_1052
    4797             :   { 1379,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1379 = INT_PTX_SATOM_EXCH_b64_sys_gen_anonymous_1062anonymous_1053
    4798             :   { 1380,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1380 = INT_PTX_SATOM_INC_u32_cta_gen_anonymous_1062anonymous_1050
    4799             :   { 1381,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1381 = INT_PTX_SATOM_INC_u32_cta_gen_anonymous_1062anonymous_1051
    4800             :   { 1382,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1382 = INT_PTX_SATOM_INC_u32_cta_gen_anonymous_1062anonymous_1052
    4801             :   { 1383,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1383 = INT_PTX_SATOM_INC_u32_cta_gen_anonymous_1062anonymous_1053
    4802             :   { 1384,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1384 = INT_PTX_SATOM_INC_u32_sys_gen_anonymous_1062anonymous_1050
    4803             :   { 1385,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1385 = INT_PTX_SATOM_INC_u32_sys_gen_anonymous_1062anonymous_1051
    4804             :   { 1386,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1386 = INT_PTX_SATOM_INC_u32_sys_gen_anonymous_1062anonymous_1052
    4805             :   { 1387,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1387 = INT_PTX_SATOM_INC_u32_sys_gen_anonymous_1062anonymous_1053
    4806             :   { 1388,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1388 = INT_PTX_SATOM_MAX_s32_cta_gen_anonymous_1062anonymous_1050
    4807             :   { 1389,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1389 = INT_PTX_SATOM_MAX_s32_cta_gen_anonymous_1062anonymous_1051
    4808             :   { 1390,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1390 = INT_PTX_SATOM_MAX_s32_cta_gen_anonymous_1062anonymous_1052
    4809             :   { 1391,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1391 = INT_PTX_SATOM_MAX_s32_cta_gen_anonymous_1062anonymous_1053
    4810             :   { 1392,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1392 = INT_PTX_SATOM_MAX_s32_sys_gen_anonymous_1062anonymous_1050
    4811             :   { 1393,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1393 = INT_PTX_SATOM_MAX_s32_sys_gen_anonymous_1062anonymous_1051
    4812             :   { 1394,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1394 = INT_PTX_SATOM_MAX_s32_sys_gen_anonymous_1062anonymous_1052
    4813             :   { 1395,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1395 = INT_PTX_SATOM_MAX_s32_sys_gen_anonymous_1062anonymous_1053
    4814             :   { 1396,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #1396 = INT_PTX_SATOM_MAX_s64_cta_gen_anonymous_1062anonymous_1050
    4815             :   { 1397,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1397 = INT_PTX_SATOM_MAX_s64_cta_gen_anonymous_1062anonymous_1051
    4816             :   { 1398,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #1398 = INT_PTX_SATOM_MAX_s64_cta_gen_anonymous_1062anonymous_1052
    4817             :   { 1399,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1399 = INT_PTX_SATOM_MAX_s64_cta_gen_anonymous_1062anonymous_1053
    4818             :   { 1400,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #1400 = INT_PTX_SATOM_MAX_s64_sys_gen_anonymous_1062anonymous_1050
    4819             :   { 1401,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1401 = INT_PTX_SATOM_MAX_s64_sys_gen_anonymous_1062anonymous_1051
    4820             :   { 1402,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #1402 = INT_PTX_SATOM_MAX_s64_sys_gen_anonymous_1062anonymous_1052
    4821             :   { 1403,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1403 = INT_PTX_SATOM_MAX_s64_sys_gen_anonymous_1062anonymous_1053
    4822             :   { 1404,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1404 = INT_PTX_SATOM_MAX_u32_cta_gen_anonymous_1062anonymous_1050
    4823             :   { 1405,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1405 = INT_PTX_SATOM_MAX_u32_cta_gen_anonymous_1062anonymous_1051
    4824             :   { 1406,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1406 = INT_PTX_SATOM_MAX_u32_cta_gen_anonymous_1062anonymous_1052
    4825             :   { 1407,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1407 = INT_PTX_SATOM_MAX_u32_cta_gen_anonymous_1062anonymous_1053
    4826             :   { 1408,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1408 = INT_PTX_SATOM_MAX_u32_sys_gen_anonymous_1062anonymous_1050
    4827             :   { 1409,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1409 = INT_PTX_SATOM_MAX_u32_sys_gen_anonymous_1062anonymous_1051
    4828             :   { 1410,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1410 = INT_PTX_SATOM_MAX_u32_sys_gen_anonymous_1062anonymous_1052
    4829             :   { 1411,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1411 = INT_PTX_SATOM_MAX_u32_sys_gen_anonymous_1062anonymous_1053
    4830             :   { 1412,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #1412 = INT_PTX_SATOM_MAX_u64_cta_gen_anonymous_1062anonymous_1050
    4831             :   { 1413,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1413 = INT_PTX_SATOM_MAX_u64_cta_gen_anonymous_1062anonymous_1051
    4832             :   { 1414,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #1414 = INT_PTX_SATOM_MAX_u64_cta_gen_anonymous_1062anonymous_1052
    4833             :   { 1415,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1415 = INT_PTX_SATOM_MAX_u64_cta_gen_anonymous_1062anonymous_1053
    4834             :   { 1416,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #1416 = INT_PTX_SATOM_MAX_u64_sys_gen_anonymous_1062anonymous_1050
    4835             :   { 1417,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1417 = INT_PTX_SATOM_MAX_u64_sys_gen_anonymous_1062anonymous_1051
    4836             :   { 1418,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #1418 = INT_PTX_SATOM_MAX_u64_sys_gen_anonymous_1062anonymous_1052
    4837             :   { 1419,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1419 = INT_PTX_SATOM_MAX_u64_sys_gen_anonymous_1062anonymous_1053
    4838             :   { 1420,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1420 = INT_PTX_SATOM_MIN_s32_cta_gen_anonymous_1062anonymous_1050
    4839             :   { 1421,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1421 = INT_PTX_SATOM_MIN_s32_cta_gen_anonymous_1062anonymous_1051
    4840             :   { 1422,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1422 = INT_PTX_SATOM_MIN_s32_cta_gen_anonymous_1062anonymous_1052
    4841             :   { 1423,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1423 = INT_PTX_SATOM_MIN_s32_cta_gen_anonymous_1062anonymous_1053
    4842             :   { 1424,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1424 = INT_PTX_SATOM_MIN_s32_sys_gen_anonymous_1062anonymous_1050
    4843             :   { 1425,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1425 = INT_PTX_SATOM_MIN_s32_sys_gen_anonymous_1062anonymous_1051
    4844             :   { 1426,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1426 = INT_PTX_SATOM_MIN_s32_sys_gen_anonymous_1062anonymous_1052
    4845             :   { 1427,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1427 = INT_PTX_SATOM_MIN_s32_sys_gen_anonymous_1062anonymous_1053
    4846             :   { 1428,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #1428 = INT_PTX_SATOM_MIN_s64_cta_gen_anonymous_1062anonymous_1050
    4847             :   { 1429,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1429 = INT_PTX_SATOM_MIN_s64_cta_gen_anonymous_1062anonymous_1051
    4848             :   { 1430,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #1430 = INT_PTX_SATOM_MIN_s64_cta_gen_anonymous_1062anonymous_1052
    4849             :   { 1431,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1431 = INT_PTX_SATOM_MIN_s64_cta_gen_anonymous_1062anonymous_1053
    4850             :   { 1432,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #1432 = INT_PTX_SATOM_MIN_s64_sys_gen_anonymous_1062anonymous_1050
    4851             :   { 1433,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1433 = INT_PTX_SATOM_MIN_s64_sys_gen_anonymous_1062anonymous_1051
    4852             :   { 1434,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #1434 = INT_PTX_SATOM_MIN_s64_sys_gen_anonymous_1062anonymous_1052
    4853             :   { 1435,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1435 = INT_PTX_SATOM_MIN_s64_sys_gen_anonymous_1062anonymous_1053
    4854             :   { 1436,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1436 = INT_PTX_SATOM_MIN_u32_cta_gen_anonymous_1062anonymous_1050
    4855             :   { 1437,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1437 = INT_PTX_SATOM_MIN_u32_cta_gen_anonymous_1062anonymous_1051
    4856             :   { 1438,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1438 = INT_PTX_SATOM_MIN_u32_cta_gen_anonymous_1062anonymous_1052
    4857             :   { 1439,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1439 = INT_PTX_SATOM_MIN_u32_cta_gen_anonymous_1062anonymous_1053
    4858             :   { 1440,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1440 = INT_PTX_SATOM_MIN_u32_sys_gen_anonymous_1062anonymous_1050
    4859             :   { 1441,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1441 = INT_PTX_SATOM_MIN_u32_sys_gen_anonymous_1062anonymous_1051
    4860             :   { 1442,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1442 = INT_PTX_SATOM_MIN_u32_sys_gen_anonymous_1062anonymous_1052
    4861             :   { 1443,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1443 = INT_PTX_SATOM_MIN_u32_sys_gen_anonymous_1062anonymous_1053
    4862             :   { 1444,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #1444 = INT_PTX_SATOM_MIN_u64_cta_gen_anonymous_1062anonymous_1050
    4863             :   { 1445,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1445 = INT_PTX_SATOM_MIN_u64_cta_gen_anonymous_1062anonymous_1051
    4864             :   { 1446,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #1446 = INT_PTX_SATOM_MIN_u64_cta_gen_anonymous_1062anonymous_1052
    4865             :   { 1447,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1447 = INT_PTX_SATOM_MIN_u64_cta_gen_anonymous_1062anonymous_1053
    4866             :   { 1448,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #1448 = INT_PTX_SATOM_MIN_u64_sys_gen_anonymous_1062anonymous_1050
    4867             :   { 1449,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1449 = INT_PTX_SATOM_MIN_u64_sys_gen_anonymous_1062anonymous_1051
    4868             :   { 1450,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #1450 = INT_PTX_SATOM_MIN_u64_sys_gen_anonymous_1062anonymous_1052
    4869             :   { 1451,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1451 = INT_PTX_SATOM_MIN_u64_sys_gen_anonymous_1062anonymous_1053
    4870             :   { 1452,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1452 = INT_PTX_SATOM_OR_b32_cta_gen_anonymous_1062anonymous_1050
    4871             :   { 1453,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1453 = INT_PTX_SATOM_OR_b32_cta_gen_anonymous_1062anonymous_1051
    4872             :   { 1454,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1454 = INT_PTX_SATOM_OR_b32_cta_gen_anonymous_1062anonymous_1052
    4873             :   { 1455,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1455 = INT_PTX_SATOM_OR_b32_cta_gen_anonymous_1062anonymous_1053
    4874             :   { 1456,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1456 = INT_PTX_SATOM_OR_b32_sys_gen_anonymous_1062anonymous_1050
    4875             :   { 1457,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1457 = INT_PTX_SATOM_OR_b32_sys_gen_anonymous_1062anonymous_1051
    4876             :   { 1458,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1458 = INT_PTX_SATOM_OR_b32_sys_gen_anonymous_1062anonymous_1052
    4877             :   { 1459,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1459 = INT_PTX_SATOM_OR_b32_sys_gen_anonymous_1062anonymous_1053
    4878             :   { 1460,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #1460 = INT_PTX_SATOM_OR_b64_cta_gen_anonymous_1062anonymous_1050
    4879             :   { 1461,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1461 = INT_PTX_SATOM_OR_b64_cta_gen_anonymous_1062anonymous_1051
    4880             :   { 1462,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #1462 = INT_PTX_SATOM_OR_b64_cta_gen_anonymous_1062anonymous_1052
    4881             :   { 1463,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1463 = INT_PTX_SATOM_OR_b64_cta_gen_anonymous_1062anonymous_1053
    4882             :   { 1464,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #1464 = INT_PTX_SATOM_OR_b64_sys_gen_anonymous_1062anonymous_1050
    4883             :   { 1465,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1465 = INT_PTX_SATOM_OR_b64_sys_gen_anonymous_1062anonymous_1051
    4884             :   { 1466,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #1466 = INT_PTX_SATOM_OR_b64_sys_gen_anonymous_1062anonymous_1052
    4885             :   { 1467,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1467 = INT_PTX_SATOM_OR_b64_sys_gen_anonymous_1062anonymous_1053
    4886             :   { 1468,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1468 = INT_PTX_SATOM_XOR_b32_cta_gen_anonymous_1062anonymous_1050
    4887             :   { 1469,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1469 = INT_PTX_SATOM_XOR_b32_cta_gen_anonymous_1062anonymous_1051
    4888             :   { 1470,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1470 = INT_PTX_SATOM_XOR_b32_cta_gen_anonymous_1062anonymous_1052
    4889             :   { 1471,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1471 = INT_PTX_SATOM_XOR_b32_cta_gen_anonymous_1062anonymous_1053
    4890             :   { 1472,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1472 = INT_PTX_SATOM_XOR_b32_sys_gen_anonymous_1062anonymous_1050
    4891             :   { 1473,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1473 = INT_PTX_SATOM_XOR_b32_sys_gen_anonymous_1062anonymous_1051
    4892             :   { 1474,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1474 = INT_PTX_SATOM_XOR_b32_sys_gen_anonymous_1062anonymous_1052
    4893             :   { 1475,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #1475 = INT_PTX_SATOM_XOR_b32_sys_gen_anonymous_1062anonymous_1053
    4894             :   { 1476,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #1476 = INT_PTX_SATOM_XOR_b64_cta_gen_anonymous_1062anonymous_1050
    4895             :   { 1477,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1477 = INT_PTX_SATOM_XOR_b64_cta_gen_anonymous_1062anonymous_1051
    4896             :   { 1478,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #1478 = INT_PTX_SATOM_XOR_b64_cta_gen_anonymous_1062anonymous_1052
    4897             :   { 1479,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1479 = INT_PTX_SATOM_XOR_b64_cta_gen_anonymous_1062anonymous_1053
    4898             :   { 1480,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #1480 = INT_PTX_SATOM_XOR_b64_sys_gen_anonymous_1062anonymous_1050
    4899             :   { 1481,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1481 = INT_PTX_SATOM_XOR_b64_sys_gen_anonymous_1062anonymous_1051
    4900             :   { 1482,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #1482 = INT_PTX_SATOM_XOR_b64_sys_gen_anonymous_1062anonymous_1052
    4901             :   { 1483,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1483 = INT_PTX_SATOM_XOR_b64_sys_gen_anonymous_1062anonymous_1053
    4902             :   { 1484,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1484 = INT_PTX_SREG_CLOCK
    4903             :   { 1485,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr },  // Inst #1485 = INT_PTX_SREG_CLOCK64
    4904             :   { 1486,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1486 = INT_PTX_SREG_CTAID_W
    4905             :   { 1487,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1487 = INT_PTX_SREG_CTAID_X
    4906             :   { 1488,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1488 = INT_PTX_SREG_CTAID_Y
    4907             :   { 1489,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1489 = INT_PTX_SREG_CTAID_Z
    4908             :   { 1490,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1490 = INT_PTX_SREG_GRIDID
    4909             :   { 1491,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1491 = INT_PTX_SREG_LANEID
    4910             :   { 1492,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1492 = INT_PTX_SREG_LANEMASK_EQ
    4911             :   { 1493,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1493 = INT_PTX_SREG_LANEMASK_GE
    4912             :   { 1494,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1494 = INT_PTX_SREG_LANEMASK_GT
    4913             :   { 1495,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1495 = INT_PTX_SREG_LANEMASK_LE
    4914             :   { 1496,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1496 = INT_PTX_SREG_LANEMASK_LT
    4915             :   { 1497,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1497 = INT_PTX_SREG_NCTAID_W
    4916             :   { 1498,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1498 = INT_PTX_SREG_NCTAID_X
    4917             :   { 1499,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1499 = INT_PTX_SREG_NCTAID_Y
    4918             :   { 1500,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1500 = INT_PTX_SREG_NCTAID_Z
    4919             :   { 1501,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1501 = INT_PTX_SREG_NSMID
    4920             :   { 1502,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1502 = INT_PTX_SREG_NTID_W
    4921             :   { 1503,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1503 = INT_PTX_SREG_NTID_X
    4922             :   { 1504,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1504 = INT_PTX_SREG_NTID_Y
    4923             :   { 1505,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1505 = INT_PTX_SREG_NTID_Z
    4924             :   { 1506,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1506 = INT_PTX_SREG_NWARPID
    4925             :   { 1507,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1507 = INT_PTX_SREG_PM0
    4926             :   { 1508,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1508 = INT_PTX_SREG_PM1
    4927             :   { 1509,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1509 = INT_PTX_SREG_PM2
    4928             :   { 1510,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1510 = INT_PTX_SREG_PM3
    4929             :   { 1511,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1511 = INT_PTX_SREG_SMID
    4930             :   { 1512,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1512 = INT_PTX_SREG_TID_W
    4931             :   { 1513,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1513 = INT_PTX_SREG_TID_X
    4932             :   { 1514,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1514 = INT_PTX_SREG_TID_Y
    4933             :   { 1515,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1515 = INT_PTX_SREG_TID_Z
    4934             :   { 1516,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1516 = INT_PTX_SREG_WARPID
    4935             :   { 1517,       1,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1517 = INT_PTX_SREG_WARPSIZE
    4936             :   { 1518,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo236, -1 ,nullptr },  // Inst #1518 = INT_SHFL_BFLY_F32imm1
    4937             :   { 1519,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo237, -1 ,nullptr },  // Inst #1519 = INT_SHFL_BFLY_F32imm2
    4938             :   { 1520,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr },  // Inst #1520 = INT_SHFL_BFLY_F32imm3
    4939             :   { 1521,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr },  // Inst #1521 = INT_SHFL_BFLY_F32reg
    4940             :   { 1522,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr },  // Inst #1522 = INT_SHFL_BFLY_I32imm1
    4941             :   { 1523,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1523 = INT_SHFL_BFLY_I32imm2
    4942             :   { 1524,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #1524 = INT_SHFL_BFLY_I32imm3
    4943             :   { 1525,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1525 = INT_SHFL_BFLY_I32reg
    4944             :   { 1526,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo236, -1 ,nullptr },  // Inst #1526 = INT_SHFL_DOWN_F32imm1
    4945             :   { 1527,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo237, -1 ,nullptr },  // Inst #1527 = INT_SHFL_DOWN_F32imm2
    4946             :   { 1528,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr },  // Inst #1528 = INT_SHFL_DOWN_F32imm3
    4947             :   { 1529,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr },  // Inst #1529 = INT_SHFL_DOWN_F32reg
    4948             :   { 1530,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr },  // Inst #1530 = INT_SHFL_DOWN_I32imm1
    4949             :   { 1531,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1531 = INT_SHFL_DOWN_I32imm2
    4950             :   { 1532,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #1532 = INT_SHFL_DOWN_I32imm3
    4951             :   { 1533,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1533 = INT_SHFL_DOWN_I32reg
    4952             :   { 1534,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo236, -1 ,nullptr },  // Inst #1534 = INT_SHFL_IDX_F32imm1
    4953             :   { 1535,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo237, -1 ,nullptr },  // Inst #1535 = INT_SHFL_IDX_F32imm2
    4954             :   { 1536,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr },  // Inst #1536 = INT_SHFL_IDX_F32imm3
    4955             :   { 1537,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr },  // Inst #1537 = INT_SHFL_IDX_F32reg
    4956             :   { 1538,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr },  // Inst #1538 = INT_SHFL_IDX_I32imm1
    4957             :   { 1539,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1539 = INT_SHFL_IDX_I32imm2
    4958             :   { 1540,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #1540 = INT_SHFL_IDX_I32imm3
    4959             :   { 1541,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1541 = INT_SHFL_IDX_I32reg
    4960             :   { 1542,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo236, -1 ,nullptr },  // Inst #1542 = INT_SHFL_UP_F32imm1
    4961             :   { 1543,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo237, -1 ,nullptr },  // Inst #1543 = INT_SHFL_UP_F32imm2
    4962             :   { 1544,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr },  // Inst #1544 = INT_SHFL_UP_F32imm3
    4963             :   { 1545,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr },  // Inst #1545 = INT_SHFL_UP_F32reg
    4964             :   { 1546,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr },  // Inst #1546 = INT_SHFL_UP_I32imm1
    4965             :   { 1547,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1547 = INT_SHFL_UP_I32imm2
    4966             :   { 1548,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #1548 = INT_SHFL_UP_I32imm3
    4967             :   { 1549,       4,      1,      0,      0,      0|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1549 = INT_SHFL_UP_I32reg
    4968             :   { 1550,       2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr },  // Inst #1550 = ISSPACEP_CONST_32
    4969             :   { 1551,       2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr },  // Inst #1551 = ISSPACEP_CONST_64
    4970             :   { 1552,       2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr },  // Inst #1552 = ISSPACEP_GLOBAL_32
    4971             :   { 1553,       2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr },  // Inst #1553 = ISSPACEP_GLOBAL_64
    4972             :   { 1554,       2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr },  // Inst #1554 = ISSPACEP_LOCAL_32
    4973             :   { 1555,       2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr },  // Inst #1555 = ISSPACEP_LOCAL_64
    4974             :   { 1556,       2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr },  // Inst #1556 = ISSPACEP_SHARED_32
    4975             :   { 1557,       2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr },  // Inst #1557 = ISSPACEP_SHARED_64
    4976             :   { 1558,       2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr },  // Inst #1558 = ISTYPEP_SAMPLER
    4977             :   { 1559,       2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr },  // Inst #1559 = ISTYPEP_SURFACE
    4978             :   { 1560,       2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr },  // Inst #1560 = ISTYPEP_TEXTURE
    4979             :   { 1561,       8,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr },  // Inst #1561 = LDV_f16_v2_areg
    4980             :   { 1562,       8,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr },  // Inst #1562 = LDV_f16_v2_areg_64
    4981             :   { 1563,       9,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr },  // Inst #1563 = LDV_f16_v2_ari
    4982             :   { 1564,       9,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr },  // Inst #1564 = LDV_f16_v2_ari_64
    4983             :   { 1565,       9,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo245, -1 ,nullptr },  // Inst #1565 = LDV_f16_v2_asi
    4984             :   { 1566,       8,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr },  // Inst #1566 = LDV_f16_v2_avar
    4985             :   { 1567,       10,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr },  // Inst #1567 = LDV_f16_v4_areg
    4986             :   { 1568,       10,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr },  // Inst #1568 = LDV_f16_v4_areg_64
    4987             :   { 1569,       11,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo249, -1 ,nullptr },  // Inst #1569 = LDV_f16_v4_ari
    4988             :   { 1570,       11,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr },  // Inst #1570 = LDV_f16_v4_ari_64
    4989             :   { 1571,       11,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo251, -1 ,nullptr },  // Inst #1571 = LDV_f16_v4_asi
    4990             :   { 1572,       10,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo252, -1 ,nullptr },  // Inst #1572 = LDV_f16_v4_avar
    4991             :   { 1573,       8,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr },  // Inst #1573 = LDV_f16x2_v2_areg
    4992             :   { 1574,       8,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo254, -1 ,nullptr },  // Inst #1574 = LDV_f16x2_v2_areg_64
    4993             :   { 1575,       9,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr },  // Inst #1575 = LDV_f16x2_v2_ari
    4994             :   { 1576,       9,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr },  // Inst #1576 = LDV_f16x2_v2_ari_64
    4995             :   { 1577,       9,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr },  // Inst #1577 = LDV_f16x2_v2_asi
    4996             :   { 1578,       8,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo258, -1 ,nullptr },  // Inst #1578 = LDV_f16x2_v2_avar
    4997             :   { 1579,       10,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr },  // Inst #1579 = LDV_f16x2_v4_areg
    4998             :   { 1580,       10,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr },  // Inst #1580 = LDV_f16x2_v4_areg_64
    4999             :   { 1581,       11,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr },  // Inst #1581 = LDV_f16x2_v4_ari
    5000             :   { 1582,       11,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo262, -1 ,nullptr },  // Inst #1582 = LDV_f16x2_v4_ari_64
    5001             :   { 1583,       11,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo263, -1 ,nullptr },  // Inst #1583 = LDV_f16x2_v4_asi
    5002             :   { 1584,       10,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo264, -1 ,nullptr },  // Inst #1584 = LDV_f16x2_v4_avar
    5003             :   { 1585,       8,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr },  // Inst #1585 = LDV_f32_v2_areg
    5004             :   { 1586,       8,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr },  // Inst #1586 = LDV_f32_v2_areg_64
    5005             :   { 1587,       9,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr },  // Inst #1587 = LDV_f32_v2_ari
    5006             :   { 1588,       9,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr },  // Inst #1588 = LDV_f32_v2_ari_64
    5007             :   { 1589,       9,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo269, -1 ,nullptr },  // Inst #1589 = LDV_f32_v2_asi
    5008             :   { 1590,       8,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr },  // Inst #1590 = LDV_f32_v2_avar
    5009             :   { 1591,       10,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr },  // Inst #1591 = LDV_f32_v4_areg
    5010             :   { 1592,       10,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo272, -1 ,nullptr },  // Inst #1592 = LDV_f32_v4_areg_64
    5011             :   { 1593,       11,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo273, -1 ,nullptr },  // Inst #1593 = LDV_f32_v4_ari
    5012             :   { 1594,       11,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr },  // Inst #1594 = LDV_f32_v4_ari_64
    5013             :   { 1595,       11,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr },  // Inst #1595 = LDV_f32_v4_asi
    5014             :   { 1596,       10,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr },  // Inst #1596 = LDV_f32_v4_avar
    5015             :   { 1597,       8,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo277, -1 ,nullptr },  // Inst #1597 = LDV_f64_v2_areg
    5016             :   { 1598,       8,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo278, -1 ,nullptr },  // Inst #1598 = LDV_f64_v2_areg_64
    5017             :   { 1599,       9,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo279, -1 ,nullptr },  // Inst #1599 = LDV_f64_v2_ari
    5018             :   { 1600,       9,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo280, -1 ,nullptr },  // Inst #1600 = LDV_f64_v2_ari_64
    5019             :   { 1601,       9,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo281, -1 ,nullptr },  // Inst #1601 = LDV_f64_v2_asi
    5020             :   { 1602,       8,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr },  // Inst #1602 = LDV_f64_v2_avar
    5021             :   { 1603,       10,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr },  // Inst #1603 = LDV_f64_v4_areg
    5022             :   { 1604,       10,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr },  // Inst #1604 = LDV_f64_v4_areg_64
    5023             :   { 1605,       11,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr },  // Inst #1605 = LDV_f64_v4_ari
    5024             :   { 1606,       11,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr },  // Inst #1606 = LDV_f64_v4_ari_64
    5025             :   { 1607,       11,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr },  // Inst #1607 = LDV_f64_v4_asi
    5026             :   { 1608,       10,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo288, -1 ,nullptr },  // Inst #1608 = LDV_f64_v4_avar
    5027             :   { 1609,       8,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo289, -1 ,nullptr },  // Inst #1609 = LDV_i16_v2_areg
    5028             :   { 1610,       8,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr },  // Inst #1610 = LDV_i16_v2_areg_64
    5029             :   { 1611,       9,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr },  // Inst #1611 = LDV_i16_v2_ari
    5030             :   { 1612,       9,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr },  // Inst #1612 = LDV_i16_v2_ari_64
    5031             :   { 1613,       9,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo293, -1 ,nullptr },  // Inst #1613 = LDV_i16_v2_asi
    5032             :   { 1614,       8,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr },  // Inst #1614 = LDV_i16_v2_avar
    5033             :   { 1615,       10,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr },  // Inst #1615 = LDV_i16_v4_areg
    5034             :   { 1616,       10,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr },  // Inst #1616 = LDV_i16_v4_areg_64
    5035             :   { 1617,       11,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr },  // Inst #1617 = LDV_i16_v4_ari
    5036             :   { 1618,       11,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo298, -1 ,nullptr },  // Inst #1618 = LDV_i16_v4_ari_64
    5037             :   { 1619,       11,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo299, -1 ,nullptr },  // Inst #1619 = LDV_i16_v4_asi
    5038             :   { 1620,       10,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo300, -1 ,nullptr },  // Inst #1620 = LDV_i16_v4_avar
    5039             :   { 1621,       8,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo301, -1 ,nullptr },  // Inst #1621 = LDV_i32_v2_areg
    5040             :   { 1622,       8,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo302, -1 ,nullptr },  // Inst #1622 = LDV_i32_v2_areg_64
    5041             :   { 1623,       9,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr },  // Inst #1623 = LDV_i32_v2_ari
    5042             :   { 1624,       9,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo304, -1 ,nullptr },  // Inst #1624 = LDV_i32_v2_ari_64
    5043             :   { 1625,       9,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo305, -1 ,nullptr },  // Inst #1625 = LDV_i32_v2_asi
    5044             :   { 1626,       8,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo306, -1 ,nullptr },  // Inst #1626 = LDV_i32_v2_avar
    5045             :   { 1627,       10,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo307, -1 ,nullptr },  // Inst #1627 = LDV_i32_v4_areg
    5046             :   { 1628,       10,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo308, -1 ,nullptr },  // Inst #1628 = LDV_i32_v4_areg_64
    5047             :   { 1629,       11,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo309, -1 ,nullptr },  // Inst #1629 = LDV_i32_v4_ari
    5048             :   { 1630,       11,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo310, -1 ,nullptr },  // Inst #1630 = LDV_i32_v4_ari_64
    5049             :   { 1631,       11,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo311, -1 ,nullptr },  // Inst #1631 = LDV_i32_v4_asi
    5050             :   { 1632,       10,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr },  // Inst #1632 = LDV_i32_v4_avar
    5051             :   { 1633,       8,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr },  // Inst #1633 = LDV_i64_v2_areg
    5052             :   { 1634,       8,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo314, -1 ,nullptr },  // Inst #1634 = LDV_i64_v2_areg_64
    5053             :   { 1635,       9,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr },  // Inst #1635 = LDV_i64_v2_ari
    5054             :   { 1636,       9,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo316, -1 ,nullptr },  // Inst #1636 = LDV_i64_v2_ari_64
    5055             :   { 1637,       9,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo317, -1 ,nullptr },  // Inst #1637 = LDV_i64_v2_asi
    5056             :   { 1638,       8,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo318, -1 ,nullptr },  // Inst #1638 = LDV_i64_v2_avar
    5057             :   { 1639,       10,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo319, -1 ,nullptr },  // Inst #1639 = LDV_i64_v4_areg
    5058             :   { 1640,       10,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo320, -1 ,nullptr },  // Inst #1640 = LDV_i64_v4_areg_64
    5059             :   { 1641,       11,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr },  // Inst #1641 = LDV_i64_v4_ari
    5060             :   { 1642,       11,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo322, -1 ,nullptr },  // Inst #1642 = LDV_i64_v4_ari_64
    5061             :   { 1643,       11,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo323, -1 ,nullptr },  // Inst #1643 = LDV_i64_v4_asi
    5062             :   { 1644,       10,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo324, -1 ,nullptr },  // Inst #1644 = LDV_i64_v4_avar
    5063             :   { 1645,       8,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo289, -1 ,nullptr },  // Inst #1645 = LDV_i8_v2_areg
    5064             :   { 1646,       8,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr },  // Inst #1646 = LDV_i8_v2_areg_64
    5065             :   { 1647,       9,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr },  // Inst #1647 = LDV_i8_v2_ari
    5066             :   { 1648,       9,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr },  // Inst #1648 = LDV_i8_v2_ari_64
    5067             :   { 1649,       9,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo293, -1 ,nullptr },  // Inst #1649 = LDV_i8_v2_asi
    5068             :   { 1650,       8,      2,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr },  // Inst #1650 = LDV_i8_v2_avar
    5069             :   { 1651,       10,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr },  // Inst #1651 = LDV_i8_v4_areg
    5070             :   { 1652,       10,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr },  // Inst #1652 = LDV_i8_v4_areg_64
    5071             :   { 1653,       11,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr },  // Inst #1653 = LDV_i8_v4_ari
    5072             :   { 1654,       11,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo298, -1 ,nullptr },  // Inst #1654 = LDV_i8_v4_ari_64
    5073             :   { 1655,       11,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo299, -1 ,nullptr },  // Inst #1655 = LDV_i8_v4_asi
    5074             :   { 1656,       10,     4,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo300, -1 ,nullptr },  // Inst #1656 = LDV_i8_v4_avar
    5075             :   { 1657,       7,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo325, -1 ,nullptr },  // Inst #1657 = LD_f16_areg
    5076             :   { 1658,       7,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo326, -1 ,nullptr },  // Inst #1658 = LD_f16_areg_64
    5077             :   { 1659,       8,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr },  // Inst #1659 = LD_f16_ari
    5078             :   { 1660,       8,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo328, -1 ,nullptr },  // Inst #1660 = LD_f16_ari_64
    5079             :   { 1661,       8,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr },  // Inst #1661 = LD_f16_asi
    5080             :   { 1662,       7,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr },  // Inst #1662 = LD_f16_avar
    5081             :   { 1663,       7,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr },  // Inst #1663 = LD_f16x2_areg
    5082             :   { 1664,       7,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr },  // Inst #1664 = LD_f16x2_areg_64
    5083             :   { 1665,       8,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo333, -1 ,nullptr },  // Inst #1665 = LD_f16x2_ari
    5084             :   { 1666,       8,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo334, -1 ,nullptr },  // Inst #1666 = LD_f16x2_ari_64
    5085             :   { 1667,       8,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo335, -1 ,nullptr },  // Inst #1667 = LD_f16x2_asi
    5086             :   { 1668,       7,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo336, -1 ,nullptr },  // Inst #1668 = LD_f16x2_avar
    5087             :   { 1669,       7,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr },  // Inst #1669 = LD_f32_areg
    5088             :   { 1670,       7,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr },  // Inst #1670 = LD_f32_areg_64
    5089             :   { 1671,       8,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo339, -1 ,nullptr },  // Inst #1671 = LD_f32_ari
    5090             :   { 1672,       8,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo340, -1 ,nullptr },  // Inst #1672 = LD_f32_ari_64
    5091             :   { 1673,       8,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr },  // Inst #1673 = LD_f32_asi
    5092             :   { 1674,       7,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr },  // Inst #1674 = LD_f32_avar
    5093             :   { 1675,       7,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr },  // Inst #1675 = LD_f64_areg
    5094             :   { 1676,       7,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr },  // Inst #1676 = LD_f64_areg_64
    5095             :   { 1677,       8,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo345, -1 ,nullptr },  // Inst #1677 = LD_f64_ari
    5096             :   { 1678,       8,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo346, -1 ,nullptr },  // Inst #1678 = LD_f64_ari_64
    5097             :   { 1679,       8,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo347, -1 ,nullptr },  // Inst #1679 = LD_f64_asi
    5098             :   { 1680,       7,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo348, -1 ,nullptr },  // Inst #1680 = LD_f64_avar
    5099             :   { 1681,       7,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo349, -1 ,nullptr },  // Inst #1681 = LD_i16_areg
    5100             :   { 1682,       7,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo350, -1 ,nullptr },  // Inst #1682 = LD_i16_areg_64
    5101             :   { 1683,       8,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo351, -1 ,nullptr },  // Inst #1683 = LD_i16_ari
    5102             :   { 1684,       8,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo352, -1 ,nullptr },  // Inst #1684 = LD_i16_ari_64
    5103             :   { 1685,       8,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo353, -1 ,nullptr },  // Inst #1685 = LD_i16_asi
    5104             :   { 1686,       7,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo354, -1 ,nullptr },  // Inst #1686 = LD_i16_avar
    5105             :   { 1687,       7,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo355, -1 ,nullptr },  // Inst #1687 = LD_i32_areg
    5106             :   { 1688,       7,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo356, -1 ,nullptr },  // Inst #1688 = LD_i32_areg_64
    5107             :   { 1689,       8,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo357, -1 ,nullptr },  // Inst #1689 = LD_i32_ari
    5108             :   { 1690,       8,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo358, -1 ,nullptr },  // Inst #1690 = LD_i32_ari_64
    5109             :   { 1691,       8,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr },  // Inst #1691 = LD_i32_asi
    5110             :   { 1692,       7,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo360, -1 ,nullptr },  // Inst #1692 = LD_i32_avar
    5111             :   { 1693,       7,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo361, -1 ,nullptr },  // Inst #1693 = LD_i64_areg
    5112             :   { 1694,       7,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo362, -1 ,nullptr },  // Inst #1694 = LD_i64_areg_64
    5113             :   { 1695,       8,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo363, -1 ,nullptr },  // Inst #1695 = LD_i64_ari
    5114             :   { 1696,       8,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo364, -1 ,nullptr },  // Inst #1696 = LD_i64_ari_64
    5115             :   { 1697,       8,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo365, -1 ,nullptr },  // Inst #1697 = LD_i64_asi
    5116             :   { 1698,       7,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo366, -1 ,nullptr },  // Inst #1698 = LD_i64_avar
    5117             :   { 1699,       7,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo349, -1 ,nullptr },  // Inst #1699 = LD_i8_areg
    5118             :   { 1700,       7,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo350, -1 ,nullptr },  // Inst #1700 = LD_i8_areg_64
    5119             :   { 1701,       8,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo351, -1 ,nullptr },  // Inst #1701 = LD_i8_ari
    5120             :   { 1702,       8,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo352, -1 ,nullptr },  // Inst #1702 = LD_i8_ari_64
    5121             :   { 1703,       8,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo353, -1 ,nullptr },  // Inst #1703 = LD_i8_asi
    5122             :   { 1704,       7,      1,      0,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo354, -1 ,nullptr },  // Inst #1704 = LD_i8_avar
    5123             :   { 1705,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr },  // Inst #1705 = LEA_ADDRi
    5124             :   { 1706,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr },  // Inst #1706 = LEA_ADDRi64
    5125             :   { 1707,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo367, -1 ,nullptr },  // Inst #1707 = LOAD_CONST_F16
    5126             :   { 1708,       1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #1708 = LastCallArgF32
    5127             :   { 1709,       1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #1709 = LastCallArgF64
    5128             :   { 1710,       1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr },  // Inst #1710 = LastCallArgI16
    5129             :   { 1711,       1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1711 = LastCallArgI32
    5130             :   { 1712,       1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #1712 = LastCallArgI32imm
    5131             :   { 1713,       1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr },  // Inst #1713 = LastCallArgI64
    5132             :   { 1714,       1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #1714 = LastCallArgParam
    5133             :   { 1715,       2,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo367, -1 ,nullptr },  // Inst #1715 = LoadParamMemF16
    5134             :   { 1716,       2,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #1716 = LoadParamMemF16x2
    5135             :   { 1717,       2,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #1717 = LoadParamMemF32
    5136             :   { 1718,       2,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #1718 = LoadParamMemF64
    5137             :   { 1719,       2,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr },  // Inst #1719 = LoadParamMemI16
    5138             :   { 1720,       2,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr },  // Inst #1720 = LoadParamMemI32
    5139             :   { 1721,       2,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #1721 = LoadParamMemI64
    5140             :   { 1722,       2,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr },  // Inst #1722 = LoadParamMemI8
    5141             :   { 1723,       3,      2,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo368, -1 ,nullptr },  // Inst #1723 = LoadParamMemV2F16
    5142             :   { 1724,       3,      2,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo369, -1 ,nullptr },  // Inst #1724 = LoadParamMemV2F16x2
    5143             :   { 1725,       3,      2,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #1725 = LoadParamMemV2F32
    5144             :   { 1726,       3,      2,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #1726 = LoadParamMemV2F64
    5145             :   { 1727,       3,      2,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #1727 = LoadParamMemV2I16
    5146             :   { 1728,       3,      2,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1728 = LoadParamMemV2I32
    5147             :   { 1729,       3,      2,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1729 = LoadParamMemV2I64
    5148             :   { 1730,       3,      2,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #1730 = LoadParamMemV2I8
    5149             :   { 1731,       5,      4,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo370, -1 ,nullptr },  // Inst #1731 = LoadParamMemV4F16
    5150             :   { 1732,       5,      4,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo371, -1 ,nullptr },  // Inst #1732 = LoadParamMemV4F16x2
    5151             :   { 1733,       5,      4,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo372, -1 ,nullptr },  // Inst #1733 = LoadParamMemV4F32
    5152             :   { 1734,       5,      4,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo373, -1 ,nullptr },  // Inst #1734 = LoadParamMemV4I16
    5153             :   { 1735,       5,      4,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo374, -1 ,nullptr },  // Inst #1735 = LoadParamMemV4I32
    5154             :   { 1736,       5,      4,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo373, -1 ,nullptr },  // Inst #1736 = LoadParamMemV4I8
    5155             :   { 1737,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo375, -1 ,nullptr },  // Inst #1737 = MAD16rii
    5156             :   { 1738,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo376, -1 ,nullptr },  // Inst #1738 = MAD16rir
    5157             :   { 1739,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo377, -1 ,nullptr },  // Inst #1739 = MAD16rri
    5158             :   { 1740,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo378, -1 ,nullptr },  // Inst #1740 = MAD16rrr
    5159             :   { 1741,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #1741 = MAD32rii
    5160             :   { 1742,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr },  // Inst #1742 = MAD32rir
    5161             :   { 1743,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1743 = MAD32rri
    5162             :   { 1744,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1744 = MAD32rrr
    5163             :   { 1745,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #1745 = MAD64rii
    5164             :   { 1746,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #1746 = MAD64rir
    5165             :   { 1747,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #1747 = MAD64rri
    5166             :   { 1748,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #1748 = MAD64rrr
    5167             :   { 1749,       2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr },  // Inst #1749 = MOV_ADDR
    5168             :   { 1750,       2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr },  // Inst #1750 = MOV_ADDR64
    5169             :   { 1751,       2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr },  // Inst #1751 = MOV_DEPOT_ADDR
    5170             :   { 1752,       2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #1752 = MOV_DEPOT_ADDR_64
    5171             :   { 1753,       2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo379, -1 ,nullptr },  // Inst #1753 = MOV_SPECIAL
    5172             :   { 1754,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #1754 = MULTHSi16ri
    5173             :   { 1755,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #1755 = MULTHSi16rr
    5174             :   { 1756,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1756 = MULTHSi32ri
    5175             :   { 1757,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1757 = MULTHSi32rr
    5176             :   { 1758,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1758 = MULTHSi64ri
    5177             :   { 1759,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1759 = MULTHSi64rr
    5178             :   { 1760,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #1760 = MULTHUi16ri
    5179             :   { 1761,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #1761 = MULTHUi16rr
    5180             :   { 1762,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1762 = MULTHUi32ri
    5181             :   { 1763,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1763 = MULTHUi32rr
    5182             :   { 1764,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1764 = MULTHUi64ri
    5183             :   { 1765,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1765 = MULTHUi64rr
    5184             :   { 1766,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #1766 = MULTi16ri
    5185             :   { 1767,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #1767 = MULTi16rr
    5186             :   { 1768,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1768 = MULTi32ri
    5187             :   { 1769,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1769 = MULTi32rr
    5188             :   { 1770,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1770 = MULTi64ri
    5189             :   { 1771,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1771 = MULTi64rr
    5190             :   { 1772,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo380, -1 ,nullptr },  // Inst #1772 = MULWIDES32
    5191             :   { 1773,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo381, -1 ,nullptr },  // Inst #1773 = MULWIDES32Imm
    5192             :   { 1774,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo381, -1 ,nullptr },  // Inst #1774 = MULWIDES32Imm32
    5193             :   { 1775,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo382, -1 ,nullptr },  // Inst #1775 = MULWIDES64
    5194             :   { 1776,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #1776 = MULWIDES64Imm
    5195             :   { 1777,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #1777 = MULWIDES64Imm64
    5196             :   { 1778,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo380, -1 ,nullptr },  // Inst #1778 = MULWIDEU32
    5197             :   { 1779,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo381, -1 ,nullptr },  // Inst #1779 = MULWIDEU32Imm
    5198             :   { 1780,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo381, -1 ,nullptr },  // Inst #1780 = MULWIDEU32Imm32
    5199             :   { 1781,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo382, -1 ,nullptr },  // Inst #1781 = MULWIDEU64
    5200             :   { 1782,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #1782 = MULWIDEU64Imm
    5201             :   { 1783,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #1783 = MULWIDEU64Imm64
    5202             :   { 1784,       2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #1784 = MoveParamF16
    5203             :   { 1785,       2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #1785 = MoveParamF32
    5204             :   { 1786,       2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #1786 = MoveParamF64
    5205             :   { 1787,       2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #1787 = MoveParamI16
    5206             :   { 1788,       2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #1788 = MoveParamI32
    5207             :   { 1789,       2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #1789 = MoveParamI64
    5208             :   { 1790,       0,      0,      0,      0,      0, 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1790 = NOP
    5209             :   { 1791,       2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #1791 = NOT1
    5210             :   { 1792,       2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #1792 = NOT16
    5211             :   { 1793,       2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #1793 = NOT32
    5212             :   { 1794,       2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #1794 = NOT64
    5213             :   { 1795,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #1795 = ORb16ri
    5214             :   { 1796,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #1796 = ORb16rr
    5215             :   { 1797,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1797 = ORb1ri
    5216             :   { 1798,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #1798 = ORb1rr
    5217             :   { 1799,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1799 = ORb32ri
    5218             :   { 1800,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1800 = ORb32rr
    5219             :   { 1801,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1801 = ORb64ri
    5220             :   { 1802,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1802 = ORb64rr
    5221             :   { 1803,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo382, -1 ,nullptr },  // Inst #1803 = PACK_TWO_INT32
    5222             :   { 1804,       2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #1804 = POPCr32
    5223             :   { 1805,       2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #1805 = POPCr64
    5224             :   { 1806,       1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #1806 = PrototypeInst
    5225             :   { 1807,       1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #1807 = PseudoUseParamF32
    5226             :   { 1808,       1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #1808 = PseudoUseParamF64
    5227             :   { 1809,       1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr },  // Inst #1809 = PseudoUseParamI16
    5228             :   { 1810,       1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1810 = PseudoUseParamI32
    5229             :   { 1811,       1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr },  // Inst #1811 = PseudoUseParamI64
    5230             :   { 1812,       0,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1812 = RETURNInst
    5231             :   { 1813,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #1813 = ROT32imm_sw
    5232             :   { 1814,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #1814 = ROT64imm_sw
    5233             :   { 1815,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1815 = ROTATE_B32_HW_IMM
    5234             :   { 1816,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1816 = ROTATE_B32_HW_REG
    5235             :   { 1817,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1817 = ROTL32imm_hw
    5236             :   { 1818,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1818 = ROTL32reg_hw
    5237             :   { 1819,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1819 = ROTL32reg_sw
    5238             :   { 1820,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr },  // Inst #1820 = ROTL64reg_sw
    5239             :   { 1821,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1821 = ROTR32imm_hw
    5240             :   { 1822,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1822 = ROTR32reg_hw
    5241             :   { 1823,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1823 = ROTR32reg_sw
    5242             :   { 1824,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr },  // Inst #1824 = ROTR64reg_sw
    5243             :   { 1825,       0,      0,      0,      0,      0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1825 = Return
    5244             :   { 1826,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #1826 = SDIVi16ri
    5245             :   { 1827,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #1827 = SDIVi16rr
    5246             :   { 1828,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1828 = SDIVi32ri
    5247             :   { 1829,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1829 = SDIVi32rr
    5248             :   { 1830,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1830 = SDIVi64ri
    5249             :   { 1831,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1831 = SDIVi64rr
    5250             :   { 1832,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo383, -1 ,nullptr },  // Inst #1832 = SELP_b16ii
    5251             :   { 1833,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo384, -1 ,nullptr },  // Inst #1833 = SELP_b16ir
    5252             :   { 1834,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo385, -1 ,nullptr },  // Inst #1834 = SELP_b16ri
    5253             :   { 1835,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo386, -1 ,nullptr },  // Inst #1835 = SELP_b16rr
    5254             :   { 1836,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo387, -1 ,nullptr },  // Inst #1836 = SELP_b32ii
    5255             :   { 1837,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo388, -1 ,nullptr },  // Inst #1837 = SELP_b32ir
    5256             :   { 1838,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo389, -1 ,nullptr },  // Inst #1838 = SELP_b32ri
    5257             :   { 1839,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo390, -1 ,nullptr },  // Inst #1839 = SELP_b32rr
    5258             :   { 1840,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo391, -1 ,nullptr },  // Inst #1840 = SELP_b64ii
    5259             :   { 1841,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo392, -1 ,nullptr },  // Inst #1841 = SELP_b64ir
    5260             :   { 1842,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo393, -1 ,nullptr },  // Inst #1842 = SELP_b64ri
    5261             :   { 1843,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo394, -1 ,nullptr },  // Inst #1843 = SELP_b64rr
    5262             :   { 1844,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo395, -1 ,nullptr },  // Inst #1844 = SELP_f16ii
    5263             :   { 1845,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo396, -1 ,nullptr },  // Inst #1845 = SELP_f16ir
    5264             :   { 1846,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo397, -1 ,nullptr },  // Inst #1846 = SELP_f16ri
    5265             :   { 1847,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo398, -1 ,nullptr },  // Inst #1847 = SELP_f16rr
    5266             :   { 1848,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo399, -1 ,nullptr },  // Inst #1848 = SELP_f16x2rr
    5267             :   { 1849,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo400, -1 ,nullptr },  // Inst #1849 = SELP_f32ii
    5268             :   { 1850,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo401, -1 ,nullptr },  // Inst #1850 = SELP_f32ir
    5269             :   { 1851,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo402, -1 ,nullptr },  // Inst #1851 = SELP_f32ri
    5270             :   { 1852,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo403, -1 ,nullptr },  // Inst #1852 = SELP_f32rr
    5271             :   { 1853,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo404, -1 ,nullptr },  // Inst #1853 = SELP_f64ii
    5272             :   { 1854,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo405, -1 ,nullptr },  // Inst #1854 = SELP_f64ir
    5273             :   { 1855,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo406, -1 ,nullptr },  // Inst #1855 = SELP_f64ri
    5274             :   { 1856,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo407, -1 ,nullptr },  // Inst #1856 = SELP_f64rr
    5275             :   { 1857,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo383, -1 ,nullptr },  // Inst #1857 = SELP_s16ii
    5276             :   { 1858,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo384, -1 ,nullptr },  // Inst #1858 = SELP_s16ir
    5277             :   { 1859,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo385, -1 ,nullptr },  // Inst #1859 = SELP_s16ri
    5278             :   { 1860,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo386, -1 ,nullptr },  // Inst #1860 = SELP_s16rr
    5279             :   { 1861,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo387, -1 ,nullptr },  // Inst #1861 = SELP_s32ii
    5280             :   { 1862,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo388, -1 ,nullptr },  // Inst #1862 = SELP_s32ir
    5281             :   { 1863,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo389, -1 ,nullptr },  // Inst #1863 = SELP_s32ri
    5282             :   { 1864,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo390, -1 ,nullptr },  // Inst #1864 = SELP_s32rr
    5283             :   { 1865,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo391, -1 ,nullptr },  // Inst #1865 = SELP_s64ii
    5284             :   { 1866,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo392, -1 ,nullptr },  // Inst #1866 = SELP_s64ir
    5285             :   { 1867,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo393, -1 ,nullptr },  // Inst #1867 = SELP_s64ri
    5286             :   { 1868,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo394, -1 ,nullptr },  // Inst #1868 = SELP_s64rr
    5287             :   { 1869,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo383, -1 ,nullptr },  // Inst #1869 = SELP_u16ii
    5288             :   { 1870,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo384, -1 ,nullptr },  // Inst #1870 = SELP_u16ir
    5289             :   { 1871,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo385, -1 ,nullptr },  // Inst #1871 = SELP_u16ri
    5290             :   { 1872,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo386, -1 ,nullptr },  // Inst #1872 = SELP_u16rr
    5291             :   { 1873,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo387, -1 ,nullptr },  // Inst #1873 = SELP_u32ii
    5292             :   { 1874,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo388, -1 ,nullptr },  // Inst #1874 = SELP_u32ir
    5293             :   { 1875,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo389, -1 ,nullptr },  // Inst #1875 = SELP_u32ri
    5294             :   { 1876,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo390, -1 ,nullptr },  // Inst #1876 = SELP_u32rr
    5295             :   { 1877,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo391, -1 ,nullptr },  // Inst #1877 = SELP_u64ii
    5296             :   { 1878,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo392, -1 ,nullptr },  // Inst #1878 = SELP_u64ir
    5297             :   { 1879,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo393, -1 ,nullptr },  // Inst #1879 = SELP_u64ri
    5298             :   { 1880,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo394, -1 ,nullptr },  // Inst #1880 = SELP_u64rr
    5299             :   { 1881,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo408, -1 ,nullptr },  // Inst #1881 = SETP_b16ir
    5300             :   { 1882,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo409, -1 ,nullptr },  // Inst #1882 = SETP_b16ri
    5301             :   { 1883,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo410, -1 ,nullptr },  // Inst #1883 = SETP_b16rr
    5302             :   { 1884,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo411, -1 ,nullptr },  // Inst #1884 = SETP_b32ir
    5303             :   { 1885,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo412, -1 ,nullptr },  // Inst #1885 = SETP_b32ri
    5304             :   { 1886,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo413, -1 ,nullptr },  // Inst #1886 = SETP_b32rr
    5305             :   { 1887,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo414, -1 ,nullptr },  // Inst #1887 = SETP_b64ir
    5306             :   { 1888,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo415, -1 ,nullptr },  // Inst #1888 = SETP_b64ri
    5307             :   { 1889,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo416, -1 ,nullptr },  // Inst #1889 = SETP_b64rr
    5308             :   { 1890,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo417, -1 ,nullptr },  // Inst #1890 = SETP_f16rr
    5309             :   { 1891,       5,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo418, -1 ,nullptr },  // Inst #1891 = SETP_f16x2rr
    5310             :   { 1892,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo419, -1 ,nullptr },  // Inst #1892 = SETP_f32ir
    5311             :   { 1893,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo420, -1 ,nullptr },  // Inst #1893 = SETP_f32ri
    5312             :   { 1894,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo421, -1 ,nullptr },  // Inst #1894 = SETP_f32rr
    5313             :   { 1895,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo422, -1 ,nullptr },  // Inst #1895 = SETP_f64ir
    5314             :   { 1896,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo423, -1 ,nullptr },  // Inst #1896 = SETP_f64ri
    5315             :   { 1897,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo424, -1 ,nullptr },  // Inst #1897 = SETP_f64rr
    5316             :   { 1898,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo408, -1 ,nullptr },  // Inst #1898 = SETP_s16ir
    5317             :   { 1899,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo409, -1 ,nullptr },  // Inst #1899 = SETP_s16ri
    5318             :   { 1900,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo410, -1 ,nullptr },  // Inst #1900 = SETP_s16rr
    5319             :   { 1901,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo411, -1 ,nullptr },  // Inst #1901 = SETP_s32ir
    5320             :   { 1902,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo412, -1 ,nullptr },  // Inst #1902 = SETP_s32ri
    5321             :   { 1903,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo413, -1 ,nullptr },  // Inst #1903 = SETP_s32rr
    5322             :   { 1904,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo414, -1 ,nullptr },  // Inst #1904 = SETP_s64ir
    5323             :   { 1905,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo415, -1 ,nullptr },  // Inst #1905 = SETP_s64ri
    5324             :   { 1906,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo416, -1 ,nullptr },  // Inst #1906 = SETP_s64rr
    5325             :   { 1907,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo408, -1 ,nullptr },  // Inst #1907 = SETP_u16ir
    5326             :   { 1908,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo409, -1 ,nullptr },  // Inst #1908 = SETP_u16ri
    5327             :   { 1909,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo410, -1 ,nullptr },  // Inst #1909 = SETP_u16rr
    5328             :   { 1910,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo411, -1 ,nullptr },  // Inst #1910 = SETP_u32ir
    5329             :   { 1911,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo412, -1 ,nullptr },  // Inst #1911 = SETP_u32ri
    5330             :   { 1912,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo413, -1 ,nullptr },  // Inst #1912 = SETP_u32rr
    5331             :   { 1913,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo414, -1 ,nullptr },  // Inst #1913 = SETP_u64ir
    5332             :   { 1914,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo415, -1 ,nullptr },  // Inst #1914 = SETP_u64ri
    5333             :   { 1915,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo416, -1 ,nullptr },  // Inst #1915 = SETP_u64rr
    5334             :   { 1916,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo425, -1 ,nullptr },  // Inst #1916 = SET_b16ir
    5335             :   { 1917,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo426, -1 ,nullptr },  // Inst #1917 = SET_b16ri
    5336             :   { 1918,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo427, -1 ,nullptr },  // Inst #1918 = SET_b16rr
    5337             :   { 1919,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo428, -1 ,nullptr },  // Inst #1919 = SET_b32ir
    5338             :   { 1920,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo429, -1 ,nullptr },  // Inst #1920 = SET_b32ri
    5339             :   { 1921,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo430, -1 ,nullptr },  // Inst #1921 = SET_b32rr
    5340             :   { 1922,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo431, -1 ,nullptr },  // Inst #1922 = SET_b64ir
    5341             :   { 1923,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo432, -1 ,nullptr },  // Inst #1923 = SET_b64ri
    5342             :   { 1924,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo433, -1 ,nullptr },  // Inst #1924 = SET_b64rr
    5343             :   { 1925,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo434, -1 ,nullptr },  // Inst #1925 = SET_f16ir
    5344             :   { 1926,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo435, -1 ,nullptr },  // Inst #1926 = SET_f16ri
    5345             :   { 1927,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo436, -1 ,nullptr },  // Inst #1927 = SET_f16rr
    5346             :   { 1928,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo437, -1 ,nullptr },  // Inst #1928 = SET_f32ir
    5347             :   { 1929,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo438, -1 ,nullptr },  // Inst #1929 = SET_f32ri
    5348             :   { 1930,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo439, -1 ,nullptr },  // Inst #1930 = SET_f32rr
    5349             :   { 1931,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo440, -1 ,nullptr },  // Inst #1931 = SET_f64ir
    5350             :   { 1932,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo441, -1 ,nullptr },  // Inst #1932 = SET_f64ri
    5351             :   { 1933,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo442, -1 ,nullptr },  // Inst #1933 = SET_f64rr
    5352             :   { 1934,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo425, -1 ,nullptr },  // Inst #1934 = SET_s16ir
    5353             :   { 1935,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo426, -1 ,nullptr },  // Inst #1935 = SET_s16ri
    5354             :   { 1936,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo427, -1 ,nullptr },  // Inst #1936 = SET_s16rr
    5355             :   { 1937,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo428, -1 ,nullptr },  // Inst #1937 = SET_s32ir
    5356             :   { 1938,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo429, -1 ,nullptr },  // Inst #1938 = SET_s32ri
    5357             :   { 1939,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo430, -1 ,nullptr },  // Inst #1939 = SET_s32rr
    5358             :   { 1940,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo431, -1 ,nullptr },  // Inst #1940 = SET_s64ir
    5359             :   { 1941,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo432, -1 ,nullptr },  // Inst #1941 = SET_s64ri
    5360             :   { 1942,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo433, -1 ,nullptr },  // Inst #1942 = SET_s64rr
    5361             :   { 1943,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo425, -1 ,nullptr },  // Inst #1943 = SET_u16ir
    5362             :   { 1944,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo426, -1 ,nullptr },  // Inst #1944 = SET_u16ri
    5363             :   { 1945,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo427, -1 ,nullptr },  // Inst #1945 = SET_u16rr
    5364             :   { 1946,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo428, -1 ,nullptr },  // Inst #1946 = SET_u32ir
    5365             :   { 1947,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo429, -1 ,nullptr },  // Inst #1947 = SET_u32ri
    5366             :   { 1948,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo430, -1 ,nullptr },  // Inst #1948 = SET_u32rr
    5367             :   { 1949,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo431, -1 ,nullptr },  // Inst #1949 = SET_u64ir
    5368             :   { 1950,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo432, -1 ,nullptr },  // Inst #1950 = SET_u64ri
    5369             :   { 1951,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo433, -1 ,nullptr },  // Inst #1951 = SET_u64rr
    5370             :   { 1952,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1952 = SHF_L_WRAP_B32_IMM
    5371             :   { 1953,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1953 = SHF_L_WRAP_B32_REG
    5372             :   { 1954,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1954 = SHF_R_WRAP_B32_IMM
    5373             :   { 1955,       4,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1955 = SHF_R_WRAP_B32_REG
    5374             :   { 1956,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #1956 = SHLi16ri
    5375             :   { 1957,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr },  // Inst #1957 = SHLi16rr
    5376             :   { 1958,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo443, -1 ,nullptr },  // Inst #1958 = SHLi32ii
    5377             :   { 1959,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1959 = SHLi32ri
    5378             :   { 1960,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1960 = SHLi32rr
    5379             :   { 1961,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1961 = SHLi64ri
    5380             :   { 1962,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr },  // Inst #1962 = SHLi64rr
    5381             :   { 1963,       2,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #1963 = SINF
    5382             :   { 1964,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #1964 = SMAXi16ri
    5383             :   { 1965,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #1965 = SMAXi16rr
    5384             :   { 1966,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1966 = SMAXi32ri
    5385             :   { 1967,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1967 = SMAXi32rr
    5386             :   { 1968,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1968 = SMAXi64ri
    5387             :   { 1969,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1969 = SMAXi64rr
    5388             :   { 1970,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #1970 = SMINi16ri
    5389             :   { 1971,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #1971 = SMINi16rr
    5390             :   { 1972,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1972 = SMINi32ri
    5391             :   { 1973,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1973 = SMINi32rr
    5392             :   { 1974,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1974 = SMINi64ri
    5393             :   { 1975,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1975 = SMINi64rr
    5394             :   { 1976,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #1976 = SRAi16ri
    5395             :   { 1977,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr },  // Inst #1977 = SRAi16rr
    5396             :   { 1978,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo443, -1 ,nullptr },  // Inst #1978 = SRAi32ii
    5397             :   { 1979,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1979 = SRAi32ri
    5398             :   { 1980,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1980 = SRAi32rr
    5399             :   { 1981,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1981 = SRAi64ri
    5400             :   { 1982,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr },  // Inst #1982 = SRAi64rr
    5401             :   { 1983,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #1983 = SREMi16ri
    5402             :   { 1984,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #1984 = SREMi16rr
    5403             :   { 1985,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1985 = SREMi32ri
    5404             :   { 1986,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1986 = SREMi32rr
    5405             :   { 1987,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1987 = SREMi64ri
    5406             :   { 1988,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1988 = SREMi64rr
    5407             :   { 1989,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #1989 = SRLi16ri
    5408             :   { 1990,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr },  // Inst #1990 = SRLi16rr
    5409             :   { 1991,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo443, -1 ,nullptr },  // Inst #1991 = SRLi32ii
    5410             :   { 1992,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1992 = SRLi32ri
    5411             :   { 1993,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1993 = SRLi32rr
    5412             :   { 1994,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1994 = SRLi64ri
    5413             :   { 1995,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr },  // Inst #1995 = SRLi64rr
    5414             :   { 1996,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr },  // Inst #1996 = STV_f16_v2_areg
    5415             :   { 1997,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr },  // Inst #1997 = STV_f16_v2_areg_64
    5416             :   { 1998,       9,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr },  // Inst #1998 = STV_f16_v2_ari
    5417             :   { 1999,       9,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr },  // Inst #1999 = STV_f16_v2_ari_64
    5418             :   { 2000,       9,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo245, -1 ,nullptr },  // Inst #2000 = STV_f16_v2_asi
    5419             :   { 2001,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr },  // Inst #2001 = STV_f16_v2_avar
    5420             :   { 2002,       10,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr },  // Inst #2002 = STV_f16_v4_areg
    5421             :   { 2003,       10,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr },  // Inst #2003 = STV_f16_v4_areg_64
    5422             :   { 2004,       11,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo249, -1 ,nullptr },  // Inst #2004 = STV_f16_v4_ari
    5423             :   { 2005,       11,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr },  // Inst #2005 = STV_f16_v4_ari_64
    5424             :   { 2006,       11,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo251, -1 ,nullptr },  // Inst #2006 = STV_f16_v4_asi
    5425             :   { 2007,       10,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo252, -1 ,nullptr },  // Inst #2007 = STV_f16_v4_avar
    5426             :   { 2008,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr },  // Inst #2008 = STV_f16x2_v2_areg
    5427             :   { 2009,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo254, -1 ,nullptr },  // Inst #2009 = STV_f16x2_v2_areg_64
    5428             :   { 2010,       9,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr },  // Inst #2010 = STV_f16x2_v2_ari
    5429             :   { 2011,       9,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr },  // Inst #2011 = STV_f16x2_v2_ari_64
    5430             :   { 2012,       9,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr },  // Inst #2012 = STV_f16x2_v2_asi
    5431             :   { 2013,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo258, -1 ,nullptr },  // Inst #2013 = STV_f16x2_v2_avar
    5432             :   { 2014,       10,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr },  // Inst #2014 = STV_f16x2_v4_areg
    5433             :   { 2015,       10,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr },  // Inst #2015 = STV_f16x2_v4_areg_64
    5434             :   { 2016,       11,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr },  // Inst #2016 = STV_f16x2_v4_ari
    5435             :   { 2017,       11,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo262, -1 ,nullptr },  // Inst #2017 = STV_f16x2_v4_ari_64
    5436             :   { 2018,       11,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo263, -1 ,nullptr },  // Inst #2018 = STV_f16x2_v4_asi
    5437             :   { 2019,       10,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo264, -1 ,nullptr },  // Inst #2019 = STV_f16x2_v4_avar
    5438             :   { 2020,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr },  // Inst #2020 = STV_f32_v2_areg
    5439             :   { 2021,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr },  // Inst #2021 = STV_f32_v2_areg_64
    5440             :   { 2022,       9,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr },  // Inst #2022 = STV_f32_v2_ari
    5441             :   { 2023,       9,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr },  // Inst #2023 = STV_f32_v2_ari_64
    5442             :   { 2024,       9,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo269, -1 ,nullptr },  // Inst #2024 = STV_f32_v2_asi
    5443             :   { 2025,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr },  // Inst #2025 = STV_f32_v2_avar
    5444             :   { 2026,       10,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr },  // Inst #2026 = STV_f32_v4_areg
    5445             :   { 2027,       10,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo272, -1 ,nullptr },  // Inst #2027 = STV_f32_v4_areg_64
    5446             :   { 2028,       11,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo273, -1 ,nullptr },  // Inst #2028 = STV_f32_v4_ari
    5447             :   { 2029,       11,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr },  // Inst #2029 = STV_f32_v4_ari_64
    5448             :   { 2030,       11,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr },  // Inst #2030 = STV_f32_v4_asi
    5449             :   { 2031,       10,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr },  // Inst #2031 = STV_f32_v4_avar
    5450             :   { 2032,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo277, -1 ,nullptr },  // Inst #2032 = STV_f64_v2_areg
    5451             :   { 2033,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo278, -1 ,nullptr },  // Inst #2033 = STV_f64_v2_areg_64
    5452             :   { 2034,       9,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo279, -1 ,nullptr },  // Inst #2034 = STV_f64_v2_ari
    5453             :   { 2035,       9,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo280, -1 ,nullptr },  // Inst #2035 = STV_f64_v2_ari_64
    5454             :   { 2036,       9,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo281, -1 ,nullptr },  // Inst #2036 = STV_f64_v2_asi
    5455             :   { 2037,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr },  // Inst #2037 = STV_f64_v2_avar
    5456             :   { 2038,       10,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr },  // Inst #2038 = STV_f64_v4_areg
    5457             :   { 2039,       10,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr },  // Inst #2039 = STV_f64_v4_areg_64
    5458             :   { 2040,       11,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr },  // Inst #2040 = STV_f64_v4_ari
    5459             :   { 2041,       11,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr },  // Inst #2041 = STV_f64_v4_ari_64
    5460             :   { 2042,       11,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr },  // Inst #2042 = STV_f64_v4_asi
    5461             :   { 2043,       10,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo288, -1 ,nullptr },  // Inst #2043 = STV_f64_v4_avar
    5462             :   { 2044,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo289, -1 ,nullptr },  // Inst #2044 = STV_i16_v2_areg
    5463             :   { 2045,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr },  // Inst #2045 = STV_i16_v2_areg_64
    5464             :   { 2046,       9,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr },  // Inst #2046 = STV_i16_v2_ari
    5465             :   { 2047,       9,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr },  // Inst #2047 = STV_i16_v2_ari_64
    5466             :   { 2048,       9,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo293, -1 ,nullptr },  // Inst #2048 = STV_i16_v2_asi
    5467             :   { 2049,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr },  // Inst #2049 = STV_i16_v2_avar
    5468             :   { 2050,       10,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr },  // Inst #2050 = STV_i16_v4_areg
    5469             :   { 2051,       10,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr },  // Inst #2051 = STV_i16_v4_areg_64
    5470             :   { 2052,       11,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr },  // Inst #2052 = STV_i16_v4_ari
    5471             :   { 2053,       11,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo298, -1 ,nullptr },  // Inst #2053 = STV_i16_v4_ari_64
    5472             :   { 2054,       11,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo299, -1 ,nullptr },  // Inst #2054 = STV_i16_v4_asi
    5473             :   { 2055,       10,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo300, -1 ,nullptr },  // Inst #2055 = STV_i16_v4_avar
    5474             :   { 2056,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo301, -1 ,nullptr },  // Inst #2056 = STV_i32_v2_areg
    5475             :   { 2057,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo302, -1 ,nullptr },  // Inst #2057 = STV_i32_v2_areg_64
    5476             :   { 2058,       9,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr },  // Inst #2058 = STV_i32_v2_ari
    5477             :   { 2059,       9,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo304, -1 ,nullptr },  // Inst #2059 = STV_i32_v2_ari_64
    5478             :   { 2060,       9,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo305, -1 ,nullptr },  // Inst #2060 = STV_i32_v2_asi
    5479             :   { 2061,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo306, -1 ,nullptr },  // Inst #2061 = STV_i32_v2_avar
    5480             :   { 2062,       10,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo307, -1 ,nullptr },  // Inst #2062 = STV_i32_v4_areg
    5481             :   { 2063,       10,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo308, -1 ,nullptr },  // Inst #2063 = STV_i32_v4_areg_64
    5482             :   { 2064,       11,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo309, -1 ,nullptr },  // Inst #2064 = STV_i32_v4_ari
    5483             :   { 2065,       11,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo310, -1 ,nullptr },  // Inst #2065 = STV_i32_v4_ari_64
    5484             :   { 2066,       11,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo311, -1 ,nullptr },  // Inst #2066 = STV_i32_v4_asi
    5485             :   { 2067,       10,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr },  // Inst #2067 = STV_i32_v4_avar
    5486             :   { 2068,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr },  // Inst #2068 = STV_i64_v2_areg
    5487             :   { 2069,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo314, -1 ,nullptr },  // Inst #2069 = STV_i64_v2_areg_64
    5488             :   { 2070,       9,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr },  // Inst #2070 = STV_i64_v2_ari
    5489             :   { 2071,       9,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo316, -1 ,nullptr },  // Inst #2071 = STV_i64_v2_ari_64
    5490             :   { 2072,       9,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo317, -1 ,nullptr },  // Inst #2072 = STV_i64_v2_asi
    5491             :   { 2073,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo318, -1 ,nullptr },  // Inst #2073 = STV_i64_v2_avar
    5492             :   { 2074,       10,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo319, -1 ,nullptr },  // Inst #2074 = STV_i64_v4_areg
    5493             :   { 2075,       10,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo320, -1 ,nullptr },  // Inst #2075 = STV_i64_v4_areg_64
    5494             :   { 2076,       11,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr },  // Inst #2076 = STV_i64_v4_ari
    5495             :   { 2077,       11,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo322, -1 ,nullptr },  // Inst #2077 = STV_i64_v4_ari_64
    5496             :   { 2078,       11,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo323, -1 ,nullptr },  // Inst #2078 = STV_i64_v4_asi
    5497             :   { 2079,       10,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo324, -1 ,nullptr },  // Inst #2079 = STV_i64_v4_avar
    5498             :   { 2080,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo289, -1 ,nullptr },  // Inst #2080 = STV_i8_v2_areg
    5499             :   { 2081,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr },  // Inst #2081 = STV_i8_v2_areg_64
    5500             :   { 2082,       9,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr },  // Inst #2082 = STV_i8_v2_ari
    5501             :   { 2083,       9,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr },  // Inst #2083 = STV_i8_v2_ari_64
    5502             :   { 2084,       9,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo293, -1 ,nullptr },  // Inst #2084 = STV_i8_v2_asi
    5503             :   { 2085,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr },  // Inst #2085 = STV_i8_v2_avar
    5504             :   { 2086,       10,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr },  // Inst #2086 = STV_i8_v4_areg
    5505             :   { 2087,       10,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr },  // Inst #2087 = STV_i8_v4_areg_64
    5506             :   { 2088,       11,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr },  // Inst #2088 = STV_i8_v4_ari
    5507             :   { 2089,       11,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo298, -1 ,nullptr },  // Inst #2089 = STV_i8_v4_ari_64
    5508             :   { 2090,       11,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo299, -1 ,nullptr },  // Inst #2090 = STV_i8_v4_asi
    5509             :   { 2091,       10,     0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo300, -1 ,nullptr },  // Inst #2091 = STV_i8_v4_avar
    5510             :   { 2092,       7,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo325, -1 ,nullptr },  // Inst #2092 = ST_f16_areg
    5511             :   { 2093,       7,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo326, -1 ,nullptr },  // Inst #2093 = ST_f16_areg_64
    5512             :   { 2094,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr },  // Inst #2094 = ST_f16_ari
    5513             :   { 2095,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo328, -1 ,nullptr },  // Inst #2095 = ST_f16_ari_64
    5514             :   { 2096,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr },  // Inst #2096 = ST_f16_asi
    5515             :   { 2097,       7,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr },  // Inst #2097 = ST_f16_avar
    5516             :   { 2098,       7,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr },  // Inst #2098 = ST_f16x2_areg
    5517             :   { 2099,       7,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr },  // Inst #2099 = ST_f16x2_areg_64
    5518             :   { 2100,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo333, -1 ,nullptr },  // Inst #2100 = ST_f16x2_ari
    5519             :   { 2101,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo334, -1 ,nullptr },  // Inst #2101 = ST_f16x2_ari_64
    5520             :   { 2102,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo335, -1 ,nullptr },  // Inst #2102 = ST_f16x2_asi
    5521             :   { 2103,       7,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo336, -1 ,nullptr },  // Inst #2103 = ST_f16x2_avar
    5522             :   { 2104,       7,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr },  // Inst #2104 = ST_f32_areg
    5523             :   { 2105,       7,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr },  // Inst #2105 = ST_f32_areg_64
    5524             :   { 2106,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo339, -1 ,nullptr },  // Inst #2106 = ST_f32_ari
    5525             :   { 2107,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo340, -1 ,nullptr },  // Inst #2107 = ST_f32_ari_64
    5526             :   { 2108,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr },  // Inst #2108 = ST_f32_asi
    5527             :   { 2109,       7,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr },  // Inst #2109 = ST_f32_avar
    5528             :   { 2110,       7,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr },  // Inst #2110 = ST_f64_areg
    5529             :   { 2111,       7,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr },  // Inst #2111 = ST_f64_areg_64
    5530             :   { 2112,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo345, -1 ,nullptr },  // Inst #2112 = ST_f64_ari
    5531             :   { 2113,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo346, -1 ,nullptr },  // Inst #2113 = ST_f64_ari_64
    5532             :   { 2114,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo347, -1 ,nullptr },  // Inst #2114 = ST_f64_asi
    5533             :   { 2115,       7,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo348, -1 ,nullptr },  // Inst #2115 = ST_f64_avar
    5534             :   { 2116,       7,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo349, -1 ,nullptr },  // Inst #2116 = ST_i16_areg
    5535             :   { 2117,       7,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo350, -1 ,nullptr },  // Inst #2117 = ST_i16_areg_64
    5536             :   { 2118,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo351, -1 ,nullptr },  // Inst #2118 = ST_i16_ari
    5537             :   { 2119,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo352, -1 ,nullptr },  // Inst #2119 = ST_i16_ari_64
    5538             :   { 2120,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo353, -1 ,nullptr },  // Inst #2120 = ST_i16_asi
    5539             :   { 2121,       7,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo354, -1 ,nullptr },  // Inst #2121 = ST_i16_avar
    5540             :   { 2122,       7,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo355, -1 ,nullptr },  // Inst #2122 = ST_i32_areg
    5541             :   { 2123,       7,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo356, -1 ,nullptr },  // Inst #2123 = ST_i32_areg_64
    5542             :   { 2124,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo357, -1 ,nullptr },  // Inst #2124 = ST_i32_ari
    5543             :   { 2125,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo358, -1 ,nullptr },  // Inst #2125 = ST_i32_ari_64
    5544             :   { 2126,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr },  // Inst #2126 = ST_i32_asi
    5545             :   { 2127,       7,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo360, -1 ,nullptr },  // Inst #2127 = ST_i32_avar
    5546             :   { 2128,       7,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo361, -1 ,nullptr },  // Inst #2128 = ST_i64_areg
    5547             :   { 2129,       7,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo362, -1 ,nullptr },  // Inst #2129 = ST_i64_areg_64
    5548             :   { 2130,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo363, -1 ,nullptr },  // Inst #2130 = ST_i64_ari
    5549             :   { 2131,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo364, -1 ,nullptr },  // Inst #2131 = ST_i64_ari_64
    5550             :   { 2132,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo365, -1 ,nullptr },  // Inst #2132 = ST_i64_asi
    5551             :   { 2133,       7,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo366, -1 ,nullptr },  // Inst #2133 = ST_i64_avar
    5552             :   { 2134,       7,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo349, -1 ,nullptr },  // Inst #2134 = ST_i8_areg
    5553             :   { 2135,       7,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo350, -1 ,nullptr },  // Inst #2135 = ST_i8_areg_64
    5554             :   { 2136,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo351, -1 ,nullptr },  // Inst #2136 = ST_i8_ari
    5555             :   { 2137,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo352, -1 ,nullptr },  // Inst #2137 = ST_i8_ari_64
    5556             :   { 2138,       8,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo353, -1 ,nullptr },  // Inst #2138 = ST_i8_asi
    5557             :   { 2139,       7,      0,      0,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo354, -1 ,nullptr },  // Inst #2139 = ST_i8_avar
    5558             :   { 2140,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #2140 = SUBCCCi32ri
    5559             :   { 2141,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #2141 = SUBCCCi32rr
    5560             :   { 2142,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #2142 = SUBCCi32ri
    5561             :   { 2143,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #2143 = SUBCCi32rr
    5562             :   { 2144,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #2144 = SUB_i1_ri
    5563             :   { 2145,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #2145 = SUB_i1_rr
    5564             :   { 2146,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #2146 = SUBi16ri
    5565             :   { 2147,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #2147 = SUBi16rr
    5566             :   { 2148,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #2148 = SUBi32ri
    5567             :   { 2149,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #2149 = SUBi32rr
    5568             :   { 2150,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #2150 = SUBi64ri
    5569             :   { 2151,       3,      1,      0,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #2151 = SUBi64rr
    5570             :   { 2152,       4,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo444, -1 ,nullptr },  // Inst #2152 = SULD_1D_ARRAY_I16_CLAMP
    5571             :   { 2153,       4,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo444, -1 ,nullptr },  // Inst #2153 = SULD_1D_ARRAY_I16_TRAP
    5572             :   { 2154,       4,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo444, -1 ,nullptr },  // Inst #2154 = SULD_1D_ARRAY_I16_ZERO
    5573             :   { 2155,       4,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #2155 = SULD_1D_ARRAY_I32_CLAMP
    5574             :   { 2156,       4,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #2156 = SULD_1D_ARRAY_I32_TRAP
    5575             :   { 2157,       4,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #2157 = SULD_1D_ARRAY_I32_ZERO
    5576             :   { 2158,       4,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #2158 = SULD_1D_ARRAY_I64_CLAMP
    5577             :   { 2159,       4,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #2159 = SULD_1D_ARRAY_I64_TRAP
    5578             :   { 2160,       4,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #2160 = SULD_1D_ARRAY_I64_ZERO
    5579             :   { 2161,       4,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo444, -1 ,nullptr },  // Inst #2161 = SULD_1D_ARRAY_I8_CLAMP
    5580             :   { 2162,       4,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo444, -1 ,nullptr },  // Inst #2162 = SULD_1D_ARRAY_I8_TRAP
    5581             :   { 2163,       4,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo444, -1 ,nullptr },  // Inst #2163 = SULD_1D_ARRAY_I8_ZERO
    5582             :   { 2164,       5,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo445, -1 ,nullptr },  // Inst #2164 = SULD_1D_ARRAY_V2I16_CLAMP
    5583             :   { 2165,       5,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo445, -1 ,nullptr },  // Inst #2165 = SULD_1D_ARRAY_V2I16_TRAP
    5584             :   { 2166,       5,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo445, -1 ,nullptr },  // Inst #2166 = SULD_1D_ARRAY_V2I16_ZERO
    5585             :   { 2167,       5,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo446, -1 ,nullptr },  // Inst #2167 = SULD_1D_ARRAY_V2I32_CLAMP
    5586             :   { 2168,       5,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo446, -1 ,nullptr },  // Inst #2168 = SULD_1D_ARRAY_V2I32_TRAP
    5587             :   { 2169,       5,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo446, -1 ,nullptr },  // Inst #2169 = SULD_1D_ARRAY_V2I32_ZERO
    5588             :   { 2170,       5,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo447, -1 ,nullptr },  // Inst #2170 = SULD_1D_ARRAY_V2I64_CLAMP
    5589             :   { 2171,       5,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo447, -1 ,nullptr },  // Inst #2171 = SULD_1D_ARRAY_V2I64_TRAP
    5590             :   { 2172,       5,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo447, -1 ,nullptr },  // Inst #2172 = SULD_1D_ARRAY_V2I64_ZERO
    5591             :   { 2173,       5,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo445, -1 ,nullptr },  // Inst #2173 = SULD_1D_ARRAY_V2I8_CLAMP
    5592             :   { 2174,       5,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo445, -1 ,nullptr },  // Inst #2174 = SULD_1D_ARRAY_V2I8_TRAP
    5593             :   { 2175,       5,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo445, -1 ,nullptr },  // Inst #2175 = SULD_1D_ARRAY_V2I8_ZERO
    5594             :   { 2176,       7,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr },  // Inst #2176 = SULD_1D_ARRAY_V4I16_CLAMP
    5595             :   { 2177,       7,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr },  // Inst #2177 = SULD_1D_ARRAY_V4I16_TRAP
    5596             :   { 2178,       7,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr },  // Inst #2178 = SULD_1D_ARRAY_V4I16_ZERO
    5597             :   { 2179,       7,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo449, -1 ,nullptr },  // Inst #2179 = SULD_1D_ARRAY_V4I32_CLAMP
    5598             :   { 2180,       7,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo449, -1 ,nullptr },  // Inst #2180 = SULD_1D_ARRAY_V4I32_TRAP
    5599             :   { 2181,       7,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo449, -1 ,nullptr },  // Inst #2181 = SULD_1D_ARRAY_V4I32_ZERO
    5600             :   { 2182,       7,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr },  // Inst #2182 = SULD_1D_ARRAY_V4I8_CLAMP
    5601             :   { 2183,       7,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr },  // Inst #2183 = SULD_1D_ARRAY_V4I8_TRAP
    5602             :   { 2184,       7,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr },  // Inst #2184 = SULD_1D_ARRAY_V4I8_ZERO
    5603             :   { 2185,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo450, -1 ,nullptr },  // Inst #2185 = SULD_1D_I16_CLAMP
    5604             :   { 2186,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo450, -1 ,nullptr },  // Inst #2186 = SULD_1D_I16_TRAP
    5605             :   { 2187,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo450, -1 ,nullptr },  // Inst #2187 = SULD_1D_I16_ZERO
    5606             :   { 2188,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #2188 = SULD_1D_I32_CLAMP
    5607             :   { 2189,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #2189 = SULD_1D_I32_TRAP
    5608             :   { 2190,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #2190 = SULD_1D_I32_ZERO
    5609             :   { 2191,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr },  // Inst #2191 = SULD_1D_I64_CLAMP
    5610             :   { 2192,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr },  // Inst #2192 = SULD_1D_I64_TRAP
    5611             :   { 2193,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr },  // Inst #2193 = SULD_1D_I64_ZERO
    5612             :   { 2194,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo450, -1 ,nullptr },  // Inst #2194 = SULD_1D_I8_CLAMP
    5613             :   { 2195,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo450, -1 ,nullptr },  // Inst #2195 = SULD_1D_I8_TRAP
    5614             :   { 2196,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo450, -1 ,nullptr },  // Inst #2196 = SULD_1D_I8_ZERO
    5615             :   { 2197,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo451, -1 ,nullptr },  // Inst #2197 = SULD_1D_V2I16_CLAMP
    5616             :   { 2198,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo451, -1 ,nullptr },  // Inst #2198 = SULD_1D_V2I16_TRAP
    5617             :   { 2199,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo451, -1 ,nullptr },  // Inst #2199 = SULD_1D_V2I16_ZERO
    5618             :   { 2200,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo452, -1 ,nullptr },  // Inst #2200 = SULD_1D_V2I32_CLAMP
    5619             :   { 2201,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo452, -1 ,nullptr },  // Inst #2201 = SULD_1D_V2I32_TRAP
    5620             :   { 2202,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo452, -1 ,nullptr },  // Inst #2202 = SULD_1D_V2I32_ZERO
    5621             :   { 2203,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo453, -1 ,nullptr },  // Inst #2203 = SULD_1D_V2I64_CLAMP
    5622             :   { 2204,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo453, -1 ,nullptr },  // Inst #2204 = SULD_1D_V2I64_TRAP
    5623             :   { 2205,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo453, -1 ,nullptr },  // Inst #2205 = SULD_1D_V2I64_ZERO
    5624             :   { 2206,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo451, -1 ,nullptr },  // Inst #2206 = SULD_1D_V2I8_CLAMP
    5625             :   { 2207,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo451, -1 ,nullptr },  // Inst #2207 = SULD_1D_V2I8_TRAP
    5626             :   { 2208,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo451, -1 ,nullptr },  // Inst #2208 = SULD_1D_V2I8_ZERO
    5627             :   { 2209,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo454, -1 ,nullptr },  // Inst #2209 = SULD_1D_V4I16_CLAMP
    5628             :   { 2210,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo454, -1 ,nullptr },  // Inst #2210 = SULD_1D_V4I16_TRAP
    5629             :   { 2211,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo454, -1 ,nullptr },  // Inst #2211 = SULD_1D_V4I16_ZERO
    5630             :   { 2212,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo455, -1 ,nullptr },  // Inst #2212 = SULD_1D_V4I32_CLAMP
    5631             :   { 2213,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo455, -1 ,nullptr },  // Inst #2213 = SULD_1D_V4I32_TRAP
    5632             :   { 2214,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo455, -1 ,nullptr },  // Inst #2214 = SULD_1D_V4I32_ZERO
    5633             :   { 2215,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo454, -1 ,nullptr },  // Inst #2215 = SULD_1D_V4I8_CLAMP
    5634             :   { 2216,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo454, -1 ,nullptr },  // Inst #2216 = SULD_1D_V4I8_TRAP
    5635             :   { 2217,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo454, -1 ,nullptr },  // Inst #2217 = SULD_1D_V4I8_ZERO
    5636             :   { 2218,       5,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo456, -1 ,nullptr },  // Inst #2218 = SULD_2D_ARRAY_I16_CLAMP
    5637             :   { 2219,       5,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo456, -1 ,nullptr },  // Inst #2219 = SULD_2D_ARRAY_I16_TRAP
    5638             :   { 2220,       5,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo456, -1 ,nullptr },  // Inst #2220 = SULD_2D_ARRAY_I16_ZERO
    5639             :   { 2221,       5,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo457, -1 ,nullptr },  // Inst #2221 = SULD_2D_ARRAY_I32_CLAMP
    5640             :   { 2222,       5,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo457, -1 ,nullptr },  // Inst #2222 = SULD_2D_ARRAY_I32_TRAP
    5641             :   { 2223,       5,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo457, -1 ,nullptr },  // Inst #2223 = SULD_2D_ARRAY_I32_ZERO
    5642             :   { 2224,       5,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo458, -1 ,nullptr },  // Inst #2224 = SULD_2D_ARRAY_I64_CLAMP
    5643             :   { 2225,       5,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo458, -1 ,nullptr },  // Inst #2225 = SULD_2D_ARRAY_I64_TRAP
    5644             :   { 2226,       5,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo458, -1 ,nullptr },  // Inst #2226 = SULD_2D_ARRAY_I64_ZERO
    5645             :   { 2227,       5,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo456, -1 ,nullptr },  // Inst #2227 = SULD_2D_ARRAY_I8_CLAMP
    5646             :   { 2228,       5,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo456, -1 ,nullptr },  // Inst #2228 = SULD_2D_ARRAY_I8_TRAP
    5647             :   { 2229,       5,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo456, -1 ,nullptr },  // Inst #2229 = SULD_2D_ARRAY_I8_ZERO
    5648             :   { 2230,       6,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo459, -1 ,nullptr },  // Inst #2230 = SULD_2D_ARRAY_V2I16_CLAMP
    5649             :   { 2231,       6,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo459, -1 ,nullptr },  // Inst #2231 = SULD_2D_ARRAY_V2I16_TRAP
    5650             :   { 2232,       6,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo459, -1 ,nullptr },  // Inst #2232 = SULD_2D_ARRAY_V2I16_ZERO
    5651             :   { 2233,       6,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo460, -1 ,nullptr },  // Inst #2233 = SULD_2D_ARRAY_V2I32_CLAMP
    5652             :   { 2234,       6,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo460, -1 ,nullptr },  // Inst #2234 = SULD_2D_ARRAY_V2I32_TRAP
    5653             :   { 2235,       6,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo460, -1 ,nullptr },  // Inst #2235 = SULD_2D_ARRAY_V2I32_ZERO
    5654             :   { 2236,       6,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo461, -1 ,nullptr },  // Inst #2236 = SULD_2D_ARRAY_V2I64_CLAMP
    5655             :   { 2237,       6,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo461, -1 ,nullptr },  // Inst #2237 = SULD_2D_ARRAY_V2I64_TRAP
    5656             :   { 2238,       6,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo461, -1 ,nullptr },  // Inst #2238 = SULD_2D_ARRAY_V2I64_ZERO
    5657             :   { 2239,       6,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo459, -1 ,nullptr },  // Inst #2239 = SULD_2D_ARRAY_V2I8_CLAMP
    5658             :   { 2240,       6,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo459, -1 ,nullptr },  // Inst #2240 = SULD_2D_ARRAY_V2I8_TRAP
    5659             :   { 2241,       6,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo459, -1 ,nullptr },  // Inst #2241 = SULD_2D_ARRAY_V2I8_ZERO
    5660             :   { 2242,       8,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo462, -1 ,nullptr },  // Inst #2242 = SULD_2D_ARRAY_V4I16_CLAMP
    5661             :   { 2243,       8,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo462, -1 ,nullptr },  // Inst #2243 = SULD_2D_ARRAY_V4I16_TRAP
    5662             :   { 2244,       8,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo462, -1 ,nullptr },  // Inst #2244 = SULD_2D_ARRAY_V4I16_ZERO
    5663             :   { 2245,       8,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo463, -1 ,nullptr },  // Inst #2245 = SULD_2D_ARRAY_V4I32_CLAMP
    5664             :   { 2246,       8,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo463, -1 ,nullptr },  // Inst #2246 = SULD_2D_ARRAY_V4I32_TRAP
    5665             :   { 2247,       8,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo463, -1 ,nullptr },  // Inst #2247 = SULD_2D_ARRAY_V4I32_ZERO
    5666             :   { 2248,       8,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo462, -1 ,nullptr },  // Inst #2248 = SULD_2D_ARRAY_V4I8_CLAMP
    5667             :   { 2249,       8,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo462, -1 ,nullptr },  // Inst #2249 = SULD_2D_ARRAY_V4I8_TRAP
    5668             :   { 2250,       8,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo462, -1 ,nullptr },  // Inst #2250 = SULD_2D_ARRAY_V4I8_ZERO
    5669             :   { 2251,       4,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo444, -1 ,nullptr },  // Inst #2251 = SULD_2D_I16_CLAMP
    5670             :   { 2252,       4,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo444, -1 ,nullptr },  // Inst #2252 = SULD_2D_I16_TRAP
    5671             :   { 2253,       4,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo444, -1 ,nullptr },  // Inst #2253 = SULD_2D_I16_ZERO
    5672             :   { 2254,       4,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #2254 = SULD_2D_I32_CLAMP
    5673             :   { 2255,       4,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #2255 = SULD_2D_I32_TRAP
    5674             :   { 2256,       4,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #2256 = SULD_2D_I32_ZERO
    5675             :   { 2257,       4,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #2257 = SULD_2D_I64_CLAMP
    5676             :   { 2258,       4,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #2258 = SULD_2D_I64_TRAP
    5677             :   { 2259,       4,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #2259 = SULD_2D_I64_ZERO
    5678             :   { 2260,       4,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo444, -1 ,nullptr },  // Inst #2260 = SULD_2D_I8_CLAMP
    5679             :   { 2261,       4,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo444, -1 ,nullptr },  // Inst #2261 = SULD_2D_I8_TRAP
    5680             :   { 2262,       4,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo444, -1 ,nullptr },  // Inst #2262 = SULD_2D_I8_ZERO
    5681             :   { 2263,       5,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo445, -1 ,nullptr },  // Inst #2263 = SULD_2D_V2I16_CLAMP
    5682             :   { 2264,       5,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo445, -1 ,nullptr },  // Inst #2264 = SULD_2D_V2I16_TRAP
    5683             :   { 2265,       5,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo445, -1 ,nullptr },  // Inst #2265 = SULD_2D_V2I16_ZERO
    5684             :   { 2266,       5,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo446, -1 ,nullptr },  // Inst #2266 = SULD_2D_V2I32_CLAMP
    5685             :   { 2267,       5,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo446, -1 ,nullptr },  // Inst #2267 = SULD_2D_V2I32_TRAP
    5686             :   { 2268,       5,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo446, -1 ,nullptr },  // Inst #2268 = SULD_2D_V2I32_ZERO
    5687             :   { 2269,       5,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo447, -1 ,nullptr },  // Inst #2269 = SULD_2D_V2I64_CLAMP
    5688             :   { 2270,       5,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo447, -1 ,nullptr },  // Inst #2270 = SULD_2D_V2I64_TRAP
    5689             :   { 2271,       5,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo447, -1 ,nullptr },  // Inst #2271 = SULD_2D_V2I64_ZERO
    5690             :   { 2272,       5,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo445, -1 ,nullptr },  // Inst #2272 = SULD_2D_V2I8_CLAMP
    5691             :   { 2273,       5,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo445, -1 ,nullptr },  // Inst #2273 = SULD_2D_V2I8_TRAP
    5692             :   { 2274,       5,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo445, -1 ,nullptr },  // Inst #2274 = SULD_2D_V2I8_ZERO
    5693             :   { 2275,       7,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr },  // Inst #2275 = SULD_2D_V4I16_CLAMP
    5694             :   { 2276,       7,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr },  // Inst #2276 = SULD_2D_V4I16_TRAP
    5695             :   { 2277,       7,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr },  // Inst #2277 = SULD_2D_V4I16_ZERO
    5696             :   { 2278,       7,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo449, -1 ,nullptr },  // Inst #2278 = SULD_2D_V4I32_CLAMP
    5697             :   { 2279,       7,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo449, -1 ,nullptr },  // Inst #2279 = SULD_2D_V4I32_TRAP
    5698             :   { 2280,       7,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo449, -1 ,nullptr },  // Inst #2280 = SULD_2D_V4I32_ZERO
    5699             :   { 2281,       7,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr },  // Inst #2281 = SULD_2D_V4I8_CLAMP
    5700             :   { 2282,       7,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr },  // Inst #2282 = SULD_2D_V4I8_TRAP
    5701             :   { 2283,       7,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr },  // Inst #2283 = SULD_2D_V4I8_ZERO
    5702             :   { 2284,       5,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo456, -1 ,nullptr },  // Inst #2284 = SULD_3D_I16_CLAMP
    5703             :   { 2285,       5,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo456, -1 ,nullptr },  // Inst #2285 = SULD_3D_I16_TRAP
    5704             :   { 2286,       5,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo456, -1 ,nullptr },  // Inst #2286 = SULD_3D_I16_ZERO
    5705             :   { 2287,       5,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo457, -1 ,nullptr },  // Inst #2287 = SULD_3D_I32_CLAMP
    5706             :   { 2288,       5,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo457, -1 ,nullptr },  // Inst #2288 = SULD_3D_I32_TRAP
    5707             :   { 2289,       5,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo457, -1 ,nullptr },  // Inst #2289 = SULD_3D_I32_ZERO
    5708             :   { 2290,       5,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo458, -1 ,nullptr },  // Inst #2290 = SULD_3D_I64_CLAMP
    5709             :   { 2291,       5,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo458, -1 ,nullptr },  // Inst #2291 = SULD_3D_I64_TRAP
    5710             :   { 2292,       5,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo458, -1 ,nullptr },  // Inst #2292 = SULD_3D_I64_ZERO
    5711             :   { 2293,       5,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo456, -1 ,nullptr },  // Inst #2293 = SULD_3D_I8_CLAMP
    5712             :   { 2294,       5,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo456, -1 ,nullptr },  // Inst #2294 = SULD_3D_I8_TRAP
    5713             :   { 2295,       5,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo456, -1 ,nullptr },  // Inst #2295 = SULD_3D_I8_ZERO
    5714             :   { 2296,       6,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo459, -1 ,nullptr },  // Inst #2296 = SULD_3D_V2I16_CLAMP
    5715             :   { 2297,       6,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo459, -1 ,nullptr },  // Inst #2297 = SULD_3D_V2I16_TRAP
    5716             :   { 2298,       6,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo459, -1 ,nullptr },  // Inst #2298 = SULD_3D_V2I16_ZERO
    5717             :   { 2299,       6,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo460, -1 ,nullptr },  // Inst #2299 = SULD_3D_V2I32_CLAMP
    5718             :   { 2300,       6,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo460, -1 ,nullptr },  // Inst #2300 = SULD_3D_V2I32_TRAP
    5719             :   { 2301,       6,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo460, -1 ,nullptr },  // Inst #2301 = SULD_3D_V2I32_ZERO
    5720             :   { 2302,       6,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo461, -1 ,nullptr },  // Inst #2302 = SULD_3D_V2I64_CLAMP
    5721             :   { 2303,       6,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo461, -1 ,nullptr },  // Inst #2303 = SULD_3D_V2I64_TRAP
    5722             :   { 2304,       6,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo461, -1 ,nullptr },  // Inst #2304 = SULD_3D_V2I64_ZERO
    5723             :   { 2305,       6,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo459, -1 ,nullptr },  // Inst #2305 = SULD_3D_V2I8_CLAMP
    5724             :   { 2306,       6,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo459, -1 ,nullptr },  // Inst #2306 = SULD_3D_V2I8_TRAP
    5725             :   { 2307,       6,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo459, -1 ,nullptr },  // Inst #2307 = SULD_3D_V2I8_ZERO
    5726             :   { 2308,       8,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo462, -1 ,nullptr },  // Inst #2308 = SULD_3D_V4I16_CLAMP
    5727             :   { 2309,       8,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo462, -1 ,nullptr },  // Inst #2309 = SULD_3D_V4I16_TRAP
    5728             :   { 2310,       8,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo462, -1 ,nullptr },  // Inst #2310 = SULD_3D_V4I16_ZERO
    5729             :   { 2311,       8,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo463, -1 ,nullptr },  // Inst #2311 = SULD_3D_V4I32_CLAMP
    5730             :   { 2312,       8,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo463, -1 ,nullptr },  // Inst #2312 = SULD_3D_V4I32_TRAP
    5731             :   { 2313,       8,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo463, -1 ,nullptr },  // Inst #2313 = SULD_3D_V4I32_ZERO
    5732             :   { 2314,       8,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo462, -1 ,nullptr },  // Inst #2314 = SULD_3D_V4I8_CLAMP
    5733             :   { 2315,       8,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo462, -1 ,nullptr },  // Inst #2315 = SULD_3D_V4I8_TRAP
    5734             :   { 2316,       8,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, nullptr, OperandInfo462, -1 ,nullptr },  // Inst #2316 = SULD_3D_V4I8_ZERO
    5735             :   { 2317,       2,      1,      0,      0,      0, 0x800ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #2317 = SUQ_ARRAY_SIZE
    5736             :   { 2318,       2,      1,      0,      0,      0, 0x800ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #2318 = SUQ_CHANNEL_DATA_TYPE
    5737             :   { 2319,       2,      1,      0,      0,      0, 0x800ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #2319 = SUQ_CHANNEL_ORDER
    5738             :   { 2320,       2,      1,      0,      0,      0, 0x800ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #2320 = SUQ_DEPTH
    5739             :   { 2321,       2,      1,      0,      0,      0, 0x800ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #2321 = SUQ_HEIGHT
    5740             :   { 2322,       2,      1,      0,      0,      0, 0x800ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #2322 = SUQ_WIDTH
    5741             :   { 2323,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo464, -1 ,nullptr },  // Inst #2323 = SUST_B_1D_ARRAY_B16_CLAMP
    5742             :   { 2324,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo464, -1 ,nullptr },  // Inst #2324 = SUST_B_1D_ARRAY_B16_TRAP
    5743             :   { 2325,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo464, -1 ,nullptr },  // Inst #2325 = SUST_B_1D_ARRAY_B16_ZERO
    5744             :   { 2326,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo465, -1 ,nullptr },  // Inst #2326 = SUST_B_1D_ARRAY_B32_CLAMP
    5745             :   { 2327,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo465, -1 ,nullptr },  // Inst #2327 = SUST_B_1D_ARRAY_B32_TRAP
    5746             :   { 2328,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo465, -1 ,nullptr },  // Inst #2328 = SUST_B_1D_ARRAY_B32_ZERO
    5747             :   { 2329,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo466, -1 ,nullptr },  // Inst #2329 = SUST_B_1D_ARRAY_B64_CLAMP
    5748             :   { 2330,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo466, -1 ,nullptr },  // Inst #2330 = SUST_B_1D_ARRAY_B64_TRAP
    5749             :   { 2331,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo466, -1 ,nullptr },  // Inst #2331 = SUST_B_1D_ARRAY_B64_ZERO
    5750             :   { 2332,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo464, -1 ,nullptr },  // Inst #2332 = SUST_B_1D_ARRAY_B8_CLAMP
    5751             :   { 2333,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo464, -1 ,nullptr },  // Inst #2333 = SUST_B_1D_ARRAY_B8_TRAP
    5752             :   { 2334,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo464, -1 ,nullptr },  // Inst #2334 = SUST_B_1D_ARRAY_B8_ZERO
    5753             :   { 2335,       5,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo467, -1 ,nullptr },  // Inst #2335 = SUST_B_1D_ARRAY_V2B16_CLAMP
    5754             :   { 2336,       5,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo467, -1 ,nullptr },  // Inst #2336 = SUST_B_1D_ARRAY_V2B16_TRAP
    5755             :   { 2337,       5,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo467, -1 ,nullptr },  // Inst #2337 = SUST_B_1D_ARRAY_V2B16_ZERO
    5756             :   { 2338,       5,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo468, -1 ,nullptr },  // Inst #2338 = SUST_B_1D_ARRAY_V2B32_CLAMP
    5757             :   { 2339,       5,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo468, -1 ,nullptr },  // Inst #2339 = SUST_B_1D_ARRAY_V2B32_TRAP
    5758             :   { 2340,       5,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo468, -1 ,nullptr },  // Inst #2340 = SUST_B_1D_ARRAY_V2B32_ZERO
    5759             :   { 2341,       5,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo469, -1 ,nullptr },  // Inst #2341 = SUST_B_1D_ARRAY_V2B64_CLAMP
    5760             :   { 2342,       5,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo469, -1 ,nullptr },  // Inst #2342 = SUST_B_1D_ARRAY_V2B64_TRAP
    5761             :   { 2343,       5,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo469, -1 ,nullptr },  // Inst #2343 = SUST_B_1D_ARRAY_V2B64_ZERO
    5762             :   { 2344,       5,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo467, -1 ,nullptr },  // Inst #2344 = SUST_B_1D_ARRAY_V2B8_CLAMP
    5763             :   { 2345,       5,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo467, -1 ,nullptr },  // Inst #2345 = SUST_B_1D_ARRAY_V2B8_TRAP
    5764             :   { 2346,       5,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo467, -1 ,nullptr },  // Inst #2346 = SUST_B_1D_ARRAY_V2B8_ZERO
    5765             :   { 2347,       7,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo470, -1 ,nullptr },  // Inst #2347 = SUST_B_1D_ARRAY_V4B16_CLAMP
    5766             :   { 2348,       7,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo470, -1 ,nullptr },  // Inst #2348 = SUST_B_1D_ARRAY_V4B16_TRAP
    5767             :   { 2349,       7,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo470, -1 ,nullptr },  // Inst #2349 = SUST_B_1D_ARRAY_V4B16_ZERO
    5768             :   { 2350,       7,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo471, -1 ,nullptr },  // Inst #2350 = SUST_B_1D_ARRAY_V4B32_CLAMP
    5769             :   { 2351,       7,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo471, -1 ,nullptr },  // Inst #2351 = SUST_B_1D_ARRAY_V4B32_TRAP
    5770             :   { 2352,       7,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo471, -1 ,nullptr },  // Inst #2352 = SUST_B_1D_ARRAY_V4B32_ZERO
    5771             :   { 2353,       7,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo470, -1 ,nullptr },  // Inst #2353 = SUST_B_1D_ARRAY_V4B8_CLAMP
    5772             :   { 2354,       7,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo470, -1 ,nullptr },  // Inst #2354 = SUST_B_1D_ARRAY_V4B8_TRAP
    5773             :   { 2355,       7,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo470, -1 ,nullptr },  // Inst #2355 = SUST_B_1D_ARRAY_V4B8_ZERO
    5774             :   { 2356,       3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo472, -1 ,nullptr },  // Inst #2356 = SUST_B_1D_B16_CLAMP
    5775             :   { 2357,       3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo472, -1 ,nullptr },  // Inst #2357 = SUST_B_1D_B16_TRAP
    5776             :   { 2358,       3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo472, -1 ,nullptr },  // Inst #2358 = SUST_B_1D_B16_ZERO
    5777             :   { 2359,       3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo382, -1 ,nullptr },  // Inst #2359 = SUST_B_1D_B32_CLAMP
    5778             :   { 2360,       3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo382, -1 ,nullptr },  // Inst #2360 = SUST_B_1D_B32_TRAP
    5779             :   { 2361,       3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo382, -1 ,nullptr },  // Inst #2361 = SUST_B_1D_B32_ZERO
    5780             :   { 2362,       3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #2362 = SUST_B_1D_B64_CLAMP
    5781             :   { 2363,       3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #2363 = SUST_B_1D_B64_TRAP
    5782             :   { 2364,       3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #2364 = SUST_B_1D_B64_ZERO
    5783             :   { 2365,       3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo472, -1 ,nullptr },  // Inst #2365 = SUST_B_1D_B8_CLAMP
    5784             :   { 2366,       3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo472, -1 ,nullptr },  // Inst #2366 = SUST_B_1D_B8_TRAP
    5785             :   { 2367,       3,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo472, -1 ,nullptr },  // Inst #2367 = SUST_B_1D_B8_ZERO
    5786             :   { 2368,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo473, -1 ,nullptr },  // Inst #2368 = SUST_B_1D_V2B16_CLAMP
    5787             :   { 2369,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo473, -1 ,nullptr },  // Inst #2369 = SUST_B_1D_V2B16_TRAP
    5788             :   { 2370,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo473, -1 ,nullptr },  // Inst #2370 = SUST_B_1D_V2B16_ZERO
    5789             :   { 2371,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo465, -1 ,nullptr },  // Inst #2371 = SUST_B_1D_V2B32_CLAMP
    5790             :   { 2372,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo465, -1 ,nullptr },  // Inst #2372 = SUST_B_1D_V2B32_TRAP
    5791             :   { 2373,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo465, -1 ,nullptr },  // Inst #2373 = SUST_B_1D_V2B32_ZERO
    5792             :   { 2374,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #2374 = SUST_B_1D_V2B64_CLAMP
    5793             :   { 2375,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #2375 = SUST_B_1D_V2B64_TRAP
    5794             :   { 2376,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #2376 = SUST_B_1D_V2B64_ZERO
    5795             :   { 2377,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo473, -1 ,nullptr },  // Inst #2377 = SUST_B_1D_V2B8_CLAMP
    5796             :   { 2378,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo473, -1 ,nullptr },  // Inst #2378 = SUST_B_1D_V2B8_TRAP
    5797             :   { 2379,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo473, -1 ,nullptr },  // Inst #2379 = SUST_B_1D_V2B8_ZERO
    5798             :   { 2380,       6,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo474, -1 ,nullptr },  // Inst #2380 = SUST_B_1D_V4B16_CLAMP
    5799             :   { 2381,       6,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo474, -1 ,nullptr },  // Inst #2381 = SUST_B_1D_V4B16_TRAP
    5800             :   { 2382,       6,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo474, -1 ,nullptr },  // Inst #2382 = SUST_B_1D_V4B16_ZERO
    5801             :   { 2383,       6,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo475, -1 ,nullptr },  // Inst #2383 = SUST_B_1D_V4B32_CLAMP
    5802             :   { 2384,       6,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo475, -1 ,nullptr },  // Inst #2384 = SUST_B_1D_V4B32_TRAP
    5803             :   { 2385,       6,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo475, -1 ,nullptr },  // Inst #2385 = SUST_B_1D_V4B32_ZERO
    5804             :   { 2386,       6,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo474, -1 ,nullptr },  // Inst #2386 = SUST_B_1D_V4B8_CLAMP
    5805             :   { 2387,       6,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo474, -1 ,nullptr },  // Inst #2387 = SUST_B_1D_V4B8_TRAP
    5806             :   { 2388,       6,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo474, -1 ,nullptr },  // Inst #2388 = SUST_B_1D_V4B8_ZERO
    5807             :   { 2389,       5,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo476, -1 ,nullptr },  // Inst #2389 = SUST_B_2D_ARRAY_B16_CLAMP
    5808             :   { 2390,       5,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo476, -1 ,nullptr },  // Inst #2390 = SUST_B_2D_ARRAY_B16_TRAP
    5809             :   { 2391,       5,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo476, -1 ,nullptr },  // Inst #2391 = SUST_B_2D_ARRAY_B16_ZERO
    5810             :   { 2392,       5,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo468, -1 ,nullptr },  // Inst #2392 = SUST_B_2D_ARRAY_B32_CLAMP
    5811             :   { 2393,       5,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo468, -1 ,nullptr },  // Inst #2393 = SUST_B_2D_ARRAY_B32_TRAP
    5812             :   { 2394,       5,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo468, -1 ,nullptr },  // Inst #2394 = SUST_B_2D_ARRAY_B32_ZERO
    5813             :   { 2395,       5,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo477, -1 ,nullptr },  // Inst #2395 = SUST_B_2D_ARRAY_B64_CLAMP
    5814             :   { 2396,       5,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo477, -1 ,nullptr },  // Inst #2396 = SUST_B_2D_ARRAY_B64_TRAP
    5815             :   { 2397,       5,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo477, -1 ,nullptr },  // Inst #2397 = SUST_B_2D_ARRAY_B64_ZERO
    5816             :   { 2398,       5,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo476, -1 ,nullptr },  // Inst #2398 = SUST_B_2D_ARRAY_B8_CLAMP
    5817             :   { 2399,       5,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo476, -1 ,nullptr },  // Inst #2399 = SUST_B_2D_ARRAY_B8_TRAP
    5818             :   { 2400,       5,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo476, -1 ,nullptr },  // Inst #2400 = SUST_B_2D_ARRAY_B8_ZERO
    5819             :   { 2401,       6,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr },  // Inst #2401 = SUST_B_2D_ARRAY_V2B16_CLAMP
    5820             :   { 2402,       6,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr },  // Inst #2402 = SUST_B_2D_ARRAY_V2B16_TRAP
    5821             :   { 2403,       6,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr },  // Inst #2403 = SUST_B_2D_ARRAY_V2B16_ZERO
    5822             :   { 2404,       6,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo475, -1 ,nullptr },  // Inst #2404 = SUST_B_2D_ARRAY_V2B32_CLAMP
    5823             :   { 2405,       6,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo475, -1 ,nullptr },  // Inst #2405 = SUST_B_2D_ARRAY_V2B32_TRAP
    5824             :   { 2406,       6,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo475, -1 ,nullptr },  // Inst #2406 = SUST_B_2D_ARRAY_V2B32_ZERO
    5825             :   { 2407,       6,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo479, -1 ,nullptr },  // Inst #2407 = SUST_B_2D_ARRAY_V2B64_CLAMP
    5826             :   { 2408,       6,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo479, -1 ,nullptr },  // Inst #2408 = SUST_B_2D_ARRAY_V2B64_TRAP
    5827             :   { 2409,       6,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo479, -1 ,nullptr },  // Inst #2409 = SUST_B_2D_ARRAY_V2B64_ZERO
    5828             :   { 2410,       6,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr },  // Inst #2410 = SUST_B_2D_ARRAY_V2B8_CLAMP
    5829             :   { 2411,       6,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr },  // Inst #2411 = SUST_B_2D_ARRAY_V2B8_TRAP
    5830             :   { 2412,       6,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr },  // Inst #2412 = SUST_B_2D_ARRAY_V2B8_ZERO
    5831             :   { 2413,       8,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo480, -1 ,nullptr },  // Inst #2413 = SUST_B_2D_ARRAY_V4B16_CLAMP
    5832             :   { 2414,       8,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo480, -1 ,nullptr },  // Inst #2414 = SUST_B_2D_ARRAY_V4B16_TRAP
    5833             :   { 2415,       8,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo480, -1 ,nullptr },  // Inst #2415 = SUST_B_2D_ARRAY_V4B16_ZERO
    5834             :   { 2416,       8,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr },  // Inst #2416 = SUST_B_2D_ARRAY_V4B32_CLAMP
    5835             :   { 2417,       8,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr },  // Inst #2417 = SUST_B_2D_ARRAY_V4B32_TRAP
    5836             :   { 2418,       8,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr },  // Inst #2418 = SUST_B_2D_ARRAY_V4B32_ZERO
    5837             :   { 2419,       8,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo480, -1 ,nullptr },  // Inst #2419 = SUST_B_2D_ARRAY_V4B8_CLAMP
    5838             :   { 2420,       8,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo480, -1 ,nullptr },  // Inst #2420 = SUST_B_2D_ARRAY_V4B8_TRAP
    5839             :   { 2421,       8,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo480, -1 ,nullptr },  // Inst #2421 = SUST_B_2D_ARRAY_V4B8_ZERO
    5840             :   { 2422,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo464, -1 ,nullptr },  // Inst #2422 = SUST_B_2D_B16_CLAMP
    5841             :   { 2423,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo464, -1 ,nullptr },  // Inst #2423 = SUST_B_2D_B16_TRAP
    5842             :   { 2424,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo464, -1 ,nullptr },  // Inst #2424 = SUST_B_2D_B16_ZERO
    5843             :   { 2425,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo465, -1 ,nullptr },  // Inst #2425 = SUST_B_2D_B32_CLAMP
    5844             :   { 2426,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo465, -1 ,nullptr },  // Inst #2426 = SUST_B_2D_B32_TRAP
    5845             :   { 2427,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo465, -1 ,nullptr },  // Inst #2427 = SUST_B_2D_B32_ZERO
    5846             :   { 2428,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo466, -1 ,nullptr },  // Inst #2428 = SUST_B_2D_B64_CLAMP
    5847             :   { 2429,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo466, -1 ,nullptr },  // Inst #2429 = SUST_B_2D_B64_TRAP
    5848             :   { 2430,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo466, -1 ,nullptr },  // Inst #2430 = SUST_B_2D_B64_ZERO
    5849             :   { 2431,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo464, -1 ,nullptr },  // Inst #2431 = SUST_B_2D_B8_CLAMP
    5850             :   { 2432,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo464, -1 ,nullptr },  // Inst #2432 = SUST_B_2D_B8_TRAP
    5851             :   { 2433,       4,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo464, -1 ,nullptr },  // Inst #2433 = SUST_B_2D_B8_ZERO
    5852             :   { 2434,       5,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo467, -1 ,nullptr },  // Inst #2434 = SUST_B_2D_V2B16_CLAMP
    5853             :   { 2435,       5,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo467, -1 ,nullptr },  // Inst #2435 = SUST_B_2D_V2B16_TRAP
    5854             :   { 2436,       5,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL, nullptr, nullptr, OperandInfo467, -1 ,nullptr },  // Inst #2436 = SUST_B_2D_V2B16_ZERO
    5855             :   { 2437,       5,      0,      0,      0,