LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/NVPTX - NVPTXGenInstrInfo.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 4 4 100.0 %
Date: 2018-06-17 00:07:59 Functions: 1 3 33.3 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Target Instruction Enum Values and Descriptors                             *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : #ifdef GET_INSTRINFO_ENUM
      10             : #undef GET_INSTRINFO_ENUM
      11             : namespace llvm {
      12             : 
      13             : namespace NVPTX {
      14             :   enum {
      15             :     PHI = 0,
      16             :     INLINEASM   = 1,
      17             :     CFI_INSTRUCTION     = 2,
      18             :     EH_LABEL    = 3,
      19             :     GC_LABEL    = 4,
      20             :     ANNOTATION_LABEL    = 5,
      21             :     KILL        = 6,
      22             :     EXTRACT_SUBREG      = 7,
      23             :     INSERT_SUBREG       = 8,
      24             :     IMPLICIT_DEF        = 9,
      25             :     SUBREG_TO_REG       = 10,
      26             :     COPY_TO_REGCLASS    = 11,
      27             :     DBG_VALUE   = 12,
      28             :     DBG_LABEL   = 13,
      29             :     REG_SEQUENCE        = 14,
      30             :     COPY        = 15,
      31             :     BUNDLE      = 16,
      32             :     LIFETIME_START      = 17,
      33             :     LIFETIME_END        = 18,
      34             :     STACKMAP    = 19,
      35             :     FENTRY_CALL = 20,
      36             :     PATCHPOINT  = 21,
      37             :     LOAD_STACK_GUARD    = 22,
      38             :     STATEPOINT  = 23,
      39             :     LOCAL_ESCAPE        = 24,
      40             :     FAULTING_OP = 25,
      41             :     PATCHABLE_OP        = 26,
      42             :     PATCHABLE_FUNCTION_ENTER    = 27,
      43             :     PATCHABLE_RET       = 28,
      44             :     PATCHABLE_FUNCTION_EXIT     = 29,
      45             :     PATCHABLE_TAIL_CALL = 30,
      46             :     PATCHABLE_EVENT_CALL        = 31,
      47             :     PATCHABLE_TYPED_EVENT_CALL  = 32,
      48             :     ICALL_BRANCH_FUNNEL = 33,
      49             :     G_ADD       = 34,
      50             :     G_SUB       = 35,
      51             :     G_MUL       = 36,
      52             :     G_SDIV      = 37,
      53             :     G_UDIV      = 38,
      54             :     G_SREM      = 39,
      55             :     G_UREM      = 40,
      56             :     G_AND       = 41,
      57             :     G_OR        = 42,
      58             :     G_XOR       = 43,
      59             :     G_IMPLICIT_DEF      = 44,
      60             :     G_PHI       = 45,
      61             :     G_FRAME_INDEX       = 46,
      62             :     G_GLOBAL_VALUE      = 47,
      63             :     G_EXTRACT   = 48,
      64             :     G_UNMERGE_VALUES    = 49,
      65             :     G_INSERT    = 50,
      66             :     G_MERGE_VALUES      = 51,
      67             :     G_PTRTOINT  = 52,
      68             :     G_INTTOPTR  = 53,
      69             :     G_BITCAST   = 54,
      70             :     G_LOAD      = 55,
      71             :     G_SEXTLOAD  = 56,
      72             :     G_ZEXTLOAD  = 57,
      73             :     G_STORE     = 58,
      74             :     G_ATOMIC_CMPXCHG_WITH_SUCCESS       = 59,
      75             :     G_ATOMIC_CMPXCHG    = 60,
      76             :     G_ATOMICRMW_XCHG    = 61,
      77             :     G_ATOMICRMW_ADD     = 62,
      78             :     G_ATOMICRMW_SUB     = 63,
      79             :     G_ATOMICRMW_AND     = 64,
      80             :     G_ATOMICRMW_NAND    = 65,
      81             :     G_ATOMICRMW_OR      = 66,
      82             :     G_ATOMICRMW_XOR     = 67,
      83             :     G_ATOMICRMW_MAX     = 68,
      84             :     G_ATOMICRMW_MIN     = 69,
      85             :     G_ATOMICRMW_UMAX    = 70,
      86             :     G_ATOMICRMW_UMIN    = 71,
      87             :     G_BRCOND    = 72,
      88             :     G_BRINDIRECT        = 73,
      89             :     G_INTRINSIC = 74,
      90             :     G_INTRINSIC_W_SIDE_EFFECTS  = 75,
      91             :     G_ANYEXT    = 76,
      92             :     G_TRUNC     = 77,
      93             :     G_CONSTANT  = 78,
      94             :     G_FCONSTANT = 79,
      95             :     G_VASTART   = 80,
      96             :     G_VAARG     = 81,
      97             :     G_SEXT      = 82,
      98             :     G_ZEXT      = 83,
      99             :     G_SHL       = 84,
     100             :     G_LSHR      = 85,
     101             :     G_ASHR      = 86,
     102             :     G_ICMP      = 87,
     103             :     G_FCMP      = 88,
     104             :     G_SELECT    = 89,
     105             :     G_UADDE     = 90,
     106             :     G_USUBE     = 91,
     107             :     G_SADDO     = 92,
     108             :     G_SSUBO     = 93,
     109             :     G_UMULO     = 94,
     110             :     G_SMULO     = 95,
     111             :     G_UMULH     = 96,
     112             :     G_SMULH     = 97,
     113             :     G_FADD      = 98,
     114             :     G_FSUB      = 99,
     115             :     G_FMUL      = 100,
     116             :     G_FMA       = 101,
     117             :     G_FDIV      = 102,
     118             :     G_FREM      = 103,
     119             :     G_FPOW      = 104,
     120             :     G_FEXP      = 105,
     121             :     G_FEXP2     = 106,
     122             :     G_FLOG      = 107,
     123             :     G_FLOG2     = 108,
     124             :     G_FNEG      = 109,
     125             :     G_FPEXT     = 110,
     126             :     G_FPTRUNC   = 111,
     127             :     G_FPTOSI    = 112,
     128             :     G_FPTOUI    = 113,
     129             :     G_SITOFP    = 114,
     130             :     G_UITOFP    = 115,
     131             :     G_FABS      = 116,
     132             :     G_GEP       = 117,
     133             :     G_PTR_MASK  = 118,
     134             :     G_BR        = 119,
     135             :     G_INSERT_VECTOR_ELT = 120,
     136             :     G_EXTRACT_VECTOR_ELT        = 121,
     137             :     G_SHUFFLE_VECTOR    = 122,
     138             :     G_BSWAP     = 123,
     139             :     ADDCCCi32ri = 124,
     140             :     ADDCCCi32rr = 125,
     141             :     ADDCCi32ri  = 126,
     142             :     ADDCCi32rr  = 127,
     143             :     ADD_i1_ri   = 128,
     144             :     ADD_i1_rr   = 129,
     145             :     ADDi16ri    = 130,
     146             :     ADDi16rr    = 131,
     147             :     ADDi32ri    = 132,
     148             :     ADDi32rr    = 133,
     149             :     ADDi64ri    = 134,
     150             :     ADDi64rr    = 135,
     151             :     ANDb16ri    = 136,
     152             :     ANDb16rr    = 137,
     153             :     ANDb1ri     = 138,
     154             :     ANDb1rr     = 139,
     155             :     ANDb32ri    = 140,
     156             :     ANDb32rr    = 141,
     157             :     ANDb64ri    = 142,
     158             :     ANDb64rr    = 143,
     159             :     BFE_S32rii  = 144,
     160             :     BFE_S32rri  = 145,
     161             :     BFE_S32rrr  = 146,
     162             :     BFE_S64rii  = 147,
     163             :     BFE_S64rri  = 148,
     164             :     BFE_S64rrr  = 149,
     165             :     BFE_U32rii  = 150,
     166             :     BFE_U32rri  = 151,
     167             :     BFE_U32rrr  = 152,
     168             :     BFE_U64rii  = 153,
     169             :     BFE_U64rri  = 154,
     170             :     BFE_U64rrr  = 155,
     171             :     BITCONVERT_16_F2I   = 156,
     172             :     BITCONVERT_16_I2F   = 157,
     173             :     BITCONVERT_32_F16x22I       = 158,
     174             :     BITCONVERT_32_F2I   = 159,
     175             :     BITCONVERT_32_I2F   = 160,
     176             :     BITCONVERT_32_I2F16x2       = 161,
     177             :     BITCONVERT_64_F2I   = 162,
     178             :     BITCONVERT_64_I2F   = 163,
     179             :     BREV32      = 164,
     180             :     BREV64      = 165,
     181             :     BuildF16x2  = 166,
     182             :     BuildF16x2i = 167,
     183             :     CALL        = 168,
     184             :     CALL_PROTOTYPE      = 169,
     185             :     CBranch     = 170,
     186             :     CBranchOther        = 171,
     187             :     CLZr32      = 172,
     188             :     CLZr64      = 173,
     189             :     COSF        = 174,
     190             :     CVT_INREG_s16_s8    = 175,
     191             :     CVT_INREG_s32_s16   = 176,
     192             :     CVT_INREG_s32_s8    = 177,
     193             :     CVT_INREG_s64_s16   = 178,
     194             :     CVT_INREG_s64_s32   = 179,
     195             :     CVT_INREG_s64_s8    = 180,
     196             :     CVT_f16_f16 = 181,
     197             :     CVT_f16_f32 = 182,
     198             :     CVT_f16_f64 = 183,
     199             :     CVT_f16_s16 = 184,
     200             :     CVT_f16_s32 = 185,
     201             :     CVT_f16_s64 = 186,
     202             :     CVT_f16_s8  = 187,
     203             :     CVT_f16_u16 = 188,
     204             :     CVT_f16_u32 = 189,
     205             :     CVT_f16_u64 = 190,
     206             :     CVT_f16_u8  = 191,
     207             :     CVT_f32_f16 = 192,
     208             :     CVT_f32_f32 = 193,
     209             :     CVT_f32_f64 = 194,
     210             :     CVT_f32_s16 = 195,
     211             :     CVT_f32_s32 = 196,
     212             :     CVT_f32_s64 = 197,
     213             :     CVT_f32_s8  = 198,
     214             :     CVT_f32_u16 = 199,
     215             :     CVT_f32_u32 = 200,
     216             :     CVT_f32_u64 = 201,
     217             :     CVT_f32_u8  = 202,
     218             :     CVT_f64_f16 = 203,
     219             :     CVT_f64_f32 = 204,
     220             :     CVT_f64_f64 = 205,
     221             :     CVT_f64_s16 = 206,
     222             :     CVT_f64_s32 = 207,
     223             :     CVT_f64_s64 = 208,
     224             :     CVT_f64_s8  = 209,
     225             :     CVT_f64_u16 = 210,
     226             :     CVT_f64_u32 = 211,
     227             :     CVT_f64_u64 = 212,
     228             :     CVT_f64_u8  = 213,
     229             :     CVT_s16_f16 = 214,
     230             :     CVT_s16_f32 = 215,
     231             :     CVT_s16_f64 = 216,
     232             :     CVT_s16_s16 = 217,
     233             :     CVT_s16_s32 = 218,
     234             :     CVT_s16_s64 = 219,
     235             :     CVT_s16_s8  = 220,
     236             :     CVT_s16_u16 = 221,
     237             :     CVT_s16_u32 = 222,
     238             :     CVT_s16_u64 = 223,
     239             :     CVT_s16_u8  = 224,
     240             :     CVT_s32_f16 = 225,
     241             :     CVT_s32_f32 = 226,
     242             :     CVT_s32_f64 = 227,
     243             :     CVT_s32_s16 = 228,
     244             :     CVT_s32_s32 = 229,
     245             :     CVT_s32_s64 = 230,
     246             :     CVT_s32_s8  = 231,
     247             :     CVT_s32_u16 = 232,
     248             :     CVT_s32_u32 = 233,
     249             :     CVT_s32_u64 = 234,
     250             :     CVT_s32_u8  = 235,
     251             :     CVT_s64_f16 = 236,
     252             :     CVT_s64_f32 = 237,
     253             :     CVT_s64_f64 = 238,
     254             :     CVT_s64_s16 = 239,
     255             :     CVT_s64_s32 = 240,
     256             :     CVT_s64_s64 = 241,
     257             :     CVT_s64_s8  = 242,
     258             :     CVT_s64_u16 = 243,
     259             :     CVT_s64_u32 = 244,
     260             :     CVT_s64_u64 = 245,
     261             :     CVT_s64_u8  = 246,
     262             :     CVT_s8_f16  = 247,
     263             :     CVT_s8_f32  = 248,
     264             :     CVT_s8_f64  = 249,
     265             :     CVT_s8_s16  = 250,
     266             :     CVT_s8_s32  = 251,
     267             :     CVT_s8_s64  = 252,
     268             :     CVT_s8_s8   = 253,
     269             :     CVT_s8_u16  = 254,
     270             :     CVT_s8_u32  = 255,
     271             :     CVT_s8_u64  = 256,
     272             :     CVT_s8_u8   = 257,
     273             :     CVT_u16_f16 = 258,
     274             :     CVT_u16_f32 = 259,
     275             :     CVT_u16_f64 = 260,
     276             :     CVT_u16_s16 = 261,
     277             :     CVT_u16_s32 = 262,
     278             :     CVT_u16_s64 = 263,
     279             :     CVT_u16_s8  = 264,
     280             :     CVT_u16_u16 = 265,
     281             :     CVT_u16_u32 = 266,
     282             :     CVT_u16_u64 = 267,
     283             :     CVT_u16_u8  = 268,
     284             :     CVT_u32_f16 = 269,
     285             :     CVT_u32_f32 = 270,
     286             :     CVT_u32_f64 = 271,
     287             :     CVT_u32_s16 = 272,
     288             :     CVT_u32_s32 = 273,
     289             :     CVT_u32_s64 = 274,
     290             :     CVT_u32_s8  = 275,
     291             :     CVT_u32_u16 = 276,
     292             :     CVT_u32_u32 = 277,
     293             :     CVT_u32_u64 = 278,
     294             :     CVT_u32_u8  = 279,
     295             :     CVT_u64_f16 = 280,
     296             :     CVT_u64_f32 = 281,
     297             :     CVT_u64_f64 = 282,
     298             :     CVT_u64_s16 = 283,
     299             :     CVT_u64_s32 = 284,
     300             :     CVT_u64_s64 = 285,
     301             :     CVT_u64_s8  = 286,
     302             :     CVT_u64_u16 = 287,
     303             :     CVT_u64_u32 = 288,
     304             :     CVT_u64_u64 = 289,
     305             :     CVT_u64_u8  = 290,
     306             :     CVT_u8_f16  = 291,
     307             :     CVT_u8_f32  = 292,
     308             :     CVT_u8_f64  = 293,
     309             :     CVT_u8_s16  = 294,
     310             :     CVT_u8_s32  = 295,
     311             :     CVT_u8_s64  = 296,
     312             :     CVT_u8_s8   = 297,
     313             :     CVT_u8_u16  = 298,
     314             :     CVT_u8_u32  = 299,
     315             :     CVT_u8_u64  = 300,
     316             :     CVT_u8_u8   = 301,
     317             :     CallArgBeginInst    = 302,
     318             :     CallArgEndInst0     = 303,
     319             :     CallArgEndInst1     = 304,
     320             :     CallArgF32  = 305,
     321             :     CallArgF64  = 306,
     322             :     CallArgI16  = 307,
     323             :     CallArgI32  = 308,
     324             :     CallArgI32imm       = 309,
     325             :     CallArgI64  = 310,
     326             :     CallArgParam        = 311,
     327             :     CallPrintCallNoRetInst      = 312,
     328             :     CallPrintCallRetInst1       = 313,
     329             :     CallPrintCallRetInst2       = 314,
     330             :     CallPrintCallRetInst3       = 315,
     331             :     CallPrintCallRetInst4       = 316,
     332             :     CallPrintCallRetInst5       = 317,
     333             :     CallPrintCallRetInst6       = 318,
     334             :     CallPrintCallRetInst7       = 319,
     335             :     CallPrintCallRetInst8       = 320,
     336             :     CallUniPrintCallNoRetInst   = 321,
     337             :     CallUniPrintCallRetInst1    = 322,
     338             :     CallUniPrintCallRetInst2    = 323,
     339             :     CallUniPrintCallRetInst3    = 324,
     340             :     CallUniPrintCallRetInst4    = 325,
     341             :     CallUniPrintCallRetInst5    = 326,
     342             :     CallUniPrintCallRetInst6    = 327,
     343             :     CallUniPrintCallRetInst7    = 328,
     344             :     CallUniPrintCallRetInst8    = 329,
     345             :     CallVoidInst        = 330,
     346             :     CallVoidInstReg     = 331,
     347             :     CallVoidInstReg64   = 332,
     348             :     Callseq_End = 333,
     349             :     Callseq_Start       = 334,
     350             :     ConvergentCallPrintCallNoRetInst    = 335,
     351             :     ConvergentCallPrintCallRetInst1     = 336,
     352             :     ConvergentCallPrintCallRetInst2     = 337,
     353             :     ConvergentCallPrintCallRetInst3     = 338,
     354             :     ConvergentCallPrintCallRetInst4     = 339,
     355             :     ConvergentCallPrintCallRetInst5     = 340,
     356             :     ConvergentCallPrintCallRetInst6     = 341,
     357             :     ConvergentCallPrintCallRetInst7     = 342,
     358             :     ConvergentCallPrintCallRetInst8     = 343,
     359             :     ConvergentCallUniPrintCallNoRetInst = 344,
     360             :     ConvergentCallUniPrintCallRetInst1  = 345,
     361             :     ConvergentCallUniPrintCallRetInst2  = 346,
     362             :     ConvergentCallUniPrintCallRetInst3  = 347,
     363             :     ConvergentCallUniPrintCallRetInst4  = 348,
     364             :     ConvergentCallUniPrintCallRetInst5  = 349,
     365             :     ConvergentCallUniPrintCallRetInst6  = 350,
     366             :     ConvergentCallUniPrintCallRetInst7  = 351,
     367             :     ConvergentCallUniPrintCallRetInst8  = 352,
     368             :     DeclareParamInst    = 353,
     369             :     DeclareRetMemInst   = 354,
     370             :     DeclareRetRegInst   = 355,
     371             :     DeclareRetScalarInst        = 356,
     372             :     DeclareScalarParamInst      = 357,
     373             :     DeclareScalarRegInst        = 358,
     374             :     F16x2toF16_0        = 359,
     375             :     F16x2toF16_1        = 360,
     376             :     F64toV2F32  = 361,
     377             :     FABSf32     = 362,
     378             :     FABSf32_ftz = 363,
     379             :     FABSf64     = 364,
     380             :     FADD_rnf16rr        = 365,
     381             :     FADD_rnf16rr_ftz    = 366,
     382             :     FADD_rnf16x2rr      = 367,
     383             :     FADD_rnf16x2rr_ftz  = 368,
     384             :     FADD_rnf32ri        = 369,
     385             :     FADD_rnf32ri_ftz    = 370,
     386             :     FADD_rnf32rr        = 371,
     387             :     FADD_rnf32rr_ftz    = 372,
     388             :     FADD_rnf64ri        = 373,
     389             :     FADD_rnf64rr        = 374,
     390             :     FADDf16rr   = 375,
     391             :     FADDf16rr_ftz       = 376,
     392             :     FADDf16x2rr = 377,
     393             :     FADDf16x2rr_ftz     = 378,
     394             :     FADDf32ri   = 379,
     395             :     FADDf32ri_ftz       = 380,
     396             :     FADDf32rr   = 381,
     397             :     FADDf32rr_ftz       = 382,
     398             :     FADDf64ri   = 383,
     399             :     FADDf64rr   = 384,
     400             :     FDIV321r    = 385,
     401             :     FDIV321r_approx     = 386,
     402             :     FDIV321r_approx_ftz = 387,
     403             :     FDIV321r_ftz        = 388,
     404             :     FDIV321r_prec       = 389,
     405             :     FDIV321r_prec_ftz   = 390,
     406             :     FDIV32approxri      = 391,
     407             :     FDIV32approxri_ftz  = 392,
     408             :     FDIV32approxrr      = 393,
     409             :     FDIV32approxrr_ftz  = 394,
     410             :     FDIV32ri    = 395,
     411             :     FDIV32ri_ftz        = 396,
     412             :     FDIV32ri_prec       = 397,
     413             :     FDIV32ri_prec_ftz   = 398,
     414             :     FDIV32rr    = 399,
     415             :     FDIV32rr_ftz        = 400,
     416             :     FDIV32rr_prec       = 401,
     417             :     FDIV32rr_prec_ftz   = 402,
     418             :     FDIV641r    = 403,
     419             :     FDIV64ri    = 404,
     420             :     FDIV64rr    = 405,
     421             :     FMA16_ftzrrr        = 406,
     422             :     FMA16rrr    = 407,
     423             :     FMA16x2_ftzrrr      = 408,
     424             :     FMA16x2rrr  = 409,
     425             :     FMA32_ftzrii        = 410,
     426             :     FMA32_ftzrir        = 411,
     427             :     FMA32_ftzrri        = 412,
     428             :     FMA32_ftzrrr        = 413,
     429             :     FMA32rii    = 414,
     430             :     FMA32rir    = 415,
     431             :     FMA32rri    = 416,
     432             :     FMA32rrr    = 417,
     433             :     FMA64rii    = 418,
     434             :     FMA64rir    = 419,
     435             :     FMA64rri    = 420,
     436             :     FMA64rrr    = 421,
     437             :     FMAXf32ri   = 422,
     438             :     FMAXf32ri_ftz       = 423,
     439             :     FMAXf32rr   = 424,
     440             :     FMAXf32rr_ftz       = 425,
     441             :     FMAXf64ri   = 426,
     442             :     FMAXf64rr   = 427,
     443             :     FMINf32ri   = 428,
     444             :     FMINf32ri_ftz       = 429,
     445             :     FMINf32rr   = 430,
     446             :     FMINf32rr_ftz       = 431,
     447             :     FMINf64ri   = 432,
     448             :     FMINf64rr   = 433,
     449             :     FMOV16rr    = 434,
     450             :     FMOV32ri    = 435,
     451             :     FMOV32rr    = 436,
     452             :     FMOV64ri    = 437,
     453             :     FMOV64rr    = 438,
     454             :     FMUL_rnf16rr        = 439,
     455             :     FMUL_rnf16rr_ftz    = 440,
     456             :     FMUL_rnf16x2rr      = 441,
     457             :     FMUL_rnf16x2rr_ftz  = 442,
     458             :     FMUL_rnf32ri        = 443,
     459             :     FMUL_rnf32ri_ftz    = 444,
     460             :     FMUL_rnf32rr        = 445,
     461             :     FMUL_rnf32rr_ftz    = 446,
     462             :     FMUL_rnf64ri        = 447,
     463             :     FMUL_rnf64rr        = 448,
     464             :     FMULf16rr   = 449,
     465             :     FMULf16rr_ftz       = 450,
     466             :     FMULf16x2rr = 451,
     467             :     FMULf16x2rr_ftz     = 452,
     468             :     FMULf32ri   = 453,
     469             :     FMULf32ri_ftz       = 454,
     470             :     FMULf32rr   = 455,
     471             :     FMULf32rr_ftz       = 456,
     472             :     FMULf64ri   = 457,
     473             :     FMULf64rr   = 458,
     474             :     FNEGf32     = 459,
     475             :     FNEGf32_ftz = 460,
     476             :     FNEGf64     = 461,
     477             :     FSQRTf32    = 462,
     478             :     FSQRTf32_ftz        = 463,
     479             :     FSQRTf64    = 464,
     480             :     FSUB_rnf16rr        = 465,
     481             :     FSUB_rnf16rr_ftz    = 466,
     482             :     FSUB_rnf16x2rr      = 467,
     483             :     FSUB_rnf16x2rr_ftz  = 468,
     484             :     FSUB_rnf32ri        = 469,
     485             :     FSUB_rnf32ri_ftz    = 470,
     486             :     FSUB_rnf32rr        = 471,
     487             :     FSUB_rnf32rr_ftz    = 472,
     488             :     FSUB_rnf64ri        = 473,
     489             :     FSUB_rnf64rr        = 474,
     490             :     FSUBf16rr   = 475,
     491             :     FSUBf16rr_ftz       = 476,
     492             :     FSUBf16x2rr = 477,
     493             :     FSUBf16x2rr_ftz     = 478,
     494             :     FSUBf32ri   = 479,
     495             :     FSUBf32ri_ftz       = 480,
     496             :     FSUBf32rr   = 481,
     497             :     FSUBf32rr_ftz       = 482,
     498             :     FSUBf64ri   = 483,
     499             :     FSUBf64rr   = 484,
     500             :     FUNSHFLCLAMP        = 485,
     501             :     FUNSHFRCLAMP        = 486,
     502             :     GET_HI_INT64        = 487,
     503             :     GET_LO_INT64        = 488,
     504             :     GOTO        = 489,
     505             :     I32toV2I16  = 490,
     506             :     I64toV2I32  = 491,
     507             :     I64toV4I16  = 492,
     508             :     IMOV16ri    = 493,
     509             :     IMOV16rr    = 494,
     510             :     IMOV1ri     = 495,
     511             :     IMOV1rr     = 496,
     512             :     IMOV32ri    = 497,
     513             :     IMOV32rr    = 498,
     514             :     IMOV64i     = 499,
     515             :     IMOV64rr    = 500,
     516             :     INEG16      = 501,
     517             :     INEG32      = 502,
     518             :     INEG64      = 503,
     519             :     INT_BARRIER = 504,
     520             :     INT_BARRIER0        = 505,
     521             :     INT_BARRIER0_AND    = 506,
     522             :     INT_BARRIER0_OR     = 507,
     523             :     INT_BARRIER0_POPC   = 508,
     524             :     INT_BARRIERN        = 509,
     525             :     INT_BARRIER_SYNC_CNT_II     = 510,
     526             :     INT_BARRIER_SYNC_CNT_IR     = 511,
     527             :     INT_BARRIER_SYNC_CNT_RI     = 512,
     528             :     INT_BARRIER_SYNC_CNT_RR     = 513,
     529             :     INT_BARRIER_SYNC_I  = 514,
     530             :     INT_BARRIER_SYNC_R  = 515,
     531             :     INT_BAR_SYNC        = 516,
     532             :     INT_BAR_WARP_SYNC_I = 517,
     533             :     INT_BAR_WARP_SYNC_R = 518,
     534             :     INT_FNS_iii = 519,
     535             :     INT_FNS_iir = 520,
     536             :     INT_FNS_iri = 521,
     537             :     INT_FNS_irr = 522,
     538             :     INT_FNS_rii = 523,
     539             :     INT_FNS_rir = 524,
     540             :     INT_FNS_rri = 525,
     541             :     INT_FNS_rrr = 526,
     542             :     INT_MEMBAR_CTA      = 527,
     543             :     INT_MEMBAR_GL       = 528,
     544             :     INT_MEMBAR_SYS      = 529,
     545             :     INT_NVVM_ADD_RM_D   = 530,
     546             :     INT_NVVM_ADD_RM_F   = 531,
     547             :     INT_NVVM_ADD_RM_FTZ_F       = 532,
     548             :     INT_NVVM_ADD_RN_D   = 533,
     549             :     INT_NVVM_ADD_RN_F   = 534,
     550             :     INT_NVVM_ADD_RN_FTZ_F       = 535,
     551             :     INT_NVVM_ADD_RP_D   = 536,
     552             :     INT_NVVM_ADD_RP_F   = 537,
     553             :     INT_NVVM_ADD_RP_FTZ_F       = 538,
     554             :     INT_NVVM_ADD_RZ_D   = 539,
     555             :     INT_NVVM_ADD_RZ_F   = 540,
     556             :     INT_NVVM_ADD_RZ_FTZ_F       = 541,
     557             :     INT_NVVM_BITCAST_D2LL       = 542,
     558             :     INT_NVVM_BITCAST_F2I        = 543,
     559             :     INT_NVVM_BITCAST_I2F        = 544,
     560             :     INT_NVVM_BITCAST_LL2D       = 545,
     561             :     INT_NVVM_COMPILER_ERROR_32  = 546,
     562             :     INT_NVVM_COMPILER_ERROR_64  = 547,
     563             :     INT_NVVM_COMPILER_WARN_32   = 548,
     564             :     INT_NVVM_COMPILER_WARN_64   = 549,
     565             :     INT_NVVM_COS_APPROX_F       = 550,
     566             :     INT_NVVM_COS_APPROX_FTZ_F   = 551,
     567             :     INT_NVVM_D2I_HI     = 552,
     568             :     INT_NVVM_D2I_LO     = 553,
     569             :     INT_NVVM_DIV_APPROX_F       = 554,
     570             :     INT_NVVM_DIV_APPROX_FTZ_F   = 555,
     571             :     INT_NVVM_DIV_RM_D   = 556,
     572             :     INT_NVVM_DIV_RM_F   = 557,
     573             :     INT_NVVM_DIV_RM_FTZ_F       = 558,
     574             :     INT_NVVM_DIV_RN_D   = 559,
     575             :     INT_NVVM_DIV_RN_F   = 560,
     576             :     INT_NVVM_DIV_RN_FTZ_F       = 561,
     577             :     INT_NVVM_DIV_RP_D   = 562,
     578             :     INT_NVVM_DIV_RP_F   = 563,
     579             :     INT_NVVM_DIV_RP_FTZ_F       = 564,
     580             :     INT_NVVM_DIV_RZ_D   = 565,
     581             :     INT_NVVM_DIV_RZ_F   = 566,
     582             :     INT_NVVM_DIV_RZ_FTZ_F       = 567,
     583             :     INT_NVVM_EX2_APPROX_D       = 568,
     584             :     INT_NVVM_EX2_APPROX_F       = 569,
     585             :     INT_NVVM_EX2_APPROX_FTZ_F   = 570,
     586             :     INT_NVVM_FABS_D     = 571,
     587             :     INT_NVVM_FABS_F     = 572,
     588             :     INT_NVVM_FABS_FTZ_F = 573,
     589             :     INT_NVVM_FMAX_D     = 574,
     590             :     INT_NVVM_FMAX_F     = 575,
     591             :     INT_NVVM_FMAX_FTZ_F = 576,
     592             :     INT_NVVM_FMA_RM_D   = 577,
     593             :     INT_NVVM_FMA_RM_F   = 578,
     594             :     INT_NVVM_FMA_RM_FTZ_F       = 579,
     595             :     INT_NVVM_FMA_RN_D   = 580,
     596             :     INT_NVVM_FMA_RN_F   = 581,
     597             :     INT_NVVM_FMA_RN_FTZ_F       = 582,
     598             :     INT_NVVM_FMA_RP_D   = 583,
     599             :     INT_NVVM_FMA_RP_F   = 584,
     600             :     INT_NVVM_FMA_RP_FTZ_F       = 585,
     601             :     INT_NVVM_FMA_RZ_D   = 586,
     602             :     INT_NVVM_FMA_RZ_F   = 587,
     603             :     INT_NVVM_FMA_RZ_FTZ_F       = 588,
     604             :     INT_NVVM_FMIN_D     = 589,
     605             :     INT_NVVM_FMIN_F     = 590,
     606             :     INT_NVVM_FMIN_FTZ_F = 591,
     607             :     INT_NVVM_LG2_APPROX_D       = 592,
     608             :     INT_NVVM_LG2_APPROX_F       = 593,
     609             :     INT_NVVM_LG2_APPROX_FTZ_F   = 594,
     610             :     INT_NVVM_LOHI_I2D   = 595,
     611             :     INT_NVVM_MUL24_I    = 596,
     612             :     INT_NVVM_MUL24_UI   = 597,
     613             :     INT_NVVM_MULHI_I    = 598,
     614             :     INT_NVVM_MULHI_LL   = 599,
     615             :     INT_NVVM_MULHI_UI   = 600,
     616             :     INT_NVVM_MULHI_ULL  = 601,
     617             :     INT_NVVM_MUL_RM_D   = 602,
     618             :     INT_NVVM_MUL_RM_F   = 603,
     619             :     INT_NVVM_MUL_RM_FTZ_F       = 604,
     620             :     INT_NVVM_MUL_RN_D   = 605,
     621             :     INT_NVVM_MUL_RN_F   = 606,
     622             :     INT_NVVM_MUL_RN_FTZ_F       = 607,
     623             :     INT_NVVM_MUL_RP_D   = 608,
     624             :     INT_NVVM_MUL_RP_F   = 609,
     625             :     INT_NVVM_MUL_RP_FTZ_F       = 610,
     626             :     INT_NVVM_MUL_RZ_D   = 611,
     627             :     INT_NVVM_MUL_RZ_F   = 612,
     628             :     INT_NVVM_MUL_RZ_FTZ_F       = 613,
     629             :     INT_NVVM_PRMT       = 614,
     630             :     INT_NVVM_RCP_APPROX_FTZ_D   = 615,
     631             :     INT_NVVM_RCP_RM_D   = 616,
     632             :     INT_NVVM_RCP_RM_F   = 617,
     633             :     INT_NVVM_RCP_RM_FTZ_F       = 618,
     634             :     INT_NVVM_RCP_RN_D   = 619,
     635             :     INT_NVVM_RCP_RN_F   = 620,
     636             :     INT_NVVM_RCP_RN_FTZ_F       = 621,
     637             :     INT_NVVM_RCP_RP_D   = 622,
     638             :     INT_NVVM_RCP_RP_F   = 623,
     639             :     INT_NVVM_RCP_RP_FTZ_F       = 624,
     640             :     INT_NVVM_RCP_RZ_D   = 625,
     641             :     INT_NVVM_RCP_RZ_F   = 626,
     642             :     INT_NVVM_RCP_RZ_FTZ_F       = 627,
     643             :     INT_NVVM_RSQRT_APPROX_D     = 628,
     644             :     INT_NVVM_RSQRT_APPROX_F     = 629,
     645             :     INT_NVVM_RSQRT_APPROX_FTZ_F = 630,
     646             :     INT_NVVM_SAD_I      = 631,
     647             :     INT_NVVM_SAD_UI     = 632,
     648             :     INT_NVVM_SIN_APPROX_F       = 633,
     649             :     INT_NVVM_SIN_APPROX_FTZ_F   = 634,
     650             :     INT_NVVM_SQRT_APPROX_F      = 635,
     651             :     INT_NVVM_SQRT_APPROX_FTZ_F  = 636,
     652             :     INT_NVVM_SQRT_RM_D  = 637,
     653             :     INT_NVVM_SQRT_RM_F  = 638,
     654             :     INT_NVVM_SQRT_RM_FTZ_F      = 639,
     655             :     INT_NVVM_SQRT_RN_D  = 640,
     656             :     INT_NVVM_SQRT_RN_F  = 641,
     657             :     INT_NVVM_SQRT_RN_FTZ_F      = 642,
     658             :     INT_NVVM_SQRT_RP_D  = 643,
     659             :     INT_NVVM_SQRT_RP_F  = 644,
     660             :     INT_NVVM_SQRT_RP_FTZ_F      = 645,
     661             :     INT_NVVM_SQRT_RZ_D  = 646,
     662             :     INT_NVVM_SQRT_RZ_F  = 647,
     663             :     INT_NVVM_SQRT_RZ_FTZ_F      = 648,
     664             :     INT_PTX_ATOM_ADD_GEN_32_USE_Gp32imm = 649,
     665             :     INT_PTX_ATOM_ADD_GEN_32_USE_Gp32reg = 650,
     666             :     INT_PTX_ATOM_ADD_GEN_32_USE_Gp64imm = 651,
     667             :     INT_PTX_ATOM_ADD_GEN_32_USE_Gp64reg = 652,
     668             :     INT_PTX_ATOM_ADD_GEN_32p32imm       = 653,
     669             :     INT_PTX_ATOM_ADD_GEN_32p32reg       = 654,
     670             :     INT_PTX_ATOM_ADD_GEN_32p64imm       = 655,
     671             :     INT_PTX_ATOM_ADD_GEN_32p64reg       = 656,
     672             :     INT_PTX_ATOM_ADD_GEN_64_USE_Gp32imm = 657,
     673             :     INT_PTX_ATOM_ADD_GEN_64_USE_Gp32reg = 658,
     674             :     INT_PTX_ATOM_ADD_GEN_64_USE_Gp64imm = 659,
     675             :     INT_PTX_ATOM_ADD_GEN_64_USE_Gp64reg = 660,
     676             :     INT_PTX_ATOM_ADD_GEN_64p32imm       = 661,
     677             :     INT_PTX_ATOM_ADD_GEN_64p32reg       = 662,
     678             :     INT_PTX_ATOM_ADD_GEN_64p64imm       = 663,
     679             :     INT_PTX_ATOM_ADD_GEN_64p64reg       = 664,
     680             :     INT_PTX_ATOM_ADD_GEN_F32p32imm      = 665,
     681             :     INT_PTX_ATOM_ADD_GEN_F32p32reg      = 666,
     682             :     INT_PTX_ATOM_ADD_GEN_F32p64imm      = 667,
     683             :     INT_PTX_ATOM_ADD_GEN_F32p64reg      = 668,
     684             :     INT_PTX_ATOM_ADD_GEN_F64p32imm      = 669,
     685             :     INT_PTX_ATOM_ADD_GEN_F64p32reg      = 670,
     686             :     INT_PTX_ATOM_ADD_GEN_F64p64imm      = 671,
     687             :     INT_PTX_ATOM_ADD_GEN_F64p64reg      = 672,
     688             :     INT_PTX_ATOM_ADD_G_32p32imm = 673,
     689             :     INT_PTX_ATOM_ADD_G_32p32reg = 674,
     690             :     INT_PTX_ATOM_ADD_G_32p64imm = 675,
     691             :     INT_PTX_ATOM_ADD_G_32p64reg = 676,
     692             :     INT_PTX_ATOM_ADD_G_64p32imm = 677,
     693             :     INT_PTX_ATOM_ADD_G_64p32reg = 678,
     694             :     INT_PTX_ATOM_ADD_G_64p64imm = 679,
     695             :     INT_PTX_ATOM_ADD_G_64p64reg = 680,
     696             :     INT_PTX_ATOM_ADD_G_F32p32imm        = 681,
     697             :     INT_PTX_ATOM_ADD_G_F32p32reg        = 682,
     698             :     INT_PTX_ATOM_ADD_G_F32p64imm        = 683,
     699             :     INT_PTX_ATOM_ADD_G_F32p64reg        = 684,
     700             :     INT_PTX_ATOM_ADD_G_F64p32imm        = 685,
     701             :     INT_PTX_ATOM_ADD_G_F64p32reg        = 686,
     702             :     INT_PTX_ATOM_ADD_G_F64p64imm        = 687,
     703             :     INT_PTX_ATOM_ADD_G_F64p64reg        = 688,
     704             :     INT_PTX_ATOM_ADD_S_32p32imm = 689,
     705             :     INT_PTX_ATOM_ADD_S_32p32reg = 690,
     706             :     INT_PTX_ATOM_ADD_S_32p64imm = 691,
     707             :     INT_PTX_ATOM_ADD_S_32p64reg = 692,
     708             :     INT_PTX_ATOM_ADD_S_64p32imm = 693,
     709             :     INT_PTX_ATOM_ADD_S_64p32reg = 694,
     710             :     INT_PTX_ATOM_ADD_S_64p64imm = 695,
     711             :     INT_PTX_ATOM_ADD_S_64p64reg = 696,
     712             :     INT_PTX_ATOM_ADD_S_F32p32imm        = 697,
     713             :     INT_PTX_ATOM_ADD_S_F32p32reg        = 698,
     714             :     INT_PTX_ATOM_ADD_S_F32p64imm        = 699,
     715             :     INT_PTX_ATOM_ADD_S_F32p64reg        = 700,
     716             :     INT_PTX_ATOM_ADD_S_F64p32imm        = 701,
     717             :     INT_PTX_ATOM_ADD_S_F64p32reg        = 702,
     718             :     INT_PTX_ATOM_ADD_S_F64p64imm        = 703,
     719             :     INT_PTX_ATOM_ADD_S_F64p64reg        = 704,
     720             :     INT_PTX_ATOM_AND_GEN_32_USE_Gp32imm = 705,
     721             :     INT_PTX_ATOM_AND_GEN_32_USE_Gp32reg = 706,
     722             :     INT_PTX_ATOM_AND_GEN_32_USE_Gp64imm = 707,
     723             :     INT_PTX_ATOM_AND_GEN_32_USE_Gp64reg = 708,
     724             :     INT_PTX_ATOM_AND_GEN_32p32imm       = 709,
     725             :     INT_PTX_ATOM_AND_GEN_32p32reg       = 710,
     726             :     INT_PTX_ATOM_AND_GEN_32p64imm       = 711,
     727             :     INT_PTX_ATOM_AND_GEN_32p64reg       = 712,
     728             :     INT_PTX_ATOM_AND_GEN_64_USE_Gp32imm = 713,
     729             :     INT_PTX_ATOM_AND_GEN_64_USE_Gp32reg = 714,
     730             :     INT_PTX_ATOM_AND_GEN_64_USE_Gp64imm = 715,
     731             :     INT_PTX_ATOM_AND_GEN_64_USE_Gp64reg = 716,
     732             :     INT_PTX_ATOM_AND_GEN_64p32imm       = 717,
     733             :     INT_PTX_ATOM_AND_GEN_64p32reg       = 718,
     734             :     INT_PTX_ATOM_AND_GEN_64p64imm       = 719,
     735             :     INT_PTX_ATOM_AND_GEN_64p64reg       = 720,
     736             :     INT_PTX_ATOM_AND_G_32p32imm = 721,
     737             :     INT_PTX_ATOM_AND_G_32p32reg = 722,
     738             :     INT_PTX_ATOM_AND_G_32p64imm = 723,
     739             :     INT_PTX_ATOM_AND_G_32p64reg = 724,
     740             :     INT_PTX_ATOM_AND_G_64p32imm = 725,
     741             :     INT_PTX_ATOM_AND_G_64p32reg = 726,
     742             :     INT_PTX_ATOM_AND_G_64p64imm = 727,
     743             :     INT_PTX_ATOM_AND_G_64p64reg = 728,
     744             :     INT_PTX_ATOM_AND_S_32p32imm = 729,
     745             :     INT_PTX_ATOM_AND_S_32p32reg = 730,
     746             :     INT_PTX_ATOM_AND_S_32p64imm = 731,
     747             :     INT_PTX_ATOM_AND_S_32p64reg = 732,
     748             :     INT_PTX_ATOM_AND_S_64p32imm = 733,
     749             :     INT_PTX_ATOM_AND_S_64p32reg = 734,
     750             :     INT_PTX_ATOM_AND_S_64p64imm = 735,
     751             :     INT_PTX_ATOM_AND_S_64p64reg = 736,
     752             :     INT_PTX_ATOM_CAS_GEN_32_USE_Gp32imm1        = 737,
     753             :     INT_PTX_ATOM_CAS_GEN_32_USE_Gp32imm2        = 738,
     754             :     INT_PTX_ATOM_CAS_GEN_32_USE_Gp32imm3        = 739,
     755             :     INT_PTX_ATOM_CAS_GEN_32_USE_Gp32reg = 740,
     756             :     INT_PTX_ATOM_CAS_GEN_32_USE_Gp64imm1        = 741,
     757             :     INT_PTX_ATOM_CAS_GEN_32_USE_Gp64imm2        = 742,
     758             :     INT_PTX_ATOM_CAS_GEN_32_USE_Gp64imm3        = 743,
     759             :     INT_PTX_ATOM_CAS_GEN_32_USE_Gp64reg = 744,
     760             :     INT_PTX_ATOM_CAS_GEN_32p32imm1      = 745,
     761             :     INT_PTX_ATOM_CAS_GEN_32p32imm2      = 746,
     762             :     INT_PTX_ATOM_CAS_GEN_32p32imm3      = 747,
     763             :     INT_PTX_ATOM_CAS_GEN_32p32reg       = 748,
     764             :     INT_PTX_ATOM_CAS_GEN_32p64imm1      = 749,
     765             :     INT_PTX_ATOM_CAS_GEN_32p64imm2      = 750,
     766             :     INT_PTX_ATOM_CAS_GEN_32p64imm3      = 751,
     767             :     INT_PTX_ATOM_CAS_GEN_32p64reg       = 752,
     768             :     INT_PTX_ATOM_CAS_GEN_64_USE_Gp32imm1        = 753,
     769             :     INT_PTX_ATOM_CAS_GEN_64_USE_Gp32imm2        = 754,
     770             :     INT_PTX_ATOM_CAS_GEN_64_USE_Gp32imm3        = 755,
     771             :     INT_PTX_ATOM_CAS_GEN_64_USE_Gp32reg = 756,
     772             :     INT_PTX_ATOM_CAS_GEN_64_USE_Gp64imm1        = 757,
     773             :     INT_PTX_ATOM_CAS_GEN_64_USE_Gp64imm2        = 758,
     774             :     INT_PTX_ATOM_CAS_GEN_64_USE_Gp64imm3        = 759,
     775             :     INT_PTX_ATOM_CAS_GEN_64_USE_Gp64reg = 760,
     776             :     INT_PTX_ATOM_CAS_GEN_64p32imm1      = 761,
     777             :     INT_PTX_ATOM_CAS_GEN_64p32imm2      = 762,
     778             :     INT_PTX_ATOM_CAS_GEN_64p32imm3      = 763,
     779             :     INT_PTX_ATOM_CAS_GEN_64p32reg       = 764,
     780             :     INT_PTX_ATOM_CAS_GEN_64p64imm1      = 765,
     781             :     INT_PTX_ATOM_CAS_GEN_64p64imm2      = 766,
     782             :     INT_PTX_ATOM_CAS_GEN_64p64imm3      = 767,
     783             :     INT_PTX_ATOM_CAS_GEN_64p64reg       = 768,
     784             :     INT_PTX_ATOM_CAS_G_32p32imm1        = 769,
     785             :     INT_PTX_ATOM_CAS_G_32p32imm2        = 770,
     786             :     INT_PTX_ATOM_CAS_G_32p32imm3        = 771,
     787             :     INT_PTX_ATOM_CAS_G_32p32reg = 772,
     788             :     INT_PTX_ATOM_CAS_G_32p64imm1        = 773,
     789             :     INT_PTX_ATOM_CAS_G_32p64imm2        = 774,
     790             :     INT_PTX_ATOM_CAS_G_32p64imm3        = 775,
     791             :     INT_PTX_ATOM_CAS_G_32p64reg = 776,
     792             :     INT_PTX_ATOM_CAS_G_64p32imm1        = 777,
     793             :     INT_PTX_ATOM_CAS_G_64p32imm2        = 778,
     794             :     INT_PTX_ATOM_CAS_G_64p32imm3        = 779,
     795             :     INT_PTX_ATOM_CAS_G_64p32reg = 780,
     796             :     INT_PTX_ATOM_CAS_G_64p64imm1        = 781,
     797             :     INT_PTX_ATOM_CAS_G_64p64imm2        = 782,
     798             :     INT_PTX_ATOM_CAS_G_64p64imm3        = 783,
     799             :     INT_PTX_ATOM_CAS_G_64p64reg = 784,
     800             :     INT_PTX_ATOM_CAS_S_32p32imm1        = 785,
     801             :     INT_PTX_ATOM_CAS_S_32p32imm2        = 786,
     802             :     INT_PTX_ATOM_CAS_S_32p32imm3        = 787,
     803             :     INT_PTX_ATOM_CAS_S_32p32reg = 788,
     804             :     INT_PTX_ATOM_CAS_S_32p64imm1        = 789,
     805             :     INT_PTX_ATOM_CAS_S_32p64imm2        = 790,
     806             :     INT_PTX_ATOM_CAS_S_32p64imm3        = 791,
     807             :     INT_PTX_ATOM_CAS_S_32p64reg = 792,
     808             :     INT_PTX_ATOM_CAS_S_64p32imm1        = 793,
     809             :     INT_PTX_ATOM_CAS_S_64p32imm2        = 794,
     810             :     INT_PTX_ATOM_CAS_S_64p32imm3        = 795,
     811             :     INT_PTX_ATOM_CAS_S_64p32reg = 796,
     812             :     INT_PTX_ATOM_CAS_S_64p64imm1        = 797,
     813             :     INT_PTX_ATOM_CAS_S_64p64imm2        = 798,
     814             :     INT_PTX_ATOM_CAS_S_64p64imm3        = 799,
     815             :     INT_PTX_ATOM_CAS_S_64p64reg = 800,
     816             :     INT_PTX_ATOM_DEC_GEN_32_USE_Gp32imm = 801,
     817             :     INT_PTX_ATOM_DEC_GEN_32_USE_Gp32reg = 802,
     818             :     INT_PTX_ATOM_DEC_GEN_32_USE_Gp64imm = 803,
     819             :     INT_PTX_ATOM_DEC_GEN_32_USE_Gp64reg = 804,
     820             :     INT_PTX_ATOM_DEC_GEN_32p32imm       = 805,
     821             :     INT_PTX_ATOM_DEC_GEN_32p32reg       = 806,
     822             :     INT_PTX_ATOM_DEC_GEN_32p64imm       = 807,
     823             :     INT_PTX_ATOM_DEC_GEN_32p64reg       = 808,
     824             :     INT_PTX_ATOM_DEC_G_32p32imm = 809,
     825             :     INT_PTX_ATOM_DEC_G_32p32reg = 810,
     826             :     INT_PTX_ATOM_DEC_G_32p64imm = 811,
     827             :     INT_PTX_ATOM_DEC_G_32p64reg = 812,
     828             :     INT_PTX_ATOM_DEC_S_32p32imm = 813,
     829             :     INT_PTX_ATOM_DEC_S_32p32reg = 814,
     830             :     INT_PTX_ATOM_DEC_S_32p64imm = 815,
     831             :     INT_PTX_ATOM_DEC_S_32p64reg = 816,
     832             :     INT_PTX_ATOM_INC_GEN_32_USE_Gp32imm = 817,
     833             :     INT_PTX_ATOM_INC_GEN_32_USE_Gp32reg = 818,
     834             :     INT_PTX_ATOM_INC_GEN_32_USE_Gp64imm = 819,
     835             :     INT_PTX_ATOM_INC_GEN_32_USE_Gp64reg = 820,
     836             :     INT_PTX_ATOM_INC_GEN_32p32imm       = 821,
     837             :     INT_PTX_ATOM_INC_GEN_32p32reg       = 822,
     838             :     INT_PTX_ATOM_INC_GEN_32p64imm       = 823,
     839             :     INT_PTX_ATOM_INC_GEN_32p64reg       = 824,
     840             :     INT_PTX_ATOM_INC_G_32p32imm = 825,
     841             :     INT_PTX_ATOM_INC_G_32p32reg = 826,
     842             :     INT_PTX_ATOM_INC_G_32p64imm = 827,
     843             :     INT_PTX_ATOM_INC_G_32p64reg = 828,
     844             :     INT_PTX_ATOM_INC_S_32p32imm = 829,
     845             :     INT_PTX_ATOM_INC_S_32p32reg = 830,
     846             :     INT_PTX_ATOM_INC_S_32p64imm = 831,
     847             :     INT_PTX_ATOM_INC_S_32p64reg = 832,
     848             :     INT_PTX_ATOM_LOAD_MAX_GEN_32_USE_Gp32imm    = 833,
     849             :     INT_PTX_ATOM_LOAD_MAX_GEN_32_USE_Gp32reg    = 834,
     850             :     INT_PTX_ATOM_LOAD_MAX_GEN_32_USE_Gp64imm    = 835,
     851             :     INT_PTX_ATOM_LOAD_MAX_GEN_32_USE_Gp64reg    = 836,
     852             :     INT_PTX_ATOM_LOAD_MAX_GEN_32p32imm  = 837,
     853             :     INT_PTX_ATOM_LOAD_MAX_GEN_32p32reg  = 838,
     854             :     INT_PTX_ATOM_LOAD_MAX_GEN_32p64imm  = 839,
     855             :     INT_PTX_ATOM_LOAD_MAX_GEN_32p64reg  = 840,
     856             :     INT_PTX_ATOM_LOAD_MAX_GEN_64_USE_Gp32imm    = 841,
     857             :     INT_PTX_ATOM_LOAD_MAX_GEN_64_USE_Gp32reg    = 842,
     858             :     INT_PTX_ATOM_LOAD_MAX_GEN_64_USE_Gp64imm    = 843,
     859             :     INT_PTX_ATOM_LOAD_MAX_GEN_64_USE_Gp64reg    = 844,
     860             :     INT_PTX_ATOM_LOAD_MAX_GEN_64p32imm  = 845,
     861             :     INT_PTX_ATOM_LOAD_MAX_GEN_64p32reg  = 846,
     862             :     INT_PTX_ATOM_LOAD_MAX_GEN_64p64imm  = 847,
     863             :     INT_PTX_ATOM_LOAD_MAX_GEN_64p64reg  = 848,
     864             :     INT_PTX_ATOM_LOAD_MAX_G_32p32imm    = 849,
     865             :     INT_PTX_ATOM_LOAD_MAX_G_32p32reg    = 850,
     866             :     INT_PTX_ATOM_LOAD_MAX_G_32p64imm    = 851,
     867             :     INT_PTX_ATOM_LOAD_MAX_G_32p64reg    = 852,
     868             :     INT_PTX_ATOM_LOAD_MAX_G_64p32imm    = 853,
     869             :     INT_PTX_ATOM_LOAD_MAX_G_64p32reg    = 854,
     870             :     INT_PTX_ATOM_LOAD_MAX_G_64p64imm    = 855,
     871             :     INT_PTX_ATOM_LOAD_MAX_G_64p64reg    = 856,
     872             :     INT_PTX_ATOM_LOAD_MAX_S_32p32imm    = 857,
     873             :     INT_PTX_ATOM_LOAD_MAX_S_32p32reg    = 858,
     874             :     INT_PTX_ATOM_LOAD_MAX_S_32p64imm    = 859,
     875             :     INT_PTX_ATOM_LOAD_MAX_S_32p64reg    = 860,
     876             :     INT_PTX_ATOM_LOAD_MAX_S_64p32imm    = 861,
     877             :     INT_PTX_ATOM_LOAD_MAX_S_64p32reg    = 862,
     878             :     INT_PTX_ATOM_LOAD_MAX_S_64p64imm    = 863,
     879             :     INT_PTX_ATOM_LOAD_MAX_S_64p64reg    = 864,
     880             :     INT_PTX_ATOM_LOAD_MIN_GEN_32_USE_Gp32imm    = 865,
     881             :     INT_PTX_ATOM_LOAD_MIN_GEN_32_USE_Gp32reg    = 866,
     882             :     INT_PTX_ATOM_LOAD_MIN_GEN_32_USE_Gp64imm    = 867,
     883             :     INT_PTX_ATOM_LOAD_MIN_GEN_32_USE_Gp64reg    = 868,
     884             :     INT_PTX_ATOM_LOAD_MIN_GEN_32p32imm  = 869,
     885             :     INT_PTX_ATOM_LOAD_MIN_GEN_32p32reg  = 870,
     886             :     INT_PTX_ATOM_LOAD_MIN_GEN_32p64imm  = 871,
     887             :     INT_PTX_ATOM_LOAD_MIN_GEN_32p64reg  = 872,
     888             :     INT_PTX_ATOM_LOAD_MIN_GEN_64_USE_Gp32imm    = 873,
     889             :     INT_PTX_ATOM_LOAD_MIN_GEN_64_USE_Gp32reg    = 874,
     890             :     INT_PTX_ATOM_LOAD_MIN_GEN_64_USE_Gp64imm    = 875,
     891             :     INT_PTX_ATOM_LOAD_MIN_GEN_64_USE_Gp64reg    = 876,
     892             :     INT_PTX_ATOM_LOAD_MIN_GEN_64p32imm  = 877,
     893             :     INT_PTX_ATOM_LOAD_MIN_GEN_64p32reg  = 878,
     894             :     INT_PTX_ATOM_LOAD_MIN_GEN_64p64imm  = 879,
     895             :     INT_PTX_ATOM_LOAD_MIN_GEN_64p64reg  = 880,
     896             :     INT_PTX_ATOM_LOAD_MIN_G_32p32imm    = 881,
     897             :     INT_PTX_ATOM_LOAD_MIN_G_32p32reg    = 882,
     898             :     INT_PTX_ATOM_LOAD_MIN_G_32p64imm    = 883,
     899             :     INT_PTX_ATOM_LOAD_MIN_G_32p64reg    = 884,
     900             :     INT_PTX_ATOM_LOAD_MIN_G_64p32imm    = 885,
     901             :     INT_PTX_ATOM_LOAD_MIN_G_64p32reg    = 886,
     902             :     INT_PTX_ATOM_LOAD_MIN_G_64p64imm    = 887,
     903             :     INT_PTX_ATOM_LOAD_MIN_G_64p64reg    = 888,
     904             :     INT_PTX_ATOM_LOAD_MIN_S_32p32imm    = 889,
     905             :     INT_PTX_ATOM_LOAD_MIN_S_32p32reg    = 890,
     906             :     INT_PTX_ATOM_LOAD_MIN_S_32p64imm    = 891,
     907             :     INT_PTX_ATOM_LOAD_MIN_S_32p64reg    = 892,
     908             :     INT_PTX_ATOM_LOAD_MIN_S_64p32imm    = 893,
     909             :     INT_PTX_ATOM_LOAD_MIN_S_64p32reg    = 894,
     910             :     INT_PTX_ATOM_LOAD_MIN_S_64p64imm    = 895,
     911             :     INT_PTX_ATOM_LOAD_MIN_S_64p64reg    = 896,
     912             :     INT_PTX_ATOM_LOAD_UMAX_GEN_32_USE_Gp32imm   = 897,
     913             :     INT_PTX_ATOM_LOAD_UMAX_GEN_32_USE_Gp32reg   = 898,
     914             :     INT_PTX_ATOM_LOAD_UMAX_GEN_32_USE_Gp64imm   = 899,
     915             :     INT_PTX_ATOM_LOAD_UMAX_GEN_32_USE_Gp64reg   = 900,
     916             :     INT_PTX_ATOM_LOAD_UMAX_GEN_32p32imm = 901,
     917             :     INT_PTX_ATOM_LOAD_UMAX_GEN_32p32reg = 902,
     918             :     INT_PTX_ATOM_LOAD_UMAX_GEN_32p64imm = 903,
     919             :     INT_PTX_ATOM_LOAD_UMAX_GEN_32p64reg = 904,
     920             :     INT_PTX_ATOM_LOAD_UMAX_GEN_64_USE_Gp32imm   = 905,
     921             :     INT_PTX_ATOM_LOAD_UMAX_GEN_64_USE_Gp32reg   = 906,
     922             :     INT_PTX_ATOM_LOAD_UMAX_GEN_64_USE_Gp64imm   = 907,
     923             :     INT_PTX_ATOM_LOAD_UMAX_GEN_64_USE_Gp64reg   = 908,
     924             :     INT_PTX_ATOM_LOAD_UMAX_GEN_64p32imm = 909,
     925             :     INT_PTX_ATOM_LOAD_UMAX_GEN_64p32reg = 910,
     926             :     INT_PTX_ATOM_LOAD_UMAX_GEN_64p64imm = 911,
     927             :     INT_PTX_ATOM_LOAD_UMAX_GEN_64p64reg = 912,
     928             :     INT_PTX_ATOM_LOAD_UMAX_G_32p32imm   = 913,
     929             :     INT_PTX_ATOM_LOAD_UMAX_G_32p32reg   = 914,
     930             :     INT_PTX_ATOM_LOAD_UMAX_G_32p64imm   = 915,
     931             :     INT_PTX_ATOM_LOAD_UMAX_G_32p64reg   = 916,
     932             :     INT_PTX_ATOM_LOAD_UMAX_G_64p32imm   = 917,
     933             :     INT_PTX_ATOM_LOAD_UMAX_G_64p32reg   = 918,
     934             :     INT_PTX_ATOM_LOAD_UMAX_G_64p64imm   = 919,
     935             :     INT_PTX_ATOM_LOAD_UMAX_G_64p64reg   = 920,
     936             :     INT_PTX_ATOM_LOAD_UMAX_S_32p32imm   = 921,
     937             :     INT_PTX_ATOM_LOAD_UMAX_S_32p32reg   = 922,
     938             :     INT_PTX_ATOM_LOAD_UMAX_S_32p64imm   = 923,
     939             :     INT_PTX_ATOM_LOAD_UMAX_S_32p64reg   = 924,
     940             :     INT_PTX_ATOM_LOAD_UMAX_S_64p32imm   = 925,
     941             :     INT_PTX_ATOM_LOAD_UMAX_S_64p32reg   = 926,
     942             :     INT_PTX_ATOM_LOAD_UMAX_S_64p64imm   = 927,
     943             :     INT_PTX_ATOM_LOAD_UMAX_S_64p64reg   = 928,
     944             :     INT_PTX_ATOM_LOAD_UMIN_GEN_32_USE_Gp32imm   = 929,
     945             :     INT_PTX_ATOM_LOAD_UMIN_GEN_32_USE_Gp32reg   = 930,
     946             :     INT_PTX_ATOM_LOAD_UMIN_GEN_32_USE_Gp64imm   = 931,
     947             :     INT_PTX_ATOM_LOAD_UMIN_GEN_32_USE_Gp64reg   = 932,
     948             :     INT_PTX_ATOM_LOAD_UMIN_GEN_32p32imm = 933,
     949             :     INT_PTX_ATOM_LOAD_UMIN_GEN_32p32reg = 934,
     950             :     INT_PTX_ATOM_LOAD_UMIN_GEN_32p64imm = 935,
     951             :     INT_PTX_ATOM_LOAD_UMIN_GEN_32p64reg = 936,
     952             :     INT_PTX_ATOM_LOAD_UMIN_GEN_64_USE_Gp32imm   = 937,
     953             :     INT_PTX_ATOM_LOAD_UMIN_GEN_64_USE_Gp32reg   = 938,
     954             :     INT_PTX_ATOM_LOAD_UMIN_GEN_64_USE_Gp64imm   = 939,
     955             :     INT_PTX_ATOM_LOAD_UMIN_GEN_64_USE_Gp64reg   = 940,
     956             :     INT_PTX_ATOM_LOAD_UMIN_GEN_64p32imm = 941,
     957             :     INT_PTX_ATOM_LOAD_UMIN_GEN_64p32reg = 942,
     958             :     INT_PTX_ATOM_LOAD_UMIN_GEN_64p64imm = 943,
     959             :     INT_PTX_ATOM_LOAD_UMIN_GEN_64p64reg = 944,
     960             :     INT_PTX_ATOM_LOAD_UMIN_G_32p32imm   = 945,
     961             :     INT_PTX_ATOM_LOAD_UMIN_G_32p32reg   = 946,
     962             :     INT_PTX_ATOM_LOAD_UMIN_G_32p64imm   = 947,
     963             :     INT_PTX_ATOM_LOAD_UMIN_G_32p64reg   = 948,
     964             :     INT_PTX_ATOM_LOAD_UMIN_G_64p32imm   = 949,
     965             :     INT_PTX_ATOM_LOAD_UMIN_G_64p32reg   = 950,
     966             :     INT_PTX_ATOM_LOAD_UMIN_G_64p64imm   = 951,
     967             :     INT_PTX_ATOM_LOAD_UMIN_G_64p64reg   = 952,
     968             :     INT_PTX_ATOM_LOAD_UMIN_S_32p32imm   = 953,
     969             :     INT_PTX_ATOM_LOAD_UMIN_S_32p32reg   = 954,
     970             :     INT_PTX_ATOM_LOAD_UMIN_S_32p64imm   = 955,
     971             :     INT_PTX_ATOM_LOAD_UMIN_S_32p64reg   = 956,
     972             :     INT_PTX_ATOM_LOAD_UMIN_S_64p32imm   = 957,
     973             :     INT_PTX_ATOM_LOAD_UMIN_S_64p32reg   = 958,
     974             :     INT_PTX_ATOM_LOAD_UMIN_S_64p64imm   = 959,
     975             :     INT_PTX_ATOM_LOAD_UMIN_S_64p64reg   = 960,
     976             :     INT_PTX_ATOM_OR_GEN_32_USE_Gp32imm  = 961,
     977             :     INT_PTX_ATOM_OR_GEN_32_USE_Gp32reg  = 962,
     978             :     INT_PTX_ATOM_OR_GEN_32_USE_Gp64imm  = 963,
     979             :     INT_PTX_ATOM_OR_GEN_32_USE_Gp64reg  = 964,
     980             :     INT_PTX_ATOM_OR_GEN_32p32imm        = 965,
     981             :     INT_PTX_ATOM_OR_GEN_32p32reg        = 966,
     982             :     INT_PTX_ATOM_OR_GEN_32p64imm        = 967,
     983             :     INT_PTX_ATOM_OR_GEN_32p64reg        = 968,
     984             :     INT_PTX_ATOM_OR_GEN_64_USE_Gp32imm  = 969,
     985             :     INT_PTX_ATOM_OR_GEN_64_USE_Gp32reg  = 970,
     986             :     INT_PTX_ATOM_OR_GEN_64_USE_Gp64imm  = 971,
     987             :     INT_PTX_ATOM_OR_GEN_64_USE_Gp64reg  = 972,
     988             :     INT_PTX_ATOM_OR_GEN_64p32imm        = 973,
     989             :     INT_PTX_ATOM_OR_GEN_64p32reg        = 974,
     990             :     INT_PTX_ATOM_OR_GEN_64p64imm        = 975,
     991             :     INT_PTX_ATOM_OR_GEN_64p64reg        = 976,
     992             :     INT_PTX_ATOM_OR_G_32p32imm  = 977,
     993             :     INT_PTX_ATOM_OR_G_32p32reg  = 978,
     994             :     INT_PTX_ATOM_OR_G_32p64imm  = 979,
     995             :     INT_PTX_ATOM_OR_G_32p64reg  = 980,
     996             :     INT_PTX_ATOM_OR_G_64p32imm  = 981,
     997             :     INT_PTX_ATOM_OR_G_64p32reg  = 982,
     998             :     INT_PTX_ATOM_OR_G_64p64imm  = 983,
     999             :     INT_PTX_ATOM_OR_G_64p64reg  = 984,
    1000             :     INT_PTX_ATOM_OR_S_32p32imm  = 985,
    1001             :     INT_PTX_ATOM_OR_S_32p32reg  = 986,
    1002             :     INT_PTX_ATOM_OR_S_32p64imm  = 987,
    1003             :     INT_PTX_ATOM_OR_S_32p64reg  = 988,
    1004             :     INT_PTX_ATOM_OR_S_64p32imm  = 989,
    1005             :     INT_PTX_ATOM_OR_S_64p32reg  = 990,
    1006             :     INT_PTX_ATOM_OR_S_64p64imm  = 991,
    1007             :     INT_PTX_ATOM_OR_S_64p64reg  = 992,
    1008             :     INT_PTX_ATOM_SUB_GEN_32_USE_Gp32reg = 993,
    1009             :     INT_PTX_ATOM_SUB_GEN_32_USE_Gp64reg = 994,
    1010             :     INT_PTX_ATOM_SUB_GEN_32p32reg       = 995,
    1011             :     INT_PTX_ATOM_SUB_GEN_32p64reg       = 996,
    1012             :     INT_PTX_ATOM_SUB_GEN_64_USE_Gp32reg = 997,
    1013             :     INT_PTX_ATOM_SUB_GEN_64_USE_Gp64reg = 998,
    1014             :     INT_PTX_ATOM_SUB_GEN_64p32reg       = 999,
    1015             :     INT_PTX_ATOM_SUB_GEN_64p64reg       = 1000,
    1016             :     INT_PTX_ATOM_SUB_G_32p32reg = 1001,
    1017             :     INT_PTX_ATOM_SUB_G_32p64reg = 1002,
    1018             :     INT_PTX_ATOM_SUB_G_64p32reg = 1003,
    1019             :     INT_PTX_ATOM_SUB_G_64p64reg = 1004,
    1020             :     INT_PTX_ATOM_SUB_S_32p32reg = 1005,
    1021             :     INT_PTX_ATOM_SUB_S_32p64reg = 1006,
    1022             :     INT_PTX_ATOM_SUB_S_64p32reg = 1007,
    1023             :     INT_PTX_ATOM_SUB_S_64p64reg = 1008,
    1024             :     INT_PTX_ATOM_SWAP_GEN_32_USE_Gp32imm        = 1009,
    1025             :     INT_PTX_ATOM_SWAP_GEN_32_USE_Gp32reg        = 1010,
    1026             :     INT_PTX_ATOM_SWAP_GEN_32_USE_Gp64imm        = 1011,
    1027             :     INT_PTX_ATOM_SWAP_GEN_32_USE_Gp64reg        = 1012,
    1028             :     INT_PTX_ATOM_SWAP_GEN_32p32imm      = 1013,
    1029             :     INT_PTX_ATOM_SWAP_GEN_32p32reg      = 1014,
    1030             :     INT_PTX_ATOM_SWAP_GEN_32p64imm      = 1015,
    1031             :     INT_PTX_ATOM_SWAP_GEN_32p64reg      = 1016,
    1032             :     INT_PTX_ATOM_SWAP_GEN_64_USE_Gp32imm        = 1017,
    1033             :     INT_PTX_ATOM_SWAP_GEN_64_USE_Gp32reg        = 1018,
    1034             :     INT_PTX_ATOM_SWAP_GEN_64_USE_Gp64imm        = 1019,
    1035             :     INT_PTX_ATOM_SWAP_GEN_64_USE_Gp64reg        = 1020,
    1036             :     INT_PTX_ATOM_SWAP_GEN_64p32imm      = 1021,
    1037             :     INT_PTX_ATOM_SWAP_GEN_64p32reg      = 1022,
    1038             :     INT_PTX_ATOM_SWAP_GEN_64p64imm      = 1023,
    1039             :     INT_PTX_ATOM_SWAP_GEN_64p64reg      = 1024,
    1040             :     INT_PTX_ATOM_SWAP_G_32p32imm        = 1025,
    1041             :     INT_PTX_ATOM_SWAP_G_32p32reg        = 1026,
    1042             :     INT_PTX_ATOM_SWAP_G_32p64imm        = 1027,
    1043             :     INT_PTX_ATOM_SWAP_G_32p64reg        = 1028,
    1044             :     INT_PTX_ATOM_SWAP_G_64p32imm        = 1029,
    1045             :     INT_PTX_ATOM_SWAP_G_64p32reg        = 1030,
    1046             :     INT_PTX_ATOM_SWAP_G_64p64imm        = 1031,
    1047             :     INT_PTX_ATOM_SWAP_G_64p64reg        = 1032,
    1048             :     INT_PTX_ATOM_SWAP_S_32p32imm        = 1033,
    1049             :     INT_PTX_ATOM_SWAP_S_32p32reg        = 1034,
    1050             :     INT_PTX_ATOM_SWAP_S_32p64imm        = 1035,
    1051             :     INT_PTX_ATOM_SWAP_S_32p64reg        = 1036,
    1052             :     INT_PTX_ATOM_SWAP_S_64p32imm        = 1037,
    1053             :     INT_PTX_ATOM_SWAP_S_64p32reg        = 1038,
    1054             :     INT_PTX_ATOM_SWAP_S_64p64imm        = 1039,
    1055             :     INT_PTX_ATOM_SWAP_S_64p64reg        = 1040,
    1056             :     INT_PTX_ATOM_XOR_GEN_32_USE_Gp32imm = 1041,
    1057             :     INT_PTX_ATOM_XOR_GEN_32_USE_Gp32reg = 1042,
    1058             :     INT_PTX_ATOM_XOR_GEN_32_USE_Gp64imm = 1043,
    1059             :     INT_PTX_ATOM_XOR_GEN_32_USE_Gp64reg = 1044,
    1060             :     INT_PTX_ATOM_XOR_GEN_32p32imm       = 1045,
    1061             :     INT_PTX_ATOM_XOR_GEN_32p32reg       = 1046,
    1062             :     INT_PTX_ATOM_XOR_GEN_32p64imm       = 1047,
    1063             :     INT_PTX_ATOM_XOR_GEN_32p64reg       = 1048,
    1064             :     INT_PTX_ATOM_XOR_GEN_64_USE_Gp32imm = 1049,
    1065             :     INT_PTX_ATOM_XOR_GEN_64_USE_Gp32reg = 1050,
    1066             :     INT_PTX_ATOM_XOR_GEN_64_USE_Gp64imm = 1051,
    1067             :     INT_PTX_ATOM_XOR_GEN_64_USE_Gp64reg = 1052,
    1068             :     INT_PTX_ATOM_XOR_GEN_64p32imm       = 1053,
    1069             :     INT_PTX_ATOM_XOR_GEN_64p32reg       = 1054,
    1070             :     INT_PTX_ATOM_XOR_GEN_64p64imm       = 1055,
    1071             :     INT_PTX_ATOM_XOR_GEN_64p64reg       = 1056,
    1072             :     INT_PTX_ATOM_XOR_G_32p32imm = 1057,
    1073             :     INT_PTX_ATOM_XOR_G_32p32reg = 1058,
    1074             :     INT_PTX_ATOM_XOR_G_32p64imm = 1059,
    1075             :     INT_PTX_ATOM_XOR_G_32p64reg = 1060,
    1076             :     INT_PTX_ATOM_XOR_G_64p32imm = 1061,
    1077             :     INT_PTX_ATOM_XOR_G_64p32reg = 1062,
    1078             :     INT_PTX_ATOM_XOR_G_64p64imm = 1063,
    1079             :     INT_PTX_ATOM_XOR_G_64p64reg = 1064,
    1080             :     INT_PTX_ATOM_XOR_S_32p32imm = 1065,
    1081             :     INT_PTX_ATOM_XOR_S_32p32reg = 1066,
    1082             :     INT_PTX_ATOM_XOR_S_32p64imm = 1067,
    1083             :     INT_PTX_ATOM_XOR_S_32p64reg = 1068,
    1084             :     INT_PTX_ATOM_XOR_S_64p32imm = 1069,
    1085             :     INT_PTX_ATOM_XOR_S_64p32reg = 1070,
    1086             :     INT_PTX_ATOM_XOR_S_64p64imm = 1071,
    1087             :     INT_PTX_ATOM_XOR_S_64p64reg = 1072,
    1088             :     INT_PTX_LDG_GLOBAL_f16areg  = 1073,
    1089             :     INT_PTX_LDG_GLOBAL_f16areg64        = 1074,
    1090             :     INT_PTX_LDG_GLOBAL_f16ari   = 1075,
    1091             :     INT_PTX_LDG_GLOBAL_f16ari64 = 1076,
    1092             :     INT_PTX_LDG_GLOBAL_f16avar  = 1077,
    1093             :     INT_PTX_LDG_GLOBAL_f16x2areg        = 1078,
    1094             :     INT_PTX_LDG_GLOBAL_f16x2areg64      = 1079,
    1095             :     INT_PTX_LDG_GLOBAL_f16x2ari = 1080,
    1096             :     INT_PTX_LDG_GLOBAL_f16x2ari64       = 1081,
    1097             :     INT_PTX_LDG_GLOBAL_f16x2avar        = 1082,
    1098             :     INT_PTX_LDG_GLOBAL_f32areg  = 1083,
    1099             :     INT_PTX_LDG_GLOBAL_f32areg64        = 1084,
    1100             :     INT_PTX_LDG_GLOBAL_f32ari   = 1085,
    1101             :     INT_PTX_LDG_GLOBAL_f32ari64 = 1086,
    1102             :     INT_PTX_LDG_GLOBAL_f32avar  = 1087,
    1103             :     INT_PTX_LDG_GLOBAL_f64areg  = 1088,
    1104             :     INT_PTX_LDG_GLOBAL_f64areg64        = 1089,
    1105             :     INT_PTX_LDG_GLOBAL_f64ari   = 1090,
    1106             :     INT_PTX_LDG_GLOBAL_f64ari64 = 1091,
    1107             :     INT_PTX_LDG_GLOBAL_f64avar  = 1092,
    1108             :     INT_PTX_LDG_GLOBAL_i16areg  = 1093,
    1109             :     INT_PTX_LDG_GLOBAL_i16areg64        = 1094,
    1110             :     INT_PTX_LDG_GLOBAL_i16ari   = 1095,
    1111             :     INT_PTX_LDG_GLOBAL_i16ari64 = 1096,
    1112             :     INT_PTX_LDG_GLOBAL_i16avar  = 1097,
    1113             :     INT_PTX_LDG_GLOBAL_i32areg  = 1098,
    1114             :     INT_PTX_LDG_GLOBAL_i32areg64        = 1099,
    1115             :     INT_PTX_LDG_GLOBAL_i32ari   = 1100,
    1116             :     INT_PTX_LDG_GLOBAL_i32ari64 = 1101,
    1117             :     INT_PTX_LDG_GLOBAL_i32avar  = 1102,
    1118             :     INT_PTX_LDG_GLOBAL_i64areg  = 1103,
    1119             :     INT_PTX_LDG_GLOBAL_i64areg64        = 1104,
    1120             :     INT_PTX_LDG_GLOBAL_i64ari   = 1105,
    1121             :     INT_PTX_LDG_GLOBAL_i64ari64 = 1106,
    1122             :     INT_PTX_LDG_GLOBAL_i64avar  = 1107,
    1123             :     INT_PTX_LDG_GLOBAL_i8areg   = 1108,
    1124             :     INT_PTX_LDG_GLOBAL_i8areg64 = 1109,
    1125             :     INT_PTX_LDG_GLOBAL_i8ari    = 1110,
    1126             :     INT_PTX_LDG_GLOBAL_i8ari64  = 1111,
    1127             :     INT_PTX_LDG_GLOBAL_i8avar   = 1112,
    1128             :     INT_PTX_LDG_GLOBAL_p32areg  = 1113,
    1129             :     INT_PTX_LDG_GLOBAL_p32areg64        = 1114,
    1130             :     INT_PTX_LDG_GLOBAL_p32ari   = 1115,
    1131             :     INT_PTX_LDG_GLOBAL_p32ari64 = 1116,
    1132             :     INT_PTX_LDG_GLOBAL_p32avar  = 1117,
    1133             :     INT_PTX_LDG_GLOBAL_p64areg  = 1118,
    1134             :     INT_PTX_LDG_GLOBAL_p64areg64        = 1119,
    1135             :     INT_PTX_LDG_GLOBAL_p64ari   = 1120,
    1136             :     INT_PTX_LDG_GLOBAL_p64ari64 = 1121,
    1137             :     INT_PTX_LDG_GLOBAL_p64avar  = 1122,
    1138             :     INT_PTX_LDG_G_v2f16_ELE_areg32      = 1123,
    1139             :     INT_PTX_LDG_G_v2f16_ELE_areg64      = 1124,
    1140             :     INT_PTX_LDG_G_v2f16_ELE_ari32       = 1125,
    1141             :     INT_PTX_LDG_G_v2f16_ELE_ari64       = 1126,
    1142             :     INT_PTX_LDG_G_v2f16_ELE_avar        = 1127,
    1143             :     INT_PTX_LDG_G_v2f16x2_ELE_areg32    = 1128,
    1144             :     INT_PTX_LDG_G_v2f16x2_ELE_areg64    = 1129,
    1145             :     INT_PTX_LDG_G_v2f16x2_ELE_ari32     = 1130,
    1146             :     INT_PTX_LDG_G_v2f16x2_ELE_ari64     = 1131,
    1147             :     INT_PTX_LDG_G_v2f16x2_ELE_avar      = 1132,
    1148             :     INT_PTX_LDG_G_v2f32_ELE_areg32      = 1133,
    1149             :     INT_PTX_LDG_G_v2f32_ELE_areg64      = 1134,
    1150             :     INT_PTX_LDG_G_v2f32_ELE_ari32       = 1135,
    1151             :     INT_PTX_LDG_G_v2f32_ELE_ari64       = 1136,
    1152             :     INT_PTX_LDG_G_v2f32_ELE_avar        = 1137,
    1153             :     INT_PTX_LDG_G_v2f64_ELE_areg32      = 1138,
    1154             :     INT_PTX_LDG_G_v2f64_ELE_areg64      = 1139,
    1155             :     INT_PTX_LDG_G_v2f64_ELE_ari32       = 1140,
    1156             :     INT_PTX_LDG_G_v2f64_ELE_ari64       = 1141,
    1157             :     INT_PTX_LDG_G_v2f64_ELE_avar        = 1142,
    1158             :     INT_PTX_LDG_G_v2i16_ELE_areg32      = 1143,
    1159             :     INT_PTX_LDG_G_v2i16_ELE_areg64      = 1144,
    1160             :     INT_PTX_LDG_G_v2i16_ELE_ari32       = 1145,
    1161             :     INT_PTX_LDG_G_v2i16_ELE_ari64       = 1146,
    1162             :     INT_PTX_LDG_G_v2i16_ELE_avar        = 1147,
    1163             :     INT_PTX_LDG_G_v2i32_ELE_areg32      = 1148,
    1164             :     INT_PTX_LDG_G_v2i32_ELE_areg64      = 1149,
    1165             :     INT_PTX_LDG_G_v2i32_ELE_ari32       = 1150,
    1166             :     INT_PTX_LDG_G_v2i32_ELE_ari64       = 1151,
    1167             :     INT_PTX_LDG_G_v2i32_ELE_avar        = 1152,
    1168             :     INT_PTX_LDG_G_v2i64_ELE_areg32      = 1153,
    1169             :     INT_PTX_LDG_G_v2i64_ELE_areg64      = 1154,
    1170             :     INT_PTX_LDG_G_v2i64_ELE_ari32       = 1155,
    1171             :     INT_PTX_LDG_G_v2i64_ELE_ari64       = 1156,
    1172             :     INT_PTX_LDG_G_v2i64_ELE_avar        = 1157,
    1173             :     INT_PTX_LDG_G_v2i8_ELE_areg32       = 1158,
    1174             :     INT_PTX_LDG_G_v2i8_ELE_areg64       = 1159,
    1175             :     INT_PTX_LDG_G_v2i8_ELE_ari32        = 1160,
    1176             :     INT_PTX_LDG_G_v2i8_ELE_ari64        = 1161,
    1177             :     INT_PTX_LDG_G_v2i8_ELE_avar = 1162,
    1178             :     INT_PTX_LDG_G_v4f16_ELE_areg32      = 1163,
    1179             :     INT_PTX_LDG_G_v4f16_ELE_areg64      = 1164,
    1180             :     INT_PTX_LDG_G_v4f16_ELE_ari32       = 1165,
    1181             :     INT_PTX_LDG_G_v4f16_ELE_ari64       = 1166,
    1182             :     INT_PTX_LDG_G_v4f16_ELE_avar        = 1167,
    1183             :     INT_PTX_LDG_G_v4f16x2_ELE_areg32    = 1168,
    1184             :     INT_PTX_LDG_G_v4f16x2_ELE_areg64    = 1169,
    1185             :     INT_PTX_LDG_G_v4f16x2_ELE_ari32     = 1170,
    1186             :     INT_PTX_LDG_G_v4f16x2_ELE_ari64     = 1171,
    1187             :     INT_PTX_LDG_G_v4f16x2_ELE_avar      = 1172,
    1188             :     INT_PTX_LDG_G_v4f32_ELE_areg32      = 1173,
    1189             :     INT_PTX_LDG_G_v4f32_ELE_areg64      = 1174,
    1190             :     INT_PTX_LDG_G_v4f32_ELE_ari32       = 1175,
    1191             :     INT_PTX_LDG_G_v4f32_ELE_ari64       = 1176,
    1192             :     INT_PTX_LDG_G_v4f32_ELE_avar        = 1177,
    1193             :     INT_PTX_LDG_G_v4i16_ELE_areg32      = 1178,
    1194             :     INT_PTX_LDG_G_v4i16_ELE_areg64      = 1179,
    1195             :     INT_PTX_LDG_G_v4i16_ELE_ari32       = 1180,
    1196             :     INT_PTX_LDG_G_v4i16_ELE_ari64       = 1181,
    1197             :     INT_PTX_LDG_G_v4i16_ELE_avar        = 1182,
    1198             :     INT_PTX_LDG_G_v4i32_ELE_areg32      = 1183,
    1199             :     INT_PTX_LDG_G_v4i32_ELE_areg64      = 1184,
    1200             :     INT_PTX_LDG_G_v4i32_ELE_ari32       = 1185,
    1201             :     INT_PTX_LDG_G_v4i32_ELE_ari64       = 1186,
    1202             :     INT_PTX_LDG_G_v4i32_ELE_avar        = 1187,
    1203             :     INT_PTX_LDG_G_v4i8_ELE_areg32       = 1188,
    1204             :     INT_PTX_LDG_G_v4i8_ELE_areg64       = 1189,
    1205             :     INT_PTX_LDG_G_v4i8_ELE_ari32        = 1190,
    1206             :     INT_PTX_LDG_G_v4i8_ELE_ari64        = 1191,
    1207             :     INT_PTX_LDG_G_v4i8_ELE_avar = 1192,
    1208             :     INT_PTX_LDU_GLOBAL_f16areg  = 1193,
    1209             :     INT_PTX_LDU_GLOBAL_f16areg64        = 1194,
    1210             :     INT_PTX_LDU_GLOBAL_f16ari   = 1195,
    1211             :     INT_PTX_LDU_GLOBAL_f16ari64 = 1196,
    1212             :     INT_PTX_LDU_GLOBAL_f16avar  = 1197,
    1213             :     INT_PTX_LDU_GLOBAL_f16x2areg        = 1198,
    1214             :     INT_PTX_LDU_GLOBAL_f16x2areg64      = 1199,
    1215             :     INT_PTX_LDU_GLOBAL_f16x2ari = 1200,
    1216             :     INT_PTX_LDU_GLOBAL_f16x2ari64       = 1201,
    1217             :     INT_PTX_LDU_GLOBAL_f16x2avar        = 1202,
    1218             :     INT_PTX_LDU_GLOBAL_f32areg  = 1203,
    1219             :     INT_PTX_LDU_GLOBAL_f32areg64        = 1204,
    1220             :     INT_PTX_LDU_GLOBAL_f32ari   = 1205,
    1221             :     INT_PTX_LDU_GLOBAL_f32ari64 = 1206,
    1222             :     INT_PTX_LDU_GLOBAL_f32avar  = 1207,
    1223             :     INT_PTX_LDU_GLOBAL_f64areg  = 1208,
    1224             :     INT_PTX_LDU_GLOBAL_f64areg64        = 1209,
    1225             :     INT_PTX_LDU_GLOBAL_f64ari   = 1210,
    1226             :     INT_PTX_LDU_GLOBAL_f64ari64 = 1211,
    1227             :     INT_PTX_LDU_GLOBAL_f64avar  = 1212,
    1228             :     INT_PTX_LDU_GLOBAL_i16areg  = 1213,
    1229             :     INT_PTX_LDU_GLOBAL_i16areg64        = 1214,
    1230             :     INT_PTX_LDU_GLOBAL_i16ari   = 1215,
    1231             :     INT_PTX_LDU_GLOBAL_i16ari64 = 1216,
    1232             :     INT_PTX_LDU_GLOBAL_i16avar  = 1217,
    1233             :     INT_PTX_LDU_GLOBAL_i32areg  = 1218,
    1234             :     INT_PTX_LDU_GLOBAL_i32areg64        = 1219,
    1235             :     INT_PTX_LDU_GLOBAL_i32ari   = 1220,
    1236             :     INT_PTX_LDU_GLOBAL_i32ari64 = 1221,
    1237             :     INT_PTX_LDU_GLOBAL_i32avar  = 1222,
    1238             :     INT_PTX_LDU_GLOBAL_i64areg  = 1223,
    1239             :     INT_PTX_LDU_GLOBAL_i64areg64        = 1224,
    1240             :     INT_PTX_LDU_GLOBAL_i64ari   = 1225,
    1241             :     INT_PTX_LDU_GLOBAL_i64ari64 = 1226,
    1242             :     INT_PTX_LDU_GLOBAL_i64avar  = 1227,
    1243             :     INT_PTX_LDU_GLOBAL_i8areg   = 1228,
    1244             :     INT_PTX_LDU_GLOBAL_i8areg64 = 1229,
    1245             :     INT_PTX_LDU_GLOBAL_i8ari    = 1230,
    1246             :     INT_PTX_LDU_GLOBAL_i8ari64  = 1231,
    1247             :     INT_PTX_LDU_GLOBAL_i8avar   = 1232,
    1248             :     INT_PTX_LDU_GLOBAL_p32areg  = 1233,
    1249             :     INT_PTX_LDU_GLOBAL_p32areg64        = 1234,
    1250             :     INT_PTX_LDU_GLOBAL_p32ari   = 1235,
    1251             :     INT_PTX_LDU_GLOBAL_p32ari64 = 1236,
    1252             :     INT_PTX_LDU_GLOBAL_p32avar  = 1237,
    1253             :     INT_PTX_LDU_GLOBAL_p64areg  = 1238,
    1254             :     INT_PTX_LDU_GLOBAL_p64areg64        = 1239,
    1255             :     INT_PTX_LDU_GLOBAL_p64ari   = 1240,
    1256             :     INT_PTX_LDU_GLOBAL_p64ari64 = 1241,
    1257             :     INT_PTX_LDU_GLOBAL_p64avar  = 1242,
    1258             :     INT_PTX_LDU_G_v2f16_ELE_areg32      = 1243,
    1259             :     INT_PTX_LDU_G_v2f16_ELE_areg64      = 1244,
    1260             :     INT_PTX_LDU_G_v2f16_ELE_ari32       = 1245,
    1261             :     INT_PTX_LDU_G_v2f16_ELE_ari64       = 1246,
    1262             :     INT_PTX_LDU_G_v2f16_ELE_avar        = 1247,
    1263             :     INT_PTX_LDU_G_v2f16x2_ELE_areg32    = 1248,
    1264             :     INT_PTX_LDU_G_v2f16x2_ELE_areg64    = 1249,
    1265             :     INT_PTX_LDU_G_v2f16x2_ELE_ari32     = 1250,
    1266             :     INT_PTX_LDU_G_v2f16x2_ELE_ari64     = 1251,
    1267             :     INT_PTX_LDU_G_v2f16x2_ELE_avar      = 1252,
    1268             :     INT_PTX_LDU_G_v2f32_ELE_areg32      = 1253,
    1269             :     INT_PTX_LDU_G_v2f32_ELE_areg64      = 1254,
    1270             :     INT_PTX_LDU_G_v2f32_ELE_ari32       = 1255,
    1271             :     INT_PTX_LDU_G_v2f32_ELE_ari64       = 1256,
    1272             :     INT_PTX_LDU_G_v2f32_ELE_avar        = 1257,
    1273             :     INT_PTX_LDU_G_v2f64_ELE_areg32      = 1258,
    1274             :     INT_PTX_LDU_G_v2f64_ELE_areg64      = 1259,
    1275             :     INT_PTX_LDU_G_v2f64_ELE_ari32       = 1260,
    1276             :     INT_PTX_LDU_G_v2f64_ELE_ari64       = 1261,
    1277             :     INT_PTX_LDU_G_v2f64_ELE_avar        = 1262,
    1278             :     INT_PTX_LDU_G_v2i16_ELE_areg32      = 1263,
    1279             :     INT_PTX_LDU_G_v2i16_ELE_areg64      = 1264,
    1280             :     INT_PTX_LDU_G_v2i16_ELE_ari32       = 1265,
    1281             :     INT_PTX_LDU_G_v2i16_ELE_ari64       = 1266,
    1282             :     INT_PTX_LDU_G_v2i16_ELE_avar        = 1267,
    1283             :     INT_PTX_LDU_G_v2i32_ELE_areg32      = 1268,
    1284             :     INT_PTX_LDU_G_v2i32_ELE_areg64      = 1269,
    1285             :     INT_PTX_LDU_G_v2i32_ELE_ari32       = 1270,
    1286             :     INT_PTX_LDU_G_v2i32_ELE_ari64       = 1271,
    1287             :     INT_PTX_LDU_G_v2i32_ELE_avar        = 1272,
    1288             :     INT_PTX_LDU_G_v2i64_ELE_areg32      = 1273,
    1289             :     INT_PTX_LDU_G_v2i64_ELE_areg64      = 1274,
    1290             :     INT_PTX_LDU_G_v2i64_ELE_ari32       = 1275,
    1291             :     INT_PTX_LDU_G_v2i64_ELE_ari64       = 1276,
    1292             :     INT_PTX_LDU_G_v2i64_ELE_avar        = 1277,
    1293             :     INT_PTX_LDU_G_v2i8_ELE_areg32       = 1278,
    1294             :     INT_PTX_LDU_G_v2i8_ELE_areg64       = 1279,
    1295             :     INT_PTX_LDU_G_v2i8_ELE_ari32        = 1280,
    1296             :     INT_PTX_LDU_G_v2i8_ELE_ari64        = 1281,
    1297             :     INT_PTX_LDU_G_v2i8_ELE_avar = 1282,
    1298             :     INT_PTX_LDU_G_v4f16_ELE_areg32      = 1283,
    1299             :     INT_PTX_LDU_G_v4f16_ELE_areg64      = 1284,
    1300             :     INT_PTX_LDU_G_v4f16_ELE_ari32       = 1285,
    1301             :     INT_PTX_LDU_G_v4f16_ELE_ari64       = 1286,
    1302             :     INT_PTX_LDU_G_v4f16_ELE_avar        = 1287,
    1303             :     INT_PTX_LDU_G_v4f16x2_ELE_areg32    = 1288,
    1304             :     INT_PTX_LDU_G_v4f16x2_ELE_areg64    = 1289,
    1305             :     INT_PTX_LDU_G_v4f16x2_ELE_ari32     = 1290,
    1306             :     INT_PTX_LDU_G_v4f16x2_ELE_ari64     = 1291,
    1307             :     INT_PTX_LDU_G_v4f16x2_ELE_avar      = 1292,
    1308             :     INT_PTX_LDU_G_v4f32_ELE_areg32      = 1293,
    1309             :     INT_PTX_LDU_G_v4f32_ELE_areg64      = 1294,
    1310             :     INT_PTX_LDU_G_v4f32_ELE_ari32       = 1295,
    1311             :     INT_PTX_LDU_G_v4f32_ELE_ari64       = 1296,
    1312             :     INT_PTX_LDU_G_v4f32_ELE_avar        = 1297,
    1313             :     INT_PTX_LDU_G_v4i16_ELE_areg32      = 1298,
    1314             :     INT_PTX_LDU_G_v4i16_ELE_areg64      = 1299,
    1315             :     INT_PTX_LDU_G_v4i16_ELE_ari32       = 1300,
    1316             :     INT_PTX_LDU_G_v4i16_ELE_ari64       = 1301,
    1317             :     INT_PTX_LDU_G_v4i16_ELE_avar        = 1302,
    1318             :     INT_PTX_LDU_G_v4i32_ELE_areg32      = 1303,
    1319             :     INT_PTX_LDU_G_v4i32_ELE_areg64      = 1304,
    1320             :     INT_PTX_LDU_G_v4i32_ELE_ari32       = 1305,
    1321             :     INT_PTX_LDU_G_v4i32_ELE_ari64       = 1306,
    1322             :     INT_PTX_LDU_G_v4i32_ELE_avar        = 1307,
    1323             :     INT_PTX_LDU_G_v4i8_ELE_areg32       = 1308,
    1324             :     INT_PTX_LDU_G_v4i8_ELE_areg64       = 1309,
    1325             :     INT_PTX_LDU_G_v4i8_ELE_ari32        = 1310,
    1326             :     INT_PTX_LDU_G_v4i8_ELE_ari64        = 1311,
    1327             :     INT_PTX_LDU_G_v4i8_ELE_avar = 1312,
    1328             :     INT_PTX_SREG_CLOCK  = 1313,
    1329             :     INT_PTX_SREG_CLOCK64        = 1314,
    1330             :     INT_PTX_SREG_CTAID_W        = 1315,
    1331             :     INT_PTX_SREG_CTAID_X        = 1316,
    1332             :     INT_PTX_SREG_CTAID_Y        = 1317,
    1333             :     INT_PTX_SREG_CTAID_Z        = 1318,
    1334             :     INT_PTX_SREG_GRIDID = 1319,
    1335             :     INT_PTX_SREG_LANEID = 1320,
    1336             :     INT_PTX_SREG_LANEMASK_EQ    = 1321,
    1337             :     INT_PTX_SREG_LANEMASK_GE    = 1322,
    1338             :     INT_PTX_SREG_LANEMASK_GT    = 1323,
    1339             :     INT_PTX_SREG_LANEMASK_LE    = 1324,
    1340             :     INT_PTX_SREG_LANEMASK_LT    = 1325,
    1341             :     INT_PTX_SREG_NCTAID_W       = 1326,
    1342             :     INT_PTX_SREG_NCTAID_X       = 1327,
    1343             :     INT_PTX_SREG_NCTAID_Y       = 1328,
    1344             :     INT_PTX_SREG_NCTAID_Z       = 1329,
    1345             :     INT_PTX_SREG_NSMID  = 1330,
    1346             :     INT_PTX_SREG_NTID_W = 1331,
    1347             :     INT_PTX_SREG_NTID_X = 1332,
    1348             :     INT_PTX_SREG_NTID_Y = 1333,
    1349             :     INT_PTX_SREG_NTID_Z = 1334,
    1350             :     INT_PTX_SREG_NWARPID        = 1335,
    1351             :     INT_PTX_SREG_PM0    = 1336,
    1352             :     INT_PTX_SREG_PM1    = 1337,
    1353             :     INT_PTX_SREG_PM2    = 1338,
    1354             :     INT_PTX_SREG_PM3    = 1339,
    1355             :     INT_PTX_SREG_SMID   = 1340,
    1356             :     INT_PTX_SREG_TID_W  = 1341,
    1357             :     INT_PTX_SREG_TID_X  = 1342,
    1358             :     INT_PTX_SREG_TID_Y  = 1343,
    1359             :     INT_PTX_SREG_TID_Z  = 1344,
    1360             :     INT_PTX_SREG_WARPID = 1345,
    1361             :     INT_PTX_SREG_WARPSIZE       = 1346,
    1362             :     INT_SHFL_BFLY_F32imm1       = 1347,
    1363             :     INT_SHFL_BFLY_F32imm2       = 1348,
    1364             :     INT_SHFL_BFLY_F32imm3       = 1349,
    1365             :     INT_SHFL_BFLY_F32reg        = 1350,
    1366             :     INT_SHFL_BFLY_I32imm1       = 1351,
    1367             :     INT_SHFL_BFLY_I32imm2       = 1352,
    1368             :     INT_SHFL_BFLY_I32imm3       = 1353,
    1369             :     INT_SHFL_BFLY_I32reg        = 1354,
    1370             :     INT_SHFL_DOWN_F32imm1       = 1355,
    1371             :     INT_SHFL_DOWN_F32imm2       = 1356,
    1372             :     INT_SHFL_DOWN_F32imm3       = 1357,
    1373             :     INT_SHFL_DOWN_F32reg        = 1358,
    1374             :     INT_SHFL_DOWN_I32imm1       = 1359,
    1375             :     INT_SHFL_DOWN_I32imm2       = 1360,
    1376             :     INT_SHFL_DOWN_I32imm3       = 1361,
    1377             :     INT_SHFL_DOWN_I32reg        = 1362,
    1378             :     INT_SHFL_IDX_F32imm1        = 1363,
    1379             :     INT_SHFL_IDX_F32imm2        = 1364,
    1380             :     INT_SHFL_IDX_F32imm3        = 1365,
    1381             :     INT_SHFL_IDX_F32reg = 1366,
    1382             :     INT_SHFL_IDX_I32imm1        = 1367,
    1383             :     INT_SHFL_IDX_I32imm2        = 1368,
    1384             :     INT_SHFL_IDX_I32imm3        = 1369,
    1385             :     INT_SHFL_IDX_I32reg = 1370,
    1386             :     INT_SHFL_SYNC_BFLY_F32iii   = 1371,
    1387             :     INT_SHFL_SYNC_BFLY_F32iir   = 1372,
    1388             :     INT_SHFL_SYNC_BFLY_F32iri   = 1373,
    1389             :     INT_SHFL_SYNC_BFLY_F32irr   = 1374,
    1390             :     INT_SHFL_SYNC_BFLY_F32rii   = 1375,
    1391             :     INT_SHFL_SYNC_BFLY_F32rir   = 1376,
    1392             :     INT_SHFL_SYNC_BFLY_F32rri   = 1377,
    1393             :     INT_SHFL_SYNC_BFLY_F32rrr   = 1378,
    1394             :     INT_SHFL_SYNC_BFLY_I32iii   = 1379,
    1395             :     INT_SHFL_SYNC_BFLY_I32iir   = 1380,
    1396             :     INT_SHFL_SYNC_BFLY_I32iri   = 1381,
    1397             :     INT_SHFL_SYNC_BFLY_I32irr   = 1382,
    1398             :     INT_SHFL_SYNC_BFLY_I32rii   = 1383,
    1399             :     INT_SHFL_SYNC_BFLY_I32rir   = 1384,
    1400             :     INT_SHFL_SYNC_BFLY_I32rri   = 1385,
    1401             :     INT_SHFL_SYNC_BFLY_I32rrr   = 1386,
    1402             :     INT_SHFL_SYNC_DOWN_F32iii   = 1387,
    1403             :     INT_SHFL_SYNC_DOWN_F32iir   = 1388,
    1404             :     INT_SHFL_SYNC_DOWN_F32iri   = 1389,
    1405             :     INT_SHFL_SYNC_DOWN_F32irr   = 1390,
    1406             :     INT_SHFL_SYNC_DOWN_F32rii   = 1391,
    1407             :     INT_SHFL_SYNC_DOWN_F32rir   = 1392,
    1408             :     INT_SHFL_SYNC_DOWN_F32rri   = 1393,
    1409             :     INT_SHFL_SYNC_DOWN_F32rrr   = 1394,
    1410             :     INT_SHFL_SYNC_DOWN_I32iii   = 1395,
    1411             :     INT_SHFL_SYNC_DOWN_I32iir   = 1396,
    1412             :     INT_SHFL_SYNC_DOWN_I32iri   = 1397,
    1413             :     INT_SHFL_SYNC_DOWN_I32irr   = 1398,
    1414             :     INT_SHFL_SYNC_DOWN_I32rii   = 1399,
    1415             :     INT_SHFL_SYNC_DOWN_I32rir   = 1400,
    1416             :     INT_SHFL_SYNC_DOWN_I32rri   = 1401,
    1417             :     INT_SHFL_SYNC_DOWN_I32rrr   = 1402,
    1418             :     INT_SHFL_SYNC_IDX_F32iii    = 1403,
    1419             :     INT_SHFL_SYNC_IDX_F32iir    = 1404,
    1420             :     INT_SHFL_SYNC_IDX_F32iri    = 1405,
    1421             :     INT_SHFL_SYNC_IDX_F32irr    = 1406,
    1422             :     INT_SHFL_SYNC_IDX_F32rii    = 1407,
    1423             :     INT_SHFL_SYNC_IDX_F32rir    = 1408,
    1424             :     INT_SHFL_SYNC_IDX_F32rri    = 1409,
    1425             :     INT_SHFL_SYNC_IDX_F32rrr    = 1410,
    1426             :     INT_SHFL_SYNC_IDX_I32iii    = 1411,
    1427             :     INT_SHFL_SYNC_IDX_I32iir    = 1412,
    1428             :     INT_SHFL_SYNC_IDX_I32iri    = 1413,
    1429             :     INT_SHFL_SYNC_IDX_I32irr    = 1414,
    1430             :     INT_SHFL_SYNC_IDX_I32rii    = 1415,
    1431             :     INT_SHFL_SYNC_IDX_I32rir    = 1416,
    1432             :     INT_SHFL_SYNC_IDX_I32rri    = 1417,
    1433             :     INT_SHFL_SYNC_IDX_I32rrr    = 1418,
    1434             :     INT_SHFL_SYNC_UP_F32iii     = 1419,
    1435             :     INT_SHFL_SYNC_UP_F32iir     = 1420,
    1436             :     INT_SHFL_SYNC_UP_F32iri     = 1421,
    1437             :     INT_SHFL_SYNC_UP_F32irr     = 1422,
    1438             :     INT_SHFL_SYNC_UP_F32rii     = 1423,
    1439             :     INT_SHFL_SYNC_UP_F32rir     = 1424,
    1440             :     INT_SHFL_SYNC_UP_F32rri     = 1425,
    1441             :     INT_SHFL_SYNC_UP_F32rrr     = 1426,
    1442             :     INT_SHFL_SYNC_UP_I32iii     = 1427,
    1443             :     INT_SHFL_SYNC_UP_I32iir     = 1428,
    1444             :     INT_SHFL_SYNC_UP_I32iri     = 1429,
    1445             :     INT_SHFL_SYNC_UP_I32irr     = 1430,
    1446             :     INT_SHFL_SYNC_UP_I32rii     = 1431,
    1447             :     INT_SHFL_SYNC_UP_I32rir     = 1432,
    1448             :     INT_SHFL_SYNC_UP_I32rri     = 1433,
    1449             :     INT_SHFL_SYNC_UP_I32rrr     = 1434,
    1450             :     INT_SHFL_UP_F32imm1 = 1435,
    1451             :     INT_SHFL_UP_F32imm2 = 1436,
    1452             :     INT_SHFL_UP_F32imm3 = 1437,
    1453             :     INT_SHFL_UP_F32reg  = 1438,
    1454             :     INT_SHFL_UP_I32imm1 = 1439,
    1455             :     INT_SHFL_UP_I32imm2 = 1440,
    1456             :     INT_SHFL_UP_I32imm3 = 1441,
    1457             :     INT_SHFL_UP_I32reg  = 1442,
    1458             :     INT_WMMA_MMA_m16n16k16_col_col_f16_f16      = 1443,
    1459             :     INT_WMMA_MMA_m16n16k16_col_col_f16_f16_satfinite    = 1444,
    1460             :     INT_WMMA_MMA_m16n16k16_col_col_f16_f32      = 1445,
    1461             :     INT_WMMA_MMA_m16n16k16_col_col_f16_f32_satfinite    = 1446,
    1462             :     INT_WMMA_MMA_m16n16k16_col_col_f32_f16      = 1447,
    1463             :     INT_WMMA_MMA_m16n16k16_col_col_f32_f16_satfinite    = 1448,
    1464             :     INT_WMMA_MMA_m16n16k16_col_col_f32_f32      = 1449,
    1465             :     INT_WMMA_MMA_m16n16k16_col_col_f32_f32_satfinite    = 1450,
    1466             :     INT_WMMA_MMA_m16n16k16_col_row_f16_f16      = 1451,
    1467             :     INT_WMMA_MMA_m16n16k16_col_row_f16_f16_satfinite    = 1452,
    1468             :     INT_WMMA_MMA_m16n16k16_col_row_f16_f32      = 1453,
    1469             :     INT_WMMA_MMA_m16n16k16_col_row_f16_f32_satfinite    = 1454,
    1470             :     INT_WMMA_MMA_m16n16k16_col_row_f32_f16      = 1455,
    1471             :     INT_WMMA_MMA_m16n16k16_col_row_f32_f16_satfinite    = 1456,
    1472             :     INT_WMMA_MMA_m16n16k16_col_row_f32_f32      = 1457,
    1473             :     INT_WMMA_MMA_m16n16k16_col_row_f32_f32_satfinite    = 1458,
    1474             :     INT_WMMA_MMA_m16n16k16_row_col_f16_f16      = 1459,
    1475             :     INT_WMMA_MMA_m16n16k16_row_col_f16_f16_satfinite    = 1460,
    1476             :     INT_WMMA_MMA_m16n16k16_row_col_f16_f32      = 1461,
    1477             :     INT_WMMA_MMA_m16n16k16_row_col_f16_f32_satfinite    = 1462,
    1478             :     INT_WMMA_MMA_m16n16k16_row_col_f32_f16      = 1463,
    1479             :     INT_WMMA_MMA_m16n16k16_row_col_f32_f16_satfinite    = 1464,
    1480             :     INT_WMMA_MMA_m16n16k16_row_col_f32_f32      = 1465,
    1481             :     INT_WMMA_MMA_m16n16k16_row_col_f32_f32_satfinite    = 1466,
    1482             :     INT_WMMA_MMA_m16n16k16_row_row_f16_f16      = 1467,
    1483             :     INT_WMMA_MMA_m16n16k16_row_row_f16_f16_satfinite    = 1468,
    1484             :     INT_WMMA_MMA_m16n16k16_row_row_f16_f32      = 1469,
    1485             :     INT_WMMA_MMA_m16n16k16_row_row_f16_f32_satfinite    = 1470,
    1486             :     INT_WMMA_MMA_m16n16k16_row_row_f32_f16      = 1471,
    1487             :     INT_WMMA_MMA_m16n16k16_row_row_f32_f16_satfinite    = 1472,
    1488             :     INT_WMMA_MMA_m16n16k16_row_row_f32_f32      = 1473,
    1489             :     INT_WMMA_MMA_m16n16k16_row_row_f32_f32_satfinite    = 1474,
    1490             :     INT_WMMA_MMA_m32n8k16_col_col_f16_f16       = 1475,
    1491             :     INT_WMMA_MMA_m32n8k16_col_col_f16_f16_satfinite     = 1476,
    1492             :     INT_WMMA_MMA_m32n8k16_col_col_f16_f32       = 1477,
    1493             :     INT_WMMA_MMA_m32n8k16_col_col_f16_f32_satfinite     = 1478,
    1494             :     INT_WMMA_MMA_m32n8k16_col_col_f32_f16       = 1479,
    1495             :     INT_WMMA_MMA_m32n8k16_col_col_f32_f16_satfinite     = 1480,
    1496             :     INT_WMMA_MMA_m32n8k16_col_col_f32_f32       = 1481,
    1497             :     INT_WMMA_MMA_m32n8k16_col_col_f32_f32_satfinite     = 1482,
    1498             :     INT_WMMA_MMA_m32n8k16_col_row_f16_f16       = 1483,
    1499             :     INT_WMMA_MMA_m32n8k16_col_row_f16_f16_satfinite     = 1484,
    1500             :     INT_WMMA_MMA_m32n8k16_col_row_f16_f32       = 1485,
    1501             :     INT_WMMA_MMA_m32n8k16_col_row_f16_f32_satfinite     = 1486,
    1502             :     INT_WMMA_MMA_m32n8k16_col_row_f32_f16       = 1487,
    1503             :     INT_WMMA_MMA_m32n8k16_col_row_f32_f16_satfinite     = 1488,
    1504             :     INT_WMMA_MMA_m32n8k16_col_row_f32_f32       = 1489,
    1505             :     INT_WMMA_MMA_m32n8k16_col_row_f32_f32_satfinite     = 1490,
    1506             :     INT_WMMA_MMA_m32n8k16_row_col_f16_f16       = 1491,
    1507             :     INT_WMMA_MMA_m32n8k16_row_col_f16_f16_satfinite     = 1492,
    1508             :     INT_WMMA_MMA_m32n8k16_row_col_f16_f32       = 1493,
    1509             :     INT_WMMA_MMA_m32n8k16_row_col_f16_f32_satfinite     = 1494,
    1510             :     INT_WMMA_MMA_m32n8k16_row_col_f32_f16       = 1495,
    1511             :     INT_WMMA_MMA_m32n8k16_row_col_f32_f16_satfinite     = 1496,
    1512             :     INT_WMMA_MMA_m32n8k16_row_col_f32_f32       = 1497,
    1513             :     INT_WMMA_MMA_m32n8k16_row_col_f32_f32_satfinite     = 1498,
    1514             :     INT_WMMA_MMA_m32n8k16_row_row_f16_f16       = 1499,
    1515             :     INT_WMMA_MMA_m32n8k16_row_row_f16_f16_satfinite     = 1500,
    1516             :     INT_WMMA_MMA_m32n8k16_row_row_f16_f32       = 1501,
    1517             :     INT_WMMA_MMA_m32n8k16_row_row_f16_f32_satfinite     = 1502,
    1518             :     INT_WMMA_MMA_m32n8k16_row_row_f32_f16       = 1503,
    1519             :     INT_WMMA_MMA_m32n8k16_row_row_f32_f16_satfinite     = 1504,
    1520             :     INT_WMMA_MMA_m32n8k16_row_row_f32_f32       = 1505,
    1521             :     INT_WMMA_MMA_m32n8k16_row_row_f32_f32_satfinite     = 1506,
    1522             :     INT_WMMA_MMA_m8n32k16_col_col_f16_f16       = 1507,
    1523             :     INT_WMMA_MMA_m8n32k16_col_col_f16_f16_satfinite     = 1508,
    1524             :     INT_WMMA_MMA_m8n32k16_col_col_f16_f32       = 1509,
    1525             :     INT_WMMA_MMA_m8n32k16_col_col_f16_f32_satfinite     = 1510,
    1526             :     INT_WMMA_MMA_m8n32k16_col_col_f32_f16       = 1511,
    1527             :     INT_WMMA_MMA_m8n32k16_col_col_f32_f16_satfinite     = 1512,
    1528             :     INT_WMMA_MMA_m8n32k16_col_col_f32_f32       = 1513,
    1529             :     INT_WMMA_MMA_m8n32k16_col_col_f32_f32_satfinite     = 1514,
    1530             :     INT_WMMA_MMA_m8n32k16_col_row_f16_f16       = 1515,
    1531             :     INT_WMMA_MMA_m8n32k16_col_row_f16_f16_satfinite     = 1516,
    1532             :     INT_WMMA_MMA_m8n32k16_col_row_f16_f32       = 1517,
    1533             :     INT_WMMA_MMA_m8n32k16_col_row_f16_f32_satfinite     = 1518,
    1534             :     INT_WMMA_MMA_m8n32k16_col_row_f32_f16       = 1519,
    1535             :     INT_WMMA_MMA_m8n32k16_col_row_f32_f16_satfinite     = 1520,
    1536             :     INT_WMMA_MMA_m8n32k16_col_row_f32_f32       = 1521,
    1537             :     INT_WMMA_MMA_m8n32k16_col_row_f32_f32_satfinite     = 1522,
    1538             :     INT_WMMA_MMA_m8n32k16_row_col_f16_f16       = 1523,
    1539             :     INT_WMMA_MMA_m8n32k16_row_col_f16_f16_satfinite     = 1524,
    1540             :     INT_WMMA_MMA_m8n32k16_row_col_f16_f32       = 1525,
    1541             :     INT_WMMA_MMA_m8n32k16_row_col_f16_f32_satfinite     = 1526,
    1542             :     INT_WMMA_MMA_m8n32k16_row_col_f32_f16       = 1527,
    1543             :     INT_WMMA_MMA_m8n32k16_row_col_f32_f16_satfinite     = 1528,
    1544             :     INT_WMMA_MMA_m8n32k16_row_col_f32_f32       = 1529,
    1545             :     INT_WMMA_MMA_m8n32k16_row_col_f32_f32_satfinite     = 1530,
    1546             :     INT_WMMA_MMA_m8n32k16_row_row_f16_f16       = 1531,
    1547             :     INT_WMMA_MMA_m8n32k16_row_row_f16_f16_satfinite     = 1532,
    1548             :     INT_WMMA_MMA_m8n32k16_row_row_f16_f32       = 1533,
    1549             :     INT_WMMA_MMA_m8n32k16_row_row_f16_f32_satfinite     = 1534,
    1550             :     INT_WMMA_MMA_m8n32k16_row_row_f32_f16       = 1535,
    1551             :     INT_WMMA_MMA_m8n32k16_row_row_f32_f16_satfinite     = 1536,
    1552             :     INT_WMMA_MMA_m8n32k16_row_row_f32_f32       = 1537,
    1553             :     INT_WMMA_MMA_m8n32k16_row_row_f32_f32_satfinite     = 1538,
    1554             :     INT_WMMA_m16n16k16_load_a_col_areg  = 1539,
    1555             :     INT_WMMA_m16n16k16_load_a_col_areg64        = 1540,
    1556             :     INT_WMMA_m16n16k16_load_a_col_ari   = 1541,
    1557             :     INT_WMMA_m16n16k16_load_a_col_ari64 = 1542,
    1558             :     INT_WMMA_m16n16k16_load_a_col_avar  = 1543,
    1559             :     INT_WMMA_m16n16k16_load_a_col_global_areg   = 1544,
    1560             :     INT_WMMA_m16n16k16_load_a_col_global_areg64 = 1545,
    1561             :     INT_WMMA_m16n16k16_load_a_col_global_ari    = 1546,
    1562             :     INT_WMMA_m16n16k16_load_a_col_global_ari64  = 1547,
    1563             :     INT_WMMA_m16n16k16_load_a_col_global_avar   = 1548,
    1564             :     INT_WMMA_m16n16k16_load_a_col_global_stride_areg    = 1549,
    1565             :     INT_WMMA_m16n16k16_load_a_col_global_stride_areg64  = 1550,
    1566             :     INT_WMMA_m16n16k16_load_a_col_global_stride_ari     = 1551,
    1567             :     INT_WMMA_m16n16k16_load_a_col_global_stride_ari64   = 1552,
    1568             :     INT_WMMA_m16n16k16_load_a_col_global_stride_avar    = 1553,
    1569             :     INT_WMMA_m16n16k16_load_a_col_shared_areg   = 1554,
    1570             :     INT_WMMA_m16n16k16_load_a_col_shared_areg64 = 1555,
    1571             :     INT_WMMA_m16n16k16_load_a_col_shared_ari    = 1556,
    1572             :     INT_WMMA_m16n16k16_load_a_col_shared_ari64  = 1557,
    1573             :     INT_WMMA_m16n16k16_load_a_col_shared_avar   = 1558,
    1574             :     INT_WMMA_m16n16k16_load_a_col_shared_stride_areg    = 1559,
    1575             :     INT_WMMA_m16n16k16_load_a_col_shared_stride_areg64  = 1560,
    1576             :     INT_WMMA_m16n16k16_load_a_col_shared_stride_ari     = 1561,
    1577             :     INT_WMMA_m16n16k16_load_a_col_shared_stride_ari64   = 1562,
    1578             :     INT_WMMA_m16n16k16_load_a_col_shared_stride_avar    = 1563,
    1579             :     INT_WMMA_m16n16k16_load_a_col_stride_areg   = 1564,
    1580             :     INT_WMMA_m16n16k16_load_a_col_stride_areg64 = 1565,
    1581             :     INT_WMMA_m16n16k16_load_a_col_stride_ari    = 1566,
    1582             :     INT_WMMA_m16n16k16_load_a_col_stride_ari64  = 1567,
    1583             :     INT_WMMA_m16n16k16_load_a_col_stride_avar   = 1568,
    1584             :     INT_WMMA_m16n16k16_load_a_row_areg  = 1569,
    1585             :     INT_WMMA_m16n16k16_load_a_row_areg64        = 1570,
    1586             :     INT_WMMA_m16n16k16_load_a_row_ari   = 1571,
    1587             :     INT_WMMA_m16n16k16_load_a_row_ari64 = 1572,
    1588             :     INT_WMMA_m16n16k16_load_a_row_avar  = 1573,
    1589             :     INT_WMMA_m16n16k16_load_a_row_global_areg   = 1574,
    1590             :     INT_WMMA_m16n16k16_load_a_row_global_areg64 = 1575,
    1591             :     INT_WMMA_m16n16k16_load_a_row_global_ari    = 1576,
    1592             :     INT_WMMA_m16n16k16_load_a_row_global_ari64  = 1577,
    1593             :     INT_WMMA_m16n16k16_load_a_row_global_avar   = 1578,
    1594             :     INT_WMMA_m16n16k16_load_a_row_global_stride_areg    = 1579,
    1595             :     INT_WMMA_m16n16k16_load_a_row_global_stride_areg64  = 1580,
    1596             :     INT_WMMA_m16n16k16_load_a_row_global_stride_ari     = 1581,
    1597             :     INT_WMMA_m16n16k16_load_a_row_global_stride_ari64   = 1582,
    1598             :     INT_WMMA_m16n16k16_load_a_row_global_stride_avar    = 1583,
    1599             :     INT_WMMA_m16n16k16_load_a_row_shared_areg   = 1584,
    1600             :     INT_WMMA_m16n16k16_load_a_row_shared_areg64 = 1585,
    1601             :     INT_WMMA_m16n16k16_load_a_row_shared_ari    = 1586,
    1602             :     INT_WMMA_m16n16k16_load_a_row_shared_ari64  = 1587,
    1603             :     INT_WMMA_m16n16k16_load_a_row_shared_avar   = 1588,
    1604             :     INT_WMMA_m16n16k16_load_a_row_shared_stride_areg    = 1589,
    1605             :     INT_WMMA_m16n16k16_load_a_row_shared_stride_areg64  = 1590,
    1606             :     INT_WMMA_m16n16k16_load_a_row_shared_stride_ari     = 1591,
    1607             :     INT_WMMA_m16n16k16_load_a_row_shared_stride_ari64   = 1592,
    1608             :     INT_WMMA_m16n16k16_load_a_row_shared_stride_avar    = 1593,
    1609             :     INT_WMMA_m16n16k16_load_a_row_stride_areg   = 1594,
    1610             :     INT_WMMA_m16n16k16_load_a_row_stride_areg64 = 1595,
    1611             :     INT_WMMA_m16n16k16_load_a_row_stride_ari    = 1596,
    1612             :     INT_WMMA_m16n16k16_load_a_row_stride_ari64  = 1597,
    1613             :     INT_WMMA_m16n16k16_load_a_row_stride_avar   = 1598,
    1614             :     INT_WMMA_m16n16k16_load_b_col_areg  = 1599,
    1615             :     INT_WMMA_m16n16k16_load_b_col_areg64        = 1600,
    1616             :     INT_WMMA_m16n16k16_load_b_col_ari   = 1601,
    1617             :     INT_WMMA_m16n16k16_load_b_col_ari64 = 1602,
    1618             :     INT_WMMA_m16n16k16_load_b_col_avar  = 1603,
    1619             :     INT_WMMA_m16n16k16_load_b_col_global_areg   = 1604,
    1620             :     INT_WMMA_m16n16k16_load_b_col_global_areg64 = 1605,
    1621             :     INT_WMMA_m16n16k16_load_b_col_global_ari    = 1606,
    1622             :     INT_WMMA_m16n16k16_load_b_col_global_ari64  = 1607,
    1623             :     INT_WMMA_m16n16k16_load_b_col_global_avar   = 1608,
    1624             :     INT_WMMA_m16n16k16_load_b_col_global_stride_areg    = 1609,
    1625             :     INT_WMMA_m16n16k16_load_b_col_global_stride_areg64  = 1610,
    1626             :     INT_WMMA_m16n16k16_load_b_col_global_stride_ari     = 1611,
    1627             :     INT_WMMA_m16n16k16_load_b_col_global_stride_ari64   = 1612,
    1628             :     INT_WMMA_m16n16k16_load_b_col_global_stride_avar    = 1613,
    1629             :     INT_WMMA_m16n16k16_load_b_col_shared_areg   = 1614,
    1630             :     INT_WMMA_m16n16k16_load_b_col_shared_areg64 = 1615,
    1631             :     INT_WMMA_m16n16k16_load_b_col_shared_ari    = 1616,
    1632             :     INT_WMMA_m16n16k16_load_b_col_shared_ari64  = 1617,
    1633             :     INT_WMMA_m16n16k16_load_b_col_shared_avar   = 1618,
    1634             :     INT_WMMA_m16n16k16_load_b_col_shared_stride_areg    = 1619,
    1635             :     INT_WMMA_m16n16k16_load_b_col_shared_stride_areg64  = 1620,
    1636             :     INT_WMMA_m16n16k16_load_b_col_shared_stride_ari     = 1621,
    1637             :     INT_WMMA_m16n16k16_load_b_col_shared_stride_ari64   = 1622,
    1638             :     INT_WMMA_m16n16k16_load_b_col_shared_stride_avar    = 1623,
    1639             :     INT_WMMA_m16n16k16_load_b_col_stride_areg   = 1624,
    1640             :     INT_WMMA_m16n16k16_load_b_col_stride_areg64 = 1625,
    1641             :     INT_WMMA_m16n16k16_load_b_col_stride_ari    = 1626,
    1642             :     INT_WMMA_m16n16k16_load_b_col_stride_ari64  = 1627,
    1643             :     INT_WMMA_m16n16k16_load_b_col_stride_avar   = 1628,
    1644             :     INT_WMMA_m16n16k16_load_b_row_areg  = 1629,
    1645             :     INT_WMMA_m16n16k16_load_b_row_areg64        = 1630,
    1646             :     INT_WMMA_m16n16k16_load_b_row_ari   = 1631,
    1647             :     INT_WMMA_m16n16k16_load_b_row_ari64 = 1632,
    1648             :     INT_WMMA_m16n16k16_load_b_row_avar  = 1633,
    1649             :     INT_WMMA_m16n16k16_load_b_row_global_areg   = 1634,
    1650             :     INT_WMMA_m16n16k16_load_b_row_global_areg64 = 1635,
    1651             :     INT_WMMA_m16n16k16_load_b_row_global_ari    = 1636,
    1652             :     INT_WMMA_m16n16k16_load_b_row_global_ari64  = 1637,
    1653             :     INT_WMMA_m16n16k16_load_b_row_global_avar   = 1638,
    1654             :     INT_WMMA_m16n16k16_load_b_row_global_stride_areg    = 1639,
    1655             :     INT_WMMA_m16n16k16_load_b_row_global_stride_areg64  = 1640,
    1656             :     INT_WMMA_m16n16k16_load_b_row_global_stride_ari     = 1641,
    1657             :     INT_WMMA_m16n16k16_load_b_row_global_stride_ari64   = 1642,
    1658             :     INT_WMMA_m16n16k16_load_b_row_global_stride_avar    = 1643,
    1659             :     INT_WMMA_m16n16k16_load_b_row_shared_areg   = 1644,
    1660             :     INT_WMMA_m16n16k16_load_b_row_shared_areg64 = 1645,
    1661             :     INT_WMMA_m16n16k16_load_b_row_shared_ari    = 1646,
    1662             :     INT_WMMA_m16n16k16_load_b_row_shared_ari64  = 1647,
    1663             :     INT_WMMA_m16n16k16_load_b_row_shared_avar   = 1648,
    1664             :     INT_WMMA_m16n16k16_load_b_row_shared_stride_areg    = 1649,
    1665             :     INT_WMMA_m16n16k16_load_b_row_shared_stride_areg64  = 1650,
    1666             :     INT_WMMA_m16n16k16_load_b_row_shared_stride_ari     = 1651,
    1667             :     INT_WMMA_m16n16k16_load_b_row_shared_stride_ari64   = 1652,
    1668             :     INT_WMMA_m16n16k16_load_b_row_shared_stride_avar    = 1653,
    1669             :     INT_WMMA_m16n16k16_load_b_row_stride_areg   = 1654,
    1670             :     INT_WMMA_m16n16k16_load_b_row_stride_areg64 = 1655,
    1671             :     INT_WMMA_m16n16k16_load_b_row_stride_ari    = 1656,
    1672             :     INT_WMMA_m16n16k16_load_b_row_stride_ari64  = 1657,
    1673             :     INT_WMMA_m16n16k16_load_b_row_stride_avar   = 1658,
    1674             :     INT_WMMA_m16n16k16_load_c_f16_col_areg      = 1659,
    1675             :     INT_WMMA_m16n16k16_load_c_f16_col_areg64    = 1660,
    1676             :     INT_WMMA_m16n16k16_load_c_f16_col_ari       = 1661,
    1677             :     INT_WMMA_m16n16k16_load_c_f16_col_ari64     = 1662,
    1678             :     INT_WMMA_m16n16k16_load_c_f16_col_avar      = 1663,
    1679             :     INT_WMMA_m16n16k16_load_c_f16_col_global_areg       = 1664,
    1680             :     INT_WMMA_m16n16k16_load_c_f16_col_global_areg64     = 1665,
    1681             :     INT_WMMA_m16n16k16_load_c_f16_col_global_ari        = 1666,
    1682             :     INT_WMMA_m16n16k16_load_c_f16_col_global_ari64      = 1667,
    1683             :     INT_WMMA_m16n16k16_load_c_f16_col_global_avar       = 1668,
    1684             :     INT_WMMA_m16n16k16_load_c_f16_col_global_stride_areg        = 1669,
    1685             :     INT_WMMA_m16n16k16_load_c_f16_col_global_stride_areg64      = 1670,
    1686             :     INT_WMMA_m16n16k16_load_c_f16_col_global_stride_ari = 1671,
    1687             :     INT_WMMA_m16n16k16_load_c_f16_col_global_stride_ari64       = 1672,
    1688             :     INT_WMMA_m16n16k16_load_c_f16_col_global_stride_avar        = 1673,
    1689             :     INT_WMMA_m16n16k16_load_c_f16_col_shared_areg       = 1674,
    1690             :     INT_WMMA_m16n16k16_load_c_f16_col_shared_areg64     = 1675,
    1691             :     INT_WMMA_m16n16k16_load_c_f16_col_shared_ari        = 1676,
    1692             :     INT_WMMA_m16n16k16_load_c_f16_col_shared_ari64      = 1677,
    1693             :     INT_WMMA_m16n16k16_load_c_f16_col_shared_avar       = 1678,
    1694             :     INT_WMMA_m16n16k16_load_c_f16_col_shared_stride_areg        = 1679,
    1695             :     INT_WMMA_m16n16k16_load_c_f16_col_shared_stride_areg64      = 1680,
    1696             :     INT_WMMA_m16n16k16_load_c_f16_col_shared_stride_ari = 1681,
    1697             :     INT_WMMA_m16n16k16_load_c_f16_col_shared_stride_ari64       = 1682,
    1698             :     INT_WMMA_m16n16k16_load_c_f16_col_shared_stride_avar        = 1683,
    1699             :     INT_WMMA_m16n16k16_load_c_f16_col_stride_areg       = 1684,
    1700             :     INT_WMMA_m16n16k16_load_c_f16_col_stride_areg64     = 1685,
    1701             :     INT_WMMA_m16n16k16_load_c_f16_col_stride_ari        = 1686,
    1702             :     INT_WMMA_m16n16k16_load_c_f16_col_stride_ari64      = 1687,
    1703             :     INT_WMMA_m16n16k16_load_c_f16_col_stride_avar       = 1688,
    1704             :     INT_WMMA_m16n16k16_load_c_f16_row_areg      = 1689,
    1705             :     INT_WMMA_m16n16k16_load_c_f16_row_areg64    = 1690,
    1706             :     INT_WMMA_m16n16k16_load_c_f16_row_ari       = 1691,
    1707             :     INT_WMMA_m16n16k16_load_c_f16_row_ari64     = 1692,
    1708             :     INT_WMMA_m16n16k16_load_c_f16_row_avar      = 1693,
    1709             :     INT_WMMA_m16n16k16_load_c_f16_row_global_areg       = 1694,
    1710             :     INT_WMMA_m16n16k16_load_c_f16_row_global_areg64     = 1695,
    1711             :     INT_WMMA_m16n16k16_load_c_f16_row_global_ari        = 1696,
    1712             :     INT_WMMA_m16n16k16_load_c_f16_row_global_ari64      = 1697,
    1713             :     INT_WMMA_m16n16k16_load_c_f16_row_global_avar       = 1698,
    1714             :     INT_WMMA_m16n16k16_load_c_f16_row_global_stride_areg        = 1699,
    1715             :     INT_WMMA_m16n16k16_load_c_f16_row_global_stride_areg64      = 1700,
    1716             :     INT_WMMA_m16n16k16_load_c_f16_row_global_stride_ari = 1701,
    1717             :     INT_WMMA_m16n16k16_load_c_f16_row_global_stride_ari64       = 1702,
    1718             :     INT_WMMA_m16n16k16_load_c_f16_row_global_stride_avar        = 1703,
    1719             :     INT_WMMA_m16n16k16_load_c_f16_row_shared_areg       = 1704,
    1720             :     INT_WMMA_m16n16k16_load_c_f16_row_shared_areg64     = 1705,
    1721             :     INT_WMMA_m16n16k16_load_c_f16_row_shared_ari        = 1706,
    1722             :     INT_WMMA_m16n16k16_load_c_f16_row_shared_ari64      = 1707,
    1723             :     INT_WMMA_m16n16k16_load_c_f16_row_shared_avar       = 1708,
    1724             :     INT_WMMA_m16n16k16_load_c_f16_row_shared_stride_areg        = 1709,
    1725             :     INT_WMMA_m16n16k16_load_c_f16_row_shared_stride_areg64      = 1710,
    1726             :     INT_WMMA_m16n16k16_load_c_f16_row_shared_stride_ari = 1711,
    1727             :     INT_WMMA_m16n16k16_load_c_f16_row_shared_stride_ari64       = 1712,
    1728             :     INT_WMMA_m16n16k16_load_c_f16_row_shared_stride_avar        = 1713,
    1729             :     INT_WMMA_m16n16k16_load_c_f16_row_stride_areg       = 1714,
    1730             :     INT_WMMA_m16n16k16_load_c_f16_row_stride_areg64     = 1715,
    1731             :     INT_WMMA_m16n16k16_load_c_f16_row_stride_ari        = 1716,
    1732             :     INT_WMMA_m16n16k16_load_c_f16_row_stride_ari64      = 1717,
    1733             :     INT_WMMA_m16n16k16_load_c_f16_row_stride_avar       = 1718,
    1734             :     INT_WMMA_m16n16k16_load_c_f32_col_areg      = 1719,
    1735             :     INT_WMMA_m16n16k16_load_c_f32_col_areg64    = 1720,
    1736             :     INT_WMMA_m16n16k16_load_c_f32_col_ari       = 1721,
    1737             :     INT_WMMA_m16n16k16_load_c_f32_col_ari64     = 1722,
    1738             :     INT_WMMA_m16n16k16_load_c_f32_col_avar      = 1723,
    1739             :     INT_WMMA_m16n16k16_load_c_f32_col_global_areg       = 1724,
    1740             :     INT_WMMA_m16n16k16_load_c_f32_col_global_areg64     = 1725,
    1741             :     INT_WMMA_m16n16k16_load_c_f32_col_global_ari        = 1726,
    1742             :     INT_WMMA_m16n16k16_load_c_f32_col_global_ari64      = 1727,
    1743             :     INT_WMMA_m16n16k16_load_c_f32_col_global_avar       = 1728,
    1744             :     INT_WMMA_m16n16k16_load_c_f32_col_global_stride_areg        = 1729,
    1745             :     INT_WMMA_m16n16k16_load_c_f32_col_global_stride_areg64      = 1730,
    1746             :     INT_WMMA_m16n16k16_load_c_f32_col_global_stride_ari = 1731,
    1747             :     INT_WMMA_m16n16k16_load_c_f32_col_global_stride_ari64       = 1732,
    1748             :     INT_WMMA_m16n16k16_load_c_f32_col_global_stride_avar        = 1733,
    1749             :     INT_WMMA_m16n16k16_load_c_f32_col_shared_areg       = 1734,
    1750             :     INT_WMMA_m16n16k16_load_c_f32_col_shared_areg64     = 1735,
    1751             :     INT_WMMA_m16n16k16_load_c_f32_col_shared_ari        = 1736,
    1752             :     INT_WMMA_m16n16k16_load_c_f32_col_shared_ari64      = 1737,
    1753             :     INT_WMMA_m16n16k16_load_c_f32_col_shared_avar       = 1738,
    1754             :     INT_WMMA_m16n16k16_load_c_f32_col_shared_stride_areg        = 1739,
    1755             :     INT_WMMA_m16n16k16_load_c_f32_col_shared_stride_areg64      = 1740,
    1756             :     INT_WMMA_m16n16k16_load_c_f32_col_shared_stride_ari = 1741,
    1757             :     INT_WMMA_m16n16k16_load_c_f32_col_shared_stride_ari64       = 1742,
    1758             :     INT_WMMA_m16n16k16_load_c_f32_col_shared_stride_avar        = 1743,
    1759             :     INT_WMMA_m16n16k16_load_c_f32_col_stride_areg       = 1744,
    1760             :     INT_WMMA_m16n16k16_load_c_f32_col_stride_areg64     = 1745,
    1761             :     INT_WMMA_m16n16k16_load_c_f32_col_stride_ari        = 1746,
    1762             :     INT_WMMA_m16n16k16_load_c_f32_col_stride_ari64      = 1747,
    1763             :     INT_WMMA_m16n16k16_load_c_f32_col_stride_avar       = 1748,
    1764             :     INT_WMMA_m16n16k16_load_c_f32_row_areg      = 1749,
    1765             :     INT_WMMA_m16n16k16_load_c_f32_row_areg64    = 1750,
    1766             :     INT_WMMA_m16n16k16_load_c_f32_row_ari       = 1751,
    1767             :     INT_WMMA_m16n16k16_load_c_f32_row_ari64     = 1752,
    1768             :     INT_WMMA_m16n16k16_load_c_f32_row_avar      = 1753,
    1769             :     INT_WMMA_m16n16k16_load_c_f32_row_global_areg       = 1754,
    1770             :     INT_WMMA_m16n16k16_load_c_f32_row_global_areg64     = 1755,
    1771             :     INT_WMMA_m16n16k16_load_c_f32_row_global_ari        = 1756,
    1772             :     INT_WMMA_m16n16k16_load_c_f32_row_global_ari64      = 1757,
    1773             :     INT_WMMA_m16n16k16_load_c_f32_row_global_avar       = 1758,
    1774             :     INT_WMMA_m16n16k16_load_c_f32_row_global_stride_areg        = 1759,
    1775             :     INT_WMMA_m16n16k16_load_c_f32_row_global_stride_areg64      = 1760,
    1776             :     INT_WMMA_m16n16k16_load_c_f32_row_global_stride_ari = 1761,
    1777             :     INT_WMMA_m16n16k16_load_c_f32_row_global_stride_ari64       = 1762,
    1778             :     INT_WMMA_m16n16k16_load_c_f32_row_global_stride_avar        = 1763,
    1779             :     INT_WMMA_m16n16k16_load_c_f32_row_shared_areg       = 1764,
    1780             :     INT_WMMA_m16n16k16_load_c_f32_row_shared_areg64     = 1765,
    1781             :     INT_WMMA_m16n16k16_load_c_f32_row_shared_ari        = 1766,
    1782             :     INT_WMMA_m16n16k16_load_c_f32_row_shared_ari64      = 1767,
    1783             :     INT_WMMA_m16n16k16_load_c_f32_row_shared_avar       = 1768,
    1784             :     INT_WMMA_m16n16k16_load_c_f32_row_shared_stride_areg        = 1769,
    1785             :     INT_WMMA_m16n16k16_load_c_f32_row_shared_stride_areg64      = 1770,
    1786             :     INT_WMMA_m16n16k16_load_c_f32_row_shared_stride_ari = 1771,
    1787             :     INT_WMMA_m16n16k16_load_c_f32_row_shared_stride_ari64       = 1772,
    1788             :     INT_WMMA_m16n16k16_load_c_f32_row_shared_stride_avar        = 1773,
    1789             :     INT_WMMA_m16n16k16_load_c_f32_row_stride_areg       = 1774,
    1790             :     INT_WMMA_m16n16k16_load_c_f32_row_stride_areg64     = 1775,
    1791             :     INT_WMMA_m16n16k16_load_c_f32_row_stride_ari        = 1776,
    1792             :     INT_WMMA_m16n16k16_load_c_f32_row_stride_ari64      = 1777,
    1793             :     INT_WMMA_m16n16k16_load_c_f32_row_stride_avar       = 1778,
    1794             :     INT_WMMA_m16n16k16_store_d_f16_col_areg     = 1779,
    1795             :     INT_WMMA_m16n16k16_store_d_f16_col_areg64   = 1780,
    1796             :     INT_WMMA_m16n16k16_store_d_f16_col_ari      = 1781,
    1797             :     INT_WMMA_m16n16k16_store_d_f16_col_ari64    = 1782,
    1798             :     INT_WMMA_m16n16k16_store_d_f16_col_avar     = 1783,
    1799             :     INT_WMMA_m16n16k16_store_d_f16_col_global_areg      = 1784,
    1800             :     INT_WMMA_m16n16k16_store_d_f16_col_global_areg64    = 1785,
    1801             :     INT_WMMA_m16n16k16_store_d_f16_col_global_ari       = 1786,
    1802             :     INT_WMMA_m16n16k16_store_d_f16_col_global_ari64     = 1787,
    1803             :     INT_WMMA_m16n16k16_store_d_f16_col_global_avar      = 1788,
    1804             :     INT_WMMA_m16n16k16_store_d_f16_col_global_stride_areg       = 1789,
    1805             :     INT_WMMA_m16n16k16_store_d_f16_col_global_stride_areg64     = 1790,
    1806             :     INT_WMMA_m16n16k16_store_d_f16_col_global_stride_ari        = 1791,
    1807             :     INT_WMMA_m16n16k16_store_d_f16_col_global_stride_ari64      = 1792,
    1808             :     INT_WMMA_m16n16k16_store_d_f16_col_global_stride_avar       = 1793,
    1809             :     INT_WMMA_m16n16k16_store_d_f16_col_shared_areg      = 1794,
    1810             :     INT_WMMA_m16n16k16_store_d_f16_col_shared_areg64    = 1795,
    1811             :     INT_WMMA_m16n16k16_store_d_f16_col_shared_ari       = 1796,
    1812             :     INT_WMMA_m16n16k16_store_d_f16_col_shared_ari64     = 1797,
    1813             :     INT_WMMA_m16n16k16_store_d_f16_col_shared_avar      = 1798,
    1814             :     INT_WMMA_m16n16k16_store_d_f16_col_shared_stride_areg       = 1799,
    1815             :     INT_WMMA_m16n16k16_store_d_f16_col_shared_stride_areg64     = 1800,
    1816             :     INT_WMMA_m16n16k16_store_d_f16_col_shared_stride_ari        = 1801,
    1817             :     INT_WMMA_m16n16k16_store_d_f16_col_shared_stride_ari64      = 1802,
    1818             :     INT_WMMA_m16n16k16_store_d_f16_col_shared_stride_avar       = 1803,
    1819             :     INT_WMMA_m16n16k16_store_d_f16_col_stride_areg      = 1804,
    1820             :     INT_WMMA_m16n16k16_store_d_f16_col_stride_areg64    = 1805,
    1821             :     INT_WMMA_m16n16k16_store_d_f16_col_stride_ari       = 1806,
    1822             :     INT_WMMA_m16n16k16_store_d_f16_col_stride_ari64     = 1807,
    1823             :     INT_WMMA_m16n16k16_store_d_f16_col_stride_avar      = 1808,
    1824             :     INT_WMMA_m16n16k16_store_d_f16_row_areg     = 1809,
    1825             :     INT_WMMA_m16n16k16_store_d_f16_row_areg64   = 1810,
    1826             :     INT_WMMA_m16n16k16_store_d_f16_row_ari      = 1811,
    1827             :     INT_WMMA_m16n16k16_store_d_f16_row_ari64    = 1812,
    1828             :     INT_WMMA_m16n16k16_store_d_f16_row_avar     = 1813,
    1829             :     INT_WMMA_m16n16k16_store_d_f16_row_global_areg      = 1814,
    1830             :     INT_WMMA_m16n16k16_store_d_f16_row_global_areg64    = 1815,
    1831             :     INT_WMMA_m16n16k16_store_d_f16_row_global_ari       = 1816,
    1832             :     INT_WMMA_m16n16k16_store_d_f16_row_global_ari64     = 1817,
    1833             :     INT_WMMA_m16n16k16_store_d_f16_row_global_avar      = 1818,
    1834             :     INT_WMMA_m16n16k16_store_d_f16_row_global_stride_areg       = 1819,
    1835             :     INT_WMMA_m16n16k16_store_d_f16_row_global_stride_areg64     = 1820,
    1836             :     INT_WMMA_m16n16k16_store_d_f16_row_global_stride_ari        = 1821,
    1837             :     INT_WMMA_m16n16k16_store_d_f16_row_global_stride_ari64      = 1822,
    1838             :     INT_WMMA_m16n16k16_store_d_f16_row_global_stride_avar       = 1823,
    1839             :     INT_WMMA_m16n16k16_store_d_f16_row_shared_areg      = 1824,
    1840             :     INT_WMMA_m16n16k16_store_d_f16_row_shared_areg64    = 1825,
    1841             :     INT_WMMA_m16n16k16_store_d_f16_row_shared_ari       = 1826,
    1842             :     INT_WMMA_m16n16k16_store_d_f16_row_shared_ari64     = 1827,
    1843             :     INT_WMMA_m16n16k16_store_d_f16_row_shared_avar      = 1828,
    1844             :     INT_WMMA_m16n16k16_store_d_f16_row_shared_stride_areg       = 1829,
    1845             :     INT_WMMA_m16n16k16_store_d_f16_row_shared_stride_areg64     = 1830,
    1846             :     INT_WMMA_m16n16k16_store_d_f16_row_shared_stride_ari        = 1831,
    1847             :     INT_WMMA_m16n16k16_store_d_f16_row_shared_stride_ari64      = 1832,
    1848             :     INT_WMMA_m16n16k16_store_d_f16_row_shared_stride_avar       = 1833,
    1849             :     INT_WMMA_m16n16k16_store_d_f16_row_stride_areg      = 1834,
    1850             :     INT_WMMA_m16n16k16_store_d_f16_row_stride_areg64    = 1835,
    1851             :     INT_WMMA_m16n16k16_store_d_f16_row_stride_ari       = 1836,
    1852             :     INT_WMMA_m16n16k16_store_d_f16_row_stride_ari64     = 1837,
    1853             :     INT_WMMA_m16n16k16_store_d_f16_row_stride_avar      = 1838,
    1854             :     INT_WMMA_m16n16k16_store_d_f32_col_areg     = 1839,
    1855             :     INT_WMMA_m16n16k16_store_d_f32_col_areg64   = 1840,
    1856             :     INT_WMMA_m16n16k16_store_d_f32_col_ari      = 1841,
    1857             :     INT_WMMA_m16n16k16_store_d_f32_col_ari64    = 1842,
    1858             :     INT_WMMA_m16n16k16_store_d_f32_col_avar     = 1843,
    1859             :     INT_WMMA_m16n16k16_store_d_f32_col_global_areg      = 1844,
    1860             :     INT_WMMA_m16n16k16_store_d_f32_col_global_areg64    = 1845,
    1861             :     INT_WMMA_m16n16k16_store_d_f32_col_global_ari       = 1846,
    1862             :     INT_WMMA_m16n16k16_store_d_f32_col_global_ari64     = 1847,
    1863             :     INT_WMMA_m16n16k16_store_d_f32_col_global_avar      = 1848,
    1864             :     INT_WMMA_m16n16k16_store_d_f32_col_global_stride_areg       = 1849,
    1865             :     INT_WMMA_m16n16k16_store_d_f32_col_global_stride_areg64     = 1850,
    1866             :     INT_WMMA_m16n16k16_store_d_f32_col_global_stride_ari        = 1851,
    1867             :     INT_WMMA_m16n16k16_store_d_f32_col_global_stride_ari64      = 1852,
    1868             :     INT_WMMA_m16n16k16_store_d_f32_col_global_stride_avar       = 1853,
    1869             :     INT_WMMA_m16n16k16_store_d_f32_col_shared_areg      = 1854,
    1870             :     INT_WMMA_m16n16k16_store_d_f32_col_shared_areg64    = 1855,
    1871             :     INT_WMMA_m16n16k16_store_d_f32_col_shared_ari       = 1856,
    1872             :     INT_WMMA_m16n16k16_store_d_f32_col_shared_ari64     = 1857,
    1873             :     INT_WMMA_m16n16k16_store_d_f32_col_shared_avar      = 1858,
    1874             :     INT_WMMA_m16n16k16_store_d_f32_col_shared_stride_areg       = 1859,
    1875             :     INT_WMMA_m16n16k16_store_d_f32_col_shared_stride_areg64     = 1860,
    1876             :     INT_WMMA_m16n16k16_store_d_f32_col_shared_stride_ari        = 1861,
    1877             :     INT_WMMA_m16n16k16_store_d_f32_col_shared_stride_ari64      = 1862,
    1878             :     INT_WMMA_m16n16k16_store_d_f32_col_shared_stride_avar       = 1863,
    1879             :     INT_WMMA_m16n16k16_store_d_f32_col_stride_areg      = 1864,
    1880             :     INT_WMMA_m16n16k16_store_d_f32_col_stride_areg64    = 1865,
    1881             :     INT_WMMA_m16n16k16_store_d_f32_col_stride_ari       = 1866,
    1882             :     INT_WMMA_m16n16k16_store_d_f32_col_stride_ari64     = 1867,
    1883             :     INT_WMMA_m16n16k16_store_d_f32_col_stride_avar      = 1868,
    1884             :     INT_WMMA_m16n16k16_store_d_f32_row_areg     = 1869,
    1885             :     INT_WMMA_m16n16k16_store_d_f32_row_areg64   = 1870,
    1886             :     INT_WMMA_m16n16k16_store_d_f32_row_ari      = 1871,
    1887             :     INT_WMMA_m16n16k16_store_d_f32_row_ari64    = 1872,
    1888             :     INT_WMMA_m16n16k16_store_d_f32_row_avar     = 1873,
    1889             :     INT_WMMA_m16n16k16_store_d_f32_row_global_areg      = 1874,
    1890             :     INT_WMMA_m16n16k16_store_d_f32_row_global_areg64    = 1875,
    1891             :     INT_WMMA_m16n16k16_store_d_f32_row_global_ari       = 1876,
    1892             :     INT_WMMA_m16n16k16_store_d_f32_row_global_ari64     = 1877,
    1893             :     INT_WMMA_m16n16k16_store_d_f32_row_global_avar      = 1878,
    1894             :     INT_WMMA_m16n16k16_store_d_f32_row_global_stride_areg       = 1879,
    1895             :     INT_WMMA_m16n16k16_store_d_f32_row_global_stride_areg64     = 1880,
    1896             :     INT_WMMA_m16n16k16_store_d_f32_row_global_stride_ari        = 1881,
    1897             :     INT_WMMA_m16n16k16_store_d_f32_row_global_stride_ari64      = 1882,
    1898             :     INT_WMMA_m16n16k16_store_d_f32_row_global_stride_avar       = 1883,
    1899             :     INT_WMMA_m16n16k16_store_d_f32_row_shared_areg      = 1884,
    1900             :     INT_WMMA_m16n16k16_store_d_f32_row_shared_areg64    = 1885,
    1901             :     INT_WMMA_m16n16k16_store_d_f32_row_shared_ari       = 1886,
    1902             :     INT_WMMA_m16n16k16_store_d_f32_row_shared_ari64     = 1887,
    1903             :     INT_WMMA_m16n16k16_store_d_f32_row_shared_avar      = 1888,
    1904             :     INT_WMMA_m16n16k16_store_d_f32_row_shared_stride_areg       = 1889,
    1905             :     INT_WMMA_m16n16k16_store_d_f32_row_shared_stride_areg64     = 1890,
    1906             :     INT_WMMA_m16n16k16_store_d_f32_row_shared_stride_ari        = 1891,
    1907             :     INT_WMMA_m16n16k16_store_d_f32_row_shared_stride_ari64      = 1892,
    1908             :     INT_WMMA_m16n16k16_store_d_f32_row_shared_stride_avar       = 1893,
    1909             :     INT_WMMA_m16n16k16_store_d_f32_row_stride_areg      = 1894,
    1910             :     INT_WMMA_m16n16k16_store_d_f32_row_stride_areg64    = 1895,
    1911             :     INT_WMMA_m16n16k16_store_d_f32_row_stride_ari       = 1896,
    1912             :     INT_WMMA_m16n16k16_store_d_f32_row_stride_ari64     = 1897,
    1913             :     INT_WMMA_m16n16k16_store_d_f32_row_stride_avar      = 1898,
    1914             :     INT_WMMA_m32n8k16_load_a_col_areg   = 1899,
    1915             :     INT_WMMA_m32n8k16_load_a_col_areg64 = 1900,
    1916             :     INT_WMMA_m32n8k16_load_a_col_ari    = 1901,
    1917             :     INT_WMMA_m32n8k16_load_a_col_ari64  = 1902,
    1918             :     INT_WMMA_m32n8k16_load_a_col_avar   = 1903,
    1919             :     INT_WMMA_m32n8k16_load_a_col_global_areg    = 1904,
    1920             :     INT_WMMA_m32n8k16_load_a_col_global_areg64  = 1905,
    1921             :     INT_WMMA_m32n8k16_load_a_col_global_ari     = 1906,
    1922             :     INT_WMMA_m32n8k16_load_a_col_global_ari64   = 1907,
    1923             :     INT_WMMA_m32n8k16_load_a_col_global_avar    = 1908,
    1924             :     INT_WMMA_m32n8k16_load_a_col_global_stride_areg     = 1909,
    1925             :     INT_WMMA_m32n8k16_load_a_col_global_stride_areg64   = 1910,
    1926             :     INT_WMMA_m32n8k16_load_a_col_global_stride_ari      = 1911,
    1927             :     INT_WMMA_m32n8k16_load_a_col_global_stride_ari64    = 1912,
    1928             :     INT_WMMA_m32n8k16_load_a_col_global_stride_avar     = 1913,
    1929             :     INT_WMMA_m32n8k16_load_a_col_shared_areg    = 1914,
    1930             :     INT_WMMA_m32n8k16_load_a_col_shared_areg64  = 1915,
    1931             :     INT_WMMA_m32n8k16_load_a_col_shared_ari     = 1916,
    1932             :     INT_WMMA_m32n8k16_load_a_col_shared_ari64   = 1917,
    1933             :     INT_WMMA_m32n8k16_load_a_col_shared_avar    = 1918,
    1934             :     INT_WMMA_m32n8k16_load_a_col_shared_stride_areg     = 1919,
    1935             :     INT_WMMA_m32n8k16_load_a_col_shared_stride_areg64   = 1920,
    1936             :     INT_WMMA_m32n8k16_load_a_col_shared_stride_ari      = 1921,
    1937             :     INT_WMMA_m32n8k16_load_a_col_shared_stride_ari64    = 1922,
    1938             :     INT_WMMA_m32n8k16_load_a_col_shared_stride_avar     = 1923,
    1939             :     INT_WMMA_m32n8k16_load_a_col_stride_areg    = 1924,
    1940             :     INT_WMMA_m32n8k16_load_a_col_stride_areg64  = 1925,
    1941             :     INT_WMMA_m32n8k16_load_a_col_stride_ari     = 1926,
    1942             :     INT_WMMA_m32n8k16_load_a_col_stride_ari64   = 1927,
    1943             :     INT_WMMA_m32n8k16_load_a_col_stride_avar    = 1928,
    1944             :     INT_WMMA_m32n8k16_load_a_row_areg   = 1929,
    1945             :     INT_WMMA_m32n8k16_load_a_row_areg64 = 1930,
    1946             :     INT_WMMA_m32n8k16_load_a_row_ari    = 1931,
    1947             :     INT_WMMA_m32n8k16_load_a_row_ari64  = 1932,
    1948             :     INT_WMMA_m32n8k16_load_a_row_avar   = 1933,
    1949             :     INT_WMMA_m32n8k16_load_a_row_global_areg    = 1934,
    1950             :     INT_WMMA_m32n8k16_load_a_row_global_areg64  = 1935,
    1951             :     INT_WMMA_m32n8k16_load_a_row_global_ari     = 1936,
    1952             :     INT_WMMA_m32n8k16_load_a_row_global_ari64   = 1937,
    1953             :     INT_WMMA_m32n8k16_load_a_row_global_avar    = 1938,
    1954             :     INT_WMMA_m32n8k16_load_a_row_global_stride_areg     = 1939,
    1955             :     INT_WMMA_m32n8k16_load_a_row_global_stride_areg64   = 1940,
    1956             :     INT_WMMA_m32n8k16_load_a_row_global_stride_ari      = 1941,
    1957             :     INT_WMMA_m32n8k16_load_a_row_global_stride_ari64    = 1942,
    1958             :     INT_WMMA_m32n8k16_load_a_row_global_stride_avar     = 1943,
    1959             :     INT_WMMA_m32n8k16_load_a_row_shared_areg    = 1944,
    1960             :     INT_WMMA_m32n8k16_load_a_row_shared_areg64  = 1945,
    1961             :     INT_WMMA_m32n8k16_load_a_row_shared_ari     = 1946,
    1962             :     INT_WMMA_m32n8k16_load_a_row_shared_ari64   = 1947,
    1963             :     INT_WMMA_m32n8k16_load_a_row_shared_avar    = 1948,
    1964             :     INT_WMMA_m32n8k16_load_a_row_shared_stride_areg     = 1949,
    1965             :     INT_WMMA_m32n8k16_load_a_row_shared_stride_areg64   = 1950,
    1966             :     INT_WMMA_m32n8k16_load_a_row_shared_stride_ari      = 1951,
    1967             :     INT_WMMA_m32n8k16_load_a_row_shared_stride_ari64    = 1952,
    1968             :     INT_WMMA_m32n8k16_load_a_row_shared_stride_avar     = 1953,
    1969             :     INT_WMMA_m32n8k16_load_a_row_stride_areg    = 1954,
    1970             :     INT_WMMA_m32n8k16_load_a_row_stride_areg64  = 1955,
    1971             :     INT_WMMA_m32n8k16_load_a_row_stride_ari     = 1956,
    1972             :     INT_WMMA_m32n8k16_load_a_row_stride_ari64   = 1957,
    1973             :     INT_WMMA_m32n8k16_load_a_row_stride_avar    = 1958,
    1974             :     INT_WMMA_m32n8k16_load_b_col_areg   = 1959,
    1975             :     INT_WMMA_m32n8k16_load_b_col_areg64 = 1960,
    1976             :     INT_WMMA_m32n8k16_load_b_col_ari    = 1961,
    1977             :     INT_WMMA_m32n8k16_load_b_col_ari64  = 1962,
    1978             :     INT_WMMA_m32n8k16_load_b_col_avar   = 1963,
    1979             :     INT_WMMA_m32n8k16_load_b_col_global_areg    = 1964,
    1980             :     INT_WMMA_m32n8k16_load_b_col_global_areg64  = 1965,
    1981             :     INT_WMMA_m32n8k16_load_b_col_global_ari     = 1966,
    1982             :     INT_WMMA_m32n8k16_load_b_col_global_ari64   = 1967,
    1983             :     INT_WMMA_m32n8k16_load_b_col_global_avar    = 1968,
    1984             :     INT_WMMA_m32n8k16_load_b_col_global_stride_areg     = 1969,
    1985             :     INT_WMMA_m32n8k16_load_b_col_global_stride_areg64   = 1970,
    1986             :     INT_WMMA_m32n8k16_load_b_col_global_stride_ari      = 1971,
    1987             :     INT_WMMA_m32n8k16_load_b_col_global_stride_ari64    = 1972,
    1988             :     INT_WMMA_m32n8k16_load_b_col_global_stride_avar     = 1973,
    1989             :     INT_WMMA_m32n8k16_load_b_col_shared_areg    = 1974,
    1990             :     INT_WMMA_m32n8k16_load_b_col_shared_areg64  = 1975,
    1991             :     INT_WMMA_m32n8k16_load_b_col_shared_ari     = 1976,
    1992             :     INT_WMMA_m32n8k16_load_b_col_shared_ari64   = 1977,
    1993             :     INT_WMMA_m32n8k16_load_b_col_shared_avar    = 1978,
    1994             :     INT_WMMA_m32n8k16_load_b_col_shared_stride_areg     = 1979,
    1995             :     INT_WMMA_m32n8k16_load_b_col_shared_stride_areg64   = 1980,
    1996             :     INT_WMMA_m32n8k16_load_b_col_shared_stride_ari      = 1981,
    1997             :     INT_WMMA_m32n8k16_load_b_col_shared_stride_ari64    = 1982,
    1998             :     INT_WMMA_m32n8k16_load_b_col_shared_stride_avar     = 1983,
    1999             :     INT_WMMA_m32n8k16_load_b_col_stride_areg    = 1984,
    2000             :     INT_WMMA_m32n8k16_load_b_col_stride_areg64  = 1985,
    2001             :     INT_WMMA_m32n8k16_load_b_col_stride_ari     = 1986,
    2002             :     INT_WMMA_m32n8k16_load_b_col_stride_ari64   = 1987,
    2003             :     INT_WMMA_m32n8k16_load_b_col_stride_avar    = 1988,
    2004             :     INT_WMMA_m32n8k16_load_b_row_areg   = 1989,
    2005             :     INT_WMMA_m32n8k16_load_b_row_areg64 = 1990,
    2006             :     INT_WMMA_m32n8k16_load_b_row_ari    = 1991,
    2007             :     INT_WMMA_m32n8k16_load_b_row_ari64  = 1992,
    2008             :     INT_WMMA_m32n8k16_load_b_row_avar   = 1993,
    2009             :     INT_WMMA_m32n8k16_load_b_row_global_areg    = 1994,
    2010             :     INT_WMMA_m32n8k16_load_b_row_global_areg64  = 1995,
    2011             :     INT_WMMA_m32n8k16_load_b_row_global_ari     = 1996,
    2012             :     INT_WMMA_m32n8k16_load_b_row_global_ari64   = 1997,
    2013             :     INT_WMMA_m32n8k16_load_b_row_global_avar    = 1998,
    2014             :     INT_WMMA_m32n8k16_load_b_row_global_stride_areg     = 1999,
    2015             :     INT_WMMA_m32n8k16_load_b_row_global_stride_areg64   = 2000,
    2016             :     INT_WMMA_m32n8k16_load_b_row_global_stride_ari      = 2001,
    2017             :     INT_WMMA_m32n8k16_load_b_row_global_stride_ari64    = 2002,
    2018             :     INT_WMMA_m32n8k16_load_b_row_global_stride_avar     = 2003,
    2019             :     INT_WMMA_m32n8k16_load_b_row_shared_areg    = 2004,
    2020             :     INT_WMMA_m32n8k16_load_b_row_shared_areg64  = 2005,
    2021             :     INT_WMMA_m32n8k16_load_b_row_shared_ari     = 2006,
    2022             :     INT_WMMA_m32n8k16_load_b_row_shared_ari64   = 2007,
    2023             :     INT_WMMA_m32n8k16_load_b_row_shared_avar    = 2008,
    2024             :     INT_WMMA_m32n8k16_load_b_row_shared_stride_areg     = 2009,
    2025             :     INT_WMMA_m32n8k16_load_b_row_shared_stride_areg64   = 2010,
    2026             :     INT_WMMA_m32n8k16_load_b_row_shared_stride_ari      = 2011,
    2027             :     INT_WMMA_m32n8k16_load_b_row_shared_stride_ari64    = 2012,
    2028             :     INT_WMMA_m32n8k16_load_b_row_shared_stride_avar     = 2013,
    2029             :     INT_WMMA_m32n8k16_load_b_row_stride_areg    = 2014,
    2030             :     INT_WMMA_m32n8k16_load_b_row_stride_areg64  = 2015,
    2031             :     INT_WMMA_m32n8k16_load_b_row_stride_ari     = 2016,
    2032             :     INT_WMMA_m32n8k16_load_b_row_stride_ari64   = 2017,
    2033             :     INT_WMMA_m32n8k16_load_b_row_stride_avar    = 2018,
    2034             :     INT_WMMA_m32n8k16_load_c_f16_col_areg       = 2019,
    2035             :     INT_WMMA_m32n8k16_load_c_f16_col_areg64     = 2020,
    2036             :     INT_WMMA_m32n8k16_load_c_f16_col_ari        = 2021,
    2037             :     INT_WMMA_m32n8k16_load_c_f16_col_ari64      = 2022,
    2038             :     INT_WMMA_m32n8k16_load_c_f16_col_avar       = 2023,
    2039             :     INT_WMMA_m32n8k16_load_c_f16_col_global_areg        = 2024,
    2040             :     INT_WMMA_m32n8k16_load_c_f16_col_global_areg64      = 2025,
    2041             :     INT_WMMA_m32n8k16_load_c_f16_col_global_ari = 2026,
    2042             :     INT_WMMA_m32n8k16_load_c_f16_col_global_ari64       = 2027,
    2043             :     INT_WMMA_m32n8k16_load_c_f16_col_global_avar        = 2028,
    2044             :     INT_WMMA_m32n8k16_load_c_f16_col_global_stride_areg = 2029,
    2045             :     INT_WMMA_m32n8k16_load_c_f16_col_global_stride_areg64       = 2030,
    2046             :     INT_WMMA_m32n8k16_load_c_f16_col_global_stride_ari  = 2031,
    2047             :     INT_WMMA_m32n8k16_load_c_f16_col_global_stride_ari64        = 2032,
    2048             :     INT_WMMA_m32n8k16_load_c_f16_col_global_stride_avar = 2033,
    2049             :     INT_WMMA_m32n8k16_load_c_f16_col_shared_areg        = 2034,
    2050             :     INT_WMMA_m32n8k16_load_c_f16_col_shared_areg64      = 2035,
    2051             :     INT_WMMA_m32n8k16_load_c_f16_col_shared_ari = 2036,
    2052             :     INT_WMMA_m32n8k16_load_c_f16_col_shared_ari64       = 2037,
    2053             :     INT_WMMA_m32n8k16_load_c_f16_col_shared_avar        = 2038,
    2054             :     INT_WMMA_m32n8k16_load_c_f16_col_shared_stride_areg = 2039,
    2055             :     INT_WMMA_m32n8k16_load_c_f16_col_shared_stride_areg64       = 2040,
    2056             :     INT_WMMA_m32n8k16_load_c_f16_col_shared_stride_ari  = 2041,
    2057             :     INT_WMMA_m32n8k16_load_c_f16_col_shared_stride_ari64        = 2042,
    2058             :     INT_WMMA_m32n8k16_load_c_f16_col_shared_stride_avar = 2043,
    2059             :     INT_WMMA_m32n8k16_load_c_f16_col_stride_areg        = 2044,
    2060             :     INT_WMMA_m32n8k16_load_c_f16_col_stride_areg64      = 2045,
    2061             :     INT_WMMA_m32n8k16_load_c_f16_col_stride_ari = 2046,
    2062             :     INT_WMMA_m32n8k16_load_c_f16_col_stride_ari64       = 2047,
    2063             :     INT_WMMA_m32n8k16_load_c_f16_col_stride_avar        = 2048,
    2064             :     INT_WMMA_m32n8k16_load_c_f16_row_areg       = 2049,
    2065             :     INT_WMMA_m32n8k16_load_c_f16_row_areg64     = 2050,
    2066             :     INT_WMMA_m32n8k16_load_c_f16_row_ari        = 2051,
    2067             :     INT_WMMA_m32n8k16_load_c_f16_row_ari64      = 2052,
    2068             :     INT_WMMA_m32n8k16_load_c_f16_row_avar       = 2053,
    2069             :     INT_WMMA_m32n8k16_load_c_f16_row_global_areg        = 2054,
    2070             :     INT_WMMA_m32n8k16_load_c_f16_row_global_areg64      = 2055,
    2071             :     INT_WMMA_m32n8k16_load_c_f16_row_global_ari = 2056,
    2072             :     INT_WMMA_m32n8k16_load_c_f16_row_global_ari64       = 2057,
    2073             :     INT_WMMA_m32n8k16_load_c_f16_row_global_avar        = 2058,
    2074             :     INT_WMMA_m32n8k16_load_c_f16_row_global_stride_areg = 2059,
    2075             :     INT_WMMA_m32n8k16_load_c_f16_row_global_stride_areg64       = 2060,
    2076             :     INT_WMMA_m32n8k16_load_c_f16_row_global_stride_ari  = 2061,
    2077             :     INT_WMMA_m32n8k16_load_c_f16_row_global_stride_ari64        = 2062,
    2078             :     INT_WMMA_m32n8k16_load_c_f16_row_global_stride_avar = 2063,
    2079             :     INT_WMMA_m32n8k16_load_c_f16_row_shared_areg        = 2064,
    2080             :     INT_WMMA_m32n8k16_load_c_f16_row_shared_areg64      = 2065,
    2081             :     INT_WMMA_m32n8k16_load_c_f16_row_shared_ari = 2066,
    2082             :     INT_WMMA_m32n8k16_load_c_f16_row_shared_ari64       = 2067,
    2083             :     INT_WMMA_m32n8k16_load_c_f16_row_shared_avar        = 2068,
    2084             :     INT_WMMA_m32n8k16_load_c_f16_row_shared_stride_areg = 2069,
    2085             :     INT_WMMA_m32n8k16_load_c_f16_row_shared_stride_areg64       = 2070,
    2086             :     INT_WMMA_m32n8k16_load_c_f16_row_shared_stride_ari  = 2071,
    2087             :     INT_WMMA_m32n8k16_load_c_f16_row_shared_stride_ari64        = 2072,
    2088             :     INT_WMMA_m32n8k16_load_c_f16_row_shared_stride_avar = 2073,
    2089             :     INT_WMMA_m32n8k16_load_c_f16_row_stride_areg        = 2074,
    2090             :     INT_WMMA_m32n8k16_load_c_f16_row_stride_areg64      = 2075,
    2091             :     INT_WMMA_m32n8k16_load_c_f16_row_stride_ari = 2076,
    2092             :     INT_WMMA_m32n8k16_load_c_f16_row_stride_ari64       = 2077,
    2093             :     INT_WMMA_m32n8k16_load_c_f16_row_stride_avar        = 2078,
    2094             :     INT_WMMA_m32n8k16_load_c_f32_col_areg       = 2079,
    2095             :     INT_WMMA_m32n8k16_load_c_f32_col_areg64     = 2080,
    2096             :     INT_WMMA_m32n8k16_load_c_f32_col_ari        = 2081,
    2097             :     INT_WMMA_m32n8k16_load_c_f32_col_ari64      = 2082,
    2098             :     INT_WMMA_m32n8k16_load_c_f32_col_avar       = 2083,
    2099             :     INT_WMMA_m32n8k16_load_c_f32_col_global_areg        = 2084,
    2100             :     INT_WMMA_m32n8k16_load_c_f32_col_global_areg64      = 2085,
    2101             :     INT_WMMA_m32n8k16_load_c_f32_col_global_ari = 2086,
    2102             :     INT_WMMA_m32n8k16_load_c_f32_col_global_ari64       = 2087,
    2103             :     INT_WMMA_m32n8k16_load_c_f32_col_global_avar        = 2088,
    2104             :     INT_WMMA_m32n8k16_load_c_f32_col_global_stride_areg = 2089,
    2105             :     INT_WMMA_m32n8k16_load_c_f32_col_global_stride_areg64       = 2090,
    2106             :     INT_WMMA_m32n8k16_load_c_f32_col_global_stride_ari  = 2091,
    2107             :     INT_WMMA_m32n8k16_load_c_f32_col_global_stride_ari64        = 2092,
    2108             :     INT_WMMA_m32n8k16_load_c_f32_col_global_stride_avar = 2093,
    2109             :     INT_WMMA_m32n8k16_load_c_f32_col_shared_areg        = 2094,
    2110             :     INT_WMMA_m32n8k16_load_c_f32_col_shared_areg64      = 2095,
    2111             :     INT_WMMA_m32n8k16_load_c_f32_col_shared_ari = 2096,
    2112             :     INT_WMMA_m32n8k16_load_c_f32_col_shared_ari64       = 2097,
    2113             :     INT_WMMA_m32n8k16_load_c_f32_col_shared_avar        = 2098,
    2114             :     INT_WMMA_m32n8k16_load_c_f32_col_shared_stride_areg = 2099,
    2115             :     INT_WMMA_m32n8k16_load_c_f32_col_shared_stride_areg64       = 2100,
    2116             :     INT_WMMA_m32n8k16_load_c_f32_col_shared_stride_ari  = 2101,
    2117             :     INT_WMMA_m32n8k16_load_c_f32_col_shared_stride_ari64        = 2102,
    2118             :     INT_WMMA_m32n8k16_load_c_f32_col_shared_stride_avar = 2103,
    2119             :     INT_WMMA_m32n8k16_load_c_f32_col_stride_areg        = 2104,
    2120             :     INT_WMMA_m32n8k16_load_c_f32_col_stride_areg64      = 2105,
    2121             :     INT_WMMA_m32n8k16_load_c_f32_col_stride_ari = 2106,
    2122             :     INT_WMMA_m32n8k16_load_c_f32_col_stride_ari64       = 2107,
    2123             :     INT_WMMA_m32n8k16_load_c_f32_col_stride_avar        = 2108,
    2124             :     INT_WMMA_m32n8k16_load_c_f32_row_areg       = 2109,
    2125             :     INT_WMMA_m32n8k16_load_c_f32_row_areg64     = 2110,
    2126             :     INT_WMMA_m32n8k16_load_c_f32_row_ari        = 2111,
    2127             :     INT_WMMA_m32n8k16_load_c_f32_row_ari64      = 2112,
    2128             :     INT_WMMA_m32n8k16_load_c_f32_row_avar       = 2113,
    2129             :     INT_WMMA_m32n8k16_load_c_f32_row_global_areg        = 2114,
    2130             :     INT_WMMA_m32n8k16_load_c_f32_row_global_areg64      = 2115,
    2131             :     INT_WMMA_m32n8k16_load_c_f32_row_global_ari = 2116,
    2132             :     INT_WMMA_m32n8k16_load_c_f32_row_global_ari64       = 2117,
    2133             :     INT_WMMA_m32n8k16_load_c_f32_row_global_avar        = 2118,
    2134             :     INT_WMMA_m32n8k16_load_c_f32_row_global_stride_areg = 2119,
    2135             :     INT_WMMA_m32n8k16_load_c_f32_row_global_stride_areg64       = 2120,
    2136             :     INT_WMMA_m32n8k16_load_c_f32_row_global_stride_ari  = 2121,
    2137             :     INT_WMMA_m32n8k16_load_c_f32_row_global_stride_ari64        = 2122,
    2138             :     INT_WMMA_m32n8k16_load_c_f32_row_global_stride_avar = 2123,
    2139             :     INT_WMMA_m32n8k16_load_c_f32_row_shared_areg        = 2124,
    2140             :     INT_WMMA_m32n8k16_load_c_f32_row_shared_areg64      = 2125,
    2141             :     INT_WMMA_m32n8k16_load_c_f32_row_shared_ari = 2126,
    2142             :     INT_WMMA_m32n8k16_load_c_f32_row_shared_ari64       = 2127,
    2143             :     INT_WMMA_m32n8k16_load_c_f32_row_shared_avar        = 2128,
    2144             :     INT_WMMA_m32n8k16_load_c_f32_row_shared_stride_areg = 2129,
    2145             :     INT_WMMA_m32n8k16_load_c_f32_row_shared_stride_areg64       = 2130,
    2146             :     INT_WMMA_m32n8k16_load_c_f32_row_shared_stride_ari  = 2131,
    2147             :     INT_WMMA_m32n8k16_load_c_f32_row_shared_stride_ari64        = 2132,
    2148             :     INT_WMMA_m32n8k16_load_c_f32_row_shared_stride_avar = 2133,
    2149             :     INT_WMMA_m32n8k16_load_c_f32_row_stride_areg        = 2134,
    2150             :     INT_WMMA_m32n8k16_load_c_f32_row_stride_areg64      = 2135,
    2151             :     INT_WMMA_m32n8k16_load_c_f32_row_stride_ari = 2136,
    2152             :     INT_WMMA_m32n8k16_load_c_f32_row_stride_ari64       = 2137,
    2153             :     INT_WMMA_m32n8k16_load_c_f32_row_stride_avar        = 2138,
    2154             :     INT_WMMA_m32n8k16_store_d_f16_col_areg      = 2139,
    2155             :     INT_WMMA_m32n8k16_store_d_f16_col_areg64    = 2140,
    2156             :     INT_WMMA_m32n8k16_store_d_f16_col_ari       = 2141,
    2157             :     INT_WMMA_m32n8k16_store_d_f16_col_ari64     = 2142,
    2158             :     INT_WMMA_m32n8k16_store_d_f16_col_avar      = 2143,
    2159             :     INT_WMMA_m32n8k16_store_d_f16_col_global_areg       = 2144,
    2160             :     INT_WMMA_m32n8k16_store_d_f16_col_global_areg64     = 2145,
    2161             :     INT_WMMA_m32n8k16_store_d_f16_col_global_ari        = 2146,
    2162             :     INT_WMMA_m32n8k16_store_d_f16_col_global_ari64      = 2147,
    2163             :     INT_WMMA_m32n8k16_store_d_f16_col_global_avar       = 2148,
    2164             :     INT_WMMA_m32n8k16_store_d_f16_col_global_stride_areg        = 2149,
    2165             :     INT_WMMA_m32n8k16_store_d_f16_col_global_stride_areg64      = 2150,
    2166             :     INT_WMMA_m32n8k16_store_d_f16_col_global_stride_ari = 2151,
    2167             :     INT_WMMA_m32n8k16_store_d_f16_col_global_stride_ari64       = 2152,
    2168             :     INT_WMMA_m32n8k16_store_d_f16_col_global_stride_avar        = 2153,
    2169             :     INT_WMMA_m32n8k16_store_d_f16_col_shared_areg       = 2154,
    2170             :     INT_WMMA_m32n8k16_store_d_f16_col_shared_areg64     = 2155,
    2171             :     INT_WMMA_m32n8k16_store_d_f16_col_shared_ari        = 2156,
    2172             :     INT_WMMA_m32n8k16_store_d_f16_col_shared_ari64      = 2157,
    2173             :     INT_WMMA_m32n8k16_store_d_f16_col_shared_avar       = 2158,
    2174             :     INT_WMMA_m32n8k16_store_d_f16_col_shared_stride_areg        = 2159,
    2175             :     INT_WMMA_m32n8k16_store_d_f16_col_shared_stride_areg64      = 2160,
    2176             :     INT_WMMA_m32n8k16_store_d_f16_col_shared_stride_ari = 2161,
    2177             :     INT_WMMA_m32n8k16_store_d_f16_col_shared_stride_ari64       = 2162,
    2178             :     INT_WMMA_m32n8k16_store_d_f16_col_shared_stride_avar        = 2163,
    2179             :     INT_WMMA_m32n8k16_store_d_f16_col_stride_areg       = 2164,
    2180             :     INT_WMMA_m32n8k16_store_d_f16_col_stride_areg64     = 2165,
    2181             :     INT_WMMA_m32n8k16_store_d_f16_col_stride_ari        = 2166,
    2182             :     INT_WMMA_m32n8k16_store_d_f16_col_stride_ari64      = 2167,
    2183             :     INT_WMMA_m32n8k16_store_d_f16_col_stride_avar       = 2168,
    2184             :     INT_WMMA_m32n8k16_store_d_f16_row_areg      = 2169,
    2185             :     INT_WMMA_m32n8k16_store_d_f16_row_areg64    = 2170,
    2186             :     INT_WMMA_m32n8k16_store_d_f16_row_ari       = 2171,
    2187             :     INT_WMMA_m32n8k16_store_d_f16_row_ari64     = 2172,
    2188             :     INT_WMMA_m32n8k16_store_d_f16_row_avar      = 2173,
    2189             :     INT_WMMA_m32n8k16_store_d_f16_row_global_areg       = 2174,
    2190             :     INT_WMMA_m32n8k16_store_d_f16_row_global_areg64     = 2175,
    2191             :     INT_WMMA_m32n8k16_store_d_f16_row_global_ari        = 2176,
    2192             :     INT_WMMA_m32n8k16_store_d_f16_row_global_ari64      = 2177,
    2193             :     INT_WMMA_m32n8k16_store_d_f16_row_global_avar       = 2178,
    2194             :     INT_WMMA_m32n8k16_store_d_f16_row_global_stride_areg        = 2179,
    2195             :     INT_WMMA_m32n8k16_store_d_f16_row_global_stride_areg64      = 2180,
    2196             :     INT_WMMA_m32n8k16_store_d_f16_row_global_stride_ari = 2181,
    2197             :     INT_WMMA_m32n8k16_store_d_f16_row_global_stride_ari64       = 2182,
    2198             :     INT_WMMA_m32n8k16_store_d_f16_row_global_stride_avar        = 2183,
    2199             :     INT_WMMA_m32n8k16_store_d_f16_row_shared_areg       = 2184,
    2200             :     INT_WMMA_m32n8k16_store_d_f16_row_shared_areg64     = 2185,
    2201             :     INT_WMMA_m32n8k16_store_d_f16_row_shared_ari        = 2186,
    2202             :     INT_WMMA_m32n8k16_store_d_f16_row_shared_ari64      = 2187,
    2203             :     INT_WMMA_m32n8k16_store_d_f16_row_shared_avar       = 2188,
    2204             :     INT_WMMA_m32n8k16_store_d_f16_row_shared_stride_areg        = 2189,
    2205             :     INT_WMMA_m32n8k16_store_d_f16_row_shared_stride_areg64      = 2190,
    2206             :     INT_WMMA_m32n8k16_store_d_f16_row_shared_stride_ari = 2191,
    2207             :     INT_WMMA_m32n8k16_store_d_f16_row_shared_stride_ari64       = 2192,
    2208             :     INT_WMMA_m32n8k16_store_d_f16_row_shared_stride_avar        = 2193,
    2209             :     INT_WMMA_m32n8k16_store_d_f16_row_stride_areg       = 2194,
    2210             :     INT_WMMA_m32n8k16_store_d_f16_row_stride_areg64     = 2195,
    2211             :     INT_WMMA_m32n8k16_store_d_f16_row_stride_ari        = 2196,
    2212             :     INT_WMMA_m32n8k16_store_d_f16_row_stride_ari64      = 2197,
    2213             :     INT_WMMA_m32n8k16_store_d_f16_row_stride_avar       = 2198,
    2214             :     INT_WMMA_m32n8k16_store_d_f32_col_areg      = 2199,
    2215             :     INT_WMMA_m32n8k16_store_d_f32_col_areg64    = 2200,
    2216             :     INT_WMMA_m32n8k16_store_d_f32_col_ari       = 2201,
    2217             :     INT_WMMA_m32n8k16_store_d_f32_col_ari64     = 2202,
    2218             :     INT_WMMA_m32n8k16_store_d_f32_col_avar      = 2203,
    2219             :     INT_WMMA_m32n8k16_store_d_f32_col_global_areg       = 2204,
    2220             :     INT_WMMA_m32n8k16_store_d_f32_col_global_areg64     = 2205,
    2221             :     INT_WMMA_m32n8k16_store_d_f32_col_global_ari        = 2206,
    2222             :     INT_WMMA_m32n8k16_store_d_f32_col_global_ari64      = 2207,
    2223             :     INT_WMMA_m32n8k16_store_d_f32_col_global_avar       = 2208,
    2224             :     INT_WMMA_m32n8k16_store_d_f32_col_global_stride_areg        = 2209,
    2225             :     INT_WMMA_m32n8k16_store_d_f32_col_global_stride_areg64      = 2210,
    2226             :     INT_WMMA_m32n8k16_store_d_f32_col_global_stride_ari = 2211,
    2227             :     INT_WMMA_m32n8k16_store_d_f32_col_global_stride_ari64       = 2212,
    2228             :     INT_WMMA_m32n8k16_store_d_f32_col_global_stride_avar        = 2213,
    2229             :     INT_WMMA_m32n8k16_store_d_f32_col_shared_areg       = 2214,
    2230             :     INT_WMMA_m32n8k16_store_d_f32_col_shared_areg64     = 2215,
    2231             :     INT_WMMA_m32n8k16_store_d_f32_col_shared_ari        = 2216,
    2232             :     INT_WMMA_m32n8k16_store_d_f32_col_shared_ari64      = 2217,
    2233             :     INT_WMMA_m32n8k16_store_d_f32_col_shared_avar       = 2218,
    2234             :     INT_WMMA_m32n8k16_store_d_f32_col_shared_stride_areg        = 2219,
    2235             :     INT_WMMA_m32n8k16_store_d_f32_col_shared_stride_areg64      = 2220,
    2236             :     INT_WMMA_m32n8k16_store_d_f32_col_shared_stride_ari = 2221,
    2237             :     INT_WMMA_m32n8k16_store_d_f32_col_shared_stride_ari64       = 2222,
    2238             :     INT_WMMA_m32n8k16_store_d_f32_col_shared_stride_avar        = 2223,
    2239             :     INT_WMMA_m32n8k16_store_d_f32_col_stride_areg       = 2224,
    2240             :     INT_WMMA_m32n8k16_store_d_f32_col_stride_areg64     = 2225,
    2241             :     INT_WMMA_m32n8k16_store_d_f32_col_stride_ari        = 2226,
    2242             :     INT_WMMA_m32n8k16_store_d_f32_col_stride_ari64      = 2227,
    2243             :     INT_WMMA_m32n8k16_store_d_f32_col_stride_avar       = 2228,
    2244             :     INT_WMMA_m32n8k16_store_d_f32_row_areg      = 2229,
    2245             :     INT_WMMA_m32n8k16_store_d_f32_row_areg64    = 2230,
    2246             :     INT_WMMA_m32n8k16_store_d_f32_row_ari       = 2231,
    2247             :     INT_WMMA_m32n8k16_store_d_f32_row_ari64     = 2232,
    2248             :     INT_WMMA_m32n8k16_store_d_f32_row_avar      = 2233,
    2249             :     INT_WMMA_m32n8k16_store_d_f32_row_global_areg       = 2234,
    2250             :     INT_WMMA_m32n8k16_store_d_f32_row_global_areg64     = 2235,
    2251             :     INT_WMMA_m32n8k16_store_d_f32_row_global_ari        = 2236,
    2252             :     INT_WMMA_m32n8k16_store_d_f32_row_global_ari64      = 2237,
    2253             :     INT_WMMA_m32n8k16_store_d_f32_row_global_avar       = 2238,
    2254             :     INT_WMMA_m32n8k16_store_d_f32_row_global_stride_areg        = 2239,
    2255             :     INT_WMMA_m32n8k16_store_d_f32_row_global_stride_areg64      = 2240,
    2256             :     INT_WMMA_m32n8k16_store_d_f32_row_global_stride_ari = 2241,
    2257             :     INT_WMMA_m32n8k16_store_d_f32_row_global_stride_ari64       = 2242,
    2258             :     INT_WMMA_m32n8k16_store_d_f32_row_global_stride_avar        = 2243,
    2259             :     INT_WMMA_m32n8k16_store_d_f32_row_shared_areg       = 2244,
    2260             :     INT_WMMA_m32n8k16_store_d_f32_row_shared_areg64     = 2245,
    2261             :     INT_WMMA_m32n8k16_store_d_f32_row_shared_ari        = 2246,
    2262             :     INT_WMMA_m32n8k16_store_d_f32_row_shared_ari64      = 2247,
    2263             :     INT_WMMA_m32n8k16_store_d_f32_row_shared_avar       = 2248,
    2264             :     INT_WMMA_m32n8k16_store_d_f32_row_shared_stride_areg        = 2249,
    2265             :     INT_WMMA_m32n8k16_store_d_f32_row_shared_stride_areg64      = 2250,
    2266             :     INT_WMMA_m32n8k16_store_d_f32_row_shared_stride_ari = 2251,
    2267             :     INT_WMMA_m32n8k16_store_d_f32_row_shared_stride_ari64       = 2252,
    2268             :     INT_WMMA_m32n8k16_store_d_f32_row_shared_stride_avar        = 2253,
    2269             :     INT_WMMA_m32n8k16_store_d_f32_row_stride_areg       = 2254,
    2270             :     INT_WMMA_m32n8k16_store_d_f32_row_stride_areg64     = 2255,
    2271             :     INT_WMMA_m32n8k16_store_d_f32_row_stride_ari        = 2256,
    2272             :     INT_WMMA_m32n8k16_store_d_f32_row_stride_ari64      = 2257,
    2273             :     INT_WMMA_m32n8k16_store_d_f32_row_stride_avar       = 2258,
    2274             :     INT_WMMA_m8n32k16_load_a_col_areg   = 2259,
    2275             :     INT_WMMA_m8n32k16_load_a_col_areg64 = 2260,
    2276             :     INT_WMMA_m8n32k16_load_a_col_ari    = 2261,
    2277             :     INT_WMMA_m8n32k16_load_a_col_ari64  = 2262,
    2278             :     INT_WMMA_m8n32k16_load_a_col_avar   = 2263,
    2279             :     INT_WMMA_m8n32k16_load_a_col_global_areg    = 2264,
    2280             :     INT_WMMA_m8n32k16_load_a_col_global_areg64  = 2265,
    2281             :     INT_WMMA_m8n32k16_load_a_col_global_ari     = 2266,
    2282             :     INT_WMMA_m8n32k16_load_a_col_global_ari64   = 2267,
    2283             :     INT_WMMA_m8n32k16_load_a_col_global_avar    = 2268,
    2284             :     INT_WMMA_m8n32k16_load_a_col_global_stride_areg     = 2269,
    2285             :     INT_WMMA_m8n32k16_load_a_col_global_stride_areg64   = 2270,
    2286             :     INT_WMMA_m8n32k16_load_a_col_global_stride_ari      = 2271,
    2287             :     INT_WMMA_m8n32k16_load_a_col_global_stride_ari64    = 2272,
    2288             :     INT_WMMA_m8n32k16_load_a_col_global_stride_avar     = 2273,
    2289             :     INT_WMMA_m8n32k16_load_a_col_shared_areg    = 2274,
    2290             :     INT_WMMA_m8n32k16_load_a_col_shared_areg64  = 2275,
    2291             :     INT_WMMA_m8n32k16_load_a_col_shared_ari     = 2276,
    2292             :     INT_WMMA_m8n32k16_load_a_col_shared_ari64   = 2277,
    2293             :     INT_WMMA_m8n32k16_load_a_col_shared_avar    = 2278,
    2294             :     INT_WMMA_m8n32k16_load_a_col_shared_stride_areg     = 2279,
    2295             :     INT_WMMA_m8n32k16_load_a_col_shared_stride_areg64   = 2280,
    2296             :     INT_WMMA_m8n32k16_load_a_col_shared_stride_ari      = 2281,
    2297             :     INT_WMMA_m8n32k16_load_a_col_shared_stride_ari64    = 2282,
    2298             :     INT_WMMA_m8n32k16_load_a_col_shared_stride_avar     = 2283,
    2299             :     INT_WMMA_m8n32k16_load_a_col_stride_areg    = 2284,
    2300             :     INT_WMMA_m8n32k16_load_a_col_stride_areg64  = 2285,
    2301             :     INT_WMMA_m8n32k16_load_a_col_stride_ari     = 2286,
    2302             :     INT_WMMA_m8n32k16_load_a_col_stride_ari64   = 2287,
    2303             :     INT_WMMA_m8n32k16_load_a_col_stride_avar    = 2288,
    2304             :     INT_WMMA_m8n32k16_load_a_row_areg   = 2289,
    2305             :     INT_WMMA_m8n32k16_load_a_row_areg64 = 2290,
    2306             :     INT_WMMA_m8n32k16_load_a_row_ari    = 2291,
    2307             :     INT_WMMA_m8n32k16_load_a_row_ari64  = 2292,
    2308             :     INT_WMMA_m8n32k16_load_a_row_avar   = 2293,
    2309             :     INT_WMMA_m8n32k16_load_a_row_global_areg    = 2294,
    2310             :     INT_WMMA_m8n32k16_load_a_row_global_areg64  = 2295,
    2311             :     INT_WMMA_m8n32k16_load_a_row_global_ari     = 2296,
    2312             :     INT_WMMA_m8n32k16_load_a_row_global_ari64   = 2297,
    2313             :     INT_WMMA_m8n32k16_load_a_row_global_avar    = 2298,
    2314             :     INT_WMMA_m8n32k16_load_a_row_global_stride_areg     = 2299,
    2315             :     INT_WMMA_m8n32k16_load_a_row_global_stride_areg64   = 2300,
    2316             :     INT_WMMA_m8n32k16_load_a_row_global_stride_ari      = 2301,
    2317             :     INT_WMMA_m8n32k16_load_a_row_global_stride_ari64    = 2302,
    2318             :     INT_WMMA_m8n32k16_load_a_row_global_stride_avar     = 2303,
    2319             :     INT_WMMA_m8n32k16_load_a_row_shared_areg    = 2304,
    2320             :     INT_WMMA_m8n32k16_load_a_row_shared_areg64  = 2305,
    2321             :     INT_WMMA_m8n32k16_load_a_row_shared_ari     = 2306,
    2322             :     INT_WMMA_m8n32k16_load_a_row_shared_ari64   = 2307,
    2323             :     INT_WMMA_m8n32k16_load_a_row_shared_avar    = 2308,
    2324             :     INT_WMMA_m8n32k16_load_a_row_shared_stride_areg     = 2309,
    2325             :     INT_WMMA_m8n32k16_load_a_row_shared_stride_areg64   = 2310,
    2326             :     INT_WMMA_m8n32k16_load_a_row_shared_stride_ari      = 2311,
    2327             :     INT_WMMA_m8n32k16_load_a_row_shared_stride_ari64    = 2312,
    2328             :     INT_WMMA_m8n32k16_load_a_row_shared_stride_avar     = 2313,
    2329             :     INT_WMMA_m8n32k16_load_a_row_stride_areg    = 2314,
    2330             :     INT_WMMA_m8n32k16_load_a_row_stride_areg64  = 2315,
    2331             :     INT_WMMA_m8n32k16_load_a_row_stride_ari     = 2316,
    2332             :     INT_WMMA_m8n32k16_load_a_row_stride_ari64   = 2317,
    2333             :     INT_WMMA_m8n32k16_load_a_row_stride_avar    = 2318,
    2334             :     INT_WMMA_m8n32k16_load_b_col_areg   = 2319,
    2335             :     INT_WMMA_m8n32k16_load_b_col_areg64 = 2320,
    2336             :     INT_WMMA_m8n32k16_load_b_col_ari    = 2321,
    2337             :     INT_WMMA_m8n32k16_load_b_col_ari64  = 2322,
    2338             :     INT_WMMA_m8n32k16_load_b_col_avar   = 2323,
    2339             :     INT_WMMA_m8n32k16_load_b_col_global_areg    = 2324,
    2340             :     INT_WMMA_m8n32k16_load_b_col_global_areg64  = 2325,
    2341             :     INT_WMMA_m8n32k16_load_b_col_global_ari     = 2326,
    2342             :     INT_WMMA_m8n32k16_load_b_col_global_ari64   = 2327,
    2343             :     INT_WMMA_m8n32k16_load_b_col_global_avar    = 2328,
    2344             :     INT_WMMA_m8n32k16_load_b_col_global_stride_areg     = 2329,
    2345             :     INT_WMMA_m8n32k16_load_b_col_global_stride_areg64   = 2330,
    2346             :     INT_WMMA_m8n32k16_load_b_col_global_stride_ari      = 2331,
    2347             :     INT_WMMA_m8n32k16_load_b_col_global_stride_ari64    = 2332,
    2348             :     INT_WMMA_m8n32k16_load_b_col_global_stride_avar     = 2333,
    2349             :     INT_WMMA_m8n32k16_load_b_col_shared_areg    = 2334,
    2350             :     INT_WMMA_m8n32k16_load_b_col_shared_areg64  = 2335,
    2351             :     INT_WMMA_m8n32k16_load_b_col_shared_ari     = 2336,
    2352             :     INT_WMMA_m8n32k16_load_b_col_shared_ari64   = 2337,
    2353             :     INT_WMMA_m8n32k16_load_b_col_shared_avar    = 2338,
    2354             :     INT_WMMA_m8n32k16_load_b_col_shared_stride_areg     = 2339,
    2355             :     INT_WMMA_m8n32k16_load_b_col_shared_stride_areg64   = 2340,
    2356             :     INT_WMMA_m8n32k16_load_b_col_shared_stride_ari      = 2341,
    2357             :     INT_WMMA_m8n32k16_load_b_col_shared_stride_ari64    = 2342,
    2358             :     INT_WMMA_m8n32k16_load_b_col_shared_stride_avar     = 2343,
    2359             :     INT_WMMA_m8n32k16_load_b_col_stride_areg    = 2344,
    2360             :     INT_WMMA_m8n32k16_load_b_col_stride_areg64  = 2345,
    2361             :     INT_WMMA_m8n32k16_load_b_col_stride_ari     = 2346,
    2362             :     INT_WMMA_m8n32k16_load_b_col_stride_ari64   = 2347,
    2363             :     INT_WMMA_m8n32k16_load_b_col_stride_avar    = 2348,
    2364             :     INT_WMMA_m8n32k16_load_b_row_areg   = 2349,
    2365             :     INT_WMMA_m8n32k16_load_b_row_areg64 = 2350,
    2366             :     INT_WMMA_m8n32k16_load_b_row_ari    = 2351,
    2367             :     INT_WMMA_m8n32k16_load_b_row_ari64  = 2352,
    2368             :     INT_WMMA_m8n32k16_load_b_row_avar   = 2353,
    2369             :     INT_WMMA_m8n32k16_load_b_row_global_areg    = 2354,
    2370             :     INT_WMMA_m8n32k16_load_b_row_global_areg64  = 2355,
    2371             :     INT_WMMA_m8n32k16_load_b_row_global_ari     = 2356,
    2372             :     INT_WMMA_m8n32k16_load_b_row_global_ari64   = 2357,
    2373             :     INT_WMMA_m8n32k16_load_b_row_global_avar    = 2358,
    2374             :     INT_WMMA_m8n32k16_load_b_row_global_stride_areg     = 2359,
    2375             :     INT_WMMA_m8n32k16_load_b_row_global_stride_areg64   = 2360,
    2376             :     INT_WMMA_m8n32k16_load_b_row_global_stride_ari      = 2361,
    2377             :     INT_WMMA_m8n32k16_load_b_row_global_stride_ari64    = 2362,
    2378             :     INT_WMMA_m8n32k16_load_b_row_global_stride_avar     = 2363,
    2379             :     INT_WMMA_m8n32k16_load_b_row_shared_areg    = 2364,
    2380             :     INT_WMMA_m8n32k16_load_b_row_shared_areg64  = 2365,
    2381             :     INT_WMMA_m8n32k16_load_b_row_shared_ari     = 2366,
    2382             :     INT_WMMA_m8n32k16_load_b_row_shared_ari64   = 2367,
    2383             :     INT_WMMA_m8n32k16_load_b_row_shared_avar    = 2368,
    2384             :     INT_WMMA_m8n32k16_load_b_row_shared_stride_areg     = 2369,
    2385             :     INT_WMMA_m8n32k16_load_b_row_shared_stride_areg64   = 2370,
    2386             :     INT_WMMA_m8n32k16_load_b_row_shared_stride_ari      = 2371,
    2387             :     INT_WMMA_m8n32k16_load_b_row_shared_stride_ari64    = 2372,
    2388             :     INT_WMMA_m8n32k16_load_b_row_shared_stride_avar     = 2373,
    2389             :     INT_WMMA_m8n32k16_load_b_row_stride_areg    = 2374,
    2390             :     INT_WMMA_m8n32k16_load_b_row_stride_areg64  = 2375,
    2391             :     INT_WMMA_m8n32k16_load_b_row_stride_ari     = 2376,
    2392             :     INT_WMMA_m8n32k16_load_b_row_stride_ari64   = 2377,
    2393             :     INT_WMMA_m8n32k16_load_b_row_stride_avar    = 2378,
    2394             :     INT_WMMA_m8n32k16_load_c_f16_col_areg       = 2379,
    2395             :     INT_WMMA_m8n32k16_load_c_f16_col_areg64     = 2380,
    2396             :     INT_WMMA_m8n32k16_load_c_f16_col_ari        = 2381,
    2397             :     INT_WMMA_m8n32k16_load_c_f16_col_ari64      = 2382,
    2398             :     INT_WMMA_m8n32k16_load_c_f16_col_avar       = 2383,
    2399             :     INT_WMMA_m8n32k16_load_c_f16_col_global_areg        = 2384,
    2400             :     INT_WMMA_m8n32k16_load_c_f16_col_global_areg64      = 2385,
    2401             :     INT_WMMA_m8n32k16_load_c_f16_col_global_ari = 2386,
    2402             :     INT_WMMA_m8n32k16_load_c_f16_col_global_ari64       = 2387,
    2403             :     INT_WMMA_m8n32k16_load_c_f16_col_global_avar        = 2388,
    2404             :     INT_WMMA_m8n32k16_load_c_f16_col_global_stride_areg = 2389,
    2405             :     INT_WMMA_m8n32k16_load_c_f16_col_global_stride_areg64       = 2390,
    2406             :     INT_WMMA_m8n32k16_load_c_f16_col_global_stride_ari  = 2391,
    2407             :     INT_WMMA_m8n32k16_load_c_f16_col_global_stride_ari64        = 2392,
    2408             :     INT_WMMA_m8n32k16_load_c_f16_col_global_stride_avar = 2393,
    2409             :     INT_WMMA_m8n32k16_load_c_f16_col_shared_areg        = 2394,
    2410             :     INT_WMMA_m8n32k16_load_c_f16_col_shared_areg64      = 2395,
    2411             :     INT_WMMA_m8n32k16_load_c_f16_col_shared_ari = 2396,
    2412             :     INT_WMMA_m8n32k16_load_c_f16_col_shared_ari64       = 2397,
    2413             :     INT_WMMA_m8n32k16_load_c_f16_col_shared_avar        = 2398,
    2414             :     INT_WMMA_m8n32k16_load_c_f16_col_shared_stride_areg = 2399,
    2415             :     INT_WMMA_m8n32k16_load_c_f16_col_shared_stride_areg64       = 2400,
    2416             :     INT_WMMA_m8n32k16_load_c_f16_col_shared_stride_ari  = 2401,
    2417             :     INT_WMMA_m8n32k16_load_c_f16_col_shared_stride_ari64        = 2402,
    2418             :     INT_WMMA_m8n32k16_load_c_f16_col_shared_stride_avar = 2403,
    2419             :     INT_WMMA_m8n32k16_load_c_f16_col_stride_areg        = 2404,
    2420             :     INT_WMMA_m8n32k16_load_c_f16_col_stride_areg64      = 2405,
    2421             :     INT_WMMA_m8n32k16_load_c_f16_col_stride_ari = 2406,
    2422             :     INT_WMMA_m8n32k16_load_c_f16_col_stride_ari64       = 2407,
    2423             :     INT_WMMA_m8n32k16_load_c_f16_col_stride_avar        = 2408,
    2424             :     INT_WMMA_m8n32k16_load_c_f16_row_areg       = 2409,
    2425             :     INT_WMMA_m8n32k16_load_c_f16_row_areg64     = 2410,
    2426             :     INT_WMMA_m8n32k16_load_c_f16_row_ari        = 2411,
    2427             :     INT_WMMA_m8n32k16_load_c_f16_row_ari64      = 2412,
    2428             :     INT_WMMA_m8n32k16_load_c_f16_row_avar       = 2413,
    2429             :     INT_WMMA_m8n32k16_load_c_f16_row_global_areg        = 2414,
    2430             :     INT_WMMA_m8n32k16_load_c_f16_row_global_areg64      = 2415,
    2431             :     INT_WMMA_m8n32k16_load_c_f16_row_global_ari = 2416,
    2432             :     INT_WMMA_m8n32k16_load_c_f16_row_global_ari64       = 2417,
    2433             :     INT_WMMA_m8n32k16_load_c_f16_row_global_avar        = 2418,
    2434             :     INT_WMMA_m8n32k16_load_c_f16_row_global_stride_areg = 2419,
    2435             :     INT_WMMA_m8n32k16_load_c_f16_row_global_stride_areg64       = 2420,
    2436             :     INT_WMMA_m8n32k16_load_c_f16_row_global_stride_ari  = 2421,
    2437             :     INT_WMMA_m8n32k16_load_c_f16_row_global_stride_ari64        = 2422,
    2438             :     INT_WMMA_m8n32k16_load_c_f16_row_global_stride_avar = 2423,
    2439             :     INT_WMMA_m8n32k16_load_c_f16_row_shared_areg        = 2424,
    2440             :     INT_WMMA_m8n32k16_load_c_f16_row_shared_areg64      = 2425,
    2441             :     INT_WMMA_m8n32k16_load_c_f16_row_shared_ari = 2426,
    2442             :     INT_WMMA_m8n32k16_load_c_f16_row_shared_ari64       = 2427,
    2443             :     INT_WMMA_m8n32k16_load_c_f16_row_shared_avar        = 2428,
    2444             :     INT_WMMA_m8n32k16_load_c_f16_row_shared_stride_areg = 2429,
    2445             :     INT_WMMA_m8n32k16_load_c_f16_row_shared_stride_areg64       = 2430,
    2446             :     INT_WMMA_m8n32k16_load_c_f16_row_shared_stride_ari  = 2431,
    2447             :     INT_WMMA_m8n32k16_load_c_f16_row_shared_stride_ari64        = 2432,
    2448             :     INT_WMMA_m8n32k16_load_c_f16_row_shared_stride_avar = 2433,
    2449             :     INT_WMMA_m8n32k16_load_c_f16_row_stride_areg        = 2434,
    2450             :     INT_WMMA_m8n32k16_load_c_f16_row_stride_areg64      = 2435,
    2451             :     INT_WMMA_m8n32k16_load_c_f16_row_stride_ari = 2436,
    2452             :     INT_WMMA_m8n32k16_load_c_f16_row_stride_ari64       = 2437,
    2453             :     INT_WMMA_m8n32k16_load_c_f16_row_stride_avar        = 2438,
    2454             :     INT_WMMA_m8n32k16_load_c_f32_col_areg       = 2439,
    2455             :     INT_WMMA_m8n32k16_load_c_f32_col_areg64     = 2440,
    2456             :     INT_WMMA_m8n32k16_load_c_f32_col_ari        = 2441,
    2457             :     INT_WMMA_m8n32k16_load_c_f32_col_ari64      = 2442,
    2458             :     INT_WMMA_m8n32k16_load_c_f32_col_avar       = 2443,
    2459             :     INT_WMMA_m8n32k16_load_c_f32_col_global_areg        = 2444,
    2460             :     INT_WMMA_m8n32k16_load_c_f32_col_global_areg64      = 2445,
    2461             :     INT_WMMA_m8n32k16_load_c_f32_col_global_ari = 2446,
    2462             :     INT_WMMA_m8n32k16_load_c_f32_col_global_ari64       = 2447,
    2463             :     INT_WMMA_m8n32k16_load_c_f32_col_global_avar        = 2448,
    2464             :     INT_WMMA_m8n32k16_load_c_f32_col_global_stride_areg = 2449,
    2465             :     INT_WMMA_m8n32k16_load_c_f32_col_global_stride_areg64       = 2450,
    2466             :     INT_WMMA_m8n32k16_load_c_f32_col_global_stride_ari  = 2451,
    2467             :     INT_WMMA_m8n32k16_load_c_f32_col_global_stride_ari64        = 2452,
    2468             :     INT_WMMA_m8n32k16_load_c_f32_col_global_stride_avar = 2453,
    2469             :     INT_WMMA_m8n32k16_load_c_f32_col_shared_areg        = 2454,
    2470             :     INT_WMMA_m8n32k16_load_c_f32_col_shared_areg64      = 2455,
    2471             :     INT_WMMA_m8n32k16_load_c_f32_col_shared_ari = 2456,
    2472             :     INT_WMMA_m8n32k16_load_c_f32_col_shared_ari64       = 2457,
    2473             :     INT_WMMA_m8n32k16_load_c_f32_col_shared_avar        = 2458,
    2474             :     INT_WMMA_m8n32k16_load_c_f32_col_shared_stride_areg = 2459,
    2475             :     INT_WMMA_m8n32k16_load_c_f32_col_shared_stride_areg64       = 2460,
    2476             :     INT_WMMA_m8n32k16_load_c_f32_col_shared_stride_ari  = 2461,
    2477             :     INT_WMMA_m8n32k16_load_c_f32_col_shared_stride_ari64        = 2462,
    2478             :     INT_WMMA_m8n32k16_load_c_f32_col_shared_stride_avar = 2463,
    2479             :     INT_WMMA_m8n32k16_load_c_f32_col_stride_areg        = 2464,
    2480             :     INT_WMMA_m8n32k16_load_c_f32_col_stride_areg64      = 2465,
    2481             :     INT_WMMA_m8n32k16_load_c_f32_col_stride_ari = 2466,
    2482             :     INT_WMMA_m8n32k16_load_c_f32_col_stride_ari64       = 2467,
    2483             :     INT_WMMA_m8n32k16_load_c_f32_col_stride_avar        = 2468,
    2484             :     INT_WMMA_m8n32k16_load_c_f32_row_areg       = 2469,
    2485             :     INT_WMMA_m8n32k16_load_c_f32_row_areg64     = 2470,
    2486             :     INT_WMMA_m8n32k16_load_c_f32_row_ari        = 2471,
    2487             :     INT_WMMA_m8n32k16_load_c_f32_row_ari64      = 2472,
    2488             :     INT_WMMA_m8n32k16_load_c_f32_row_avar       = 2473,
    2489             :     INT_WMMA_m8n32k16_load_c_f32_row_global_areg        = 2474,
    2490             :     INT_WMMA_m8n32k16_load_c_f32_row_global_areg64      = 2475,
    2491             :     INT_WMMA_m8n32k16_load_c_f32_row_global_ari = 2476,
    2492             :     INT_WMMA_m8n32k16_load_c_f32_row_global_ari64       = 2477,
    2493             :     INT_WMMA_m8n32k16_load_c_f32_row_global_avar        = 2478,
    2494             :     INT_WMMA_m8n32k16_load_c_f32_row_global_stride_areg = 2479,
    2495             :     INT_WMMA_m8n32k16_load_c_f32_row_global_stride_areg64       = 2480,
    2496             :     INT_WMMA_m8n32k16_load_c_f32_row_global_stride_ari  = 2481,
    2497             :     INT_WMMA_m8n32k16_load_c_f32_row_global_stride_ari64        = 2482,
    2498             :     INT_WMMA_m8n32k16_load_c_f32_row_global_stride_avar = 2483,
    2499             :     INT_WMMA_m8n32k16_load_c_f32_row_shared_areg        = 2484,
    2500             :     INT_WMMA_m8n32k16_load_c_f32_row_shared_areg64      = 2485,
    2501             :     INT_WMMA_m8n32k16_load_c_f32_row_shared_ari = 2486,
    2502             :     INT_WMMA_m8n32k16_load_c_f32_row_shared_ari64       = 2487,
    2503             :     INT_WMMA_m8n32k16_load_c_f32_row_shared_avar        = 2488,
    2504             :     INT_WMMA_m8n32k16_load_c_f32_row_shared_stride_areg = 2489,
    2505             :     INT_WMMA_m8n32k16_load_c_f32_row_shared_stride_areg64       = 2490,
    2506             :     INT_WMMA_m8n32k16_load_c_f32_row_shared_stride_ari  = 2491,
    2507             :     INT_WMMA_m8n32k16_load_c_f32_row_shared_stride_ari64        = 2492,
    2508             :     INT_WMMA_m8n32k16_load_c_f32_row_shared_stride_avar = 2493,
    2509             :     INT_WMMA_m8n32k16_load_c_f32_row_stride_areg        = 2494,
    2510             :     INT_WMMA_m8n32k16_load_c_f32_row_stride_areg64      = 2495,
    2511             :     INT_WMMA_m8n32k16_load_c_f32_row_stride_ari = 2496,
    2512             :     INT_WMMA_m8n32k16_load_c_f32_row_stride_ari64       = 2497,
    2513             :     INT_WMMA_m8n32k16_load_c_f32_row_stride_avar        = 2498,
    2514             :     INT_WMMA_m8n32k16_store_d_f16_col_areg      = 2499,
    2515             :     INT_WMMA_m8n32k16_store_d_f16_col_areg64    = 2500,
    2516             :     INT_WMMA_m8n32k16_store_d_f16_col_ari       = 2501,
    2517             :     INT_WMMA_m8n32k16_store_d_f16_col_ari64     = 2502,
    2518             :     INT_WMMA_m8n32k16_store_d_f16_col_avar      = 2503,
    2519             :     INT_WMMA_m8n32k16_store_d_f16_col_global_areg       = 2504,
    2520             :     INT_WMMA_m8n32k16_store_d_f16_col_global_areg64     = 2505,
    2521             :     INT_WMMA_m8n32k16_store_d_f16_col_global_ari        = 2506,
    2522             :     INT_WMMA_m8n32k16_store_d_f16_col_global_ari64      = 2507,
    2523             :     INT_WMMA_m8n32k16_store_d_f16_col_global_avar       = 2508,
    2524             :     INT_WMMA_m8n32k16_store_d_f16_col_global_stride_areg        = 2509,
    2525             :     INT_WMMA_m8n32k16_store_d_f16_col_global_stride_areg64      = 2510,
    2526             :     INT_WMMA_m8n32k16_store_d_f16_col_global_stride_ari = 2511,
    2527             :     INT_WMMA_m8n32k16_store_d_f16_col_global_stride_ari64       = 2512,
    2528             :     INT_WMMA_m8n32k16_store_d_f16_col_global_stride_avar        = 2513,
    2529             :     INT_WMMA_m8n32k16_store_d_f16_col_shared_areg       = 2514,
    2530             :     INT_WMMA_m8n32k16_store_d_f16_col_shared_areg64     = 2515,
    2531             :     INT_WMMA_m8n32k16_store_d_f16_col_shared_ari        = 2516,
    2532             :     INT_WMMA_m8n32k16_store_d_f16_col_shared_ari64      = 2517,
    2533             :     INT_WMMA_m8n32k16_store_d_f16_col_shared_avar       = 2518,
    2534             :     INT_WMMA_m8n32k16_store_d_f16_col_shared_stride_areg        = 2519,
    2535             :     INT_WMMA_m8n32k16_store_d_f16_col_shared_stride_areg64      = 2520,
    2536             :     INT_WMMA_m8n32k16_store_d_f16_col_shared_stride_ari = 2521,
    2537             :     INT_WMMA_m8n32k16_store_d_f16_col_shared_stride_ari64       = 2522,
    2538             :     INT_WMMA_m8n32k16_store_d_f16_col_shared_stride_avar        = 2523,
    2539             :     INT_WMMA_m8n32k16_store_d_f16_col_stride_areg       = 2524,
    2540             :     INT_WMMA_m8n32k16_store_d_f16_col_stride_areg64     = 2525,
    2541             :     INT_WMMA_m8n32k16_store_d_f16_col_stride_ari        = 2526,
    2542             :     INT_WMMA_m8n32k16_store_d_f16_col_stride_ari64      = 2527,
    2543             :     INT_WMMA_m8n32k16_store_d_f16_col_stride_avar       = 2528,
    2544             :     INT_WMMA_m8n32k16_store_d_f16_row_areg      = 2529,
    2545             :     INT_WMMA_m8n32k16_store_d_f16_row_areg64    = 2530,
    2546             :     INT_WMMA_m8n32k16_store_d_f16_row_ari       = 2531,
    2547             :     INT_WMMA_m8n32k16_store_d_f16_row_ari64     = 2532,
    2548             :     INT_WMMA_m8n32k16_store_d_f16_row_avar      = 2533,
    2549             :     INT_WMMA_m8n32k16_store_d_f16_row_global_areg       = 2534,
    2550             :     INT_WMMA_m8n32k16_store_d_f16_row_global_areg64     = 2535,
    2551             :     INT_WMMA_m8n32k16_store_d_f16_row_global_ari        = 2536,
    2552             :     INT_WMMA_m8n32k16_store_d_f16_row_global_ari64      = 2537,
    2553             :     INT_WMMA_m8n32k16_store_d_f16_row_global_avar       = 2538,
    2554             :     INT_WMMA_m8n32k16_store_d_f16_row_global_stride_areg        = 2539,
    2555             :     INT_WMMA_m8n32k16_store_d_f16_row_global_stride_areg64      = 2540,
    2556             :     INT_WMMA_m8n32k16_store_d_f16_row_global_stride_ari = 2541,
    2557             :     INT_WMMA_m8n32k16_store_d_f16_row_global_stride_ari64       = 2542,
    2558             :     INT_WMMA_m8n32k16_store_d_f16_row_global_stride_avar        = 2543,
    2559             :     INT_WMMA_m8n32k16_store_d_f16_row_shared_areg       = 2544,
    2560             :     INT_WMMA_m8n32k16_store_d_f16_row_shared_areg64     = 2545,
    2561             :     INT_WMMA_m8n32k16_store_d_f16_row_shared_ari        = 2546,
    2562             :     INT_WMMA_m8n32k16_store_d_f16_row_shared_ari64      = 2547,
    2563             :     INT_WMMA_m8n32k16_store_d_f16_row_shared_avar       = 2548,
    2564             :     INT_WMMA_m8n32k16_store_d_f16_row_shared_stride_areg        = 2549,
    2565             :     INT_WMMA_m8n32k16_store_d_f16_row_shared_stride_areg64      = 2550,
    2566             :     INT_WMMA_m8n32k16_store_d_f16_row_shared_stride_ari = 2551,
    2567             :     INT_WMMA_m8n32k16_store_d_f16_row_shared_stride_ari64       = 2552,
    2568             :     INT_WMMA_m8n32k16_store_d_f16_row_shared_stride_avar        = 2553,
    2569             :     INT_WMMA_m8n32k16_store_d_f16_row_stride_areg       = 2554,
    2570             :     INT_WMMA_m8n32k16_store_d_f16_row_stride_areg64     = 2555,
    2571             :     INT_WMMA_m8n32k16_store_d_f16_row_stride_ari        = 2556,
    2572             :     INT_WMMA_m8n32k16_store_d_f16_row_stride_ari64      = 2557,
    2573             :     INT_WMMA_m8n32k16_store_d_f16_row_stride_avar       = 2558,
    2574             :     INT_WMMA_m8n32k16_store_d_f32_col_areg      = 2559,
    2575             :     INT_WMMA_m8n32k16_store_d_f32_col_areg64    = 2560,
    2576             :     INT_WMMA_m8n32k16_store_d_f32_col_ari       = 2561,
    2577             :     INT_WMMA_m8n32k16_store_d_f32_col_ari64     = 2562,
    2578             :     INT_WMMA_m8n32k16_store_d_f32_col_avar      = 2563,
    2579             :     INT_WMMA_m8n32k16_store_d_f32_col_global_areg       = 2564,
    2580             :     INT_WMMA_m8n32k16_store_d_f32_col_global_areg64     = 2565,
    2581             :     INT_WMMA_m8n32k16_store_d_f32_col_global_ari        = 2566,
    2582             :     INT_WMMA_m8n32k16_store_d_f32_col_global_ari64      = 2567,
    2583             :     INT_WMMA_m8n32k16_store_d_f32_col_global_avar       = 2568,
    2584             :     INT_WMMA_m8n32k16_store_d_f32_col_global_stride_areg        = 2569,
    2585             :     INT_WMMA_m8n32k16_store_d_f32_col_global_stride_areg64      = 2570,
    2586             :     INT_WMMA_m8n32k16_store_d_f32_col_global_stride_ari = 2571,
    2587             :     INT_WMMA_m8n32k16_store_d_f32_col_global_stride_ari64       = 2572,
    2588             :     INT_WMMA_m8n32k16_store_d_f32_col_global_stride_avar        = 2573,
    2589             :     INT_WMMA_m8n32k16_store_d_f32_col_shared_areg       = 2574,
    2590             :     INT_WMMA_m8n32k16_store_d_f32_col_shared_areg64     = 2575,
    2591             :     INT_WMMA_m8n32k16_store_d_f32_col_shared_ari        = 2576,
    2592             :     INT_WMMA_m8n32k16_store_d_f32_col_shared_ari64      = 2577,
    2593             :     INT_WMMA_m8n32k16_store_d_f32_col_shared_avar       = 2578,
    2594             :     INT_WMMA_m8n32k16_store_d_f32_col_shared_stride_areg        = 2579,
    2595             :     INT_WMMA_m8n32k16_store_d_f32_col_shared_stride_areg64      = 2580,
    2596             :     INT_WMMA_m8n32k16_store_d_f32_col_shared_stride_ari = 2581,
    2597             :     INT_WMMA_m8n32k16_store_d_f32_col_shared_stride_ari64       = 2582,
    2598             :     INT_WMMA_m8n32k16_store_d_f32_col_shared_stride_avar        = 2583,
    2599             :     INT_WMMA_m8n32k16_store_d_f32_col_stride_areg       = 2584,
    2600             :     INT_WMMA_m8n32k16_store_d_f32_col_stride_areg64     = 2585,
    2601             :     INT_WMMA_m8n32k16_store_d_f32_col_stride_ari        = 2586,
    2602             :     INT_WMMA_m8n32k16_store_d_f32_col_stride_ari64      = 2587,
    2603             :     INT_WMMA_m8n32k16_store_d_f32_col_stride_avar       = 2588,
    2604             :     INT_WMMA_m8n32k16_store_d_f32_row_areg      = 2589,
    2605             :     INT_WMMA_m8n32k16_store_d_f32_row_areg64    = 2590,
    2606             :     INT_WMMA_m8n32k16_store_d_f32_row_ari       = 2591,
    2607             :     INT_WMMA_m8n32k16_store_d_f32_row_ari64     = 2592,
    2608             :     INT_WMMA_m8n32k16_store_d_f32_row_avar      = 2593,
    2609             :     INT_WMMA_m8n32k16_store_d_f32_row_global_areg       = 2594,
    2610             :     INT_WMMA_m8n32k16_store_d_f32_row_global_areg64     = 2595,
    2611             :     INT_WMMA_m8n32k16_store_d_f32_row_global_ari        = 2596,
    2612             :     INT_WMMA_m8n32k16_store_d_f32_row_global_ari64      = 2597,
    2613             :     INT_WMMA_m8n32k16_store_d_f32_row_global_avar       = 2598,
    2614             :     INT_WMMA_m8n32k16_store_d_f32_row_global_stride_areg        = 2599,
    2615             :     INT_WMMA_m8n32k16_store_d_f32_row_global_stride_areg64      = 2600,
    2616             :     INT_WMMA_m8n32k16_store_d_f32_row_global_stride_ari = 2601,
    2617             :     INT_WMMA_m8n32k16_store_d_f32_row_global_stride_ari64       = 2602,
    2618             :     INT_WMMA_m8n32k16_store_d_f32_row_global_stride_avar        = 2603,
    2619             :     INT_WMMA_m8n32k16_store_d_f32_row_shared_areg       = 2604,
    2620             :     INT_WMMA_m8n32k16_store_d_f32_row_shared_areg64     = 2605,
    2621             :     INT_WMMA_m8n32k16_store_d_f32_row_shared_ari        = 2606,
    2622             :     INT_WMMA_m8n32k16_store_d_f32_row_shared_ari64      = 2607,
    2623             :     INT_WMMA_m8n32k16_store_d_f32_row_shared_avar       = 2608,
    2624             :     INT_WMMA_m8n32k16_store_d_f32_row_shared_stride_areg        = 2609,
    2625             :     INT_WMMA_m8n32k16_store_d_f32_row_shared_stride_areg64      = 2610,
    2626             :     INT_WMMA_m8n32k16_store_d_f32_row_shared_stride_ari = 2611,
    2627             :     INT_WMMA_m8n32k16_store_d_f32_row_shared_stride_ari64       = 2612,
    2628             :     INT_WMMA_m8n32k16_store_d_f32_row_shared_stride_avar        = 2613,
    2629             :     INT_WMMA_m8n32k16_store_d_f32_row_stride_areg       = 2614,
    2630             :     INT_WMMA_m8n32k16_store_d_f32_row_stride_areg64     = 2615,
    2631             :     INT_WMMA_m8n32k16_store_d_f32_row_stride_ari        = 2616,
    2632             :     INT_WMMA_m8n32k16_store_d_f32_row_stride_ari64      = 2617,
    2633             :     INT_WMMA_m8n32k16_store_d_f32_row_stride_avar       = 2618,
    2634             :     ISSPACEP_CONST_32   = 2619,
    2635             :     ISSPACEP_CONST_64   = 2620,
    2636             :     ISSPACEP_GLOBAL_32  = 2621,
    2637             :     ISSPACEP_GLOBAL_64  = 2622,
    2638             :     ISSPACEP_LOCAL_32   = 2623,
    2639             :     ISSPACEP_LOCAL_64   = 2624,
    2640             :     ISSPACEP_SHARED_32  = 2625,
    2641             :     ISSPACEP_SHARED_64  = 2626,
    2642             :     ISTYPEP_SAMPLER     = 2627,
    2643             :     ISTYPEP_SURFACE     = 2628,
    2644             :     ISTYPEP_TEXTURE     = 2629,
    2645             :     LDV_f16_v2_areg     = 2630,
    2646             :     LDV_f16_v2_areg_64  = 2631,
    2647             :     LDV_f16_v2_ari      = 2632,
    2648             :     LDV_f16_v2_ari_64   = 2633,
    2649             :     LDV_f16_v2_asi      = 2634,
    2650             :     LDV_f16_v2_avar     = 2635,
    2651             :     LDV_f16_v4_areg     = 2636,
    2652             :     LDV_f16_v4_areg_64  = 2637,
    2653             :     LDV_f16_v4_ari      = 2638,
    2654             :     LDV_f16_v4_ari_64   = 2639,
    2655             :     LDV_f16_v4_asi      = 2640,
    2656             :     LDV_f16_v4_avar     = 2641,
    2657             :     LDV_f16x2_v2_areg   = 2642,
    2658             :     LDV_f16x2_v2_areg_64        = 2643,
    2659             :     LDV_f16x2_v2_ari    = 2644,
    2660             :     LDV_f16x2_v2_ari_64 = 2645,
    2661             :     LDV_f16x2_v2_asi    = 2646,
    2662             :     LDV_f16x2_v2_avar   = 2647,
    2663             :     LDV_f16x2_v4_areg   = 2648,
    2664             :     LDV_f16x2_v4_areg_64        = 2649,
    2665             :     LDV_f16x2_v4_ari    = 2650,
    2666             :     LDV_f16x2_v4_ari_64 = 2651,
    2667             :     LDV_f16x2_v4_asi    = 2652,
    2668             :     LDV_f16x2_v4_avar   = 2653,
    2669             :     LDV_f32_v2_areg     = 2654,
    2670             :     LDV_f32_v2_areg_64  = 2655,
    2671             :     LDV_f32_v2_ari      = 2656,
    2672             :     LDV_f32_v2_ari_64   = 2657,
    2673             :     LDV_f32_v2_asi      = 2658,
    2674             :     LDV_f32_v2_avar     = 2659,
    2675             :     LDV_f32_v4_areg     = 2660,
    2676             :     LDV_f32_v4_areg_64  = 2661,
    2677             :     LDV_f32_v4_ari      = 2662,
    2678             :     LDV_f32_v4_ari_64   = 2663,
    2679             :     LDV_f32_v4_asi      = 2664,
    2680             :     LDV_f32_v4_avar     = 2665,
    2681             :     LDV_f64_v2_areg     = 2666,
    2682             :     LDV_f64_v2_areg_64  = 2667,
    2683             :     LDV_f64_v2_ari      = 2668,
    2684             :     LDV_f64_v2_ari_64   = 2669,
    2685             :     LDV_f64_v2_asi      = 2670,
    2686             :     LDV_f64_v2_avar     = 2671,
    2687             :     LDV_f64_v4_areg     = 2672,
    2688             :     LDV_f64_v4_areg_64  = 2673,
    2689             :     LDV_f64_v4_ari      = 2674,
    2690             :     LDV_f64_v4_ari_64   = 2675,
    2691             :     LDV_f64_v4_asi      = 2676,
    2692             :     LDV_f64_v4_avar     = 2677,
    2693             :     LDV_i16_v2_areg     = 2678,
    2694             :     LDV_i16_v2_areg_64  = 2679,
    2695             :     LDV_i16_v2_ari      = 2680,
    2696             :     LDV_i16_v2_ari_64   = 2681,
    2697             :     LDV_i16_v2_asi      = 2682,
    2698             :     LDV_i16_v2_avar     = 2683,
    2699             :     LDV_i16_v4_areg     = 2684,
    2700             :     LDV_i16_v4_areg_64  = 2685,
    2701             :     LDV_i16_v4_ari      = 2686,
    2702             :     LDV_i16_v4_ari_64   = 2687,
    2703             :     LDV_i16_v4_asi      = 2688,
    2704             :     LDV_i16_v4_avar     = 2689,
    2705             :     LDV_i32_v2_areg     = 2690,
    2706             :     LDV_i32_v2_areg_64  = 2691,
    2707             :     LDV_i32_v2_ari      = 2692,
    2708             :     LDV_i32_v2_ari_64   = 2693,
    2709             :     LDV_i32_v2_asi      = 2694,
    2710             :     LDV_i32_v2_avar     = 2695,
    2711             :     LDV_i32_v4_areg     = 2696,
    2712             :     LDV_i32_v4_areg_64  = 2697,
    2713             :     LDV_i32_v4_ari      = 2698,
    2714             :     LDV_i32_v4_ari_64   = 2699,
    2715             :     LDV_i32_v4_asi      = 2700,
    2716             :     LDV_i32_v4_avar     = 2701,
    2717             :     LDV_i64_v2_areg     = 2702,
    2718             :     LDV_i64_v2_areg_64  = 2703,
    2719             :     LDV_i64_v2_ari      = 2704,
    2720             :     LDV_i64_v2_ari_64   = 2705,
    2721             :     LDV_i64_v2_asi      = 2706,
    2722             :     LDV_i64_v2_avar     = 2707,
    2723             :     LDV_i64_v4_areg     = 2708,
    2724             :     LDV_i64_v4_areg_64  = 2709,
    2725             :     LDV_i64_v4_ari      = 2710,
    2726             :     LDV_i64_v4_ari_64   = 2711,
    2727             :     LDV_i64_v4_asi      = 2712,
    2728             :     LDV_i64_v4_avar     = 2713,
    2729             :     LDV_i8_v2_areg      = 2714,
    2730             :     LDV_i8_v2_areg_64   = 2715,
    2731             :     LDV_i8_v2_ari       = 2716,
    2732             :     LDV_i8_v2_ari_64    = 2717,
    2733             :     LDV_i8_v2_asi       = 2718,
    2734             :     LDV_i8_v2_avar      = 2719,
    2735             :     LDV_i8_v4_areg      = 2720,
    2736             :     LDV_i8_v4_areg_64   = 2721,
    2737             :     LDV_i8_v4_ari       = 2722,
    2738             :     LDV_i8_v4_ari_64    = 2723,
    2739             :     LDV_i8_v4_asi       = 2724,
    2740             :     LDV_i8_v4_avar      = 2725,
    2741             :     LD_f16_areg = 2726,
    2742             :     LD_f16_areg_64      = 2727,
    2743             :     LD_f16_ari  = 2728,
    2744             :     LD_f16_ari_64       = 2729,
    2745             :     LD_f16_asi  = 2730,
    2746             :     LD_f16_avar = 2731,
    2747             :     LD_f16x2_areg       = 2732,
    2748             :     LD_f16x2_areg_64    = 2733,
    2749             :     LD_f16x2_ari        = 2734,
    2750             :     LD_f16x2_ari_64     = 2735,
    2751             :     LD_f16x2_asi        = 2736,
    2752             :     LD_f16x2_avar       = 2737,
    2753             :     LD_f32_areg = 2738,
    2754             :     LD_f32_areg_64      = 2739,
    2755             :     LD_f32_ari  = 2740,
    2756             :     LD_f32_ari_64       = 2741,
    2757             :     LD_f32_asi  = 2742,
    2758             :     LD_f32_avar = 2743,
    2759             :     LD_f64_areg = 2744,
    2760             :     LD_f64_areg_64      = 2745,
    2761             :     LD_f64_ari  = 2746,
    2762             :     LD_f64_ari_64       = 2747,
    2763             :     LD_f64_asi  = 2748,
    2764             :     LD_f64_avar = 2749,
    2765             :     LD_i16_areg = 2750,
    2766             :     LD_i16_areg_64      = 2751,
    2767             :     LD_i16_ari  = 2752,
    2768             :     LD_i16_ari_64       = 2753,
    2769             :     LD_i16_asi  = 2754,
    2770             :     LD_i16_avar = 2755,
    2771             :     LD_i32_areg = 2756,
    2772             :     LD_i32_areg_64      = 2757,
    2773             :     LD_i32_ari  = 2758,
    2774             :     LD_i32_ari_64       = 2759,
    2775             :     LD_i32_asi  = 2760,
    2776             :     LD_i32_avar = 2761,
    2777             :     LD_i64_areg = 2762,
    2778             :     LD_i64_areg_64      = 2763,
    2779             :     LD_i64_ari  = 2764,
    2780             :     LD_i64_ari_64       = 2765,
    2781             :     LD_i64_asi  = 2766,
    2782             :     LD_i64_avar = 2767,
    2783             :     LD_i8_areg  = 2768,
    2784             :     LD_i8_areg_64       = 2769,
    2785             :     LD_i8_ari   = 2770,
    2786             :     LD_i8_ari_64        = 2771,
    2787             :     LD_i8_asi   = 2772,
    2788             :     LD_i8_avar  = 2773,
    2789             :     LEA_ADDRi   = 2774,
    2790             :     LEA_ADDRi64 = 2775,
    2791             :     LOAD_CONST_F16      = 2776,
    2792             :     LastCallArgF32      = 2777,
    2793             :     LastCallArgF64      = 2778,
    2794             :     LastCallArgI16      = 2779,
    2795             :     LastCallArgI32      = 2780,
    2796             :     LastCallArgI32imm   = 2781,
    2797             :     LastCallArgI64      = 2782,
    2798             :     LastCallArgParam    = 2783,
    2799             :     LoadParamMemF16     = 2784,
    2800             :     LoadParamMemF16x2   = 2785,
    2801             :     LoadParamMemF32     = 2786,
    2802             :     LoadParamMemF64     = 2787,
    2803             :     LoadParamMemI16     = 2788,
    2804             :     LoadParamMemI32     = 2789,
    2805             :     LoadParamMemI64     = 2790,
    2806             :     LoadParamMemI8      = 2791,
    2807             :     LoadParamMemV2F16   = 2792,
    2808             :     LoadParamMemV2F16x2 = 2793,
    2809             :     LoadParamMemV2F32   = 2794,
    2810             :     LoadParamMemV2F64   = 2795,
    2811             :     LoadParamMemV2I16   = 2796,
    2812             :     LoadParamMemV2I32   = 2797,
    2813             :     LoadParamMemV2I64   = 2798,
    2814             :     LoadParamMemV2I8    = 2799,
    2815             :     LoadParamMemV4F16   = 2800,
    2816             :     LoadParamMemV4F16x2 = 2801,
    2817             :     LoadParamMemV4F32   = 2802,
    2818             :     LoadParamMemV4I16   = 2803,
    2819             :     LoadParamMemV4I32   = 2804,
    2820             :     LoadParamMemV4I8    = 2805,
    2821             :     MAD16rii    = 2806,
    2822             :     MAD16rir    = 2807,
    2823             :     MAD16rri    = 2808,
    2824             :     MAD16rrr    = 2809,
    2825             :     MAD32rii    = 2810,
    2826             :     MAD32rir    = 2811,
    2827             :     MAD32rri    = 2812,
    2828             :     MAD32rrr    = 2813,
    2829             :     MAD64rii    = 2814,
    2830             :     MAD64rir    = 2815,
    2831             :     MAD64rri    = 2816,
    2832             :     MAD64rrr    = 2817,
    2833             :     MATCH_ALLP_SYNC_32ii        = 2818,
    2834             :     MATCH_ALLP_SYNC_32ir        = 2819,
    2835             :     MATCH_ALLP_SYNC_32ri        = 2820,
    2836             :     MATCH_ALLP_SYNC_32rr        = 2821,
    2837             :     MATCH_ALLP_SYNC_64ii        = 2822,
    2838             :     MATCH_ALLP_SYNC_64ir        = 2823,
    2839             :     MATCH_ALLP_SYNC_64ri        = 2824,
    2840             :     MATCH_ALLP_SYNC_64rr        = 2825,
    2841             :     MATCH_ANY_SYNC_32ii = 2826,
    2842             :     MATCH_ANY_SYNC_32ir = 2827,
    2843             :     MATCH_ANY_SYNC_32ri = 2828,
    2844             :     MATCH_ANY_SYNC_32rr = 2829,
    2845             :     MATCH_ANY_SYNC_64ii = 2830,
    2846             :     MATCH_ANY_SYNC_64ir = 2831,
    2847             :     MATCH_ANY_SYNC_64ri = 2832,
    2848             :     MATCH_ANY_SYNC_64rr = 2833,
    2849             :     MOV_ADDR    = 2834,
    2850             :     MOV_ADDR64  = 2835,
    2851             :     MOV_DEPOT_ADDR      = 2836,
    2852             :     MOV_DEPOT_ADDR_64   = 2837,
    2853             :     MOV_SPECIAL = 2838,
    2854             :     MULTHSi16ri = 2839,
    2855             :     MULTHSi16rr = 2840,
    2856             :     MULTHSi32ri = 2841,
    2857             :     MULTHSi32rr = 2842,
    2858             :     MULTHSi64ri = 2843,
    2859             :     MULTHSi64rr = 2844,
    2860             :     MULTHUi16ri = 2845,
    2861             :     MULTHUi16rr = 2846,
    2862             :     MULTHUi32ri = 2847,
    2863             :     MULTHUi32rr = 2848,
    2864             :     MULTHUi64ri = 2849,
    2865             :     MULTHUi64rr = 2850,
    2866             :     MULTi16ri   = 2851,
    2867             :     MULTi16rr   = 2852,
    2868             :     MULTi32ri   = 2853,
    2869             :     MULTi32rr   = 2854,
    2870             :     MULTi64ri   = 2855,
    2871             :     MULTi64rr   = 2856,
    2872             :     MULWIDES32  = 2857,
    2873             :     MULWIDES32Imm       = 2858,
    2874             :     MULWIDES32Imm32     = 2859,
    2875             :     MULWIDES64  = 2860,
    2876             :     MULWIDES64Imm       = 2861,
    2877             :     MULWIDES64Imm64     = 2862,
    2878             :     MULWIDEU32  = 2863,
    2879             :     MULWIDEU32Imm       = 2864,
    2880             :     MULWIDEU32Imm32     = 2865,
    2881             :     MULWIDEU64  = 2866,
    2882             :     MULWIDEU64Imm       = 2867,
    2883             :     MULWIDEU64Imm64     = 2868,
    2884             :     MoveParamF16        = 2869,
    2885             :     MoveParamF32        = 2870,
    2886             :     MoveParamF64        = 2871,
    2887             :     MoveParamI16        = 2872,
    2888             :     MoveParamI32        = 2873,
    2889             :     MoveParamI64        = 2874,
    2890             :     NOP = 2875,
    2891             :     NOT1        = 2876,
    2892             :     NOT16       = 2877,
    2893             :     NOT32       = 2878,
    2894             :     NOT64       = 2879,
    2895             :     ORb16ri     = 2880,
    2896             :     ORb16rr     = 2881,
    2897             :     ORb1ri      = 2882,
    2898             :     ORb1rr      = 2883,
    2899             :     ORb32ri     = 2884,
    2900             :     ORb32rr     = 2885,
    2901             :     ORb64ri     = 2886,
    2902             :     ORb64rr     = 2887,
    2903             :     PACK_TWO_INT32      = 2888,
    2904             :     POPCr32     = 2889,
    2905             :     POPCr64     = 2890,
    2906             :     PrototypeInst       = 2891,
    2907             :     PseudoUseParamF32   = 2892,
    2908             :     PseudoUseParamF64   = 2893,
    2909             :     PseudoUseParamI16   = 2894,
    2910             :     PseudoUseParamI32   = 2895,
    2911             :     PseudoUseParamI64   = 2896,
    2912             :     RETURNInst  = 2897,
    2913             :     ROT32imm_sw = 2898,
    2914             :     ROT64imm_sw = 2899,
    2915             :     ROTATE_B32_HW_IMM   = 2900,
    2916             :     ROTATE_B32_HW_REG   = 2901,
    2917             :     ROTL32imm_hw        = 2902,
    2918             :     ROTL32reg_hw        = 2903,
    2919             :     ROTL32reg_sw        = 2904,
    2920             :     ROTL64reg_sw        = 2905,
    2921             :     ROTR32imm_hw        = 2906,
    2922             :     ROTR32reg_hw        = 2907,
    2923             :     ROTR32reg_sw        = 2908,
    2924             :     ROTR64reg_sw        = 2909,
    2925             :     Return      = 2910,
    2926             :     SDIVi16ri   = 2911,
    2927             :     SDIVi16rr   = 2912,
    2928             :     SDIVi32ri   = 2913,
    2929             :     SDIVi32rr   = 2914,
    2930             :     SDIVi64ri   = 2915,
    2931             :     SDIVi64rr   = 2916,
    2932             :     SELP_b16ii  = 2917,
    2933             :     SELP_b16ir  = 2918,
    2934             :     SELP_b16ri  = 2919,
    2935             :     SELP_b16rr  = 2920,
    2936             :     SELP_b32ii  = 2921,
    2937             :     SELP_b32ir  = 2922,
    2938             :     SELP_b32ri  = 2923,
    2939             :     SELP_b32rr  = 2924,
    2940             :     SELP_b64ii  = 2925,
    2941             :     SELP_b64ir  = 2926,
    2942             :     SELP_b64ri  = 2927,
    2943             :     SELP_b64rr  = 2928,
    2944             :     SELP_f16ii  = 2929,
    2945             :     SELP_f16ir  = 2930,
    2946             :     SELP_f16ri  = 2931,
    2947             :     SELP_f16rr  = 2932,
    2948             :     SELP_f16x2rr        = 2933,
    2949             :     SELP_f32ii  = 2934,
    2950             :     SELP_f32ir  = 2935,
    2951             :     SELP_f32ri  = 2936,
    2952             :     SELP_f32rr  = 2937,
    2953             :     SELP_f64ii  = 2938,
    2954             :     SELP_f64ir  = 2939,
    2955             :     SELP_f64ri  = 2940,
    2956             :     SELP_f64rr  = 2941,
    2957             :     SELP_s16ii  = 2942,
    2958             :     SELP_s16ir  = 2943,
    2959             :     SELP_s16ri  = 2944,
    2960             :     SELP_s16rr  = 2945,
    2961             :     SELP_s32ii  = 2946,
    2962             :     SELP_s32ir  = 2947,
    2963             :     SELP_s32ri  = 2948,
    2964             :     SELP_s32rr  = 2949,
    2965             :     SELP_s64ii  = 2950,
    2966             :     SELP_s64ir  = 2951,
    2967             :     SELP_s64ri  = 2952,
    2968             :     SELP_s64rr  = 2953,
    2969             :     SELP_u16ii  = 2954,
    2970             :     SELP_u16ir  = 2955,
    2971             :     SELP_u16ri  = 2956,
    2972             :     SELP_u16rr  = 2957,
    2973             :     SELP_u32ii  = 2958,
    2974             :     SELP_u32ir  = 2959,
    2975             :     SELP_u32ri  = 2960,
    2976             :     SELP_u32rr  = 2961,
    2977             :     SELP_u64ii  = 2962,
    2978             :     SELP_u64ir  = 2963,
    2979             :     SELP_u64ri  = 2964,
    2980             :     SELP_u64rr  = 2965,
    2981             :     SETP_b16ir  = 2966,
    2982             :     SETP_b16ri  = 2967,
    2983             :     SETP_b16rr  = 2968,
    2984             :     SETP_b32ir  = 2969,
    2985             :     SETP_b32ri  = 2970,
    2986             :     SETP_b32rr  = 2971,
    2987             :     SETP_b64ir  = 2972,
    2988             :     SETP_b64ri  = 2973,
    2989             :     SETP_b64rr  = 2974,
    2990             :     SETP_f16rr  = 2975,
    2991             :     SETP_f16x2rr        = 2976,
    2992             :     SETP_f32ir  = 2977,
    2993             :     SETP_f32ri  = 2978,
    2994             :     SETP_f32rr  = 2979,
    2995             :     SETP_f64ir  = 2980,
    2996             :     SETP_f64ri  = 2981,
    2997             :     SETP_f64rr  = 2982,
    2998             :     SETP_s16ir  = 2983,
    2999             :     SETP_s16ri  = 2984,
    3000             :     SETP_s16rr  = 2985,
    3001             :     SETP_s32ir  = 2986,
    3002             :     SETP_s32ri  = 2987,
    3003             :     SETP_s32rr  = 2988,
    3004             :     SETP_s64ir  = 2989,
    3005             :     SETP_s64ri  = 2990,
    3006             :     SETP_s64rr  = 2991,
    3007             :     SETP_u16ir  = 2992,
    3008             :     SETP_u16ri  = 2993,
    3009             :     SETP_u16rr  = 2994,
    3010             :     SETP_u32ir  = 2995,
    3011             :     SETP_u32ri  = 2996,
    3012             :     SETP_u32rr  = 2997,
    3013             :     SETP_u64ir  = 2998,
    3014             :     SETP_u64ri  = 2999,
    3015             :     SETP_u64rr  = 3000,
    3016             :     SET_b16ir   = 3001,
    3017             :     SET_b16ri   = 3002,
    3018             :     SET_b16rr   = 3003,
    3019             :     SET_b32ir   = 3004,
    3020             :     SET_b32ri   = 3005,
    3021             :     SET_b32rr   = 3006,
    3022             :     SET_b64ir   = 3007,
    3023             :     SET_b64ri   = 3008,
    3024             :     SET_b64rr   = 3009,
    3025             :     SET_f16ir   = 3010,
    3026             :     SET_f16ri   = 3011,
    3027             :     SET_f16rr   = 3012,
    3028             :     SET_f32ir   = 3013,
    3029             :     SET_f32ri   = 3014,
    3030             :     SET_f32rr   = 3015,
    3031             :     SET_f64ir   = 3016,
    3032             :     SET_f64ri   = 3017,
    3033             :     SET_f64rr   = 3018,
    3034             :     SET_s16ir   = 3019,
    3035             :     SET_s16ri   = 3020,
    3036             :     SET_s16rr   = 3021,
    3037             :     SET_s32ir   = 3022,
    3038             :     SET_s32ri   = 3023,
    3039             :     SET_s32rr   = 3024,
    3040             :     SET_s64ir   = 3025,
    3041             :     SET_s64ri   = 3026,
    3042             :     SET_s64rr   = 3027,
    3043             :     SET_u16ir   = 3028,
    3044             :     SET_u16ri   = 3029,
    3045             :     SET_u16rr   = 3030,
    3046             :     SET_u32ir   = 3031,
    3047             :     SET_u32ri   = 3032,
    3048             :     SET_u32rr   = 3033,
    3049             :     SET_u64ir   = 3034,
    3050             :     SET_u64ri   = 3035,
    3051             :     SET_u64rr   = 3036,
    3052             :     SHF_L_WRAP_B32_IMM  = 3037,
    3053             :     SHF_L_WRAP_B32_REG  = 3038,
    3054             :     SHF_R_WRAP_B32_IMM  = 3039,
    3055             :     SHF_R_WRAP_B32_REG  = 3040,
    3056             :     SHLi16ri    = 3041,
    3057             :     SHLi16rr    = 3042,
    3058             :     SHLi32ii    = 3043,
    3059             :     SHLi32ri    = 3044,
    3060             :     SHLi32rr    = 3045,
    3061             :     SHLi64ri    = 3046,
    3062             :     SHLi64rr    = 3047,
    3063             :     SINF        = 3048,
    3064             :     SMAXi16ri   = 3049,
    3065             :     SMAXi16rr   = 3050,
    3066             :     SMAXi32ri   = 3051,
    3067             :     SMAXi32rr   = 3052,
    3068             :     SMAXi64ri   = 3053,
    3069             :     SMAXi64rr   = 3054,
    3070             :     SMINi16ri   = 3055,
    3071             :     SMINi16rr   = 3056,
    3072             :     SMINi32ri   = 3057,
    3073             :     SMINi32rr   = 3058,
    3074             :     SMINi64ri   = 3059,
    3075             :     SMINi64rr   = 3060,
    3076             :     SRAi16ri    = 3061,
    3077             :     SRAi16rr    = 3062,
    3078             :     SRAi32ii    = 3063,
    3079             :     SRAi32ri    = 3064,
    3080             :     SRAi32rr    = 3065,
    3081             :     SRAi64ri    = 3066,
    3082             :     SRAi64rr    = 3067,
    3083             :     SREMi16ri   = 3068,
    3084             :     SREMi16rr   = 3069,
    3085             :     SREMi32ri   = 3070,
    3086             :     SREMi32rr   = 3071,
    3087             :     SREMi64ri   = 3072,
    3088             :     SREMi64rr   = 3073,
    3089             :     SRLi16ri    = 3074,
    3090             :     SRLi16rr    = 3075,
    3091             :     SRLi32ii    = 3076,
    3092             :     SRLi32ri    = 3077,
    3093             :     SRLi32rr    = 3078,
    3094             :     SRLi64ri    = 3079,
    3095             :     SRLi64rr    = 3080,
    3096             :     STV_f16_v2_areg     = 3081,
    3097             :     STV_f16_v2_areg_64  = 3082,
    3098             :     STV_f16_v2_ari      = 3083,
    3099             :     STV_f16_v2_ari_64   = 3084,
    3100             :     STV_f16_v2_asi      = 3085,
    3101             :     STV_f16_v2_avar     = 3086,
    3102             :     STV_f16_v4_areg     = 3087,
    3103             :     STV_f16_v4_areg_64  = 3088,
    3104             :     STV_f16_v4_ari      = 3089,
    3105             :     STV_f16_v4_ari_64   = 3090,
    3106             :     STV_f16_v4_asi      = 3091,
    3107             :     STV_f16_v4_avar     = 3092,
    3108             :     STV_f16x2_v2_areg   = 3093,
    3109             :     STV_f16x2_v2_areg_64        = 3094,
    3110             :     STV_f16x2_v2_ari    = 3095,
    3111             :     STV_f16x2_v2_ari_64 = 3096,
    3112             :     STV_f16x2_v2_asi    = 3097,
    3113             :     STV_f16x2_v2_avar   = 3098,
    3114             :     STV_f16x2_v4_areg   = 3099,
    3115             :     STV_f16x2_v4_areg_64        = 3100,
    3116             :     STV_f16x2_v4_ari    = 3101,
    3117             :     STV_f16x2_v4_ari_64 = 3102,
    3118             :     STV_f16x2_v4_asi    = 3103,
    3119             :     STV_f16x2_v4_avar   = 3104,
    3120             :     STV_f32_v2_areg     = 3105,
    3121             :     STV_f32_v2_areg_64  = 3106,
    3122             :     STV_f32_v2_ari      = 3107,
    3123             :     STV_f32_v2_ari_64   = 3108,
    3124             :     STV_f32_v2_asi      = 3109,
    3125             :     STV_f32_v2_avar     = 3110,
    3126             :     STV_f32_v4_areg     = 3111,
    3127             :     STV_f32_v4_areg_64  = 3112,
    3128             :     STV_f32_v4_ari      = 3113,
    3129             :     STV_f32_v4_ari_64   = 3114,
    3130             :     STV_f32_v4_asi      = 3115,
    3131             :     STV_f32_v4_avar     = 3116,
    3132             :     STV_f64_v2_areg     = 3117,
    3133             :     STV_f64_v2_areg_64  = 3118,
    3134             :     STV_f64_v2_ari      = 3119,
    3135             :     STV_f64_v2_ari_64   = 3120,
    3136             :     STV_f64_v2_asi      = 3121,
    3137             :     STV_f64_v2_avar     = 3122,
    3138             :     STV_f64_v4_areg     = 3123,
    3139             :     STV_f64_v4_areg_64  = 3124,
    3140             :     STV_f64_v4_ari      = 3125,
    3141             :     STV_f64_v4_ari_64   = 3126,
    3142             :     STV_f64_v4_asi      = 3127,
    3143             :     STV_f64_v4_avar     = 3128,
    3144             :     STV_i16_v2_areg     = 3129,
    3145             :     STV_i16_v2_areg_64  = 3130,
    3146             :     STV_i16_v2_ari      = 3131,
    3147             :     STV_i16_v2_ari_64   = 3132,
    3148             :     STV_i16_v2_asi      = 3133,
    3149             :     STV_i16_v2_avar     = 3134,
    3150             :     STV_i16_v4_areg     = 3135,
    3151             :     STV_i16_v4_areg_64  = 3136,
    3152             :     STV_i16_v4_ari      = 3137,
    3153             :     STV_i16_v4_ari_64   = 3138,
    3154             :     STV_i16_v4_asi      = 3139,
    3155             :     STV_i16_v4_avar     = 3140,
    3156             :     STV_i32_v2_areg     = 3141,
    3157             :     STV_i32_v2_areg_64  = 3142,
    3158             :     STV_i32_v2_ari      = 3143,
    3159             :     STV_i32_v2_ari_64   = 3144,
    3160             :     STV_i32_v2_asi      = 3145,
    3161             :     STV_i32_v2_avar     = 3146,
    3162             :     STV_i32_v4_areg     = 3147,
    3163             :     STV_i32_v4_areg_64  = 3148,
    3164             :     STV_i32_v4_ari      = 3149,
    3165             :     STV_i32_v4_ari_64   = 3150,
    3166             :     STV_i32_v4_asi      = 3151,
    3167             :     STV_i32_v4_avar     = 3152,
    3168             :     STV_i64_v2_areg     = 3153,
    3169             :     STV_i64_v2_areg_64  = 3154,
    3170             :     STV_i64_v2_ari      = 3155,
    3171             :     STV_i64_v2_ari_64   = 3156,
    3172             :     STV_i64_v2_asi      = 3157,
    3173             :     STV_i64_v2_avar     = 3158,
    3174             :     STV_i64_v4_areg     = 3159,
    3175             :     STV_i64_v4_areg_64  = 3160,
    3176             :     STV_i64_v4_ari      = 3161,
    3177             :     STV_i64_v4_ari_64   = 3162,
    3178             :     STV_i64_v4_asi      = 3163,
    3179             :     STV_i64_v4_avar     = 3164,
    3180             :     STV_i8_v2_areg      = 3165,
    3181             :     STV_i8_v2_areg_64   = 3166,
    3182             :     STV_i8_v2_ari       = 3167,
    3183             :     STV_i8_v2_ari_64    = 3168,
    3184             :     STV_i8_v2_asi       = 3169,
    3185             :     STV_i8_v2_avar      = 3170,
    3186             :     STV_i8_v4_areg      = 3171,
    3187             :     STV_i8_v4_areg_64   = 3172,
    3188             :     STV_i8_v4_ari       = 3173,
    3189             :     STV_i8_v4_ari_64    = 3174,
    3190             :     STV_i8_v4_asi       = 3175,
    3191             :     STV_i8_v4_avar      = 3176,
    3192             :     ST_f16_areg = 3177,
    3193             :     ST_f16_areg_64      = 3178,
    3194             :     ST_f16_ari  = 3179,
    3195             :     ST_f16_ari_64       = 3180,
    3196             :     ST_f16_asi  = 3181,
    3197             :     ST_f16_avar = 3182,
    3198             :     ST_f16x2_areg       = 3183,
    3199             :     ST_f16x2_areg_64    = 3184,
    3200             :     ST_f16x2_ari        = 3185,
    3201             :     ST_f16x2_ari_64     = 3186,
    3202             :     ST_f16x2_asi        = 3187,
    3203             :     ST_f16x2_avar       = 3188,
    3204             :     ST_f32_areg = 3189,
    3205             :     ST_f32_areg_64      = 3190,
    3206             :     ST_f32_ari  = 3191,
    3207             :     ST_f32_ari_64       = 3192,
    3208             :     ST_f32_asi  = 3193,
    3209             :     ST_f32_avar = 3194,
    3210             :     ST_f64_areg = 3195,
    3211             :     ST_f64_areg_64      = 3196,
    3212             :     ST_f64_ari  = 3197,
    3213             :     ST_f64_ari_64       = 3198,
    3214             :     ST_f64_asi  = 3199,
    3215             :     ST_f64_avar = 3200,
    3216             :     ST_i16_areg = 3201,
    3217             :     ST_i16_areg_64      = 3202,
    3218             :     ST_i16_ari  = 3203,
    3219             :     ST_i16_ari_64       = 3204,
    3220             :     ST_i16_asi  = 3205,
    3221             :     ST_i16_avar = 3206,
    3222             :     ST_i32_areg = 3207,
    3223             :     ST_i32_areg_64      = 3208,
    3224             :     ST_i32_ari  = 3209,
    3225             :     ST_i32_ari_64       = 3210,
    3226             :     ST_i32_asi  = 3211,
    3227             :     ST_i32_avar = 3212,
    3228             :     ST_i64_areg = 3213,
    3229             :     ST_i64_areg_64      = 3214,
    3230             :     ST_i64_ari  = 3215,
    3231             :     ST_i64_ari_64       = 3216,
    3232             :     ST_i64_asi  = 3217,
    3233             :     ST_i64_avar = 3218,
    3234             :     ST_i8_areg  = 3219,
    3235             :     ST_i8_areg_64       = 3220,
    3236             :     ST_i8_ari   = 3221,
    3237             :     ST_i8_ari_64        = 3222,
    3238             :     ST_i8_asi   = 3223,
    3239             :     ST_i8_avar  = 3224,
    3240             :     SUBCCCi32ri = 3225,
    3241             :     SUBCCCi32rr = 3226,
    3242             :     SUBCCi32ri  = 3227,
    3243             :     SUBCCi32rr  = 3228,
    3244             :     SUB_i1_ri   = 3229,
    3245             :     SUB_i1_rr   = 3230,
    3246             :     SUBi16ri    = 3231,
    3247             :     SUBi16rr    = 3232,
    3248             :     SUBi32ri    = 3233,
    3249             :     SUBi32rr    = 3234,
    3250             :     SUBi64ri    = 3235,
    3251             :     SUBi64rr    = 3236,
    3252             :     SULD_1D_ARRAY_I16_CLAMP     = 3237,
    3253             :     SULD_1D_ARRAY_I16_TRAP      = 3238,
    3254             :     SULD_1D_ARRAY_I16_ZERO      = 3239,
    3255             :     SULD_1D_ARRAY_I32_CLAMP     = 3240,
    3256             :     SULD_1D_ARRAY_I32_TRAP      = 3241,
    3257             :     SULD_1D_ARRAY_I32_ZERO      = 3242,
    3258             :     SULD_1D_ARRAY_I64_CLAMP     = 3243,
    3259             :     SULD_1D_ARRAY_I64_TRAP      = 3244,
    3260             :     SULD_1D_ARRAY_I64_ZERO      = 3245,
    3261             :     SULD_1D_ARRAY_I8_CLAMP      = 3246,
    3262             :     SULD_1D_ARRAY_I8_TRAP       = 3247,
    3263             :     SULD_1D_ARRAY_I8_ZERO       = 3248,
    3264             :     SULD_1D_ARRAY_V2I16_CLAMP   = 3249,
    3265             :     SULD_1D_ARRAY_V2I16_TRAP    = 3250,
    3266             :     SULD_1D_ARRAY_V2I16_ZERO    = 3251,
    3267             :     SULD_1D_ARRAY_V2I32_CLAMP   = 3252,
    3268             :     SULD_1D_ARRAY_V2I32_TRAP    = 3253,
    3269             :     SULD_1D_ARRAY_V2I32_ZERO    = 3254,
    3270             :     SULD_1D_ARRAY_V2I64_CLAMP   = 3255,
    3271             :     SULD_1D_ARRAY_V2I64_TRAP    = 3256,
    3272             :     SULD_1D_ARRAY_V2I64_ZERO    = 3257,
    3273             :     SULD_1D_ARRAY_V2I8_CLAMP    = 3258,
    3274             :     SULD_1D_ARRAY_V2I8_TRAP     = 3259,
    3275             :     SULD_1D_ARRAY_V2I8_ZERO     = 3260,
    3276             :     SULD_1D_ARRAY_V4I16_CLAMP   = 3261,
    3277             :     SULD_1D_ARRAY_V4I16_TRAP    = 3262,
    3278             :     SULD_1D_ARRAY_V4I16_ZERO    = 3263,
    3279             :     SULD_1D_ARRAY_V4I32_CLAMP   = 3264,
    3280             :     SULD_1D_ARRAY_V4I32_TRAP    = 3265,
    3281             :     SULD_1D_ARRAY_V4I32_ZERO    = 3266,
    3282             :     SULD_1D_ARRAY_V4I8_CLAMP    = 3267,
    3283             :     SULD_1D_ARRAY_V4I8_TRAP     = 3268,
    3284             :     SULD_1D_ARRAY_V4I8_ZERO     = 3269,
    3285             :     SULD_1D_I16_CLAMP   = 3270,
    3286             :     SULD_1D_I16_TRAP    = 3271,
    3287             :     SULD_1D_I16_ZERO    = 3272,
    3288             :     SULD_1D_I32_CLAMP   = 3273,
    3289             :     SULD_1D_I32_TRAP    = 3274,
    3290             :     SULD_1D_I32_ZERO    = 3275,
    3291             :     SULD_1D_I64_CLAMP   = 3276,
    3292             :     SULD_1D_I64_TRAP    = 3277,
    3293             :     SULD_1D_I64_ZERO    = 3278,
    3294             :     SULD_1D_I8_CLAMP    = 3279,
    3295             :     SULD_1D_I8_TRAP     = 3280,
    3296             :     SULD_1D_I8_ZERO     = 3281,
    3297             :     SULD_1D_V2I16_CLAMP = 3282,
    3298             :     SULD_1D_V2I16_TRAP  = 3283,
    3299             :     SULD_1D_V2I16_ZERO  = 3284,
    3300             :     SULD_1D_V2I32_CLAMP = 3285,
    3301             :     SULD_1D_V2I32_TRAP  = 3286,
    3302             :     SULD_1D_V2I32_ZERO  = 3287,
    3303             :     SULD_1D_V2I64_CLAMP = 3288,
    3304             :     SULD_1D_V2I64_TRAP  = 3289,
    3305             :     SULD_1D_V2I64_ZERO  = 3290,
    3306             :     SULD_1D_V2I8_CLAMP  = 3291,
    3307             :     SULD_1D_V2I8_TRAP   = 3292,
    3308             :     SULD_1D_V2I8_ZERO   = 3293,
    3309             :     SULD_1D_V4I16_CLAMP = 3294,
    3310             :     SULD_1D_V4I16_TRAP  = 3295,
    3311             :     SULD_1D_V4I16_ZERO  = 3296,
    3312             :     SULD_1D_V4I32_CLAMP = 3297,
    3313             :     SULD_1D_V4I32_TRAP  = 3298,
    3314             :     SULD_1D_V4I32_ZERO  = 3299,
    3315             :     SULD_1D_V4I8_CLAMP  = 3300,
    3316             :     SULD_1D_V4I8_TRAP   = 3301,
    3317             :     SULD_1D_V4I8_ZERO   = 3302,
    3318             :     SULD_2D_ARRAY_I16_CLAMP     = 3303,
    3319             :     SULD_2D_ARRAY_I16_TRAP      = 3304,
    3320             :     SULD_2D_ARRAY_I16_ZERO      = 3305,
    3321             :     SULD_2D_ARRAY_I32_CLAMP     = 3306,
    3322             :     SULD_2D_ARRAY_I32_TRAP      = 3307,
    3323             :     SULD_2D_ARRAY_I32_ZERO      = 3308,
    3324             :     SULD_2D_ARRAY_I64_CLAMP     = 3309,
    3325             :     SULD_2D_ARRAY_I64_TRAP      = 3310,
    3326             :     SULD_2D_ARRAY_I64_ZERO      = 3311,
    3327             :     SULD_2D_ARRAY_I8_CLAMP      = 3312,
    3328             :     SULD_2D_ARRAY_I8_TRAP       = 3313,
    3329             :     SULD_2D_ARRAY_I8_ZERO       = 3314,
    3330             :     SULD_2D_ARRAY_V2I16_CLAMP   = 3315,
    3331             :     SULD_2D_ARRAY_V2I16_TRAP    = 3316,
    3332             :     SULD_2D_ARRAY_V2I16_ZERO    = 3317,
    3333             :     SULD_2D_ARRAY_V2I32_CLAMP   = 3318,
    3334             :     SULD_2D_ARRAY_V2I32_TRAP    = 3319,
    3335             :     SULD_2D_ARRAY_V2I32_ZERO    = 3320,
    3336             :     SULD_2D_ARRAY_V2I64_CLAMP   = 3321,
    3337             :     SULD_2D_ARRAY_V2I64_TRAP    = 3322,
    3338             :     SULD_2D_ARRAY_V2I64_ZERO    = 3323,
    3339             :     SULD_2D_ARRAY_V2I8_CLAMP    = 3324,
    3340             :     SULD_2D_ARRAY_V2I8_TRAP     = 3325,
    3341             :     SULD_2D_ARRAY_V2I8_ZERO     = 3326,
    3342             :     SULD_2D_ARRAY_V4I16_CLAMP   = 3327,
    3343             :     SULD_2D_ARRAY_V4I16_TRAP    = 3328,
    3344             :     SULD_2D_ARRAY_V4I16_ZERO    = 3329,
    3345             :     SULD_2D_ARRAY_V4I32_CLAMP   = 3330,
    3346             :     SULD_2D_ARRAY_V4I32_TRAP    = 3331,
    3347             :     SULD_2D_ARRAY_V4I32_ZERO    = 3332,
    3348             :     SULD_2D_ARRAY_V4I8_CLAMP    = 3333,
    3349             :     SULD_2D_ARRAY_V4I8_TRAP     = 3334,
    3350             :     SULD_2D_ARRAY_V4I8_ZERO     = 3335,
    3351             :     SULD_2D_I16_CLAMP   = 3336,
    3352             :     SULD_2D_I16_TRAP    = 3337,
    3353             :     SULD_2D_I16_ZERO    = 3338,
    3354             :     SULD_2D_I32_CLAMP   = 3339,
    3355             :     SULD_2D_I32_TRAP    = 3340,
    3356             :     SULD_2D_I32_ZERO    = 3341,
    3357             :     SULD_2D_I64_CLAMP   = 3342,
    3358             :     SULD_2D_I64_TRAP    = 3343,
    3359             :     SULD_2D_I64_ZERO    = 3344,
    3360             :     SULD_2D_I8_CLAMP    = 3345,
    3361             :     SULD_2D_I8_TRAP     = 3346,
    3362             :     SULD_2D_I8_ZERO     = 3347,
    3363             :     SULD_2D_V2I16_CLAMP = 3348,
    3364             :     SULD_2D_V2I16_TRAP  = 3349,
    3365             :     SULD_2D_V2I16_ZERO  = 3350,
    3366             :     SULD_2D_V2I32_CLAMP = 3351,
    3367             :     SULD_2D_V2I32_TRAP  = 3352,
    3368             :     SULD_2D_V2I32_ZERO  = 3353,
    3369             :     SULD_2D_V2I64_CLAMP = 3354,
    3370             :     SULD_2D_V2I64_TRAP  = 3355,
    3371             :     SULD_2D_V2I64_ZERO  = 3356,
    3372             :     SULD_2D_V2I8_CLAMP  = 3357,
    3373             :     SULD_2D_V2I8_TRAP   = 3358,
    3374             :     SULD_2D_V2I8_ZERO   = 3359,
    3375             :     SULD_2D_V4I16_CLAMP = 3360,
    3376             :     SULD_2D_V4I16_TRAP  = 3361,
    3377             :     SULD_2D_V4I16_ZERO  = 3362,
    3378             :     SULD_2D_V4I32_CLAMP = 3363,
    3379             :     SULD_2D_V4I32_TRAP  = 3364,
    3380             :     SULD_2D_V4I32_ZERO  = 3365,
    3381             :     SULD_2D_V4I8_CLAMP  = 3366,
    3382             :     SULD_2D_V4I8_TRAP   = 3367,
    3383             :     SULD_2D_V4I8_ZERO   = 3368,
    3384             :     SULD_3D_I16_CLAMP   = 3369,
    3385             :     SULD_3D_I16_TRAP    = 3370,
    3386             :     SULD_3D_I16_ZERO    = 3371,
    3387             :     SULD_3D_I32_CLAMP   = 3372,
    3388             :     SULD_3D_I32_TRAP    = 3373,
    3389             :     SULD_3D_I32_ZERO    = 3374,
    3390             :     SULD_3D_I64_CLAMP   = 3375,
    3391             :     SULD_3D_I64_TRAP    = 3376,
    3392             :     SULD_3D_I64_ZERO    = 3377,
    3393             :     SULD_3D_I8_CLAMP    = 3378,
    3394             :     SULD_3D_I8_TRAP     = 3379,
    3395             :     SULD_3D_I8_ZERO     = 3380,
    3396             :     SULD_3D_V2I16_CLAMP = 3381,
    3397             :     SULD_3D_V2I16_TRAP  = 3382,
    3398             :     SULD_3D_V2I16_ZERO  = 3383,
    3399             :     SULD_3D_V2I32_CLAMP = 3384,
    3400             :     SULD_3D_V2I32_TRAP  = 3385,
    3401             :     SULD_3D_V2I32_ZERO  = 3386,
    3402             :     SULD_3D_V2I64_CLAMP = 3387,
    3403             :     SULD_3D_V2I64_TRAP  = 3388,
    3404             :     SULD_3D_V2I64_ZERO  = 3389,
    3405             :     SULD_3D_V2I8_CLAMP  = 3390,
    3406             :     SULD_3D_V2I8_TRAP   = 3391,
    3407             :     SULD_3D_V2I8_ZERO   = 3392,
    3408             :     SULD_3D_V4I16_CLAMP = 3393,
    3409             :     SULD_3D_V4I16_TRAP  = 3394,
    3410             :     SULD_3D_V4I16_ZERO  = 3395,
    3411             :     SULD_3D_V4I32_CLAMP = 3396,
    3412             :     SULD_3D_V4I32_TRAP  = 3397,
    3413             :     SULD_3D_V4I32_ZERO  = 3398,
    3414             :     SULD_3D_V4I8_CLAMP  = 3399,
    3415             :     SULD_3D_V4I8_TRAP   = 3400,
    3416             :     SULD_3D_V4I8_ZERO   = 3401,
    3417             :     SUQ_ARRAY_SIZE      = 3402,
    3418             :     SUQ_CHANNEL_DATA_TYPE       = 3403,
    3419             :     SUQ_CHANNEL_ORDER   = 3404,
    3420             :     SUQ_DEPTH   = 3405,
    3421             :     SUQ_HEIGHT  = 3406,
    3422             :     SUQ_WIDTH   = 3407,
    3423             :     SUST_B_1D_ARRAY_B16_CLAMP   = 3408,
    3424             :     SUST_B_1D_ARRAY_B16_TRAP    = 3409,
    3425             :     SUST_B_1D_ARRAY_B16_ZERO    = 3410,
    3426             :     SUST_B_1D_ARRAY_B32_CLAMP   = 3411,
    3427             :     SUST_B_1D_ARRAY_B32_TRAP    = 3412,
    3428             :     SUST_B_1D_ARRAY_B32_ZERO    = 3413,
    3429             :     SUST_B_1D_ARRAY_B64_CLAMP   = 3414,
    3430             :     SUST_B_1D_ARRAY_B64_TRAP    = 3415,
    3431             :     SUST_B_1D_ARRAY_B64_ZERO    = 3416,
    3432             :     SUST_B_1D_ARRAY_B8_CLAMP    = 3417,
    3433             :     SUST_B_1D_ARRAY_B8_TRAP     = 3418,
    3434             :     SUST_B_1D_ARRAY_B8_ZERO     = 3419,
    3435             :     SUST_B_1D_ARRAY_V2B16_CLAMP = 3420,
    3436             :     SUST_B_1D_ARRAY_V2B16_TRAP  = 3421,
    3437             :     SUST_B_1D_ARRAY_V2B16_ZERO  = 3422,
    3438             :     SUST_B_1D_ARRAY_V2B32_CLAMP = 3423,
    3439             :     SUST_B_1D_ARRAY_V2B32_TRAP  = 3424,
    3440             :     SUST_B_1D_ARRAY_V2B32_ZERO  = 3425,
    3441             :     SUST_B_1D_ARRAY_V2B64_CLAMP = 3426,
    3442             :     SUST_B_1D_ARRAY_V2B64_TRAP  = 3427,
    3443             :     SUST_B_1D_ARRAY_V2B64_ZERO  = 3428,
    3444             :     SUST_B_1D_ARRAY_V2B8_CLAMP  = 3429,
    3445             :     SUST_B_1D_ARRAY_V2B8_TRAP   = 3430,
    3446             :     SUST_B_1D_ARRAY_V2B8_ZERO   = 3431,
    3447             :     SUST_B_1D_ARRAY_V4B16_CLAMP = 3432,
    3448             :     SUST_B_1D_ARRAY_V4B16_TRAP  = 3433,
    3449             :     SUST_B_1D_ARRAY_V4B16_ZERO  = 3434,
    3450             :     SUST_B_1D_ARRAY_V4B32_CLAMP = 3435,
    3451             :     SUST_B_1D_ARRAY_V4B32_TRAP  = 3436,
    3452             :     SUST_B_1D_ARRAY_V4B32_ZERO  = 3437,
    3453             :     SUST_B_1D_ARRAY_V4B8_CLAMP  = 3438,
    3454             :     SUST_B_1D_ARRAY_V4B8_TRAP   = 3439,
    3455             :     SUST_B_1D_ARRAY_V4B8_ZERO   = 3440,
    3456             :     SUST_B_1D_B16_CLAMP = 3441,
    3457             :     SUST_B_1D_B16_TRAP  = 3442,
    3458             :     SUST_B_1D_B16_ZERO  = 3443,
    3459             :     SUST_B_1D_B32_CLAMP = 3444,
    3460             :     SUST_B_1D_B32_TRAP  = 3445,
    3461             :     SUST_B_1D_B32_ZERO  = 3446,
    3462             :     SUST_B_1D_B64_CLAMP = 3447,
    3463             :     SUST_B_1D_B64_TRAP  = 3448,
    3464             :     SUST_B_1D_B64_ZERO  = 3449,
    3465             :     SUST_B_1D_B8_CLAMP  = 3450,
    3466             :     SUST_B_1D_B8_TRAP   = 3451,
    3467             :     SUST_B_1D_B8_ZERO   = 3452,
    3468             :     SUST_B_1D_V2B16_CLAMP       = 3453,
    3469             :     SUST_B_1D_V2B16_TRAP        = 3454,
    3470             :     SUST_B_1D_V2B16_ZERO        = 3455,
    3471             :     SUST_B_1D_V2B32_CLAMP       = 3456,
    3472             :     SUST_B_1D_V2B32_TRAP        = 3457,
    3473             :     SUST_B_1D_V2B32_ZERO        = 3458,
    3474             :     SUST_B_1D_V2B64_CLAMP       = 3459,
    3475             :     SUST_B_1D_V2B64_TRAP        = 3460,
    3476             :     SUST_B_1D_V2B64_ZERO        = 3461,
    3477             :     SUST_B_1D_V2B8_CLAMP        = 3462,
    3478             :     SUST_B_1D_V2B8_TRAP = 3463,
    3479             :     SUST_B_1D_V2B8_ZERO = 3464,
    3480             :     SUST_B_1D_V4B16_CLAMP       = 3465,
    3481             :     SUST_B_1D_V4B16_TRAP        = 3466,
    3482             :     SUST_B_1D_V4B16_ZERO        = 3467,
    3483             :     SUST_B_1D_V4B32_CLAMP       = 3468,
    3484             :     SUST_B_1D_V4B32_TRAP        = 3469,
    3485             :     SUST_B_1D_V4B32_ZERO        = 3470,
    3486             :     SUST_B_1D_V4B8_CLAMP        = 3471,
    3487             :     SUST_B_1D_V4B8_TRAP = 3472,
    3488             :     SUST_B_1D_V4B8_ZERO = 3473,
    3489             :     SUST_B_2D_ARRAY_B16_CLAMP   = 3474,
    3490             :     SUST_B_2D_ARRAY_B16_TRAP    = 3475,
    3491             :     SUST_B_2D_ARRAY_B16_ZERO    = 3476,
    3492             :     SUST_B_2D_ARRAY_B32_CLAMP   = 3477,
    3493             :     SUST_B_2D_ARRAY_B32_TRAP    = 3478,
    3494             :     SUST_B_2D_ARRAY_B32_ZERO    = 3479,
    3495             :     SUST_B_2D_ARRAY_B64_CLAMP   = 3480,
    3496             :     SUST_B_2D_ARRAY_B64_TRAP    = 3481,
    3497             :     SUST_B_2D_ARRAY_B64_ZERO    = 3482,
    3498             :     SUST_B_2D_ARRAY_B8_CLAMP    = 3483,
    3499             :     SUST_B_2D_ARRAY_B8_TRAP     = 3484,
    3500             :     SUST_B_2D_ARRAY_B8_ZERO     = 3485,
    3501             :     SUST_B_2D_ARRAY_V2B16_CLAMP = 3486,
    3502             :     SUST_B_2D_ARRAY_V2B16_TRAP  = 3487,
    3503             :     SUST_B_2D_ARRAY_V2B16_ZERO  = 3488,
    3504             :     SUST_B_2D_ARRAY_V2B32_CLAMP = 3489,
    3505             :     SUST_B_2D_ARRAY_V2B32_TRAP  = 3490,
    3506             :     SUST_B_2D_ARRAY_V2B32_ZERO  = 3491,
    3507             :     SUST_B_2D_ARRAY_V2B64_CLAMP = 3492,
    3508             :     SUST_B_2D_ARRAY_V2B64_TRAP  = 3493,
    3509             :     SUST_B_2D_ARRAY_V2B64_ZERO  = 3494,
    3510             :     SUST_B_2D_ARRAY_V2B8_CLAMP  = 3495,
    3511             :     SUST_B_2D_ARRAY_V2B8_TRAP   = 3496,
    3512             :     SUST_B_2D_ARRAY_V2B8_ZERO   = 3497,
    3513             :     SUST_B_2D_ARRAY_V4B16_CLAMP = 3498,
    3514             :     SUST_B_2D_ARRAY_V4B16_TRAP  = 3499,
    3515             :     SUST_B_2D_ARRAY_V4B16_ZERO  = 3500,
    3516             :     SUST_B_2D_ARRAY_V4B32_CLAMP = 3501,
    3517             :     SUST_B_2D_ARRAY_V4B32_TRAP  = 3502,
    3518             :     SUST_B_2D_ARRAY_V4B32_ZERO  = 3503,
    3519             :     SUST_B_2D_ARRAY_V4B8_CLAMP  = 3504,
    3520             :     SUST_B_2D_ARRAY_V4B8_TRAP   = 3505,
    3521             :     SUST_B_2D_ARRAY_V4B8_ZERO   = 3506,
    3522             :     SUST_B_2D_B16_CLAMP = 3507,
    3523             :     SUST_B_2D_B16_TRAP  = 3508,
    3524             :     SUST_B_2D_B16_ZERO  = 3509,
    3525             :     SUST_B_2D_B32_CLAMP = 3510,
    3526             :     SUST_B_2D_B32_TRAP  = 3511,
    3527             :     SUST_B_2D_B32_ZERO  = 3512,
    3528             :     SUST_B_2D_B64_CLAMP = 3513,
    3529             :     SUST_B_2D_B64_TRAP  = 3514,
    3530             :     SUST_B_2D_B64_ZERO  = 3515,
    3531             :     SUST_B_2D_B8_CLAMP  = 3516,
    3532             :     SUST_B_2D_B8_TRAP   = 3517,
    3533             :     SUST_B_2D_B8_ZERO   = 3518,
    3534             :     SUST_B_2D_V2B16_CLAMP       = 3519,
    3535             :     SUST_B_2D_V2B16_TRAP        = 3520,
    3536             :     SUST_B_2D_V2B16_ZERO        = 3521,
    3537             :     SUST_B_2D_V2B32_CLAMP       = 3522,
    3538             :     SUST_B_2D_V2B32_TRAP        = 3523,
    3539             :     SUST_B_2D_V2B32_ZERO        = 3524,
    3540             :     SUST_B_2D_V2B64_CLAMP       = 3525,
    3541             :     SUST_B_2D_V2B64_TRAP        = 3526,
    3542             :     SUST_B_2D_V2B64_ZERO        = 3527,
    3543             :     SUST_B_2D_V2B8_CLAMP        = 3528,
    3544             :     SUST_B_2D_V2B8_TRAP = 3529,
    3545             :     SUST_B_2D_V2B8_ZERO = 3530,
    3546             :     SUST_B_2D_V4B16_CLAMP       = 3531,
    3547             :     SUST_B_2D_V4B16_TRAP        = 3532,
    3548             :     SUST_B_2D_V4B16_ZERO        = 3533,
    3549             :     SUST_B_2D_V4B32_CLAMP       = 3534,
    3550             :     SUST_B_2D_V4B32_TRAP        = 3535,
    3551             :     SUST_B_2D_V4B32_ZERO        = 3536,
    3552             :     SUST_B_2D_V4B8_CLAMP        = 3537,
    3553             :     SUST_B_2D_V4B8_TRAP = 3538,
    3554             :     SUST_B_2D_V4B8_ZERO = 3539,
    3555             :     SUST_B_3D_B16_CLAMP = 3540,
    3556             :     SUST_B_3D_B16_TRAP  = 3541,
    3557             :     SUST_B_3D_B16_ZERO  = 3542,
    3558             :     SUST_B_3D_B32_CLAMP = 3543,
    3559             :     SUST_B_3D_B32_TRAP  = 3544,
    3560             :     SUST_B_3D_B32_ZERO  = 3545,
    3561             :     SUST_B_3D_B64_CLAMP = 3546,
    3562             :     SUST_B_3D_B64_TRAP  = 3547,
    3563             :     SUST_B_3D_B64_ZERO  = 3548,
    3564             :     SUST_B_3D_B8_CLAMP  = 3549,
    3565             :     SUST_B_3D_B8_TRAP   = 3550,
    3566             :     SUST_B_3D_B8_ZERO   = 3551,
    3567             :     SUST_B_3D_V2B16_CLAMP       = 3552,
    3568             :     SUST_B_3D_V2B16_TRAP        = 3553,
    3569             :     SUST_B_3D_V2B16_ZERO        = 3554,
    3570             :     SUST_B_3D_V2B32_CLAMP       = 3555,
    3571             :     SUST_B_3D_V2B32_TRAP        = 3556,
    3572             :     SUST_B_3D_V2B32_ZERO        = 3557,
    3573             :     SUST_B_3D_V2B64_CLAMP       = 3558,
    3574             :     SUST_B_3D_V2B64_TRAP        = 3559,
    3575             :     SUST_B_3D_V2B64_ZERO        = 3560,
    3576             :     SUST_B_3D_V2B8_CLAMP        = 3561,
    3577             :     SUST_B_3D_V2B8_TRAP = 3562,
    3578             :     SUST_B_3D_V2B8_ZERO = 3563,
    3579             :     SUST_B_3D_V4B16_CLAMP       = 3564,
    3580             :     SUST_B_3D_V4B16_TRAP        = 3565,
    3581             :     SUST_B_3D_V4B16_ZERO        = 3566,
    3582             :     SUST_B_3D_V4B32_CLAMP       = 3567,
    3583             :     SUST_B_3D_V4B32_TRAP        = 3568,
    3584             :     SUST_B_3D_V4B32_ZERO        = 3569,
    3585             :     SUST_B_3D_V4B8_CLAMP        = 3570,
    3586             :     SUST_B_3D_V4B8_TRAP = 3571,
    3587             :     SUST_B_3D_V4B8_ZERO = 3572,
    3588             :     SUST_P_1D_ARRAY_B16_TRAP    = 3573,
    3589             :     SUST_P_1D_ARRAY_B32_TRAP    = 3574,
    3590             :     SUST_P_1D_ARRAY_B8_TRAP     = 3575,
    3591             :     SUST_P_1D_ARRAY_V2B16_TRAP  = 3576,
    3592             :     SUST_P_1D_ARRAY_V2B32_TRAP  = 3577,
    3593             :     SUST_P_1D_ARRAY_V2B8_TRAP   = 3578,
    3594             :     SUST_P_1D_ARRAY_V4B16_TRAP  = 3579,
    3595             :     SUST_P_1D_ARRAY_V4B32_TRAP  = 3580,
    3596             :     SUST_P_1D_ARRAY_V4B8_TRAP   = 3581,
    3597             :     SUST_P_1D_B16_TRAP  = 3582,
    3598             :     SUST_P_1D_B32_TRAP  = 3583,
    3599             :     SUST_P_1D_B8_TRAP   = 3584,
    3600             :     SUST_P_1D_V2B16_TRAP        = 3585,
    3601             :     SUST_P_1D_V2B32_TRAP        = 3586,
    3602             :     SUST_P_1D_V2B8_TRAP = 3587,
    3603             :     SUST_P_1D_V4B16_TRAP        = 3588,
    3604             :     SUST_P_1D_V4B32_TRAP        = 3589,
    3605             :     SUST_P_1D_V4B8_TRAP = 3590,
    3606             :     SUST_P_2D_ARRAY_B16_TRAP    = 3591,
    3607             :     SUST_P_2D_ARRAY_B32_TRAP    = 3592,
    3608             :     SUST_P_2D_ARRAY_B8_TRAP     = 3593,
    3609             :     SUST_P_2D_ARRAY_V2B16_TRAP  = 3594,
    3610             :     SUST_P_2D_ARRAY_V2B32_TRAP  = 3595,
    3611             :     SUST_P_2D_ARRAY_V2B8_TRAP   = 3596,
    3612             :     SUST_P_2D_ARRAY_V4B16_TRAP  = 3597,
    3613             :     SUST_P_2D_ARRAY_V4B32_TRAP  = 3598,
    3614             :     SUST_P_2D_ARRAY_V4B8_TRAP   = 3599,
    3615             :     SUST_P_2D_B16_TRAP  = 3600,
    3616             :     SUST_P_2D_B32_TRAP  = 3601,
    3617             :     SUST_P_2D_B8_TRAP   = 3602,
    3618             :     SUST_P_2D_V2B16_TRAP        = 3603,
    3619             :     SUST_P_2D_V2B32_TRAP        = 3604,
    3620             :     SUST_P_2D_V2B8_TRAP = 3605,
    3621             :     SUST_P_2D_V4B16_TRAP        = 3606,
    3622             :     SUST_P_2D_V4B32_TRAP        = 3607,
    3623             :     SUST_P_2D_V4B8_TRAP = 3608,
    3624             :     SUST_P_3D_B16_TRAP  = 3609,
    3625             :     SUST_P_3D_B32_TRAP  = 3610,
    3626             :     SUST_P_3D_B8_TRAP   = 3611,
    3627             :     SUST_P_3D_V2B16_TRAP        = 3612,
    3628             :     SUST_P_3D_V2B32_TRAP        = 3613,
    3629             :     SUST_P_3D_V2B8_TRAP = 3614,
    3630             :     SUST_P_3D_V4B16_TRAP        = 3615,
    3631             :     SUST_P_3D_V4B32_TRAP        = 3616,
    3632             :     SUST_P_3D_V4B8_TRAP = 3617,
    3633             :     SplitF16x2  = 3618,
    3634             :     SplitI32toF16x2     = 3619,
    3635             :     StoreParamF16       = 3620,
    3636             :     StoreParamF16x2     = 3621,
    3637             :     StoreParamF32       = 3622,
    3638             :     StoreParamF64       = 3623,
    3639             :     StoreParamI16       = 3624,
    3640             :     StoreParamI32       = 3625,
    3641             :     StoreParamI64       = 3626,
    3642             :     StoreParamI8        = 3627,
    3643             :     StoreParamV2F16     = 3628,
    3644             :     StoreParamV2F16x2   = 3629,
    3645             :     StoreParamV2F32     = 3630,
    3646             :     StoreParamV2F64     = 3631,
    3647             :     StoreParamV2I16     = 3632,
    3648             :     StoreParamV2I32     = 3633,
    3649             :     StoreParamV2I64     = 3634,
    3650             :     StoreParamV2I8      = 3635,
    3651             :     StoreParamV4F16     = 3636,
    3652             :     StoreParamV4F16x2   = 3637,
    3653             :     StoreParamV4F32     = 3638,
    3654             :     StoreParamV4I16     = 3639,
    3655             :     StoreParamV4I32     = 3640,
    3656             :     StoreParamV4I8      = 3641,
    3657             :     StoreRetvalF16      = 3642,
    3658             :     StoreRetvalF16x2    = 3643,
    3659             :     StoreRetvalF32      = 3644,
    3660             :     StoreRetvalF64      = 3645,
    3661             :     StoreRetvalI16      = 3646,
    3662             :     StoreRetvalI32      = 3647,
    3663             :     StoreRetvalI64      = 3648,
    3664             :     StoreRetvalI8       = 3649,
    3665             :     StoreRetvalV2F16    = 3650,
    3666             :     StoreRetvalV2F16x2  = 3651,
    3667             :     StoreRetvalV2F32    = 3652,
    3668             :     StoreRetvalV2F64    = 3653,
    3669             :     StoreRetvalV2I16    = 3654,
    3670             :     StoreRetvalV2I32    = 3655,
    3671             :     StoreRetvalV2I64    = 3656,
    3672             :     StoreRetvalV2I8     = 3657,
    3673             :     StoreRetvalV4F16    = 3658,
    3674             :     StoreRetvalV4F16x2  = 3659,
    3675             :     StoreRetvalV4F32    = 3660,
    3676             :     StoreRetvalV4I16    = 3661,
    3677             :     StoreRetvalV4I32    = 3662,
    3678             :     StoreRetvalV4I8     = 3663,
    3679             :     TEX_1D_ARRAY_F32_F32        = 3664,
    3680             :     TEX_1D_ARRAY_F32_F32_GRAD   = 3665,
    3681             :     TEX_1D_ARRAY_F32_F32_LEVEL  = 3666,
    3682             :     TEX_1D_ARRAY_F32_S32        = 3667,
    3683             :     TEX_1D_ARRAY_S32_F32        = 3668,
    3684             :     TEX_1D_ARRAY_S32_F32_GRAD   = 3669,
    3685             :     TEX_1D_ARRAY_S32_F32_LEVEL  = 3670,
    3686             :     TEX_1D_ARRAY_S32_S32        = 3671,
    3687             :     TEX_1D_ARRAY_U32_F32        = 3672,
    3688             :     TEX_1D_ARRAY_U32_F32_GRAD   = 3673,
    3689             :     TEX_1D_ARRAY_U32_F32_LEVEL  = 3674,
    3690             :     TEX_1D_ARRAY_U32_S32        = 3675,
    3691             :     TEX_1D_F32_F32      = 3676,
    3692             :     TEX_1D_F32_F32_GRAD = 3677,
    3693             :     TEX_1D_F32_F32_LEVEL        = 3678,
    3694             :     TEX_1D_F32_S32      = 3679,
    3695             :     TEX_1D_S32_F32      = 3680,
    3696             :     TEX_1D_S32_F32_GRAD = 3681,
    3697             :     TEX_1D_S32_F32_LEVEL        = 3682,
    3698             :     TEX_1D_S32_S32      = 3683,
    3699             :     TEX_1D_U32_F32      = 3684,
    3700             :     TEX_1D_U32_F32_GRAD = 3685,
    3701             :     TEX_1D_U32_F32_LEVEL        = 3686,
    3702             :     TEX_1D_U32_S32      = 3687,
    3703             :     TEX_2D_ARRAY_F32_F32        = 3688,
    3704             :     TEX_2D_ARRAY_F32_F32_GRAD   = 3689,
    3705             :     TEX_2D_ARRAY_F32_F32_LEVEL  = 3690,
    3706             :     TEX_2D_ARRAY_F32_S32        = 3691,
    3707             :     TEX_2D_ARRAY_S32_F32        = 3692,
    3708             :     TEX_2D_ARRAY_S32_F32_GRAD   = 3693,
    3709             :     TEX_2D_ARRAY_S32_F32_LEVEL  = 3694,
    3710             :     TEX_2D_ARRAY_S32_S32        = 3695,
    3711             :     TEX_2D_ARRAY_U32_F32        = 3696,
    3712             :     TEX_2D_ARRAY_U32_F32_GRAD   = 3697,
    3713             :     TEX_2D_ARRAY_U32_F32_LEVEL  = 3698,
    3714             :     TEX_2D_ARRAY_U32_S32        = 3699,
    3715             :     TEX_2D_F32_F32      = 3700,
    3716             :     TEX_2D_F32_F32_GRAD = 3701,
    3717             :     TEX_2D_F32_F32_LEVEL        = 3702,
    3718             :     TEX_2D_F32_S32      = 3703,
    3719             :     TEX_2D_S32_F32      = 3704,
    3720             :     TEX_2D_S32_F32_GRAD = 3705,
    3721             :     TEX_2D_S32_F32_LEVEL        = 3706,
    3722             :     TEX_2D_S32_S32      = 3707,
    3723             :     TEX_2D_U32_F32      = 3708,
    3724             :     TEX_2D_U32_F32_GRAD = 3709,
    3725             :     TEX_2D_U32_F32_LEVEL        = 3710,
    3726             :     TEX_2D_U32_S32      = 3711,
    3727             :     TEX_3D_F32_F32      = 3712,
    3728             :     TEX_3D_F32_F32_GRAD = 3713,
    3729             :     TEX_3D_F32_F32_LEVEL        = 3714,
    3730             :     TEX_3D_F32_S32      = 3715,
    3731             :     TEX_3D_S32_F32      = 3716,
    3732             :     TEX_3D_S32_F32_GRAD = 3717,
    3733             :     TEX_3D_S32_F32_LEVEL        = 3718,
    3734             :     TEX_3D_S32_S32      = 3719,
    3735             :     TEX_3D_U32_F32      = 3720,
    3736             :     TEX_3D_U32_F32_GRAD = 3721,
    3737             :     TEX_3D_U32_F32_LEVEL        = 3722,
    3738             :     TEX_3D_U32_S32      = 3723,
    3739             :     TEX_CUBE_ARRAY_F32_F32      = 3724,
    3740             :     TEX_CUBE_ARRAY_F32_F32_LEVEL        = 3725,
    3741             :     TEX_CUBE_ARRAY_S32_F32      = 3726,
    3742             :     TEX_CUBE_ARRAY_S32_F32_LEVEL        = 3727,
    3743             :     TEX_CUBE_ARRAY_U32_F32      = 3728,
    3744             :     TEX_CUBE_ARRAY_U32_F32_LEVEL        = 3729,
    3745             :     TEX_CUBE_F32_F32    = 3730,
    3746             :     TEX_CUBE_F32_F32_LEVEL      = 3731,
    3747             :     TEX_CUBE_S32_F32    = 3732,
    3748             :     TEX_CUBE_S32_F32_LEVEL      = 3733,
    3749             :     TEX_CUBE_U32_F32    = 3734,
    3750             :     TEX_CUBE_U32_F32_LEVEL      = 3735,
    3751             :     TEX_UNIFIED_1D_ARRAY_F32_F32        = 3736,
    3752             :     TEX_UNIFIED_1D_ARRAY_F32_F32_GRAD   = 3737,
    3753             :     TEX_UNIFIED_1D_ARRAY_F32_F32_LEVEL  = 3738,
    3754             :     TEX_UNIFIED_1D_ARRAY_F32_S32        = 3739,
    3755             :     TEX_UNIFIED_1D_ARRAY_S32_F32        = 3740,
    3756             :     TEX_UNIFIED_1D_ARRAY_S32_F32_GRAD   = 3741,
    3757             :     TEX_UNIFIED_1D_ARRAY_S32_F32_LEVEL  = 3742,
    3758             :     TEX_UNIFIED_1D_ARRAY_S32_S32        = 3743,
    3759             :     TEX_UNIFIED_1D_ARRAY_U32_F32        = 3744,
    3760             :     TEX_UNIFIED_1D_ARRAY_U32_F32_GRAD   = 3745,
    3761             :     TEX_UNIFIED_1D_ARRAY_U32_F32_LEVEL  = 3746,
    3762             :     TEX_UNIFIED_1D_ARRAY_U32_S32        = 3747,
    3763             :     TEX_UNIFIED_1D_F32_F32      = 3748,
    3764             :     TEX_UNIFIED_1D_F32_F32_GRAD = 3749,
    3765             :     TEX_UNIFIED_1D_F32_F32_LEVEL        = 3750,
    3766             :     TEX_UNIFIED_1D_F32_S32      = 3751,
    3767             :     TEX_UNIFIED_1D_S32_F32      = 3752,
    3768             :     TEX_UNIFIED_1D_S32_F32_GRAD = 3753,
    3769             :     TEX_UNIFIED_1D_S32_F32_LEVEL        = 3754,
    3770             :     TEX_UNIFIED_1D_S32_S32      = 3755,
    3771             :     TEX_UNIFIED_1D_U32_F32      = 3756,
    3772             :     TEX_UNIFIED_1D_U32_F32_GRAD = 3757,
    3773             :     TEX_UNIFIED_1D_U32_F32_LEVEL        = 3758,
    3774             :     TEX_UNIFIED_1D_U32_S32      = 3759,
    3775             :     TEX_UNIFIED_2D_ARRAY_F32_F32        = 3760,
    3776             :     TEX_UNIFIED_2D_ARRAY_F32_F32_GRAD   = 3761,
    3777             :     TEX_UNIFIED_2D_ARRAY_F32_F32_LEVEL  = 3762,
    3778             :     TEX_UNIFIED_2D_ARRAY_F32_S32        = 3763,
    3779             :     TEX_UNIFIED_2D_ARRAY_S32_F32        = 3764,
    3780             :     TEX_UNIFIED_2D_ARRAY_S32_F32_GRAD   = 3765,
    3781             :     TEX_UNIFIED_2D_ARRAY_S32_F32_LEVEL  = 3766,
    3782             :     TEX_UNIFIED_2D_ARRAY_S32_S32        = 3767,
    3783             :     TEX_UNIFIED_2D_ARRAY_U32_F32        = 3768,
    3784             :     TEX_UNIFIED_2D_ARRAY_U32_F32_GRAD   = 3769,
    3785             :     TEX_UNIFIED_2D_ARRAY_U32_F32_LEVEL  = 3770,
    3786             :     TEX_UNIFIED_2D_ARRAY_U32_S32        = 3771,
    3787             :     TEX_UNIFIED_2D_F32_F32      = 3772,
    3788             :     TEX_UNIFIED_2D_F32_F32_GRAD = 3773,
    3789             :     TEX_UNIFIED_2D_F32_F32_LEVEL        = 3774,
    3790             :     TEX_UNIFIED_2D_F32_S32      = 3775,
    3791             :     TEX_UNIFIED_2D_S32_F32      = 3776,
    3792             :     TEX_UNIFIED_2D_S32_F32_GRAD = 3777,
    3793             :     TEX_UNIFIED_2D_S32_F32_LEVEL        = 3778,
    3794             :     TEX_UNIFIED_2D_S32_S32      = 3779,
    3795             :     TEX_UNIFIED_2D_U32_F32      = 3780,
    3796             :     TEX_UNIFIED_2D_U32_F32_GRAD = 3781,
    3797             :     TEX_UNIFIED_2D_U32_F32_LEVEL        = 3782,
    3798             :     TEX_UNIFIED_2D_U32_S32      = 3783,
    3799             :     TEX_UNIFIED_3D_F32_F32      = 3784,
    3800             :     TEX_UNIFIED_3D_F32_F32_GRAD = 3785,
    3801             :     TEX_UNIFIED_3D_F32_F32_LEVEL        = 3786,
    3802             :     TEX_UNIFIED_3D_F32_S32      = 3787,
    3803             :     TEX_UNIFIED_3D_S32_F32      = 3788,
    3804             :     TEX_UNIFIED_3D_S32_F32_GRAD = 3789,
    3805             :     TEX_UNIFIED_3D_S32_F32_LEVEL        = 3790,
    3806             :     TEX_UNIFIED_3D_S32_S32      = 3791,
    3807             :     TEX_UNIFIED_3D_U32_F32      = 3792,
    3808             :     TEX_UNIFIED_3D_U32_F32_GRAD = 3793,
    3809             :     TEX_UNIFIED_3D_U32_F32_LEVEL        = 3794,
    3810             :     TEX_UNIFIED_3D_U32_S32      = 3795,
    3811             :     TEX_UNIFIED_CUBE_ARRAY_F32_F32      = 3796,
    3812             :     TEX_UNIFIED_CUBE_ARRAY_F32_F32_LEVEL        = 3797,
    3813             :     TEX_UNIFIED_CUBE_ARRAY_S32_F32      = 3798,
    3814             :     TEX_UNIFIED_CUBE_ARRAY_S32_F32_LEVEL        = 3799,
    3815             :     TEX_UNIFIED_CUBE_ARRAY_U32_F32      = 3800,
    3816             :     TEX_UNIFIED_CUBE_ARRAY_U32_F32_LEVEL        = 3801,
    3817             :     TEX_UNIFIED_CUBE_F32_F32    = 3802,
    3818             :     TEX_UNIFIED_CUBE_F32_F32_LEVEL      = 3803,
    3819             :     TEX_UNIFIED_CUBE_S32_F32    = 3804,
    3820             :     TEX_UNIFIED_CUBE_S32_F32_LEVEL      = 3805,
    3821             :     TEX_UNIFIED_CUBE_U32_F32    = 3806,
    3822             :     TEX_UNIFIED_CUBE_U32_F32_LEVEL      = 3807,
    3823             :     TLD4_A_2D_F32_F32   = 3808,
    3824             :     TLD4_A_2D_S32_F32   = 3809,
    3825             :     TLD4_A_2D_U32_F32   = 3810,
    3826             :     TLD4_B_2D_F32_F32   = 3811,
    3827             :     TLD4_B_2D_S32_F32   = 3812,
    3828             :     TLD4_B_2D_U32_F32   = 3813,
    3829             :     TLD4_G_2D_F32_F32   = 3814,
    3830             :     TLD4_G_2D_S32_F32   = 3815,
    3831             :     TLD4_G_2D_U32_F32   = 3816,
    3832             :     TLD4_R_2D_F32_F32   = 3817,
    3833             :     TLD4_R_2D_S32_F32   = 3818,
    3834             :     TLD4_R_2D_U32_F32   = 3819,
    3835             :     TLD4_UNIFIED_A_2D_F32_F32   = 3820,
    3836             :     TLD4_UNIFIED_A_2D_S32_F32   = 3821,
    3837             :     TLD4_UNIFIED_A_2D_U32_F32   = 3822,
    3838             :     TLD4_UNIFIED_B_2D_F32_F32   = 3823,
    3839             :     TLD4_UNIFIED_B_2D_S32_F32   = 3824,
    3840             :     TLD4_UNIFIED_B_2D_U32_F32   = 3825,
    3841             :     TLD4_UNIFIED_G_2D_F32_F32   = 3826,
    3842             :     TLD4_UNIFIED_G_2D_S32_F32   = 3827,
    3843             :     TLD4_UNIFIED_G_2D_U32_F32   = 3828,
    3844             :     TLD4_UNIFIED_R_2D_F32_F32   = 3829,
    3845             :     TLD4_UNIFIED_R_2D_S32_F32   = 3830,
    3846             :     TLD4_UNIFIED_R_2D_U32_F32   = 3831,
    3847             :     TXQ_ARRAY_SIZE      = 3832,
    3848             :     TXQ_CHANNEL_DATA_TYPE       = 3833,
    3849             :     TXQ_CHANNEL_ORDER   = 3834,
    3850             :     TXQ_DEPTH   = 3835,
    3851             :     TXQ_HEIGHT  = 3836,
    3852             :     TXQ_NUM_MIPMAP_LEVELS       = 3837,
    3853             :     TXQ_NUM_SAMPLES     = 3838,
    3854             :     TXQ_WIDTH   = 3839,
    3855             :     UDIVi16ri   = 3840,
    3856             :     UDIVi16rr   = 3841,
    3857             :     UDIVi32ri   = 3842,
    3858             :     UDIVi32rr   = 3843,
    3859             :     UDIVi64ri   = 3844,
    3860             :     UDIVi64rr   = 3845,
    3861             :     UMAXi16ri   = 3846,
    3862             :     UMAXi16rr   = 3847,
    3863             :     UMAXi32ri   = 3848,
    3864             :     UMAXi32rr   = 3849,
    3865             :     UMAXi64ri   = 3850,
    3866             :     UMAXi64rr   = 3851,
    3867             :     UMINi16ri   = 3852,
    3868             :     UMINi16rr   = 3853,
    3869             :     UMINi32ri   = 3854,
    3870             :     UMINi32rr   = 3855,
    3871             :     UMINi64ri   = 3856,
    3872             :     UMINi64rr   = 3857,
    3873             :     UREMi16ri   = 3858,
    3874             :     UREMi16rr   = 3859,
    3875             :     UREMi32ri   = 3860,
    3876             :     UREMi32rr   = 3861,
    3877             :     UREMi64ri   = 3862,
    3878             :     UREMi64rr   = 3863,
    3879             :     V2F32toF64  = 3864,
    3880             :     V2I16toI32  = 3865,
    3881             :     V2I32toI64  = 3866,
    3882             :     V4I16toI64  = 3867,
    3883             :     VOTE_SYNC_ALLi      = 3868,
    3884             :     VOTE_SYNC_ALLr      = 3869,
    3885             :     VOTE_SYNC_ANYi      = 3870,
    3886             :     VOTE_SYNC_ANYr      = 3871,
    3887             :     VOTE_SYNC_BALLOTi   = 3872,
    3888             :     VOTE_SYNC_BALLOTr   = 3873,
    3889             :     VOTE_SYNC_UNIi      = 3874,
    3890             :     VOTE_SYNC_UNIr      = 3875,
    3891             :     XORb16ri    = 3876,
    3892             :     XORb16rr    = 3877,
    3893             :     XORb1ri     = 3878,
    3894             :     XORb1rr     = 3879,
    3895             :     XORb32ri    = 3880,
    3896             :     XORb32rr    = 3881,
    3897             :     XORb64ri    = 3882,
    3898             :     XORb64rr    = 3883,
    3899             :     anonymous_1974      = 3884,
    3900             :     anonymous_1975      = 3885,
    3901             :     anonymous_1976      = 3886,
    3902             :     anonymous_1977      = 3887,
    3903             :     anonymous_2095      = 3888,
    3904             :     anonymous_2096      = 3889,
    3905             :     anonymous_2097      = 3890,
    3906             :     anonymous_2098      = 3891,
    3907             :     anonymous_2099      = 3892,
    3908             :     anonymous_2100      = 3893,
    3909             :     anonymous_2101      = 3894,
    3910             :     anonymous_2102      = 3895,
    3911             :     anonymous_2103      = 3896,
    3912             :     anonymous_2104      = 3897,
    3913             :     anonymous_2105      = 3898,
    3914             :     anonymous_2106      = 3899,
    3915             :     anonymous_2109      = 3900,
    3916             :     anonymous_2110      = 3901,
    3917             :     anonymous_2111      = 3902,
    3918             :     anonymous_2112      = 3903,
    3919             :     anonymous_2113      = 3904,
    3920             :     anonymous_2114      = 3905,
    3921             :     anonymous_2115      = 3906,
    3922             :     anonymous_2116      = 3907,
    3923             :     anonymous_2117      = 3908,
    3924             :     anonymous_2118      = 3909,
    3925             :     anonymous_2119      = 3910,
    3926             :     anonymous_2120      = 3911,
    3927             :     anonymous_2121      = 3912,
    3928             :     anonymous_2122      = 3913,
    3929             :     anonymous_2123      = 3914,
    3930             :     anonymous_2124      = 3915,
    3931             :     anonymous_2125      = 3916,
    3932             :     anonymous_2126      = 3917,
    3933             :     anonymous_2127      = 3918,
    3934             :     anonymous_2128      = 3919,
    3935             :     anonymous_2129      = 3920,
    3936             :     anonymous_2130      = 3921,
    3937             :     anonymous_2131      = 3922,
    3938             :     anonymous_2132      = 3923,
    3939             :     anonymous_2133      = 3924,
    3940             :     anonymous_2134      = 3925,
    3941             :     anonymous_2135      = 3926,
    3942             :     anonymous_2136      = 3927,
    3943             :     anonymous_2137      = 3928,
    3944             :     anonymous_2138      = 3929,
    3945             :     anonymous_2139      = 3930,
    3946             :     anonymous_2140      = 3931,
    3947             :     anonymous_2141      = 3932,
    3948             :     anonymous_2142      = 3933,
    3949             :     anonymous_2143      = 3934,
    3950             :     anonymous_2144      = 3935,
    3951             :     anonymous_2145      = 3936,
    3952             :     anonymous_2146      = 3937,
    3953             :     anonymous_2147      = 3938,
    3954             :     anonymous_2148      = 3939,
    3955             :     anonymous_2149      = 3940,
    3956             :     anonymous_2150      = 3941,
    3957             :     anonymous_2151      = 3942,
    3958             :     anonymous_2152      = 3943,
    3959             :     anonymous_2153      = 3944,
    3960             :     anonymous_2154      = 3945,
    3961             :     anonymous_2155      = 3946,
    3962             :     anonymous_2156      = 3947,
    3963             :     anonymous_2157      = 3948,
    3964             :     anonymous_2158      = 3949,
    3965             :     anonymous_2159      = 3950,
    3966             :     anonymous_2160      = 3951,
    3967             :     anonymous_2161      = 3952,
    3968             :     anonymous_2162      = 3953,
    3969             :     anonymous_2163      = 3954,
    3970             :     anonymous_2164      = 3955,
    3971             :     anonymous_2165      = 3956,
    3972             :     anonymous_2166      = 3957,
    3973             :     anonymous_2167      = 3958,
    3974             :     anonymous_2168      = 3959,
    3975             :     anonymous_2169      = 3960,
    3976             :     anonymous_2170      = 3961,
    3977             :     anonymous_2171      = 3962,
    3978             :     anonymous_2172      = 3963,
    3979             :     anonymous_2173      = 3964,
    3980             :     anonymous_2174      = 3965,
    3981             :     anonymous_2175      = 3966,
    3982             :     anonymous_2176      = 3967,
    3983             :     anonymous_2177      = 3968,
    3984             :     anonymous_2178      = 3969,
    3985             :     anonymous_2179      = 3970,
    3986             :     anonymous_2180      = 3971,
    3987             :     anonymous_2181      = 3972,
    3988             :     anonymous_2182      = 3973,
    3989             :     anonymous_2183      = 3974,
    3990             :     anonymous_2184      = 3975,
    3991             :     anonymous_2185      = 3976,
    3992             :     anonymous_2186      = 3977,
    3993             :     anonymous_2187      = 3978,
    3994             :     anonymous_2188      = 3979,
    3995             :     anonymous_2189      = 3980,
    3996             :     anonymous_2190      = 3981,
    3997             :     anonymous_2191      = 3982,
    3998             :     anonymous_2192      = 3983,
    3999             :     anonymous_2193      = 3984,
    4000             :     anonymous_2194      = 3985,
    4001             :     anonymous_2195      = 3986,
    4002             :     anonymous_2196      = 3987,
    4003             :     anonymous_2197      = 3988,
    4004             :     anonymous_2198      = 3989,
    4005             :     anonymous_2199      = 3990,
    4006             :     anonymous_2200      = 3991,
    4007             :     anonymous_2201      = 3992,
    4008             :     anonymous_2202      = 3993,
    4009             :     anonymous_2203      = 3994,
    4010             :     anonymous_2204      = 3995,
    4011             :     anonymous_2205      = 3996,
    4012             :     anonymous_2206      = 3997,
    4013             :     anonymous_2207      = 3998,
    4014             :     anonymous_2208      = 3999,
    4015             :     anonymous_2209      = 4000,
    4016             :     anonymous_2210      = 4001,
    4017             :     anonymous_2211      = 4002,
    4018             :     anonymous_2212      = 4003,
    4019             :     anonymous_2213      = 4004,
    4020             :     anonymous_2214      = 4005,
    4021             :     anonymous_2215      = 4006,
    4022             :     anonymous_2216      = 4007,
    4023             :     anonymous_2217      = 4008,
    4024             :     anonymous_2218      = 4009,
    4025             :     anonymous_2219      = 4010,
    4026             :     anonymous_2220      = 4011,
    4027             :     anonymous_2221      = 4012,
    4028             :     anonymous_2222      = 4013,
    4029             :     anonymous_2223      = 4014,
    4030             :     anonymous_2224      = 4015,
    4031             :     anonymous_2225      = 4016,
    4032             :     anonymous_2226      = 4017,
    4033             :     anonymous_2227      = 4018,
    4034             :     anonymous_2228      = 4019,
    4035             :     anonymous_2229      = 4020,
    4036             :     anonymous_2230      = 4021,
    4037             :     anonymous_2231      = 4022,
    4038             :     anonymous_2232      = 4023,
    4039             :     anonymous_2233      = 4024,
    4040             :     anonymous_2234      = 4025,
    4041             :     anonymous_2235      = 4026,
    4042             :     anonymous_2236      = 4027,
    4043             :     anonymous_2237      = 4028,
    4044             :     anonymous_2238      = 4029,
    4045             :     anonymous_2239      = 4030,
    4046             :     anonymous_2240      = 4031,
    4047             :     anonymous_2241      = 4032,
    4048             :     anonymous_2242      = 4033,
    4049             :     anonymous_2243      = 4034,
    4050             :     anonymous_2244      = 4035,
    4051             :     anonymous_2245      = 4036,
    4052             :     anonymous_2246      = 4037,
    4053             :     anonymous_2247      = 4038,
    4054             :     anonymous_2248      = 4039,
    4055             :     anonymous_2249      = 4040,
    4056             :     anonymous_2250      = 4041,
    4057             :     anonymous_2251      = 4042,
    4058             :     anonymous_2252      = 4043,
    4059             :     anonymous_2253      = 4044,
    4060             :     anonymous_2254      = 4045,
    4061             :     anonymous_2255      = 4046,
    4062             :     anonymous_2256      = 4047,
    4063             :     anonymous_2257      = 4048,
    4064             :     anonymous_2258      = 4049,
    4065             :     anonymous_2259      = 4050,
    4066             :     anonymous_2260      = 4051,
    4067             :     anonymous_2261      = 4052,
    4068             :     anonymous_2262      = 4053,
    4069             :     anonymous_2263      = 4054,
    4070             :     anonymous_2264      = 4055,
    4071             :     anonymous_2265      = 4056,
    4072             :     anonymous_2266      = 4057,
    4073             :     anonymous_2267      = 4058,
    4074             :     anonymous_2268      = 4059,
    4075             :     anonymous_2269      = 4060,
    4076             :     anonymous_2270      = 4061,
    4077             :     anonymous_2271      = 4062,
    4078             :     anonymous_2272      = 4063,
    4079             :     anonymous_2273      = 4064,
    4080             :     anonymous_2274      = 4065,
    4081             :     anonymous_2275      = 4066,
    4082             :     anonymous_2276      = 4067,
    4083             :     anonymous_2277      = 4068,
    4084             :     anonymous_2278      = 4069,
    4085             :     anonymous_2279      = 4070,
    4086             :     anonymous_2280      = 4071,
    4087             :     anonymous_2281      = 4072,
    4088             :     anonymous_2282      = 4073,
    4089             :     anonymous_2283      = 4074,
    4090             :     anonymous_2284      = 4075,
    4091             :     anonymous_2285      = 4076,
    4092             :     anonymous_2286      = 4077,
    4093             :     anonymous_2287      = 4078,
    4094             :     anonymous_2288      = 4079,
    4095             :     anonymous_2289      = 4080,
    4096             :     anonymous_2290      = 4081,
    4097             :     anonymous_2291      = 4082,
    4098             :     anonymous_2292      = 4083,
    4099             :     anonymous_2293      = 4084,
    4100             :     anonymous_2294      = 4085,
    4101             :     anonymous_2295      = 4086,
    4102             :     anonymous_2296      = 4087,
    4103             :     anonymous_2297      = 4088,
    4104             :     anonymous_2298      = 4089,
    4105             :     anonymous_2299      = 4090,
    4106             :     anonymous_2300      = 4091,
    4107             :     anonymous_2301      = 4092,
    4108             :     anonymous_2302      = 4093,
    4109             :     anonymous_2303      = 4094,
    4110             :     anonymous_2304      = 4095,
    4111             :     anonymous_2305      = 4096,
    4112             :     anonymous_2306      = 4097,
    4113             :     anonymous_2307      = 4098,
    4114             :     anonymous_2308      = 4099,
    4115             :     anonymous_2309      = 4100,
    4116             :     anonymous_2310      = 4101,
    4117             :     anonymous_2311      = 4102,
    4118             :     anonymous_2312      = 4103,
    4119             :     anonymous_938       = 4104,
    4120             :     anonymous_939       = 4105,
    4121             :     anonymous_940       = 4106,
    4122             :     cvta_const_yes      = 4107,
    4123             :     cvta_const_yes_64   = 4108,
    4124             :     cvta_const_yes_6432 = 4109,
    4125             :     cvta_global_yes     = 4110,
    4126             :     cvta_global_yes_64  = 4111,
    4127             :     cvta_global_yes_6432        = 4112,
    4128             :     cvta_local_yes      = 4113,
    4129             :     cvta_local_yes_64   = 4114,
    4130             :     cvta_local_yes_6432 = 4115,
    4131             :     cvta_shared_yes     = 4116,
    4132             :     cvta_shared_yes_64  = 4117,
    4133             :     cvta_shared_yes_6432        = 4118,
    4134             :     cvta_to_const_yes   = 4119,
    4135             :     cvta_to_const_yes_3264      = 4120,
    4136             :     cvta_to_const_yes_64        = 4121,
    4137             :     cvta_to_global_yes  = 4122,
    4138             :     cvta_to_global_yes_3264     = 4123,
    4139             :     cvta_to_global_yes_64       = 4124,
    4140             :     cvta_to_local_yes   = 4125,
    4141             :     cvta_to_local_yes_3264      = 4126,
    4142             :     cvta_to_local_yes_64        = 4127,
    4143             :     cvta_to_shared_yes  = 4128,
    4144             :     cvta_to_shared_yes_3264     = 4129,
    4145             :     cvta_to_shared_yes_64       = 4130,
    4146             :     nvvm_move_double    = 4131,
    4147             :     nvvm_move_float     = 4132,
    4148             :     nvvm_move_i16       = 4133,
    4149             :     nvvm_move_i32       = 4134,
    4150             :     nvvm_move_i64       = 4135,
    4151             :     nvvm_move_ptr32     = 4136,
    4152             :     nvvm_move_ptr64     = 4137,
    4153             :     nvvm_ptr_gen_to_param       = 4138,
    4154             :     nvvm_ptr_gen_to_param_64    = 4139,
    4155             :     texsurf_handles     = 4140,
    4156             :     trapinst    = 4141,
    4157             :     INSTRUCTION_LIST_END = 4142
    4158             :   };
    4159             : 
    4160             : } // end NVPTX namespace
    4161             : } // end llvm namespace
    4162             : #endif // GET_INSTRINFO_ENUM
    4163             : 
    4164             : #ifdef GET_INSTRINFO_SCHED_ENUM
    4165             : #undef GET_INSTRINFO_SCHED_ENUM
    4166             : namespace llvm {
    4167             : 
    4168             : namespace NVPTX {
    4169             : namespace Sched {
    4170             :   enum {
    4171             :     NoInstrModel        = 0,
    4172             :     SCHED_LIST_END = 1
    4173             :   };
    4174             : } // end Sched namespace
    4175             : } // end NVPTX namespace
    4176             : } // end llvm namespace
    4177             : #endif // GET_INSTRINFO_SCHED_ENUM
    4178             : 
    4179             : #ifdef GET_INSTRINFO_MC_DESC
    4180             : #undef GET_INSTRINFO_MC_DESC
    4181             : namespace llvm {
    4182             : 
    4183             : 
    4184             : static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4185             : static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4186             : static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4187             : static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4188             : static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4189             : static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4190             : static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4191             : static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4192             : static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
    4193             : static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4194             : static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4195             : static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
    4196             : static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
    4197             : static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4198             : static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4199             : static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
    4200             : static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4201             : static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
    4202             : static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
    4203             : static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
    4204             : static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
    4205             : static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
    4206             : static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
    4207             : static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
    4208             : static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
    4209             : static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4210             : static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
    4211             : static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
    4212             : static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
    4213             : static const MCOperandInfo OperandInfo31[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4214             : static const MCOperandInfo OperandInfo32[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4215             : static const MCOperandInfo OperandInfo33[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4216             : static const MCOperandInfo OperandInfo34[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4217             : static const MCOperandInfo OperandInfo35[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4218             : static const MCOperandInfo OperandInfo36[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4219             : static const MCOperandInfo OperandInfo37[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4220             : static const MCOperandInfo OperandInfo38[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4221             : static const MCOperandInfo OperandInfo39[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4222             : static const MCOperandInfo OperandInfo40[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4223             : static const MCOperandInfo OperandInfo41[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4224             : static const MCOperandInfo OperandInfo42[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4225             : static const MCOperandInfo OperandInfo43[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4226             : static const MCOperandInfo OperandInfo44[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4227             : static const MCOperandInfo OperandInfo45[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4228             : static const MCOperandInfo OperandInfo46[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4229             : static const MCOperandInfo OperandInfo47[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4230             : static const MCOperandInfo OperandInfo48[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4231             : static const MCOperandInfo OperandInfo49[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4232             : static const MCOperandInfo OperandInfo50[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4233             : static const MCOperandInfo OperandInfo51[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4234             : static const MCOperandInfo OperandInfo52[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4235             : static const MCOperandInfo OperandInfo53[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4236             : static const MCOperandInfo OperandInfo54[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4237             : static const MCOperandInfo OperandInfo55[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4238             : static const MCOperandInfo OperandInfo56[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4239             : static const MCOperandInfo OperandInfo57[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4240             : static const MCOperandInfo OperandInfo58[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4241             : static const MCOperandInfo OperandInfo59[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4242             : static const MCOperandInfo OperandInfo60[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4243             : static const MCOperandInfo OperandInfo61[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4244             : static const MCOperandInfo OperandInfo62[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4245             : static const MCOperandInfo OperandInfo63[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4246             : static const MCOperandInfo OperandInfo64[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4247             : static const MCOperandInfo OperandInfo65[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4248             : static const MCOperandInfo OperandInfo66[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4249             : static const MCOperandInfo OperandInfo67[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4250             : static const MCOperandInfo OperandInfo68[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4251             : static const MCOperandInfo OperandInfo69[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4252             : static const MCOperandInfo OperandInfo70[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4253             : static const MCOperandInfo OperandInfo71[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4254             : static const MCOperandInfo OperandInfo72[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4255             : static const MCOperandInfo OperandInfo73[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4256             : static const MCOperandInfo OperandInfo74[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4257             : static const MCOperandInfo OperandInfo75[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4258             : static const MCOperandInfo OperandInfo76[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4259             : static const MCOperandInfo OperandInfo77[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4260             : static const MCOperandInfo OperandInfo78[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4261             : static const MCOperandInfo OperandInfo79[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4262             : static const MCOperandInfo OperandInfo80[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4263             : static const MCOperandInfo OperandInfo81[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4264             : static const MCOperandInfo OperandInfo82[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4265             : static const MCOperandInfo OperandInfo83[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4266             : static const MCOperandInfo OperandInfo84[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4267             : static const MCOperandInfo OperandInfo85[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4268             : static const MCOperandInfo OperandInfo86[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4269             : static const MCOperandInfo OperandInfo87[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4270             : static const MCOperandInfo OperandInfo88[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4271             : static const MCOperandInfo OperandInfo89[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4272             : static const MCOperandInfo OperandInfo90[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4273             : static const MCOperandInfo OperandInfo91[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4274             : static const MCOperandInfo OperandInfo92[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4275             : static const MCOperandInfo OperandInfo93[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4276             : static const MCOperandInfo OperandInfo94[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4277             : static const MCOperandInfo OperandInfo95[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4278             : static const MCOperandInfo OperandInfo96[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4279             : static const MCOperandInfo OperandInfo97[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4280             : static const MCOperandInfo OperandInfo98[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4281             : static const MCOperandInfo OperandInfo99[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4282             : static const MCOperandInfo OperandInfo100[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4283             : static const MCOperandInfo OperandInfo101[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4284             : static const MCOperandInfo OperandInfo102[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4285             : static const MCOperandInfo OperandInfo103[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4286             : static const MCOperandInfo OperandInfo104[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4287             : static const MCOperandInfo OperandInfo105[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4288             : static const MCOperandInfo OperandInfo106[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4289             : static const MCOperandInfo OperandInfo107[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4290             : static const MCOperandInfo OperandInfo108[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4291             : static const MCOperandInfo OperandInfo109[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4292             : static const MCOperandInfo OperandInfo110[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4293             : static const MCOperandInfo OperandInfo111[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4294             : static const MCOperandInfo OperandInfo112[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4295             : static const MCOperandInfo OperandInfo113[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4296             : static const MCOperandInfo OperandInfo114[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4297             : static const MCOperandInfo OperandInfo115[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4298             : static const MCOperandInfo OperandInfo116[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4299             : static const MCOperandInfo OperandInfo117[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4300             : static const MCOperandInfo OperandInfo118[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4301             : static const MCOperandInfo OperandInfo119[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4302             : static const MCOperandInfo OperandInfo120[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4303             : static const MCOperandInfo OperandInfo121[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4304             : static const MCOperandInfo OperandInfo122[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4305             : static const MCOperandInfo OperandInfo123[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4306             : static const MCOperandInfo OperandInfo124[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4307             : static const MCOperandInfo OperandInfo125[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4308             : static const MCOperandInfo OperandInfo126[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4309             : static const MCOperandInfo OperandInfo127[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4310             : static const MCOperandInfo OperandInfo128[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4311             : static const MCOperandInfo OperandInfo129[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4312             : static const MCOperandInfo OperandInfo130[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4313             : static const MCOperandInfo OperandInfo131[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4314             : static const MCOperandInfo OperandInfo132[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4315             : static const MCOperandInfo OperandInfo133[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4316             : static const MCOperandInfo OperandInfo134[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4317             : static const MCOperandInfo OperandInfo135[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4318             : static const MCOperandInfo OperandInfo136[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4319             : static const MCOperandInfo OperandInfo137[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4320             : static const MCOperandInfo OperandInfo138[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4321             : static const MCOperandInfo OperandInfo139[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4322             : static const MCOperandInfo OperandInfo140[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4323             : static const MCOperandInfo OperandInfo141[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4324             : static const MCOperandInfo OperandInfo142[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4325             : static const MCOperandInfo OperandInfo143[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4326             : static const MCOperandInfo OperandInfo144[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4327             : static const MCOperandInfo OperandInfo145[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4328             : static const MCOperandInfo OperandInfo146[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4329             : static const MCOperandInfo OperandInfo147[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4330             : static const MCOperandInfo OperandInfo148[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4331             : static const MCOperandInfo OperandInfo149[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4332             : static const MCOperandInfo OperandInfo150[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4333             : static const MCOperandInfo OperandInfo151[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4334             : static const MCOperandInfo OperandInfo152[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4335             : static const MCOperandInfo OperandInfo153[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4336             : static const MCOperandInfo OperandInfo154[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4337             : static const MCOperandInfo OperandInfo155[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4338             : static const MCOperandInfo OperandInfo156[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4339             : static const MCOperandInfo OperandInfo157[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4340             : static const MCOperandInfo OperandInfo158[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4341             : static const MCOperandInfo OperandInfo159[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4342             : static const MCOperandInfo OperandInfo160[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4343             : static const MCOperandInfo OperandInfo161[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4344             : static const MCOperandInfo OperandInfo162[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4345             : static const MCOperandInfo OperandInfo163[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4346             : static const MCOperandInfo OperandInfo164[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4347             : static const MCOperandInfo OperandInfo165[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4348             : static const MCOperandInfo OperandInfo166[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4349             : static const MCOperandInfo OperandInfo167[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4350             : static const MCOperandInfo OperandInfo168[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4351             : static const MCOperandInfo OperandInfo169[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4352             : static const MCOperandInfo OperandInfo170[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4353             : static const MCOperandInfo OperandInfo171[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4354             : static const MCOperandInfo OperandInfo172[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4355             : static const MCOperandInfo OperandInfo173[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4356             : static const MCOperandInfo OperandInfo174[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4357             : static const MCOperandInfo OperandInfo175[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4358             : static const MCOperandInfo OperandInfo176[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4359             : static const MCOperandInfo OperandInfo177[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4360             : static const MCOperandInfo OperandInfo178[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4361             : static const MCOperandInfo OperandInfo179[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4362             : static const MCOperandInfo OperandInfo180[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4363             : static const MCOperandInfo OperandInfo181[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4364             : static const MCOperandInfo OperandInfo182[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4365             : static const MCOperandInfo OperandInfo183[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4366             : static const MCOperandInfo OperandInfo184[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4367             : static const MCOperandInfo OperandInfo185[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4368             : static const MCOperandInfo OperandInfo186[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4369             : static const MCOperandInfo OperandInfo187[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4370             : static const MCOperandInfo OperandInfo188[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4371             : static const MCOperandInfo OperandInfo189[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4372             : static const MCOperandInfo OperandInfo190[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4373             : static const MCOperandInfo OperandInfo191[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4374             : static const MCOperandInfo OperandInfo192[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4375             : static const MCOperandInfo OperandInfo193[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4376             : static const MCOperandInfo OperandInfo194[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4377             : static const MCOperandInfo OperandInfo195[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4378             : static const MCOperandInfo OperandInfo196[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4379             : static const MCOperandInfo OperandInfo197[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4380             : static const MCOperandInfo OperandInfo198[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4381             : static const MCOperandInfo OperandInfo199[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4382             : static const MCOperandInfo OperandInfo200[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4383             : static const MCOperandInfo OperandInfo201[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4384             : static const MCOperandInfo OperandInfo202[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4385             : static const MCOperandInfo OperandInfo203[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4386             : static const MCOperandInfo OperandInfo204[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4387             : static const MCOperandInfo OperandInfo205[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4388             : static const MCOperandInfo OperandInfo206[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4389             : static const MCOperandInfo OperandInfo207[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4390             : static const MCOperandInfo OperandInfo208[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4391             : static const MCOperandInfo OperandInfo209[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4392             : static const MCOperandInfo OperandInfo210[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4393             : static const MCOperandInfo OperandInfo211[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4394             : static const MCOperandInfo OperandInfo212[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4395             : static const MCOperandInfo OperandInfo213[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4396             : static const MCOperandInfo OperandInfo214[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4397             : static const MCOperandInfo OperandInfo215[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4398             : static const MCOperandInfo OperandInfo216[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4399             : static const MCOperandInfo OperandInfo217[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4400             : static const MCOperandInfo OperandInfo218[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4401             : static const MCOperandInfo OperandInfo219[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4402             : static const MCOperandInfo OperandInfo220[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4403             : static const MCOperandInfo OperandInfo221[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4404             : static const MCOperandInfo OperandInfo222[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4405             : static const MCOperandInfo OperandInfo223[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4406             : static const MCOperandInfo OperandInfo224[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4407             : static const MCOperandInfo OperandInfo225[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4408             : static const MCOperandInfo OperandInfo226[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4409             : static const MCOperandInfo OperandInfo227[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4410             : static const MCOperandInfo OperandInfo228[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4411             : static const MCOperandInfo OperandInfo229[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4412             : static const MCOperandInfo OperandInfo230[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4413             : static const MCOperandInfo OperandInfo231[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4414             : static const MCOperandInfo OperandInfo232[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4415             : static const MCOperandInfo OperandInfo233[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4416             : static const MCOperandInfo OperandInfo234[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4417             : static const MCOperandInfo OperandInfo235[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4418             : static const MCOperandInfo OperandInfo236[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4419             : static const MCOperandInfo OperandInfo237[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4420             : static const MCOperandInfo OperandInfo238[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4421             : static const MCOperandInfo OperandInfo239[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4422             : static const MCOperandInfo OperandInfo240[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4423             : static const MCOperandInfo OperandInfo241[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4424             : static const MCOperandInfo OperandInfo242[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4425             : static const MCOperandInfo OperandInfo243[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4426             : static const MCOperandInfo OperandInfo244[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4427             : static const MCOperandInfo OperandInfo245[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4428             : static const MCOperandInfo OperandInfo246[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4429             : static const MCOperandInfo OperandInfo247[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4430             : static const MCOperandInfo OperandInfo248[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4431             : static const MCOperandInfo OperandInfo249[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4432             : static const MCOperandInfo OperandInfo250[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4433             : static const MCOperandInfo OperandInfo251[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4434             : static const MCOperandInfo OperandInfo252[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4435             : static const MCOperandInfo OperandInfo253[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4436             : static const MCOperandInfo OperandInfo254[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4437             : static const MCOperandInfo OperandInfo255[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4438             : static const MCOperandInfo OperandInfo256[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4439             : static const MCOperandInfo OperandInfo257[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4440             : static const MCOperandInfo OperandInfo258[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4441             : static const MCOperandInfo OperandInfo259[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4442             : static const MCOperandInfo OperandInfo260[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4443             : static const MCOperandInfo OperandInfo261[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4444             : static const MCOperandInfo OperandInfo262[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4445             : static const MCOperandInfo OperandInfo263[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4446             : static const MCOperandInfo OperandInfo264[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4447             : static const MCOperandInfo OperandInfo265[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4448             : static const MCOperandInfo OperandInfo266[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4449             : static const MCOperandInfo OperandInfo267[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4450             : static const MCOperandInfo OperandInfo268[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4451             : static const MCOperandInfo OperandInfo269[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4452             : static const MCOperandInfo OperandInfo270[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4453             : static const MCOperandInfo OperandInfo271[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4454             : static const MCOperandInfo OperandInfo272[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4455             : static const MCOperandInfo OperandInfo273[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4456             : static const MCOperandInfo OperandInfo274[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4457             : static const MCOperandInfo OperandInfo275[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4458             : static const MCOperandInfo OperandInfo276[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4459             : static const MCOperandInfo OperandInfo277[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4460             : static const MCOperandInfo OperandInfo278[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4461             : static const MCOperandInfo OperandInfo279[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4462             : static const MCOperandInfo OperandInfo280[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4463             : static const MCOperandInfo OperandInfo281[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4464             : static const MCOperandInfo OperandInfo282[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4465             : static const MCOperandInfo OperandInfo283[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4466             : static const MCOperandInfo OperandInfo284[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4467             : static const MCOperandInfo OperandInfo285[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4468             : static const MCOperandInfo OperandInfo286[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4469             : static const MCOperandInfo OperandInfo287[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4470             : static const MCOperandInfo OperandInfo288[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4471             : static const MCOperandInfo OperandInfo289[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4472             : static const MCOperandInfo OperandInfo290[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4473             : static const MCOperandInfo OperandInfo291[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4474             : static const MCOperandInfo OperandInfo292[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4475             : static const MCOperandInfo OperandInfo293[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4476             : static const MCOperandInfo OperandInfo294[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4477             : static const MCOperandInfo OperandInfo295[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4478             : static const MCOperandInfo OperandInfo296[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4479             : static const MCOperandInfo OperandInfo297[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4480             : static const MCOperandInfo OperandInfo298[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4481             : static const MCOperandInfo OperandInfo299[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4482             : static const MCOperandInfo OperandInfo300[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4483             : static const MCOperandInfo OperandInfo301[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4484             : static const MCOperandInfo OperandInfo302[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4485             : static const MCOperandInfo OperandInfo303[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4486             : static const MCOperandInfo OperandInfo304[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4487             : static const MCOperandInfo OperandInfo305[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4488             : static const MCOperandInfo OperandInfo306[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4489             : static const MCOperandInfo OperandInfo307[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4490             : static const MCOperandInfo OperandInfo308[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4491             : static const MCOperandInfo OperandInfo309[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4492             : static const MCOperandInfo OperandInfo310[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4493             : static const MCOperandInfo OperandInfo311[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4494             : static const MCOperandInfo OperandInfo312[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4495             : static const MCOperandInfo OperandInfo313[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4496             : static const MCOperandInfo OperandInfo314[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4497             : static const MCOperandInfo OperandInfo315[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4498             : static const MCOperandInfo OperandInfo316[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4499             : static const MCOperandInfo OperandInfo317[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4500             : static const MCOperandInfo OperandInfo318[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4501             : static const MCOperandInfo OperandInfo319[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4502             : static const MCOperandInfo OperandInfo320[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4503             : static const MCOperandInfo OperandInfo321[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4504             : static const MCOperandInfo OperandInfo322[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4505             : static const MCOperandInfo OperandInfo323[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4506             : static const MCOperandInfo OperandInfo324[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4507             : static const MCOperandInfo OperandInfo325[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4508             : static const MCOperandInfo OperandInfo326[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4509             : static const MCOperandInfo OperandInfo327[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4510             : static const MCOperandInfo OperandInfo328[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4511             : static const MCOperandInfo OperandInfo329[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4512             : static const MCOperandInfo OperandInfo330[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4513             : static const MCOperandInfo OperandInfo331[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4514             : static const MCOperandInfo OperandInfo332[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4515             : static const MCOperandInfo OperandInfo333[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4516             : static const MCOperandInfo OperandInfo334[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4517             : static const MCOperandInfo OperandInfo335[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4518             : static const MCOperandInfo OperandInfo336[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4519             : static const MCOperandInfo OperandInfo337[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4520             : static const MCOperandInfo OperandInfo338[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4521             : static const MCOperandInfo OperandInfo339[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4522             : static const MCOperandInfo OperandInfo340[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4523             : static const MCOperandInfo OperandInfo341[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4524             : static const MCOperandInfo OperandInfo342[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4525             : static const MCOperandInfo OperandInfo343[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4526             : static const MCOperandInfo OperandInfo344[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4527             : static const MCOperandInfo OperandInfo345[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4528             : static const MCOperandInfo OperandInfo346[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4529             : static const MCOperandInfo OperandInfo347[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4530             : static const MCOperandInfo OperandInfo348[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4531             : static const MCOperandInfo OperandInfo349[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4532             : static const MCOperandInfo OperandInfo350[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4533             : static const MCOperandInfo OperandInfo351[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4534             : static const MCOperandInfo OperandInfo352[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4535             : static const MCOperandInfo OperandInfo353[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4536             : static const MCOperandInfo OperandInfo354[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4537             : static const MCOperandInfo OperandInfo355[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4538             : static const MCOperandInfo OperandInfo356[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4539             : static const MCOperandInfo OperandInfo357[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4540             : static const MCOperandInfo OperandInfo358[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4541             : static const MCOperandInfo OperandInfo359[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4542             : static const MCOperandInfo OperandInfo360[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4543             : static const MCOperandInfo OperandInfo361[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4544             : static const MCOperandInfo OperandInfo362[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4545             : static const MCOperandInfo OperandInfo363[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4546             : static const MCOperandInfo OperandInfo364[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4547             : static const MCOperandInfo OperandInfo365[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4548             : static const MCOperandInfo OperandInfo366[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4549             : static const MCOperandInfo OperandInfo367[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4550             : static const MCOperandInfo OperandInfo368[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4551             : static const MCOperandInfo OperandInfo369[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4552             : static const MCOperandInfo OperandInfo370[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4553             : static const MCOperandInfo OperandInfo371[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4554             : static const MCOperandInfo OperandInfo372[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4555             : static const MCOperandInfo OperandInfo373[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4556             : static const MCOperandInfo OperandInfo374[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4557             : static const MCOperandInfo OperandInfo375[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4558             : static const MCOperandInfo OperandInfo376[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4559             : static const MCOperandInfo OperandInfo377[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4560             : static const MCOperandInfo OperandInfo378[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4561             : static const MCOperandInfo OperandInfo379[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4562             : static const MCOperandInfo OperandInfo380[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4563             : static const MCOperandInfo OperandInfo381[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4564             : static const MCOperandInfo OperandInfo382[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4565             : static const MCOperandInfo OperandInfo383[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4566             : static const MCOperandInfo OperandInfo384[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4567             : static const MCOperandInfo OperandInfo385[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4568             : static const MCOperandInfo OperandInfo386[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4569             : static const MCOperandInfo OperandInfo387[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4570             : static const MCOperandInfo OperandInfo388[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4571             : static const MCOperandInfo OperandInfo389[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4572             : static const MCOperandInfo OperandInfo390[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4573             : static const MCOperandInfo OperandInfo391[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4574             : static const MCOperandInfo OperandInfo392[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4575             : static const MCOperandInfo OperandInfo393[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4576             : static const MCOperandInfo OperandInfo394[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4577             : static const MCOperandInfo OperandInfo395[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4578             : static const MCOperandInfo OperandInfo396[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4579             : static const MCOperandInfo OperandInfo397[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4580             : static const MCOperandInfo OperandInfo398[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4581             : static const MCOperandInfo OperandInfo399[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4582             : static const MCOperandInfo OperandInfo400[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4583             : static const MCOperandInfo OperandInfo401[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4584             : static const MCOperandInfo OperandInfo402[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4585             : static const MCOperandInfo OperandInfo403[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4586             : static const MCOperandInfo OperandInfo404[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4587             : static const MCOperandInfo OperandInfo405[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4588             : static const MCOperandInfo OperandInfo406[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4589             : static const MCOperandInfo OperandInfo407[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4590             : static const MCOperandInfo OperandInfo408[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4591             : static const MCOperandInfo OperandInfo409[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4592             : static const MCOperandInfo OperandInfo410[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4593             : static const MCOperandInfo OperandInfo411[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4594             : static const MCOperandInfo OperandInfo412[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4595             : static const MCOperandInfo OperandInfo413[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4596             : static const MCOperandInfo OperandInfo414[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4597             : static const MCOperandInfo OperandInfo415[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4598             : static const MCOperandInfo OperandInfo416[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4599             : static const MCOperandInfo OperandInfo417[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4600             : static const MCOperandInfo OperandInfo418[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4601             : static const MCOperandInfo OperandInfo419[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4602             : static const MCOperandInfo OperandInfo420[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4603             : static const MCOperandInfo OperandInfo421[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4604             : static const MCOperandInfo OperandInfo422[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4605             : static const MCOperandInfo OperandInfo423[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4606             : static const MCOperandInfo OperandInfo424[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4607             : static const MCOperandInfo OperandInfo425[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4608             : static const MCOperandInfo OperandInfo426[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4609             : static const MCOperandInfo OperandInfo427[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4610             : static const MCOperandInfo OperandInfo428[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4611             : static const MCOperandInfo OperandInfo429[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4612             : static const MCOperandInfo OperandInfo430[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4613             : static const MCOperandInfo OperandInfo431[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4614             : static const MCOperandInfo OperandInfo432[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4615             : static const MCOperandInfo OperandInfo433[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4616             : static const MCOperandInfo OperandInfo434[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4617             : static const MCOperandInfo OperandInfo435[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4618             : static const MCOperandInfo OperandInfo436[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4619             : static const MCOperandInfo OperandInfo437[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4620             : static const MCOperandInfo OperandInfo438[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4621             : static const MCOperandInfo OperandInfo439[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4622             : static const MCOperandInfo OperandInfo440[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4623             : static const MCOperandInfo OperandInfo441[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4624             : static const MCOperandInfo OperandInfo442[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4625             : static const MCOperandInfo OperandInfo443[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4626             : static const MCOperandInfo OperandInfo444[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4627             : static const MCOperandInfo OperandInfo445[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4628             : static const MCOperandInfo OperandInfo446[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4629             : static const MCOperandInfo OperandInfo447[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4630             : static const MCOperandInfo OperandInfo448[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4631             : static const MCOperandInfo OperandInfo449[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4632             : static const MCOperandInfo OperandInfo450[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4633             : static const MCOperandInfo OperandInfo451[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4634             : static const MCOperandInfo OperandInfo452[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4635             : static const MCOperandInfo OperandInfo453[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4636             : static const MCOperandInfo OperandInfo454[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4637             : static const MCOperandInfo OperandInfo455[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4638             : static const MCOperandInfo OperandInfo456[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4639             : static const MCOperandInfo OperandInfo457[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4640             : static const MCOperandInfo OperandInfo458[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4641             : static const MCOperandInfo OperandInfo459[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4642             : static const MCOperandInfo OperandInfo460[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4643             : static const MCOperandInfo OperandInfo461[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4644             : static const MCOperandInfo OperandInfo462[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::SpecialRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4645             : static const MCOperandInfo OperandInfo463[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4646             : static const MCOperandInfo OperandInfo464[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4647             : static const MCOperandInfo OperandInfo465[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4648             : static const MCOperandInfo OperandInfo466[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4649             : static const MCOperandInfo OperandInfo467[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4650             : static const MCOperandInfo OperandInfo468[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4651             : static const MCOperandInfo OperandInfo469[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4652             : static const MCOperandInfo OperandInfo470[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4653             : static const MCOperandInfo OperandInfo471[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4654             : static const MCOperandInfo OperandInfo472[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4655             : static const MCOperandInfo OperandInfo473[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4656             : static const MCOperandInfo OperandInfo474[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4657             : static const MCOperandInfo OperandInfo475[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4658             : static const MCOperandInfo OperandInfo476[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4659             : static const MCOperandInfo OperandInfo477[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4660             : static const MCOperandInfo OperandInfo478[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4661             : static const MCOperandInfo OperandInfo479[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4662             : static const MCOperandInfo OperandInfo480[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4663             : static const MCOperandInfo OperandInfo481[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4664             : static const MCOperandInfo OperandInfo482[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4665             : static const MCOperandInfo OperandInfo483[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4666             : static const MCOperandInfo OperandInfo484[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4667             : static const MCOperandInfo OperandInfo485[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4668             : static const MCOperandInfo OperandInfo486[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4669             : static const MCOperandInfo OperandInfo487[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4670             : static const MCOperandInfo OperandInfo488[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4671             : static const MCOperandInfo OperandInfo489[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4672             : static const MCOperandInfo OperandInfo490[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4673             : static const MCOperandInfo OperandInfo491[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4674             : static const MCOperandInfo OperandInfo492[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4675             : static const MCOperandInfo OperandInfo493[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4676             : static const MCOperandInfo OperandInfo494[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4677             : static const MCOperandInfo OperandInfo495[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4678             : static const MCOperandInfo OperandInfo496[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4679             : static const MCOperandInfo OperandInfo497[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4680             : static const MCOperandInfo OperandInfo498[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4681             : static const MCOperandInfo OperandInfo499[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4682             : static const MCOperandInfo OperandInfo500[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4683             : static const MCOperandInfo OperandInfo501[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4684             : static const MCOperandInfo OperandInfo502[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4685             : static const MCOperandInfo OperandInfo503[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4686             : static const MCOperandInfo OperandInfo504[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4687             : static const MCOperandInfo OperandInfo505[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4688             : static const MCOperandInfo OperandInfo506[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4689             : static const MCOperandInfo OperandInfo507[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4690             : static const MCOperandInfo OperandInfo508[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4691             : static const MCOperandInfo OperandInfo509[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4692             : static const MCOperandInfo OperandInfo510[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4693             : static const MCOperandInfo OperandInfo511[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4694             : static const MCOperandInfo OperandInfo512[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4695             : static const MCOperandInfo OperandInfo513[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4696             : static const MCOperandInfo OperandInfo514[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4697             : static const MCOperandInfo OperandInfo515[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4698             : static const MCOperandInfo OperandInfo516[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4699             : static const MCOperandInfo OperandInfo517[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4700             : static const MCOperandInfo OperandInfo518[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4701             : static const MCOperandInfo OperandInfo519[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4702             : static const MCOperandInfo OperandInfo520[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4703             : static const MCOperandInfo OperandInfo521[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4704             : static const MCOperandInfo OperandInfo522[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4705             : static const MCOperandInfo OperandInfo523[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4706             : static const MCOperandInfo OperandInfo524[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4707             : static const MCOperandInfo OperandInfo525[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
    4708             : static const MCOperandInfo OperandInfo526[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4709             : static const MCOperandInfo OperandInfo527[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4710             : static const MCOperandInfo OperandInfo528[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4711             : static const MCOperandInfo OperandInfo529[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4712             : static const MCOperandInfo OperandInfo530[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4713             : static const MCOperandInfo OperandInfo531[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4714             : static const MCOperandInfo OperandInfo532[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4715             : static const MCOperandInfo OperandInfo533[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4716             : static const MCOperandInfo OperandInfo534[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4717             : static const MCOperandInfo OperandInfo535[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4718             : static const MCOperandInfo OperandInfo536[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4719             : static const MCOperandInfo OperandInfo537[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4720             : static const MCOperandInfo OperandInfo538[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4721             : static const MCOperandInfo OperandInfo539[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4722             : static const MCOperandInfo OperandInfo540[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4723             : static const MCOperandInfo OperandInfo541[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4724             : static const MCOperandInfo OperandInfo542[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4725             : static const MCOperandInfo OperandInfo543[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4726             : static const MCOperandInfo OperandInfo544[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4727             : static const MCOperandInfo OperandInfo545[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4728             : static const MCOperandInfo OperandInfo546[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4729             : static const MCOperandInfo OperandInfo547[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4730             : static const MCOperandInfo OperandInfo548[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4731             : static const MCOperandInfo OperandInfo549[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4732             : static const MCOperandInfo OperandInfo550[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4733             : static const MCOperandInfo OperandInfo551[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4734             : static const MCOperandInfo OperandInfo552[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4735             : static const MCOperandInfo OperandInfo553[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4736             : static const MCOperandInfo OperandInfo554[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4737             : static const MCOperandInfo OperandInfo555[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4738             : static const MCOperandInfo OperandInfo556[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4739             : static const MCOperandInfo OperandInfo557[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4740             : static const MCOperandInfo OperandInfo558[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4741             : static const MCOperandInfo OperandInfo559[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4742             : static const MCOperandInfo OperandInfo560[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4743             : static const MCOperandInfo OperandInfo561[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4744             : static const MCOperandInfo OperandInfo562[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4745             : static const MCOperandInfo OperandInfo563[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4746             : static const MCOperandInfo OperandInfo564[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4747             : static const MCOperandInfo OperandInfo565[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4748             : static const MCOperandInfo OperandInfo566[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4749             : static const MCOperandInfo OperandInfo567[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4750             : static const MCOperandInfo OperandInfo568[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4751             : static const MCOperandInfo OperandInfo569[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4752             : static const MCOperandInfo OperandInfo570[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4753             : static const MCOperandInfo OperandInfo571[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4754             : static const MCOperandInfo OperandInfo572[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4755             : static const MCOperandInfo OperandInfo573[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4756             : static const MCOperandInfo OperandInfo574[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4757             : static const MCOperandInfo OperandInfo575[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4758             : static const MCOperandInfo OperandInfo576[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
    4759             : static const MCOperandInfo OperandInfo577[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4760             : static const MCOperandInfo OperandInfo578[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4761             : static const MCOperandInfo OperandInfo579[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4762             : static const MCOperandInfo OperandInfo580[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4763             : static const MCOperandInfo OperandInfo581[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4764             : static const MCOperandInfo OperandInfo582[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4765             : static const MCOperandInfo OperandInfo583[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4766             : static const MCOperandInfo OperandInfo584[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4767             : static const MCOperandInfo OperandInfo585[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4768             : static const MCOperandInfo OperandInfo586[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4769             : static const MCOperandInfo OperandInfo587[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4770             : static const MCOperandInfo OperandInfo588[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4771             : static const MCOperandInfo OperandInfo589[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4772             : static const MCOperandInfo OperandInfo590[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4773             : static const MCOperandInfo OperandInfo591[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4774             : static const MCOperandInfo OperandInfo592[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4775             : static const MCOperandInfo OperandInfo593[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4776             : static const MCOperandInfo OperandInfo594[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4777             : static const MCOperandInfo OperandInfo595[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4778             : static const MCOperandInfo OperandInfo596[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4779             : static const MCOperandInfo OperandInfo597[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4780             : static const MCOperandInfo OperandInfo598[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4781             : static const MCOperandInfo OperandInfo599[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4782             : static const MCOperandInfo OperandInfo600[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4783             : static const MCOperandInfo OperandInfo601[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4784             : static const MCOperandInfo OperandInfo602[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4785             : static const MCOperandInfo OperandInfo603[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4786             : static const MCOperandInfo OperandInfo604[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4787             : static const MCOperandInfo OperandInfo605[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4788             : static const MCOperandInfo OperandInfo606[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4789             : static const MCOperandInfo OperandInfo607[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4790             : static const MCOperandInfo OperandInfo608[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4791             : static const MCOperandInfo OperandInfo609[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4792             : static const MCOperandInfo OperandInfo610[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4793             : static const MCOperandInfo OperandInfo611[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4794             : static const MCOperandInfo OperandInfo612[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4795             : static const MCOperandInfo OperandInfo613[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4796             : static const MCOperandInfo OperandInfo614[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4797             : static const MCOperandInfo OperandInfo615[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4798             : static const MCOperandInfo OperandInfo616[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4799             : static const MCOperandInfo OperandInfo617[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4800             : static const MCOperandInfo OperandInfo618[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4801             : static const MCOperandInfo OperandInfo619[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4802             : static const MCOperandInfo OperandInfo620[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4803             : static const MCOperandInfo OperandInfo621[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4804             : static const MCOperandInfo OperandInfo622[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4805             : static const MCOperandInfo OperandInfo623[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4806             : static const MCOperandInfo OperandInfo624[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4807             : static const MCOperandInfo OperandInfo625[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4808             : static const MCOperandInfo OperandInfo626[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4809             : static const MCOperandInfo OperandInfo627[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4810             : static const MCOperandInfo OperandInfo628[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4811             : static const MCOperandInfo OperandInfo629[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4812             : static const MCOperandInfo OperandInfo630[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4813             : static const MCOperandInfo OperandInfo631[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4814             : static const MCOperandInfo OperandInfo632[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4815             : static const MCOperandInfo OperandInfo633[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4816             : static const MCOperandInfo OperandInfo634[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4817             : static const MCOperandInfo OperandInfo635[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4818             : static const MCOperandInfo OperandInfo636[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
    4819             : 
    4820             : extern const MCInstrDesc NVPTXInsts[] = {
    4821             :   { 0,  1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #0 = PHI
    4822             :   { 1,  0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
    4823             :   { 2,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #2 = CFI_INSTRUCTION
    4824             :   { 3,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #3 = EH_LABEL
    4825             :   { 4,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #4 = GC_LABEL
    4826             :   { 5,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #5 = ANNOTATION_LABEL
    4827             :   { 6,  0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #6 = KILL
    4828             :   { 7,  3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #7 = EXTRACT_SUBREG
    4829             :   { 8,  4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #8 = INSERT_SUBREG
    4830             :   { 9,  1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #9 = IMPLICIT_DEF
    4831             :   { 10, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #10 = SUBREG_TO_REG
    4832             :   { 11, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #11 = COPY_TO_REGCLASS
    4833             :   { 12, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #12 = DBG_VALUE
    4834             :   { 13, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #13 = DBG_LABEL
    4835             :   { 14, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #14 = REG_SEQUENCE
    4836             :   { 15, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #15 = COPY
    4837             :   { 16, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #16 = BUNDLE
    4838             :   { 17, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #17 = LIFETIME_START
    4839             :   { 18, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #18 = LIFETIME_END
    4840             :   { 19, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #19 = STACKMAP
    4841             :   { 20, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #20 = FENTRY_CALL
    4842             :   { 21, 6,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #21 = PATCHPOINT
    4843             :   { 22, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #22 = LOAD_STACK_GUARD
    4844             :   { 23, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #23 = STATEPOINT
    4845             :   { 24, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #24 = LOCAL_ESCAPE
    4846             :   { 25, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #25 = FAULTING_OP
    4847             :   { 26, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #26 = PATCHABLE_OP
    4848             :   { 27, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #27 = PATCHABLE_FUNCTION_ENTER
    4849             :   { 28, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #28 = PATCHABLE_RET
    4850             :   { 29, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #29 = PATCHABLE_FUNCTION_EXIT
    4851             :   { 30, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #30 = PATCHABLE_TAIL_CALL
    4852             :   { 31, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #31 = PATCHABLE_EVENT_CALL
    4853             :   { 32, 3,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #32 = PATCHABLE_TYPED_EVENT_CALL
    4854             :   { 33, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #33 = ICALL_BRANCH_FUNNEL
    4855             :   { 34, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #34 = G_ADD
    4856             :   { 35, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #35 = G_SUB
    4857             :   { 36, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #36 = G_MUL
    4858             :   { 37, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #37 = G_SDIV
    4859             :   { 38, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #38 = G_UDIV
    4860             :   { 39, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #39 = G_SREM
    4861             :   { 40, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #40 = G_UREM
    4862             :   { 41, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #41 = G_AND
    4863             :   { 42, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #42 = G_OR
    4864             :   { 43, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #43 = G_XOR
    4865             :   { 44, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #44 = G_IMPLICIT_DEF
    4866             :   { 45, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #45 = G_PHI
    4867             :   { 46, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #46 = G_FRAME_INDEX
    4868             :   { 47, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #47 = G_GLOBAL_VALUE
    4869             :   { 48, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #48 = G_EXTRACT
    4870             :   { 49, 2,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #49 = G_UNMERGE_VALUES
    4871             :   { 50, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #50 = G_INSERT
    4872             :   { 51, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #51 = G_MERGE_VALUES
    4873             :   { 52, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #52 = G_PTRTOINT
    4874             :   { 53, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #53 = G_INTTOPTR
    4875             :   { 54, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #54 = G_BITCAST
    4876             :   { 55, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #55 = G_LOAD
    4877             :   { 56, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #56 = G_SEXTLOAD
    4878             :   { 57, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #57 = G_ZEXTLOAD
    4879             :   { 58, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #58 = G_STORE
    4880             :   { 59, 5,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #59 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
    4881             :   { 60, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #60 = G_ATOMIC_CMPXCHG
    4882             :   { 61, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #61 = G_ATOMICRMW_XCHG
    4883             :   { 62, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #62 = G_ATOMICRMW_ADD
    4884             :   { 63, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #63 = G_ATOMICRMW_SUB
    4885             :   { 64, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #64 = G_ATOMICRMW_AND
    4886             :   { 65, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #65 = G_ATOMICRMW_NAND
    4887             :   { 66, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #66 = G_ATOMICRMW_OR
    4888             :   { 67, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #67 = G_ATOMICRMW_XOR
    4889             :   { 68, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #68 = G_ATOMICRMW_MAX
    4890             :   { 69, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #69 = G_ATOMICRMW_MIN
    4891             :   { 70, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #70 = G_ATOMICRMW_UMAX
    4892             :   { 71, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #71 = G_ATOMICRMW_UMIN
    4893             :   { 72, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #72 = G_BRCOND
    4894             :   { 73, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #73 = G_BRINDIRECT
    4895             :   { 74, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #74 = G_INTRINSIC
    4896             :   { 75, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #75 = G_INTRINSIC_W_SIDE_EFFECTS
    4897             :   { 76, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #76 = G_ANYEXT
    4898             :   { 77, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #77 = G_TRUNC
    4899             :   { 78, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #78 = G_CONSTANT
    4900             :   { 79, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #79 = G_FCONSTANT
    4901             :   { 80, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #80 = G_VASTART
    4902             :   { 81, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #81 = G_VAARG
    4903             :   { 82, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #82 = G_SEXT
    4904             :   { 83, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #83 = G_ZEXT
    4905             :   { 84, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #84 = G_SHL
    4906             :   { 85, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #85 = G_LSHR
    4907             :   { 86, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #86 = G_ASHR
    4908             :   { 87, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #87 = G_ICMP
    4909             :   { 88, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #88 = G_FCMP
    4910             :   { 89, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #89 = G_SELECT
    4911             :   { 90, 5,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #90 = G_UADDE
    4912             :   { 91, 5,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #91 = G_USUBE
    4913             :   { 92, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #92 = G_SADDO
    4914             :   { 93, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #93 = G_SSUBO
    4915             :   { 94, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #94 = G_UMULO
    4916             :   { 95, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #95 = G_SMULO
    4917             :   { 96, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #96 = G_UMULH
    4918             :   { 97, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #97 = G_SMULH
    4919             :   { 98, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #98 = G_FADD
    4920             :   { 99, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #99 = G_FSUB
    4921             :   { 100,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #100 = G_FMUL
    4922             :   { 101,        4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #101 = G_FMA
    4923             :   { 102,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #102 = G_FDIV
    4924             :   { 103,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #103 = G_FREM
    4925             :   { 104,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #104 = G_FPOW
    4926             :   { 105,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #105 = G_FEXP
    4927             :   { 106,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #106 = G_FEXP2
    4928             :   { 107,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #107 = G_FLOG
    4929             :   { 108,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #108 = G_FLOG2
    4930             :   { 109,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #109 = G_FNEG
    4931             :   { 110,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #110 = G_FPEXT
    4932             :   { 111,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #111 = G_FPTRUNC
    4933             :   { 112,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #112 = G_FPTOSI
    4934             :   { 113,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #113 = G_FPTOUI
    4935             :   { 114,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #114 = G_SITOFP
    4936             :   { 115,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #115 = G_UITOFP
    4937             :   { 116,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #116 = G_FABS
    4938             :   { 117,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #117 = G_GEP
    4939             :   { 118,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #118 = G_PTR_MASK
    4940             :   { 119,        1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #119 = G_BR
    4941             :   { 120,        4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #120 = G_INSERT_VECTOR_ELT
    4942             :   { 121,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #121 = G_EXTRACT_VECTOR_ELT
    4943             :   { 122,        4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #122 = G_SHUFFLE_VECTOR
    4944             :   { 123,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #123 = G_BSWAP
    4945             :   { 124,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #124 = ADDCCCi32ri
    4946             :   { 125,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #125 = ADDCCCi32rr
    4947             :   { 126,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #126 = ADDCCi32ri
    4948             :   { 127,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #127 = ADDCCi32rr
    4949             :   { 128,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #128 = ADD_i1_ri
    4950             :   { 129,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #129 = ADD_i1_rr
    4951             :   { 130,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #130 = ADDi16ri
    4952             :   { 131,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #131 = ADDi16rr
    4953             :   { 132,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #132 = ADDi32ri
    4954             :   { 133,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #133 = ADDi32rr
    4955             :   { 134,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #134 = ADDi64ri
    4956             :   { 135,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #135 = ADDi64rr
    4957             :   { 136,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #136 = ANDb16ri
    4958             :   { 137,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #137 = ANDb16rr
    4959             :   { 138,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #138 = ANDb1ri
    4960             :   { 139,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #139 = ANDb1rr
    4961             :   { 140,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #140 = ANDb32ri
    4962             :   { 141,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #141 = ANDb32rr
    4963             :   { 142,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #142 = ANDb64ri
    4964             :   { 143,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #143 = ANDb64rr
    4965             :   { 144,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #144 = BFE_S32rii
    4966             :   { 145,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #145 = BFE_S32rri
    4967             :   { 146,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #146 = BFE_S32rrr
    4968             :   { 147,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #147 = BFE_S64rii
    4969             :   { 148,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #148 = BFE_S64rri
    4970             :   { 149,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #149 = BFE_S64rrr
    4971             :   { 150,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #150 = BFE_U32rii
    4972             :   { 151,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #151 = BFE_U32rri
    4973             :   { 152,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #152 = BFE_U32rrr
    4974             :   { 153,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #153 = BFE_U64rii
    4975             :   { 154,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #154 = BFE_U64rri
    4976             :   { 155,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #155 = BFE_U64rrr
    4977             :   { 156,        2,      1,      0,      0,      0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #156 = BITCONVERT_16_F2I
    4978             :   { 157,        2,      1,      0,      0,      0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #157 = BITCONVERT_16_I2F
    4979             :   { 158,        2,      1,      0,      0,      0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #158 = BITCONVERT_32_F16x22I
    4980             :   { 159,        2,      1,      0,      0,      0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #159 = BITCONVERT_32_F2I
    4981             :   { 160,        2,      1,      0,      0,      0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #160 = BITCONVERT_32_I2F
    4982             :   { 161,        2,      1,      0,      0,      0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #161 = BITCONVERT_32_I2F16x2
    4983             :   { 162,        2,      1,      0,      0,      0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #162 = BITCONVERT_64_F2I
    4984             :   { 163,        2,      1,      0,      0,      0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #163 = BITCONVERT_64_I2F
    4985             :   { 164,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #164 = BREV32
    4986             :   { 165,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #165 = BREV64
    4987             :   { 166,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #166 = BuildF16x2
    4988             :   { 167,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #167 = BuildF16x2i
    4989             :   { 168,        1,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #168 = CALL
    4990             :   { 169,        1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #169 = CALL_PROTOTYPE
    4991             :   { 170,        2,      0,      0,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #170 = CBranch
    4992             :   { 171,        2,      0,      0,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #171 = CBranchOther
    4993             :   { 172,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #172 = CLZr32
    4994             :   { 173,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #173 = CLZr64
    4995             :   { 174,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #174 = COSF
    4996             :   { 175,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #175 = CVT_INREG_s16_s8
    4997             :   { 176,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #176 = CVT_INREG_s32_s16
    4998             :   { 177,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #177 = CVT_INREG_s32_s8
    4999             :   { 178,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #178 = CVT_INREG_s64_s16
    5000             :   { 179,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #179 = CVT_INREG_s64_s32
    5001             :   { 180,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #180 = CVT_INREG_s64_s8
    5002             :   { 181,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #181 = CVT_f16_f16
    5003             :   { 182,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr },  // Inst #182 = CVT_f16_f32
    5004             :   { 183,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #183 = CVT_f16_f64
    5005             :   { 184,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr },  // Inst #184 = CVT_f16_s16
    5006             :   { 185,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr },  // Inst #185 = CVT_f16_s32
    5007             :   { 186,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #186 = CVT_f16_s64
    5008             :   { 187,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr },  // Inst #187 = CVT_f16_s8
    5009             :   { 188,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr },  // Inst #188 = CVT_f16_u16
    5010             :   { 189,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr },  // Inst #189 = CVT_f16_u32
    5011             :   { 190,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #190 = CVT_f16_u64
    5012             :   { 191,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr },  // Inst #191 = CVT_f16_u8
    5013             :   { 192,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #192 = CVT_f32_f16
    5014             :   { 193,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #193 = CVT_f32_f32
    5015             :   { 194,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #194 = CVT_f32_f64
    5016             :   { 195,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #195 = CVT_f32_s16
    5017             :   { 196,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr },  // Inst #196 = CVT_f32_s32
    5018             :   { 197,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr },  // Inst #197 = CVT_f32_s64
    5019             :   { 198,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #198 = CVT_f32_s8
    5020             :   { 199,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #199 = CVT_f32_u16
    5021             :   { 200,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr },  // Inst #200 = CVT_f32_u32
    5022             :   { 201,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr },  // Inst #201 = CVT_f32_u64
    5023             :   { 202,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #202 = CVT_f32_u8
    5024             :   { 203,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr },  // Inst #203 = CVT_f64_f16
    5025             :   { 204,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr },  // Inst #204 = CVT_f64_f32
    5026             :   { 205,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr },  // Inst #205 = CVT_f64_f64
    5027             :   { 206,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo76, -1 ,nullptr },  // Inst #206 = CVT_f64_s16
    5028             :   { 207,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr },  // Inst #207 = CVT_f64_s32
    5029             :   { 208,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr },  // Inst #208 = CVT_f64_s64
    5030             :   { 209,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo76, -1 ,nullptr },  // Inst #209 = CVT_f64_s8
    5031             :   { 210,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo76, -1 ,nullptr },  // Inst #210 = CVT_f64_u16
    5032             :   { 211,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr },  // Inst #211 = CVT_f64_u32
    5033             :   { 212,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr },  // Inst #212 = CVT_f64_u64
    5034             :   { 213,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo76, -1 ,nullptr },  // Inst #213 = CVT_f64_u8
    5035             :   { 214,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #214 = CVT_s16_f16
    5036             :   { 215,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #215 = CVT_s16_f32
    5037             :   { 216,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #216 = CVT_s16_f64
    5038             :   { 217,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #217 = CVT_s16_s16
    5039             :   { 218,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr },  // Inst #218 = CVT_s16_s32
    5040             :   { 219,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr },  // Inst #219 = CVT_s16_s64
    5041             :   { 220,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #220 = CVT_s16_s8
    5042             :   { 221,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #221 = CVT_s16_u16
    5043             :   { 222,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr },  // Inst #222 = CVT_s16_u32
    5044             :   { 223,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr },  // Inst #223 = CVT_s16_u64
    5045             :   { 224,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #224 = CVT_s16_u8
    5046             :   { 225,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr },  // Inst #225 = CVT_s32_f16
    5047             :   { 226,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #226 = CVT_s32_f32
    5048             :   { 227,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #227 = CVT_s32_f64
    5049             :   { 228,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr },  // Inst #228 = CVT_s32_s16
    5050             :   { 229,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr },  // Inst #229 = CVT_s32_s32
    5051             :   { 230,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #230 = CVT_s32_s64
    5052             :   { 231,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr },  // Inst #231 = CVT_s32_s8
    5053             :   { 232,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr },  // Inst #232 = CVT_s32_u16
    5054             :   { 233,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr },  // Inst #233 = CVT_s32_u32
    5055             :   { 234,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #234 = CVT_s32_u64
    5056             :   { 235,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr },  // Inst #235 = CVT_s32_u8
    5057             :   { 236,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #236 = CVT_s64_f16
    5058             :   { 237,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #237 = CVT_s64_f32
    5059             :   { 238,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #238 = CVT_s64_f64
    5060             :   { 239,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #239 = CVT_s64_s16
    5061             :   { 240,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #240 = CVT_s64_s32
    5062             :   { 241,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr },  // Inst #241 = CVT_s64_s64
    5063             :   { 242,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #242 = CVT_s64_s8
    5064             :   { 243,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #243 = CVT_s64_u16
    5065             :   { 244,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #244 = CVT_s64_u32
    5066             :   { 245,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr },  // Inst #245 = CVT_s64_u64
    5067             :   { 246,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #246 = CVT_s64_u8
    5068             :   { 247,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #247 = CVT_s8_f16
    5069             :   { 248,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #248 = CVT_s8_f32
    5070             :   { 249,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #249 = CVT_s8_f64
    5071             :   { 250,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #250 = CVT_s8_s16
    5072             :   { 251,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr },  // Inst #251 = CVT_s8_s32
    5073             :   { 252,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr },  // Inst #252 = CVT_s8_s64
    5074             :   { 253,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #253 = CVT_s8_s8
    5075             :   { 254,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #254 = CVT_s8_u16
    5076             :   { 255,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr },  // Inst #255 = CVT_s8_u32
    5077             :   { 256,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr },  // Inst #256 = CVT_s8_u64
    5078             :   { 257,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #257 = CVT_s8_u8
    5079             :   { 258,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #258 = CVT_u16_f16
    5080             :   { 259,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #259 = CVT_u16_f32
    5081             :   { 260,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #260 = CVT_u16_f64
    5082             :   { 261,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #261 = CVT_u16_s16
    5083             :   { 262,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr },  // Inst #262 = CVT_u16_s32
    5084             :   { 263,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr },  // Inst #263 = CVT_u16_s64
    5085             :   { 264,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #264 = CVT_u16_s8
    5086             :   { 265,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #265 = CVT_u16_u16
    5087             :   { 266,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr },  // Inst #266 = CVT_u16_u32
    5088             :   { 267,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr },  // Inst #267 = CVT_u16_u64
    5089             :   { 268,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #268 = CVT_u16_u8
    5090             :   { 269,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr },  // Inst #269 = CVT_u32_f16
    5091             :   { 270,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #270 = CVT_u32_f32
    5092             :   { 271,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #271 = CVT_u32_f64
    5093             :   { 272,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr },  // Inst #272 = CVT_u32_s16
    5094             :   { 273,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr },  // Inst #273 = CVT_u32_s32
    5095             :   { 274,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #274 = CVT_u32_s64
    5096             :   { 275,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr },  // Inst #275 = CVT_u32_s8
    5097             :   { 276,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr },  // Inst #276 = CVT_u32_u16
    5098             :   { 277,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr },  // Inst #277 = CVT_u32_u32
    5099             :   { 278,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #278 = CVT_u32_u64
    5100             :   { 279,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr },  // Inst #279 = CVT_u32_u8
    5101             :   { 280,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #280 = CVT_u64_f16
    5102             :   { 281,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #281 = CVT_u64_f32
    5103             :   { 282,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #282 = CVT_u64_f64
    5104             :   { 283,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #283 = CVT_u64_s16
    5105             :   { 284,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #284 = CVT_u64_s32
    5106             :   { 285,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr },  // Inst #285 = CVT_u64_s64
    5107             :   { 286,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #286 = CVT_u64_s8
    5108             :   { 287,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #287 = CVT_u64_u16
    5109             :   { 288,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #288 = CVT_u64_u32
    5110             :   { 289,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr },  // Inst #289 = CVT_u64_u64
    5111             :   { 290,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #290 = CVT_u64_u8
    5112             :   { 291,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #291 = CVT_u8_f16
    5113             :   { 292,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #292 = CVT_u8_f32
    5114             :   { 293,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #293 = CVT_u8_f64
    5115             :   { 294,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #294 = CVT_u8_s16
    5116             :   { 295,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr },  // Inst #295 = CVT_u8_s32
    5117             :   { 296,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr },  // Inst #296 = CVT_u8_s64
    5118             :   { 297,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #297 = CVT_u8_s8
    5119             :   { 298,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #298 = CVT_u8_u16
    5120             :   { 299,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr },  // Inst #299 = CVT_u8_u32
    5121             :   { 300,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr },  // Inst #300 = CVT_u8_u64
    5122             :   { 301,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #301 = CVT_u8_u8
    5123             :   { 302,        0,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #302 = CallArgBeginInst
    5124             :   { 303,        0,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #303 = CallArgEndInst0
    5125             :   { 304,        0,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #304 = CallArgEndInst1
    5126             :   { 305,        1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #305 = CallArgF32
    5127             :   { 306,        1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr },  // Inst #306 = CallArgF64
    5128             :   { 307,        1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr },  // Inst #307 = CallArgI16
    5129             :   { 308,        1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #308 = CallArgI32
    5130             :   { 309,        1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #309 = CallArgI32imm
    5131             :   { 310,        1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #310 = CallArgI64
    5132             :   { 311,        1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #311 = CallArgParam
    5133             :   { 312,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #312 = CallPrintCallNoRetInst
    5134             :   { 313,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #313 = CallPrintCallRetInst1
    5135             :   { 314,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #314 = CallPrintCallRetInst2
    5136             :   { 315,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #315 = CallPrintCallRetInst3
    5137             :   { 316,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #316 = CallPrintCallRetInst4
    5138             :   { 317,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #317 = CallPrintCallRetInst5
    5139             :   { 318,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #318 = CallPrintCallRetInst6
    5140             :   { 319,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #319 = CallPrintCallRetInst7
    5141             :   { 320,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #320 = CallPrintCallRetInst8
    5142             :   { 321,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #321 = CallUniPrintCallNoRetInst
    5143             :   { 322,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #322 = CallUniPrintCallRetInst1
    5144             :   { 323,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #323 = CallUniPrintCallRetInst2
    5145             :   { 324,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #324 = CallUniPrintCallRetInst3
    5146             :   { 325,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #325 = CallUniPrintCallRetInst4
    5147             :   { 326,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #326 = CallUniPrintCallRetInst5
    5148             :   { 327,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #327 = CallUniPrintCallRetInst6
    5149             :   { 328,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #328 = CallUniPrintCallRetInst7
    5150             :   { 329,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #329 = CallUniPrintCallRetInst8
    5151             :   { 330,        1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #330 = CallVoidInst
    5152             :   { 331,        1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #331 = CallVoidInstReg
    5153             :   { 332,        1,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #332 = CallVoidInstReg64
    5154             :   { 333,        2,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #333 = Callseq_End
    5155             :   { 334,        2,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #334 = Callseq_Start
    5156             :   { 335,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #335 = ConvergentCallPrintCallNoRetInst
    5157             :   { 336,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #336 = ConvergentCallPrintCallRetInst1
    5158             :   { 337,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #337 = ConvergentCallPrintCallRetInst2
    5159             :   { 338,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #338 = ConvergentCallPrintCallRetInst3
    5160             :   { 339,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #339 = ConvergentCallPrintCallRetInst4
    5161             :   { 340,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #340 = ConvergentCallPrintCallRetInst5
    5162             :   { 341,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #341 = ConvergentCallPrintCallRetInst6
    5163             :   { 342,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #342 = ConvergentCallPrintCallRetInst7
    5164             :   { 343,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #343 = ConvergentCallPrintCallRetInst8
    5165             :   { 344,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #344 = ConvergentCallUniPrintCallNoRetInst
    5166             :   { 345,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #345 = ConvergentCallUniPrintCallRetInst1
    5167             :   { 346,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #346 = ConvergentCallUniPrintCallRetInst2
    5168             :   { 347,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #347 = ConvergentCallUniPrintCallRetInst3
    5169             :   { 348,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #348 = ConvergentCallUniPrintCallRetInst4
    5170             :   { 349,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #349 = ConvergentCallUniPrintCallRetInst5
    5171             :   { 350,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #350 = ConvergentCallUniPrintCallRetInst6
    5172             :   { 351,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #351 = ConvergentCallUniPrintCallRetInst7
    5173             :   { 352,        0,      0,      0,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #352 = ConvergentCallUniPrintCallRetInst8
    5174             :   { 353,        3,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #353 = DeclareParamInst
    5175             :   { 354,        3,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #354 = DeclareRetMemInst
    5176             :   { 355,        2,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #355 = DeclareRetRegInst
    5177             :   { 356,        2,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #356 = DeclareRetScalarInst
    5178             :   { 357,        2,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #357 = DeclareScalarParamInst
    5179             :   { 358,        2,      0,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #358 = DeclareScalarRegInst
    5180             :   { 359,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr },  // Inst #359 = F16x2toF16_0
    5181             :   { 360,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr },  // Inst #360 = F16x2toF16_1
    5182             :   { 361,        3,      2,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr },  // Inst #361 = F64toV2F32
    5183             :   { 362,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #362 = FABSf32
    5184             :   { 363,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #363 = FABSf32_ftz
    5185             :   { 364,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #364 = FABSf64
    5186             :   { 365,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #365 = FADD_rnf16rr
    5187             :   { 366,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #366 = FADD_rnf16rr_ftz
    5188             :   { 367,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #367 = FADD_rnf16x2rr
    5189             :   { 368,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #368 = FADD_rnf16x2rr_ftz
    5190             :   { 369,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #369 = FADD_rnf32ri
    5191             :   { 370,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #370 = FADD_rnf32ri_ftz
    5192             :   { 371,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #371 = FADD_rnf32rr
    5193             :   { 372,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #372 = FADD_rnf32rr_ftz
    5194             :   { 373,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr },  // Inst #373 = FADD_rnf64ri
    5195             :   { 374,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #374 = FADD_rnf64rr
    5196             :   { 375,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #375 = FADDf16rr
    5197             :   { 376,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #376 = FADDf16rr_ftz
    5198             :   { 377,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #377 = FADDf16x2rr
    5199             :   { 378,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #378 = FADDf16x2rr_ftz
    5200             :   { 379,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #379 = FADDf32ri
    5201             :   { 380,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #380 = FADDf32ri_ftz
    5202             :   { 381,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #381 = FADDf32rr
    5203             :   { 382,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #382 = FADDf32rr_ftz
    5204             :   { 383,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr },  // Inst #383 = FADDf64ri
    5205             :   { 384,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #384 = FADDf64rr
    5206             :   { 385,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr },  // Inst #385 = FDIV321r
    5207             :   { 386,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr },  // Inst #386 = FDIV321r_approx
    5208             :   { 387,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr },  // Inst #387 = FDIV321r_approx_ftz
    5209             :   { 388,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr },  // Inst #388 = FDIV321r_ftz
    5210             :   { 389,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr },  // Inst #389 = FDIV321r_prec
    5211             :   { 390,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr },  // Inst #390 = FDIV321r_prec_ftz
    5212             :   { 391,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #391 = FDIV32approxri
    5213             :   { 392,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #392 = FDIV32approxri_ftz
    5214             :   { 393,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #393 = FDIV32approxrr
    5215             :   { 394,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #394 = FDIV32approxrr_ftz
    5216             :   { 395,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #395 = FDIV32ri
    5217             :   { 396,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #396 = FDIV32ri_ftz
    5218             :   { 397,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #397 = FDIV32ri_prec
    5219             :   { 398,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #398 = FDIV32ri_prec_ftz
    5220             :   { 399,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #399 = FDIV32rr
    5221             :   { 400,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #400 = FDIV32rr_ftz
    5222             :   { 401,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #401 = FDIV32rr_prec
    5223             :   { 402,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #402 = FDIV32rr_prec_ftz
    5224             :   { 403,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr },  // Inst #403 = FDIV641r
    5225             :   { 404,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr },  // Inst #404 = FDIV64ri
    5226             :   { 405,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #405 = FDIV64rr
    5227             :   { 406,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #406 = FMA16_ftzrrr
    5228             :   { 407,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #407 = FMA16rrr
    5229             :   { 408,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #408 = FMA16x2_ftzrrr
    5230             :   { 409,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #409 = FMA16x2rrr
    5231             :   { 410,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #410 = FMA32_ftzrii
    5232             :   { 411,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr },  // Inst #411 = FMA32_ftzrir
    5233             :   { 412,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #412 = FMA32_ftzrri
    5234             :   { 413,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #413 = FMA32_ftzrrr
    5235             :   { 414,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #414 = FMA32rii
    5236             :   { 415,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr },  // Inst #415 = FMA32rir
    5237             :   { 416,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #416 = FMA32rri
    5238             :   { 417,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #417 = FMA32rrr
    5239             :   { 418,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #418 = FMA64rii
    5240             :   { 419,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #419 = FMA64rir
    5241             :   { 420,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #420 = FMA64rri
    5242             :   { 421,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #421 = FMA64rrr
    5243             :   { 422,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #422 = FMAXf32ri
    5244             :   { 423,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #423 = FMAXf32ri_ftz
    5245             :   { 424,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #424 = FMAXf32rr
    5246             :   { 425,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #425 = FMAXf32rr_ftz
    5247             :   { 426,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr },  // Inst #426 = FMAXf64ri
    5248             :   { 427,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #427 = FMAXf64rr
    5249             :   { 428,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #428 = FMINf32ri
    5250             :   { 429,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #429 = FMINf32ri_ftz
    5251             :   { 430,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #430 = FMINf32rr
    5252             :   { 431,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #431 = FMINf32rr_ftz
    5253             :   { 432,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr },  // Inst #432 = FMINf64ri
    5254             :   { 433,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #433 = FMINf64rr
    5255             :   { 434,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr },  // Inst #434 = FMOV16rr
    5256             :   { 435,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr },  // Inst #435 = FMOV32ri
    5257             :   { 436,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #436 = FMOV32rr
    5258             :   { 437,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr },  // Inst #437 = FMOV64ri
    5259             :   { 438,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #438 = FMOV64rr
    5260             :   { 439,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #439 = FMUL_rnf16rr
    5261             :   { 440,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #440 = FMUL_rnf16rr_ftz
    5262             :   { 441,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #441 = FMUL_rnf16x2rr
    5263             :   { 442,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #442 = FMUL_rnf16x2rr_ftz
    5264             :   { 443,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #443 = FMUL_rnf32ri
    5265             :   { 444,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #444 = FMUL_rnf32ri_ftz
    5266             :   { 445,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #445 = FMUL_rnf32rr
    5267             :   { 446,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #446 = FMUL_rnf32rr_ftz
    5268             :   { 447,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr },  // Inst #447 = FMUL_rnf64ri
    5269             :   { 448,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #448 = FMUL_rnf64rr
    5270             :   { 449,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #449 = FMULf16rr
    5271             :   { 450,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #450 = FMULf16rr_ftz
    5272             :   { 451,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #451 = FMULf16x2rr
    5273             :   { 452,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #452 = FMULf16x2rr_ftz
    5274             :   { 453,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #453 = FMULf32ri
    5275             :   { 454,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #454 = FMULf32ri_ftz
    5276             :   { 455,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #455 = FMULf32rr
    5277             :   { 456,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #456 = FMULf32rr_ftz
    5278             :   { 457,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr },  // Inst #457 = FMULf64ri
    5279             :   { 458,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #458 = FMULf64rr
    5280             :   { 459,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #459 = FNEGf32
    5281             :   { 460,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #460 = FNEGf32_ftz
    5282             :   { 461,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #461 = FNEGf64
    5283             :   { 462,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #462 = FSQRTf32
    5284             :   { 463,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #463 = FSQRTf32_ftz
    5285             :   { 464,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #464 = FSQRTf64
    5286             :   { 465,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #465 = FSUB_rnf16rr
    5287             :   { 466,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #466 = FSUB_rnf16rr_ftz
    5288             :   { 467,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #467 = FSUB_rnf16x2rr
    5289             :   { 468,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #468 = FSUB_rnf16x2rr_ftz
    5290             :   { 469,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #469 = FSUB_rnf32ri
    5291             :   { 470,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #470 = FSUB_rnf32ri_ftz
    5292             :   { 471,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #471 = FSUB_rnf32rr
    5293             :   { 472,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #472 = FSUB_rnf32rr_ftz
    5294             :   { 473,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr },  // Inst #473 = FSUB_rnf64ri
    5295             :   { 474,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #474 = FSUB_rnf64rr
    5296             :   { 475,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #475 = FSUBf16rr
    5297             :   { 476,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #476 = FSUBf16rr_ftz
    5298             :   { 477,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #477 = FSUBf16x2rr
    5299             :   { 478,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #478 = FSUBf16x2rr_ftz
    5300             :   { 479,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #479 = FSUBf32ri
    5301             :   { 480,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #480 = FSUBf32ri_ftz
    5302             :   { 481,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #481 = FSUBf32rr
    5303             :   { 482,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #482 = FSUBf32rr_ftz
    5304             :   { 483,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr },  // Inst #483 = FSUBf64ri
    5305             :   { 484,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #484 = FSUBf64rr
    5306             :   { 485,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #485 = FUNSHFLCLAMP
    5307             :   { 486,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #486 = FUNSHFRCLAMP
    5308             :   { 487,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #487 = GET_HI_INT64
    5309             :   { 488,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #488 = GET_LO_INT64
    5310             :   { 489,        1,      0,      0,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #489 = GOTO
    5311             :   { 490,        3,      2,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr },  // Inst #490 = I32toV2I16
    5312             :   { 491,        3,      2,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr },  // Inst #491 = I64toV2I32
    5313             :   { 492,        5,      4,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #492 = I64toV4I16
    5314             :   { 493,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr },  // Inst #493 = IMOV16ri
    5315             :   { 494,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #494 = IMOV16rr
    5316             :   { 495,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #495 = IMOV1ri
    5317             :   { 496,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr },  // Inst #496 = IMOV1rr
    5318             :   { 497,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr },  // Inst #497 = IMOV32ri
    5319             :   { 498,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #498 = IMOV32rr
    5320             :   { 499,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #499 = IMOV64i
    5321             :   { 500,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #500 = IMOV64rr
    5322             :   { 501,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #501 = INEG16
    5323             :   { 502,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #502 = INEG32
    5324             :   { 503,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #503 = INEG64
    5325             :   { 504,        2,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #504 = INT_BARRIER
    5326             :   { 505,        0,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #505 = INT_BARRIER0
    5327             :   { 506,        2,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #506 = INT_BARRIER0_AND
    5328             :   { 507,        2,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #507 = INT_BARRIER0_OR
    5329             :   { 508,        2,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #508 = INT_BARRIER0_POPC
    5330             :   { 509,        1,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #509 = INT_BARRIERN
    5331             :   { 510,        2,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #510 = INT_BARRIER_SYNC_CNT_II
    5332             :   { 511,        2,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #511 = INT_BARRIER_SYNC_CNT_IR
    5333             :   { 512,        2,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr },  // Inst #512 = INT_BARRIER_SYNC_CNT_RI
    5334             :   { 513,        2,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #513 = INT_BARRIER_SYNC_CNT_RR
    5335             :   { 514,        1,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #514 = INT_BARRIER_SYNC_I
    5336             :   { 515,        1,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #515 = INT_BARRIER_SYNC_R
    5337             :   { 516,        1,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #516 = INT_BAR_SYNC
    5338             :   { 517,        1,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #517 = INT_BAR_WARP_SYNC_I
    5339             :   { 518,        1,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #518 = INT_BAR_WARP_SYNC_R
    5340             :   { 519,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #519 = INT_FNS_iii
    5341             :   { 520,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #520 = INT_FNS_iir
    5342             :   { 521,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr },  // Inst #521 = INT_FNS_iri
    5343             :   { 522,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr },  // Inst #522 = INT_FNS_irr
    5344             :   { 523,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #523 = INT_FNS_rii
    5345             :   { 524,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #524 = INT_FNS_rir
    5346             :   { 525,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #525 = INT_FNS_rri
    5347             :   { 526,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #526 = INT_FNS_rrr
    5348             :   { 527,        0,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #527 = INT_MEMBAR_CTA
    5349             :   { 528,        0,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #528 = INT_MEMBAR_GL
    5350             :   { 529,        0,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #529 = INT_MEMBAR_SYS
    5351             :   { 530,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #530 = INT_NVVM_ADD_RM_D
    5352             :   { 531,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #531 = INT_NVVM_ADD_RM_F
    5353             :   { 532,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #532 = INT_NVVM_ADD_RM_FTZ_F
    5354             :   { 533,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #533 = INT_NVVM_ADD_RN_D
    5355             :   { 534,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #534 = INT_NVVM_ADD_RN_F
    5356             :   { 535,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #535 = INT_NVVM_ADD_RN_FTZ_F
    5357             :   { 536,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #536 = INT_NVVM_ADD_RP_D
    5358             :   { 537,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #537 = INT_NVVM_ADD_RP_F
    5359             :   { 538,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #538 = INT_NVVM_ADD_RP_FTZ_F
    5360             :   { 539,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #539 = INT_NVVM_ADD_RZ_D
    5361             :   { 540,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #540 = INT_NVVM_ADD_RZ_F
    5362             :   { 541,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #541 = INT_NVVM_ADD_RZ_FTZ_F
    5363             :   { 542,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #542 = INT_NVVM_BITCAST_D2LL
    5364             :   { 543,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #543 = INT_NVVM_BITCAST_F2I
    5365             :   { 544,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #544 = INT_NVVM_BITCAST_I2F
    5366             :   { 545,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #545 = INT_NVVM_BITCAST_LL2D
    5367             :   { 546,        1,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #546 = INT_NVVM_COMPILER_ERROR_32
    5368             :   { 547,        1,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #547 = INT_NVVM_COMPILER_ERROR_64
    5369             :   { 548,        1,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #548 = INT_NVVM_COMPILER_WARN_32
    5370             :   { 549,        1,      0,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #549 = INT_NVVM_COMPILER_WARN_64
    5371             :   { 550,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #550 = INT_NVVM_COS_APPROX_F
    5372             :   { 551,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #551 = INT_NVVM_COS_APPROX_FTZ_F
    5373             :   { 552,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr },  // Inst #552 = INT_NVVM_D2I_HI
    5374             :   { 553,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr },  // Inst #553 = INT_NVVM_D2I_LO
    5375             :   { 554,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #554 = INT_NVVM_DIV_APPROX_F
    5376             :   { 555,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #555 = INT_NVVM_DIV_APPROX_FTZ_F
    5377             :   { 556,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #556 = INT_NVVM_DIV_RM_D
    5378             :   { 557,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #557 = INT_NVVM_DIV_RM_F
    5379             :   { 558,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #558 = INT_NVVM_DIV_RM_FTZ_F
    5380             :   { 559,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #559 = INT_NVVM_DIV_RN_D
    5381             :   { 560,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #560 = INT_NVVM_DIV_RN_F
    5382             :   { 561,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #561 = INT_NVVM_DIV_RN_FTZ_F
    5383             :   { 562,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #562 = INT_NVVM_DIV_RP_D
    5384             :   { 563,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #563 = INT_NVVM_DIV_RP_F
    5385             :   { 564,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #564 = INT_NVVM_DIV_RP_FTZ_F
    5386             :   { 565,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #565 = INT_NVVM_DIV_RZ_D
    5387             :   { 566,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #566 = INT_NVVM_DIV_RZ_F
    5388             :   { 567,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #567 = INT_NVVM_DIV_RZ_FTZ_F
    5389             :   { 568,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #568 = INT_NVVM_EX2_APPROX_D
    5390             :   { 569,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #569 = INT_NVVM_EX2_APPROX_F
    5391             :   { 570,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #570 = INT_NVVM_EX2_APPROX_FTZ_F
    5392             :   { 571,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #571 = INT_NVVM_FABS_D
    5393             :   { 572,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #572 = INT_NVVM_FABS_F
    5394             :   { 573,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #573 = INT_NVVM_FABS_FTZ_F
    5395             :   { 574,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #574 = INT_NVVM_FMAX_D
    5396             :   { 575,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #575 = INT_NVVM_FMAX_F
    5397             :   { 576,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #576 = INT_NVVM_FMAX_FTZ_F
    5398             :   { 577,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #577 = INT_NVVM_FMA_RM_D
    5399             :   { 578,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #578 = INT_NVVM_FMA_RM_F
    5400             :   { 579,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #579 = INT_NVVM_FMA_RM_FTZ_F
    5401             :   { 580,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #580 = INT_NVVM_FMA_RN_D
    5402             :   { 581,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #581 = INT_NVVM_FMA_RN_F
    5403             :   { 582,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #582 = INT_NVVM_FMA_RN_FTZ_F
    5404             :   { 583,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #583 = INT_NVVM_FMA_RP_D
    5405             :   { 584,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #584 = INT_NVVM_FMA_RP_F
    5406             :   { 585,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #585 = INT_NVVM_FMA_RP_FTZ_F
    5407             :   { 586,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #586 = INT_NVVM_FMA_RZ_D
    5408             :   { 587,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #587 = INT_NVVM_FMA_RZ_F
    5409             :   { 588,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #588 = INT_NVVM_FMA_RZ_FTZ_F
    5410             :   { 589,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #589 = INT_NVVM_FMIN_D
    5411             :   { 590,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #590 = INT_NVVM_FMIN_F
    5412             :   { 591,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #591 = INT_NVVM_FMIN_FTZ_F
    5413             :   { 592,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #592 = INT_NVVM_LG2_APPROX_D
    5414             :   { 593,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #593 = INT_NVVM_LG2_APPROX_F
    5415             :   { 594,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #594 = INT_NVVM_LG2_APPROX_FTZ_F
    5416             :   { 595,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr },  // Inst #595 = INT_NVVM_LOHI_I2D
    5417             :   { 596,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #596 = INT_NVVM_MUL24_I
    5418             :   { 597,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #597 = INT_NVVM_MUL24_UI
    5419             :   { 598,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #598 = INT_NVVM_MULHI_I
    5420             :   { 599,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #599 = INT_NVVM_MULHI_LL
    5421             :   { 600,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #600 = INT_NVVM_MULHI_UI
    5422             :   { 601,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #601 = INT_NVVM_MULHI_ULL
    5423             :   { 602,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #602 = INT_NVVM_MUL_RM_D
    5424             :   { 603,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #603 = INT_NVVM_MUL_RM_F
    5425             :   { 604,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #604 = INT_NVVM_MUL_RM_FTZ_F
    5426             :   { 605,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #605 = INT_NVVM_MUL_RN_D
    5427             :   { 606,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #606 = INT_NVVM_MUL_RN_F
    5428             :   { 607,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #607 = INT_NVVM_MUL_RN_FTZ_F
    5429             :   { 608,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #608 = INT_NVVM_MUL_RP_D
    5430             :   { 609,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #609 = INT_NVVM_MUL_RP_F
    5431             :   { 610,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #610 = INT_NVVM_MUL_RP_FTZ_F
    5432             :   { 611,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #611 = INT_NVVM_MUL_RZ_D
    5433             :   { 612,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #612 = INT_NVVM_MUL_RZ_F
    5434             :   { 613,        3,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #613 = INT_NVVM_MUL_RZ_FTZ_F
    5435             :   { 614,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #614 = INT_NVVM_PRMT
    5436             :   { 615,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #615 = INT_NVVM_RCP_APPROX_FTZ_D
    5437             :   { 616,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #616 = INT_NVVM_RCP_RM_D
    5438             :   { 617,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #617 = INT_NVVM_RCP_RM_F
    5439             :   { 618,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #618 = INT_NVVM_RCP_RM_FTZ_F
    5440             :   { 619,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #619 = INT_NVVM_RCP_RN_D
    5441             :   { 620,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #620 = INT_NVVM_RCP_RN_F
    5442             :   { 621,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #621 = INT_NVVM_RCP_RN_FTZ_F
    5443             :   { 622,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #622 = INT_NVVM_RCP_RP_D
    5444             :   { 623,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #623 = INT_NVVM_RCP_RP_F
    5445             :   { 624,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #624 = INT_NVVM_RCP_RP_FTZ_F
    5446             :   { 625,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #625 = INT_NVVM_RCP_RZ_D
    5447             :   { 626,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #626 = INT_NVVM_RCP_RZ_F
    5448             :   { 627,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #627 = INT_NVVM_RCP_RZ_FTZ_F
    5449             :   { 628,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #628 = INT_NVVM_RSQRT_APPROX_D
    5450             :   { 629,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #629 = INT_NVVM_RSQRT_APPROX_F
    5451             :   { 630,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #630 = INT_NVVM_RSQRT_APPROX_FTZ_F
    5452             :   { 631,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #631 = INT_NVVM_SAD_I
    5453             :   { 632,        4,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #632 = INT_NVVM_SAD_UI
    5454             :   { 633,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #633 = INT_NVVM_SIN_APPROX_F
    5455             :   { 634,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #634 = INT_NVVM_SIN_APPROX_FTZ_F
    5456             :   { 635,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #635 = INT_NVVM_SQRT_APPROX_F
    5457             :   { 636,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #636 = INT_NVVM_SQRT_APPROX_FTZ_F
    5458             :   { 637,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #637 = INT_NVVM_SQRT_RM_D
    5459             :   { 638,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #638 = INT_NVVM_SQRT_RM_F
    5460             :   { 639,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #639 = INT_NVVM_SQRT_RM_FTZ_F
    5461             :   { 640,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #640 = INT_NVVM_SQRT_RN_D
    5462             :   { 641,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #641 = INT_NVVM_SQRT_RN_F
    5463             :   { 642,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #642 = INT_NVVM_SQRT_RN_FTZ_F
    5464             :   { 643,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #643 = INT_NVVM_SQRT_RP_D
    5465             :   { 644,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #644 = INT_NVVM_SQRT_RP_F
    5466             :   { 645,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #645 = INT_NVVM_SQRT_RP_FTZ_F
    5467             :   { 646,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #646 = INT_NVVM_SQRT_RZ_D
    5468             :   { 647,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #647 = INT_NVVM_SQRT_RZ_F
    5469             :   { 648,        2,      1,      0,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #648 = INT_NVVM_SQRT_RZ_FTZ_F
    5470             :   { 649,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #649 = INT_PTX_ATOM_ADD_GEN_32_USE_Gp32imm
    5471             :   { 650,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #650 = INT_PTX_ATOM_ADD_GEN_32_USE_Gp32reg
    5472             :   { 651,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #651 = INT_PTX_ATOM_ADD_GEN_32_USE_Gp64imm
    5473             :   { 652,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #652 = INT_PTX_ATOM_ADD_GEN_32_USE_Gp64reg
    5474             :   { 653,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #653 = INT_PTX_ATOM_ADD_GEN_32p32imm
    5475             :   { 654,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #654 = INT_PTX_ATOM_ADD_GEN_32p32reg
    5476             :   { 655,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #655 = INT_PTX_ATOM_ADD_GEN_32p64imm
    5477             :   { 656,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #656 = INT_PTX_ATOM_ADD_GEN_32p64reg
    5478             :   { 657,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #657 = INT_PTX_ATOM_ADD_GEN_64_USE_Gp32imm
    5479             :   { 658,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #658 = INT_PTX_ATOM_ADD_GEN_64_USE_Gp32reg
    5480             :   { 659,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #659 = INT_PTX_ATOM_ADD_GEN_64_USE_Gp64imm
    5481             :   { 660,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #660 = INT_PTX_ATOM_ADD_GEN_64_USE_Gp64reg
    5482             :   { 661,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #661 = INT_PTX_ATOM_ADD_GEN_64p32imm
    5483             :   { 662,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #662 = INT_PTX_ATOM_ADD_GEN_64p32reg
    5484             :   { 663,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #663 = INT_PTX_ATOM_ADD_GEN_64p64imm
    5485             :   { 664,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #664 = INT_PTX_ATOM_ADD_GEN_64p64reg
    5486             :   { 665,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #665 = INT_PTX_ATOM_ADD_GEN_F32p32imm
    5487             :   { 666,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #666 = INT_PTX_ATOM_ADD_GEN_F32p32reg
    5488             :   { 667,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #667 = INT_PTX_ATOM_ADD_GEN_F32p64imm
    5489             :   { 668,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #668 = INT_PTX_ATOM_ADD_GEN_F32p64reg
    5490             :   { 669,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #669 = INT_PTX_ATOM_ADD_GEN_F64p32imm
    5491             :   { 670,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #670 = INT_PTX_ATOM_ADD_GEN_F64p32reg
    5492             :   { 671,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #671 = INT_PTX_ATOM_ADD_GEN_F64p64imm
    5493             :   { 672,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr },  // Inst #672 = INT_PTX_ATOM_ADD_GEN_F64p64reg
    5494             :   { 673,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #673 = INT_PTX_ATOM_ADD_G_32p32imm
    5495             :   { 674,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #674 = INT_PTX_ATOM_ADD_G_32p32reg
    5496             :   { 675,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #675 = INT_PTX_ATOM_ADD_G_32p64imm
    5497             :   { 676,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #676 = INT_PTX_ATOM_ADD_G_32p64reg
    5498             :   { 677,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #677 = INT_PTX_ATOM_ADD_G_64p32imm
    5499             :   { 678,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #678 = INT_PTX_ATOM_ADD_G_64p32reg
    5500             :   { 679,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #679 = INT_PTX_ATOM_ADD_G_64p64imm
    5501             :   { 680,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #680 = INT_PTX_ATOM_ADD_G_64p64reg
    5502             :   { 681,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #681 = INT_PTX_ATOM_ADD_G_F32p32imm
    5503             :   { 682,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #682 = INT_PTX_ATOM_ADD_G_F32p32reg
    5504             :   { 683,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #683 = INT_PTX_ATOM_ADD_G_F32p64imm
    5505             :   { 684,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #684 = INT_PTX_ATOM_ADD_G_F32p64reg
    5506             :   { 685,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #685 = INT_PTX_ATOM_ADD_G_F64p32imm
    5507             :   { 686,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #686 = INT_PTX_ATOM_ADD_G_F64p32reg
    5508             :   { 687,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #687 = INT_PTX_ATOM_ADD_G_F64p64imm
    5509             :   { 688,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr },  // Inst #688 = INT_PTX_ATOM_ADD_G_F64p64reg
    5510             :   { 689,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #689 = INT_PTX_ATOM_ADD_S_32p32imm
    5511             :   { 690,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #690 = INT_PTX_ATOM_ADD_S_32p32reg
    5512             :   { 691,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #691 = INT_PTX_ATOM_ADD_S_32p64imm
    5513             :   { 692,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #692 = INT_PTX_ATOM_ADD_S_32p64reg
    5514             :   { 693,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #693 = INT_PTX_ATOM_ADD_S_64p32imm
    5515             :   { 694,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #694 = INT_PTX_ATOM_ADD_S_64p32reg
    5516             :   { 695,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #695 = INT_PTX_ATOM_ADD_S_64p64imm
    5517             :   { 696,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #696 = INT_PTX_ATOM_ADD_S_64p64reg
    5518             :   { 697,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #697 = INT_PTX_ATOM_ADD_S_F32p32imm
    5519             :   { 698,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #698 = INT_PTX_ATOM_ADD_S_F32p32reg
    5520             :   { 699,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #699 = INT_PTX_ATOM_ADD_S_F32p64imm
    5521             :   { 700,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #700 = INT_PTX_ATOM_ADD_S_F32p64reg
    5522             :   { 701,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #701 = INT_PTX_ATOM_ADD_S_F64p32imm
    5523             :   { 702,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #702 = INT_PTX_ATOM_ADD_S_F64p32reg
    5524             :   { 703,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #703 = INT_PTX_ATOM_ADD_S_F64p64imm
    5525             :   { 704,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr },  // Inst #704 = INT_PTX_ATOM_ADD_S_F64p64reg
    5526             :   { 705,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #705 = INT_PTX_ATOM_AND_GEN_32_USE_Gp32imm
    5527             :   { 706,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #706 = INT_PTX_ATOM_AND_GEN_32_USE_Gp32reg
    5528             :   { 707,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #707 = INT_PTX_ATOM_AND_GEN_32_USE_Gp64imm
    5529             :   { 708,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #708 = INT_PTX_ATOM_AND_GEN_32_USE_Gp64reg
    5530             :   { 709,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #709 = INT_PTX_ATOM_AND_GEN_32p32imm
    5531             :   { 710,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #710 = INT_PTX_ATOM_AND_GEN_32p32reg
    5532             :   { 711,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #711 = INT_PTX_ATOM_AND_GEN_32p64imm
    5533             :   { 712,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #712 = INT_PTX_ATOM_AND_GEN_32p64reg
    5534             :   { 713,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #713 = INT_PTX_ATOM_AND_GEN_64_USE_Gp32imm
    5535             :   { 714,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #714 = INT_PTX_ATOM_AND_GEN_64_USE_Gp32reg
    5536             :   { 715,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #715 = INT_PTX_ATOM_AND_GEN_64_USE_Gp64imm
    5537             :   { 716,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #716 = INT_PTX_ATOM_AND_GEN_64_USE_Gp64reg
    5538             :   { 717,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #717 = INT_PTX_ATOM_AND_GEN_64p32imm
    5539             :   { 718,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #718 = INT_PTX_ATOM_AND_GEN_64p32reg
    5540             :   { 719,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #719 = INT_PTX_ATOM_AND_GEN_64p64imm
    5541             :   { 720,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #720 = INT_PTX_ATOM_AND_GEN_64p64reg
    5542             :   { 721,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #721 = INT_PTX_ATOM_AND_G_32p32imm
    5543             :   { 722,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #722 = INT_PTX_ATOM_AND_G_32p32reg
    5544             :   { 723,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #723 = INT_PTX_ATOM_AND_G_32p64imm
    5545             :   { 724,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #724 = INT_PTX_ATOM_AND_G_32p64reg
    5546             :   { 725,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #725 = INT_PTX_ATOM_AND_G_64p32imm
    5547             :   { 726,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #726 = INT_PTX_ATOM_AND_G_64p32reg
    5548             :   { 727,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #727 = INT_PTX_ATOM_AND_G_64p64imm
    5549             :   { 728,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #728 = INT_PTX_ATOM_AND_G_64p64reg
    5550             :   { 729,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #729 = INT_PTX_ATOM_AND_S_32p32imm
    5551             :   { 730,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #730 = INT_PTX_ATOM_AND_S_32p32reg
    5552             :   { 731,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #731 = INT_PTX_ATOM_AND_S_32p64imm
    5553             :   { 732,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #732 = INT_PTX_ATOM_AND_S_32p64reg
    5554             :   { 733,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #733 = INT_PTX_ATOM_AND_S_64p32imm
    5555             :   { 734,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #734 = INT_PTX_ATOM_AND_S_64p32reg
    5556             :   { 735,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #735 = INT_PTX_ATOM_AND_S_64p64imm
    5557             :   { 736,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #736 = INT_PTX_ATOM_AND_S_64p64reg
    5558             :   { 737,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #737 = INT_PTX_ATOM_CAS_GEN_32_USE_Gp32imm1
    5559             :   { 738,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #738 = INT_PTX_ATOM_CAS_GEN_32_USE_Gp32imm2
    5560             :   { 739,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #739 = INT_PTX_ATOM_CAS_GEN_32_USE_Gp32imm3
    5561             :   { 740,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #740 = INT_PTX_ATOM_CAS_GEN_32_USE_Gp32reg
    5562             :   { 741,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr },  // Inst #741 = INT_PTX_ATOM_CAS_GEN_32_USE_Gp64imm1
    5563             :   { 742,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #742 = INT_PTX_ATOM_CAS_GEN_32_USE_Gp64imm2
    5564             :   { 743,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr },  // Inst #743 = INT_PTX_ATOM_CAS_GEN_32_USE_Gp64imm3
    5565             :   { 744,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr },  // Inst #744 = INT_PTX_ATOM_CAS_GEN_32_USE_Gp64reg
    5566             :   { 745,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #745 = INT_PTX_ATOM_CAS_GEN_32p32imm1
    5567             :   { 746,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #746 = INT_PTX_ATOM_CAS_GEN_32p32imm2
    5568             :   { 747,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #747 = INT_PTX_ATOM_CAS_GEN_32p32imm3
    5569             :   { 748,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #748 = INT_PTX_ATOM_CAS_GEN_32p32reg
    5570             :   { 749,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr },  // Inst #749 = INT_PTX_ATOM_CAS_GEN_32p64imm1
    5571             :   { 750,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #750 = INT_PTX_ATOM_CAS_GEN_32p64imm2
    5572             :   { 751,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr },  // Inst #751 = INT_PTX_ATOM_CAS_GEN_32p64imm3
    5573             :   { 752,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr },  // Inst #752 = INT_PTX_ATOM_CAS_GEN_32p64reg
    5574             :   { 753,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr },  // Inst #753 = INT_PTX_ATOM_CAS_GEN_64_USE_Gp32imm1
    5575             :   { 754,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr },  // Inst #754 = INT_PTX_ATOM_CAS_GEN_64_USE_Gp32imm2
    5576             :   { 755,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #755 = INT_PTX_ATOM_CAS_GEN_64_USE_Gp32imm3
    5577             :   { 756,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr },  // Inst #756 = INT_PTX_ATOM_CAS_GEN_64_USE_Gp32reg
    5578             :   { 757,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr },  // Inst #757 = INT_PTX_ATOM_CAS_GEN_64_USE_Gp64imm1
    5579             :   { 758,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #758 = INT_PTX_ATOM_CAS_GEN_64_USE_Gp64imm2
    5580             :   { 759,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #759 = INT_PTX_ATOM_CAS_GEN_64_USE_Gp64imm3
    5581             :   { 760,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr },  // Inst #760 = INT_PTX_ATOM_CAS_GEN_64_USE_Gp64reg
    5582             :   { 761,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr },  // Inst #761 = INT_PTX_ATOM_CAS_GEN_64p32imm1
    5583             :   { 762,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr },  // Inst #762 = INT_PTX_ATOM_CAS_GEN_64p32imm2
    5584             :   { 763,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #763 = INT_PTX_ATOM_CAS_GEN_64p32imm3
    5585             :   { 764,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr },  // Inst #764 = INT_PTX_ATOM_CAS_GEN_64p32reg
    5586             :   { 765,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr },  // Inst #765 = INT_PTX_ATOM_CAS_GEN_64p64imm1
    5587             :   { 766,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #766 = INT_PTX_ATOM_CAS_GEN_64p64imm2
    5588             :   { 767,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #767 = INT_PTX_ATOM_CAS_GEN_64p64imm3
    5589             :   { 768,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr },  // Inst #768 = INT_PTX_ATOM_CAS_GEN_64p64reg
    5590             :   { 769,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #769 = INT_PTX_ATOM_CAS_G_32p32imm1
    5591             :   { 770,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #770 = INT_PTX_ATOM_CAS_G_32p32imm2
    5592             :   { 771,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #771 = INT_PTX_ATOM_CAS_G_32p32imm3
    5593             :   { 772,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #772 = INT_PTX_ATOM_CAS_G_32p32reg
    5594             :   { 773,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr },  // Inst #773 = INT_PTX_ATOM_CAS_G_32p64imm1
    5595             :   { 774,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #774 = INT_PTX_ATOM_CAS_G_32p64imm2
    5596             :   { 775,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr },  // Inst #775 = INT_PTX_ATOM_CAS_G_32p64imm3
    5597             :   { 776,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr },  // Inst #776 = INT_PTX_ATOM_CAS_G_32p64reg
    5598             :   { 777,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr },  // Inst #777 = INT_PTX_ATOM_CAS_G_64p32imm1
    5599             :   { 778,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr },  // Inst #778 = INT_PTX_ATOM_CAS_G_64p32imm2
    5600             :   { 779,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #779 = INT_PTX_ATOM_CAS_G_64p32imm3
    5601             :   { 780,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr },  // Inst #780 = INT_PTX_ATOM_CAS_G_64p32reg
    5602             :   { 781,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr },  // Inst #781 = INT_PTX_ATOM_CAS_G_64p64imm1
    5603             :   { 782,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #782 = INT_PTX_ATOM_CAS_G_64p64imm2
    5604             :   { 783,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #783 = INT_PTX_ATOM_CAS_G_64p64imm3
    5605             :   { 784,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr },  // Inst #784 = INT_PTX_ATOM_CAS_G_64p64reg
    5606             :   { 785,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #785 = INT_PTX_ATOM_CAS_S_32p32imm1
    5607             :   { 786,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #786 = INT_PTX_ATOM_CAS_S_32p32imm2
    5608             :   { 787,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #787 = INT_PTX_ATOM_CAS_S_32p32imm3
    5609             :   { 788,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #788 = INT_PTX_ATOM_CAS_S_32p32reg
    5610             :   { 789,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr },  // Inst #789 = INT_PTX_ATOM_CAS_S_32p64imm1
    5611             :   { 790,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #790 = INT_PTX_ATOM_CAS_S_32p64imm2
    5612             :   { 791,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr },  // Inst #791 = INT_PTX_ATOM_CAS_S_32p64imm3
    5613             :   { 792,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr },  // Inst #792 = INT_PTX_ATOM_CAS_S_32p64reg
    5614             :   { 793,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr },  // Inst #793 = INT_PTX_ATOM_CAS_S_64p32imm1
    5615             :   { 794,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr },  // Inst #794 = INT_PTX_ATOM_CAS_S_64p32imm2
    5616             :   { 795,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #795 = INT_PTX_ATOM_CAS_S_64p32imm3
    5617             :   { 796,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr },  // Inst #796 = INT_PTX_ATOM_CAS_S_64p32reg
    5618             :   { 797,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr },  // Inst #797 = INT_PTX_ATOM_CAS_S_64p64imm1
    5619             :   { 798,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #798 = INT_PTX_ATOM_CAS_S_64p64imm2
    5620             :   { 799,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #799 = INT_PTX_ATOM_CAS_S_64p64imm3
    5621             :   { 800,        4,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr },  // Inst #800 = INT_PTX_ATOM_CAS_S_64p64reg
    5622             :   { 801,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #801 = INT_PTX_ATOM_DEC_GEN_32_USE_Gp32imm
    5623             :   { 802,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #802 = INT_PTX_ATOM_DEC_GEN_32_USE_Gp32reg
    5624             :   { 803,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #803 = INT_PTX_ATOM_DEC_GEN_32_USE_Gp64imm
    5625             :   { 804,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #804 = INT_PTX_ATOM_DEC_GEN_32_USE_Gp64reg
    5626             :   { 805,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #805 = INT_PTX_ATOM_DEC_GEN_32p32imm
    5627             :   { 806,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #806 = INT_PTX_ATOM_DEC_GEN_32p32reg
    5628             :   { 807,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #807 = INT_PTX_ATOM_DEC_GEN_32p64imm
    5629             :   { 808,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #808 = INT_PTX_ATOM_DEC_GEN_32p64reg
    5630             :   { 809,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #809 = INT_PTX_ATOM_DEC_G_32p32imm
    5631             :   { 810,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #810 = INT_PTX_ATOM_DEC_G_32p32reg
    5632             :   { 811,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #811 = INT_PTX_ATOM_DEC_G_32p64imm
    5633             :   { 812,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #812 = INT_PTX_ATOM_DEC_G_32p64reg
    5634             :   { 813,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #813 = INT_PTX_ATOM_DEC_S_32p32imm
    5635             :   { 814,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #814 = INT_PTX_ATOM_DEC_S_32p32reg
    5636             :   { 815,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #815 = INT_PTX_ATOM_DEC_S_32p64imm
    5637             :   { 816,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #816 = INT_PTX_ATOM_DEC_S_32p64reg
    5638             :   { 817,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #817 = INT_PTX_ATOM_INC_GEN_32_USE_Gp32imm
    5639             :   { 818,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #818 = INT_PTX_ATOM_INC_GEN_32_USE_Gp32reg
    5640             :   { 819,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #819 = INT_PTX_ATOM_INC_GEN_32_USE_Gp64imm
    5641             :   { 820,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #820 = INT_PTX_ATOM_INC_GEN_32_USE_Gp64reg
    5642             :   { 821,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #821 = INT_PTX_ATOM_INC_GEN_32p32imm
    5643             :   { 822,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #822 = INT_PTX_ATOM_INC_GEN_32p32reg
    5644             :   { 823,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #823 = INT_PTX_ATOM_INC_GEN_32p64imm
    5645             :   { 824,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #824 = INT_PTX_ATOM_INC_GEN_32p64reg
    5646             :   { 825,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #825 = INT_PTX_ATOM_INC_G_32p32imm
    5647             :   { 826,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #826 = INT_PTX_ATOM_INC_G_32p32reg
    5648             :   { 827,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #827 = INT_PTX_ATOM_INC_G_32p64imm
    5649             :   { 828,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #828 = INT_PTX_ATOM_INC_G_32p64reg
    5650             :   { 829,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #829 = INT_PTX_ATOM_INC_S_32p32imm
    5651             :   { 830,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #830 = INT_PTX_ATOM_INC_S_32p32reg
    5652             :   { 831,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #831 = INT_PTX_ATOM_INC_S_32p64imm
    5653             :   { 832,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #832 = INT_PTX_ATOM_INC_S_32p64reg
    5654             :   { 833,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #833 = INT_PTX_ATOM_LOAD_MAX_GEN_32_USE_Gp32imm
    5655             :   { 834,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #834 = INT_PTX_ATOM_LOAD_MAX_GEN_32_USE_Gp32reg
    5656             :   { 835,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #835 = INT_PTX_ATOM_LOAD_MAX_GEN_32_USE_Gp64imm
    5657             :   { 836,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #836 = INT_PTX_ATOM_LOAD_MAX_GEN_32_USE_Gp64reg
    5658             :   { 837,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #837 = INT_PTX_ATOM_LOAD_MAX_GEN_32p32imm
    5659             :   { 838,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #838 = INT_PTX_ATOM_LOAD_MAX_GEN_32p32reg
    5660             :   { 839,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #839 = INT_PTX_ATOM_LOAD_MAX_GEN_32p64imm
    5661             :   { 840,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #840 = INT_PTX_ATOM_LOAD_MAX_GEN_32p64reg
    5662             :   { 841,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #841 = INT_PTX_ATOM_LOAD_MAX_GEN_64_USE_Gp32imm
    5663             :   { 842,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #842 = INT_PTX_ATOM_LOAD_MAX_GEN_64_USE_Gp32reg
    5664             :   { 843,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #843 = INT_PTX_ATOM_LOAD_MAX_GEN_64_USE_Gp64imm
    5665             :   { 844,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #844 = INT_PTX_ATOM_LOAD_MAX_GEN_64_USE_Gp64reg
    5666             :   { 845,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #845 = INT_PTX_ATOM_LOAD_MAX_GEN_64p32imm
    5667             :   { 846,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #846 = INT_PTX_ATOM_LOAD_MAX_GEN_64p32reg
    5668             :   { 847,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #847 = INT_PTX_ATOM_LOAD_MAX_GEN_64p64imm
    5669             :   { 848,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #848 = INT_PTX_ATOM_LOAD_MAX_GEN_64p64reg
    5670             :   { 849,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #849 = INT_PTX_ATOM_LOAD_MAX_G_32p32imm
    5671             :   { 850,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #850 = INT_PTX_ATOM_LOAD_MAX_G_32p32reg
    5672             :   { 851,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #851 = INT_PTX_ATOM_LOAD_MAX_G_32p64imm
    5673             :   { 852,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #852 = INT_PTX_ATOM_LOAD_MAX_G_32p64reg
    5674             :   { 853,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #853 = INT_PTX_ATOM_LOAD_MAX_G_64p32imm
    5675             :   { 854,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #854 = INT_PTX_ATOM_LOAD_MAX_G_64p32reg
    5676             :   { 855,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #855 = INT_PTX_ATOM_LOAD_MAX_G_64p64imm
    5677             :   { 856,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #856 = INT_PTX_ATOM_LOAD_MAX_G_64p64reg
    5678             :   { 857,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #857 = INT_PTX_ATOM_LOAD_MAX_S_32p32imm
    5679             :   { 858,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #858 = INT_PTX_ATOM_LOAD_MAX_S_32p32reg
    5680             :   { 859,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #859 = INT_PTX_ATOM_LOAD_MAX_S_32p64imm
    5681             :   { 860,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #860 = INT_PTX_ATOM_LOAD_MAX_S_32p64reg
    5682             :   { 861,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #861 = INT_PTX_ATOM_LOAD_MAX_S_64p32imm
    5683             :   { 862,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #862 = INT_PTX_ATOM_LOAD_MAX_S_64p32reg
    5684             :   { 863,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #863 = INT_PTX_ATOM_LOAD_MAX_S_64p64imm
    5685             :   { 864,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #864 = INT_PTX_ATOM_LOAD_MAX_S_64p64reg
    5686             :   { 865,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #865 = INT_PTX_ATOM_LOAD_MIN_GEN_32_USE_Gp32imm
    5687             :   { 866,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #866 = INT_PTX_ATOM_LOAD_MIN_GEN_32_USE_Gp32reg
    5688             :   { 867,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #867 = INT_PTX_ATOM_LOAD_MIN_GEN_32_USE_Gp64imm
    5689             :   { 868,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #868 = INT_PTX_ATOM_LOAD_MIN_GEN_32_USE_Gp64reg
    5690             :   { 869,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #869 = INT_PTX_ATOM_LOAD_MIN_GEN_32p32imm
    5691             :   { 870,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #870 = INT_PTX_ATOM_LOAD_MIN_GEN_32p32reg
    5692             :   { 871,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #871 = INT_PTX_ATOM_LOAD_MIN_GEN_32p64imm
    5693             :   { 872,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #872 = INT_PTX_ATOM_LOAD_MIN_GEN_32p64reg
    5694             :   { 873,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #873 = INT_PTX_ATOM_LOAD_MIN_GEN_64_USE_Gp32imm
    5695             :   { 874,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #874 = INT_PTX_ATOM_LOAD_MIN_GEN_64_USE_Gp32reg
    5696             :   { 875,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #875 = INT_PTX_ATOM_LOAD_MIN_GEN_64_USE_Gp64imm
    5697             :   { 876,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #876 = INT_PTX_ATOM_LOAD_MIN_GEN_64_USE_Gp64reg
    5698             :   { 877,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #877 = INT_PTX_ATOM_LOAD_MIN_GEN_64p32imm
    5699             :   { 878,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #878 = INT_PTX_ATOM_LOAD_MIN_GEN_64p32reg
    5700             :   { 879,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #879 = INT_PTX_ATOM_LOAD_MIN_GEN_64p64imm
    5701             :   { 880,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #880 = INT_PTX_ATOM_LOAD_MIN_GEN_64p64reg
    5702             :   { 881,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #881 = INT_PTX_ATOM_LOAD_MIN_G_32p32imm
    5703             :   { 882,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #882 = INT_PTX_ATOM_LOAD_MIN_G_32p32reg
    5704             :   { 883,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #883 = INT_PTX_ATOM_LOAD_MIN_G_32p64imm
    5705             :   { 884,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #884 = INT_PTX_ATOM_LOAD_MIN_G_32p64reg
    5706             :   { 885,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #885 = INT_PTX_ATOM_LOAD_MIN_G_64p32imm
    5707             :   { 886,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #886 = INT_PTX_ATOM_LOAD_MIN_G_64p32reg
    5708             :   { 887,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #887 = INT_PTX_ATOM_LOAD_MIN_G_64p64imm
    5709             :   { 888,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #888 = INT_PTX_ATOM_LOAD_MIN_G_64p64reg
    5710             :   { 889,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #889 = INT_PTX_ATOM_LOAD_MIN_S_32p32imm
    5711             :   { 890,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #890 = INT_PTX_ATOM_LOAD_MIN_S_32p32reg
    5712             :   { 891,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #891 = INT_PTX_ATOM_LOAD_MIN_S_32p64imm
    5713             :   { 892,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #892 = INT_PTX_ATOM_LOAD_MIN_S_32p64reg
    5714             :   { 893,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #893 = INT_PTX_ATOM_LOAD_MIN_S_64p32imm
    5715             :   { 894,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #894 = INT_PTX_ATOM_LOAD_MIN_S_64p32reg
    5716             :   { 895,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #895 = INT_PTX_ATOM_LOAD_MIN_S_64p64imm
    5717             :   { 896,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #896 = INT_PTX_ATOM_LOAD_MIN_S_64p64reg
    5718             :   { 897,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #897 = INT_PTX_ATOM_LOAD_UMAX_GEN_32_USE_Gp32imm
    5719             :   { 898,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #898 = INT_PTX_ATOM_LOAD_UMAX_GEN_32_USE_Gp32reg
    5720             :   { 899,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #899 = INT_PTX_ATOM_LOAD_UMAX_GEN_32_USE_Gp64imm
    5721             :   { 900,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #900 = INT_PTX_ATOM_LOAD_UMAX_GEN_32_USE_Gp64reg
    5722             :   { 901,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #901 = INT_PTX_ATOM_LOAD_UMAX_GEN_32p32imm
    5723             :   { 902,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #902 = INT_PTX_ATOM_LOAD_UMAX_GEN_32p32reg
    5724             :   { 903,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #903 = INT_PTX_ATOM_LOAD_UMAX_GEN_32p64imm
    5725             :   { 904,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #904 = INT_PTX_ATOM_LOAD_UMAX_GEN_32p64reg
    5726             :   { 905,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #905 = INT_PTX_ATOM_LOAD_UMAX_GEN_64_USE_Gp32imm
    5727             :   { 906,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #906 = INT_PTX_ATOM_LOAD_UMAX_GEN_64_USE_Gp32reg
    5728             :   { 907,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #907 = INT_PTX_ATOM_LOAD_UMAX_GEN_64_USE_Gp64imm
    5729             :   { 908,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #908 = INT_PTX_ATOM_LOAD_UMAX_GEN_64_USE_Gp64reg
    5730             :   { 909,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #909 = INT_PTX_ATOM_LOAD_UMAX_GEN_64p32imm
    5731             :   { 910,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #910 = INT_PTX_ATOM_LOAD_UMAX_GEN_64p32reg
    5732             :   { 911,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #911 = INT_PTX_ATOM_LOAD_UMAX_GEN_64p64imm
    5733             :   { 912,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #912 = INT_PTX_ATOM_LOAD_UMAX_GEN_64p64reg
    5734             :   { 913,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #913 = INT_PTX_ATOM_LOAD_UMAX_G_32p32imm
    5735             :   { 914,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #914 = INT_PTX_ATOM_LOAD_UMAX_G_32p32reg
    5736             :   { 915,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #915 = INT_PTX_ATOM_LOAD_UMAX_G_32p64imm
    5737             :   { 916,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #916 = INT_PTX_ATOM_LOAD_UMAX_G_32p64reg
    5738             :   { 917,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #917 = INT_PTX_ATOM_LOAD_UMAX_G_64p32imm
    5739             :   { 918,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #918 = INT_PTX_ATOM_LOAD_UMAX_G_64p32reg
    5740             :   { 919,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #919 = INT_PTX_ATOM_LOAD_UMAX_G_64p64imm
    5741             :   { 920,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #920 = INT_PTX_ATOM_LOAD_UMAX_G_64p64reg
    5742             :   { 921,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #921 = INT_PTX_ATOM_LOAD_UMAX_S_32p32imm
    5743             :   { 922,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #922 = INT_PTX_ATOM_LOAD_UMAX_S_32p32reg
    5744             :   { 923,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #923 = INT_PTX_ATOM_LOAD_UMAX_S_32p64imm
    5745             :   { 924,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #924 = INT_PTX_ATOM_LOAD_UMAX_S_32p64reg
    5746             :   { 925,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #925 = INT_PTX_ATOM_LOAD_UMAX_S_64p32imm
    5747             :   { 926,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #926 = INT_PTX_ATOM_LOAD_UMAX_S_64p32reg
    5748             :   { 927,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #927 = INT_PTX_ATOM_LOAD_UMAX_S_64p64imm
    5749             :   { 928,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #928 = INT_PTX_ATOM_LOAD_UMAX_S_64p64reg
    5750             :   { 929,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #929 = INT_PTX_ATOM_LOAD_UMIN_GEN_32_USE_Gp32imm
    5751             :   { 930,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #930 = INT_PTX_ATOM_LOAD_UMIN_GEN_32_USE_Gp32reg
    5752             :   { 931,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #931 = INT_PTX_ATOM_LOAD_UMIN_GEN_32_USE_Gp64imm
    5753             :   { 932,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #932 = INT_PTX_ATOM_LOAD_UMIN_GEN_32_USE_Gp64reg
    5754             :   { 933,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #933 = INT_PTX_ATOM_LOAD_UMIN_GEN_32p32imm
    5755             :   { 934,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #934 = INT_PTX_ATOM_LOAD_UMIN_GEN_32p32reg
    5756             :   { 935,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #935 = INT_PTX_ATOM_LOAD_UMIN_GEN_32p64imm
    5757             :   { 936,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #936 = INT_PTX_ATOM_LOAD_UMIN_GEN_32p64reg
    5758             :   { 937,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #937 = INT_PTX_ATOM_LOAD_UMIN_GEN_64_USE_Gp32imm
    5759             :   { 938,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #938 = INT_PTX_ATOM_LOAD_UMIN_GEN_64_USE_Gp32reg
    5760             :   { 939,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #939 = INT_PTX_ATOM_LOAD_UMIN_GEN_64_USE_Gp64imm
    5761             :   { 940,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #940 = INT_PTX_ATOM_LOAD_UMIN_GEN_64_USE_Gp64reg
    5762             :   { 941,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #941 = INT_PTX_ATOM_LOAD_UMIN_GEN_64p32imm
    5763             :   { 942,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #942 = INT_PTX_ATOM_LOAD_UMIN_GEN_64p32reg
    5764             :   { 943,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #943 = INT_PTX_ATOM_LOAD_UMIN_GEN_64p64imm
    5765             :   { 944,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #944 = INT_PTX_ATOM_LOAD_UMIN_GEN_64p64reg
    5766             :   { 945,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #945 = INT_PTX_ATOM_LOAD_UMIN_G_32p32imm
    5767             :   { 946,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #946 = INT_PTX_ATOM_LOAD_UMIN_G_32p32reg
    5768             :   { 947,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #947 = INT_PTX_ATOM_LOAD_UMIN_G_32p64imm
    5769             :   { 948,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #948 = INT_PTX_ATOM_LOAD_UMIN_G_32p64reg
    5770             :   { 949,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #949 = INT_PTX_ATOM_LOAD_UMIN_G_64p32imm
    5771             :   { 950,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #950 = INT_PTX_ATOM_LOAD_UMIN_G_64p32reg
    5772             :   { 951,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #951 = INT_PTX_ATOM_LOAD_UMIN_G_64p64imm
    5773             :   { 952,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #952 = INT_PTX_ATOM_LOAD_UMIN_G_64p64reg
    5774             :   { 953,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #953 = INT_PTX_ATOM_LOAD_UMIN_S_32p32imm
    5775             :   { 954,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #954 = INT_PTX_ATOM_LOAD_UMIN_S_32p32reg
    5776             :   { 955,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #955 = INT_PTX_ATOM_LOAD_UMIN_S_32p64imm
    5777             :   { 956,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #956 = INT_PTX_ATOM_LOAD_UMIN_S_32p64reg
    5778             :   { 957,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #957 = INT_PTX_ATOM_LOAD_UMIN_S_64p32imm
    5779             :   { 958,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #958 = INT_PTX_ATOM_LOAD_UMIN_S_64p32reg
    5780             :   { 959,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #959 = INT_PTX_ATOM_LOAD_UMIN_S_64p64imm
    5781             :   { 960,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #960 = INT_PTX_ATOM_LOAD_UMIN_S_64p64reg
    5782             :   { 961,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #961 = INT_PTX_ATOM_OR_GEN_32_USE_Gp32imm
    5783             :   { 962,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #962 = INT_PTX_ATOM_OR_GEN_32_USE_Gp32reg
    5784             :   { 963,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #963 = INT_PTX_ATOM_OR_GEN_32_USE_Gp64imm
    5785             :   { 964,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #964 = INT_PTX_ATOM_OR_GEN_32_USE_Gp64reg
    5786             :   { 965,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #965 = INT_PTX_ATOM_OR_GEN_32p32imm
    5787             :   { 966,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #966 = INT_PTX_ATOM_OR_GEN_32p32reg
    5788             :   { 967,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #967 = INT_PTX_ATOM_OR_GEN_32p64imm
    5789             :   { 968,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #968 = INT_PTX_ATOM_OR_GEN_32p64reg
    5790             :   { 969,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #969 = INT_PTX_ATOM_OR_GEN_64_USE_Gp32imm
    5791             :   { 970,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #970 = INT_PTX_ATOM_OR_GEN_64_USE_Gp32reg
    5792             :   { 971,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #971 = INT_PTX_ATOM_OR_GEN_64_USE_Gp64imm
    5793             :   { 972,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #972 = INT_PTX_ATOM_OR_GEN_64_USE_Gp64reg
    5794             :   { 973,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #973 = INT_PTX_ATOM_OR_GEN_64p32imm
    5795             :   { 974,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #974 = INT_PTX_ATOM_OR_GEN_64p32reg
    5796             :   { 975,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #975 = INT_PTX_ATOM_OR_GEN_64p64imm
    5797             :   { 976,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #976 = INT_PTX_ATOM_OR_GEN_64p64reg
    5798             :   { 977,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #977 = INT_PTX_ATOM_OR_G_32p32imm
    5799             :   { 978,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #978 = INT_PTX_ATOM_OR_G_32p32reg
    5800             :   { 979,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #979 = INT_PTX_ATOM_OR_G_32p64imm
    5801             :   { 980,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #980 = INT_PTX_ATOM_OR_G_32p64reg
    5802             :   { 981,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #981 = INT_PTX_ATOM_OR_G_64p32imm
    5803             :   { 982,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #982 = INT_PTX_ATOM_OR_G_64p32reg
    5804             :   { 983,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #983 = INT_PTX_ATOM_OR_G_64p64imm
    5805             :   { 984,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #984 = INT_PTX_ATOM_OR_G_64p64reg
    5806             :   { 985,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #985 = INT_PTX_ATOM_OR_S_32p32imm
    5807             :   { 986,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #986 = INT_PTX_ATOM_OR_S_32p32reg
    5808             :   { 987,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #987 = INT_PTX_ATOM_OR_S_32p64imm
    5809             :   { 988,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #988 = INT_PTX_ATOM_OR_S_32p64reg
    5810             :   { 989,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #989 = INT_PTX_ATOM_OR_S_64p32imm
    5811             :   { 990,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #990 = INT_PTX_ATOM_OR_S_64p32reg
    5812             :   { 991,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #991 = INT_PTX_ATOM_OR_S_64p64imm
    5813             :   { 992,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #992 = INT_PTX_ATOM_OR_S_64p64reg
    5814             :   { 993,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #993 = INT_PTX_ATOM_SUB_GEN_32_USE_Gp32reg
    5815             :   { 994,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #994 = INT_PTX_ATOM_SUB_GEN_32_USE_Gp64reg
    5816             :   { 995,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #995 = INT_PTX_ATOM_SUB_GEN_32p32reg
    5817             :   { 996,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #996 = INT_PTX_ATOM_SUB_GEN_32p64reg
    5818             :   { 997,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #997 = INT_PTX_ATOM_SUB_GEN_64_USE_Gp32reg
    5819             :   { 998,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #998 = INT_PTX_ATOM_SUB_GEN_64_USE_Gp64reg
    5820             :   { 999,        3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #999 = INT_PTX_ATOM_SUB_GEN_64p32reg
    5821             :   { 1000,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1000 = INT_PTX_ATOM_SUB_GEN_64p64reg
    5822             :   { 1001,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1001 = INT_PTX_ATOM_SUB_G_32p32reg
    5823             :   { 1002,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #1002 = INT_PTX_ATOM_SUB_G_32p64reg
    5824             :   { 1003,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #1003 = INT_PTX_ATOM_SUB_G_64p32reg
    5825             :   { 1004,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1004 = INT_PTX_ATOM_SUB_G_64p64reg
    5826             :   { 1005,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1005 = INT_PTX_ATOM_SUB_S_32p32reg
    5827             :   { 1006,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #1006 = INT_PTX_ATOM_SUB_S_32p64reg
    5828             :   { 1007,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #1007 = INT_PTX_ATOM_SUB_S_64p32reg
    5829             :   { 1008,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1008 = INT_PTX_ATOM_SUB_S_64p64reg
    5830             :   { 1009,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1009 = INT_PTX_ATOM_SWAP_GEN_32_USE_Gp32imm
    5831             :   { 1010,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1010 = INT_PTX_ATOM_SWAP_GEN_32_USE_Gp32reg
    5832             :   { 1011,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #1011 = INT_PTX_ATOM_SWAP_GEN_32_USE_Gp64imm
    5833             :   { 1012,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #1012 = INT_PTX_ATOM_SWAP_GEN_32_USE_Gp64reg
    5834             :   { 1013,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1013 = INT_PTX_ATOM_SWAP_GEN_32p32imm
    5835             :   { 1014,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1014 = INT_PTX_ATOM_SWAP_GEN_32p32reg
    5836             :   { 1015,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #1015 = INT_PTX_ATOM_SWAP_GEN_32p64imm
    5837             :   { 1016,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #1016 = INT_PTX_ATOM_SWAP_GEN_32p64reg
    5838             :   { 1017,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #1017 = INT_PTX_ATOM_SWAP_GEN_64_USE_Gp32imm
    5839             :   { 1018,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #1018 = INT_PTX_ATOM_SWAP_GEN_64_USE_Gp32reg
    5840             :   { 1019,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1019 = INT_PTX_ATOM_SWAP_GEN_64_USE_Gp64imm
    5841             :   { 1020,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1020 = INT_PTX_ATOM_SWAP_GEN_64_USE_Gp64reg
    5842             :   { 1021,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #1021 = INT_PTX_ATOM_SWAP_GEN_64p32imm
    5843             :   { 1022,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #1022 = INT_PTX_ATOM_SWAP_GEN_64p32reg
    5844             :   { 1023,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1023 = INT_PTX_ATOM_SWAP_GEN_64p64imm
    5845             :   { 1024,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1024 = INT_PTX_ATOM_SWAP_GEN_64p64reg
    5846             :   { 1025,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1025 = INT_PTX_ATOM_SWAP_G_32p32imm
    5847             :   { 1026,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1026 = INT_PTX_ATOM_SWAP_G_32p32reg
    5848             :   { 1027,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #1027 = INT_PTX_ATOM_SWAP_G_32p64imm
    5849             :   { 1028,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #1028 = INT_PTX_ATOM_SWAP_G_32p64reg
    5850             :   { 1029,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #1029 = INT_PTX_ATOM_SWAP_G_64p32imm
    5851             :   { 1030,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #1030 = INT_PTX_ATOM_SWAP_G_64p32reg
    5852             :   { 1031,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1031 = INT_PTX_ATOM_SWAP_G_64p64imm
    5853             :   { 1032,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1032 = INT_PTX_ATOM_SWAP_G_64p64reg
    5854             :   { 1033,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1033 = INT_PTX_ATOM_SWAP_S_32p32imm
    5855             :   { 1034,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1034 = INT_PTX_ATOM_SWAP_S_32p32reg
    5856             :   { 1035,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #1035 = INT_PTX_ATOM_SWAP_S_32p64imm
    5857             :   { 1036,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #1036 = INT_PTX_ATOM_SWAP_S_32p64reg
    5858             :   { 1037,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #1037 = INT_PTX_ATOM_SWAP_S_64p32imm
    5859             :   { 1038,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #1038 = INT_PTX_ATOM_SWAP_S_64p32reg
    5860             :   { 1039,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1039 = INT_PTX_ATOM_SWAP_S_64p64imm
    5861             :   { 1040,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1040 = INT_PTX_ATOM_SWAP_S_64p64reg
    5862             :   { 1041,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1041 = INT_PTX_ATOM_XOR_GEN_32_USE_Gp32imm
    5863             :   { 1042,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1042 = INT_PTX_ATOM_XOR_GEN_32_USE_Gp32reg
    5864             :   { 1043,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #1043 = INT_PTX_ATOM_XOR_GEN_32_USE_Gp64imm
    5865             :   { 1044,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #1044 = INT_PTX_ATOM_XOR_GEN_32_USE_Gp64reg
    5866             :   { 1045,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1045 = INT_PTX_ATOM_XOR_GEN_32p32imm
    5867             :   { 1046,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1046 = INT_PTX_ATOM_XOR_GEN_32p32reg
    5868             :   { 1047,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #1047 = INT_PTX_ATOM_XOR_GEN_32p64imm
    5869             :   { 1048,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #1048 = INT_PTX_ATOM_XOR_GEN_32p64reg
    5870             :   { 1049,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #1049 = INT_PTX_ATOM_XOR_GEN_64_USE_Gp32imm
    5871             :   { 1050,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #1050 = INT_PTX_ATOM_XOR_GEN_64_USE_Gp32reg
    5872             :   { 1051,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1051 = INT_PTX_ATOM_XOR_GEN_64_USE_Gp64imm
    5873             :   { 1052,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1052 = INT_PTX_ATOM_XOR_GEN_64_USE_Gp64reg
    5874             :   { 1053,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #1053 = INT_PTX_ATOM_XOR_GEN_64p32imm
    5875             :   { 1054,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #1054 = INT_PTX_ATOM_XOR_GEN_64p32reg
    5876             :   { 1055,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1055 = INT_PTX_ATOM_XOR_GEN_64p64imm
    5877             :   { 1056,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1056 = INT_PTX_ATOM_XOR_GEN_64p64reg
    5878             :   { 1057,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1057 = INT_PTX_ATOM_XOR_G_32p32imm
    5879             :   { 1058,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1058 = INT_PTX_ATOM_XOR_G_32p32reg
    5880             :   { 1059,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #1059 = INT_PTX_ATOM_XOR_G_32p64imm
    5881             :   { 1060,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #1060 = INT_PTX_ATOM_XOR_G_32p64reg
    5882             :   { 1061,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #1061 = INT_PTX_ATOM_XOR_G_64p32imm
    5883             :   { 1062,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #1062 = INT_PTX_ATOM_XOR_G_64p32reg
    5884             :   { 1063,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1063 = INT_PTX_ATOM_XOR_G_64p64imm
    5885             :   { 1064,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1064 = INT_PTX_ATOM_XOR_G_64p64reg
    5886             :   { 1065,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #1065 = INT_PTX_ATOM_XOR_S_32p32imm
    5887             :   { 1066,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1066 = INT_PTX_ATOM_XOR_S_32p32reg
    5888             :   { 1067,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #1067 = INT_PTX_ATOM_XOR_S_32p64imm
    5889             :   { 1068,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #1068 = INT_PTX_ATOM_XOR_S_32p64reg
    5890             :   { 1069,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #1069 = INT_PTX_ATOM_XOR_S_64p32imm
    5891             :   { 1070,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #1070 = INT_PTX_ATOM_XOR_S_64p32reg
    5892             :   { 1071,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1071 = INT_PTX_ATOM_XOR_S_64p64imm
    5893             :   { 1072,       3,      1,      0,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1072 = INT_PTX_ATOM_XOR_S_64p64reg
    5894             :   { 1073,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr },  // Inst #1073 = INT_PTX_LDG_GLOBAL_f16areg
    5895             :   { 1074,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr },  // Inst #1074 = INT_PTX_LDG_GLOBAL_f16areg64
    5896             :   { 1075,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr },  // Inst #1075 = INT_PTX_LDG_GLOBAL_f16ari
    5897             :   { 1076,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr },  // Inst #1076 = INT_PTX_LDG_GLOBAL_f16ari64
    5898             :   { 1077,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo170, -1 ,nullptr },  // Inst #1077 = INT_PTX_LDG_GLOBAL_f16avar
    5899             :   { 1078,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #1078 = INT_PTX_LDG_GLOBAL_f16x2areg
    5900             :   { 1079,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr },  // Inst #1079 = INT_PTX_LDG_GLOBAL_f16x2areg64
    5901             :   { 1080,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1080 = INT_PTX_LDG_GLOBAL_f16x2ari
    5902             :   { 1081,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1081 = INT_PTX_LDG_GLOBAL_f16x2ari64
    5903             :   { 1082,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr },  // Inst #1082 = INT_PTX_LDG_GLOBAL_f16x2avar
    5904             :   { 1083,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #1083 = INT_PTX_LDG_GLOBAL_f32areg
    5905             :   { 1084,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1084 = INT_PTX_LDG_GLOBAL_f32areg64
    5906             :   { 1085,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr },  // Inst #1085 = INT_PTX_LDG_GLOBAL_f32ari
    5907             :   { 1086,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr },  // Inst #1086 = INT_PTX_LDG_GLOBAL_f32ari64
    5908             :   { 1087,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr },  // Inst #1087 = INT_PTX_LDG_GLOBAL_f32avar
    5909             :   { 1088,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo179, -1 ,nullptr },  // Inst #1088 = INT_PTX_LDG_GLOBAL_f64areg
    5910             :   { 1089,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #1089 = INT_PTX_LDG_GLOBAL_f64areg64
    5911             :   { 1090,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr },  // Inst #1090 = INT_PTX_LDG_GLOBAL_f64ari
    5912             :   { 1091,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr },  // Inst #1091 = INT_PTX_LDG_GLOBAL_f64ari64
    5913             :   { 1092,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr },  // Inst #1092 = INT_PTX_LDG_GLOBAL_f64avar
    5914             :   { 1093,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1093 = INT_PTX_LDG_GLOBAL_i16areg
    5915             :   { 1094,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr },  // Inst #1094 = INT_PTX_LDG_GLOBAL_i16areg64
    5916             :   { 1095,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr },  // Inst #1095 = INT_PTX_LDG_GLOBAL_i16ari
    5917             :   { 1096,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr },  // Inst #1096 = INT_PTX_LDG_GLOBAL_i16ari64
    5918             :   { 1097,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr },  // Inst #1097 = INT_PTX_LDG_GLOBAL_i16avar
    5919             :   { 1098,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #1098 = INT_PTX_LDG_GLOBAL_i32areg
    5920             :   { 1099,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #1099 = INT_PTX_LDG_GLOBAL_i32areg64
    5921             :   { 1100,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo188, -1 ,nullptr },  // Inst #1100 = INT_PTX_LDG_GLOBAL_i32ari
    5922             :   { 1101,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr },  // Inst #1101 = INT_PTX_LDG_GLOBAL_i32ari64
    5923             :   { 1102,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr },  // Inst #1102 = INT_PTX_LDG_GLOBAL_i32avar
    5924             :   { 1103,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr },  // Inst #1103 = INT_PTX_LDG_GLOBAL_i64areg
    5925             :   { 1104,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #1104 = INT_PTX_LDG_GLOBAL_i64areg64
    5926             :   { 1105,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1105 = INT_PTX_LDG_GLOBAL_i64ari
    5927             :   { 1106,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1106 = INT_PTX_LDG_GLOBAL_i64ari64
    5928             :   { 1107,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #1107 = INT_PTX_LDG_GLOBAL_i64avar
    5929             :   { 1108,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1108 = INT_PTX_LDG_GLOBAL_i8areg
    5930             :   { 1109,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr },  // Inst #1109 = INT_PTX_LDG_GLOBAL_i8areg64
    5931             :   { 1110,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr },  // Inst #1110 = INT_PTX_LDG_GLOBAL_i8ari
    5932             :   { 1111,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr },  // Inst #1111 = INT_PTX_LDG_GLOBAL_i8ari64
    5933             :   { 1112,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr },  // Inst #1112 = INT_PTX_LDG_GLOBAL_i8avar
    5934             :   { 1113,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #1113 = INT_PTX_LDG_GLOBAL_p32areg
    5935             :   { 1114,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #1114 = INT_PTX_LDG_GLOBAL_p32areg64
    5936             :   { 1115,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo188, -1 ,nullptr },  // Inst #1115 = INT_PTX_LDG_GLOBAL_p32ari
    5937             :   { 1116,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr },  // Inst #1116 = INT_PTX_LDG_GLOBAL_p32ari64
    5938             :   { 1117,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr },  // Inst #1117 = INT_PTX_LDG_GLOBAL_p32avar
    5939             :   { 1118,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr },  // Inst #1118 = INT_PTX_LDG_GLOBAL_p64areg
    5940             :   { 1119,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #1119 = INT_PTX_LDG_GLOBAL_p64areg64
    5941             :   { 1120,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1120 = INT_PTX_LDG_GLOBAL_p64ari
    5942             :   { 1121,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1121 = INT_PTX_LDG_GLOBAL_p64ari64
    5943             :   { 1122,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #1122 = INT_PTX_LDG_GLOBAL_p64avar
    5944             :   { 1123,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1123 = INT_PTX_LDG_G_v2f16_ELE_areg32
    5945             :   { 1124,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr },  // Inst #1124 = INT_PTX_LDG_G_v2f16_ELE_areg64
    5946             :   { 1125,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr },  // Inst #1125 = INT_PTX_LDG_G_v2f16_ELE_ari32
    5947             :   { 1126,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr },  // Inst #1126 = INT_PTX_LDG_G_v2f16_ELE_ari64
    5948             :   { 1127,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #1127 = INT_PTX_LDG_G_v2f16_ELE_avar
    5949             :   { 1128,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #1128 = INT_PTX_LDG_G_v2f16x2_ELE_areg32
    5950             :   { 1129,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr },  // Inst #1129 = INT_PTX_LDG_G_v2f16x2_ELE_areg64
    5951             :   { 1130,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr },  // Inst #1130 = INT_PTX_LDG_G_v2f16x2_ELE_ari32
    5952             :   { 1131,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr },  // Inst #1131 = INT_PTX_LDG_G_v2f16x2_ELE_ari64
    5953             :   { 1132,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo203, -1 ,nullptr },  // Inst #1132 = INT_PTX_LDG_G_v2f16x2_ELE_avar
    5954             :   { 1133,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr },  // Inst #1133 = INT_PTX_LDG_G_v2f32_ELE_areg32
    5955             :   { 1134,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr },  // Inst #1134 = INT_PTX_LDG_G_v2f32_ELE_areg64
    5956             :   { 1135,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr },  // Inst #1135 = INT_PTX_LDG_G_v2f32_ELE_ari32
    5957             :   { 1136,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr },  // Inst #1136 = INT_PTX_LDG_G_v2f32_ELE_ari64
    5958             :   { 1137,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #1137 = INT_PTX_LDG_G_v2f32_ELE_avar
    5959             :   { 1138,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr },  // Inst #1138 = INT_PTX_LDG_G_v2f64_ELE_areg32
    5960             :   { 1139,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr },  // Inst #1139 = INT_PTX_LDG_G_v2f64_ELE_areg64
    5961             :   { 1140,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1140 = INT_PTX_LDG_G_v2f64_ELE_ari32
    5962             :   { 1141,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1141 = INT_PTX_LDG_G_v2f64_ELE_ari64
    5963             :   { 1142,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr },  // Inst #1142 = INT_PTX_LDG_G_v2f64_ELE_avar
    5964             :   { 1143,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr },  // Inst #1143 = INT_PTX_LDG_G_v2i16_ELE_areg32
    5965             :   { 1144,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo212, -1 ,nullptr },  // Inst #1144 = INT_PTX_LDG_G_v2i16_ELE_areg64
    5966             :   { 1145,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo213, -1 ,nullptr },  // Inst #1145 = INT_PTX_LDG_G_v2i16_ELE_ari32
    5967             :   { 1146,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo214, -1 ,nullptr },  // Inst #1146 = INT_PTX_LDG_G_v2i16_ELE_ari64
    5968             :   { 1147,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #1147 = INT_PTX_LDG_G_v2i16_ELE_avar
    5969             :   { 1148,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1148 = INT_PTX_LDG_G_v2i32_ELE_areg32
    5970             :   { 1149,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr },  // Inst #1149 = INT_PTX_LDG_G_v2i32_ELE_areg64
    5971             :   { 1150,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo215, -1 ,nullptr },  // Inst #1150 = INT_PTX_LDG_G_v2i32_ELE_ari32
    5972             :   { 1151,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr },  // Inst #1151 = INT_PTX_LDG_G_v2i32_ELE_ari64
    5973             :   { 1152,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr },  // Inst #1152 = INT_PTX_LDG_G_v2i32_ELE_avar
    5974             :   { 1153,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr },  // Inst #1153 = INT_PTX_LDG_G_v2i64_ELE_areg32
    5975             :   { 1154,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #1154 = INT_PTX_LDG_G_v2i64_ELE_areg64
    5976             :   { 1155,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr },  // Inst #1155 = INT_PTX_LDG_G_v2i64_ELE_ari32
    5977             :   { 1156,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo219, -1 ,nullptr },  // Inst #1156 = INT_PTX_LDG_G_v2i64_ELE_ari64
    5978             :   { 1157,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr },  // Inst #1157 = INT_PTX_LDG_G_v2i64_ELE_avar
    5979             :   { 1158,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr },  // Inst #1158 = INT_PTX_LDG_G_v2i8_ELE_areg32
    5980             :   { 1159,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo212, -1 ,nullptr },  // Inst #1159 = INT_PTX_LDG_G_v2i8_ELE_areg64
    5981             :   { 1160,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo213, -1 ,nullptr },  // Inst #1160 = INT_PTX_LDG_G_v2i8_ELE_ari32
    5982             :   { 1161,       4,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo214, -1 ,nullptr },  // Inst #1161 = INT_PTX_LDG_G_v2i8_ELE_ari64
    5983             :   { 1162,       3,      2,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #1162 = INT_PTX_LDG_G_v2i8_ELE_avar
    5984             :   { 1163,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo220, -1 ,nullptr },  // Inst #1163 = INT_PTX_LDG_G_v4f16_ELE_areg32
    5985             :   { 1164,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr },  // Inst #1164 = INT_PTX_LDG_G_v4f16_ELE_areg64
    5986             :   { 1165,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr },  // Inst #1165 = INT_PTX_LDG_G_v4f16_ELE_ari32
    5987             :   { 1166,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr },  // Inst #1166 = INT_PTX_LDG_G_v4f16_ELE_ari64
    5988             :   { 1167,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr },  // Inst #1167 = INT_PTX_LDG_G_v4f16_ELE_avar
    5989             :   { 1168,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr },  // Inst #1168 = INT_PTX_LDG_G_v4f16x2_ELE_areg32
    5990             :   { 1169,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr },  // Inst #1169 = INT_PTX_LDG_G_v4f16x2_ELE_areg64
    5991             :   { 1170,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr },  // Inst #1170 = INT_PTX_LDG_G_v4f16x2_ELE_ari32
    5992             :   { 1171,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr },  // Inst #1171 = INT_PTX_LDG_G_v4f16x2_ELE_ari64
    5993             :   { 1172,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr },  // Inst #1172 = INT_PTX_LDG_G_v4f16x2_ELE_avar
    5994             :   { 1173,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr },  // Inst #1173 = INT_PTX_LDG_G_v4f32_ELE_areg32
    5995             :   { 1174,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr },  // Inst #1174 = INT_PTX_LDG_G_v4f32_ELE_areg64
    5996             :   { 1175,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo232, -1 ,nullptr },  // Inst #1175 = INT_PTX_LDG_G_v4f32_ELE_ari32
    5997             :   { 1176,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr },  // Inst #1176 = INT_PTX_LDG_G_v4f32_ELE_ari64
    5998             :   { 1177,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr },  // Inst #1177 = INT_PTX_LDG_G_v4f32_ELE_avar
    5999             :   { 1178,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo235, -1 ,nullptr },  // Inst #1178 = INT_PTX_LDG_G_v4i16_ELE_areg32
    6000             :   { 1179,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #1179 = INT_PTX_LDG_G_v4i16_ELE_areg64
    6001             :   { 1180,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo236, -1 ,nullptr },  // Inst #1180 = INT_PTX_LDG_G_v4i16_ELE_ari32
    6002             :   { 1181,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo237, -1 ,nullptr },  // Inst #1181 = INT_PTX_LDG_G_v4i16_ELE_ari64
    6003             :   { 1182,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr },  // Inst #1182 = INT_PTX_LDG_G_v4i16_ELE_avar
    6004             :   { 1183,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr },  // Inst #1183 = INT_PTX_LDG_G_v4i32_ELE_areg32
    6005             :   { 1184,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr },  // Inst #1184 = INT_PTX_LDG_G_v4i32_ELE_areg64
    6006             :   { 1185,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr },  // Inst #1185 = INT_PTX_LDG_G_v4i32_ELE_ari32
    6007             :   { 1186,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr },  // Inst #1186 = INT_PTX_LDG_G_v4i32_ELE_ari64
    6008             :   { 1187,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr },  // Inst #1187 = INT_PTX_LDG_G_v4i32_ELE_avar
    6009             :   { 1188,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo235, -1 ,nullptr },  // Inst #1188 = INT_PTX_LDG_G_v4i8_ELE_areg32
    6010             :   { 1189,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #1189 = INT_PTX_LDG_G_v4i8_ELE_areg64
    6011             :   { 1190,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo236, -1 ,nullptr },  // Inst #1190 = INT_PTX_LDG_G_v4i8_ELE_ari32
    6012             :   { 1191,       6,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo237, -1 ,nullptr },  // Inst #1191 = INT_PTX_LDG_G_v4i8_ELE_ari64
    6013             :   { 1192,       5,      4,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr },  // Inst #1192 = INT_PTX_LDG_G_v4i8_ELE_avar
    6014             :   { 1193,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr },  // Inst #1193 = INT_PTX_LDU_GLOBAL_f16areg
    6015             :   { 1194,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr },  // Inst #1194 = INT_PTX_LDU_GLOBAL_f16areg64
    6016             :   { 1195,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr },  // Inst #1195 = INT_PTX_LDU_GLOBAL_f16ari
    6017             :   { 1196,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr },  // Inst #1196 = INT_PTX_LDU_GLOBAL_f16ari64
    6018             :   { 1197,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo170, -1 ,nullptr },  // Inst #1197 = INT_PTX_LDU_GLOBAL_f16avar
    6019             :   { 1198,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #1198 = INT_PTX_LDU_GLOBAL_f16x2areg
    6020             :   { 1199,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr },  // Inst #1199 = INT_PTX_LDU_GLOBAL_f16x2areg64
    6021             :   { 1200,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1200 = INT_PTX_LDU_GLOBAL_f16x2ari
    6022             :   { 1201,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1201 = INT_PTX_LDU_GLOBAL_f16x2ari64
    6023             :   { 1202,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr },  // Inst #1202 = INT_PTX_LDU_GLOBAL_f16x2avar
    6024             :   { 1203,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #1203 = INT_PTX_LDU_GLOBAL_f32areg
    6025             :   { 1204,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1204 = INT_PTX_LDU_GLOBAL_f32areg64
    6026             :   { 1205,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr },  // Inst #1205 = INT_PTX_LDU_GLOBAL_f32ari
    6027             :   { 1206,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr },  // Inst #1206 = INT_PTX_LDU_GLOBAL_f32ari64
    6028             :   { 1207,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr },  // Inst #1207 = INT_PTX_LDU_GLOBAL_f32avar
    6029             :   { 1208,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo179, -1 ,nullptr },  // Inst #1208 = INT_PTX_LDU_GLOBAL_f64areg
    6030             :   { 1209,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #1209 = INT_PTX_LDU_GLOBAL_f64areg64
    6031             :   { 1210,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr },  // Inst #1210 = INT_PTX_LDU_GLOBAL_f64ari
    6032             :   { 1211,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr },  // Inst #1211 = INT_PTX_LDU_GLOBAL_f64ari64
    6033             :   { 1212,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr },  // Inst #1212 = INT_PTX_LDU_GLOBAL_f64avar
    6034             :   { 1213,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1213 = INT_PTX_LDU_GLOBAL_i16areg
    6035             :   { 1214,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr },  // Inst #1214 = INT_PTX_LDU_GLOBAL_i16areg64
    6036             :   { 1215,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr },  // Inst #1215 = INT_PTX_LDU_GLOBAL_i16ari
    6037             :   { 1216,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr },  // Inst #1216 = INT_PTX_LDU_GLOBAL_i16ari64
    6038             :   { 1217,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr },  // Inst #1217 = INT_PTX_LDU_GLOBAL_i16avar
    6039             :   { 1218,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #1218 = INT_PTX_LDU_GLOBAL_i32areg
    6040             :   { 1219,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #1219 = INT_PTX_LDU_GLOBAL_i32areg64
    6041             :   { 1220,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo188, -1 ,nullptr },  // Inst #1220 = INT_PTX_LDU_GLOBAL_i32ari
    6042             :   { 1221,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr },  // Inst #1221 = INT_PTX_LDU_GLOBAL_i32ari64
    6043             :   { 1222,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr },  // Inst #1222 = INT_PTX_LDU_GLOBAL_i32avar
    6044             :   { 1223,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr },  // Inst #1223 = INT_PTX_LDU_GLOBAL_i64areg
    6045             :   { 1224,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #1224 = INT_PTX_LDU_GLOBAL_i64areg64
    6046             :   { 1225,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1225 = INT_PTX_LDU_GLOBAL_i64ari
    6047             :   { 1226,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1226 = INT_PTX_LDU_GLOBAL_i64ari64
    6048             :   { 1227,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #1227 = INT_PTX_LDU_GLOBAL_i64avar
    6049             :   { 1228,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1228 = INT_PTX_LDU_GLOBAL_i8areg
    6050             :   { 1229,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr },  // Inst #1229 = INT_PTX_LDU_GLOBAL_i8areg64
    6051             :   { 1230,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr },  // Inst #1230 = INT_PTX_LDU_GLOBAL_i8ari
    6052             :   { 1231,       3,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr },  // Inst #1231 = INT_PTX_LDU_GLOBAL_i8ari64
    6053             :   { 1232,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr },  // Inst #1232 = INT_PTX_LDU_GLOBAL_i8avar
    6054             :   { 1233,       2,      1,      0,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #1233 = INT_PTX_LDU_GLOBAL_p32areg