LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/NVPTX - NVPTXGenSubtargetInfo.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 35 43 81.4 %
Date: 2018-07-13 00:08:38 Functions: 4 11 36.4 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Subtarget Enumeration Source Fragment                                      *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : 
      10             : #ifdef GET_SUBTARGETINFO_ENUM
      11             : #undef GET_SUBTARGETINFO_ENUM
      12             : 
      13             : namespace llvm {
      14             : namespace NVPTX {
      15             : enum {
      16             :   PTX32 = 0,
      17             :   PTX40 = 1,
      18             :   PTX41 = 2,
      19             :   PTX42 = 3,
      20             :   PTX43 = 4,
      21             :   PTX50 = 5,
      22             :   PTX60 = 6,
      23             :   PTX61 = 7,
      24             :   SM20 = 8,
      25             :   SM21 = 9,
      26             :   SM30 = 10,
      27             :   SM32 = 11,
      28             :   SM35 = 12,
      29             :   SM37 = 13,
      30             :   SM50 = 14,
      31             :   SM52 = 15,
      32             :   SM53 = 16,
      33             :   SM60 = 17,
      34             :   SM61 = 18,
      35             :   SM62 = 19,
      36             :   SM70 = 20,
      37             :   SM72 = 21,
      38             : };
      39             : } // end namespace NVPTX
      40             : } // end namespace llvm
      41             : 
      42             : #endif // GET_SUBTARGETINFO_ENUM
      43             : 
      44             : 
      45             : #ifdef GET_SUBTARGETINFO_MC_DESC
      46             : #undef GET_SUBTARGETINFO_MC_DESC
      47             : 
      48             : namespace llvm {
      49             : // Sorted (by key) array of values for CPU features.
      50             : extern const llvm::SubtargetFeatureKV NVPTXFeatureKV[] = {
      51             :   { "ptx32", "Use PTX version 3.2", { NVPTX::PTX32 }, { } },
      52             :   { "ptx40", "Use PTX version 4.0", { NVPTX::PTX40 }, { } },
      53             :   { "ptx41", "Use PTX version 4.1", { NVPTX::PTX41 }, { } },
      54             :   { "ptx42", "Use PTX version 4.2", { NVPTX::PTX42 }, { } },
      55             :   { "ptx43", "Use PTX version 4.3", { NVPTX::PTX43 }, { } },
      56             :   { "ptx50", "Use PTX version 5.0", { NVPTX::PTX50 }, { } },
      57             :   { "ptx60", "Use PTX version 6.0", { NVPTX::PTX60 }, { } },
      58             :   { "ptx61", "Use PTX version 6.1", { NVPTX::PTX61 }, { } },
      59             :   { "sm_20", "Target SM 2.0", { NVPTX::SM20 }, { } },
      60             :   { "sm_21", "Target SM 2.1", { NVPTX::SM21 }, { } },
      61             :   { "sm_30", "Target SM 3.0", { NVPTX::SM30 }, { } },
      62             :   { "sm_32", "Target SM 3.2", { NVPTX::SM32 }, { } },
      63             :   { "sm_35", "Target SM 3.5", { NVPTX::SM35 }, { } },
      64             :   { "sm_37", "Target SM 3.7", { NVPTX::SM37 }, { } },
      65             :   { "sm_50", "Target SM 5.0", { NVPTX::SM50 }, { } },
      66             :   { "sm_52", "Target SM 5.2", { NVPTX::SM52 }, { } },
      67             :   { "sm_53", "Target SM 5.3", { NVPTX::SM53 }, { } },
      68             :   { "sm_60", "Target SM 6.0", { NVPTX::SM60 }, { } },
      69             :   { "sm_61", "Target SM 6.1", { NVPTX::SM61 }, { } },
      70             :   { "sm_62", "Target SM 6.2", { NVPTX::SM62 }, { } },
      71             :   { "sm_70", "Target SM 7.0", { NVPTX::SM70 }, { } },
      72             :   { "sm_72", "Target SM 7.2", { NVPTX::SM72 }, { } },
      73       99743 : };
      74             : 
      75             : // Sorted (by key) array of values for CPU subtype.
      76             : extern const llvm::SubtargetFeatureKV NVPTXSubTypeKV[] = {
      77             :   { "sm_20", "Select the sm_20 processor", { NVPTX::SM20 }, { } },
      78             :   { "sm_21", "Select the sm_21 processor", { NVPTX::SM21 }, { } },
      79             :   { "sm_30", "Select the sm_30 processor", { NVPTX::SM30 }, { } },
      80             :   { "sm_32", "Select the sm_32 processor", { NVPTX::SM32, NVPTX::PTX40 }, { } },
      81             :   { "sm_35", "Select the sm_35 processor", { NVPTX::SM35 }, { } },
      82             :   { "sm_37", "Select the sm_37 processor", { NVPTX::SM37, NVPTX::PTX41 }, { } },
      83             :   { "sm_50", "Select the sm_50 processor", { NVPTX::SM50, NVPTX::PTX40 }, { } },
      84             :   { "sm_52", "Select the sm_52 processor", { NVPTX::SM52, NVPTX::PTX41 }, { } },
      85             :   { "sm_53", "Select the sm_53 processor", { NVPTX::SM53, NVPTX::PTX42 }, { } },
      86             :   { "sm_60", "Select the sm_60 processor", { NVPTX::SM60, NVPTX::PTX50 }, { } },
      87             :   { "sm_61", "Select the sm_61 processor", { NVPTX::SM61, NVPTX::PTX50 }, { } },
      88             :   { "sm_62", "Select the sm_62 processor", { NVPTX::SM62, NVPTX::PTX50 }, { } },
      89             :   { "sm_70", "Select the sm_70 processor", { NVPTX::SM70, NVPTX::PTX60 }, { } },
      90             :   { "sm_72", "Select the sm_72 processor", { NVPTX::SM72, NVPTX::PTX61 }, { } },
      91       99743 : };
      92             : 
      93             : #ifdef DBGFIELD
      94             : #error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
      95             : #endif
      96             : #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
      97             : #define DBGFIELD(x) x,
      98             : #else
      99             : #define DBGFIELD(x)
     100             : #endif
     101             : 
     102             : // ===============================================================
     103             : // Data tables for the new per-operand machine model.
     104             : 
     105             : // {ProcResourceIdx, Cycles}
     106             : extern const llvm::MCWriteProcResEntry NVPTXWriteProcResTable[] = {
     107             :   { 0,  0}, // Invalid
     108             : }; // NVPTXWriteProcResTable
     109             : 
     110             : // {Cycles, WriteResourceID}
     111             : extern const llvm::MCWriteLatencyEntry NVPTXWriteLatencyTable[] = {
     112             :   { 0,  0}, // Invalid
     113             : }; // NVPTXWriteLatencyTable
     114             : 
     115             : // {UseIdx, WriteResourceID, Cycles}
     116             : extern const llvm::MCReadAdvanceEntry NVPTXReadAdvanceTable[] = {
     117             :   {0,  0,  0}, // Invalid
     118             : }; // NVPTXReadAdvanceTable
     119             : 
     120             : static const llvm::MCSchedModel NoSchedModel = {
     121             :   MCSchedModel::DefaultIssueWidth,
     122             :   MCSchedModel::DefaultMicroOpBufferSize,
     123             :   MCSchedModel::DefaultLoopMicroOpBufferSize,
     124             :   MCSchedModel::DefaultLoadLatency,
     125             :   MCSchedModel::DefaultHighLatency,
     126             :   MCSchedModel::DefaultMispredictPenalty,
     127             :   false, // PostRAScheduler
     128             :   false, // CompleteModel
     129             :   0, // Processor ID
     130             :   nullptr, nullptr, 0, 0, // No instruction-level machine model.
     131             :   nullptr, // No Itinerary
     132             :   nullptr // No extra processor descriptor
     133             : };
     134             : 
     135             : // Sorted (by key) array of itineraries for CPU subtype.
     136             : extern const llvm::SubtargetInfoKV NVPTXProcSchedKV[] = {
     137             :   { "sm_20", (const void *)&NoSchedModel },
     138             :   { "sm_21", (const void *)&NoSchedModel },
     139             :   { "sm_30", (const void *)&NoSchedModel },
     140             :   { "sm_32", (const void *)&NoSchedModel },
     141             :   { "sm_35", (const void *)&NoSchedModel },
     142             :   { "sm_37", (const void *)&NoSchedModel },
     143             :   { "sm_50", (const void *)&NoSchedModel },
     144             :   { "sm_52", (const void *)&NoSchedModel },
     145             :   { "sm_53", (const void *)&NoSchedModel },
     146             :   { "sm_60", (const void *)&NoSchedModel },
     147             :   { "sm_61", (const void *)&NoSchedModel },
     148             :   { "sm_62", (const void *)&NoSchedModel },
     149             :   { "sm_70", (const void *)&NoSchedModel },
     150             :   { "sm_72", (const void *)&NoSchedModel },
     151             : };
     152             : 
     153             : #undef DBGFIELD
     154             : namespace NVPTX_MC {
     155           0 : unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
     156             :     const MCInst *MI, unsigned CPUID) {
     157             :   // Don't know how to resolve this scheduling class.
     158           0 :   return 0;
     159             : }
     160             : } // end of namespace NVPTX_MC
     161             : 
     162         387 : struct NVPTXGenMCSubtargetInfo : public MCSubtargetInfo {
     163             :   NVPTXGenMCSubtargetInfo(const Triple &TT, 
     164             :     StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
     165             :     ArrayRef<SubtargetFeatureKV> PD,
     166             :     const SubtargetInfoKV *ProcSched,
     167             :     const MCWriteProcResEntry *WPR,
     168             :     const MCWriteLatencyEntry *WL,
     169             :     const MCReadAdvanceEntry *RA, const InstrStage *IS,
     170         394 :     const unsigned *OC, const unsigned *FP) :
     171             :       MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched,
     172         394 :                       WPR, WL, RA, IS, OC, FP) { }
     173             : 
     174           0 :   unsigned resolveVariantSchedClass(unsigned SchedClass,
     175             :       const MCInst *MI, unsigned CPUID) const override {
     176           0 :     return NVPTX_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID); 
     177             :   }
     178             : };
     179             : 
     180         394 : static inline MCSubtargetInfo *createNVPTXMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef FS) {
     181             :   return new NVPTXGenMCSubtargetInfo(TT, CPU, FS, NVPTXFeatureKV, NVPTXSubTypeKV, 
     182             :                       NVPTXProcSchedKV, NVPTXWriteProcResTable, NVPTXWriteLatencyTable, NVPTXReadAdvanceTable, 
     183         788 :                       nullptr, nullptr, nullptr);
     184             : }
     185             : 
     186             : } // end namespace llvm
     187             : 
     188             : #endif // GET_SUBTARGETINFO_MC_DESC
     189             : 
     190             : 
     191             : #ifdef GET_SUBTARGETINFO_TARGET_DESC
     192             : #undef GET_SUBTARGETINFO_TARGET_DESC
     193             : 
     194             : #include "llvm/Support/Debug.h"
     195             : #include "llvm/Support/raw_ostream.h"
     196             : 
     197             : // ParseSubtargetFeatures - Parses features string setting specified
     198             : // subtarget options.
     199         635 : void llvm::NVPTXSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {
     200             :   LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
     201             :   LLVM_DEBUG(dbgs() << "\nCPU:" << CPU << "\n\n");
     202         635 :   InitMCProcessorInfo(CPU, FS);
     203             :   const FeatureBitset& Bits = getFeatureBits();
     204         635 :   if (Bits[NVPTX::PTX32] && PTXVersion < 32) PTXVersion = 32;
     205         635 :   if (Bits[NVPTX::PTX40] && PTXVersion < 40) PTXVersion = 40;
     206         635 :   if (Bits[NVPTX::PTX41] && PTXVersion < 41) PTXVersion = 41;
     207         635 :   if (Bits[NVPTX::PTX42] && PTXVersion < 42) PTXVersion = 42;
     208         635 :   if (Bits[NVPTX::PTX43] && PTXVersion < 43) PTXVersion = 43;
     209         635 :   if (Bits[NVPTX::PTX50] && PTXVersion < 50) PTXVersion = 50;
     210         635 :   if (Bits[NVPTX::PTX60] && PTXVersion < 60) PTXVersion = 60;
     211         635 :   if (Bits[NVPTX::PTX61] && PTXVersion < 61) PTXVersion = 61;
     212         635 :   if (Bits[NVPTX::SM20] && SmVersion < 20) SmVersion = 20;
     213         635 :   if (Bits[NVPTX::SM21] && SmVersion < 21) SmVersion = 21;
     214         635 :   if (Bits[NVPTX::SM30] && SmVersion < 30) SmVersion = 30;
     215         635 :   if (Bits[NVPTX::SM32] && SmVersion < 32) SmVersion = 32;
     216         635 :   if (Bits[NVPTX::SM35] && SmVersion < 35) SmVersion = 35;
     217         635 :   if (Bits[NVPTX::SM37] && SmVersion < 37) SmVersion = 37;
     218         635 :   if (Bits[NVPTX::SM50] && SmVersion < 50) SmVersion = 50;
     219         635 :   if (Bits[NVPTX::SM52] && SmVersion < 52) SmVersion = 52;
     220         635 :   if (Bits[NVPTX::SM53] && SmVersion < 53) SmVersion = 53;
     221         635 :   if (Bits[NVPTX::SM60] && SmVersion < 60) SmVersion = 60;
     222         635 :   if (Bits[NVPTX::SM61] && SmVersion < 61) SmVersion = 61;
     223         635 :   if (Bits[NVPTX::SM62] && SmVersion < 62) SmVersion = 62;
     224         635 :   if (Bits[NVPTX::SM70] && SmVersion < 70) SmVersion = 70;
     225         635 :   if (Bits[NVPTX::SM72] && SmVersion < 72) SmVersion = 72;
     226         635 : }
     227             : #endif // GET_SUBTARGETINFO_TARGET_DESC
     228             : 
     229             : 
     230             : #ifdef GET_SUBTARGETINFO_HEADER
     231             : #undef GET_SUBTARGETINFO_HEADER
     232             : 
     233             : namespace llvm {
     234             : class DFAPacketizer;
     235             : namespace NVPTX_MC {
     236             : unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
     237             : }
     238             : 
     239         625 : struct NVPTXGenSubtargetInfo : public TargetSubtargetInfo {
     240             :   explicit NVPTXGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS);
     241             : public:
     242             :   unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
     243             :   unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
     244             :   DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
     245             : };
     246             : } // end namespace llvm
     247             : 
     248             : #endif // GET_SUBTARGETINFO_HEADER
     249             : 
     250             : 
     251             : #ifdef GET_SUBTARGETINFO_CTOR
     252             : #undef GET_SUBTARGETINFO_CTOR
     253             : 
     254             : #include "llvm/CodeGen/TargetSchedule.h"
     255             : 
     256             : namespace llvm {
     257             : extern const llvm::SubtargetFeatureKV NVPTXFeatureKV[];
     258             : extern const llvm::SubtargetFeatureKV NVPTXSubTypeKV[];
     259             : extern const llvm::SubtargetInfoKV NVPTXProcSchedKV[];
     260             : extern const llvm::MCWriteProcResEntry NVPTXWriteProcResTable[];
     261             : extern const llvm::MCWriteLatencyEntry NVPTXWriteLatencyTable[];
     262             : extern const llvm::MCReadAdvanceEntry NVPTXReadAdvanceTable[];
     263         635 : NVPTXGenSubtargetInfo::NVPTXGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
     264             :   : TargetSubtargetInfo(TT, CPU, FS, makeArrayRef(NVPTXFeatureKV, 22), makeArrayRef(NVPTXSubTypeKV, 14), 
     265             :                         NVPTXProcSchedKV, NVPTXWriteProcResTable, NVPTXWriteLatencyTable, NVPTXReadAdvanceTable, 
     266         635 :                         nullptr, nullptr, nullptr) {}
     267             : 
     268           0 : unsigned NVPTXGenSubtargetInfo
     269             : ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
     270           0 :   report_fatal_error("Expected a variant SchedClass");
     271             : } // NVPTXGenSubtargetInfo::resolveSchedClass
     272             : 
     273           0 : unsigned NVPTXGenSubtargetInfo
     274             : ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
     275           0 :   return NVPTX_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
     276             : } // NVPTXGenSubtargetInfo::resolveVariantSchedClass
     277             : } // end namespace llvm
     278             : 
     279             : #endif // GET_SUBTARGETINFO_CTOR
     280             : 

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