LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/NVPTX - NVPTXGenSubtargetInfo.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 32 34 94.1 %
Date: 2017-09-14 15:23:50 Functions: 3 6 50.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Subtarget Enumeration Source Fragment                                      *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : 
      10             : #ifdef GET_SUBTARGETINFO_ENUM
      11             : #undef GET_SUBTARGETINFO_ENUM
      12             : 
      13             : namespace llvm {
      14             : namespace NVPTX {
      15             : enum {
      16             :   PTX32 = 0,
      17             :   PTX40 = 1,
      18             :   PTX41 = 2,
      19             :   PTX42 = 3,
      20             :   PTX43 = 4,
      21             :   PTX50 = 5,
      22             :   PTX60 = 6,
      23             :   SATOM = 7,
      24             :   SM20 = 8,
      25             :   SM21 = 9,
      26             :   SM30 = 10,
      27             :   SM32 = 11,
      28             :   SM35 = 12,
      29             :   SM37 = 13,
      30             :   SM50 = 14,
      31             :   SM52 = 15,
      32             :   SM53 = 16,
      33             :   SM60 = 17,
      34             :   SM61 = 18,
      35             :   SM62 = 19,
      36             :   SM70 = 20
      37             : };
      38             : } // end namespace NVPTX
      39             : } // end namespace llvm
      40             : 
      41             : #endif // GET_SUBTARGETINFO_ENUM
      42             : 
      43             : 
      44             : #ifdef GET_SUBTARGETINFO_MC_DESC
      45             : #undef GET_SUBTARGETINFO_MC_DESC
      46             : 
      47             : namespace llvm {
      48             : // Sorted (by key) array of values for CPU features.
      49             : extern const llvm::SubtargetFeatureKV NVPTXFeatureKV[] = {
      50             :   { "ptx32", "Use PTX version 3.2", { NVPTX::PTX32 }, { } },
      51             :   { "ptx40", "Use PTX version 4.0", { NVPTX::PTX40 }, { } },
      52             :   { "ptx41", "Use PTX version 4.1", { NVPTX::PTX41 }, { } },
      53             :   { "ptx42", "Use PTX version 4.2", { NVPTX::PTX42 }, { } },
      54             :   { "ptx43", "Use PTX version 4.3", { NVPTX::PTX43 }, { } },
      55             :   { "ptx50", "Use PTX version 5.0", { NVPTX::PTX50 }, { } },
      56             :   { "ptx60", "Use PTX version 6.0", { NVPTX::PTX60 }, { } },
      57             :   { "satom", "Atomic operations with scope", { NVPTX::SATOM }, { } },
      58             :   { "sm_20", "Target SM 2.0", { NVPTX::SM20 }, { } },
      59             :   { "sm_21", "Target SM 2.1", { NVPTX::SM21 }, { } },
      60             :   { "sm_30", "Target SM 3.0", { NVPTX::SM30 }, { } },
      61             :   { "sm_32", "Target SM 3.2", { NVPTX::SM32 }, { } },
      62             :   { "sm_35", "Target SM 3.5", { NVPTX::SM35 }, { } },
      63             :   { "sm_37", "Target SM 3.7", { NVPTX::SM37 }, { } },
      64             :   { "sm_50", "Target SM 5.0", { NVPTX::SM50 }, { } },
      65             :   { "sm_52", "Target SM 5.2", { NVPTX::SM52 }, { } },
      66             :   { "sm_53", "Target SM 5.3", { NVPTX::SM53 }, { } },
      67             :   { "sm_60", "Target SM 6.0", { NVPTX::SM60 }, { } },
      68             :   { "sm_61", "Target SM 6.1", { NVPTX::SM61 }, { } },
      69             :   { "sm_62", "Target SM 6.2", { NVPTX::SM62 }, { } },
      70             :   { "sm_70", "Target SM 7.0", { NVPTX::SM70 }, { } }
      71       72306 : };
      72             : 
      73             : // Sorted (by key) array of values for CPU subtype.
      74             : extern const llvm::SubtargetFeatureKV NVPTXSubTypeKV[] = {
      75             :   { "sm_20", "Select the sm_20 processor", { NVPTX::SM20 }, { } },
      76             :   { "sm_21", "Select the sm_21 processor", { NVPTX::SM21 }, { } },
      77             :   { "sm_30", "Select the sm_30 processor", { NVPTX::SM30 }, { } },
      78             :   { "sm_32", "Select the sm_32 processor", { NVPTX::SM32, NVPTX::PTX40 }, { } },
      79             :   { "sm_35", "Select the sm_35 processor", { NVPTX::SM35 }, { } },
      80             :   { "sm_37", "Select the sm_37 processor", { NVPTX::SM37, NVPTX::PTX41 }, { } },
      81             :   { "sm_50", "Select the sm_50 processor", { NVPTX::SM50, NVPTX::PTX40 }, { } },
      82             :   { "sm_52", "Select the sm_52 processor", { NVPTX::SM52, NVPTX::PTX41 }, { } },
      83             :   { "sm_53", "Select the sm_53 processor", { NVPTX::SM53, NVPTX::PTX42 }, { } },
      84             :   { "sm_60", "Select the sm_60 processor", { NVPTX::SM60, NVPTX::PTX50, NVPTX::SATOM }, { } },
      85             :   { "sm_61", "Select the sm_61 processor", { NVPTX::SM61, NVPTX::PTX50, NVPTX::SATOM }, { } },
      86             :   { "sm_62", "Select the sm_62 processor", { NVPTX::SM62, NVPTX::PTX50, NVPTX::SATOM }, { } },
      87             :   { "sm_70", "Select the sm_70 processor", { NVPTX::SM70, NVPTX::PTX60, NVPTX::SATOM }, { } }
      88       72306 : };
      89             : 
      90             : #ifdef DBGFIELD
      91             : #error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
      92             : #endif
      93             : #ifndef NDEBUG
      94             : #define DBGFIELD(x) x,
      95             : #else
      96             : #define DBGFIELD(x)
      97             : #endif
      98             : 
      99             : // ===============================================================
     100             : // Data tables for the new per-operand machine model.
     101             : 
     102             : // {ProcResourceIdx, Cycles}
     103             : extern const llvm::MCWriteProcResEntry NVPTXWriteProcResTable[] = {
     104             :   { 0,  0}, // Invalid
     105             : }; // NVPTXWriteProcResTable
     106             : 
     107             : // {Cycles, WriteResourceID}
     108             : extern const llvm::MCWriteLatencyEntry NVPTXWriteLatencyTable[] = {
     109             :   { 0,  0}, // Invalid
     110             : }; // NVPTXWriteLatencyTable
     111             : 
     112             : // {UseIdx, WriteResourceID, Cycles}
     113             : extern const llvm::MCReadAdvanceEntry NVPTXReadAdvanceTable[] = {
     114             :   {0,  0,  0}, // Invalid
     115             : }; // NVPTXReadAdvanceTable
     116             : 
     117             : static const llvm::MCSchedModel NoSchedModel = {
     118             :   MCSchedModel::DefaultIssueWidth,
     119             :   MCSchedModel::DefaultMicroOpBufferSize,
     120             :   MCSchedModel::DefaultLoopMicroOpBufferSize,
     121             :   MCSchedModel::DefaultLoadLatency,
     122             :   MCSchedModel::DefaultHighLatency,
     123             :   MCSchedModel::DefaultMispredictPenalty,
     124             :   false, // PostRAScheduler
     125             :   false, // CompleteModel
     126             :   0, // Processor ID
     127             :   nullptr, nullptr, 0, 0, // No instruction-level machine model.
     128             :   nullptr}; // No Itinerary
     129             : 
     130             : // Sorted (by key) array of itineraries for CPU subtype.
     131             : extern const llvm::SubtargetInfoKV NVPTXProcSchedKV[] = {
     132             :   { "sm_20", (const void *)&NoSchedModel },
     133             :   { "sm_21", (const void *)&NoSchedModel },
     134             :   { "sm_30", (const void *)&NoSchedModel },
     135             :   { "sm_32", (const void *)&NoSchedModel },
     136             :   { "sm_35", (const void *)&NoSchedModel },
     137             :   { "sm_37", (const void *)&NoSchedModel },
     138             :   { "sm_50", (const void *)&NoSchedModel },
     139             :   { "sm_52", (const void *)&NoSchedModel },
     140             :   { "sm_53", (const void *)&NoSchedModel },
     141             :   { "sm_60", (const void *)&NoSchedModel },
     142             :   { "sm_61", (const void *)&NoSchedModel },
     143             :   { "sm_62", (const void *)&NoSchedModel },
     144             :   { "sm_70", (const void *)&NoSchedModel }
     145             : };
     146             : #undef DBGFIELD
     147         346 : static inline MCSubtargetInfo *createNVPTXMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef FS) {
     148             :   return new MCSubtargetInfo(TT, CPU, FS, NVPTXFeatureKV, NVPTXSubTypeKV, 
     149             :                       NVPTXProcSchedKV, NVPTXWriteProcResTable, NVPTXWriteLatencyTable, NVPTXReadAdvanceTable, 
     150        1038 :                       nullptr, nullptr, nullptr);
     151             : }
     152             : 
     153             : } // end namespace llvm
     154             : 
     155             : #endif // GET_SUBTARGETINFO_MC_DESC
     156             : 
     157             : 
     158             : #ifdef GET_SUBTARGETINFO_TARGET_DESC
     159             : #undef GET_SUBTARGETINFO_TARGET_DESC
     160             : 
     161             : #include "llvm/Support/Debug.h"
     162             : #include "llvm/Support/raw_ostream.h"
     163             : 
     164             : // ParseSubtargetFeatures - Parses features string setting specified
     165             : // subtarget options.
     166         573 : void llvm::NVPTXSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {
     167             :   DEBUG(dbgs() << "\nFeatures:" << FS);
     168             :   DEBUG(dbgs() << "\nCPU:" << CPU << "\n\n");
     169         573 :   InitMCProcessorInfo(CPU, FS);
     170         573 :   const FeatureBitset& Bits = getFeatureBits();
     171        1146 :   if (Bits[NVPTX::PTX32] && PTXVersion < 32) PTXVersion = 32;
     172        1146 :   if (Bits[NVPTX::PTX40] && PTXVersion < 40) PTXVersion = 40;
     173        1146 :   if (Bits[NVPTX::PTX41] && PTXVersion < 41) PTXVersion = 41;
     174        1146 :   if (Bits[NVPTX::PTX42] && PTXVersion < 42) PTXVersion = 42;
     175        1146 :   if (Bits[NVPTX::PTX43] && PTXVersion < 43) PTXVersion = 43;
     176        1146 :   if (Bits[NVPTX::PTX50] && PTXVersion < 50) PTXVersion = 50;
     177        1146 :   if (Bits[NVPTX::PTX60] && PTXVersion < 60) PTXVersion = 60;
     178        1146 :   if (Bits[NVPTX::SATOM]) HasAtomScope = true;
     179        1146 :   if (Bits[NVPTX::SM20] && SmVersion < 20) SmVersion = 20;
     180        1146 :   if (Bits[NVPTX::SM21] && SmVersion < 21) SmVersion = 21;
     181        1146 :   if (Bits[NVPTX::SM30] && SmVersion < 30) SmVersion = 30;
     182        1146 :   if (Bits[NVPTX::SM32] && SmVersion < 32) SmVersion = 32;
     183        1146 :   if (Bits[NVPTX::SM35] && SmVersion < 35) SmVersion = 35;
     184        1146 :   if (Bits[NVPTX::SM37] && SmVersion < 37) SmVersion = 37;
     185        1146 :   if (Bits[NVPTX::SM50] && SmVersion < 50) SmVersion = 50;
     186        1146 :   if (Bits[NVPTX::SM52] && SmVersion < 52) SmVersion = 52;
     187        1146 :   if (Bits[NVPTX::SM53] && SmVersion < 53) SmVersion = 53;
     188        1146 :   if (Bits[NVPTX::SM60] && SmVersion < 60) SmVersion = 60;
     189        1146 :   if (Bits[NVPTX::SM61] && SmVersion < 61) SmVersion = 61;
     190        1146 :   if (Bits[NVPTX::SM62] && SmVersion < 62) SmVersion = 62;
     191        1146 :   if (Bits[NVPTX::SM70] && SmVersion < 70) SmVersion = 70;
     192         573 : }
     193             : #endif // GET_SUBTARGETINFO_TARGET_DESC
     194             : 
     195             : 
     196             : #ifdef GET_SUBTARGETINFO_HEADER
     197             : #undef GET_SUBTARGETINFO_HEADER
     198             : 
     199             : namespace llvm {
     200             : class DFAPacketizer;
     201         563 : struct NVPTXGenSubtargetInfo : public TargetSubtargetInfo {
     202             :   explicit NVPTXGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS);
     203             : public:
     204             :   unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
     205             :   DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
     206             : };
     207             : } // end namespace llvm
     208             : 
     209             : #endif // GET_SUBTARGETINFO_HEADER
     210             : 
     211             : 
     212             : #ifdef GET_SUBTARGETINFO_CTOR
     213             : #undef GET_SUBTARGETINFO_CTOR
     214             : 
     215             : #include "llvm/CodeGen/TargetSchedule.h"
     216             : 
     217             : namespace llvm {
     218             : extern const llvm::SubtargetFeatureKV NVPTXFeatureKV[];
     219             : extern const llvm::SubtargetFeatureKV NVPTXSubTypeKV[];
     220             : extern const llvm::SubtargetInfoKV NVPTXProcSchedKV[];
     221             : extern const llvm::MCWriteProcResEntry NVPTXWriteProcResTable[];
     222             : extern const llvm::MCWriteLatencyEntry NVPTXWriteLatencyTable[];
     223             : extern const llvm::MCReadAdvanceEntry NVPTXReadAdvanceTable[];
     224         573 : NVPTXGenSubtargetInfo::NVPTXGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
     225             :   : TargetSubtargetInfo(TT, CPU, FS, makeArrayRef(NVPTXFeatureKV, 21), makeArrayRef(NVPTXSubTypeKV, 13), 
     226             :                         NVPTXProcSchedKV, NVPTXWriteProcResTable, NVPTXWriteLatencyTable, NVPTXReadAdvanceTable, 
     227        1719 :                         nullptr, nullptr, nullptr) {}
     228             : 
     229           0 : unsigned NVPTXGenSubtargetInfo
     230             : ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
     231           0 :   report_fatal_error("Expected a variant SchedClass");
     232             : } // NVPTXGenSubtargetInfo::resolveSchedClass
     233             : } // end namespace llvm
     234             : 
     235             : #endif // GET_SUBTARGETINFO_CTOR
     236             : 

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