LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/PowerPC - PPCGenFastISel.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 159 1151 13.8 %
Date: 2018-10-20 13:21:21 Functions: 28 128 21.9 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* "Fast" Instruction Selector for the PPC target                             *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : 
      10             : // FastEmit Immediate Predicate functions.
      11             : static bool Predicate_imm32SExt16(int64_t Imm) {
      12             : 
      13             :   // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
      14             :   // sign extended field.  Used by instructions like 'addi'.
      15          23 :   return (int32_t)Imm == (short)Imm;
      16             : 
      17             : }
      18             : static bool Predicate_imm64SExt16(int64_t Imm) {
      19             : 
      20             :   // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
      21             :   // sign extended field.  Used by instructions like 'addi'.
      22          19 :   return (int64_t)Imm == (short)Imm;
      23             : 
      24             : }
      25             : static bool Predicate_immSExt5NonZero(int64_t Imm) {
      26             :  return Imm && isInt<5>(Imm); 
      27             : }
      28             : 
      29             : 
      30             : // FastEmit functions for ISD::READCYCLECOUNTER.
      31             : 
      32             : unsigned fastEmit_ISD_READCYCLECOUNTER_MVT_i64_(MVT RetVT) {
      33           0 :   if (RetVT.SimpleTy != MVT::i64)
      34             :     return 0;
      35           0 :   return fastEmitInst_(PPC::MFTB8, &PPC::G8RCRegClass);
      36             : }
      37             : 
      38             : unsigned fastEmit_ISD_READCYCLECOUNTER_(MVT VT, MVT RetVT) {
      39           0 :   switch (VT.SimpleTy) {
      40           0 :   case MVT::i64: return fastEmit_ISD_READCYCLECOUNTER_MVT_i64_(RetVT);
      41             :   default: return 0;
      42             :   }
      43             : }
      44             : 
      45             : // FastEmit functions for PPCISD::MFFS.
      46             : 
      47             : unsigned fastEmit_PPCISD_MFFS_MVT_f64_(MVT RetVT) {
      48           0 :   if (RetVT.SimpleTy != MVT::f64)
      49             :     return 0;
      50           0 :   if ((PPCSubTarget->hasFPU())) {
      51           0 :     return fastEmitInst_(PPC::MFFS, &PPC::F8RCRegClass);
      52             :   }
      53             :   return 0;
      54             : }
      55             : 
      56           0 : unsigned fastEmit_PPCISD_MFFS_(MVT VT, MVT RetVT) {
      57           0 :   switch (VT.SimpleTy) {
      58           0 :   case MVT::f64: return fastEmit_PPCISD_MFFS_MVT_f64_(RetVT);
      59             :   default: return 0;
      60             :   }
      61             : }
      62             : 
      63             : // FastEmit functions for PPCISD::PPC32_GOT.
      64             : 
      65             : unsigned fastEmit_PPCISD_PPC32_GOT_MVT_i32_(MVT RetVT) {
      66           0 :   if (RetVT.SimpleTy != MVT::i32)
      67             :     return 0;
      68           0 :   return fastEmitInst_(PPC::PPC32GOT, &PPC::GPRCRegClass);
      69             : }
      70             : 
      71             : unsigned fastEmit_PPCISD_PPC32_GOT_(MVT VT, MVT RetVT) {
      72           0 :   switch (VT.SimpleTy) {
      73           0 :   case MVT::i32: return fastEmit_PPCISD_PPC32_GOT_MVT_i32_(RetVT);
      74             :   default: return 0;
      75             :   }
      76             : }
      77             : 
      78             : // Top-level FastEmit function.
      79             : 
      80           0 : unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode) override {
      81           0 :   switch (Opcode) {
      82           0 :   case ISD::READCYCLECOUNTER: return fastEmit_ISD_READCYCLECOUNTER_(VT, RetVT);
      83           0 :   case PPCISD::MFFS: return fastEmit_PPCISD_MFFS_(VT, RetVT);
      84           0 :   case PPCISD::PPC32_GOT: return fastEmit_PPCISD_PPC32_GOT_(VT, RetVT);
      85             :   default: return 0;
      86             :   }
      87             : }
      88             : 
      89             : // FastEmit functions for ISD::BITCAST.
      90             : 
      91           0 : unsigned fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      92           0 :   if (RetVT.SimpleTy != MVT::f64)
      93             :     return 0;
      94           0 :   if ((PPCSubTarget->hasDirectMove()) && (PPCSubTarget->hasVSX())) {
      95           0 :     return fastEmitInst_r(PPC::MTVSRD, &PPC::VSFRCRegClass, Op0, Op0IsKill);
      96             :   }
      97             :   return 0;
      98             : }
      99             : 
     100           0 : unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     101           0 :   if (RetVT.SimpleTy != MVT::i64)
     102             :     return 0;
     103           0 :   if ((PPCSubTarget->hasDirectMove()) && (PPCSubTarget->hasVSX())) {
     104           0 :     return fastEmitInst_r(PPC::MFVSRD, &PPC::G8RCRegClass, Op0, Op0IsKill);
     105             :   }
     106             :   return 0;
     107             : }
     108             : 
     109           1 : unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     110           1 :   switch (VT.SimpleTy) {
     111           0 :   case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0, Op0IsKill);
     112           0 :   case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0, Op0IsKill);
     113             :   default: return 0;
     114             :   }
     115             : }
     116             : 
     117             : // FastEmit functions for ISD::CTLZ.
     118             : 
     119             : unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     120           0 :   if (RetVT.SimpleTy != MVT::i32)
     121             :     return 0;
     122             :   return fastEmitInst_r(PPC::CNTLZW, &PPC::GPRCRegClass, Op0, Op0IsKill);
     123             : }
     124             : 
     125             : unsigned fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     126           0 :   if (RetVT.SimpleTy != MVT::i64)
     127             :     return 0;
     128             :   return fastEmitInst_r(PPC::CNTLZD, &PPC::G8RCRegClass, Op0, Op0IsKill);
     129             : }
     130             : 
     131             : unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     132           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     133             :     return 0;
     134           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     135             :     return fastEmitInst_r(PPC::VCLZB, &PPC::VRRCRegClass, Op0, Op0IsKill);
     136             :   }
     137             :   return 0;
     138             : }
     139             : 
     140             : unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     141           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     142             :     return 0;
     143           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     144             :     return fastEmitInst_r(PPC::VCLZH, &PPC::VRRCRegClass, Op0, Op0IsKill);
     145             :   }
     146             :   return 0;
     147             : }
     148             : 
     149             : unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     150           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     151             :     return 0;
     152           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     153             :     return fastEmitInst_r(PPC::VCLZW, &PPC::VRRCRegClass, Op0, Op0IsKill);
     154             :   }
     155             :   return 0;
     156             : }
     157             : 
     158             : unsigned fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     159           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     160             :     return 0;
     161           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     162             :     return fastEmitInst_r(PPC::VCLZD, &PPC::VRRCRegClass, Op0, Op0IsKill);
     163             :   }
     164             :   return 0;
     165             : }
     166             : 
     167           0 : unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     168           0 :   switch (VT.SimpleTy) {
     169           0 :   case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
     170           0 :   case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0, Op0IsKill);
     171           0 :   case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     172           0 :   case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     173           0 :   case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     174           0 :   case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     175             :   default: return 0;
     176             :   }
     177             : }
     178             : 
     179             : // FastEmit functions for ISD::CTPOP.
     180             : 
     181             : unsigned fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     182           0 :   if (RetVT.SimpleTy != MVT::i32)
     183             :     return 0;
     184             :   return fastEmitInst_r(PPC::POPCNTW, &PPC::GPRCRegClass, Op0, Op0IsKill);
     185             : }
     186             : 
     187             : unsigned fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     188           0 :   if (RetVT.SimpleTy != MVT::i64)
     189             :     return 0;
     190             :   return fastEmitInst_r(PPC::POPCNTD, &PPC::G8RCRegClass, Op0, Op0IsKill);
     191             : }
     192             : 
     193             : unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     194           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     195             :     return 0;
     196           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     197             :     return fastEmitInst_r(PPC::VPOPCNTB, &PPC::VRRCRegClass, Op0, Op0IsKill);
     198             :   }
     199             :   return 0;
     200             : }
     201             : 
     202             : unsigned fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     203           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     204             :     return 0;
     205           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     206             :     return fastEmitInst_r(PPC::VPOPCNTH, &PPC::VRRCRegClass, Op0, Op0IsKill);
     207             :   }
     208             :   return 0;
     209             : }
     210             : 
     211             : unsigned fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     212           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     213             :     return 0;
     214           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     215             :     return fastEmitInst_r(PPC::VPOPCNTW, &PPC::VRRCRegClass, Op0, Op0IsKill);
     216             :   }
     217             :   return 0;
     218             : }
     219             : 
     220             : unsigned fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     221           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     222             :     return 0;
     223           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     224             :     return fastEmitInst_r(PPC::VPOPCNTD, &PPC::VRRCRegClass, Op0, Op0IsKill);
     225             :   }
     226             :   return 0;
     227             : }
     228             : 
     229           0 : unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     230           0 :   switch (VT.SimpleTy) {
     231           0 :   case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0, Op0IsKill);
     232           0 :   case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0, Op0IsKill);
     233           0 :   case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     234           0 :   case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     235           0 :   case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     236           0 :   case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     237             :   default: return 0;
     238             :   }
     239             : }
     240             : 
     241             : // FastEmit functions for ISD::CTTZ.
     242             : 
     243             : unsigned fastEmit_ISD_CTTZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     244           0 :   if (RetVT.SimpleTy != MVT::i32)
     245             :     return 0;
     246           0 :   if ((PPCSubTarget->isISA3_0())) {
     247             :     return fastEmitInst_r(PPC::CNTTZW, &PPC::GPRCRegClass, Op0, Op0IsKill);
     248             :   }
     249             :   return 0;
     250             : }
     251             : 
     252             : unsigned fastEmit_ISD_CTTZ_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     253           0 :   if (RetVT.SimpleTy != MVT::i64)
     254             :     return 0;
     255           0 :   if ((PPCSubTarget->isISA3_0())) {
     256             :     return fastEmitInst_r(PPC::CNTTZD, &PPC::G8RCRegClass, Op0, Op0IsKill);
     257             :   }
     258             :   return 0;
     259             : }
     260             : 
     261             : unsigned fastEmit_ISD_CTTZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     262           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     263             :     return 0;
     264           0 :   if ((PPCSubTarget->hasP9Altivec())) {
     265             :     return fastEmitInst_r(PPC::VCTZB, &PPC::VRRCRegClass, Op0, Op0IsKill);
     266             :   }
     267             :   return 0;
     268             : }
     269             : 
     270             : unsigned fastEmit_ISD_CTTZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     271           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     272             :     return 0;
     273           0 :   if ((PPCSubTarget->hasP9Altivec())) {
     274             :     return fastEmitInst_r(PPC::VCTZH, &PPC::VRRCRegClass, Op0, Op0IsKill);
     275             :   }
     276             :   return 0;
     277             : }
     278             : 
     279             : unsigned fastEmit_ISD_CTTZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     280           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     281             :     return 0;
     282           0 :   if ((PPCSubTarget->hasP9Altivec())) {
     283             :     return fastEmitInst_r(PPC::VCTZW, &PPC::VRRCRegClass, Op0, Op0IsKill);
     284             :   }
     285             :   return 0;
     286             : }
     287             : 
     288             : unsigned fastEmit_ISD_CTTZ_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     289           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     290             :     return 0;
     291           0 :   if ((PPCSubTarget->hasP9Altivec())) {
     292             :     return fastEmitInst_r(PPC::VCTZD, &PPC::VRRCRegClass, Op0, Op0IsKill);
     293             :   }
     294             :   return 0;
     295             : }
     296             : 
     297           0 : unsigned fastEmit_ISD_CTTZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     298           0 :   switch (VT.SimpleTy) {
     299           0 :   case MVT::i32: return fastEmit_ISD_CTTZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
     300           0 :   case MVT::i64: return fastEmit_ISD_CTTZ_MVT_i64_r(RetVT, Op0, Op0IsKill);
     301           0 :   case MVT::v16i8: return fastEmit_ISD_CTTZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     302           0 :   case MVT::v8i16: return fastEmit_ISD_CTTZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     303           0 :   case MVT::v4i32: return fastEmit_ISD_CTTZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     304           0 :   case MVT::v2i64: return fastEmit_ISD_CTTZ_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     305             :   default: return 0;
     306             :   }
     307             : }
     308             : 
     309             : // FastEmit functions for ISD::FABS.
     310             : 
     311           0 : unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     312           0 :   if (RetVT.SimpleTy != MVT::f32)
     313             :     return 0;
     314           0 :   if ((PPCSubTarget->hasSPE())) {
     315           0 :     return fastEmitInst_r(PPC::EFSABS, &PPC::SPE4RCRegClass, Op0, Op0IsKill);
     316             :   }
     317           0 :   if ((PPCSubTarget->hasFPU())) {
     318           0 :     return fastEmitInst_r(PPC::FABSS, &PPC::F4RCRegClass, Op0, Op0IsKill);
     319             :   }
     320             :   return 0;
     321             : }
     322             : 
     323           0 : unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     324           0 :   if (RetVT.SimpleTy != MVT::f64)
     325             :     return 0;
     326           0 :   if ((PPCSubTarget->hasVSX())) {
     327           0 :     return fastEmitInst_r(PPC::XSABSDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     328             :   }
     329           0 :   if ((PPCSubTarget->hasSPE())) {
     330           0 :     return fastEmitInst_r(PPC::EFDABS, &PPC::SPERCRegClass, Op0, Op0IsKill);
     331             :   }
     332           0 :   if ((PPCSubTarget->hasFPU())) {
     333           0 :     return fastEmitInst_r(PPC::FABSD, &PPC::F8RCRegClass, Op0, Op0IsKill);
     334             :   }
     335             :   return 0;
     336             : }
     337             : 
     338             : unsigned fastEmit_ISD_FABS_MVT_f128_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     339           0 :   if (RetVT.SimpleTy != MVT::f128)
     340             :     return 0;
     341           0 :   if ((PPCSubTarget->hasP9Vector())) {
     342             :     return fastEmitInst_r(PPC::XSABSQP, &PPC::VRRCRegClass, Op0, Op0IsKill);
     343             :   }
     344             :   return 0;
     345             : }
     346             : 
     347           0 : unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     348           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     349             :     return 0;
     350           0 :   if ((PPCSubTarget->hasVSX())) {
     351           0 :     return fastEmitInst_r(PPC::XVABSSP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     352             :   }
     353           0 :   if ((PPCSubTarget->hasQPX())) {
     354           0 :     return fastEmitInst_r(PPC::QVFABSs, &PPC::QSRCRegClass, Op0, Op0IsKill);
     355             :   }
     356             :   return 0;
     357             : }
     358             : 
     359             : unsigned fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     360           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     361             :     return 0;
     362           0 :   if ((PPCSubTarget->hasVSX())) {
     363             :     return fastEmitInst_r(PPC::XVABSDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     364             :   }
     365             :   return 0;
     366             : }
     367             : 
     368             : unsigned fastEmit_ISD_FABS_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     369           0 :   if (RetVT.SimpleTy != MVT::v4f64)
     370             :     return 0;
     371           0 :   if ((PPCSubTarget->hasQPX())) {
     372             :     return fastEmitInst_r(PPC::QVFABS, &PPC::QFRCRegClass, Op0, Op0IsKill);
     373             :   }
     374             :   return 0;
     375             : }
     376             : 
     377           0 : unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     378           0 :   switch (VT.SimpleTy) {
     379           0 :   case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill);
     380           0 :   case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0, Op0IsKill);
     381           0 :   case MVT::f128: return fastEmit_ISD_FABS_MVT_f128_r(RetVT, Op0, Op0IsKill);
     382           0 :   case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     383           0 :   case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     384           0 :   case MVT::v4f64: return fastEmit_ISD_FABS_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
     385             :   default: return 0;
     386             :   }
     387             : }
     388             : 
     389             : // FastEmit functions for ISD::FCEIL.
     390             : 
     391             : unsigned fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     392           0 :   if (RetVT.SimpleTy != MVT::f32)
     393             :     return 0;
     394           0 :   if ((PPCSubTarget->hasFPU())) {
     395             :     return fastEmitInst_r(PPC::FRIPS, &PPC::F4RCRegClass, Op0, Op0IsKill);
     396             :   }
     397             :   return 0;
     398             : }
     399             : 
     400           0 : unsigned fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     401           0 :   if (RetVT.SimpleTy != MVT::f64)
     402             :     return 0;
     403           0 :   if ((PPCSubTarget->hasVSX())) {
     404           0 :     return fastEmitInst_r(PPC::XSRDPIP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     405             :   }
     406           0 :   if ((PPCSubTarget->hasFPU())) {
     407           0 :     return fastEmitInst_r(PPC::FRIPD, &PPC::F8RCRegClass, Op0, Op0IsKill);
     408             :   }
     409             :   return 0;
     410             : }
     411             : 
     412           0 : unsigned fastEmit_ISD_FCEIL_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     413           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     414             :     return 0;
     415           0 :   if ((PPCSubTarget->hasVSX())) {
     416           0 :     return fastEmitInst_r(PPC::XVRSPIP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     417             :   }
     418           0 :   if ((PPCSubTarget->hasAltivec())) {
     419           0 :     return fastEmitInst_r(PPC::VRFIP, &PPC::VRRCRegClass, Op0, Op0IsKill);
     420             :   }
     421           0 :   if ((PPCSubTarget->hasQPX())) {
     422           0 :     return fastEmitInst_r(PPC::QVFRIPs, &PPC::QSRCRegClass, Op0, Op0IsKill);
     423             :   }
     424             :   return 0;
     425             : }
     426             : 
     427             : unsigned fastEmit_ISD_FCEIL_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     428           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     429             :     return 0;
     430           0 :   if ((PPCSubTarget->hasVSX())) {
     431             :     return fastEmitInst_r(PPC::XVRDPIP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     432             :   }
     433             :   return 0;
     434             : }
     435             : 
     436             : unsigned fastEmit_ISD_FCEIL_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     437           0 :   if (RetVT.SimpleTy != MVT::v4f64)
     438             :     return 0;
     439           0 :   if ((PPCSubTarget->hasQPX())) {
     440             :     return fastEmitInst_r(PPC::QVFRIP, &PPC::QFRCRegClass, Op0, Op0IsKill);
     441             :   }
     442             :   return 0;
     443             : }
     444             : 
     445           0 : unsigned fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     446           0 :   switch (VT.SimpleTy) {
     447           0 :   case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0, Op0IsKill);
     448           0 :   case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0, Op0IsKill);
     449           0 :   case MVT::v4f32: return fastEmit_ISD_FCEIL_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     450           0 :   case MVT::v2f64: return fastEmit_ISD_FCEIL_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     451           0 :   case MVT::v4f64: return fastEmit_ISD_FCEIL_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
     452             :   default: return 0;
     453             :   }
     454             : }
     455             : 
     456             : // FastEmit functions for ISD::FFLOOR.
     457             : 
     458             : unsigned fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     459           0 :   if (RetVT.SimpleTy != MVT::f32)
     460             :     return 0;
     461           0 :   if ((PPCSubTarget->hasFPU())) {
     462             :     return fastEmitInst_r(PPC::FRIMS, &PPC::F4RCRegClass, Op0, Op0IsKill);
     463             :   }
     464             :   return 0;
     465             : }
     466             : 
     467           0 : unsigned fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     468           0 :   if (RetVT.SimpleTy != MVT::f64)
     469             :     return 0;
     470           0 :   if ((PPCSubTarget->hasVSX())) {
     471           0 :     return fastEmitInst_r(PPC::XSRDPIM, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     472             :   }
     473           0 :   if ((PPCSubTarget->hasFPU())) {
     474           0 :     return fastEmitInst_r(PPC::FRIMD, &PPC::F8RCRegClass, Op0, Op0IsKill);
     475             :   }
     476             :   return 0;
     477             : }
     478             : 
     479           0 : unsigned fastEmit_ISD_FFLOOR_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     480           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     481             :     return 0;
     482           0 :   if ((PPCSubTarget->hasVSX())) {
     483           0 :     return fastEmitInst_r(PPC::XVRSPIM, &PPC::VSRCRegClass, Op0, Op0IsKill);
     484             :   }
     485           0 :   if ((PPCSubTarget->hasAltivec())) {
     486           0 :     return fastEmitInst_r(PPC::VRFIM, &PPC::VRRCRegClass, Op0, Op0IsKill);
     487             :   }
     488           0 :   if ((PPCSubTarget->hasQPX())) {
     489           0 :     return fastEmitInst_r(PPC::QVFRIMs, &PPC::QSRCRegClass, Op0, Op0IsKill);
     490             :   }
     491             :   return 0;
     492             : }
     493             : 
     494             : unsigned fastEmit_ISD_FFLOOR_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     495           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     496             :     return 0;
     497           0 :   if ((PPCSubTarget->hasVSX())) {
     498             :     return fastEmitInst_r(PPC::XVRDPIM, &PPC::VSRCRegClass, Op0, Op0IsKill);
     499             :   }
     500             :   return 0;
     501             : }
     502             : 
     503             : unsigned fastEmit_ISD_FFLOOR_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     504           0 :   if (RetVT.SimpleTy != MVT::v4f64)
     505             :     return 0;
     506           0 :   if ((PPCSubTarget->hasQPX())) {
     507             :     return fastEmitInst_r(PPC::QVFRIM, &PPC::QFRCRegClass, Op0, Op0IsKill);
     508             :   }
     509             :   return 0;
     510             : }
     511             : 
     512           0 : unsigned fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     513           0 :   switch (VT.SimpleTy) {
     514           0 :   case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0, Op0IsKill);
     515           0 :   case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0, Op0IsKill);
     516           0 :   case MVT::v4f32: return fastEmit_ISD_FFLOOR_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     517           0 :   case MVT::v2f64: return fastEmit_ISD_FFLOOR_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     518           0 :   case MVT::v4f64: return fastEmit_ISD_FFLOOR_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
     519             :   default: return 0;
     520             :   }
     521             : }
     522             : 
     523             : // FastEmit functions for ISD::FNEARBYINT.
     524             : 
     525             : unsigned fastEmit_ISD_FNEARBYINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     526           0 :   if (RetVT.SimpleTy != MVT::f64)
     527             :     return 0;
     528           0 :   if ((PPCSubTarget->hasVSX())) {
     529             :     return fastEmitInst_r(PPC::XSRDPIC, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     530             :   }
     531             :   return 0;
     532             : }
     533             : 
     534           0 : unsigned fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     535           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     536             :     return 0;
     537           0 :   if ((PPCSubTarget->hasVSX())) {
     538           0 :     return fastEmitInst_r(PPC::XVRSPIC, &PPC::VSRCRegClass, Op0, Op0IsKill);
     539             :   }
     540           0 :   if ((PPCSubTarget->hasAltivec())) {
     541           0 :     return fastEmitInst_r(PPC::VRFIN, &PPC::VRRCRegClass, Op0, Op0IsKill);
     542             :   }
     543             :   return 0;
     544             : }
     545             : 
     546             : unsigned fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     547           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     548             :     return 0;
     549           0 :   if ((PPCSubTarget->hasVSX())) {
     550             :     return fastEmitInst_r(PPC::XVRDPIC, &PPC::VSRCRegClass, Op0, Op0IsKill);
     551             :   }
     552             :   return 0;
     553             : }
     554             : 
     555           0 : unsigned fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     556           0 :   switch (VT.SimpleTy) {
     557           0 :   case MVT::f64: return fastEmit_ISD_FNEARBYINT_MVT_f64_r(RetVT, Op0, Op0IsKill);
     558           0 :   case MVT::v4f32: return fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     559           0 :   case MVT::v2f64: return fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     560             :   default: return 0;
     561             :   }
     562             : }
     563             : 
     564             : // FastEmit functions for ISD::FNEG.
     565             : 
     566           0 : unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     567           0 :   if (RetVT.SimpleTy != MVT::f32)
     568             :     return 0;
     569           0 :   if ((PPCSubTarget->hasSPE())) {
     570           0 :     return fastEmitInst_r(PPC::EFSNEG, &PPC::SPE4RCRegClass, Op0, Op0IsKill);
     571             :   }
     572           0 :   if ((PPCSubTarget->hasFPU())) {
     573           0 :     return fastEmitInst_r(PPC::FNEGS, &PPC::F4RCRegClass, Op0, Op0IsKill);
     574             :   }
     575             :   return 0;
     576             : }
     577             : 
     578           0 : unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     579           0 :   if (RetVT.SimpleTy != MVT::f64)
     580             :     return 0;
     581           0 :   if ((PPCSubTarget->hasVSX())) {
     582           0 :     return fastEmitInst_r(PPC::XSNEGDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     583             :   }
     584           0 :   if ((PPCSubTarget->hasSPE())) {
     585           0 :     return fastEmitInst_r(PPC::EFDNEG, &PPC::SPERCRegClass, Op0, Op0IsKill);
     586             :   }
     587           0 :   if ((PPCSubTarget->hasFPU())) {
     588           0 :     return fastEmitInst_r(PPC::FNEGD, &PPC::F8RCRegClass, Op0, Op0IsKill);
     589             :   }
     590             :   return 0;
     591             : }
     592             : 
     593             : unsigned fastEmit_ISD_FNEG_MVT_f128_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     594           0 :   if (RetVT.SimpleTy != MVT::f128)
     595             :     return 0;
     596           0 :   if ((PPCSubTarget->hasP9Vector())) {
     597             :     return fastEmitInst_r(PPC::XSNEGQP, &PPC::VRRCRegClass, Op0, Op0IsKill);
     598             :   }
     599             :   return 0;
     600             : }
     601             : 
     602           0 : unsigned fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     603           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     604             :     return 0;
     605           0 :   if ((PPCSubTarget->hasVSX())) {
     606           0 :     return fastEmitInst_r(PPC::XVNEGSP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     607             :   }
     608           0 :   if ((PPCSubTarget->hasQPX())) {
     609           0 :     return fastEmitInst_r(PPC::QVFNEGs, &PPC::QSRCRegClass, Op0, Op0IsKill);
     610             :   }
     611             :   return 0;
     612             : }
     613             : 
     614             : unsigned fastEmit_ISD_FNEG_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     615           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     616             :     return 0;
     617           0 :   if ((PPCSubTarget->hasVSX())) {
     618             :     return fastEmitInst_r(PPC::XVNEGDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     619             :   }
     620             :   return 0;
     621             : }
     622             : 
     623             : unsigned fastEmit_ISD_FNEG_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     624           0 :   if (RetVT.SimpleTy != MVT::v4f64)
     625             :     return 0;
     626           0 :   if ((PPCSubTarget->hasQPX())) {
     627             :     return fastEmitInst_r(PPC::QVFNEG, &PPC::QFRCRegClass, Op0, Op0IsKill);
     628             :   }
     629             :   return 0;
     630             : }
     631             : 
     632           0 : unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     633           0 :   switch (VT.SimpleTy) {
     634           0 :   case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill);
     635           0 :   case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0, Op0IsKill);
     636           0 :   case MVT::f128: return fastEmit_ISD_FNEG_MVT_f128_r(RetVT, Op0, Op0IsKill);
     637           0 :   case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     638           0 :   case MVT::v2f64: return fastEmit_ISD_FNEG_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     639           0 :   case MVT::v4f64: return fastEmit_ISD_FNEG_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
     640             :   default: return 0;
     641             :   }
     642             : }
     643             : 
     644             : // FastEmit functions for ISD::FP_EXTEND.
     645             : 
     646             : unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     647           0 :   if (RetVT.SimpleTy != MVT::f64)
     648             :     return 0;
     649           0 :   if ((PPCSubTarget->hasSPE())) {
     650             :     return fastEmitInst_r(PPC::EFDCFS, &PPC::SPERCRegClass, Op0, Op0IsKill);
     651             :   }
     652             :   return 0;
     653             : }
     654             : 
     655             : unsigned fastEmit_ISD_FP_EXTEND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     656           0 :   if (RetVT.SimpleTy != MVT::f128)
     657             :     return 0;
     658           0 :   if ((PPCSubTarget->hasP9Vector())) {
     659             :     return fastEmitInst_r(PPC::XSCVDPQP, &PPC::VRRCRegClass, Op0, Op0IsKill);
     660             :   }
     661             :   return 0;
     662             : }
     663             : 
     664           0 : unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     665           0 :   switch (VT.SimpleTy) {
     666           0 :   case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0, Op0IsKill);
     667           0 :   case MVT::f64: return fastEmit_ISD_FP_EXTEND_MVT_f64_r(RetVT, Op0, Op0IsKill);
     668             :   default: return 0;
     669             :   }
     670             : }
     671             : 
     672             : // FastEmit functions for ISD::FP_ROUND.
     673             : 
     674           0 : unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     675           0 :   if (RetVT.SimpleTy != MVT::f32)
     676             :     return 0;
     677           0 :   if ((PPCSubTarget->hasSPE())) {
     678           0 :     return fastEmitInst_r(PPC::EFSCFD, &PPC::SPE4RCRegClass, Op0, Op0IsKill);
     679             :   }
     680           0 :   if ((PPCSubTarget->hasFPU())) {
     681           0 :     return fastEmitInst_r(PPC::FRSP, &PPC::F4RCRegClass, Op0, Op0IsKill);
     682             :   }
     683             :   return 0;
     684             : }
     685             : 
     686             : unsigned fastEmit_ISD_FP_ROUND_MVT_f128_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     687           0 :   if (RetVT.SimpleTy != MVT::f64)
     688             :     return 0;
     689           0 :   if ((PPCSubTarget->hasP9Vector())) {
     690             :     return fastEmitInst_r(PPC::XSCVQPDP, &PPC::VFRCRegClass, Op0, Op0IsKill);
     691             :   }
     692             :   return 0;
     693             : }
     694             : 
     695           0 : unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     696           0 :   switch (VT.SimpleTy) {
     697           0 :   case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
     698           0 :   case MVT::f128: return fastEmit_ISD_FP_ROUND_MVT_f128_r(RetVT, Op0, Op0IsKill);
     699             :   default: return 0;
     700             :   }
     701             : }
     702             : 
     703             : // FastEmit functions for ISD::FP_TO_SINT.
     704             : 
     705             : unsigned fastEmit_ISD_FP_TO_SINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     706          10 :   if (RetVT.SimpleTy != MVT::i32)
     707             :     return 0;
     708           6 :   if ((PPCSubTarget->hasSPE())) {
     709             :     return fastEmitInst_r(PPC::EFSCTSIZ, &PPC::GPRCRegClass, Op0, Op0IsKill);
     710             :   }
     711             :   return 0;
     712             : }
     713             : 
     714             : unsigned fastEmit_ISD_FP_TO_SINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     715           8 :   if (RetVT.SimpleTy != MVT::i32)
     716             :     return 0;
     717           4 :   if ((PPCSubTarget->hasSPE())) {
     718             :     return fastEmitInst_r(PPC::EFDCTSIZ, &PPC::GPRCRegClass, Op0, Op0IsKill);
     719             :   }
     720             :   return 0;
     721             : }
     722             : 
     723           0 : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     724           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     725             :     return 0;
     726           0 :   if ((PPCSubTarget->hasVSX())) {
     727           0 :     return fastEmitInst_r(PPC::XVCVSPSXWS, &PPC::VSRCRegClass, Op0, Op0IsKill);
     728             :   }
     729           0 :   if ((PPCSubTarget->hasAltivec())) {
     730           0 :     return fastEmitInst_r(PPC::VCTSXS_0, &PPC::VRRCRegClass, Op0, Op0IsKill);
     731             :   }
     732             :   return 0;
     733             : }
     734             : 
     735             : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     736           1 :   if (RetVT.SimpleTy != MVT::v2i64)
     737             :     return 0;
     738           1 :   if ((PPCSubTarget->hasVSX())) {
     739             :     return fastEmitInst_r(PPC::XVCVDPSXDS, &PPC::VSRCRegClass, Op0, Op0IsKill);
     740             :   }
     741             :   return 0;
     742             : }
     743             : 
     744          19 : unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     745          19 :   switch (VT.SimpleTy) {
     746          10 :   case MVT::f32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
     747           8 :   case MVT::f64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_r(RetVT, Op0, Op0IsKill);
     748           0 :   case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     749           1 :   case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     750             :   default: return 0;
     751             :   }
     752             : }
     753             : 
     754             : // FastEmit functions for ISD::FP_TO_UINT.
     755             : 
     756             : unsigned fastEmit_ISD_FP_TO_UINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     757           0 :   if (RetVT.SimpleTy != MVT::i32)
     758             :     return 0;
     759           0 :   if ((PPCSubTarget->hasSPE())) {
     760             :     return fastEmitInst_r(PPC::EFSCTUIZ, &PPC::GPRCRegClass, Op0, Op0IsKill);
     761             :   }
     762             :   return 0;
     763             : }
     764             : 
     765             : unsigned fastEmit_ISD_FP_TO_UINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     766           0 :   if (RetVT.SimpleTy != MVT::i32)
     767             :     return 0;
     768           0 :   if ((PPCSubTarget->hasSPE())) {
     769             :     return fastEmitInst_r(PPC::EFDCTUIZ, &PPC::GPRCRegClass, Op0, Op0IsKill);
     770             :   }
     771             :   return 0;
     772             : }
     773             : 
     774           0 : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     775           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     776             :     return 0;
     777           0 :   if ((PPCSubTarget->hasVSX())) {
     778           0 :     return fastEmitInst_r(PPC::XVCVSPUXWS, &PPC::VSRCRegClass, Op0, Op0IsKill);
     779             :   }
     780           0 :   if ((PPCSubTarget->hasAltivec())) {
     781           0 :     return fastEmitInst_r(PPC::VCTUXS_0, &PPC::VRRCRegClass, Op0, Op0IsKill);
     782             :   }
     783             :   return 0;
     784             : }
     785             : 
     786             : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     787           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     788             :     return 0;
     789           0 :   if ((PPCSubTarget->hasVSX())) {
     790             :     return fastEmitInst_r(PPC::XVCVDPUXDS, &PPC::VSRCRegClass, Op0, Op0IsKill);
     791             :   }
     792             :   return 0;
     793             : }
     794             : 
     795           0 : unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     796           0 :   switch (VT.SimpleTy) {
     797           0 :   case MVT::f32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
     798           0 :   case MVT::f64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_r(RetVT, Op0, Op0IsKill);
     799           0 :   case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     800           0 :   case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     801             :   default: return 0;
     802             :   }
     803             : }
     804             : 
     805             : // FastEmit functions for ISD::FROUND.
     806             : 
     807             : unsigned fastEmit_ISD_FROUND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     808           0 :   if (RetVT.SimpleTy != MVT::f32)
     809             :     return 0;
     810           0 :   if ((PPCSubTarget->hasFPU())) {
     811             :     return fastEmitInst_r(PPC::FRINS, &PPC::F4RCRegClass, Op0, Op0IsKill);
     812             :   }
     813             :   return 0;
     814             : }
     815             : 
     816           0 : unsigned fastEmit_ISD_FROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     817           0 :   if (RetVT.SimpleTy != MVT::f64)
     818             :     return 0;
     819           0 :   if ((PPCSubTarget->hasVSX())) {
     820           0 :     return fastEmitInst_r(PPC::XSRDPI, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     821             :   }
     822           0 :   if ((PPCSubTarget->hasFPU())) {
     823           0 :     return fastEmitInst_r(PPC::FRIND, &PPC::F8RCRegClass, Op0, Op0IsKill);
     824             :   }
     825             :   return 0;
     826             : }
     827             : 
     828           0 : unsigned fastEmit_ISD_FROUND_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     829           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     830             :     return 0;
     831           0 :   if ((PPCSubTarget->hasVSX())) {
     832           0 :     return fastEmitInst_r(PPC::XVRSPI, &PPC::VSRCRegClass, Op0, Op0IsKill);
     833             :   }
     834           0 :   if ((PPCSubTarget->hasQPX())) {
     835           0 :     return fastEmitInst_r(PPC::QVFRINs, &PPC::QSRCRegClass, Op0, Op0IsKill);
     836             :   }
     837             :   return 0;
     838             : }
     839             : 
     840             : unsigned fastEmit_ISD_FROUND_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     841           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     842             :     return 0;
     843           0 :   if ((PPCSubTarget->hasVSX())) {
     844             :     return fastEmitInst_r(PPC::XVRDPI, &PPC::VSRCRegClass, Op0, Op0IsKill);
     845             :   }
     846             :   return 0;
     847             : }
     848             : 
     849             : unsigned fastEmit_ISD_FROUND_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     850           0 :   if (RetVT.SimpleTy != MVT::v4f64)
     851             :     return 0;
     852           0 :   if ((PPCSubTarget->hasQPX())) {
     853             :     return fastEmitInst_r(PPC::QVFRIN, &PPC::QFRCRegClass, Op0, Op0IsKill);
     854             :   }
     855             :   return 0;
     856             : }
     857             : 
     858           0 : unsigned fastEmit_ISD_FROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     859           0 :   switch (VT.SimpleTy) {
     860           0 :   case MVT::f32: return fastEmit_ISD_FROUND_MVT_f32_r(RetVT, Op0, Op0IsKill);
     861           0 :   case MVT::f64: return fastEmit_ISD_FROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
     862           0 :   case MVT::v4f32: return fastEmit_ISD_FROUND_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     863           0 :   case MVT::v2f64: return fastEmit_ISD_FROUND_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     864           0 :   case MVT::v4f64: return fastEmit_ISD_FROUND_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
     865             :   default: return 0;
     866             :   }
     867             : }
     868             : 
     869             : // FastEmit functions for ISD::FSQRT.
     870             : 
     871           0 : unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     872           0 :   if (RetVT.SimpleTy != MVT::f32)
     873             :     return 0;
     874           0 :   if ((PPCSubTarget->hasP8Vector())) {
     875           0 :     return fastEmitInst_r(PPC::XSSQRTSP, &PPC::VSSRCRegClass, Op0, Op0IsKill);
     876             :   }
     877           0 :   if ((PPCSubTarget->hasFPU())) {
     878           0 :     return fastEmitInst_r(PPC::FSQRTS, &PPC::F4RCRegClass, Op0, Op0IsKill);
     879             :   }
     880             :   return 0;
     881             : }
     882             : 
     883           0 : unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     884           0 :   if (RetVT.SimpleTy != MVT::f64)
     885             :     return 0;
     886           0 :   if ((PPCSubTarget->hasVSX())) {
     887           0 :     return fastEmitInst_r(PPC::XSSQRTDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     888             :   }
     889           0 :   if ((PPCSubTarget->hasFPU())) {
     890           0 :     return fastEmitInst_r(PPC::FSQRT, &PPC::F8RCRegClass, Op0, Op0IsKill);
     891             :   }
     892             :   return 0;
     893             : }
     894             : 
     895             : unsigned fastEmit_ISD_FSQRT_MVT_f128_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     896           0 :   if (RetVT.SimpleTy != MVT::f128)
     897             :     return 0;
     898           0 :   if ((PPCSubTarget->hasP9Vector())) {
     899             :     return fastEmitInst_r(PPC::XSSQRTQP, &PPC::VRRCRegClass, Op0, Op0IsKill);
     900             :   }
     901             :   return 0;
     902             : }
     903             : 
     904             : unsigned fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     905           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     906             :     return 0;
     907           0 :   if ((PPCSubTarget->hasVSX())) {
     908             :     return fastEmitInst_r(PPC::XVSQRTSP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     909             :   }
     910             :   return 0;
     911             : }
     912             : 
     913             : unsigned fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     914           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     915             :     return 0;
     916           0 :   if ((PPCSubTarget->hasVSX())) {
     917             :     return fastEmitInst_r(PPC::XVSQRTDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     918             :   }
     919             :   return 0;
     920             : }
     921             : 
     922           0 : unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     923           0 :   switch (VT.SimpleTy) {
     924           0 :   case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill);
     925           0 :   case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0, Op0IsKill);
     926           0 :   case MVT::f128: return fastEmit_ISD_FSQRT_MVT_f128_r(RetVT, Op0, Op0IsKill);
     927           0 :   case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     928           0 :   case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     929             :   default: return 0;
     930             :   }
     931             : }
     932             : 
     933             : // FastEmit functions for ISD::FTRUNC.
     934             : 
     935             : unsigned fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     936           0 :   if (RetVT.SimpleTy != MVT::f32)
     937             :     return 0;
     938           0 :   if ((PPCSubTarget->hasFPU())) {
     939             :     return fastEmitInst_r(PPC::FRIZS, &PPC::F4RCRegClass, Op0, Op0IsKill);
     940             :   }
     941             :   return 0;
     942             : }
     943             : 
     944           0 : unsigned fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     945           0 :   if (RetVT.SimpleTy != MVT::f64)
     946             :     return 0;
     947           0 :   if ((PPCSubTarget->hasVSX())) {
     948           0 :     return fastEmitInst_r(PPC::XSRDPIZ, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     949             :   }
     950           0 :   if ((PPCSubTarget->hasFPU())) {
     951           0 :     return fastEmitInst_r(PPC::FRIZD, &PPC::F8RCRegClass, Op0, Op0IsKill);
     952             :   }
     953             :   return 0;
     954             : }
     955             : 
     956           0 : unsigned fastEmit_ISD_FTRUNC_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     957           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     958             :     return 0;
     959           0 :   if ((PPCSubTarget->hasVSX())) {
     960           0 :     return fastEmitInst_r(PPC::XVRSPIZ, &PPC::VSRCRegClass, Op0, Op0IsKill);
     961             :   }
     962           0 :   if ((PPCSubTarget->hasAltivec())) {
     963           0 :     return fastEmitInst_r(PPC::VRFIZ, &PPC::VRRCRegClass, Op0, Op0IsKill);
     964             :   }
     965           0 :   if ((PPCSubTarget->hasQPX())) {
     966           0 :     return fastEmitInst_r(PPC::QVFRIZs, &PPC::QSRCRegClass, Op0, Op0IsKill);
     967             :   }
     968             :   return 0;
     969             : }
     970             : 
     971             : unsigned fastEmit_ISD_FTRUNC_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     972           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     973             :     return 0;
     974           0 :   if ((PPCSubTarget->hasVSX())) {
     975             :     return fastEmitInst_r(PPC::XVRDPIZ, &PPC::VSRCRegClass, Op0, Op0IsKill);
     976             :   }
     977             :   return 0;
     978             : }
     979             : 
     980             : unsigned fastEmit_ISD_FTRUNC_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     981           0 :   if (RetVT.SimpleTy != MVT::v4f64)
     982             :     return 0;
     983           0 :   if ((PPCSubTarget->hasQPX())) {
     984             :     return fastEmitInst_r(PPC::QVFRIZ, &PPC::QFRCRegClass, Op0, Op0IsKill);
     985             :   }
     986             :   return 0;
     987             : }
     988             : 
     989           0 : unsigned fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     990           0 :   switch (VT.SimpleTy) {
     991           0 :   case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0, Op0IsKill);
     992           0 :   case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0, Op0IsKill);
     993           0 :   case MVT::v4f32: return fastEmit_ISD_FTRUNC_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     994           0 :   case MVT::v2f64: return fastEmit_ISD_FTRUNC_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     995           0 :   case MVT::v4f64: return fastEmit_ISD_FTRUNC_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
     996             :   default: return 0;
     997             :   }
     998             : }
     999             : 
    1000             : // FastEmit functions for ISD::SCALAR_TO_VECTOR.
    1001             : 
    1002             : unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1003           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1004             :     return 0;
    1005           0 :   if ((PPCSubTarget->hasP9Vector())) {
    1006             :     return fastEmitInst_r(PPC::MTVSRWS, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1007             :   }
    1008             :   return 0;
    1009             : }
    1010             : 
    1011           0 : unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1012           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1013             :     return 0;
    1014           0 :   if ((PPCSubTarget->hasP8Vector()) && (!PPCSubTarget->isLittleEndian())) {
    1015           0 :     return fastEmitInst_r(PPC::XSCVDPSPN, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1016             :   }
    1017             :   return 0;
    1018             : }
    1019             : 
    1020           0 : unsigned fastEmit_ISD_SCALAR_TO_VECTOR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1021           0 :   switch (VT.SimpleTy) {
    1022           0 :   case MVT::i32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1023           0 :   case MVT::f32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1024             :   default: return 0;
    1025             :   }
    1026             : }
    1027             : 
    1028             : // FastEmit functions for ISD::SIGN_EXTEND.
    1029             : 
    1030             : unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1031           4 :   if (RetVT.SimpleTy != MVT::i64)
    1032             :     return 0;
    1033             :   return fastEmitInst_r(PPC::EXTSW_32_64, &PPC::G8RCRegClass, Op0, Op0IsKill);
    1034             : }
    1035             : 
    1036             : unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1037           5 :   switch (VT.SimpleTy) {
    1038           4 :   case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1039             :   default: return 0;
    1040             :   }
    1041             : }
    1042             : 
    1043             : // FastEmit functions for ISD::SINT_TO_FP.
    1044             : 
    1045             : unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
    1046           3 :   if ((PPCSubTarget->hasSPE())) {
    1047             :     return fastEmitInst_r(PPC::EFSCFSI, &PPC::SPE4RCRegClass, Op0, Op0IsKill);
    1048             :   }
    1049             :   return 0;
    1050             : }
    1051             : 
    1052             : unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
    1053           4 :   if ((PPCSubTarget->hasSPE())) {
    1054             :     return fastEmitInst_r(PPC::EFDCFSI, &PPC::SPERCRegClass, Op0, Op0IsKill);
    1055             :   }
    1056             :   return 0;
    1057             : }
    1058             : 
    1059           7 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1060           7 : switch (RetVT.SimpleTy) {
    1061           3 :   case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0, Op0IsKill);
    1062           4 :   case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0, Op0IsKill);
    1063             :   default: return 0;
    1064             : }
    1065             : }
    1066             : 
    1067           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1068           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1069             :     return 0;
    1070           0 :   if ((PPCSubTarget->hasVSX())) {
    1071           0 :     return fastEmitInst_r(PPC::XVCVSXWSP, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1072             :   }
    1073           0 :   if ((PPCSubTarget->hasAltivec())) {
    1074           0 :     return fastEmitInst_r(PPC::VCFSX_0, &PPC::VRRCRegClass, Op0, Op0IsKill);
    1075             :   }
    1076             :   return 0;
    1077             : }
    1078             : 
    1079             : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1080           1 :   if (RetVT.SimpleTy != MVT::v2f64)
    1081             :     return 0;
    1082           1 :   if ((PPCSubTarget->hasVSX())) {
    1083             :     return fastEmitInst_r(PPC::XVCVSXDDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1084             :   }
    1085             :   return 0;
    1086             : }
    1087             : 
    1088          15 : unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1089          15 :   switch (VT.SimpleTy) {
    1090           7 :   case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1091           0 :   case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    1092           1 :   case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
    1093             :   default: return 0;
    1094             :   }
    1095             : }
    1096             : 
    1097             : // FastEmit functions for ISD::TRUNCATE.
    1098             : 
    1099             : unsigned fastEmit_ISD_TRUNCATE_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1100           0 :   if (RetVT.SimpleTy != MVT::i1)
    1101             :     return 0;
    1102             :   return fastEmitInst_r(PPC::ANDIo_1_GT_BIT, &PPC::CRBITRCRegClass, Op0, Op0IsKill);
    1103             : }
    1104             : 
    1105             : unsigned fastEmit_ISD_TRUNCATE_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1106           0 :   if (RetVT.SimpleTy != MVT::i1)
    1107             :     return 0;
    1108             :   return fastEmitInst_r(PPC::ANDIo_1_GT_BIT8, &PPC::CRBITRCRegClass, Op0, Op0IsKill);
    1109             : }
    1110             : 
    1111           0 : unsigned fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1112           0 :   switch (VT.SimpleTy) {
    1113           0 :   case MVT::i32: return fastEmit_ISD_TRUNCATE_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1114           0 :   case MVT::i64: return fastEmit_ISD_TRUNCATE_MVT_i64_r(RetVT, Op0, Op0IsKill);
    1115             :   default: return 0;
    1116             :   }
    1117             : }
    1118             : 
    1119             : // FastEmit functions for ISD::UINT_TO_FP.
    1120             : 
    1121             : unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
    1122           0 :   if ((PPCSubTarget->hasSPE())) {
    1123             :     return fastEmitInst_r(PPC::EFSCFUI, &PPC::SPE4RCRegClass, Op0, Op0IsKill);
    1124             :   }
    1125             :   return 0;
    1126             : }
    1127             : 
    1128             : unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
    1129           0 :   if ((PPCSubTarget->hasSPE())) {
    1130             :     return fastEmitInst_r(PPC::EFDCFUI, &PPC::SPERCRegClass, Op0, Op0IsKill);
    1131             :   }
    1132             :   return 0;
    1133             : }
    1134             : 
    1135           0 : unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1136           0 : switch (RetVT.SimpleTy) {
    1137           0 :   case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0, Op0IsKill);
    1138           0 :   case MVT::f64: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(Op0, Op0IsKill);
    1139             :   default: return 0;
    1140             : }
    1141             : }
    1142             : 
    1143           0 : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1144           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1145             :     return 0;
    1146           0 :   if ((PPCSubTarget->hasVSX())) {
    1147           0 :     return fastEmitInst_r(PPC::XVCVUXWSP, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1148             :   }
    1149           0 :   if ((PPCSubTarget->hasAltivec())) {
    1150           0 :     return fastEmitInst_r(PPC::VCFUX_0, &PPC::VRRCRegClass, Op0, Op0IsKill);
    1151             :   }
    1152             :   return 0;
    1153             : }
    1154             : 
    1155             : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1156           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1157             :     return 0;
    1158           0 :   if ((PPCSubTarget->hasVSX())) {
    1159             :     return fastEmitInst_r(PPC::XVCVUXDDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1160             :   }
    1161             :   return 0;
    1162             : }
    1163             : 
    1164           0 : unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1165           0 :   switch (VT.SimpleTy) {
    1166           0 :   case MVT::i32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1167           0 :   case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    1168           0 :   case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
    1169             :   default: return 0;
    1170             :   }
    1171             : }
    1172             : 
    1173             : // FastEmit functions for PPCISD::FCFID.
    1174             : 
    1175           0 : unsigned fastEmit_PPCISD_FCFID_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1176           0 :   if (RetVT.SimpleTy != MVT::f64)
    1177             :     return 0;
    1178           0 :   if ((PPCSubTarget->hasVSX())) {
    1179           0 :     return fastEmitInst_r(PPC::XSCVSXDDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1180             :   }
    1181           0 :   return fastEmitInst_r(PPC::FCFID, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1182             : }
    1183             : 
    1184             : unsigned fastEmit_PPCISD_FCFID_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1185           0 :   switch (VT.SimpleTy) {
    1186           0 :   case MVT::f64: return fastEmit_PPCISD_FCFID_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1187             :   default: return 0;
    1188             :   }
    1189             : }
    1190             : 
    1191             : // FastEmit functions for PPCISD::FCFIDS.
    1192             : 
    1193           0 : unsigned fastEmit_PPCISD_FCFIDS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1194           0 :   if (RetVT.SimpleTy != MVT::f32)
    1195             :     return 0;
    1196           0 :   if ((PPCSubTarget->hasP8Vector())) {
    1197           0 :     return fastEmitInst_r(PPC::XSCVSXDSP, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1198             :   }
    1199           0 :   return fastEmitInst_r(PPC::FCFIDS, &PPC::F4RCRegClass, Op0, Op0IsKill);
    1200             : }
    1201             : 
    1202             : unsigned fastEmit_PPCISD_FCFIDS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1203           0 :   switch (VT.SimpleTy) {
    1204           0 :   case MVT::f64: return fastEmit_PPCISD_FCFIDS_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1205             :   default: return 0;
    1206             :   }
    1207             : }
    1208             : 
    1209             : // FastEmit functions for PPCISD::FCFIDU.
    1210             : 
    1211           0 : unsigned fastEmit_PPCISD_FCFIDU_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1212           0 :   if (RetVT.SimpleTy != MVT::f64)
    1213             :     return 0;
    1214           0 :   if ((PPCSubTarget->hasVSX())) {
    1215           0 :     return fastEmitInst_r(PPC::XSCVUXDDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1216             :   }
    1217           0 :   return fastEmitInst_r(PPC::FCFIDU, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1218             : }
    1219             : 
    1220             : unsigned fastEmit_PPCISD_FCFIDU_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1221           0 :   switch (VT.SimpleTy) {
    1222           0 :   case MVT::f64: return fastEmit_PPCISD_FCFIDU_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1223             :   default: return 0;
    1224             :   }
    1225             : }
    1226             : 
    1227             : // FastEmit functions for PPCISD::FCFIDUS.
    1228             : 
    1229           0 : unsigned fastEmit_PPCISD_FCFIDUS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1230           0 :   if (RetVT.SimpleTy != MVT::f32)
    1231             :     return 0;
    1232           0 :   if ((PPCSubTarget->hasP8Vector())) {
    1233           0 :     return fastEmitInst_r(PPC::XSCVUXDSP, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1234             :   }
    1235           0 :   return fastEmitInst_r(PPC::FCFIDUS, &PPC::F4RCRegClass, Op0, Op0IsKill);
    1236             : }
    1237             : 
    1238             : unsigned fastEmit_PPCISD_FCFIDUS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1239           0 :   switch (VT.SimpleTy) {
    1240           0 :   case MVT::f64: return fastEmit_PPCISD_FCFIDUS_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1241             :   default: return 0;
    1242             :   }
    1243             : }
    1244             : 
    1245             : // FastEmit functions for PPCISD::FCTIDUZ.
    1246             : 
    1247             : unsigned fastEmit_PPCISD_FCTIDUZ_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1248           0 :   if (RetVT.SimpleTy != MVT::f32)
    1249             :     return 0;
    1250           0 :   if ((PPCSubTarget->hasVSX())) {
    1251             :     return fastEmitInst_r(PPC::XSCVDPUXDSs, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1252             :   }
    1253             :   return 0;
    1254             : }
    1255             : 
    1256           0 : unsigned fastEmit_PPCISD_FCTIDUZ_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1257           0 :   if (RetVT.SimpleTy != MVT::f64)
    1258             :     return 0;
    1259           0 :   if ((PPCSubTarget->hasVSX())) {
    1260           0 :     return fastEmitInst_r(PPC::XSCVDPUXDS, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1261             :   }
    1262           0 :   return fastEmitInst_r(PPC::FCTIDUZ, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1263             : }
    1264             : 
    1265           0 : unsigned fastEmit_PPCISD_FCTIDUZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1266           0 :   switch (VT.SimpleTy) {
    1267           0 :   case MVT::f32: return fastEmit_PPCISD_FCTIDUZ_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1268           0 :   case MVT::f64: return fastEmit_PPCISD_FCTIDUZ_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1269             :   default: return 0;
    1270             :   }
    1271             : }
    1272             : 
    1273             : // FastEmit functions for PPCISD::FCTIDZ.
    1274             : 
    1275             : unsigned fastEmit_PPCISD_FCTIDZ_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1276           0 :   if (RetVT.SimpleTy != MVT::f32)
    1277             :     return 0;
    1278           0 :   if ((PPCSubTarget->hasVSX())) {
    1279             :     return fastEmitInst_r(PPC::XSCVDPSXDSs, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1280             :   }
    1281             :   return 0;
    1282             : }
    1283             : 
    1284           0 : unsigned fastEmit_PPCISD_FCTIDZ_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1285           0 :   if (RetVT.SimpleTy != MVT::f64)
    1286             :     return 0;
    1287           0 :   if ((PPCSubTarget->hasVSX())) {
    1288           0 :     return fastEmitInst_r(PPC::XSCVDPSXDS, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1289             :   }
    1290           0 :   return fastEmitInst_r(PPC::FCTIDZ, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1291             : }
    1292             : 
    1293           0 : unsigned fastEmit_PPCISD_FCTIDZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1294           0 :   switch (VT.SimpleTy) {
    1295           0 :   case MVT::f32: return fastEmit_PPCISD_FCTIDZ_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1296           0 :   case MVT::f64: return fastEmit_PPCISD_FCTIDZ_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1297             :   default: return 0;
    1298             :   }
    1299             : }
    1300             : 
    1301             : // FastEmit functions for PPCISD::FCTIWUZ.
    1302             : 
    1303             : unsigned fastEmit_PPCISD_FCTIWUZ_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1304           0 :   if (RetVT.SimpleTy != MVT::f32)
    1305             :     return 0;
    1306           0 :   if ((PPCSubTarget->hasVSX())) {
    1307             :     return fastEmitInst_r(PPC::XSCVDPUXWSs, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1308             :   }
    1309             :   return 0;
    1310             : }
    1311             : 
    1312           0 : unsigned fastEmit_PPCISD_FCTIWUZ_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1313           0 :   if (RetVT.SimpleTy != MVT::f64)
    1314             :     return 0;
    1315           0 :   if ((PPCSubTarget->hasVSX())) {
    1316           0 :     return fastEmitInst_r(PPC::XSCVDPUXWS, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1317             :   }
    1318           0 :   return fastEmitInst_r(PPC::FCTIWUZ, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1319             : }
    1320             : 
    1321           0 : unsigned fastEmit_PPCISD_FCTIWUZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1322           0 :   switch (VT.SimpleTy) {
    1323           0 :   case MVT::f32: return fastEmit_PPCISD_FCTIWUZ_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1324           0 :   case MVT::f64: return fastEmit_PPCISD_FCTIWUZ_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1325             :   default: return 0;
    1326             :   }
    1327             : }
    1328             : 
    1329             : // FastEmit functions for PPCISD::FCTIWZ.
    1330             : 
    1331             : unsigned fastEmit_PPCISD_FCTIWZ_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1332           0 :   if (RetVT.SimpleTy != MVT::f32)
    1333             :     return 0;
    1334           0 :   if ((PPCSubTarget->hasVSX())) {
    1335             :     return fastEmitInst_r(PPC::XSCVDPSXWSs, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1336             :   }
    1337             :   return 0;
    1338             : }
    1339             : 
    1340           0 : unsigned fastEmit_PPCISD_FCTIWZ_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1341           0 :   if (RetVT.SimpleTy != MVT::f64)
    1342             :     return 0;
    1343           0 :   if ((PPCSubTarget->hasVSX())) {
    1344           0 :     return fastEmitInst_r(PPC::XSCVDPSXWS, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1345             :   }
    1346           0 :   if ((PPCSubTarget->hasFPU())) {
    1347           0 :     return fastEmitInst_r(PPC::FCTIWZ, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1348             :   }
    1349             :   return 0;
    1350             : }
    1351             : 
    1352           0 : unsigned fastEmit_PPCISD_FCTIWZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1353           0 :   switch (VT.SimpleTy) {
    1354           0 :   case MVT::f32: return fastEmit_PPCISD_FCTIWZ_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1355           0 :   case MVT::f64: return fastEmit_PPCISD_FCTIWZ_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1356             :   default: return 0;
    1357             :   }
    1358             : }
    1359             : 
    1360             : // FastEmit functions for PPCISD::FRE.
    1361             : 
    1362           0 : unsigned fastEmit_PPCISD_FRE_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1363           0 :   if (RetVT.SimpleTy != MVT::f32)
    1364             :     return 0;
    1365           0 :   if ((PPCSubTarget->hasP8Vector())) {
    1366           0 :     return fastEmitInst_r(PPC::XSRESP, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1367             :   }
    1368           0 :   if ((PPCSubTarget->hasFPU())) {
    1369           0 :     return fastEmitInst_r(PPC::FRES, &PPC::F4RCRegClass, Op0, Op0IsKill);
    1370             :   }
    1371             :   return 0;
    1372             : }
    1373             : 
    1374           0 : unsigned fastEmit_PPCISD_FRE_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1375           0 :   if (RetVT.SimpleTy != MVT::f64)
    1376             :     return 0;
    1377           0 :   if ((PPCSubTarget->hasVSX())) {
    1378           0 :     return fastEmitInst_r(PPC::XSREDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1379             :   }
    1380           0 :   if ((PPCSubTarget->hasFPU())) {
    1381           0 :     return fastEmitInst_r(PPC::FRE, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1382             :   }
    1383             :   return 0;
    1384             : }
    1385             : 
    1386           0 : unsigned fastEmit_PPCISD_FRE_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1387           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1388             :     return 0;
    1389           0 :   if ((PPCSubTarget->hasVSX())) {
    1390           0 :     return fastEmitInst_r(PPC::XVRESP, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1391             :   }
    1392           0 :   if ((PPCSubTarget->hasAltivec())) {
    1393           0 :     return fastEmitInst_r(PPC::VREFP, &PPC::VRRCRegClass, Op0, Op0IsKill);
    1394             :   }
    1395           0 :   if ((PPCSubTarget->hasQPX())) {
    1396           0 :     return fastEmitInst_r(PPC::QVFRESs, &PPC::QSRCRegClass, Op0, Op0IsKill);
    1397             :   }
    1398             :   return 0;
    1399             : }
    1400             : 
    1401             : unsigned fastEmit_PPCISD_FRE_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1402           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1403             :     return 0;
    1404           0 :   if ((PPCSubTarget->hasVSX())) {
    1405             :     return fastEmitInst_r(PPC::XVREDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1406             :   }
    1407             :   return 0;
    1408             : }
    1409             : 
    1410             : unsigned fastEmit_PPCISD_FRE_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1411           0 :   if (RetVT.SimpleTy != MVT::v4f64)
    1412             :     return 0;
    1413           0 :   if ((PPCSubTarget->hasQPX())) {
    1414             :     return fastEmitInst_r(PPC::QVFRE, &PPC::QFRCRegClass, Op0, Op0IsKill);
    1415             :   }
    1416             :   return 0;
    1417             : }
    1418             : 
    1419           0 : unsigned fastEmit_PPCISD_FRE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1420           0 :   switch (VT.SimpleTy) {
    1421           0 :   case MVT::f32: return fastEmit_PPCISD_FRE_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1422           0 :   case MVT::f64: return fastEmit_PPCISD_FRE_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1423           0 :   case MVT::v4f32: return fastEmit_PPCISD_FRE_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
    1424           0 :   case MVT::v2f64: return fastEmit_PPCISD_FRE_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
    1425           0 :   case MVT::v4f64: return fastEmit_PPCISD_FRE_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
    1426             :   default: return 0;
    1427             :   }
    1428             : }
    1429             : 
    1430             : // FastEmit functions for PPCISD::FRSQRTE.
    1431             : 
    1432           0 : unsigned fastEmit_PPCISD_FRSQRTE_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1433           0 :   if (RetVT.SimpleTy != MVT::f32)
    1434             :     return 0;
    1435           0 :   if ((PPCSubTarget->hasP8Vector())) {
    1436           0 :     return fastEmitInst_r(PPC::XSRSQRTESP, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1437             :   }
    1438           0 :   if ((PPCSubTarget->hasFPU())) {
    1439           0 :     return fastEmitInst_r(PPC::FRSQRTES, &PPC::F4RCRegClass, Op0, Op0IsKill);
    1440             :   }
    1441             :   return 0;
    1442             : }
    1443             : 
    1444           0 : unsigned fastEmit_PPCISD_FRSQRTE_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1445           0 :   if (RetVT.SimpleTy != MVT::f64)
    1446             :     return 0;
    1447           0 :   if ((PPCSubTarget->hasVSX())) {
    1448           0 :     return fastEmitInst_r(PPC::XSRSQRTEDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1449             :   }
    1450           0 :   if ((PPCSubTarget->hasFPU())) {
    1451           0 :     return fastEmitInst_r(PPC::FRSQRTE, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1452             :   }
    1453             :   return 0;
    1454             : }
    1455             : 
    1456           0 : unsigned fastEmit_PPCISD_FRSQRTE_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1457           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1458             :     return 0;
    1459           0 :   if ((PPCSubTarget->hasVSX())) {
    1460           0 :     return fastEmitInst_r(PPC::XVRSQRTESP, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1461             :   }
    1462           0 :   if ((PPCSubTarget->hasAltivec())) {
    1463           0 :     return fastEmitInst_r(PPC::VRSQRTEFP, &PPC::VRRCRegClass, Op0, Op0IsKill);
    1464             :   }
    1465           0 :   if ((PPCSubTarget->hasQPX())) {
    1466           0 :     return fastEmitInst_r(PPC::QVFRSQRTESs, &PPC::QSRCRegClass, Op0, Op0IsKill);
    1467             :   }
    1468             :   return 0;
    1469             : }
    1470             : 
    1471             : unsigned fastEmit_PPCISD_FRSQRTE_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1472           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1473             :     return 0;
    1474           0 :   if ((PPCSubTarget->hasVSX())) {
    1475             :     return fastEmitInst_r(PPC::XVRSQRTEDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1476             :   }
    1477             :   return 0;
    1478             : }
    1479             : 
    1480             : unsigned fastEmit_PPCISD_FRSQRTE_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1481           0 :   if (RetVT.SimpleTy != MVT::v4f64)
    1482             :     return 0;
    1483           0 :   if ((PPCSubTarget->hasQPX())) {
    1484             :     return fastEmitInst_r(PPC::QVFRSQRTE, &PPC::QFRCRegClass, Op0, Op0IsKill);
    1485             :   }
    1486             :   return 0;
    1487             : }
    1488             : 
    1489           0 : unsigned fastEmit_PPCISD_FRSQRTE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1490           0 :   switch (VT.SimpleTy) {
    1491           0 :   case MVT::f32: return fastEmit_PPCISD_FRSQRTE_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1492           0 :   case MVT::f64: return fastEmit_PPCISD_FRSQRTE_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1493           0 :   case MVT::v4f32: return fastEmit_PPCISD_FRSQRTE_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
    1494           0 :   case MVT::v2f64: return fastEmit_PPCISD_FRSQRTE_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
    1495           0 :   case MVT::v4f64: return fastEmit_PPCISD_FRSQRTE_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
    1496             :   default: return 0;
    1497             :   }
    1498             : }
    1499             : 
    1500             : // FastEmit functions for PPCISD::MFVSR.
    1501             : 
    1502             : unsigned fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i32_r(unsigned Op0, bool Op0IsKill) {
    1503           0 :   if ((PPCSubTarget->hasDirectMove())) {
    1504             :     return fastEmitInst_r(PPC::MFVSRWZ, &PPC::GPRCRegClass, Op0, Op0IsKill);
    1505             :   }
    1506             :   return 0;
    1507             : }
    1508             : 
    1509             : unsigned fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i64_r(unsigned Op0, bool Op0IsKill) {
    1510           0 :   if ((PPCSubTarget->hasDirectMove())) {
    1511             :     return fastEmitInst_r(PPC::MFVSRD, &PPC::G8RCRegClass, Op0, Op0IsKill);
    1512             :   }
    1513             :   return 0;
    1514             : }
    1515             : 
    1516           0 : unsigned fastEmit_PPCISD_MFVSR_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1517           0 : switch (RetVT.SimpleTy) {
    1518           0 :   case MVT::i32: return fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i32_r(Op0, Op0IsKill);
    1519           0 :   case MVT::i64: return fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i64_r(Op0, Op0IsKill);
    1520             :   default: return 0;
    1521             : }
    1522             : }
    1523             : 
    1524             : unsigned fastEmit_PPCISD_MFVSR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1525           0 :   switch (VT.SimpleTy) {
    1526           0 :   case MVT::f64: return fastEmit_PPCISD_MFVSR_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1527             :   default: return 0;
    1528             :   }
    1529             : }
    1530             : 
    1531             : // FastEmit functions for PPCISD::MTCTR.
    1532             : 
    1533             : unsigned fastEmit_PPCISD_MTCTR_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1534           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    1535             :     return 0;
    1536             :   return fastEmitInst_r(PPC::MTCTR, &PPC::GPRCRegClass, Op0, Op0IsKill);
    1537             : }
    1538             : 
    1539             : unsigned fastEmit_PPCISD_MTCTR_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1540           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    1541             :     return 0;
    1542             :   return fastEmitInst_r(PPC::MTCTR8, &PPC::G8RCRegClass, Op0, Op0IsKill);
    1543             : }
    1544             : 
    1545           0 : unsigned fastEmit_PPCISD_MTCTR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1546           0 :   switch (VT.SimpleTy) {
    1547           0 :   case MVT::i32: return fastEmit_PPCISD_MTCTR_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1548           0 :   case MVT::i64: return fastEmit_PPCISD_MTCTR_MVT_i64_r(RetVT, Op0, Op0IsKill);
    1549             :   default: return 0;
    1550             :   }
    1551             : }
    1552             : 
    1553             : // FastEmit functions for PPCISD::MTVSRA.
    1554             : 
    1555             : unsigned fastEmit_PPCISD_MTVSRA_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1556           0 :   if (RetVT.SimpleTy != MVT::f64)
    1557             :     return 0;
    1558           0 :   if ((PPCSubTarget->hasDirectMove())) {
    1559             :     return fastEmitInst_r(PPC::MTVSRWA, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1560             :   }
    1561             :   return 0;
    1562             : }
    1563             : 
    1564             : unsigned fastEmit_PPCISD_MTVSRA_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1565           0 :   if (RetVT.SimpleTy != MVT::f64)
    1566             :     return 0;
    1567           0 :   if ((PPCSubTarget->hasDirectMove())) {
    1568             :     return fastEmitInst_r(PPC::MTVSRD, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1569             :   }
    1570             :   return 0;
    1571             : }
    1572             : 
    1573           0 : unsigned fastEmit_PPCISD_MTVSRA_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1574           0 :   switch (VT.SimpleTy) {
    1575           0 :   case MVT::i32: return fastEmit_PPCISD_MTVSRA_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1576           0 :   case MVT::i64: return fastEmit_PPCISD_MTVSRA_MVT_i64_r(RetVT, Op0, Op0IsKill);
    1577             :   default: return 0;
    1578             :   }
    1579             : }
    1580             : 
    1581             : // FastEmit functions for PPCISD::MTVSRZ.
    1582             : 
    1583             : unsigned fastEmit_PPCISD_MTVSRZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1584           0 :   if (RetVT.SimpleTy != MVT::f64)
    1585             :     return 0;
    1586           0 :   if ((PPCSubTarget->hasDirectMove())) {
    1587             :     return fastEmitInst_r(PPC::MTVSRWZ, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1588             :   }
    1589             :   return 0;
    1590             : }
    1591             : 
    1592           0 : unsigned fastEmit_PPCISD_MTVSRZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1593           0 :   switch (VT.SimpleTy) {
    1594           0 :   case MVT::i32: return fastEmit_PPCISD_MTVSRZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1595             :   default: return 0;
    1596             :   }
    1597             : }
    1598             : 
    1599             : // FastEmit functions for PPCISD::SExtVElems.
    1600             : 
    1601             : unsigned fastEmit_PPCISD_SExtVElems_MVT_v16i8_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
    1602           0 :   if ((PPCSubTarget->hasP9Altivec())) {
    1603             :     return fastEmitInst_r(PPC::VEXTSB2W, &PPC::VRRCRegClass, Op0, Op0IsKill);
    1604             :   }
    1605             :   return 0;
    1606             : }
    1607             : 
    1608             : unsigned fastEmit_PPCISD_SExtVElems_MVT_v16i8_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
    1609           0 :   if ((PPCSubTarget->hasP9Altivec())) {
    1610             :     return fastEmitInst_r(PPC::VEXTSB2D, &PPC::VRRCRegClass, Op0, Op0IsKill);
    1611             :   }
    1612             :   return 0;
    1613             : }
    1614             : 
    1615           0 : unsigned fastEmit_PPCISD_SExtVElems_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1616           0 : switch (RetVT.SimpleTy) {
    1617           0 :   case MVT::v4i32: return fastEmit_PPCISD_SExtVElems_MVT_v16i8_MVT_v4i32_r(Op0, Op0IsKill);
    1618           0 :   case MVT::v2i64: return fastEmit_PPCISD_SExtVElems_MVT_v16i8_MVT_v2i64_r(Op0, Op0IsKill);
    1619             :   default: return 0;
    1620             : }
    1621             : }
    1622             : 
    1623             : unsigned fastEmit_PPCISD_SExtVElems_MVT_v8i16_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
    1624           0 :   if ((PPCSubTarget->hasP9Altivec())) {
    1625             :     return fastEmitInst_r(PPC::VEXTSH2W, &PPC::VRRCRegClass, Op0, Op0IsKill);
    1626             :   }
    1627             :   return 0;
    1628             : }
    1629             : 
    1630             : unsigned fastEmit_PPCISD_SExtVElems_MVT_v8i16_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
    1631           0 :   if ((PPCSubTarget->hasP9Altivec())) {
    1632             :     return fastEmitInst_r(PPC::VEXTSH2D, &PPC::VRRCRegClass, Op0, Op0IsKill);
    1633             :   }
    1634             :   return 0;
    1635             : }
    1636             : 
    1637           0 : unsigned fastEmit_PPCISD_SExtVElems_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1638           0 : switch (RetVT.SimpleTy) {
    1639           0 :   case MVT::v4i32: return fastEmit_PPCISD_SExtVElems_MVT_v8i16_MVT_v4i32_r(Op0, Op0IsKill);
    1640           0 :   case MVT::v2i64: return fastEmit_PPCISD_SExtVElems_MVT_v8i16_MVT_v2i64_r(Op0, Op0IsKill);
    1641             :   default: return 0;
    1642             : }
    1643             : }
    1644             : 
    1645             : unsigned fastEmit_PPCISD_SExtVElems_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1646           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1647             :     return 0;
    1648           0 :   if ((PPCSubTarget->hasP9Altivec())) {
    1649             :     return fastEmitInst_r(PPC::VEXTSW2D, &PPC::VRRCRegClass, Op0, Op0IsKill);
    1650             :   }
    1651             :   return 0;
    1652             : }
    1653             : 
    1654           0 : unsigned fastEmit_PPCISD_SExtVElems_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1655           0 :   switch (VT.SimpleTy) {
    1656           0 :   case MVT::v16i8: return fastEmit_PPCISD_SExtVElems_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1657           0 :   case MVT::v8i16: return fastEmit_PPCISD_SExtVElems_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    1658           0 :   case MVT::v4i32: return fastEmit_PPCISD_SExtVElems_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    1659             :   default: return 0;
    1660             :   }
    1661             : }
    1662             : 
    1663             : // FastEmit functions for PPCISD::XXREVERSE.
    1664             : 
    1665             : unsigned fastEmit_PPCISD_XXREVERSE_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1666           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1667             :     return 0;
    1668           0 :   if ((PPCSubTarget->hasP9Vector())) {
    1669             :     return fastEmitInst_r(PPC::XXBRW, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1670             :   }
    1671             :   return 0;
    1672             : }
    1673             : 
    1674             : unsigned fastEmit_PPCISD_XXREVERSE_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1675           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1676             :     return 0;
    1677           0 :   if ((PPCSubTarget->hasP9Vector())) {
    1678             :     return fastEmitInst_r(PPC::XXBRD, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1679             :   }
    1680             :   return 0;
    1681             : }
    1682             : 
    1683           0 : unsigned fastEmit_PPCISD_XXREVERSE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1684           0 :   switch (VT.SimpleTy) {
    1685           0 :   case MVT::v4i32: return fastEmit_PPCISD_XXREVERSE_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    1686           0 :   case MVT::v2i64: return fastEmit_PPCISD_XXREVERSE_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
    1687             :   default: return 0;
    1688             :   }
    1689             : }
    1690             : 
    1691             : // Top-level FastEmit function.
    1692             : 
    1693          42 : unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill) override {
    1694          42 :   switch (Opcode) {
    1695           1 :   case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0, Op0IsKill);
    1696           0 :   case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill);
    1697           0 :   case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill);
    1698           0 :   case ISD::CTTZ: return fastEmit_ISD_CTTZ_r(VT, RetVT, Op0, Op0IsKill);
    1699           0 :   case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill);
    1700           0 :   case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0, Op0IsKill);
    1701           0 :   case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0, Op0IsKill);
    1702           0 :   case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0, Op0IsKill);
    1703           0 :   case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill);
    1704           0 :   case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
    1705           0 :   case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill);
    1706          19 :   case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill);
    1707           0 :   case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill);
    1708           0 :   case ISD::FROUND: return fastEmit_ISD_FROUND_r(VT, RetVT, Op0, Op0IsKill);
    1709           0 :   case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill);
    1710           0 :   case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0, Op0IsKill);
    1711           0 :   case ISD::SCALAR_TO_VECTOR: return fastEmit_ISD_SCALAR_TO_VECTOR_r(VT, RetVT, Op0, Op0IsKill);
    1712           5 :   case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
    1713          15 :   case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill);
    1714           0 :   case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0, Op0IsKill);
    1715           0 :   case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill);
    1716           0 :   case PPCISD::FCFID: return fastEmit_PPCISD_FCFID_r(VT, RetVT, Op0, Op0IsKill);
    1717           0 :   case PPCISD::FCFIDS: return fastEmit_PPCISD_FCFIDS_r(VT, RetVT, Op0, Op0IsKill);
    1718           0 :   case PPCISD::FCFIDU: return fastEmit_PPCISD_FCFIDU_r(VT, RetVT, Op0, Op0IsKill);
    1719           0 :   case PPCISD::FCFIDUS: return fastEmit_PPCISD_FCFIDUS_r(VT, RetVT, Op0, Op0IsKill);
    1720           0 :   case PPCISD::FCTIDUZ: return fastEmit_PPCISD_FCTIDUZ_r(VT, RetVT, Op0, Op0IsKill);
    1721           0 :   case PPCISD::FCTIDZ: return fastEmit_PPCISD_FCTIDZ_r(VT, RetVT, Op0, Op0IsKill);
    1722           0 :   case PPCISD::FCTIWUZ: return fastEmit_PPCISD_FCTIWUZ_r(VT, RetVT, Op0, Op0IsKill);
    1723           0 :   case PPCISD::FCTIWZ: return fastEmit_PPCISD_FCTIWZ_r(VT, RetVT, Op0, Op0IsKill);
    1724           0 :   case PPCISD::FRE: return fastEmit_PPCISD_FRE_r(VT, RetVT, Op0, Op0IsKill);
    1725           0 :   case PPCISD::FRSQRTE: return fastEmit_PPCISD_FRSQRTE_r(VT, RetVT, Op0, Op0IsKill);
    1726           0 :   case PPCISD::MFVSR: return fastEmit_PPCISD_MFVSR_r(VT, RetVT, Op0, Op0IsKill);
    1727           0 :   case PPCISD::MTCTR: return fastEmit_PPCISD_MTCTR_r(VT, RetVT, Op0, Op0IsKill);
    1728           0 :   case PPCISD::MTVSRA: return fastEmit_PPCISD_MTVSRA_r(VT, RetVT, Op0, Op0IsKill);
    1729           0 :   case PPCISD::MTVSRZ: return fastEmit_PPCISD_MTVSRZ_r(VT, RetVT, Op0, Op0IsKill);
    1730           0 :   case PPCISD::SExtVElems: return fastEmit_PPCISD_SExtVElems_r(VT, RetVT, Op0, Op0IsKill);
    1731           0 :   case PPCISD::XXREVERSE: return fastEmit_PPCISD_XXREVERSE_r(VT, RetVT, Op0, Op0IsKill);
    1732             :   default: return 0;
    1733             :   }
    1734             : }
    1735             : 
    1736             : // FastEmit functions for ISD::ADD.
    1737             : 
    1738             : unsigned fastEmit_ISD_ADD_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1739           0 :   if (RetVT.SimpleTy != MVT::i1)
    1740             :     return 0;
    1741             :   return fastEmitInst_rr(PPC::CRXOR, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1742             : }
    1743             : 
    1744             : unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1745           0 :   if (RetVT.SimpleTy != MVT::i32)
    1746             :     return 0;
    1747             :   return fastEmitInst_rr(PPC::ADD4, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1748             : }
    1749             : 
    1750             : unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1751           0 :   if (RetVT.SimpleTy != MVT::i64)
    1752             :     return 0;
    1753             :   return fastEmitInst_rr(PPC::ADD8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1754             : }
    1755             : 
    1756             : unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1757           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1758             :     return 0;
    1759           0 :   if ((PPCSubTarget->hasAltivec())) {
    1760             :     return fastEmitInst_rr(PPC::VADDUBM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1761             :   }
    1762             :   return 0;
    1763             : }
    1764             : 
    1765             : unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1766           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1767             :     return 0;
    1768           0 :   if ((PPCSubTarget->hasAltivec())) {
    1769             :     return fastEmitInst_rr(PPC::VADDUHM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1770             :   }
    1771             :   return 0;
    1772             : }
    1773             : 
    1774             : unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1775           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1776             :     return 0;
    1777           0 :   if ((PPCSubTarget->hasAltivec())) {
    1778             :     return fastEmitInst_rr(PPC::VADDUWM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1779             :   }
    1780             :   return 0;
    1781             : }
    1782             : 
    1783             : unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1784           1 :   if (RetVT.SimpleTy != MVT::v2i64)
    1785             :     return 0;
    1786           1 :   if ((PPCSubTarget->hasP8Altivec())) {
    1787             :     return fastEmitInst_rr(PPC::VADDUDM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1788             :   }
    1789             :   return 0;
    1790             : }
    1791             : 
    1792             : unsigned fastEmit_ISD_ADD_MVT_v1i128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1793           0 :   if (RetVT.SimpleTy != MVT::v1i128)
    1794             :     return 0;
    1795           0 :   if ((PPCSubTarget->hasP8Altivec())) {
    1796             :     return fastEmitInst_rr(PPC::VADDUQM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1797             :   }
    1798             :   return 0;
    1799             : }
    1800             : 
    1801           1 : unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1802           1 :   switch (VT.SimpleTy) {
    1803           0 :   case MVT::i1: return fastEmit_ISD_ADD_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1804           0 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1805           0 :   case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1806           0 :   case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1807           0 :   case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1808           0 :   case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1809           1 :   case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1810           0 :   case MVT::v1i128: return fastEmit_ISD_ADD_MVT_v1i128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1811             :   default: return 0;
    1812             :   }
    1813             : }
    1814             : 
    1815             : // FastEmit functions for ISD::ADDC.
    1816             : 
    1817             : unsigned fastEmit_ISD_ADDC_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1818           0 :   if (RetVT.SimpleTy != MVT::i32)
    1819             :     return 0;
    1820             :   return fastEmitInst_rr(PPC::ADDC, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1821             : }
    1822             : 
    1823             : unsigned fastEmit_ISD_ADDC_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1824           0 :   if (RetVT.SimpleTy != MVT::i64)
    1825             :     return 0;
    1826             :   return fastEmitInst_rr(PPC::ADDC8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1827             : }
    1828             : 
    1829           0 : unsigned fastEmit_ISD_ADDC_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1830           0 :   switch (VT.SimpleTy) {
    1831           0 :   case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1832           0 :   case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1833             :   default: return 0;
    1834             :   }
    1835             : }
    1836             : 
    1837             : // FastEmit functions for ISD::ADDE.
    1838             : 
    1839             : unsigned fastEmit_ISD_ADDE_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1840           0 :   if (RetVT.SimpleTy != MVT::i32)
    1841             :     return 0;
    1842             :   return fastEmitInst_rr(PPC::ADDE, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1843             : }
    1844             : 
    1845             : unsigned fastEmit_ISD_ADDE_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1846           0 :   if (RetVT.SimpleTy != MVT::i64)
    1847             :     return 0;
    1848             :   return fastEmitInst_rr(PPC::ADDE8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1849             : }
    1850             : 
    1851           0 : unsigned fastEmit_ISD_ADDE_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1852           0 :   switch (VT.SimpleTy) {
    1853           0 :   case MVT::i32: return fastEmit_ISD_ADDE_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1854           0 :   case MVT::i64: return fastEmit_ISD_ADDE_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1855             :   default: return 0;
    1856             :   }
    1857             : }
    1858             : 
    1859             : // FastEmit functions for ISD::AND.
    1860             : 
    1861             : unsigned fastEmit_ISD_AND_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1862           0 :   if (RetVT.SimpleTy != MVT::i1)
    1863             :     return 0;
    1864             :   return fastEmitInst_rr(PPC::CRAND, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1865             : }
    1866             : 
    1867             : unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1868           0 :   if (RetVT.SimpleTy != MVT::i32)
    1869             :     return 0;
    1870             :   return fastEmitInst_rr(PPC::AND, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1871             : }
    1872             : 
    1873             : unsigned fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1874           1 :   if (RetVT.SimpleTy != MVT::i64)
    1875             :     return 0;
    1876             :   return fastEmitInst_rr(PPC::AND8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1877             : }
    1878             : 
    1879           2 : unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1880           2 :   if (RetVT.SimpleTy != MVT::v4i32)
    1881             :     return 0;
    1882           2 :   if ((PPCSubTarget->hasVSX())) {
    1883           4 :     return fastEmitInst_rr(PPC::XXLAND, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1884             :   }
    1885           0 :   if ((PPCSubTarget->hasAltivec())) {
    1886           0 :     return fastEmitInst_rr(PPC::VAND, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1887             :   }
    1888             :   return 0;
    1889             : }
    1890             : 
    1891           8 : unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1892           8 :   switch (VT.SimpleTy) {
    1893           0 :   case MVT::i1: return fastEmit_ISD_AND_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1894           0 :   case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1895           1 :   case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1896           2 :   case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1897             :   default: return 0;
    1898             :   }
    1899             : }
    1900             : 
    1901             : // FastEmit functions for ISD::BUILD_VECTOR.
    1902             : 
    1903           0 : unsigned fastEmit_ISD_BUILD_VECTOR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1904           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1905             :     return 0;
    1906           0 :   if ((PPCSubTarget->hasDirectMove()) && (!PPCSubTarget->isLittleEndian()) && (PPCSubTarget->isISA3_0())) {
    1907           0 :     return fastEmitInst_rr(PPC::MTVSRDD, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1908             :   }
    1909             :   return 0;
    1910             : }
    1911             : 
    1912             : unsigned fastEmit_ISD_BUILD_VECTOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1913           0 :   switch (VT.SimpleTy) {
    1914           0 :   case MVT::i64: return fastEmit_ISD_BUILD_VECTOR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1915             :   default: return 0;
    1916             :   }
    1917             : }
    1918             : 
    1919             : // FastEmit functions for ISD::FADD.
    1920             : 
    1921           2 : unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1922           2 :   if (RetVT.SimpleTy != MVT::f32)
    1923             :     return 0;
    1924           2 :   if ((PPCSubTarget->hasP8Vector())) {
    1925           0 :     return fastEmitInst_rr(PPC::XSADDSP, &PPC::VSSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1926             :   }
    1927           2 :   if ((PPCSubTarget->hasSPE())) {
    1928           0 :     return fastEmitInst_rr(PPC::EFSADD, &PPC::SPE4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1929             :   }
    1930           2 :   if ((PPCSubTarget->hasFPU())) {
    1931           4 :     return fastEmitInst_rr(PPC::FADDS, &PPC::F4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1932             :   }
    1933             :   return 0;
    1934             : }
    1935             : 
    1936           9 : unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1937           9 :   if (RetVT.SimpleTy != MVT::f64)
    1938             :     return 0;
    1939           9 :   if ((PPCSubTarget->hasVSX())) {
    1940          14 :     return fastEmitInst_rr(PPC::XSADDDP, &PPC::VSFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1941             :   }
    1942           2 :   if ((PPCSubTarget->hasSPE())) {
    1943           0 :     return fastEmitInst_rr(PPC::EFDADD, &PPC::SPERCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1944             :   }
    1945           2 :   if ((PPCSubTarget->hasFPU())) {
    1946           4 :     return fastEmitInst_rr(PPC::FADD, &PPC::F8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1947             :   }
    1948             :   return 0;
    1949             : }
    1950             : 
    1951             : unsigned fastEmit_ISD_FADD_MVT_f128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1952           0 :   if (RetVT.SimpleTy != MVT::f128)
    1953             :     return 0;
    1954           0 :   if ((PPCSubTarget->hasP9Vector())) {
    1955             :     return fastEmitInst_rr(PPC::XSADDQP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1956             :   }
    1957             :   return 0;
    1958             : }
    1959             : 
    1960           0 : unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1961           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1962             :     return 0;
    1963           0 :   if ((PPCSubTarget->hasVSX())) {
    1964           0 :     return fastEmitInst_rr(PPC::XVADDSP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1965             :   }
    1966           0 :   if ((PPCSubTarget->hasQPX())) {
    1967           0 :     return fastEmitInst_rr(PPC::QVFADDSs, &PPC::QSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1968             :   }
    1969           0 :   if ((PPCSubTarget->hasAltivec())) {
    1970           0 :     return fastEmitInst_rr(PPC::VADDFP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1971             :   }
    1972             :   return 0;
    1973             : }
    1974             : 
    1975             : unsigned fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1976           1 :   if (RetVT.SimpleTy != MVT::v2f64)
    1977             :     return 0;
    1978           1 :   if ((PPCSubTarget->hasVSX())) {
    1979             :     return fastEmitInst_rr(PPC::XVADDDP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1980             :   }
    1981             :   return 0;
    1982             : }
    1983             : 
    1984             : unsigned fastEmit_ISD_FADD_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1985           0 :   if (RetVT.SimpleTy != MVT::v4f64)
    1986             :     return 0;
    1987           0 :   if ((PPCSubTarget->hasQPX())) {
    1988             :     return fastEmitInst_rr(PPC::QVFADD, &PPC::QFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1989             :   }
    1990             :   return 0;
    1991             : }
    1992             : 
    1993          12 : unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1994          12 :   switch (VT.SimpleTy) {
    1995           2 :   case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1996           9 :   case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1997           0 :   case MVT::f128: return fastEmit_ISD_FADD_MVT_f128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1998           0 :   case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1999           1 :   case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2000           0 :   case MVT::v4f64: return fastEmit_ISD_FADD_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2001             :   default: return 0;
    2002             :   }
    2003             : }
    2004             : 
    2005             : // FastEmit functions for ISD::FDIV.
    2006             : 
    2007           0 : unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2008           0 :   if (RetVT.SimpleTy != MVT::f32)
    2009             :     return 0;
    2010           0 :   if ((PPCSubTarget->hasP8Vector())) {
    2011           0 :     return fastEmitInst_rr(PPC::XSDIVSP, &PPC::VSSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2012             :   }
    2013           0 :   if ((PPCSubTarget->hasSPE())) {
    2014           0 :     return fastEmitInst_rr(PPC::EFSDIV, &PPC::SPE4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2015             :   }
    2016           0 :   if ((PPCSubTarget->hasFPU())) {
    2017           0 :     return fastEmitInst_rr(PPC::FDIVS, &PPC::F4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2018             :   }
    2019             :   return 0;
    2020             : }
    2021             : 
    2022           1 : unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2023           1 :   if (RetVT.SimpleTy != MVT::f64)
    2024             :     return 0;
    2025           1 :   if ((PPCSubTarget->hasVSX())) {
    2026           2 :     return fastEmitInst_rr(PPC::XSDIVDP, &PPC::VSFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2027             :   }
    2028           0 :   if ((PPCSubTarget->hasSPE())) {
    2029           0 :     return fastEmitInst_rr(PPC::EFDDIV, &PPC::SPERCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2030             :   }
    2031           0 :   if ((PPCSubTarget->hasFPU())) {
    2032           0 :     return fastEmitInst_rr(PPC::FDIV, &PPC::F8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2033             :   }
    2034             :   return 0;
    2035             : }
    2036             : 
    2037             : unsigned fastEmit_ISD_FDIV_MVT_f128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2038           0 :   if (RetVT.SimpleTy != MVT::f128)
    2039             :     return 0;
    2040           0 :   if ((PPCSubTarget->hasP9Vector())) {
    2041             :     return fastEmitInst_rr(PPC::XSDIVQP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2042             :   }
    2043             :   return 0;
    2044             : }
    2045             : 
    2046             : unsigned fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2047           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    2048             :     return 0;
    2049           0 :   if ((PPCSubTarget->hasVSX())) {
    2050             :     return fastEmitInst_rr(PPC::XVDIVSP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2051             :   }
    2052             :   return 0;
    2053             : }
    2054             : 
    2055             : unsigned fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2056           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    2057             :     return 0;
    2058           0 :   if ((PPCSubTarget->hasVSX())) {
    2059             :     return fastEmitInst_rr(PPC::XVDIVDP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2060             :   }
    2061             :   return 0;
    2062             : }
    2063             : 
    2064           1 : unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2065           1 :   switch (VT.SimpleTy) {
    2066           0 :   case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2067           1 :   case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2068           0 :   case MVT::f128: return fastEmit_ISD_FDIV_MVT_f128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2069           0 :   case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2070           0 :   case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2071             :   default: return 0;
    2072             :   }
    2073             : }
    2074             : 
    2075             : // FastEmit functions for ISD::FMUL.
    2076             : 
    2077           0 : unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2078           0 :   if (RetVT.SimpleTy != MVT::f32)
    2079             :     return 0;
    2080           0 :   if ((PPCSubTarget->hasP8Vector())) {
    2081           0 :     return fastEmitInst_rr(PPC::XSMULSP, &PPC::VSSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2082             :   }
    2083           0 :   if ((PPCSubTarget->hasSPE())) {
    2084           0 :     return fastEmitInst_rr(PPC::EFSMUL, &PPC::SPE4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2085             :   }
    2086           0 :   if ((PPCSubTarget->hasFPU())) {
    2087           0 :     return fastEmitInst_rr(PPC::FMULS, &PPC::F4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2088             :   }
    2089             :   return 0;
    2090             : }
    2091             : 
    2092           1 : unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2093           1 :   if (RetVT.SimpleTy != MVT::f64)
    2094             :     return 0;
    2095           1 :   if ((PPCSubTarget->hasVSX())) {
    2096           2 :     return fastEmitInst_rr(PPC::XSMULDP, &PPC::VSFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2097             :   }
    2098           0 :   if ((PPCSubTarget->hasSPE())) {
    2099           0 :     return fastEmitInst_rr(PPC::EFDMUL, &PPC::SPERCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2100             :   }
    2101           0 :   if ((PPCSubTarget->hasFPU())) {
    2102           0 :     return fastEmitInst_rr(PPC::FMUL, &PPC::F8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2103             :   }
    2104             :   return 0;
    2105             : }
    2106             : 
    2107             : unsigned fastEmit_ISD_FMUL_MVT_f128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2108           0 :   if (RetVT.SimpleTy != MVT::f128)
    2109             :     return 0;
    2110           0 :   if ((PPCSubTarget->hasP9Vector())) {
    2111             :     return fastEmitInst_rr(PPC::XSMULQP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2112             :   }
    2113             :   return 0;
    2114             : }
    2115             : 
    2116           0 : unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2117           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    2118             :     return 0;
    2119           0 :   if ((PPCSubTarget->hasVSX())) {
    2120           0 :     return fastEmitInst_rr(PPC::XVMULSP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2121             :   }
    2122           0 :   if ((PPCSubTarget->hasQPX())) {
    2123           0 :     return fastEmitInst_rr(PPC::QVFMULSs, &PPC::QSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2124             :   }
    2125             :   return 0;
    2126             : }
    2127             : 
    2128             : unsigned fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2129           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    2130             :     return 0;
    2131           0 :   if ((PPCSubTarget->hasVSX())) {
    2132             :     return fastEmitInst_rr(PPC::XVMULDP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2133             :   }
    2134             :   return 0;
    2135             : }
    2136             : 
    2137             : unsigned fastEmit_ISD_FMUL_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2138           0 :   if (RetVT.SimpleTy != MVT::v4f64)
    2139             :     return 0;
    2140           0 :   if ((PPCSubTarget->hasQPX())) {
    2141             :     return fastEmitInst_rr(PPC::QVFMUL, &PPC::QFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2142             :   }
    2143             :   return 0;
    2144             : }
    2145             : 
    2146           1 : unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2147           1 :   switch (VT.SimpleTy) {
    2148           0 :   case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2149           1 :   case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2150           0 :   case MVT::f128: return fastEmit_ISD_FMUL_MVT_f128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2151           0 :   case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2152           0 :   case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2153           0 :   case MVT::v4f64: return fastEmit_ISD_FMUL_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2154             :   default: return 0;
    2155             :   }
    2156             : }
    2157             : 
    2158             : // FastEmit functions for ISD::FSUB.
    2159             : 
    2160           0 : unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2161           0 :   if (RetVT.SimpleTy != MVT::f32)
    2162             :     return 0;
    2163           0 :   if ((PPCSubTarget->hasP8Vector())) {
    2164           0 :     return fastEmitInst_rr(PPC::XSSUBSP, &PPC::VSSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2165             :   }
    2166           0 :   if ((PPCSubTarget->hasSPE())) {
    2167           0 :     return fastEmitInst_rr(PPC::EFSSUB, &PPC::SPE4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2168             :   }
    2169           0 :   if ((PPCSubTarget->hasFPU())) {
    2170           0 :     return fastEmitInst_rr(PPC::FSUBS, &PPC::F4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2171             :   }
    2172             :   return 0;
    2173             : }
    2174             : 
    2175           0 : unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2176           0 :   if (RetVT.SimpleTy != MVT::f64)
    2177             :     return 0;
    2178           0 :   if ((PPCSubTarget->hasVSX())) {
    2179           0 :     return fastEmitInst_rr(PPC::XSSUBDP, &PPC::VSFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2180             :   }
    2181           0 :   if ((PPCSubTarget->hasSPE())) {
    2182           0 :     return fastEmitInst_rr(PPC::EFDSUB, &PPC::SPERCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2183             :   }
    2184           0 :   if ((PPCSubTarget->hasFPU())) {
    2185           0 :     return fastEmitInst_rr(PPC::FSUB, &PPC::F8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2186             :   }
    2187             :   return 0;
    2188             : }
    2189             : 
    2190             : unsigned fastEmit_ISD_FSUB_MVT_f128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2191           0 :   if (RetVT.SimpleTy != MVT::f128)
    2192             :     return 0;
    2193           0 :   if ((PPCSubTarget->hasP9Vector())) {
    2194             :     return fastEmitInst_rr(PPC::XSSUBQP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2195             :   }
    2196             :   return 0;
    2197             : }
    2198             : 
    2199           0 : unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2200           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    2201             :     return 0;
    2202           0 :   if ((PPCSubTarget->hasVSX())) {
    2203           0 :     return fastEmitInst_rr(PPC::XVSUBSP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2204             :   }
    2205           0 :   if ((PPCSubTarget->hasQPX())) {
    2206           0 :     return fastEmitInst_rr(PPC::QVFSUBSs, &PPC::QSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2207             :   }
    2208           0 :   if ((PPCSubTarget->hasAltivec())) {
    2209           0 :     return fastEmitInst_rr(PPC::VSUBFP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2210             :   }
    2211             :   return 0;
    2212             : }
    2213             : 
    2214             : unsigned fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2215           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    2216             :     return 0;
    2217           0 :   if ((PPCSubTarget->hasVSX())) {
    2218             :     return fastEmitInst_rr(PPC::XVSUBDP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2219             :   }
    2220             :   return 0;
    2221             : }
    2222             : 
    2223             : unsigned fastEmit_ISD_FSUB_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2224           0 :   if (RetVT.SimpleTy != MVT::v4f64)
    2225             :     return 0;
    2226           0 :   if ((PPCSubTarget->hasQPX())) {
    2227             :     return fastEmitInst_rr(PPC::QVFSUB, &PPC::QFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2228             :   }
    2229             :   return 0;
    2230             : }
    2231             : 
    2232           0 : unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2233           0 :   switch (VT.SimpleTy) {
    2234           0 :   case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2235           0 :   case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2236           0 :   case MVT::f128: return fastEmit_ISD_FSUB_MVT_f128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2237           0 :   case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2238           0 :   case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2239           0 :   case MVT::v4f64: return fastEmit_ISD_FSUB_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2240             :   default: return 0;
    2241             :   }
    2242             : }
    2243             : 
    2244             : // FastEmit functions for ISD::MUL.
    2245             : 
    2246             : unsigned fastEmit_ISD_MUL_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2247           0 :   if (RetVT.SimpleTy != MVT::i1)
    2248             :     return 0;
    2249             :   return fastEmitInst_rr(PPC::CRAND, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2250             : }
    2251             : 
    2252             : unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2253           0 :   if (RetVT.SimpleTy != MVT::i32)
    2254             :     return 0;
    2255             :   return fastEmitInst_rr(PPC::MULLW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2256             : }
    2257             : 
    2258             : unsigned fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2259           0 :   if (RetVT.SimpleTy != MVT::i64)
    2260             :     return 0;
    2261             :   return fastEmitInst_rr(PPC::MULLD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2262             : }
    2263             : 
    2264             : unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2265           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2266             :     return 0;
    2267           0 :   if ((PPCSubTarget->hasP8Altivec())) {
    2268             :     return fastEmitInst_rr(PPC::VMULUWM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2269             :   }
    2270             :   return 0;
    2271             : }
    2272             : 
    2273           0 : unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2274           0 :   switch (VT.SimpleTy) {
    2275           0 :   case MVT::i1: return fastEmit_ISD_MUL_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2276           0 :   case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2277           0 :   case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2278           0 :   case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2279             :   default: return 0;
    2280             :   }
    2281             : }
    2282             : 
    2283             : // FastEmit functions for ISD::MULHS.
    2284             : 
    2285             : unsigned fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2286           0 :   if (RetVT.SimpleTy != MVT::i32)
    2287             :     return 0;
    2288             :   return fastEmitInst_rr(PPC::MULHW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2289             : }
    2290             : 
    2291             : unsigned fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2292           0 :   if (RetVT.SimpleTy != MVT::i64)
    2293             :     return 0;
    2294             :   return fastEmitInst_rr(PPC::MULHD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2295             : }
    2296             : 
    2297           0 : unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2298           0 :   switch (VT.SimpleTy) {
    2299           0 :   case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2300           0 :   case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2301             :   default: return 0;
    2302             :   }
    2303             : }
    2304             : 
    2305             : // FastEmit functions for ISD::MULHU.
    2306             : 
    2307             : unsigned fastEmit_ISD_MULHU_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2308           0 :   if (RetVT.SimpleTy != MVT::i32)
    2309             :     return 0;
    2310             :   return fastEmitInst_rr(PPC::MULHWU, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2311             : }
    2312             : 
    2313             : unsigned fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2314           0 :   if (RetVT.SimpleTy != MVT::i64)
    2315             :     return 0;
    2316             :   return fastEmitInst_rr(PPC::MULHDU, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2317             : }
    2318             : 
    2319           0 : unsigned fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2320           0 :   switch (VT.SimpleTy) {
    2321           0 :   case MVT::i32: return fastEmit_ISD_MULHU_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2322           0 :   case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2323             :   default: return 0;
    2324             :   }
    2325             : }
    2326             : 
    2327             : // FastEmit functions for ISD::OR.
    2328             : 
    2329             : unsigned fastEmit_ISD_OR_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2330           0 :   if (RetVT.SimpleTy != MVT::i1)
    2331             :     return 0;
    2332             :   return fastEmitInst_rr(PPC::CROR, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2333             : }
    2334             : 
    2335             : unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2336           0 :   if (RetVT.SimpleTy != MVT::i32)
    2337             :     return 0;
    2338             :   return fastEmitInst_rr(PPC::OR, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2339             : }
    2340             : 
    2341             : unsigned fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2342           0 :   if (RetVT.SimpleTy != MVT::i64)
    2343             :     return 0;
    2344             :   return fastEmitInst_rr(PPC::OR8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2345             : }
    2346             : 
    2347           1 : unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2348           1 :   if (RetVT.SimpleTy != MVT::v4i32)
    2349             :     return 0;
    2350           1 :   if ((PPCSubTarget->hasVSX())) {
    2351           2 :     return fastEmitInst_rr(PPC::XXLOR, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2352             :   }
    2353           0 :   if ((PPCSubTarget->hasAltivec())) {
    2354           0 :     return fastEmitInst_rr(PPC::VOR, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2355             :   }
    2356             :   return 0;
    2357             : }
    2358             : 
    2359           3 : unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2360           3 :   switch (VT.SimpleTy) {
    2361           0 :   case MVT::i1: return fastEmit_ISD_OR_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2362           0 :   case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2363           0 :   case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2364           1 :   case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2365             :   default: return 0;
    2366             :   }
    2367             : }
    2368             : 
    2369             : // FastEmit functions for ISD::SDIV.
    2370             : 
    2371             : unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2372           0 :   if (RetVT.SimpleTy != MVT::i32)
    2373             :     return 0;
    2374             :   return fastEmitInst_rr(PPC::DIVW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2375             : }
    2376             : 
    2377             : unsigned fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2378           0 :   if (RetVT.SimpleTy != MVT::i64)
    2379             :     return 0;
    2380             :   return fastEmitInst_rr(PPC::DIVD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2381             : }
    2382             : 
    2383           0 : unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2384           0 :   switch (VT.SimpleTy) {
    2385           0 :   case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2386           0 :   case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2387             :   default: return 0;
    2388             :   }
    2389             : }
    2390             : 
    2391             : // FastEmit functions for ISD::SHL.
    2392             : 
    2393             : unsigned fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2394           2 :   if (RetVT.SimpleTy != MVT::i32)
    2395             :     return 0;
    2396             :   return fastEmitInst_rr(PPC::SLW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2397             : }
    2398             : 
    2399             : unsigned fastEmit_ISD_SHL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2400           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2401             :     return 0;
    2402           0 :   if ((PPCSubTarget->hasAltivec())) {
    2403             :     return fastEmitInst_rr(PPC::VSLB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2404             :   }
    2405             :   return 0;
    2406             : }
    2407             : 
    2408             : unsigned fastEmit_ISD_SHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2409           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2410             :     return 0;
    2411           0 :   if ((PPCSubTarget->hasAltivec())) {
    2412             :     return fastEmitInst_rr(PPC::VSLH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2413             :   }
    2414             :   return 0;
    2415             : }
    2416             : 
    2417             : unsigned fastEmit_ISD_SHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2418           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2419             :     return 0;
    2420           0 :   if ((PPCSubTarget->hasAltivec())) {
    2421             :     return fastEmitInst_rr(PPC::VSLW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2422             :   }
    2423             :   return 0;
    2424             : }
    2425             : 
    2426             : unsigned fastEmit_ISD_SHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2427           1 :   if (RetVT.SimpleTy != MVT::v2i64)
    2428             :     return 0;
    2429           1 :   if ((PPCSubTarget->hasP8Altivec())) {
    2430             :     return fastEmitInst_rr(PPC::VSLD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2431             :   }
    2432             :   return 0;
    2433             : }
    2434             : 
    2435           4 : unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2436           4 :   switch (VT.SimpleTy) {
    2437           2 :   case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2438           0 :   case MVT::v16i8: return fastEmit_ISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2439           0 :   case MVT::v8i16: return fastEmit_ISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2440           0 :   case MVT::v4i32: return fastEmit_ISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2441           1 :   case MVT::v2i64: return fastEmit_ISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2442             :   default: return 0;
    2443             :   }
    2444             : }
    2445             : 
    2446             : // FastEmit functions for ISD::SRA.
    2447             : 
    2448             : unsigned fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2449           1 :   if (RetVT.SimpleTy != MVT::i32)
    2450             :     return 0;
    2451             :   return fastEmitInst_rr(PPC::SRAW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2452             : }
    2453             : 
    2454             : unsigned fastEmit_ISD_SRA_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2455           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2456             :     return 0;
    2457           0 :   if ((PPCSubTarget->hasAltivec())) {
    2458             :     return fastEmitInst_rr(PPC::VSRAB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2459             :   }
    2460             :   return 0;
    2461             : }
    2462             : 
    2463             : unsigned fastEmit_ISD_SRA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2464           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2465             :     return 0;
    2466           0 :   if ((PPCSubTarget->hasAltivec())) {
    2467             :     return fastEmitInst_rr(PPC::VSRAH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2468             :   }
    2469             :   return 0;
    2470             : }
    2471             : 
    2472             : unsigned fastEmit_ISD_SRA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2473           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2474             :     return 0;
    2475           0 :   if ((PPCSubTarget->hasAltivec())) {
    2476             :     return fastEmitInst_rr(PPC::VSRAW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2477             :   }
    2478             :   return 0;
    2479             : }
    2480             : 
    2481             : unsigned fastEmit_ISD_SRA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2482           1 :   if (RetVT.SimpleTy != MVT::v2i64)
    2483             :     return 0;
    2484           1 :   if ((PPCSubTarget->hasP8Altivec())) {
    2485             :     return fastEmitInst_rr(PPC::VSRAD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2486             :   }
    2487             :   return 0;
    2488             : }
    2489             : 
    2490           2 : unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2491           2 :   switch (VT.SimpleTy) {
    2492           1 :   case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2493           0 :   case MVT::v16i8: return fastEmit_ISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2494           0 :   case MVT::v8i16: return fastEmit_ISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2495           0 :   case MVT::v4i32: return fastEmit_ISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2496           1 :   case MVT::v2i64: return fastEmit_ISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2497             :   default: return 0;
    2498             :   }
    2499             : }
    2500             : 
    2501             : // FastEmit functions for ISD::SREM.
    2502             : 
    2503             : unsigned fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2504           0 :   if (RetVT.SimpleTy != MVT::i32)
    2505             :     return 0;
    2506           0 :   if ((PPCSubTarget->isISA3_0())) {
    2507             :     return fastEmitInst_rr(PPC::MODSW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2508             :   }
    2509             :   return 0;
    2510             : }
    2511             : 
    2512             : unsigned fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2513           0 :   if (RetVT.SimpleTy != MVT::i64)
    2514             :     return 0;
    2515           0 :   if ((PPCSubTarget->isISA3_0())) {
    2516             :     return fastEmitInst_rr(PPC::MODSD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2517             :   }
    2518             :   return 0;
    2519             : }
    2520             : 
    2521           0 : unsigned fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2522           0 :   switch (VT.SimpleTy) {
    2523           0 :   case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2524           0 :   case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2525             :   default: return 0;
    2526             :   }
    2527             : }
    2528             : 
    2529             : // FastEmit functions for ISD::SRL.
    2530             : 
    2531             : unsigned fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2532           2 :   if (RetVT.SimpleTy != MVT::i32)
    2533             :     return 0;
    2534             :   return fastEmitInst_rr(PPC::SRW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2535             : }
    2536             : 
    2537             : unsigned fastEmit_ISD_SRL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2538           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2539             :     return 0;
    2540           0 :   if ((PPCSubTarget->hasAltivec())) {
    2541             :     return fastEmitInst_rr(PPC::VSRB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2542             :   }
    2543             :   return 0;
    2544             : }
    2545             : 
    2546             : unsigned fastEmit_ISD_SRL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2547           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2548             :     return 0;
    2549           0 :   if ((PPCSubTarget->hasAltivec())) {
    2550             :     return fastEmitInst_rr(PPC::VSRH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2551             :   }
    2552             :   return 0;
    2553             : }
    2554             : 
    2555             : unsigned fastEmit_ISD_SRL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2556           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2557             :     return 0;
    2558           0 :   if ((PPCSubTarget->hasAltivec())) {
    2559             :     return fastEmitInst_rr(PPC::VSRW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2560             :   }
    2561             :   return 0;
    2562             : }
    2563             : 
    2564             : unsigned fastEmit_ISD_SRL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2565           1 :   if (RetVT.SimpleTy != MVT::v2i64)
    2566             :     return 0;
    2567           1 :   if ((PPCSubTarget->hasP8Altivec())) {
    2568             :     return fastEmitInst_rr(PPC::VSRD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2569             :   }
    2570             :   return 0;
    2571             : }
    2572             : 
    2573           3 : unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2574           3 :   switch (VT.SimpleTy) {
    2575           2 :   case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2576           0 :   case MVT::v16i8: return fastEmit_ISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2577           0 :   case MVT::v8i16: return fastEmit_ISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2578           0 :   case MVT::v4i32: return fastEmit_ISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2579           1 :   case MVT::v2i64: return fastEmit_ISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2580             :   default: return 0;
    2581             :   }
    2582             : }
    2583             : 
    2584             : // FastEmit functions for ISD::SUB.
    2585             : 
    2586             : unsigned fastEmit_ISD_SUB_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2587           0 :   if (RetVT.SimpleTy != MVT::i1)
    2588             :     return 0;
    2589             :   return fastEmitInst_rr(PPC::CRXOR, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2590             : }
    2591             : 
    2592             : unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2593           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2594             :     return 0;
    2595           0 :   if ((PPCSubTarget->hasAltivec())) {
    2596             :     return fastEmitInst_rr(PPC::VSUBUBM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2597             :   }
    2598             :   return 0;
    2599             : }
    2600             : 
    2601             : unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2602           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2603             :     return 0;
    2604           0 :   if ((PPCSubTarget->hasAltivec())) {
    2605             :     return fastEmitInst_rr(PPC::VSUBUHM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2606             :   }
    2607             :   return 0;
    2608             : }
    2609             : 
    2610             : unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2611           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2612             :     return 0;
    2613           0 :   if ((PPCSubTarget->hasAltivec())) {
    2614             :     return fastEmitInst_rr(PPC::VSUBUWM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2615             :   }
    2616             :   return 0;
    2617             : }
    2618             : 
    2619             : unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2620           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2621             :     return 0;
    2622           0 :   if ((PPCSubTarget->hasP8Altivec())) {
    2623             :     return fastEmitInst_rr(PPC::VSUBUDM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2624             :   }
    2625             :   return 0;
    2626             : }
    2627             : 
    2628             : unsigned fastEmit_ISD_SUB_MVT_v1i128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2629           0 :   if (RetVT.SimpleTy != MVT::v1i128)
    2630             :     return 0;
    2631           0 :   if ((PPCSubTarget->hasP8Altivec())) {
    2632             :     return fastEmitInst_rr(PPC::VSUBUQM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2633             :   }
    2634             :   return 0;
    2635             : }
    2636             : 
    2637           1 : unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2638           1 :   switch (VT.SimpleTy) {
    2639           0 :   case MVT::i1: return fastEmit_ISD_SUB_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2640           0 :   case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2641           0 :   case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2642           0 :   case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2643           0 :   case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2644           0 :   case MVT::v1i128: return fastEmit_ISD_SUB_MVT_v1i128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2645             :   default: return 0;
    2646             :   }
    2647             : }
    2648             : 
    2649             : // FastEmit functions for ISD::UDIV.
    2650             : 
    2651             : unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2652           0 :   if (RetVT.SimpleTy != MVT::i32)
    2653             :     return 0;
    2654             :   return fastEmitInst_rr(PPC::DIVWU, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2655             : }
    2656             : 
    2657             : unsigned fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2658           0 :   if (RetVT.SimpleTy != MVT::i64)
    2659             :     return 0;
    2660             :   return fastEmitInst_rr(PPC::DIVDU, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2661             : }
    2662             : 
    2663           0 : unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2664           0 :   switch (VT.SimpleTy) {
    2665           0 :   case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2666           0 :   case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2667             :   default: return 0;
    2668             :   }
    2669             : }
    2670             : 
    2671             : // FastEmit functions for ISD::UREM.
    2672             : 
    2673             : unsigned fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2674           0 :   if (RetVT.SimpleTy != MVT::i32)
    2675             :     return 0;
    2676           0 :   if ((PPCSubTarget->isISA3_0())) {
    2677             :     return fastEmitInst_rr(PPC::MODUW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2678             :   }
    2679             :   return 0;
    2680             : }
    2681             : 
    2682             : unsigned fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2683           0 :   if (RetVT.SimpleTy != MVT::i64)
    2684             :     return 0;
    2685           0 :   if ((PPCSubTarget->isISA3_0())) {
    2686             :     return fastEmitInst_rr(PPC::MODUD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2687             :   }
    2688             :   return 0;
    2689             : }
    2690             : 
    2691           0 : unsigned fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2692           0 :   switch (VT.SimpleTy) {
    2693           0 :   case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2694           0 :   case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2695             :   default: return 0;
    2696             :   }
    2697             : }
    2698             : 
    2699             : // FastEmit functions for ISD::XOR.
    2700             : 
    2701             : unsigned fastEmit_ISD_XOR_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2702           0 :   if (RetVT.SimpleTy != MVT::i1)
    2703             :     return 0;
    2704             :   return fastEmitInst_rr(PPC::CRXOR, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2705             : }
    2706             : 
    2707             : unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2708           0 :   if (RetVT.SimpleTy != MVT::i32)
    2709             :     return 0;
    2710             :   return fastEmitInst_rr(PPC::XOR, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2711             : }
    2712             : 
    2713             : unsigned fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2714           0 :   if (RetVT.SimpleTy != MVT::i64)
    2715             :     return 0;
    2716             :   return fastEmitInst_rr(PPC::XOR8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2717             : }
    2718             : 
    2719           1 : unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2720           1 :   if (RetVT.SimpleTy != MVT::v4i32)
    2721             :     return 0;
    2722           1 :   if ((PPCSubTarget->hasVSX())) {
    2723           2 :     return fastEmitInst_rr(PPC::XXLXOR, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2724             :   }
    2725           0 :   if ((PPCSubTarget->hasAltivec())) {
    2726           0 :     return fastEmitInst_rr(PPC::VXOR, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2727             :   }
    2728             :   return 0;
    2729             : }
    2730             : 
    2731           3 : unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2732           3 :   switch (VT.SimpleTy) {
    2733           0 :   case MVT::i1: return fastEmit_ISD_XOR_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2734           0 :   case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2735           0 :   case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2736           1 :   case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2737             :   default: return 0;
    2738             :   }
    2739             : }
    2740             : 
    2741             : // FastEmit functions for PPCISD::CMPB.
    2742             : 
    2743             : unsigned fastEmit_PPCISD_CMPB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2744           0 :   if (RetVT.SimpleTy != MVT::i32)
    2745             :     return 0;
    2746             :   return fastEmitInst_rr(PPC::CMPB, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2747             : }
    2748             : 
    2749             : unsigned fastEmit_PPCISD_CMPB_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2750           0 :   if (RetVT.SimpleTy != MVT::i64)
    2751             :     return 0;
    2752             :   return fastEmitInst_rr(PPC::CMPB8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2753             : }
    2754             : 
    2755           0 : unsigned fastEmit_PPCISD_CMPB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2756           0 :   switch (VT.SimpleTy) {
    2757           0 :   case MVT::i32: return fastEmit_PPCISD_CMPB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2758           0 :   case MVT::i64: return fastEmit_PPCISD_CMPB_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2759             :   default: return 0;
    2760             :   }
    2761             : }
    2762             : 
    2763             : // FastEmit functions for PPCISD::FADDRTZ.
    2764             : 
    2765             : unsigned fastEmit_PPCISD_FADDRTZ_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2766           0 :   if (RetVT.SimpleTy != MVT::f64)
    2767             :     return 0;
    2768           0 :   if ((PPCSubTarget->hasFPU())) {
    2769             :     return fastEmitInst_rr(PPC::FADDrtz, &PPC::F8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2770             :   }
    2771             :   return 0;
    2772             : }
    2773             : 
    2774           0 : unsigned fastEmit_PPCISD_FADDRTZ_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2775           0 :   switch (VT.SimpleTy) {
    2776           0 :   case MVT::f64: return fastEmit_PPCISD_FADDRTZ_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2777             :   default: return 0;
    2778             :   }
    2779             : }
    2780             : 
    2781             : // FastEmit functions for PPCISD::SHL.
    2782             : 
    2783             : unsigned fastEmit_PPCISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2784           0 :   if (RetVT.SimpleTy != MVT::i32)
    2785             :     return 0;
    2786             :   return fastEmitInst_rr(PPC::SLW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2787             : }
    2788             : 
    2789             : unsigned fastEmit_PPCISD_SHL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2790           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2791             :     return 0;
    2792           0 :   if ((PPCSubTarget->hasAltivec())) {
    2793             :     return fastEmitInst_rr(PPC::VSLB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2794             :   }
    2795             :   return 0;
    2796             : }
    2797             : 
    2798             : unsigned fastEmit_PPCISD_SHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2799           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2800             :     return 0;
    2801           0 :   if ((PPCSubTarget->hasAltivec())) {
    2802             :     return fastEmitInst_rr(PPC::VSLH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2803             :   }
    2804             :   return 0;
    2805             : }
    2806             : 
    2807             : unsigned fastEmit_PPCISD_SHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2808           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2809             :     return 0;
    2810           0 :   if ((PPCSubTarget->hasAltivec())) {
    2811             :     return fastEmitInst_rr(PPC::VSLW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2812             :   }
    2813             :   return 0;
    2814             : }
    2815             : 
    2816             : unsigned fastEmit_PPCISD_SHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2817           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2818             :     return 0;
    2819           0 :   if ((PPCSubTarget->hasP8Altivec())) {
    2820             :     return fastEmitInst_rr(PPC::VSLD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2821             :   }
    2822             :   return 0;
    2823             : }
    2824             : 
    2825           0 : unsigned fastEmit_PPCISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2826           0 :   switch (VT.SimpleTy) {
    2827           0 :   case MVT::i32: return fastEmit_PPCISD_SHL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2828           0 :   case MVT::v16i8: return fastEmit_PPCISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2829           0 :   case MVT::v8i16: return fastEmit_PPCISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2830           0 :   case MVT::v4i32: return fastEmit_PPCISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2831           0 :   case MVT::v2i64: return fastEmit_PPCISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2832             :   default: return 0;
    2833             :   }
    2834             : }
    2835             : 
    2836             : // FastEmit functions for PPCISD::SRA.
    2837             : 
    2838             : unsigned fastEmit_PPCISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2839           0 :   if (RetVT.SimpleTy != MVT::i32)
    2840             :     return 0;
    2841             :   return fastEmitInst_rr(PPC::SRAW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2842             : }
    2843             : 
    2844             : unsigned fastEmit_PPCISD_SRA_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2845           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2846             :     return 0;
    2847           0 :   if ((PPCSubTarget->hasAltivec())) {
    2848             :     return fastEmitInst_rr(PPC::VSRAB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2849             :   }
    2850             :   return 0;
    2851             : }
    2852             : 
    2853             : unsigned fastEmit_PPCISD_SRA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2854           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2855             :     return 0;
    2856           0 :   if ((PPCSubTarget->hasAltivec())) {
    2857             :     return fastEmitInst_rr(PPC::VSRAH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2858             :   }
    2859             :   return 0;
    2860             : }
    2861             : 
    2862             : unsigned fastEmit_PPCISD_SRA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2863           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2864             :     return 0;
    2865           0 :   if ((PPCSubTarget->hasAltivec())) {
    2866             :     return fastEmitInst_rr(PPC::VSRAW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2867             :   }
    2868             :   return 0;
    2869             : }
    2870             : 
    2871             : unsigned fastEmit_PPCISD_SRA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2872           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2873             :     return 0;
    2874           0 :   if ((PPCSubTarget->hasP8Altivec())) {
    2875             :     return fastEmitInst_rr(PPC::VSRAD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2876             :   }
    2877             :   return 0;
    2878             : }
    2879             : 
    2880           0 : unsigned fastEmit_PPCISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2881           0 :   switch (VT.SimpleTy) {
    2882           0 :   case MVT::i32: return fastEmit_PPCISD_SRA_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2883           0 :   case MVT::v16i8: return fastEmit_PPCISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2884           0 :   case MVT::v8i16: return fastEmit_PPCISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2885           0 :   case MVT::v4i32: return fastEmit_PPCISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2886           0 :   case MVT::v2i64: return fastEmit_PPCISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2887             :   default: return 0;
    2888             :   }
    2889             : }
    2890             : 
    2891             : // FastEmit functions for PPCISD::SRL.
    2892             : 
    2893             : unsigned fastEmit_PPCISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2894           0 :   if (RetVT.SimpleTy != MVT::i32)
    2895             :     return 0;
    2896             :   return fastEmitInst_rr(PPC::SRW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2897             : }
    2898             : 
    2899             : unsigned fastEmit_PPCISD_SRL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2900           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2901             :     return 0;
    2902           0 :   if ((PPCSubTarget->hasAltivec())) {
    2903             :     return fastEmitInst_rr(PPC::VSRB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2904             :   }
    2905             :   return 0;
    2906             : }
    2907             : 
    2908             : unsigned fastEmit_PPCISD_SRL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2909           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2910             :     return 0;
    2911           0 :   if ((PPCSubTarget->hasAltivec())) {
    2912             :     return fastEmitInst_rr(PPC::VSRH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2913             :   }
    2914             :   return 0;
    2915             : }
    2916             : 
    2917             : unsigned fastEmit_PPCISD_SRL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2918           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2919             :     return 0;
    2920           0 :   if ((PPCSubTarget->hasAltivec())) {
    2921             :     return fastEmitInst_rr(PPC::VSRW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2922             :   }
    2923             :   return 0;
    2924             : }
    2925             : 
    2926             : unsigned fastEmit_PPCISD_SRL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2927           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2928             :     return 0;
    2929           0 :   if ((PPCSubTarget->hasP8Altivec())) {
    2930             :     return fastEmitInst_rr(PPC::VSRD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2931             :   }
    2932             :   return 0;
    2933             : }
    2934             : 
    2935           0 : unsigned fastEmit_PPCISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2936           0 :   switch (VT.SimpleTy) {
    2937           0 :   case MVT::i32: return fastEmit_PPCISD_SRL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2938           0 :   case MVT::v16i8: return fastEmit_PPCISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2939           0 :   case MVT::v8i16: return fastEmit_PPCISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2940           0 :   case MVT::v4i32: return fastEmit_PPCISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2941           0 :   case MVT::v2i64: return fastEmit_PPCISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2942             :   default: return 0;
    2943             :   }
    2944             : }
    2945             : 
    2946             : // Top-level FastEmit function.
    2947             : 
    2948          39 : unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) override {
    2949          39 :   switch (Opcode) {
    2950           1 :   case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2951           0 :   case ISD::ADDC: return fastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2952           0 :   case ISD::ADDE: return fastEmit_ISD_ADDE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2953           8 :   case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2954           0 :   case ISD::BUILD_VECTOR: return fastEmit_ISD_BUILD_VECTOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2955          12 :   case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2956           1 :   case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2957           1 :   case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2958           0 :   case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2959           0 :   case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2960           0 :   case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2961           0 :   case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2962           3 :   case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2963           0 :   case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2964           4 :   case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2965           2 :   case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2966           0 :   case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2967           3 :   case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2968           1 :   case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2969           0 :   case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2970           0 :   case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2971           3 :   case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2972           0 :   case PPCISD::CMPB: return fastEmit_PPCISD_CMPB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2973           0 :   case PPCISD::FADDRTZ: return fastEmit_PPCISD_FADDRTZ_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2974           0 :   case PPCISD::SHL: return fastEmit_PPCISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2975           0 :   case PPCISD::SRA: return fastEmit_PPCISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2976           0 :   case PPCISD::SRL: return fastEmit_PPCISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2977             :   default: return 0;
    2978             :   }
    2979             : }
    2980             : 
    2981             : // FastEmit functions for ISD::SRA.
    2982             : 
    2983             : unsigned fastEmit_ISD_SRA_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2984           1 :   if (RetVT.SimpleTy != MVT::i32)
    2985             :     return 0;
    2986             :   return fastEmitInst_ri(PPC::SRAWI, &PPC::GPRCRegClass, Op0, Op0IsKill, imm1);
    2987             : }
    2988             : 
    2989             : unsigned fastEmit_ISD_SRA_MVT_i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2990           0 :   if (RetVT.SimpleTy != MVT::i64)
    2991             :     return 0;
    2992             :   return fastEmitInst_ri(PPC::SRADI, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
    2993             : }
    2994             : 
    2995           1 : unsigned fastEmit_ISD_SRA_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2996           1 :   switch (VT.SimpleTy) {
    2997           1 :   case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1);
    2998           0 :   case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri(RetVT, Op0, Op0IsKill, imm1);
    2999             :   default: return 0;
    3000             :   }
    3001             : }
    3002             : 
    3003             : // FastEmit functions for PPCISD::EXTSWSLI.
    3004             : 
    3005             : unsigned fastEmit_PPCISD_EXTSWSLI_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3006           0 :   if (RetVT.SimpleTy != MVT::i64)
    3007             :     return 0;
    3008           0 :   if ((PPCSubTarget->isISA3_0())) {
    3009             :     return fastEmitInst_ri(PPC::EXTSWSLI, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
    3010             :   }
    3011             :   return 0;
    3012             : }
    3013             : 
    3014           0 : unsigned fastEmit_PPCISD_EXTSWSLI_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3015           0 :   switch (VT.SimpleTy) {
    3016           0 :   case MVT::i32: return fastEmit_PPCISD_EXTSWSLI_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1);
    3017             :   default: return 0;
    3018             :   }
    3019             : }
    3020             : 
    3021             : // FastEmit functions for PPCISD::QVESPLATI.
    3022             : 
    3023             : unsigned fastEmit_PPCISD_QVESPLATI_MVT_v4i1_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3024           0 :   if (RetVT.SimpleTy != MVT::v4i1)
    3025             :     return 0;
    3026           0 :   if ((PPCSubTarget->hasQPX())) {
    3027             :     return fastEmitInst_ri(PPC::QVESPLATIb, &PPC::QBRCRegClass, Op0, Op0IsKill, imm1);
    3028             :   }
    3029             :   return 0;
    3030             : }
    3031             : 
    3032             : unsigned fastEmit_PPCISD_QVESPLATI_MVT_v4f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3033           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    3034             :     return 0;
    3035           0 :   if ((PPCSubTarget->hasQPX())) {
    3036             :     return fastEmitInst_ri(PPC::QVESPLATIs, &PPC::QSRCRegClass, Op0, Op0IsKill, imm1);
    3037             :   }
    3038             :   return 0;
    3039             : }
    3040             : 
    3041             : unsigned fastEmit_PPCISD_QVESPLATI_MVT_v4f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3042           0 :   if (RetVT.SimpleTy != MVT::v4f64)
    3043             :     return 0;
    3044           0 :   if ((PPCSubTarget->hasQPX())) {
    3045             :     return fastEmitInst_ri(PPC::QVESPLATI, &PPC::QFRCRegClass, Op0, Op0IsKill, imm1);
    3046             :   }
    3047             :   return 0;
    3048             : }
    3049             : 
    3050           0 : unsigned fastEmit_PPCISD_QVESPLATI_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3051           0 :   switch (VT.SimpleTy) {
    3052           0 :   case MVT::v4i1: return fastEmit_PPCISD_QVESPLATI_MVT_v4i1_ri(RetVT, Op0, Op0IsKill, imm1);
    3053           0 :   case MVT::v4f32: return fastEmit_PPCISD_QVESPLATI_MVT_v4f32_ri(RetVT, Op0, Op0IsKill, imm1);
    3054           0 :   case MVT::v4f64: return fastEmit_PPCISD_QVESPLATI_MVT_v4f64_ri(RetVT, Op0, Op0IsKill, imm1);
    3055             :   default: return 0;
    3056             :   }
    3057             : }
    3058             : 
    3059             : // FastEmit functions for PPCISD::TC_RETURN.
    3060             : 
    3061             : unsigned fastEmit_PPCISD_TC_RETURN_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3062           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    3063             :     return 0;
    3064             :   return fastEmitInst_ri(PPC::TCRETURNri, &PPC::CTRRCRegClass, Op0, Op0IsKill, imm1);
    3065             : }
    3066             : 
    3067             : unsigned fastEmit_PPCISD_TC_RETURN_MVT_i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3068           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    3069             :     return 0;
    3070             :   return fastEmitInst_ri(PPC::TCRETURNri8, &PPC::CTRRC8RegClass, Op0, Op0IsKill, imm1);
    3071             : }
    3072             : 
    3073           0 : unsigned fastEmit_PPCISD_TC_RETURN_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3074           0 :   switch (VT.SimpleTy) {
    3075           0 :   case MVT::i32: return fastEmit_PPCISD_TC_RETURN_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1);
    3076           0 :   case MVT::i64: return fastEmit_PPCISD_TC_RETURN_MVT_i64_ri(RetVT, Op0, Op0IsKill, imm1);
    3077             :   default: return 0;
    3078             :   }
    3079             : }
    3080             : 
    3081             : // Top-level FastEmit function.
    3082             : 
    3083          42 : unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) override {
    3084          42 :   if (VT == MVT::i32 && Predicate_imm32SExt16(imm1))
    3085          23 :     if (unsigned Reg = fastEmit_ri_Predicate_imm32SExt16(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3086             :       return Reg;
    3087             : 
    3088          22 :   if (VT == MVT::i64 && Predicate_imm64SExt16(imm1))
    3089          19 :     if (unsigned Reg = fastEmit_ri_Predicate_imm64SExt16(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    3090             :       return Reg;
    3091             : 
    3092           5 :   switch (Opcode) {
    3093           1 :   case ISD::SRA: return fastEmit_ISD_SRA_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    3094           0 :   case PPCISD::EXTSWSLI: return fastEmit_PPCISD_EXTSWSLI_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    3095           0 :   case PPCISD::QVESPLATI: return fastEmit_PPCISD_QVESPLATI_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    3096           0 :   case PPCISD::TC_RETURN: return fastEmit_PPCISD_TC_RETURN_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    3097             :   default: return 0;
    3098             :   }
    3099             : }
    3100             : 
    3101             : // FastEmit functions for ISD::ADD.
    3102             : 
    3103             : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3104          20 :   if (RetVT.SimpleTy != MVT::i32)
    3105             :     return 0;
    3106          20 :   return fastEmitInst_ri(PPC::ADDI, &PPC::GPRCRegClass, Op0, Op0IsKill, imm1);
    3107             : }
    3108             : 
    3109             : unsigned fastEmit_ISD_ADD_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3110          20 :   switch (VT.SimpleTy) {
    3111          20 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, Op0IsKill, imm1);
    3112             :   default: return 0;
    3113             :   }
    3114             : }
    3115             : 
    3116             : // FastEmit functions for ISD::ADDC.
    3117             : 
    3118             : unsigned fastEmit_ISD_ADDC_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3119           0 :   if (RetVT.SimpleTy != MVT::i32)
    3120             :     return 0;
    3121             :   return fastEmitInst_ri(PPC::ADDIC, &PPC::GPRCRegClass, Op0, Op0IsKill, imm1);
    3122             : }
    3123             : 
    3124             : unsigned fastEmit_ISD_ADDC_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3125           0 :   switch (VT.SimpleTy) {
    3126           0 :   case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, Op0IsKill, imm1);
    3127             :   default: return 0;
    3128             :   }
    3129             : }
    3130             : 
    3131             : // FastEmit functions for ISD::MUL.
    3132             : 
    3133             : unsigned fastEmit_ISD_MUL_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3134           0 :   if (RetVT.SimpleTy != MVT::i32)
    3135             :     return 0;
    3136             :   return fastEmitInst_ri(PPC::MULLI, &PPC::GPRCRegClass, Op0, Op0IsKill, imm1);
    3137             : }
    3138             : 
    3139             : unsigned fastEmit_ISD_MUL_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3140           0 :   switch (VT.SimpleTy) {
    3141           0 :   case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, Op0IsKill, imm1);
    3142             :   default: return 0;
    3143             :   }
    3144             : }
    3145             : 
    3146             : // FastEmit functions for PPCISD::XXSPLT.
    3147             : 
    3148             : unsigned fastEmit_PPCISD_XXSPLT_MVT_v4i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3149           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    3150             :     return 0;
    3151           0 :   if ((PPCSubTarget->hasVSX())) {
    3152             :     return fastEmitInst_ri(PPC::XXSPLTW, &PPC::VSRCRegClass, Op0, Op0IsKill, imm1);
    3153             :   }
    3154             :   return 0;
    3155             : }
    3156             : 
    3157           0 : unsigned fastEmit_PPCISD_XXSPLT_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3158           0 :   switch (VT.SimpleTy) {
    3159           0 :   case MVT::v4i32: return fastEmit_PPCISD_XXSPLT_MVT_v4i32_ri_Predicate_imm32SExt16(RetVT, Op0, Op0IsKill, imm1);
    3160             :   default: return 0;
    3161             :   }
    3162             : }
    3163             : 
    3164             : // Top-level FastEmit function.
    3165             : 
    3166          23 : unsigned fastEmit_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3167          23 :   switch (Opcode) {
    3168          20 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm32SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
    3169           0 :   case ISD::ADDC: return fastEmit_ISD_ADDC_ri_Predicate_imm32SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
    3170           0 :   case ISD::MUL: return fastEmit_ISD_MUL_ri_Predicate_imm32SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
    3171           0 :   case PPCISD::XXSPLT: return fastEmit_PPCISD_XXSPLT_ri_Predicate_imm32SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
    3172             :   default: return 0;
    3173             :   }
    3174             : }
    3175             : 
    3176             : // FastEmit functions for ISD::ADD.
    3177             : 
    3178             : unsigned fastEmit_ISD_ADD_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3179          17 :   if (RetVT.SimpleTy != MVT::i64)
    3180             :     return 0;
    3181          17 :   return fastEmitInst_ri(PPC::ADDI8, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
    3182             : }
    3183             : 
    3184             : unsigned fastEmit_ISD_ADD_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3185          17 :   switch (VT.SimpleTy) {
    3186          17 :   case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, Op0IsKill, imm1);
    3187             :   default: return 0;
    3188             :   }
    3189             : }
    3190             : 
    3191             : // FastEmit functions for ISD::ADDC.
    3192             : 
    3193             : unsigned fastEmit_ISD_ADDC_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3194           0 :   if (RetVT.SimpleTy != MVT::i64)
    3195             :     return 0;
    3196             :   return fastEmitInst_ri(PPC::ADDIC8, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
    3197             : }
    3198             : 
    3199             : unsigned fastEmit_ISD_ADDC_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3200           0 :   switch (VT.SimpleTy) {
    3201           0 :   case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, Op0IsKill, imm1);
    3202             :   default: return 0;
    3203             :   }
    3204             : }
    3205             : 
    3206             : // FastEmit functions for ISD::MUL.
    3207             : 
    3208             : unsigned fastEmit_ISD_MUL_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3209           0 :   if (RetVT.SimpleTy != MVT::i64)
    3210             :     return 0;
    3211             :   return fastEmitInst_ri(PPC::MULLI8, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
    3212             : }
    3213             : 
    3214             : unsigned fastEmit_ISD_MUL_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3215           0 :   switch (VT.SimpleTy) {
    3216           0 :   case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, Op0IsKill, imm1);
    3217             :   default: return 0;
    3218             :   }
    3219             : }
    3220             : 
    3221             : // Top-level FastEmit function.
    3222             : 
    3223          19 : unsigned fastEmit_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    3224          19 :   switch (Opcode) {
    3225          17 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm64SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
    3226           0 :   case ISD::ADDC: return fastEmit_ISD_ADDC_ri_Predicate_imm64SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
    3227           0 :   case ISD::MUL: return fastEmit_ISD_MUL_ri_Predicate_imm64SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
    3228             :   default: return 0;
    3229             :   }
    3230             : }
    3231             : 

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