LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/PowerPC - PPCGenFastISel.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 142 1052 13.5 %
Date: 2018-07-13 00:08:38 Functions: 27 120 22.5 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* "Fast" Instruction Selector for the PPC target                             *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : 
      10             : // FastEmit Immediate Predicate functions.
      11             : static bool Predicate_imm32SExt16(int64_t Imm) {
      12             : 
      13             :   // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
      14             :   // sign extended field.  Used by instructions like 'addi'.
      15          23 :   return (int32_t)Imm == (short)Imm;
      16             : 
      17             : }
      18             : static bool Predicate_imm64SExt16(int64_t Imm) {
      19             : 
      20             :   // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
      21             :   // sign extended field.  Used by instructions like 'addi'.
      22          19 :   return (int64_t)Imm == (short)Imm;
      23             : 
      24             : }
      25             : static bool Predicate_immSExt5NonZero(int64_t Imm) {
      26             :  return Imm && isInt<5>(Imm); 
      27             : }
      28             : 
      29             : 
      30             : // FastEmit functions for ISD::READCYCLECOUNTER.
      31             : 
      32             : unsigned fastEmit_ISD_READCYCLECOUNTER_MVT_i64_(MVT RetVT) {
      33           0 :   if (RetVT.SimpleTy != MVT::i64)
      34             :     return 0;
      35           0 :   return fastEmitInst_(PPC::MFTB8, &PPC::G8RCRegClass);
      36             : }
      37             : 
      38             : unsigned fastEmit_ISD_READCYCLECOUNTER_(MVT VT, MVT RetVT) {
      39           0 :   switch (VT.SimpleTy) {
      40           0 :   case MVT::i64: return fastEmit_ISD_READCYCLECOUNTER_MVT_i64_(RetVT);
      41             :   default: return 0;
      42             :   }
      43             : }
      44             : 
      45             : // FastEmit functions for PPCISD::MFFS.
      46             : 
      47             : unsigned fastEmit_PPCISD_MFFS_MVT_f64_(MVT RetVT) {
      48           0 :   if (RetVT.SimpleTy != MVT::f64)
      49             :     return 0;
      50           0 :   return fastEmitInst_(PPC::MFFS, &PPC::F8RCRegClass);
      51             : }
      52             : 
      53             : unsigned fastEmit_PPCISD_MFFS_(MVT VT, MVT RetVT) {
      54           0 :   switch (VT.SimpleTy) {
      55           0 :   case MVT::f64: return fastEmit_PPCISD_MFFS_MVT_f64_(RetVT);
      56             :   default: return 0;
      57             :   }
      58             : }
      59             : 
      60             : // FastEmit functions for PPCISD::PPC32_GOT.
      61             : 
      62             : unsigned fastEmit_PPCISD_PPC32_GOT_MVT_i32_(MVT RetVT) {
      63           0 :   if (RetVT.SimpleTy != MVT::i32)
      64             :     return 0;
      65           0 :   return fastEmitInst_(PPC::PPC32GOT, &PPC::GPRCRegClass);
      66             : }
      67             : 
      68             : unsigned fastEmit_PPCISD_PPC32_GOT_(MVT VT, MVT RetVT) {
      69           0 :   switch (VT.SimpleTy) {
      70           0 :   case MVT::i32: return fastEmit_PPCISD_PPC32_GOT_MVT_i32_(RetVT);
      71             :   default: return 0;
      72             :   }
      73             : }
      74             : 
      75             : // Top-level FastEmit function.
      76             : 
      77           0 : unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode) override {
      78           0 :   switch (Opcode) {
      79           0 :   case ISD::READCYCLECOUNTER: return fastEmit_ISD_READCYCLECOUNTER_(VT, RetVT);
      80           0 :   case PPCISD::MFFS: return fastEmit_PPCISD_MFFS_(VT, RetVT);
      81           0 :   case PPCISD::PPC32_GOT: return fastEmit_PPCISD_PPC32_GOT_(VT, RetVT);
      82             :   default: return 0;
      83             :   }
      84             : }
      85             : 
      86             : // FastEmit functions for ISD::BITCAST.
      87             : 
      88           0 : unsigned fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      89           0 :   if (RetVT.SimpleTy != MVT::f64)
      90             :     return 0;
      91           0 :   if ((PPCSubTarget->hasDirectMove()) && (PPCSubTarget->hasVSX())) {
      92           0 :     return fastEmitInst_r(PPC::MTVSRD, &PPC::VSFRCRegClass, Op0, Op0IsKill);
      93             :   }
      94             :   return 0;
      95             : }
      96             : 
      97           0 : unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      98           0 :   if (RetVT.SimpleTy != MVT::i64)
      99             :     return 0;
     100           0 :   if ((PPCSubTarget->hasDirectMove()) && (PPCSubTarget->hasVSX())) {
     101           0 :     return fastEmitInst_r(PPC::MFVSRD, &PPC::G8RCRegClass, Op0, Op0IsKill);
     102             :   }
     103             :   return 0;
     104             : }
     105             : 
     106           2 : unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     107           2 :   switch (VT.SimpleTy) {
     108           0 :   case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0, Op0IsKill);
     109           0 :   case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0, Op0IsKill);
     110             :   default: return 0;
     111             :   }
     112             : }
     113             : 
     114             : // FastEmit functions for ISD::CTLZ.
     115             : 
     116             : unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     117           0 :   if (RetVT.SimpleTy != MVT::i32)
     118             :     return 0;
     119             :   return fastEmitInst_r(PPC::CNTLZW, &PPC::GPRCRegClass, Op0, Op0IsKill);
     120             : }
     121             : 
     122             : unsigned fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     123           0 :   if (RetVT.SimpleTy != MVT::i64)
     124             :     return 0;
     125             :   return fastEmitInst_r(PPC::CNTLZD, &PPC::G8RCRegClass, Op0, Op0IsKill);
     126             : }
     127             : 
     128             : unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     129           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     130             :     return 0;
     131           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     132             :     return fastEmitInst_r(PPC::VCLZB, &PPC::VRRCRegClass, Op0, Op0IsKill);
     133             :   }
     134             :   return 0;
     135             : }
     136             : 
     137             : unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     138           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     139             :     return 0;
     140           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     141             :     return fastEmitInst_r(PPC::VCLZH, &PPC::VRRCRegClass, Op0, Op0IsKill);
     142             :   }
     143             :   return 0;
     144             : }
     145             : 
     146             : unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     147           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     148             :     return 0;
     149           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     150             :     return fastEmitInst_r(PPC::VCLZW, &PPC::VRRCRegClass, Op0, Op0IsKill);
     151             :   }
     152             :   return 0;
     153             : }
     154             : 
     155             : unsigned fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     156           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     157             :     return 0;
     158           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     159             :     return fastEmitInst_r(PPC::VCLZD, &PPC::VRRCRegClass, Op0, Op0IsKill);
     160             :   }
     161             :   return 0;
     162             : }
     163             : 
     164           0 : unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     165           0 :   switch (VT.SimpleTy) {
     166           0 :   case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
     167           0 :   case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0, Op0IsKill);
     168           0 :   case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     169           0 :   case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     170           0 :   case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     171           0 :   case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     172             :   default: return 0;
     173             :   }
     174             : }
     175             : 
     176             : // FastEmit functions for ISD::CTPOP.
     177             : 
     178             : unsigned fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     179           0 :   if (RetVT.SimpleTy != MVT::i32)
     180             :     return 0;
     181             :   return fastEmitInst_r(PPC::POPCNTW, &PPC::GPRCRegClass, Op0, Op0IsKill);
     182             : }
     183             : 
     184             : unsigned fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     185           0 :   if (RetVT.SimpleTy != MVT::i64)
     186             :     return 0;
     187             :   return fastEmitInst_r(PPC::POPCNTD, &PPC::G8RCRegClass, Op0, Op0IsKill);
     188             : }
     189             : 
     190             : unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     191           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     192             :     return 0;
     193           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     194             :     return fastEmitInst_r(PPC::VPOPCNTB, &PPC::VRRCRegClass, Op0, Op0IsKill);
     195             :   }
     196             :   return 0;
     197             : }
     198             : 
     199             : unsigned fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     200           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     201             :     return 0;
     202           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     203             :     return fastEmitInst_r(PPC::VPOPCNTH, &PPC::VRRCRegClass, Op0, Op0IsKill);
     204             :   }
     205             :   return 0;
     206             : }
     207             : 
     208             : unsigned fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     209           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     210             :     return 0;
     211           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     212             :     return fastEmitInst_r(PPC::VPOPCNTW, &PPC::VRRCRegClass, Op0, Op0IsKill);
     213             :   }
     214             :   return 0;
     215             : }
     216             : 
     217             : unsigned fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     218           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     219             :     return 0;
     220           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     221             :     return fastEmitInst_r(PPC::VPOPCNTD, &PPC::VRRCRegClass, Op0, Op0IsKill);
     222             :   }
     223             :   return 0;
     224             : }
     225             : 
     226           0 : unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     227           0 :   switch (VT.SimpleTy) {
     228           0 :   case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0, Op0IsKill);
     229           0 :   case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0, Op0IsKill);
     230           0 :   case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     231           0 :   case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     232           0 :   case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     233           0 :   case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     234             :   default: return 0;
     235             :   }
     236             : }
     237             : 
     238             : // FastEmit functions for ISD::CTTZ.
     239             : 
     240             : unsigned fastEmit_ISD_CTTZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     241           0 :   if (RetVT.SimpleTy != MVT::i32)
     242             :     return 0;
     243           0 :   if ((PPCSubTarget->isISA3_0())) {
     244             :     return fastEmitInst_r(PPC::CNTTZW, &PPC::GPRCRegClass, Op0, Op0IsKill);
     245             :   }
     246             :   return 0;
     247             : }
     248             : 
     249             : unsigned fastEmit_ISD_CTTZ_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     250           0 :   if (RetVT.SimpleTy != MVT::i64)
     251             :     return 0;
     252           0 :   if ((PPCSubTarget->isISA3_0())) {
     253             :     return fastEmitInst_r(PPC::CNTTZD, &PPC::G8RCRegClass, Op0, Op0IsKill);
     254             :   }
     255             :   return 0;
     256             : }
     257             : 
     258             : unsigned fastEmit_ISD_CTTZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     259           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     260             :     return 0;
     261           0 :   if ((PPCSubTarget->hasP9Altivec())) {
     262             :     return fastEmitInst_r(PPC::VCTZB, &PPC::VRRCRegClass, Op0, Op0IsKill);
     263             :   }
     264             :   return 0;
     265             : }
     266             : 
     267             : unsigned fastEmit_ISD_CTTZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     268           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     269             :     return 0;
     270           0 :   if ((PPCSubTarget->hasP9Altivec())) {
     271             :     return fastEmitInst_r(PPC::VCTZH, &PPC::VRRCRegClass, Op0, Op0IsKill);
     272             :   }
     273             :   return 0;
     274             : }
     275             : 
     276             : unsigned fastEmit_ISD_CTTZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     277           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     278             :     return 0;
     279           0 :   if ((PPCSubTarget->hasP9Altivec())) {
     280             :     return fastEmitInst_r(PPC::VCTZW, &PPC::VRRCRegClass, Op0, Op0IsKill);
     281             :   }
     282             :   return 0;
     283             : }
     284             : 
     285             : unsigned fastEmit_ISD_CTTZ_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     286           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     287             :     return 0;
     288           0 :   if ((PPCSubTarget->hasP9Altivec())) {
     289             :     return fastEmitInst_r(PPC::VCTZD, &PPC::VRRCRegClass, Op0, Op0IsKill);
     290             :   }
     291             :   return 0;
     292             : }
     293             : 
     294           0 : unsigned fastEmit_ISD_CTTZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     295           0 :   switch (VT.SimpleTy) {
     296           0 :   case MVT::i32: return fastEmit_ISD_CTTZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
     297           0 :   case MVT::i64: return fastEmit_ISD_CTTZ_MVT_i64_r(RetVT, Op0, Op0IsKill);
     298           0 :   case MVT::v16i8: return fastEmit_ISD_CTTZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     299           0 :   case MVT::v8i16: return fastEmit_ISD_CTTZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     300           0 :   case MVT::v4i32: return fastEmit_ISD_CTTZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     301           0 :   case MVT::v2i64: return fastEmit_ISD_CTTZ_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     302             :   default: return 0;
     303             :   }
     304             : }
     305             : 
     306             : // FastEmit functions for ISD::FABS.
     307             : 
     308             : unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     309           0 :   if (RetVT.SimpleTy != MVT::f32)
     310             :     return 0;
     311             :   return fastEmitInst_r(PPC::FABSS, &PPC::F4RCRegClass, Op0, Op0IsKill);
     312             : }
     313             : 
     314           0 : unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     315           0 :   if (RetVT.SimpleTy != MVT::f64)
     316             :     return 0;
     317           0 :   if ((PPCSubTarget->hasVSX())) {
     318           0 :     return fastEmitInst_r(PPC::XSABSDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     319             :   }
     320           0 :   return fastEmitInst_r(PPC::FABSD, &PPC::F8RCRegClass, Op0, Op0IsKill);
     321             : }
     322             : 
     323             : unsigned fastEmit_ISD_FABS_MVT_f128_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     324           0 :   if (RetVT.SimpleTy != MVT::f128)
     325             :     return 0;
     326           0 :   if ((PPCSubTarget->hasP9Vector())) {
     327             :     return fastEmitInst_r(PPC::XSABSQP, &PPC::VRRCRegClass, Op0, Op0IsKill);
     328             :   }
     329             :   return 0;
     330             : }
     331             : 
     332           0 : unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     333           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     334             :     return 0;
     335           0 :   if ((PPCSubTarget->hasVSX())) {
     336           0 :     return fastEmitInst_r(PPC::XVABSSP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     337             :   }
     338           0 :   if ((PPCSubTarget->hasQPX())) {
     339           0 :     return fastEmitInst_r(PPC::QVFABSs, &PPC::QSRCRegClass, Op0, Op0IsKill);
     340             :   }
     341             :   return 0;
     342             : }
     343             : 
     344             : unsigned fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     345           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     346             :     return 0;
     347           0 :   if ((PPCSubTarget->hasVSX())) {
     348             :     return fastEmitInst_r(PPC::XVABSDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     349             :   }
     350             :   return 0;
     351             : }
     352             : 
     353             : unsigned fastEmit_ISD_FABS_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     354           0 :   if (RetVT.SimpleTy != MVT::v4f64)
     355             :     return 0;
     356           0 :   if ((PPCSubTarget->hasQPX())) {
     357             :     return fastEmitInst_r(PPC::QVFABS, &PPC::QFRCRegClass, Op0, Op0IsKill);
     358             :   }
     359             :   return 0;
     360             : }
     361             : 
     362           0 : unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     363           0 :   switch (VT.SimpleTy) {
     364           0 :   case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill);
     365           0 :   case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0, Op0IsKill);
     366           0 :   case MVT::f128: return fastEmit_ISD_FABS_MVT_f128_r(RetVT, Op0, Op0IsKill);
     367           0 :   case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     368           0 :   case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     369           0 :   case MVT::v4f64: return fastEmit_ISD_FABS_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
     370             :   default: return 0;
     371             :   }
     372             : }
     373             : 
     374             : // FastEmit functions for ISD::FCEIL.
     375             : 
     376             : unsigned fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     377           0 :   if (RetVT.SimpleTy != MVT::f32)
     378             :     return 0;
     379             :   return fastEmitInst_r(PPC::FRIPS, &PPC::F4RCRegClass, Op0, Op0IsKill);
     380             : }
     381             : 
     382           0 : unsigned fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     383           0 :   if (RetVT.SimpleTy != MVT::f64)
     384             :     return 0;
     385           0 :   if ((PPCSubTarget->hasVSX())) {
     386           0 :     return fastEmitInst_r(PPC::XSRDPIP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     387             :   }
     388           0 :   return fastEmitInst_r(PPC::FRIPD, &PPC::F8RCRegClass, Op0, Op0IsKill);
     389             : }
     390             : 
     391           0 : unsigned fastEmit_ISD_FCEIL_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     392           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     393             :     return 0;
     394           0 :   if ((PPCSubTarget->hasVSX())) {
     395           0 :     return fastEmitInst_r(PPC::XVRSPIP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     396             :   }
     397           0 :   if ((PPCSubTarget->hasAltivec())) {
     398           0 :     return fastEmitInst_r(PPC::VRFIP, &PPC::VRRCRegClass, Op0, Op0IsKill);
     399             :   }
     400           0 :   if ((PPCSubTarget->hasQPX())) {
     401           0 :     return fastEmitInst_r(PPC::QVFRIPs, &PPC::QSRCRegClass, Op0, Op0IsKill);
     402             :   }
     403             :   return 0;
     404             : }
     405             : 
     406             : unsigned fastEmit_ISD_FCEIL_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     407           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     408             :     return 0;
     409           0 :   if ((PPCSubTarget->hasVSX())) {
     410             :     return fastEmitInst_r(PPC::XVRDPIP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     411             :   }
     412             :   return 0;
     413             : }
     414             : 
     415             : unsigned fastEmit_ISD_FCEIL_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     416           0 :   if (RetVT.SimpleTy != MVT::v4f64)
     417             :     return 0;
     418           0 :   if ((PPCSubTarget->hasQPX())) {
     419             :     return fastEmitInst_r(PPC::QVFRIP, &PPC::QFRCRegClass, Op0, Op0IsKill);
     420             :   }
     421             :   return 0;
     422             : }
     423             : 
     424           0 : unsigned fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     425           0 :   switch (VT.SimpleTy) {
     426           0 :   case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0, Op0IsKill);
     427           0 :   case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0, Op0IsKill);
     428           0 :   case MVT::v4f32: return fastEmit_ISD_FCEIL_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     429           0 :   case MVT::v2f64: return fastEmit_ISD_FCEIL_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     430           0 :   case MVT::v4f64: return fastEmit_ISD_FCEIL_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
     431             :   default: return 0;
     432             :   }
     433             : }
     434             : 
     435             : // FastEmit functions for ISD::FFLOOR.
     436             : 
     437             : unsigned fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     438           0 :   if (RetVT.SimpleTy != MVT::f32)
     439             :     return 0;
     440             :   return fastEmitInst_r(PPC::FRIMS, &PPC::F4RCRegClass, Op0, Op0IsKill);
     441             : }
     442             : 
     443           0 : unsigned fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     444           0 :   if (RetVT.SimpleTy != MVT::f64)
     445             :     return 0;
     446           0 :   if ((PPCSubTarget->hasVSX())) {
     447           0 :     return fastEmitInst_r(PPC::XSRDPIM, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     448             :   }
     449           0 :   return fastEmitInst_r(PPC::FRIMD, &PPC::F8RCRegClass, Op0, Op0IsKill);
     450             : }
     451             : 
     452           0 : unsigned fastEmit_ISD_FFLOOR_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     453           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     454             :     return 0;
     455           0 :   if ((PPCSubTarget->hasVSX())) {
     456           0 :     return fastEmitInst_r(PPC::XVRSPIM, &PPC::VSRCRegClass, Op0, Op0IsKill);
     457             :   }
     458           0 :   if ((PPCSubTarget->hasAltivec())) {
     459           0 :     return fastEmitInst_r(PPC::VRFIM, &PPC::VRRCRegClass, Op0, Op0IsKill);
     460             :   }
     461           0 :   if ((PPCSubTarget->hasQPX())) {
     462           0 :     return fastEmitInst_r(PPC::QVFRIMs, &PPC::QSRCRegClass, Op0, Op0IsKill);
     463             :   }
     464             :   return 0;
     465             : }
     466             : 
     467             : unsigned fastEmit_ISD_FFLOOR_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     468           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     469             :     return 0;
     470           0 :   if ((PPCSubTarget->hasVSX())) {
     471             :     return fastEmitInst_r(PPC::XVRDPIM, &PPC::VSRCRegClass, Op0, Op0IsKill);
     472             :   }
     473             :   return 0;
     474             : }
     475             : 
     476             : unsigned fastEmit_ISD_FFLOOR_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     477           0 :   if (RetVT.SimpleTy != MVT::v4f64)
     478             :     return 0;
     479           0 :   if ((PPCSubTarget->hasQPX())) {
     480             :     return fastEmitInst_r(PPC::QVFRIM, &PPC::QFRCRegClass, Op0, Op0IsKill);
     481             :   }
     482             :   return 0;
     483             : }
     484             : 
     485           0 : unsigned fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     486           0 :   switch (VT.SimpleTy) {
     487           0 :   case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0, Op0IsKill);
     488           0 :   case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0, Op0IsKill);
     489           0 :   case MVT::v4f32: return fastEmit_ISD_FFLOOR_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     490           0 :   case MVT::v2f64: return fastEmit_ISD_FFLOOR_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     491           0 :   case MVT::v4f64: return fastEmit_ISD_FFLOOR_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
     492             :   default: return 0;
     493             :   }
     494             : }
     495             : 
     496             : // FastEmit functions for ISD::FNEARBYINT.
     497             : 
     498             : unsigned fastEmit_ISD_FNEARBYINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     499           0 :   if (RetVT.SimpleTy != MVT::f64)
     500             :     return 0;
     501           0 :   if ((PPCSubTarget->hasVSX())) {
     502             :     return fastEmitInst_r(PPC::XSRDPIC, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     503             :   }
     504             :   return 0;
     505             : }
     506             : 
     507           0 : unsigned fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     508           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     509             :     return 0;
     510           0 :   if ((PPCSubTarget->hasVSX())) {
     511           0 :     return fastEmitInst_r(PPC::XVRSPIC, &PPC::VSRCRegClass, Op0, Op0IsKill);
     512             :   }
     513           0 :   if ((PPCSubTarget->hasAltivec())) {
     514           0 :     return fastEmitInst_r(PPC::VRFIN, &PPC::VRRCRegClass, Op0, Op0IsKill);
     515             :   }
     516             :   return 0;
     517             : }
     518             : 
     519             : unsigned fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     520           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     521             :     return 0;
     522           0 :   if ((PPCSubTarget->hasVSX())) {
     523             :     return fastEmitInst_r(PPC::XVRDPIC, &PPC::VSRCRegClass, Op0, Op0IsKill);
     524             :   }
     525             :   return 0;
     526             : }
     527             : 
     528           0 : unsigned fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     529           0 :   switch (VT.SimpleTy) {
     530           0 :   case MVT::f64: return fastEmit_ISD_FNEARBYINT_MVT_f64_r(RetVT, Op0, Op0IsKill);
     531           0 :   case MVT::v4f32: return fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     532           0 :   case MVT::v2f64: return fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     533             :   default: return 0;
     534             :   }
     535             : }
     536             : 
     537             : // FastEmit functions for ISD::FNEG.
     538             : 
     539             : unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     540           0 :   if (RetVT.SimpleTy != MVT::f32)
     541             :     return 0;
     542             :   return fastEmitInst_r(PPC::FNEGS, &PPC::F4RCRegClass, Op0, Op0IsKill);
     543             : }
     544             : 
     545           0 : unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     546           0 :   if (RetVT.SimpleTy != MVT::f64)
     547             :     return 0;
     548           0 :   if ((PPCSubTarget->hasVSX())) {
     549           0 :     return fastEmitInst_r(PPC::XSNEGDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     550             :   }
     551           0 :   return fastEmitInst_r(PPC::FNEGD, &PPC::F8RCRegClass, Op0, Op0IsKill);
     552             : }
     553             : 
     554             : unsigned fastEmit_ISD_FNEG_MVT_f128_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     555           0 :   if (RetVT.SimpleTy != MVT::f128)
     556             :     return 0;
     557           0 :   if ((PPCSubTarget->hasP9Vector())) {
     558             :     return fastEmitInst_r(PPC::XSNEGQP, &PPC::VRRCRegClass, Op0, Op0IsKill);
     559             :   }
     560             :   return 0;
     561             : }
     562             : 
     563           0 : unsigned fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     564           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     565             :     return 0;
     566           0 :   if ((PPCSubTarget->hasVSX())) {
     567           0 :     return fastEmitInst_r(PPC::XVNEGSP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     568             :   }
     569           0 :   if ((PPCSubTarget->hasQPX())) {
     570           0 :     return fastEmitInst_r(PPC::QVFNEGs, &PPC::QSRCRegClass, Op0, Op0IsKill);
     571             :   }
     572             :   return 0;
     573             : }
     574             : 
     575             : unsigned fastEmit_ISD_FNEG_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     576           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     577             :     return 0;
     578           0 :   if ((PPCSubTarget->hasVSX())) {
     579             :     return fastEmitInst_r(PPC::XVNEGDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     580             :   }
     581             :   return 0;
     582             : }
     583             : 
     584             : unsigned fastEmit_ISD_FNEG_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     585           0 :   if (RetVT.SimpleTy != MVT::v4f64)
     586             :     return 0;
     587           0 :   if ((PPCSubTarget->hasQPX())) {
     588             :     return fastEmitInst_r(PPC::QVFNEG, &PPC::QFRCRegClass, Op0, Op0IsKill);
     589             :   }
     590             :   return 0;
     591             : }
     592             : 
     593           0 : unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     594           0 :   switch (VT.SimpleTy) {
     595           0 :   case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill);
     596           0 :   case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0, Op0IsKill);
     597           0 :   case MVT::f128: return fastEmit_ISD_FNEG_MVT_f128_r(RetVT, Op0, Op0IsKill);
     598           0 :   case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     599           0 :   case MVT::v2f64: return fastEmit_ISD_FNEG_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     600           0 :   case MVT::v4f64: return fastEmit_ISD_FNEG_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
     601             :   default: return 0;
     602             :   }
     603             : }
     604             : 
     605             : // FastEmit functions for ISD::FP_EXTEND.
     606             : 
     607             : unsigned fastEmit_ISD_FP_EXTEND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     608           0 :   if (RetVT.SimpleTy != MVT::f128)
     609             :     return 0;
     610           0 :   if ((PPCSubTarget->hasP9Vector())) {
     611             :     return fastEmitInst_r(PPC::XSCVDPQP, &PPC::VRRCRegClass, Op0, Op0IsKill);
     612             :   }
     613             :   return 0;
     614             : }
     615             : 
     616           0 : unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     617           0 :   switch (VT.SimpleTy) {
     618           0 :   case MVT::f64: return fastEmit_ISD_FP_EXTEND_MVT_f64_r(RetVT, Op0, Op0IsKill);
     619             :   default: return 0;
     620             :   }
     621             : }
     622             : 
     623             : // FastEmit functions for ISD::FP_ROUND.
     624             : 
     625             : unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     626           0 :   if (RetVT.SimpleTy != MVT::f32)
     627             :     return 0;
     628             :   return fastEmitInst_r(PPC::FRSP, &PPC::F4RCRegClass, Op0, Op0IsKill);
     629             : }
     630             : 
     631             : unsigned fastEmit_ISD_FP_ROUND_MVT_f128_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     632           0 :   if (RetVT.SimpleTy != MVT::f64)
     633             :     return 0;
     634           0 :   if ((PPCSubTarget->hasP9Vector())) {
     635             :     return fastEmitInst_r(PPC::XSCVQPDP, &PPC::VFRCRegClass, Op0, Op0IsKill);
     636             :   }
     637             :   return 0;
     638             : }
     639             : 
     640           0 : unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     641           0 :   switch (VT.SimpleTy) {
     642           0 :   case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
     643           0 :   case MVT::f128: return fastEmit_ISD_FP_ROUND_MVT_f128_r(RetVT, Op0, Op0IsKill);
     644             :   default: return 0;
     645             :   }
     646             : }
     647             : 
     648             : // FastEmit functions for ISD::FP_TO_SINT.
     649             : 
     650           0 : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     651           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     652             :     return 0;
     653           0 :   if ((PPCSubTarget->hasVSX())) {
     654           0 :     return fastEmitInst_r(PPC::XVCVSPSXWS, &PPC::VSRCRegClass, Op0, Op0IsKill);
     655             :   }
     656           0 :   if ((PPCSubTarget->hasAltivec())) {
     657           0 :     return fastEmitInst_r(PPC::VCTSXS_0, &PPC::VRRCRegClass, Op0, Op0IsKill);
     658             :   }
     659             :   return 0;
     660             : }
     661             : 
     662             : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     663           2 :   if (RetVT.SimpleTy != MVT::v2i64)
     664             :     return 0;
     665           2 :   if ((PPCSubTarget->hasVSX())) {
     666             :     return fastEmitInst_r(PPC::XVCVDPSXDS, &PPC::VSRCRegClass, Op0, Op0IsKill);
     667             :   }
     668             :   return 0;
     669             : }
     670             : 
     671          20 : unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     672          20 :   switch (VT.SimpleTy) {
     673           0 :   case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     674           2 :   case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     675             :   default: return 0;
     676             :   }
     677             : }
     678             : 
     679             : // FastEmit functions for ISD::FP_TO_UINT.
     680             : 
     681           0 : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     682           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     683             :     return 0;
     684           0 :   if ((PPCSubTarget->hasVSX())) {
     685           0 :     return fastEmitInst_r(PPC::XVCVSPUXWS, &PPC::VSRCRegClass, Op0, Op0IsKill);
     686             :   }
     687           0 :   if ((PPCSubTarget->hasAltivec())) {
     688           0 :     return fastEmitInst_r(PPC::VCTUXS_0, &PPC::VRRCRegClass, Op0, Op0IsKill);
     689             :   }
     690             :   return 0;
     691             : }
     692             : 
     693             : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     694           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     695             :     return 0;
     696           0 :   if ((PPCSubTarget->hasVSX())) {
     697             :     return fastEmitInst_r(PPC::XVCVDPUXDS, &PPC::VSRCRegClass, Op0, Op0IsKill);
     698             :   }
     699             :   return 0;
     700             : }
     701             : 
     702           0 : unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     703           0 :   switch (VT.SimpleTy) {
     704           0 :   case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     705           0 :   case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     706             :   default: return 0;
     707             :   }
     708             : }
     709             : 
     710             : // FastEmit functions for ISD::FROUND.
     711             : 
     712             : unsigned fastEmit_ISD_FROUND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     713           0 :   if (RetVT.SimpleTy != MVT::f32)
     714             :     return 0;
     715             :   return fastEmitInst_r(PPC::FRINS, &PPC::F4RCRegClass, Op0, Op0IsKill);
     716             : }
     717             : 
     718           0 : unsigned fastEmit_ISD_FROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     719           0 :   if (RetVT.SimpleTy != MVT::f64)
     720             :     return 0;
     721           0 :   if ((PPCSubTarget->hasVSX())) {
     722           0 :     return fastEmitInst_r(PPC::XSRDPI, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     723             :   }
     724           0 :   return fastEmitInst_r(PPC::FRIND, &PPC::F8RCRegClass, Op0, Op0IsKill);
     725             : }
     726             : 
     727           0 : unsigned fastEmit_ISD_FROUND_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     728           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     729             :     return 0;
     730           0 :   if ((PPCSubTarget->hasVSX())) {
     731           0 :     return fastEmitInst_r(PPC::XVRSPI, &PPC::VSRCRegClass, Op0, Op0IsKill);
     732             :   }
     733           0 :   if ((PPCSubTarget->hasQPX())) {
     734           0 :     return fastEmitInst_r(PPC::QVFRINs, &PPC::QSRCRegClass, Op0, Op0IsKill);
     735             :   }
     736             :   return 0;
     737             : }
     738             : 
     739             : unsigned fastEmit_ISD_FROUND_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     740           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     741             :     return 0;
     742           0 :   if ((PPCSubTarget->hasVSX())) {
     743             :     return fastEmitInst_r(PPC::XVRDPI, &PPC::VSRCRegClass, Op0, Op0IsKill);
     744             :   }
     745             :   return 0;
     746             : }
     747             : 
     748             : unsigned fastEmit_ISD_FROUND_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     749           0 :   if (RetVT.SimpleTy != MVT::v4f64)
     750             :     return 0;
     751           0 :   if ((PPCSubTarget->hasQPX())) {
     752             :     return fastEmitInst_r(PPC::QVFRIN, &PPC::QFRCRegClass, Op0, Op0IsKill);
     753             :   }
     754             :   return 0;
     755             : }
     756             : 
     757           0 : unsigned fastEmit_ISD_FROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     758           0 :   switch (VT.SimpleTy) {
     759           0 :   case MVT::f32: return fastEmit_ISD_FROUND_MVT_f32_r(RetVT, Op0, Op0IsKill);
     760           0 :   case MVT::f64: return fastEmit_ISD_FROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
     761           0 :   case MVT::v4f32: return fastEmit_ISD_FROUND_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     762           0 :   case MVT::v2f64: return fastEmit_ISD_FROUND_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     763           0 :   case MVT::v4f64: return fastEmit_ISD_FROUND_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
     764             :   default: return 0;
     765             :   }
     766             : }
     767             : 
     768             : // FastEmit functions for ISD::FSQRT.
     769             : 
     770           0 : unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     771           0 :   if (RetVT.SimpleTy != MVT::f32)
     772             :     return 0;
     773           0 :   if ((PPCSubTarget->hasP8Vector())) {
     774           0 :     return fastEmitInst_r(PPC::XSSQRTSP, &PPC::VSSRCRegClass, Op0, Op0IsKill);
     775             :   }
     776           0 :   return fastEmitInst_r(PPC::FSQRTS, &PPC::F4RCRegClass, Op0, Op0IsKill);
     777             : }
     778             : 
     779           0 : unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     780           0 :   if (RetVT.SimpleTy != MVT::f64)
     781             :     return 0;
     782           0 :   if ((PPCSubTarget->hasVSX())) {
     783           0 :     return fastEmitInst_r(PPC::XSSQRTDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     784             :   }
     785           0 :   return fastEmitInst_r(PPC::FSQRT, &PPC::F8RCRegClass, Op0, Op0IsKill);
     786             : }
     787             : 
     788             : unsigned fastEmit_ISD_FSQRT_MVT_f128_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     789           0 :   if (RetVT.SimpleTy != MVT::f128)
     790             :     return 0;
     791           0 :   if ((PPCSubTarget->hasP9Vector())) {
     792             :     return fastEmitInst_r(PPC::XSSQRTQP, &PPC::VRRCRegClass, Op0, Op0IsKill);
     793             :   }
     794             :   return 0;
     795             : }
     796             : 
     797             : unsigned fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     798           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     799             :     return 0;
     800           0 :   if ((PPCSubTarget->hasVSX())) {
     801             :     return fastEmitInst_r(PPC::XVSQRTSP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     802             :   }
     803             :   return 0;
     804             : }
     805             : 
     806             : unsigned fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     807           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     808             :     return 0;
     809           0 :   if ((PPCSubTarget->hasVSX())) {
     810             :     return fastEmitInst_r(PPC::XVSQRTDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     811             :   }
     812             :   return 0;
     813             : }
     814             : 
     815           0 : unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     816           0 :   switch (VT.SimpleTy) {
     817           0 :   case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill);
     818           0 :   case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0, Op0IsKill);
     819           0 :   case MVT::f128: return fastEmit_ISD_FSQRT_MVT_f128_r(RetVT, Op0, Op0IsKill);
     820           0 :   case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     821           0 :   case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     822             :   default: return 0;
     823             :   }
     824             : }
     825             : 
     826             : // FastEmit functions for ISD::FTRUNC.
     827             : 
     828             : unsigned fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     829           0 :   if (RetVT.SimpleTy != MVT::f32)
     830             :     return 0;
     831             :   return fastEmitInst_r(PPC::FRIZS, &PPC::F4RCRegClass, Op0, Op0IsKill);
     832             : }
     833             : 
     834           0 : unsigned fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     835           0 :   if (RetVT.SimpleTy != MVT::f64)
     836             :     return 0;
     837           0 :   if ((PPCSubTarget->hasVSX())) {
     838           0 :     return fastEmitInst_r(PPC::XSRDPIZ, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     839             :   }
     840           0 :   return fastEmitInst_r(PPC::FRIZD, &PPC::F8RCRegClass, Op0, Op0IsKill);
     841             : }
     842             : 
     843           0 : unsigned fastEmit_ISD_FTRUNC_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     844           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     845             :     return 0;
     846           0 :   if ((PPCSubTarget->hasVSX())) {
     847           0 :     return fastEmitInst_r(PPC::XVRSPIZ, &PPC::VSRCRegClass, Op0, Op0IsKill);
     848             :   }
     849           0 :   if ((PPCSubTarget->hasAltivec())) {
     850           0 :     return fastEmitInst_r(PPC::VRFIZ, &PPC::VRRCRegClass, Op0, Op0IsKill);
     851             :   }
     852           0 :   if ((PPCSubTarget->hasQPX())) {
     853           0 :     return fastEmitInst_r(PPC::QVFRIZs, &PPC::QSRCRegClass, Op0, Op0IsKill);
     854             :   }
     855             :   return 0;
     856             : }
     857             : 
     858             : unsigned fastEmit_ISD_FTRUNC_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     859           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     860             :     return 0;
     861           0 :   if ((PPCSubTarget->hasVSX())) {
     862             :     return fastEmitInst_r(PPC::XVRDPIZ, &PPC::VSRCRegClass, Op0, Op0IsKill);
     863             :   }
     864             :   return 0;
     865             : }
     866             : 
     867             : unsigned fastEmit_ISD_FTRUNC_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     868           0 :   if (RetVT.SimpleTy != MVT::v4f64)
     869             :     return 0;
     870           0 :   if ((PPCSubTarget->hasQPX())) {
     871             :     return fastEmitInst_r(PPC::QVFRIZ, &PPC::QFRCRegClass, Op0, Op0IsKill);
     872             :   }
     873             :   return 0;
     874             : }
     875             : 
     876           0 : unsigned fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     877           0 :   switch (VT.SimpleTy) {
     878           0 :   case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0, Op0IsKill);
     879           0 :   case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0, Op0IsKill);
     880           0 :   case MVT::v4f32: return fastEmit_ISD_FTRUNC_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     881           0 :   case MVT::v2f64: return fastEmit_ISD_FTRUNC_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     882           0 :   case MVT::v4f64: return fastEmit_ISD_FTRUNC_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
     883             :   default: return 0;
     884             :   }
     885             : }
     886             : 
     887             : // FastEmit functions for ISD::SCALAR_TO_VECTOR.
     888             : 
     889             : unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     890           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     891             :     return 0;
     892           0 :   if ((PPCSubTarget->hasP9Vector())) {
     893             :     return fastEmitInst_r(PPC::MTVSRWS, &PPC::VSRCRegClass, Op0, Op0IsKill);
     894             :   }
     895             :   return 0;
     896             : }
     897             : 
     898           0 : unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     899           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     900             :     return 0;
     901           0 :   if ((PPCSubTarget->hasP8Vector()) && (!PPCSubTarget->isLittleEndian())) {
     902           0 :     return fastEmitInst_r(PPC::XSCVDPSPN, &PPC::VSRCRegClass, Op0, Op0IsKill);
     903             :   }
     904             :   return 0;
     905             : }
     906             : 
     907           0 : unsigned fastEmit_ISD_SCALAR_TO_VECTOR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     908           0 :   switch (VT.SimpleTy) {
     909           0 :   case MVT::i32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(RetVT, Op0, Op0IsKill);
     910           0 :   case MVT::f32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(RetVT, Op0, Op0IsKill);
     911             :   default: return 0;
     912             :   }
     913             : }
     914             : 
     915             : // FastEmit functions for ISD::SIGN_EXTEND.
     916             : 
     917             : unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     918           4 :   if (RetVT.SimpleTy != MVT::i64)
     919             :     return 0;
     920             :   return fastEmitInst_r(PPC::EXTSW_32_64, &PPC::G8RCRegClass, Op0, Op0IsKill);
     921             : }
     922             : 
     923             : unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     924           5 :   switch (VT.SimpleTy) {
     925           4 :   case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0, Op0IsKill);
     926             :   default: return 0;
     927             :   }
     928             : }
     929             : 
     930             : // FastEmit functions for ISD::SINT_TO_FP.
     931             : 
     932           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     933           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     934             :     return 0;
     935           0 :   if ((PPCSubTarget->hasVSX())) {
     936           0 :     return fastEmitInst_r(PPC::XVCVSXWSP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     937             :   }
     938           0 :   if ((PPCSubTarget->hasAltivec())) {
     939           0 :     return fastEmitInst_r(PPC::VCFSX_0, &PPC::VRRCRegClass, Op0, Op0IsKill);
     940             :   }
     941             :   return 0;
     942             : }
     943             : 
     944             : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     945           2 :   if (RetVT.SimpleTy != MVT::v2f64)
     946             :     return 0;
     947           2 :   if ((PPCSubTarget->hasVSX())) {
     948             :     return fastEmitInst_r(PPC::XVCVSXDDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     949             :   }
     950             :   return 0;
     951             : }
     952             : 
     953          16 : unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     954          16 :   switch (VT.SimpleTy) {
     955           0 :   case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     956           2 :   case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     957             :   default: return 0;
     958             :   }
     959             : }
     960             : 
     961             : // FastEmit functions for ISD::TRUNCATE.
     962             : 
     963             : unsigned fastEmit_ISD_TRUNCATE_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     964           0 :   if (RetVT.SimpleTy != MVT::i1)
     965             :     return 0;
     966             :   return fastEmitInst_r(PPC::ANDIo_1_GT_BIT, &PPC::CRBITRCRegClass, Op0, Op0IsKill);
     967             : }
     968             : 
     969             : unsigned fastEmit_ISD_TRUNCATE_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     970           0 :   if (RetVT.SimpleTy != MVT::i1)
     971             :     return 0;
     972             :   return fastEmitInst_r(PPC::ANDIo_1_GT_BIT8, &PPC::CRBITRCRegClass, Op0, Op0IsKill);
     973             : }
     974             : 
     975           0 : unsigned fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     976           0 :   switch (VT.SimpleTy) {
     977           0 :   case MVT::i32: return fastEmit_ISD_TRUNCATE_MVT_i32_r(RetVT, Op0, Op0IsKill);
     978           0 :   case MVT::i64: return fastEmit_ISD_TRUNCATE_MVT_i64_r(RetVT, Op0, Op0IsKill);
     979             :   default: return 0;
     980             :   }
     981             : }
     982             : 
     983             : // FastEmit functions for ISD::UINT_TO_FP.
     984             : 
     985           0 : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     986           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     987             :     return 0;
     988           0 :   if ((PPCSubTarget->hasVSX())) {
     989           0 :     return fastEmitInst_r(PPC::XVCVUXWSP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     990             :   }
     991           0 :   if ((PPCSubTarget->hasAltivec())) {
     992           0 :     return fastEmitInst_r(PPC::VCFUX_0, &PPC::VRRCRegClass, Op0, Op0IsKill);
     993             :   }
     994             :   return 0;
     995             : }
     996             : 
     997             : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     998           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     999             :     return 0;
    1000           0 :   if ((PPCSubTarget->hasVSX())) {
    1001             :     return fastEmitInst_r(PPC::XVCVUXDDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1002             :   }
    1003             :   return 0;
    1004             : }
    1005             : 
    1006           0 : unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1007           0 :   switch (VT.SimpleTy) {
    1008           0 :   case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    1009           0 :   case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
    1010             :   default: return 0;
    1011             :   }
    1012             : }
    1013             : 
    1014             : // FastEmit functions for PPCISD::FCFID.
    1015             : 
    1016           0 : unsigned fastEmit_PPCISD_FCFID_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1017           0 :   if (RetVT.SimpleTy != MVT::f64)
    1018             :     return 0;
    1019           0 :   if ((PPCSubTarget->hasVSX())) {
    1020           0 :     return fastEmitInst_r(PPC::XSCVSXDDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1021             :   }
    1022           0 :   return fastEmitInst_r(PPC::FCFID, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1023             : }
    1024             : 
    1025             : unsigned fastEmit_PPCISD_FCFID_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1026           0 :   switch (VT.SimpleTy) {
    1027           0 :   case MVT::f64: return fastEmit_PPCISD_FCFID_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1028             :   default: return 0;
    1029             :   }
    1030             : }
    1031             : 
    1032             : // FastEmit functions for PPCISD::FCFIDS.
    1033             : 
    1034           0 : unsigned fastEmit_PPCISD_FCFIDS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1035           0 :   if (RetVT.SimpleTy != MVT::f32)
    1036             :     return 0;
    1037           0 :   if ((PPCSubTarget->hasP8Vector())) {
    1038           0 :     return fastEmitInst_r(PPC::XSCVSXDSP, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1039             :   }
    1040           0 :   return fastEmitInst_r(PPC::FCFIDS, &PPC::F4RCRegClass, Op0, Op0IsKill);
    1041             : }
    1042             : 
    1043             : unsigned fastEmit_PPCISD_FCFIDS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1044           0 :   switch (VT.SimpleTy) {
    1045           0 :   case MVT::f64: return fastEmit_PPCISD_FCFIDS_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1046             :   default: return 0;
    1047             :   }
    1048             : }
    1049             : 
    1050             : // FastEmit functions for PPCISD::FCFIDU.
    1051             : 
    1052           0 : unsigned fastEmit_PPCISD_FCFIDU_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1053           0 :   if (RetVT.SimpleTy != MVT::f64)
    1054             :     return 0;
    1055           0 :   if ((PPCSubTarget->hasVSX())) {
    1056           0 :     return fastEmitInst_r(PPC::XSCVUXDDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1057             :   }
    1058           0 :   return fastEmitInst_r(PPC::FCFIDU, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1059             : }
    1060             : 
    1061             : unsigned fastEmit_PPCISD_FCFIDU_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1062           0 :   switch (VT.SimpleTy) {
    1063           0 :   case MVT::f64: return fastEmit_PPCISD_FCFIDU_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1064             :   default: return 0;
    1065             :   }
    1066             : }
    1067             : 
    1068             : // FastEmit functions for PPCISD::FCFIDUS.
    1069             : 
    1070           0 : unsigned fastEmit_PPCISD_FCFIDUS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1071           0 :   if (RetVT.SimpleTy != MVT::f32)
    1072             :     return 0;
    1073           0 :   if ((PPCSubTarget->hasP8Vector())) {
    1074           0 :     return fastEmitInst_r(PPC::XSCVUXDSP, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1075             :   }
    1076           0 :   return fastEmitInst_r(PPC::FCFIDUS, &PPC::F4RCRegClass, Op0, Op0IsKill);
    1077             : }
    1078             : 
    1079             : unsigned fastEmit_PPCISD_FCFIDUS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1080           0 :   switch (VT.SimpleTy) {
    1081           0 :   case MVT::f64: return fastEmit_PPCISD_FCFIDUS_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1082             :   default: return 0;
    1083             :   }
    1084             : }
    1085             : 
    1086             : // FastEmit functions for PPCISD::FCTIDUZ.
    1087             : 
    1088             : unsigned fastEmit_PPCISD_FCTIDUZ_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1089           0 :   if (RetVT.SimpleTy != MVT::f32)
    1090             :     return 0;
    1091           0 :   if ((PPCSubTarget->hasVSX())) {
    1092             :     return fastEmitInst_r(PPC::XSCVDPUXDSs, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1093             :   }
    1094             :   return 0;
    1095             : }
    1096             : 
    1097           0 : unsigned fastEmit_PPCISD_FCTIDUZ_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1098           0 :   if (RetVT.SimpleTy != MVT::f64)
    1099             :     return 0;
    1100           0 :   if ((PPCSubTarget->hasVSX())) {
    1101           0 :     return fastEmitInst_r(PPC::XSCVDPUXDS, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1102             :   }
    1103           0 :   return fastEmitInst_r(PPC::FCTIDUZ, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1104             : }
    1105             : 
    1106           0 : unsigned fastEmit_PPCISD_FCTIDUZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1107           0 :   switch (VT.SimpleTy) {
    1108           0 :   case MVT::f32: return fastEmit_PPCISD_FCTIDUZ_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1109           0 :   case MVT::f64: return fastEmit_PPCISD_FCTIDUZ_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1110             :   default: return 0;
    1111             :   }
    1112             : }
    1113             : 
    1114             : // FastEmit functions for PPCISD::FCTIDZ.
    1115             : 
    1116             : unsigned fastEmit_PPCISD_FCTIDZ_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1117           0 :   if (RetVT.SimpleTy != MVT::f32)
    1118             :     return 0;
    1119           0 :   if ((PPCSubTarget->hasVSX())) {
    1120             :     return fastEmitInst_r(PPC::XSCVDPSXDSs, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1121             :   }
    1122             :   return 0;
    1123             : }
    1124             : 
    1125           0 : unsigned fastEmit_PPCISD_FCTIDZ_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1126           0 :   if (RetVT.SimpleTy != MVT::f64)
    1127             :     return 0;
    1128           0 :   if ((PPCSubTarget->hasVSX())) {
    1129           0 :     return fastEmitInst_r(PPC::XSCVDPSXDS, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1130             :   }
    1131           0 :   return fastEmitInst_r(PPC::FCTIDZ, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1132             : }
    1133             : 
    1134           0 : unsigned fastEmit_PPCISD_FCTIDZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1135           0 :   switch (VT.SimpleTy) {
    1136           0 :   case MVT::f32: return fastEmit_PPCISD_FCTIDZ_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1137           0 :   case MVT::f64: return fastEmit_PPCISD_FCTIDZ_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1138             :   default: return 0;
    1139             :   }
    1140             : }
    1141             : 
    1142             : // FastEmit functions for PPCISD::FCTIWUZ.
    1143             : 
    1144             : unsigned fastEmit_PPCISD_FCTIWUZ_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1145           0 :   if (RetVT.SimpleTy != MVT::f32)
    1146             :     return 0;
    1147           0 :   if ((PPCSubTarget->hasVSX())) {
    1148             :     return fastEmitInst_r(PPC::XSCVDPUXWSs, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1149             :   }
    1150             :   return 0;
    1151             : }
    1152             : 
    1153           0 : unsigned fastEmit_PPCISD_FCTIWUZ_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1154           0 :   if (RetVT.SimpleTy != MVT::f64)
    1155             :     return 0;
    1156           0 :   if ((PPCSubTarget->hasVSX())) {
    1157           0 :     return fastEmitInst_r(PPC::XSCVDPUXWS, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1158             :   }
    1159           0 :   return fastEmitInst_r(PPC::FCTIWUZ, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1160             : }
    1161             : 
    1162           0 : unsigned fastEmit_PPCISD_FCTIWUZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1163           0 :   switch (VT.SimpleTy) {
    1164           0 :   case MVT::f32: return fastEmit_PPCISD_FCTIWUZ_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1165           0 :   case MVT::f64: return fastEmit_PPCISD_FCTIWUZ_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1166             :   default: return 0;
    1167             :   }
    1168             : }
    1169             : 
    1170             : // FastEmit functions for PPCISD::FCTIWZ.
    1171             : 
    1172             : unsigned fastEmit_PPCISD_FCTIWZ_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1173           0 :   if (RetVT.SimpleTy != MVT::f32)
    1174             :     return 0;
    1175           0 :   if ((PPCSubTarget->hasVSX())) {
    1176             :     return fastEmitInst_r(PPC::XSCVDPSXWSs, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1177             :   }
    1178             :   return 0;
    1179             : }
    1180             : 
    1181           0 : unsigned fastEmit_PPCISD_FCTIWZ_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1182           0 :   if (RetVT.SimpleTy != MVT::f64)
    1183             :     return 0;
    1184           0 :   if ((PPCSubTarget->hasVSX())) {
    1185           0 :     return fastEmitInst_r(PPC::XSCVDPSXWS, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1186             :   }
    1187           0 :   return fastEmitInst_r(PPC::FCTIWZ, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1188             : }
    1189             : 
    1190           0 : unsigned fastEmit_PPCISD_FCTIWZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1191           0 :   switch (VT.SimpleTy) {
    1192           0 :   case MVT::f32: return fastEmit_PPCISD_FCTIWZ_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1193           0 :   case MVT::f64: return fastEmit_PPCISD_FCTIWZ_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1194             :   default: return 0;
    1195             :   }
    1196             : }
    1197             : 
    1198             : // FastEmit functions for PPCISD::FRE.
    1199             : 
    1200           0 : unsigned fastEmit_PPCISD_FRE_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1201           0 :   if (RetVT.SimpleTy != MVT::f32)
    1202             :     return 0;
    1203           0 :   if ((PPCSubTarget->hasP8Vector())) {
    1204           0 :     return fastEmitInst_r(PPC::XSRESP, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1205             :   }
    1206           0 :   return fastEmitInst_r(PPC::FRES, &PPC::F4RCRegClass, Op0, Op0IsKill);
    1207             : }
    1208             : 
    1209           0 : unsigned fastEmit_PPCISD_FRE_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1210           0 :   if (RetVT.SimpleTy != MVT::f64)
    1211             :     return 0;
    1212           0 :   if ((PPCSubTarget->hasVSX())) {
    1213           0 :     return fastEmitInst_r(PPC::XSREDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1214             :   }
    1215           0 :   return fastEmitInst_r(PPC::FRE, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1216             : }
    1217             : 
    1218           0 : unsigned fastEmit_PPCISD_FRE_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1219           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1220             :     return 0;
    1221           0 :   if ((PPCSubTarget->hasVSX())) {
    1222           0 :     return fastEmitInst_r(PPC::XVRESP, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1223             :   }
    1224           0 :   if ((PPCSubTarget->hasAltivec())) {
    1225           0 :     return fastEmitInst_r(PPC::VREFP, &PPC::VRRCRegClass, Op0, Op0IsKill);
    1226             :   }
    1227           0 :   if ((PPCSubTarget->hasQPX())) {
    1228           0 :     return fastEmitInst_r(PPC::QVFRESs, &PPC::QSRCRegClass, Op0, Op0IsKill);
    1229             :   }
    1230             :   return 0;
    1231             : }
    1232             : 
    1233             : unsigned fastEmit_PPCISD_FRE_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1234           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1235             :     return 0;
    1236           0 :   if ((PPCSubTarget->hasVSX())) {
    1237             :     return fastEmitInst_r(PPC::XVREDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1238             :   }
    1239             :   return 0;
    1240             : }
    1241             : 
    1242             : unsigned fastEmit_PPCISD_FRE_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1243           0 :   if (RetVT.SimpleTy != MVT::v4f64)
    1244             :     return 0;
    1245           0 :   if ((PPCSubTarget->hasQPX())) {
    1246             :     return fastEmitInst_r(PPC::QVFRE, &PPC::QFRCRegClass, Op0, Op0IsKill);
    1247             :   }
    1248             :   return 0;
    1249             : }
    1250             : 
    1251           0 : unsigned fastEmit_PPCISD_FRE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1252           0 :   switch (VT.SimpleTy) {
    1253           0 :   case MVT::f32: return fastEmit_PPCISD_FRE_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1254           0 :   case MVT::f64: return fastEmit_PPCISD_FRE_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1255           0 :   case MVT::v4f32: return fastEmit_PPCISD_FRE_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
    1256           0 :   case MVT::v2f64: return fastEmit_PPCISD_FRE_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
    1257           0 :   case MVT::v4f64: return fastEmit_PPCISD_FRE_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
    1258             :   default: return 0;
    1259             :   }
    1260             : }
    1261             : 
    1262             : // FastEmit functions for PPCISD::FRSQRTE.
    1263             : 
    1264           0 : unsigned fastEmit_PPCISD_FRSQRTE_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1265           0 :   if (RetVT.SimpleTy != MVT::f32)
    1266             :     return 0;
    1267           0 :   if ((PPCSubTarget->hasP8Vector())) {
    1268           0 :     return fastEmitInst_r(PPC::XSRSQRTESP, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1269             :   }
    1270           0 :   return fastEmitInst_r(PPC::FRSQRTES, &PPC::F4RCRegClass, Op0, Op0IsKill);
    1271             : }
    1272             : 
    1273           0 : unsigned fastEmit_PPCISD_FRSQRTE_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1274           0 :   if (RetVT.SimpleTy != MVT::f64)
    1275             :     return 0;
    1276           0 :   if ((PPCSubTarget->hasVSX())) {
    1277           0 :     return fastEmitInst_r(PPC::XSRSQRTEDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1278             :   }
    1279           0 :   return fastEmitInst_r(PPC::FRSQRTE, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1280             : }
    1281             : 
    1282           0 : unsigned fastEmit_PPCISD_FRSQRTE_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1283           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1284             :     return 0;
    1285           0 :   if ((PPCSubTarget->hasVSX())) {
    1286           0 :     return fastEmitInst_r(PPC::XVRSQRTESP, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1287             :   }
    1288           0 :   if ((PPCSubTarget->hasAltivec())) {
    1289           0 :     return fastEmitInst_r(PPC::VRSQRTEFP, &PPC::VRRCRegClass, Op0, Op0IsKill);
    1290             :   }
    1291           0 :   if ((PPCSubTarget->hasQPX())) {
    1292           0 :     return fastEmitInst_r(PPC::QVFRSQRTESs, &PPC::QSRCRegClass, Op0, Op0IsKill);
    1293             :   }
    1294             :   return 0;
    1295             : }
    1296             : 
    1297             : unsigned fastEmit_PPCISD_FRSQRTE_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1298           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1299             :     return 0;
    1300           0 :   if ((PPCSubTarget->hasVSX())) {
    1301             :     return fastEmitInst_r(PPC::XVRSQRTEDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1302             :   }
    1303             :   return 0;
    1304             : }
    1305             : 
    1306             : unsigned fastEmit_PPCISD_FRSQRTE_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1307           0 :   if (RetVT.SimpleTy != MVT::v4f64)
    1308             :     return 0;
    1309           0 :   if ((PPCSubTarget->hasQPX())) {
    1310             :     return fastEmitInst_r(PPC::QVFRSQRTE, &PPC::QFRCRegClass, Op0, Op0IsKill);
    1311             :   }
    1312             :   return 0;
    1313             : }
    1314             : 
    1315           0 : unsigned fastEmit_PPCISD_FRSQRTE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1316           0 :   switch (VT.SimpleTy) {
    1317           0 :   case MVT::f32: return fastEmit_PPCISD_FRSQRTE_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1318           0 :   case MVT::f64: return fastEmit_PPCISD_FRSQRTE_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1319           0 :   case MVT::v4f32: return fastEmit_PPCISD_FRSQRTE_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
    1320           0 :   case MVT::v2f64: return fastEmit_PPCISD_FRSQRTE_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
    1321           0 :   case MVT::v4f64: return fastEmit_PPCISD_FRSQRTE_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
    1322             :   default: return 0;
    1323             :   }
    1324             : }
    1325             : 
    1326             : // FastEmit functions for PPCISD::MFVSR.
    1327             : 
    1328             : unsigned fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i32_r(unsigned Op0, bool Op0IsKill) {
    1329           0 :   if ((PPCSubTarget->hasDirectMove())) {
    1330             :     return fastEmitInst_r(PPC::MFVSRWZ, &PPC::GPRCRegClass, Op0, Op0IsKill);
    1331             :   }
    1332             :   return 0;
    1333             : }
    1334             : 
    1335             : unsigned fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i64_r(unsigned Op0, bool Op0IsKill) {
    1336           0 :   if ((PPCSubTarget->hasDirectMove())) {
    1337             :     return fastEmitInst_r(PPC::MFVSRD, &PPC::G8RCRegClass, Op0, Op0IsKill);
    1338             :   }
    1339             :   return 0;
    1340             : }
    1341             : 
    1342           0 : unsigned fastEmit_PPCISD_MFVSR_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1343           0 : switch (RetVT.SimpleTy) {
    1344           0 :   case MVT::i32: return fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i32_r(Op0, Op0IsKill);
    1345           0 :   case MVT::i64: return fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i64_r(Op0, Op0IsKill);
    1346             :   default: return 0;
    1347             : }
    1348             : }
    1349             : 
    1350             : unsigned fastEmit_PPCISD_MFVSR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1351           0 :   switch (VT.SimpleTy) {
    1352           0 :   case MVT::f64: return fastEmit_PPCISD_MFVSR_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1353             :   default: return 0;
    1354             :   }
    1355             : }
    1356             : 
    1357             : // FastEmit functions for PPCISD::MTCTR.
    1358             : 
    1359             : unsigned fastEmit_PPCISD_MTCTR_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1360           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    1361             :     return 0;
    1362             :   return fastEmitInst_r(PPC::MTCTR, &PPC::GPRCRegClass, Op0, Op0IsKill);
    1363             : }
    1364             : 
    1365             : unsigned fastEmit_PPCISD_MTCTR_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1366           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    1367             :     return 0;
    1368             :   return fastEmitInst_r(PPC::MTCTR8, &PPC::G8RCRegClass, Op0, Op0IsKill);
    1369             : }
    1370             : 
    1371           0 : unsigned fastEmit_PPCISD_MTCTR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1372           0 :   switch (VT.SimpleTy) {
    1373           0 :   case MVT::i32: return fastEmit_PPCISD_MTCTR_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1374           0 :   case MVT::i64: return fastEmit_PPCISD_MTCTR_MVT_i64_r(RetVT, Op0, Op0IsKill);
    1375             :   default: return 0;
    1376             :   }
    1377             : }
    1378             : 
    1379             : // FastEmit functions for PPCISD::MTVSRA.
    1380             : 
    1381             : unsigned fastEmit_PPCISD_MTVSRA_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1382           0 :   if (RetVT.SimpleTy != MVT::f64)
    1383             :     return 0;
    1384           0 :   if ((PPCSubTarget->hasDirectMove())) {
    1385             :     return fastEmitInst_r(PPC::MTVSRWA, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1386             :   }
    1387             :   return 0;
    1388             : }
    1389             : 
    1390             : unsigned fastEmit_PPCISD_MTVSRA_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1391           0 :   if (RetVT.SimpleTy != MVT::f64)
    1392             :     return 0;
    1393           0 :   if ((PPCSubTarget->hasDirectMove())) {
    1394             :     return fastEmitInst_r(PPC::MTVSRD, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1395             :   }
    1396             :   return 0;
    1397             : }
    1398             : 
    1399           0 : unsigned fastEmit_PPCISD_MTVSRA_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1400           0 :   switch (VT.SimpleTy) {
    1401           0 :   case MVT::i32: return fastEmit_PPCISD_MTVSRA_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1402           0 :   case MVT::i64: return fastEmit_PPCISD_MTVSRA_MVT_i64_r(RetVT, Op0, Op0IsKill);
    1403             :   default: return 0;
    1404             :   }
    1405             : }
    1406             : 
    1407             : // FastEmit functions for PPCISD::MTVSRZ.
    1408             : 
    1409             : unsigned fastEmit_PPCISD_MTVSRZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1410           0 :   if (RetVT.SimpleTy != MVT::f64)
    1411             :     return 0;
    1412           0 :   if ((PPCSubTarget->hasDirectMove())) {
    1413             :     return fastEmitInst_r(PPC::MTVSRWZ, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1414             :   }
    1415             :   return 0;
    1416             : }
    1417             : 
    1418           0 : unsigned fastEmit_PPCISD_MTVSRZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1419           0 :   switch (VT.SimpleTy) {
    1420           0 :   case MVT::i32: return fastEmit_PPCISD_MTVSRZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1421             :   default: return 0;
    1422             :   }
    1423             : }
    1424             : 
    1425             : // FastEmit functions for PPCISD::SExtVElems.
    1426             : 
    1427             : unsigned fastEmit_PPCISD_SExtVElems_MVT_v16i8_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
    1428           0 :   if ((PPCSubTarget->hasP9Altivec())) {
    1429             :     return fastEmitInst_r(PPC::VEXTSB2W, &PPC::VRRCRegClass, Op0, Op0IsKill);
    1430             :   }
    1431             :   return 0;
    1432             : }
    1433             : 
    1434             : unsigned fastEmit_PPCISD_SExtVElems_MVT_v16i8_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
    1435           0 :   if ((PPCSubTarget->hasP9Altivec())) {
    1436             :     return fastEmitInst_r(PPC::VEXTSB2D, &PPC::VRRCRegClass, Op0, Op0IsKill);
    1437             :   }
    1438             :   return 0;
    1439             : }
    1440             : 
    1441           0 : unsigned fastEmit_PPCISD_SExtVElems_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1442           0 : switch (RetVT.SimpleTy) {
    1443           0 :   case MVT::v4i32: return fastEmit_PPCISD_SExtVElems_MVT_v16i8_MVT_v4i32_r(Op0, Op0IsKill);
    1444           0 :   case MVT::v2i64: return fastEmit_PPCISD_SExtVElems_MVT_v16i8_MVT_v2i64_r(Op0, Op0IsKill);
    1445             :   default: return 0;
    1446             : }
    1447             : }
    1448             : 
    1449             : unsigned fastEmit_PPCISD_SExtVElems_MVT_v8i16_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
    1450           0 :   if ((PPCSubTarget->hasP9Altivec())) {
    1451             :     return fastEmitInst_r(PPC::VEXTSH2W, &PPC::VRRCRegClass, Op0, Op0IsKill);
    1452             :   }
    1453             :   return 0;
    1454             : }
    1455             : 
    1456             : unsigned fastEmit_PPCISD_SExtVElems_MVT_v8i16_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
    1457           0 :   if ((PPCSubTarget->hasP9Altivec())) {
    1458             :     return fastEmitInst_r(PPC::VEXTSH2D, &PPC::VRRCRegClass, Op0, Op0IsKill);
    1459             :   }
    1460             :   return 0;
    1461             : }
    1462             : 
    1463           0 : unsigned fastEmit_PPCISD_SExtVElems_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1464           0 : switch (RetVT.SimpleTy) {
    1465           0 :   case MVT::v4i32: return fastEmit_PPCISD_SExtVElems_MVT_v8i16_MVT_v4i32_r(Op0, Op0IsKill);
    1466           0 :   case MVT::v2i64: return fastEmit_PPCISD_SExtVElems_MVT_v8i16_MVT_v2i64_r(Op0, Op0IsKill);
    1467             :   default: return 0;
    1468             : }
    1469             : }
    1470             : 
    1471             : unsigned fastEmit_PPCISD_SExtVElems_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1472           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1473             :     return 0;
    1474           0 :   if ((PPCSubTarget->hasP9Altivec())) {
    1475             :     return fastEmitInst_r(PPC::VEXTSW2D, &PPC::VRRCRegClass, Op0, Op0IsKill);
    1476             :   }
    1477             :   return 0;
    1478             : }
    1479             : 
    1480           0 : unsigned fastEmit_PPCISD_SExtVElems_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1481           0 :   switch (VT.SimpleTy) {
    1482           0 :   case MVT::v16i8: return fastEmit_PPCISD_SExtVElems_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1483           0 :   case MVT::v8i16: return fastEmit_PPCISD_SExtVElems_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    1484           0 :   case MVT::v4i32: return fastEmit_PPCISD_SExtVElems_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    1485             :   default: return 0;
    1486             :   }
    1487             : }
    1488             : 
    1489             : // FastEmit functions for PPCISD::XXREVERSE.
    1490             : 
    1491             : unsigned fastEmit_PPCISD_XXREVERSE_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1492           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1493             :     return 0;
    1494           0 :   if ((PPCSubTarget->hasP9Vector())) {
    1495             :     return fastEmitInst_r(PPC::XXBRW, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1496             :   }
    1497             :   return 0;
    1498             : }
    1499             : 
    1500             : unsigned fastEmit_PPCISD_XXREVERSE_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1501           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1502             :     return 0;
    1503           0 :   if ((PPCSubTarget->hasP9Vector())) {
    1504             :     return fastEmitInst_r(PPC::XXBRD, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1505             :   }
    1506             :   return 0;
    1507             : }
    1508             : 
    1509           0 : unsigned fastEmit_PPCISD_XXREVERSE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1510           0 :   switch (VT.SimpleTy) {
    1511           0 :   case MVT::v4i32: return fastEmit_PPCISD_XXREVERSE_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    1512           0 :   case MVT::v2i64: return fastEmit_PPCISD_XXREVERSE_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
    1513             :   default: return 0;
    1514             :   }
    1515             : }
    1516             : 
    1517             : // Top-level FastEmit function.
    1518             : 
    1519          45 : unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill) override {
    1520          45 :   switch (Opcode) {
    1521           2 :   case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0, Op0IsKill);
    1522           0 :   case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill);
    1523           0 :   case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill);
    1524           0 :   case ISD::CTTZ: return fastEmit_ISD_CTTZ_r(VT, RetVT, Op0, Op0IsKill);
    1525           0 :   case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill);
    1526           0 :   case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0, Op0IsKill);
    1527           0 :   case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0, Op0IsKill);
    1528           0 :   case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0, Op0IsKill);
    1529           0 :   case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill);
    1530           0 :   case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
    1531           0 :   case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill);
    1532          20 :   case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill);
    1533           0 :   case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill);
    1534           0 :   case ISD::FROUND: return fastEmit_ISD_FROUND_r(VT, RetVT, Op0, Op0IsKill);
    1535           0 :   case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill);
    1536           0 :   case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0, Op0IsKill);
    1537           0 :   case ISD::SCALAR_TO_VECTOR: return fastEmit_ISD_SCALAR_TO_VECTOR_r(VT, RetVT, Op0, Op0IsKill);
    1538           5 :   case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
    1539          16 :   case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill);
    1540           0 :   case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0, Op0IsKill);
    1541           0 :   case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill);
    1542           0 :   case PPCISD::FCFID: return fastEmit_PPCISD_FCFID_r(VT, RetVT, Op0, Op0IsKill);
    1543           0 :   case PPCISD::FCFIDS: return fastEmit_PPCISD_FCFIDS_r(VT, RetVT, Op0, Op0IsKill);
    1544           0 :   case PPCISD::FCFIDU: return fastEmit_PPCISD_FCFIDU_r(VT, RetVT, Op0, Op0IsKill);
    1545           0 :   case PPCISD::FCFIDUS: return fastEmit_PPCISD_FCFIDUS_r(VT, RetVT, Op0, Op0IsKill);
    1546           0 :   case PPCISD::FCTIDUZ: return fastEmit_PPCISD_FCTIDUZ_r(VT, RetVT, Op0, Op0IsKill);
    1547           0 :   case PPCISD::FCTIDZ: return fastEmit_PPCISD_FCTIDZ_r(VT, RetVT, Op0, Op0IsKill);
    1548           0 :   case PPCISD::FCTIWUZ: return fastEmit_PPCISD_FCTIWUZ_r(VT, RetVT, Op0, Op0IsKill);
    1549           0 :   case PPCISD::FCTIWZ: return fastEmit_PPCISD_FCTIWZ_r(VT, RetVT, Op0, Op0IsKill);
    1550           0 :   case PPCISD::FRE: return fastEmit_PPCISD_FRE_r(VT, RetVT, Op0, Op0IsKill);
    1551           0 :   case PPCISD::FRSQRTE: return fastEmit_PPCISD_FRSQRTE_r(VT, RetVT, Op0, Op0IsKill);
    1552           0 :   case PPCISD::MFVSR: return fastEmit_PPCISD_MFVSR_r(VT, RetVT, Op0, Op0IsKill);
    1553           0 :   case PPCISD::MTCTR: return fastEmit_PPCISD_MTCTR_r(VT, RetVT, Op0, Op0IsKill);
    1554           0 :   case PPCISD::MTVSRA: return fastEmit_PPCISD_MTVSRA_r(VT, RetVT, Op0, Op0IsKill);
    1555           0 :   case PPCISD::MTVSRZ: return fastEmit_PPCISD_MTVSRZ_r(VT, RetVT, Op0, Op0IsKill);
    1556           0 :   case PPCISD::SExtVElems: return fastEmit_PPCISD_SExtVElems_r(VT, RetVT, Op0, Op0IsKill);
    1557           0 :   case PPCISD::XXREVERSE: return fastEmit_PPCISD_XXREVERSE_r(VT, RetVT, Op0, Op0IsKill);
    1558             :   default: return 0;
    1559             :   }
    1560             : }
    1561             : 
    1562             : // FastEmit functions for ISD::ADD.
    1563             : 
    1564             : unsigned fastEmit_ISD_ADD_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1565           0 :   if (RetVT.SimpleTy != MVT::i1)
    1566             :     return 0;
    1567             :   return fastEmitInst_rr(PPC::CRXOR, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1568             : }
    1569             : 
    1570             : unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1571           0 :   if (RetVT.SimpleTy != MVT::i32)
    1572             :     return 0;
    1573             :   return fastEmitInst_rr(PPC::ADD4, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1574             : }
    1575             : 
    1576             : unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1577           0 :   if (RetVT.SimpleTy != MVT::i64)
    1578             :     return 0;
    1579             :   return fastEmitInst_rr(PPC::ADD8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1580             : }
    1581             : 
    1582             : unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1583           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1584             :     return 0;
    1585           0 :   if ((PPCSubTarget->hasAltivec())) {
    1586             :     return fastEmitInst_rr(PPC::VADDUBM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1587             :   }
    1588             :   return 0;
    1589             : }
    1590             : 
    1591             : unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1592           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1593             :     return 0;
    1594           0 :   if ((PPCSubTarget->hasAltivec())) {
    1595             :     return fastEmitInst_rr(PPC::VADDUHM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1596             :   }
    1597             :   return 0;
    1598             : }
    1599             : 
    1600             : unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1601           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1602             :     return 0;
    1603           0 :   if ((PPCSubTarget->hasAltivec())) {
    1604             :     return fastEmitInst_rr(PPC::VADDUWM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1605             :   }
    1606             :   return 0;
    1607             : }
    1608             : 
    1609             : unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1610           2 :   if (RetVT.SimpleTy != MVT::v2i64)
    1611             :     return 0;
    1612           2 :   if ((PPCSubTarget->hasP8Altivec())) {
    1613             :     return fastEmitInst_rr(PPC::VADDUDM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1614             :   }
    1615             :   return 0;
    1616             : }
    1617             : 
    1618             : unsigned fastEmit_ISD_ADD_MVT_v1i128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1619           0 :   if (RetVT.SimpleTy != MVT::v1i128)
    1620             :     return 0;
    1621           0 :   if ((PPCSubTarget->hasP8Altivec())) {
    1622             :     return fastEmitInst_rr(PPC::VADDUQM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1623             :   }
    1624             :   return 0;
    1625             : }
    1626             : 
    1627           2 : unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1628           2 :   switch (VT.SimpleTy) {
    1629           0 :   case MVT::i1: return fastEmit_ISD_ADD_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1630           0 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1631           0 :   case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1632           0 :   case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1633           0 :   case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1634           0 :   case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1635           2 :   case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1636           0 :   case MVT::v1i128: return fastEmit_ISD_ADD_MVT_v1i128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1637             :   default: return 0;
    1638             :   }
    1639             : }
    1640             : 
    1641             : // FastEmit functions for ISD::ADDC.
    1642             : 
    1643             : unsigned fastEmit_ISD_ADDC_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1644           0 :   if (RetVT.SimpleTy != MVT::i32)
    1645             :     return 0;
    1646             :   return fastEmitInst_rr(PPC::ADDC, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1647             : }
    1648             : 
    1649             : unsigned fastEmit_ISD_ADDC_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1650           0 :   if (RetVT.SimpleTy != MVT::i64)
    1651             :     return 0;
    1652             :   return fastEmitInst_rr(PPC::ADDC8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1653             : }
    1654             : 
    1655           0 : unsigned fastEmit_ISD_ADDC_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1656           0 :   switch (VT.SimpleTy) {
    1657           0 :   case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1658           0 :   case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1659             :   default: return 0;
    1660             :   }
    1661             : }
    1662             : 
    1663             : // FastEmit functions for ISD::ADDE.
    1664             : 
    1665             : unsigned fastEmit_ISD_ADDE_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1666           0 :   if (RetVT.SimpleTy != MVT::i32)
    1667             :     return 0;
    1668             :   return fastEmitInst_rr(PPC::ADDE, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1669             : }
    1670             : 
    1671             : unsigned fastEmit_ISD_ADDE_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1672           0 :   if (RetVT.SimpleTy != MVT::i64)
    1673             :     return 0;
    1674             :   return fastEmitInst_rr(PPC::ADDE8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1675             : }
    1676             : 
    1677           0 : unsigned fastEmit_ISD_ADDE_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1678           0 :   switch (VT.SimpleTy) {
    1679           0 :   case MVT::i32: return fastEmit_ISD_ADDE_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1680           0 :   case MVT::i64: return fastEmit_ISD_ADDE_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1681             :   default: return 0;
    1682             :   }
    1683             : }
    1684             : 
    1685             : // FastEmit functions for ISD::AND.
    1686             : 
    1687             : unsigned fastEmit_ISD_AND_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1688           0 :   if (RetVT.SimpleTy != MVT::i1)
    1689             :     return 0;
    1690             :   return fastEmitInst_rr(PPC::CRAND, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1691             : }
    1692             : 
    1693             : unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1694           0 :   if (RetVT.SimpleTy != MVT::i32)
    1695             :     return 0;
    1696             :   return fastEmitInst_rr(PPC::AND, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1697             : }
    1698             : 
    1699             : unsigned fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1700           1 :   if (RetVT.SimpleTy != MVT::i64)
    1701             :     return 0;
    1702             :   return fastEmitInst_rr(PPC::AND8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1703             : }
    1704             : 
    1705           4 : unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1706           4 :   if (RetVT.SimpleTy != MVT::v4i32)
    1707             :     return 0;
    1708           4 :   if ((PPCSubTarget->hasVSX())) {
    1709           8 :     return fastEmitInst_rr(PPC::XXLAND, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1710             :   }
    1711           0 :   if ((PPCSubTarget->hasAltivec())) {
    1712           0 :     return fastEmitInst_rr(PPC::VAND, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1713             :   }
    1714             :   return 0;
    1715             : }
    1716             : 
    1717          15 : unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1718          15 :   switch (VT.SimpleTy) {
    1719           0 :   case MVT::i1: return fastEmit_ISD_AND_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1720           0 :   case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1721           1 :   case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1722           4 :   case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1723             :   default: return 0;
    1724             :   }
    1725             : }
    1726             : 
    1727             : // FastEmit functions for ISD::BUILD_VECTOR.
    1728             : 
    1729           0 : unsigned fastEmit_ISD_BUILD_VECTOR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1730           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1731             :     return 0;
    1732           0 :   if ((PPCSubTarget->hasDirectMove()) && (!PPCSubTarget->isLittleEndian()) && (PPCSubTarget->isISA3_0())) {
    1733           0 :     return fastEmitInst_rr(PPC::MTVSRDD, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1734             :   }
    1735             :   return 0;
    1736             : }
    1737             : 
    1738             : unsigned fastEmit_ISD_BUILD_VECTOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1739           0 :   switch (VT.SimpleTy) {
    1740           0 :   case MVT::i64: return fastEmit_ISD_BUILD_VECTOR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1741             :   default: return 0;
    1742             :   }
    1743             : }
    1744             : 
    1745             : // FastEmit functions for ISD::FADD.
    1746             : 
    1747           2 : unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1748           2 :   if (RetVT.SimpleTy != MVT::f32)
    1749             :     return 0;
    1750           2 :   if ((PPCSubTarget->hasP8Vector())) {
    1751           0 :     return fastEmitInst_rr(PPC::XSADDSP, &PPC::VSSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1752             :   }
    1753           4 :   return fastEmitInst_rr(PPC::FADDS, &PPC::F4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1754             : }
    1755             : 
    1756          10 : unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1757          10 :   if (RetVT.SimpleTy != MVT::f64)
    1758             :     return 0;
    1759          10 :   if ((PPCSubTarget->hasVSX())) {
    1760          16 :     return fastEmitInst_rr(PPC::XSADDDP, &PPC::VSFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1761             :   }
    1762           4 :   return fastEmitInst_rr(PPC::FADD, &PPC::F8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1763             : }
    1764             : 
    1765             : unsigned fastEmit_ISD_FADD_MVT_f128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1766           0 :   if (RetVT.SimpleTy != MVT::f128)
    1767             :     return 0;
    1768           0 :   if ((PPCSubTarget->hasP9Vector())) {
    1769             :     return fastEmitInst_rr(PPC::XSADDQP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1770             :   }
    1771             :   return 0;
    1772             : }
    1773             : 
    1774           0 : unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1775           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1776             :     return 0;
    1777           0 :   if ((PPCSubTarget->hasVSX())) {
    1778           0 :     return fastEmitInst_rr(PPC::XVADDSP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1779             :   }
    1780           0 :   if ((PPCSubTarget->hasQPX())) {
    1781           0 :     return fastEmitInst_rr(PPC::QVFADDSs, &PPC::QSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1782             :   }
    1783           0 :   if ((PPCSubTarget->hasAltivec())) {
    1784           0 :     return fastEmitInst_rr(PPC::VADDFP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1785             :   }
    1786             :   return 0;
    1787             : }
    1788             : 
    1789             : unsigned fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1790           2 :   if (RetVT.SimpleTy != MVT::v2f64)
    1791             :     return 0;
    1792           2 :   if ((PPCSubTarget->hasVSX())) {
    1793             :     return fastEmitInst_rr(PPC::XVADDDP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1794             :   }
    1795             :   return 0;
    1796             : }
    1797             : 
    1798             : unsigned fastEmit_ISD_FADD_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1799           0 :   if (RetVT.SimpleTy != MVT::v4f64)
    1800             :     return 0;
    1801           0 :   if ((PPCSubTarget->hasQPX())) {
    1802             :     return fastEmitInst_rr(PPC::QVFADD, &PPC::QFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1803             :   }
    1804             :   return 0;
    1805             : }
    1806             : 
    1807          14 : unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1808          14 :   switch (VT.SimpleTy) {
    1809           2 :   case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1810          10 :   case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1811           0 :   case MVT::f128: return fastEmit_ISD_FADD_MVT_f128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1812           0 :   case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1813           2 :   case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1814           0 :   case MVT::v4f64: return fastEmit_ISD_FADD_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1815             :   default: return 0;
    1816             :   }
    1817             : }
    1818             : 
    1819             : // FastEmit functions for ISD::FDIV.
    1820             : 
    1821           0 : unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1822           0 :   if (RetVT.SimpleTy != MVT::f32)
    1823             :     return 0;
    1824           0 :   if ((PPCSubTarget->hasP8Vector())) {
    1825           0 :     return fastEmitInst_rr(PPC::XSDIVSP, &PPC::VSSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1826             :   }
    1827           0 :   return fastEmitInst_rr(PPC::FDIVS, &PPC::F4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1828             : }
    1829             : 
    1830           2 : unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1831           2 :   if (RetVT.SimpleTy != MVT::f64)
    1832             :     return 0;
    1833           2 :   if ((PPCSubTarget->hasVSX())) {
    1834           4 :     return fastEmitInst_rr(PPC::XSDIVDP, &PPC::VSFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1835             :   }
    1836           0 :   return fastEmitInst_rr(PPC::FDIV, &PPC::F8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1837             : }
    1838             : 
    1839             : unsigned fastEmit_ISD_FDIV_MVT_f128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1840           0 :   if (RetVT.SimpleTy != MVT::f128)
    1841             :     return 0;
    1842           0 :   if ((PPCSubTarget->hasP9Vector())) {
    1843             :     return fastEmitInst_rr(PPC::XSDIVQP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1844             :   }
    1845             :   return 0;
    1846             : }
    1847             : 
    1848             : unsigned fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1849           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1850             :     return 0;
    1851           0 :   if ((PPCSubTarget->hasVSX())) {
    1852             :     return fastEmitInst_rr(PPC::XVDIVSP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1853             :   }
    1854             :   return 0;
    1855             : }
    1856             : 
    1857             : unsigned fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1858           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1859             :     return 0;
    1860           0 :   if ((PPCSubTarget->hasVSX())) {
    1861             :     return fastEmitInst_rr(PPC::XVDIVDP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1862             :   }
    1863             :   return 0;
    1864             : }
    1865             : 
    1866           2 : unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1867           2 :   switch (VT.SimpleTy) {
    1868           0 :   case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1869           2 :   case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1870           0 :   case MVT::f128: return fastEmit_ISD_FDIV_MVT_f128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1871           0 :   case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1872           0 :   case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1873             :   default: return 0;
    1874             :   }
    1875             : }
    1876             : 
    1877             : // FastEmit functions for ISD::FMUL.
    1878             : 
    1879           0 : unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1880           0 :   if (RetVT.SimpleTy != MVT::f32)
    1881             :     return 0;
    1882           0 :   if ((PPCSubTarget->hasP8Vector())) {
    1883           0 :     return fastEmitInst_rr(PPC::XSMULSP, &PPC::VSSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1884             :   }
    1885           0 :   return fastEmitInst_rr(PPC::FMULS, &PPC::F4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1886             : }
    1887             : 
    1888           2 : unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1889           2 :   if (RetVT.SimpleTy != MVT::f64)
    1890             :     return 0;
    1891           2 :   if ((PPCSubTarget->hasVSX())) {
    1892           4 :     return fastEmitInst_rr(PPC::XSMULDP, &PPC::VSFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1893             :   }
    1894           0 :   return fastEmitInst_rr(PPC::FMUL, &PPC::F8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1895             : }
    1896             : 
    1897             : unsigned fastEmit_ISD_FMUL_MVT_f128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1898           0 :   if (RetVT.SimpleTy != MVT::f128)
    1899             :     return 0;
    1900           0 :   if ((PPCSubTarget->hasP9Vector())) {
    1901             :     return fastEmitInst_rr(PPC::XSMULQP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1902             :   }
    1903             :   return 0;
    1904             : }
    1905             : 
    1906           0 : unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1907           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1908             :     return 0;
    1909           0 :   if ((PPCSubTarget->hasVSX())) {
    1910           0 :     return fastEmitInst_rr(PPC::XVMULSP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1911             :   }
    1912           0 :   if ((PPCSubTarget->hasQPX())) {
    1913           0 :     return fastEmitInst_rr(PPC::QVFMULSs, &PPC::QSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1914             :   }
    1915             :   return 0;
    1916             : }
    1917             : 
    1918             : unsigned fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1919           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1920             :     return 0;
    1921           0 :   if ((PPCSubTarget->hasVSX())) {
    1922             :     return fastEmitInst_rr(PPC::XVMULDP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1923             :   }
    1924             :   return 0;
    1925             : }
    1926             : 
    1927             : unsigned fastEmit_ISD_FMUL_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1928           0 :   if (RetVT.SimpleTy != MVT::v4f64)
    1929             :     return 0;
    1930           0 :   if ((PPCSubTarget->hasQPX())) {
    1931             :     return fastEmitInst_rr(PPC::QVFMUL, &PPC::QFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1932             :   }
    1933             :   return 0;
    1934             : }
    1935             : 
    1936           2 : unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1937           2 :   switch (VT.SimpleTy) {
    1938           0 :   case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1939           2 :   case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1940           0 :   case MVT::f128: return fastEmit_ISD_FMUL_MVT_f128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1941           0 :   case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1942           0 :   case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1943           0 :   case MVT::v4f64: return fastEmit_ISD_FMUL_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1944             :   default: return 0;
    1945             :   }
    1946             : }
    1947             : 
    1948             : // FastEmit functions for ISD::FSUB.
    1949             : 
    1950           0 : unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1951           0 :   if (RetVT.SimpleTy != MVT::f32)
    1952             :     return 0;
    1953           0 :   if ((PPCSubTarget->hasP8Vector())) {
    1954           0 :     return fastEmitInst_rr(PPC::XSSUBSP, &PPC::VSSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1955             :   }
    1956           0 :   return fastEmitInst_rr(PPC::FSUBS, &PPC::F4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1957             : }
    1958             : 
    1959           0 : unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1960           0 :   if (RetVT.SimpleTy != MVT::f64)
    1961             :     return 0;
    1962           0 :   if ((PPCSubTarget->hasVSX())) {
    1963           0 :     return fastEmitInst_rr(PPC::XSSUBDP, &PPC::VSFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1964             :   }
    1965           0 :   return fastEmitInst_rr(PPC::FSUB, &PPC::F8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1966             : }
    1967             : 
    1968             : unsigned fastEmit_ISD_FSUB_MVT_f128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1969           0 :   if (RetVT.SimpleTy != MVT::f128)
    1970             :     return 0;
    1971           0 :   if ((PPCSubTarget->hasP9Vector())) {
    1972             :     return fastEmitInst_rr(PPC::XSSUBQP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1973             :   }
    1974             :   return 0;
    1975             : }
    1976             : 
    1977           0 : unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1978           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1979             :     return 0;
    1980           0 :   if ((PPCSubTarget->hasVSX())) {
    1981           0 :     return fastEmitInst_rr(PPC::XVSUBSP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1982             :   }
    1983           0 :   if ((PPCSubTarget->hasQPX())) {
    1984           0 :     return fastEmitInst_rr(PPC::QVFSUBSs, &PPC::QSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1985             :   }
    1986           0 :   if ((PPCSubTarget->hasAltivec())) {
    1987           0 :     return fastEmitInst_rr(PPC::VSUBFP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1988             :   }
    1989             :   return 0;
    1990             : }
    1991             : 
    1992             : unsigned fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1993           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1994             :     return 0;
    1995           0 :   if ((PPCSubTarget->hasVSX())) {
    1996             :     return fastEmitInst_rr(PPC::XVSUBDP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1997             :   }
    1998             :   return 0;
    1999             : }
    2000             : 
    2001             : unsigned fastEmit_ISD_FSUB_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2002           0 :   if (RetVT.SimpleTy != MVT::v4f64)
    2003             :     return 0;
    2004           0 :   if ((PPCSubTarget->hasQPX())) {
    2005             :     return fastEmitInst_rr(PPC::QVFSUB, &PPC::QFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2006             :   }
    2007             :   return 0;
    2008             : }
    2009             : 
    2010           0 : unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2011           0 :   switch (VT.SimpleTy) {
    2012           0 :   case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2013           0 :   case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2014           0 :   case MVT::f128: return fastEmit_ISD_FSUB_MVT_f128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2015           0 :   case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2016           0 :   case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2017           0 :   case MVT::v4f64: return fastEmit_ISD_FSUB_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2018             :   default: return 0;
    2019             :   }
    2020             : }
    2021             : 
    2022             : // FastEmit functions for ISD::MUL.
    2023             : 
    2024             : unsigned fastEmit_ISD_MUL_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2025           0 :   if (RetVT.SimpleTy != MVT::i1)
    2026             :     return 0;
    2027             :   return fastEmitInst_rr(PPC::CRAND, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2028             : }
    2029             : 
    2030             : unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2031           0 :   if (RetVT.SimpleTy != MVT::i32)
    2032             :     return 0;
    2033             :   return fastEmitInst_rr(PPC::MULLW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2034             : }
    2035             : 
    2036             : unsigned fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2037           0 :   if (RetVT.SimpleTy != MVT::i64)
    2038             :     return 0;
    2039             :   return fastEmitInst_rr(PPC::MULLD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2040             : }
    2041             : 
    2042             : unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2043           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2044             :     return 0;
    2045           0 :   if ((PPCSubTarget->hasP8Altivec())) {
    2046             :     return fastEmitInst_rr(PPC::VMULUWM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2047             :   }
    2048             :   return 0;
    2049             : }
    2050             : 
    2051           0 : unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2052           0 :   switch (VT.SimpleTy) {
    2053           0 :   case MVT::i1: return fastEmit_ISD_MUL_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2054           0 :   case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2055           0 :   case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2056           0 :   case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2057             :   default: return 0;
    2058             :   }
    2059             : }
    2060             : 
    2061             : // FastEmit functions for ISD::MULHS.
    2062             : 
    2063             : unsigned fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2064           0 :   if (RetVT.SimpleTy != MVT::i32)
    2065             :     return 0;
    2066             :   return fastEmitInst_rr(PPC::MULHW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2067             : }
    2068             : 
    2069             : unsigned fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2070           0 :   if (RetVT.SimpleTy != MVT::i64)
    2071             :     return 0;
    2072             :   return fastEmitInst_rr(PPC::MULHD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2073             : }
    2074             : 
    2075           0 : unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2076           0 :   switch (VT.SimpleTy) {
    2077           0 :   case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2078           0 :   case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2079             :   default: return 0;
    2080             :   }
    2081             : }
    2082             : 
    2083             : // FastEmit functions for ISD::MULHU.
    2084             : 
    2085             : unsigned fastEmit_ISD_MULHU_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2086           0 :   if (RetVT.SimpleTy != MVT::i32)
    2087             :     return 0;
    2088             :   return fastEmitInst_rr(PPC::MULHWU, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2089             : }
    2090             : 
    2091             : unsigned fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2092           0 :   if (RetVT.SimpleTy != MVT::i64)
    2093             :     return 0;
    2094             :   return fastEmitInst_rr(PPC::MULHDU, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2095             : }
    2096             : 
    2097           0 : unsigned fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2098           0 :   switch (VT.SimpleTy) {
    2099           0 :   case MVT::i32: return fastEmit_ISD_MULHU_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2100           0 :   case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2101             :   default: return 0;
    2102             :   }
    2103             : }
    2104             : 
    2105             : // FastEmit functions for ISD::OR.
    2106             : 
    2107             : unsigned fastEmit_ISD_OR_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2108           0 :   if (RetVT.SimpleTy != MVT::i1)
    2109             :     return 0;
    2110             :   return fastEmitInst_rr(PPC::CROR, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2111             : }
    2112             : 
    2113             : unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2114           0 :   if (RetVT.SimpleTy != MVT::i32)
    2115             :     return 0;
    2116             :   return fastEmitInst_rr(PPC::OR, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2117             : }
    2118             : 
    2119             : unsigned fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2120           0 :   if (RetVT.SimpleTy != MVT::i64)
    2121             :     return 0;
    2122             :   return fastEmitInst_rr(PPC::OR8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2123             : }
    2124             : 
    2125           2 : unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2126           2 :   if (RetVT.SimpleTy != MVT::v4i32)
    2127             :     return 0;
    2128           2 :   if ((PPCSubTarget->hasVSX())) {
    2129           4 :     return fastEmitInst_rr(PPC::XXLOR, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2130             :   }
    2131           0 :   if ((PPCSubTarget->hasAltivec())) {
    2132           0 :     return fastEmitInst_rr(PPC::VOR, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2133             :   }
    2134             :   return 0;
    2135             : }
    2136             : 
    2137           6 : unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2138           6 :   switch (VT.SimpleTy) {
    2139           0 :   case MVT::i1: return fastEmit_ISD_OR_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2140           0 :   case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2141           0 :   case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2142           2 :   case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2143             :   default: return 0;
    2144             :   }
    2145             : }
    2146             : 
    2147             : // FastEmit functions for ISD::SDIV.
    2148             : 
    2149             : unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2150           0 :   if (RetVT.SimpleTy != MVT::i32)
    2151             :     return 0;
    2152             :   return fastEmitInst_rr(PPC::DIVW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2153             : }
    2154             : 
    2155             : unsigned fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2156           0 :   if (RetVT.SimpleTy != MVT::i64)
    2157             :     return 0;
    2158             :   return fastEmitInst_rr(PPC::DIVD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2159             : }
    2160             : 
    2161           0 : unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2162           0 :   switch (VT.SimpleTy) {
    2163           0 :   case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2164           0 :   case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2165             :   default: return 0;
    2166             :   }
    2167             : }
    2168             : 
    2169             : // FastEmit functions for ISD::SHL.
    2170             : 
    2171             : unsigned fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2172           2 :   if (RetVT.SimpleTy != MVT::i32)
    2173             :     return 0;
    2174             :   return fastEmitInst_rr(PPC::SLW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2175             : }
    2176             : 
    2177             : unsigned fastEmit_ISD_SHL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2178           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2179             :     return 0;
    2180           0 :   if ((PPCSubTarget->hasAltivec())) {
    2181             :     return fastEmitInst_rr(PPC::VSLB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2182             :   }
    2183             :   return 0;
    2184             : }
    2185             : 
    2186             : unsigned fastEmit_ISD_SHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2187           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2188             :     return 0;
    2189           0 :   if ((PPCSubTarget->hasAltivec())) {
    2190             :     return fastEmitInst_rr(PPC::VSLH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2191             :   }
    2192             :   return 0;
    2193             : }
    2194             : 
    2195             : unsigned fastEmit_ISD_SHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2196           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2197             :     return 0;
    2198           0 :   if ((PPCSubTarget->hasAltivec())) {
    2199             :     return fastEmitInst_rr(PPC::VSLW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2200             :   }
    2201             :   return 0;
    2202             : }
    2203             : 
    2204             : unsigned fastEmit_ISD_SHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2205           2 :   if (RetVT.SimpleTy != MVT::v2i64)
    2206             :     return 0;
    2207           2 :   if ((PPCSubTarget->hasP8Altivec())) {
    2208             :     return fastEmitInst_rr(PPC::VSLD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2209             :   }
    2210             :   return 0;
    2211             : }
    2212             : 
    2213           5 : unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2214           5 :   switch (VT.SimpleTy) {
    2215           2 :   case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2216           0 :   case MVT::v16i8: return fastEmit_ISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2217           0 :   case MVT::v8i16: return fastEmit_ISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2218           0 :   case MVT::v4i32: return fastEmit_ISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2219           2 :   case MVT::v2i64: return fastEmit_ISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2220             :   default: return 0;
    2221             :   }
    2222             : }
    2223             : 
    2224             : // FastEmit functions for ISD::SRA.
    2225             : 
    2226             : unsigned fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2227           1 :   if (RetVT.SimpleTy != MVT::i32)
    2228             :     return 0;
    2229             :   return fastEmitInst_rr(PPC::SRAW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2230             : }
    2231             : 
    2232             : unsigned fastEmit_ISD_SRA_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2233           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2234             :     return 0;
    2235           0 :   if ((PPCSubTarget->hasAltivec())) {
    2236             :     return fastEmitInst_rr(PPC::VSRAB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2237             :   }
    2238             :   return 0;
    2239             : }
    2240             : 
    2241             : unsigned fastEmit_ISD_SRA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2242           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2243             :     return 0;
    2244           0 :   if ((PPCSubTarget->hasAltivec())) {
    2245             :     return fastEmitInst_rr(PPC::VSRAH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2246             :   }
    2247             :   return 0;
    2248             : }
    2249             : 
    2250             : unsigned fastEmit_ISD_SRA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2251           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2252             :     return 0;
    2253           0 :   if ((PPCSubTarget->hasAltivec())) {
    2254             :     return fastEmitInst_rr(PPC::VSRAW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2255             :   }
    2256             :   return 0;
    2257             : }
    2258             : 
    2259             : unsigned fastEmit_ISD_SRA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2260           2 :   if (RetVT.SimpleTy != MVT::v2i64)
    2261             :     return 0;
    2262           2 :   if ((PPCSubTarget->hasP8Altivec())) {
    2263             :     return fastEmitInst_rr(PPC::VSRAD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2264             :   }
    2265             :   return 0;
    2266             : }
    2267             : 
    2268           3 : unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2269           3 :   switch (VT.SimpleTy) {
    2270           1 :   case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2271           0 :   case MVT::v16i8: return fastEmit_ISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2272           0 :   case MVT::v8i16: return fastEmit_ISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2273           0 :   case MVT::v4i32: return fastEmit_ISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2274           2 :   case MVT::v2i64: return fastEmit_ISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2275             :   default: return 0;
    2276             :   }
    2277             : }
    2278             : 
    2279             : // FastEmit functions for ISD::SREM.
    2280             : 
    2281             : unsigned fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2282           0 :   if (RetVT.SimpleTy != MVT::i32)
    2283             :     return 0;
    2284           0 :   if ((PPCSubTarget->isISA3_0())) {
    2285             :     return fastEmitInst_rr(PPC::MODSW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2286             :   }
    2287             :   return 0;
    2288             : }
    2289             : 
    2290             : unsigned fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2291           0 :   if (RetVT.SimpleTy != MVT::i64)
    2292             :     return 0;
    2293           0 :   if ((PPCSubTarget->isISA3_0())) {
    2294             :     return fastEmitInst_rr(PPC::MODSD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2295             :   }
    2296             :   return 0;
    2297             : }
    2298             : 
    2299           0 : unsigned fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2300           0 :   switch (VT.SimpleTy) {
    2301           0 :   case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2302           0 :   case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2303             :   default: return 0;
    2304             :   }
    2305             : }
    2306             : 
    2307             : // FastEmit functions for ISD::SRL.
    2308             : 
    2309             : unsigned fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2310           2 :   if (RetVT.SimpleTy != MVT::i32)
    2311             :     return 0;
    2312             :   return fastEmitInst_rr(PPC::SRW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2313             : }
    2314             : 
    2315             : unsigned fastEmit_ISD_SRL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2316           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2317             :     return 0;
    2318           0 :   if ((PPCSubTarget->hasAltivec())) {
    2319             :     return fastEmitInst_rr(PPC::VSRB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2320             :   }
    2321             :   return 0;
    2322             : }
    2323             : 
    2324             : unsigned fastEmit_ISD_SRL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2325           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2326             :     return 0;
    2327           0 :   if ((PPCSubTarget->hasAltivec())) {
    2328             :     return fastEmitInst_rr(PPC::VSRH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2329             :   }
    2330             :   return 0;
    2331             : }
    2332             : 
    2333             : unsigned fastEmit_ISD_SRL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2334           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2335             :     return 0;
    2336           0 :   if ((PPCSubTarget->hasAltivec())) {
    2337             :     return fastEmitInst_rr(PPC::VSRW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2338             :   }
    2339             :   return 0;
    2340             : }
    2341             : 
    2342             : unsigned fastEmit_ISD_SRL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2343           2 :   if (RetVT.SimpleTy != MVT::v2i64)
    2344             :     return 0;
    2345           2 :   if ((PPCSubTarget->hasP8Altivec())) {
    2346             :     return fastEmitInst_rr(PPC::VSRD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2347             :   }
    2348             :   return 0;
    2349             : }
    2350             : 
    2351           4 : unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2352           4 :   switch (VT.SimpleTy) {
    2353           2 :   case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2354           0 :   case MVT::v16i8: return fastEmit_ISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2355           0 :   case MVT::v8i16: return fastEmit_ISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2356           0 :   case MVT::v4i32: return fastEmit_ISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2357           2 :   case MVT::v2i64: return fastEmit_ISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2358             :   default: return 0;
    2359             :   }
    2360             : }
    2361             : 
    2362             : // FastEmit functions for ISD::SUB.
    2363             : 
    2364             : unsigned fastEmit_ISD_SUB_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2365           0 :   if (RetVT.SimpleTy != MVT::i1)
    2366             :     return 0;
    2367             :   return fastEmitInst_rr(PPC::CRXOR, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2368             : }
    2369             : 
    2370             : unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2371           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2372             :     return 0;
    2373           0 :   if ((PPCSubTarget->hasAltivec())) {
    2374             :     return fastEmitInst_rr(PPC::VSUBUBM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2375             :   }
    2376             :   return 0;
    2377             : }
    2378             : 
    2379             : unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2380           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2381             :     return 0;
    2382           0 :   if ((PPCSubTarget->hasAltivec())) {
    2383             :     return fastEmitInst_rr(PPC::VSUBUHM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2384             :   }
    2385             :   return 0;
    2386             : }
    2387             : 
    2388             : unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2389           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2390             :     return 0;
    2391           0 :   if ((PPCSubTarget->hasAltivec())) {
    2392             :     return fastEmitInst_rr(PPC::VSUBUWM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2393             :   }
    2394             :   return 0;
    2395             : }
    2396             : 
    2397             : unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2398           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2399             :     return 0;
    2400           0 :   if ((PPCSubTarget->hasP8Altivec())) {
    2401             :     return fastEmitInst_rr(PPC::VSUBUDM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2402             :   }
    2403             :   return 0;
    2404             : }
    2405             : 
    2406             : unsigned fastEmit_ISD_SUB_MVT_v1i128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2407           0 :   if (RetVT.SimpleTy != MVT::v1i128)
    2408             :     return 0;
    2409           0 :   if ((PPCSubTarget->hasP8Altivec())) {
    2410             :     return fastEmitInst_rr(PPC::VSUBUQM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2411             :   }
    2412             :   return 0;
    2413             : }
    2414             : 
    2415           1 : unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2416           1 :   switch (VT.SimpleTy) {
    2417           0 :   case MVT::i1: return fastEmit_ISD_SUB_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2418           0 :   case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2419           0 :   case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2420           0 :   case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2421           0 :   case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2422           0 :   case MVT::v1i128: return fastEmit_ISD_SUB_MVT_v1i128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2423             :   default: return 0;
    2424             :   }
    2425             : }
    2426             : 
    2427             : // FastEmit functions for ISD::UDIV.
    2428             : 
    2429             : unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2430           0 :   if (RetVT.SimpleTy != MVT::i32)
    2431             :     return 0;
    2432             :   return fastEmitInst_rr(PPC::DIVWU, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2433             : }
    2434             : 
    2435             : unsigned fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2436           0 :   if (RetVT.SimpleTy != MVT::i64)
    2437             :     return 0;
    2438             :   return fastEmitInst_rr(PPC::DIVDU, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2439             : }
    2440             : 
    2441           0 : unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2442           0 :   switch (VT.SimpleTy) {
    2443           0 :   case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2444           0 :   case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2445             :   default: return 0;
    2446             :   }
    2447             : }
    2448             : 
    2449             : // FastEmit functions for ISD::UREM.
    2450             : 
    2451             : unsigned fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2452           0 :   if (RetVT.SimpleTy != MVT::i32)
    2453             :     return 0;
    2454           0 :   if ((PPCSubTarget->isISA3_0())) {
    2455             :     return fastEmitInst_rr(PPC::MODUW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2456             :   }
    2457             :   return 0;
    2458             : }
    2459             : 
    2460             : unsigned fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2461           0 :   if (RetVT.SimpleTy != MVT::i64)
    2462             :     return 0;
    2463           0 :   if ((PPCSubTarget->isISA3_0())) {
    2464             :     return fastEmitInst_rr(PPC::MODUD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2465             :   }
    2466             :   return 0;
    2467             : }
    2468             : 
    2469           0 : unsigned fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2470           0 :   switch (VT.SimpleTy) {
    2471           0 :   case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2472           0 :   case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2473             :   default: return 0;
    2474             :   }
    2475             : }
    2476             : 
    2477             : // FastEmit functions for ISD::XOR.
    2478             : 
    2479             : unsigned fastEmit_ISD_XOR_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2480           0 :   if (RetVT.SimpleTy != MVT::i1)
    2481             :     return 0;
    2482             :   return fastEmitInst_rr(PPC::CRXOR, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2483             : }
    2484             : 
    2485             : unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2486           0 :   if (RetVT.SimpleTy != MVT::i32)
    2487             :     return 0;
    2488             :   return fastEmitInst_rr(PPC::XOR, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2489             : }
    2490             : 
    2491             : unsigned fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2492           0 :   if (RetVT.SimpleTy != MVT::i64)
    2493             :     return 0;
    2494             :   return fastEmitInst_rr(PPC::XOR8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2495             : }
    2496             : 
    2497           2 : unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2498           2 :   if (RetVT.SimpleTy != MVT::v4i32)
    2499             :     return 0;
    2500           2 :   if ((PPCSubTarget->hasVSX())) {
    2501           4 :     return fastEmitInst_rr(PPC::XXLXOR, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2502             :   }
    2503           0 :   if ((PPCSubTarget->hasAltivec())) {
    2504           0 :     return fastEmitInst_rr(PPC::VXOR, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2505             :   }
    2506             :   return 0;
    2507             : }
    2508             : 
    2509           6 : unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2510           6 :   switch (VT.SimpleTy) {
    2511           0 :   case MVT::i1: return fastEmit_ISD_XOR_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2512           0 :   case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2513           0 :   case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2514           2 :   case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2515             :   default: return 0;
    2516             :   }
    2517             : }
    2518             : 
    2519             : // FastEmit functions for PPCISD::CMPB.
    2520             : 
    2521             : unsigned fastEmit_PPCISD_CMPB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2522           0 :   if (RetVT.SimpleTy != MVT::i32)
    2523             :     return 0;
    2524             :   return fastEmitInst_rr(PPC::CMPB, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2525             : }
    2526             : 
    2527             : unsigned fastEmit_PPCISD_CMPB_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2528           0 :   if (RetVT.SimpleTy != MVT::i64)
    2529             :     return 0;
    2530             :   return fastEmitInst_rr(PPC::CMPB8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2531             : }
    2532             : 
    2533           0 : unsigned fastEmit_PPCISD_CMPB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2534           0 :   switch (VT.SimpleTy) {
    2535           0 :   case MVT::i32: return fastEmit_PPCISD_CMPB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2536           0 :   case MVT::i64: return fastEmit_PPCISD_CMPB_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2537             :   default: return 0;
    2538             :   }
    2539             : }
    2540             : 
    2541             : // FastEmit functions for PPCISD::FADDRTZ.
    2542             : 
    2543             : unsigned fastEmit_PPCISD_FADDRTZ_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2544           0 :   if (RetVT.SimpleTy != MVT::f64)
    2545             :     return 0;
    2546             :   return fastEmitInst_rr(PPC::FADDrtz, &PPC::F8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2547             : }
    2548             : 
    2549             : unsigned fastEmit_PPCISD_FADDRTZ_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2550           0 :   switch (VT.SimpleTy) {
    2551           0 :   case MVT::f64: return fastEmit_PPCISD_FADDRTZ_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2552             :   default: return 0;
    2553             :   }
    2554             : }
    2555             : 
    2556             : // FastEmit functions for PPCISD::SHL.
    2557             : 
    2558             : unsigned fastEmit_PPCISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2559           0 :   if (RetVT.SimpleTy != MVT::i32)
    2560             :     return 0;
    2561             :   return fastEmitInst_rr(PPC::SLW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2562             : }
    2563             : 
    2564             : unsigned fastEmit_PPCISD_SHL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2565           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2566             :     return 0;
    2567           0 :   if ((PPCSubTarget->hasAltivec())) {
    2568             :     return fastEmitInst_rr(PPC::VSLB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2569             :   }
    2570             :   return 0;
    2571             : }
    2572             : 
    2573             : unsigned fastEmit_PPCISD_SHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2574           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2575             :     return 0;
    2576           0 :   if ((PPCSubTarget->hasAltivec())) {
    2577             :     return fastEmitInst_rr(PPC::VSLH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2578             :   }
    2579             :   return 0;
    2580             : }
    2581             : 
    2582             : unsigned fastEmit_PPCISD_SHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2583           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2584             :     return 0;
    2585           0 :   if ((PPCSubTarget->hasAltivec())) {
    2586             :     return fastEmitInst_rr(PPC::VSLW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2587             :   }
    2588             :   return 0;
    2589             : }
    2590             : 
    2591             : unsigned fastEmit_PPCISD_SHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2592           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2593             :     return 0;
    2594           0 :   if ((PPCSubTarget->hasP8Altivec())) {
    2595             :     return fastEmitInst_rr(PPC::VSLD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2596             :   }
    2597             :   return 0;
    2598             : }
    2599             : 
    2600           0 : unsigned fastEmit_PPCISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2601           0 :   switch (VT.SimpleTy) {
    2602           0 :   case MVT::i32: return fastEmit_PPCISD_SHL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2603           0 :   case MVT::v16i8: return fastEmit_PPCISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2604           0 :   case MVT::v8i16: return fastEmit_PPCISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2605           0 :   case MVT::v4i32: return fastEmit_PPCISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2606           0 :   case MVT::v2i64: return fastEmit_PPCISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2607             :   default: return 0;
    2608             :   }
    2609             : }
    2610             : 
    2611             : // FastEmit functions for PPCISD::SRA.
    2612             : 
    2613             : unsigned fastEmit_PPCISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2614           0 :   if (RetVT.SimpleTy != MVT::i32)
    2615             :     return 0;
    2616             :   return fastEmitInst_rr(PPC::SRAW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2617             : }
    2618             : 
    2619             : unsigned fastEmit_PPCISD_SRA_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2620           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2621             :     return 0;
    2622           0 :   if ((PPCSubTarget->hasAltivec())) {
    2623             :     return fastEmitInst_rr(PPC::VSRAB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2624             :   }
    2625             :   return 0;
    2626             : }
    2627             : 
    2628             : unsigned fastEmit_PPCISD_SRA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2629           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2630             :     return 0;
    2631           0 :   if ((PPCSubTarget->hasAltivec())) {
    2632             :     return fastEmitInst_rr(PPC::VSRAH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2633             :   }
    2634             :   return 0;
    2635             : }
    2636             : 
    2637             : unsigned fastEmit_PPCISD_SRA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2638           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2639             :     return 0;
    2640           0 :   if ((PPCSubTarget->hasAltivec())) {
    2641             :     return fastEmitInst_rr(PPC::VSRAW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2642             :   }
    2643             :   return 0;
    2644             : }
    2645             : 
    2646             : unsigned fastEmit_PPCISD_SRA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2647           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2648             :     return 0;
    2649           0 :   if ((PPCSubTarget->hasP8Altivec())) {
    2650             :     return fastEmitInst_rr(PPC::VSRAD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2651             :   }
    2652             :   return 0;
    2653             : }
    2654             : 
    2655           0 : unsigned fastEmit_PPCISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2656           0 :   switch (VT.SimpleTy) {
    2657           0 :   case MVT::i32: return fastEmit_PPCISD_SRA_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2658           0 :   case MVT::v16i8: return fastEmit_PPCISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2659           0 :   case MVT::v8i16: return fastEmit_PPCISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2660           0 :   case MVT::v4i32: return fastEmit_PPCISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2661           0 :   case MVT::v2i64: return fastEmit_PPCISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2662             :   default: return 0;
    2663             :   }
    2664             : }
    2665             : 
    2666             : // FastEmit functions for PPCISD::SRL.
    2667             : 
    2668             : unsigned fastEmit_PPCISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2669           0 :   if (RetVT.SimpleTy != MVT::i32)
    2670             :     return 0;
    2671             :   return fastEmitInst_rr(PPC::SRW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2672             : }
    2673             : 
    2674             : unsigned fastEmit_PPCISD_SRL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2675           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2676             :     return 0;
    2677           0 :   if ((PPCSubTarget->hasAltivec())) {
    2678             :     return fastEmitInst_rr(PPC::VSRB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2679             :   }
    2680             :   return 0;
    2681             : }
    2682             : 
    2683             : unsigned fastEmit_PPCISD_SRL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2684           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2685             :     return 0;
    2686           0 :   if ((PPCSubTarget->hasAltivec())) {
    2687             :     return fastEmitInst_rr(PPC::VSRH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2688             :   }
    2689             :   return 0;
    2690             : }
    2691             : 
    2692             : unsigned fastEmit_PPCISD_SRL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2693           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2694             :     return 0;
    2695           0 :   if ((PPCSubTarget->hasAltivec())) {
    2696             :     return fastEmitInst_rr(PPC::VSRW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2697             :   }
    2698             :   return 0;
    2699             : }
    2700             : 
    2701             : unsigned fastEmit_PPCISD_SRL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2702           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2703             :     return 0;
    2704           0 :   if ((PPCSubTarget->hasP8Altivec())) {
    2705             :     return fastEmitInst_rr(PPC::VSRD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2706             :   }
    2707             :   return 0;
    2708             : }
    2709             : 
    2710           0 : unsigned fastEmit_PPCISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2711           0 :   switch (VT.SimpleTy) {
    2712           0 :   case MVT::i32: return fastEmit_PPCISD_SRL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2713           0 :   case MVT::v16i8: return fastEmit_PPCISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2714           0 :   case MVT::v8i16: return fastEmit_PPCISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2715           0 :   case MVT::v4i32: return fastEmit_PPCISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2716           0 :   case MVT::v2i64: return fastEmit_PPCISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2717             :   default: return 0;
    2718             :   }
    2719             : }
    2720             : 
    2721             : // Top-level FastEmit function.
    2722             : 
    2723          60 : unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) override {
    2724          60 :   switch (Opcode) {
    2725           2 :   case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2726           0 :   case ISD::ADDC: return fastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2727           0 :   case ISD::ADDE: return fastEmit_ISD_ADDE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2728          15 :   case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2729           0 :   case ISD::BUILD_VECTOR: return fastEmit_ISD_BUILD_VECTOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2730          14 :   case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2731           2 :   case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2732           2 :   case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2733           0 :   case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2734           0 :   case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2735           0 :   case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2736           0 :   case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2737           6 :   case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2738           0 :   case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2739           5 :   case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2740           3 :   case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2741           0 :   case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2742           4 :   case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2743           1 :   case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2744           0 :   case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2745           0 :   case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2746           6 :   case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2747           0 :   case PPCISD::CMPB: return fastEmit_PPCISD_CMPB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2748           0 :   case PPCISD::FADDRTZ: return fastEmit_PPCISD_FADDRTZ_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2749           0 :   case PPCISD::SHL: return fastEmit_PPCISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2750           0 :   case PPCISD::SRA: return fastEmit_PPCISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2751           0 :   case PPCISD::SRL: return fastEmit_PPCISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2752             :   default: return 0;
    2753             :   }
    2754             : }
    2755             : 
    2756             : // FastEmit functions for ISD::SRA.
    2757             : 
    2758             : unsigned fastEmit_ISD_SRA_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2759           1 :   if (RetVT.SimpleTy != MVT::i32)
    2760             :     return 0;
    2761             :   return fastEmitInst_ri(PPC::SRAWI, &PPC::GPRCRegClass, Op0, Op0IsKill, imm1);
    2762             : }
    2763             : 
    2764             : unsigned fastEmit_ISD_SRA_MVT_i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2765           0 :   if (RetVT.SimpleTy != MVT::i64)
    2766             :     return 0;
    2767             :   return fastEmitInst_ri(PPC::SRADI, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
    2768             : }
    2769             : 
    2770           1 : unsigned fastEmit_ISD_SRA_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2771           1 :   switch (VT.SimpleTy) {
    2772           1 :   case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1);
    2773           0 :   case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri(RetVT, Op0, Op0IsKill, imm1);
    2774             :   default: return 0;
    2775             :   }
    2776             : }
    2777             : 
    2778             : // FastEmit functions for PPCISD::QVESPLATI.
    2779             : 
    2780             : unsigned fastEmit_PPCISD_QVESPLATI_MVT_v4i1_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2781           0 :   if (RetVT.SimpleTy != MVT::v4i1)
    2782             :     return 0;
    2783           0 :   if ((PPCSubTarget->hasQPX())) {
    2784             :     return fastEmitInst_ri(PPC::QVESPLATIb, &PPC::QBRCRegClass, Op0, Op0IsKill, imm1);
    2785             :   }
    2786             :   return 0;
    2787             : }
    2788             : 
    2789             : unsigned fastEmit_PPCISD_QVESPLATI_MVT_v4f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2790           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    2791             :     return 0;
    2792           0 :   if ((PPCSubTarget->hasQPX())) {
    2793             :     return fastEmitInst_ri(PPC::QVESPLATIs, &PPC::QSRCRegClass, Op0, Op0IsKill, imm1);
    2794             :   }
    2795             :   return 0;
    2796             : }
    2797             : 
    2798             : unsigned fastEmit_PPCISD_QVESPLATI_MVT_v4f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2799           0 :   if (RetVT.SimpleTy != MVT::v4f64)
    2800             :     return 0;
    2801           0 :   if ((PPCSubTarget->hasQPX())) {
    2802             :     return fastEmitInst_ri(PPC::QVESPLATI, &PPC::QFRCRegClass, Op0, Op0IsKill, imm1);
    2803             :   }
    2804             :   return 0;
    2805             : }
    2806             : 
    2807           0 : unsigned fastEmit_PPCISD_QVESPLATI_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2808           0 :   switch (VT.SimpleTy) {
    2809           0 :   case MVT::v4i1: return fastEmit_PPCISD_QVESPLATI_MVT_v4i1_ri(RetVT, Op0, Op0IsKill, imm1);
    2810           0 :   case MVT::v4f32: return fastEmit_PPCISD_QVESPLATI_MVT_v4f32_ri(RetVT, Op0, Op0IsKill, imm1);
    2811           0 :   case MVT::v4f64: return fastEmit_PPCISD_QVESPLATI_MVT_v4f64_ri(RetVT, Op0, Op0IsKill, imm1);
    2812             :   default: return 0;
    2813             :   }
    2814             : }
    2815             : 
    2816             : // FastEmit functions for PPCISD::TC_RETURN.
    2817             : 
    2818             : unsigned fastEmit_PPCISD_TC_RETURN_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2819           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2820             :     return 0;
    2821             :   return fastEmitInst_ri(PPC::TCRETURNri, &PPC::CTRRCRegClass, Op0, Op0IsKill, imm1);
    2822             : }
    2823             : 
    2824             : unsigned fastEmit_PPCISD_TC_RETURN_MVT_i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2825           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2826             :     return 0;
    2827             :   return fastEmitInst_ri(PPC::TCRETURNri8, &PPC::CTRRC8RegClass, Op0, Op0IsKill, imm1);
    2828             : }
    2829             : 
    2830           0 : unsigned fastEmit_PPCISD_TC_RETURN_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2831           0 :   switch (VT.SimpleTy) {
    2832           0 :   case MVT::i32: return fastEmit_PPCISD_TC_RETURN_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1);
    2833           0 :   case MVT::i64: return fastEmit_PPCISD_TC_RETURN_MVT_i64_ri(RetVT, Op0, Op0IsKill, imm1);
    2834             :   default: return 0;
    2835             :   }
    2836             : }
    2837             : 
    2838             : // Top-level FastEmit function.
    2839             : 
    2840          42 : unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) override {
    2841          65 :   if (VT == MVT::i32 && Predicate_imm32SExt16(imm1))
    2842          23 :     if (unsigned Reg = fastEmit_ri_Predicate_imm32SExt16(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    2843             :       return Reg;
    2844             : 
    2845          41 :   if (VT == MVT::i64 && Predicate_imm64SExt16(imm1))
    2846          19 :     if (unsigned Reg = fastEmit_ri_Predicate_imm64SExt16(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    2847             :       return Reg;
    2848             : 
    2849           5 :   switch (Opcode) {
    2850           1 :   case ISD::SRA: return fastEmit_ISD_SRA_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    2851           0 :   case PPCISD::QVESPLATI: return fastEmit_PPCISD_QVESPLATI_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    2852           0 :   case PPCISD::TC_RETURN: return fastEmit_PPCISD_TC_RETURN_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    2853             :   default: return 0;
    2854             :   }
    2855             : }
    2856             : 
    2857             : // FastEmit functions for ISD::ADD.
    2858             : 
    2859             : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2860          20 :   if (RetVT.SimpleTy != MVT::i32)
    2861             :     return 0;
    2862          20 :   return fastEmitInst_ri(PPC::ADDI, &PPC::GPRCRegClass, Op0, Op0IsKill, imm1);
    2863             : }
    2864             : 
    2865             : unsigned fastEmit_ISD_ADD_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2866          20 :   switch (VT.SimpleTy) {
    2867          20 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, Op0IsKill, imm1);
    2868             :   default: return 0;
    2869             :   }
    2870             : }
    2871             : 
    2872             : // FastEmit functions for ISD::ADDC.
    2873             : 
    2874             : unsigned fastEmit_ISD_ADDC_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2875           0 :   if (RetVT.SimpleTy != MVT::i32)
    2876             :     return 0;
    2877             :   return fastEmitInst_ri(PPC::ADDIC, &PPC::GPRCRegClass, Op0, Op0IsKill, imm1);
    2878             : }
    2879             : 
    2880             : unsigned fastEmit_ISD_ADDC_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2881           0 :   switch (VT.SimpleTy) {
    2882           0 :   case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, Op0IsKill, imm1);
    2883             :   default: return 0;
    2884             :   }
    2885             : }
    2886             : 
    2887             : // FastEmit functions for ISD::MUL.
    2888             : 
    2889             : unsigned fastEmit_ISD_MUL_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2890           0 :   if (RetVT.SimpleTy != MVT::i32)
    2891             :     return 0;
    2892             :   return fastEmitInst_ri(PPC::MULLI, &PPC::GPRCRegClass, Op0, Op0IsKill, imm1);
    2893             : }
    2894             : 
    2895             : unsigned fastEmit_ISD_MUL_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2896           0 :   switch (VT.SimpleTy) {
    2897           0 :   case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, Op0IsKill, imm1);
    2898             :   default: return 0;
    2899             :   }
    2900             : }
    2901             : 
    2902             : // FastEmit functions for PPCISD::XXSPLT.
    2903             : 
    2904             : unsigned fastEmit_PPCISD_XXSPLT_MVT_v4i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2905           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2906             :     return 0;
    2907           0 :   if ((PPCSubTarget->hasVSX())) {
    2908             :     return fastEmitInst_ri(PPC::XXSPLTW, &PPC::VSRCRegClass, Op0, Op0IsKill, imm1);
    2909             :   }
    2910             :   return 0;
    2911             : }
    2912             : 
    2913           0 : unsigned fastEmit_PPCISD_XXSPLT_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2914           0 :   switch (VT.SimpleTy) {
    2915           0 :   case MVT::v4i32: return fastEmit_PPCISD_XXSPLT_MVT_v4i32_ri_Predicate_imm32SExt16(RetVT, Op0, Op0IsKill, imm1);
    2916             :   default: return 0;
    2917             :   }
    2918             : }
    2919             : 
    2920             : // Top-level FastEmit function.
    2921             : 
    2922          23 : unsigned fastEmit_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2923          23 :   switch (Opcode) {
    2924          20 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm32SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
    2925           0 :   case ISD::ADDC: return fastEmit_ISD_ADDC_ri_Predicate_imm32SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
    2926           0 :   case ISD::MUL: return fastEmit_ISD_MUL_ri_Predicate_imm32SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
    2927           0 :   case PPCISD::XXSPLT: return fastEmit_PPCISD_XXSPLT_ri_Predicate_imm32SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
    2928             :   default: return 0;
    2929             :   }
    2930             : }
    2931             : 
    2932             : // FastEmit functions for ISD::ADD.
    2933             : 
    2934             : unsigned fastEmit_ISD_ADD_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2935          17 :   if (RetVT.SimpleTy != MVT::i64)
    2936             :     return 0;
    2937          17 :   return fastEmitInst_ri(PPC::ADDI8, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
    2938             : }
    2939             : 
    2940             : unsigned fastEmit_ISD_ADD_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2941          17 :   switch (VT.SimpleTy) {
    2942          17 :   case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, Op0IsKill, imm1);
    2943             :   default: return 0;
    2944             :   }
    2945             : }
    2946             : 
    2947             : // FastEmit functions for ISD::ADDC.
    2948             : 
    2949             : unsigned fastEmit_ISD_ADDC_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2950           0 :   if (RetVT.SimpleTy != MVT::i64)
    2951             :     return 0;
    2952             :   return fastEmitInst_ri(PPC::ADDIC8, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
    2953             : }
    2954             : 
    2955             : unsigned fastEmit_ISD_ADDC_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2956           0 :   switch (VT.SimpleTy) {
    2957           0 :   case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, Op0IsKill, imm1);
    2958             :   default: return 0;
    2959             :   }
    2960             : }
    2961             : 
    2962             : // FastEmit functions for ISD::MUL.
    2963             : 
    2964             : unsigned fastEmit_ISD_MUL_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2965           0 :   if (RetVT.SimpleTy != MVT::i64)
    2966             :     return 0;
    2967             :   return fastEmitInst_ri(PPC::MULLI8, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
    2968             : }
    2969             : 
    2970             : unsigned fastEmit_ISD_MUL_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2971           0 :   switch (VT.SimpleTy) {
    2972           0 :   case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, Op0IsKill, imm1);
    2973             :   default: return 0;
    2974             :   }
    2975             : }
    2976             : 
    2977             : // Top-level FastEmit function.
    2978             : 
    2979          19 : unsigned fastEmit_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2980          19 :   switch (Opcode) {
    2981          17 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm64SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
    2982           0 :   case ISD::ADDC: return fastEmit_ISD_ADDC_ri_Predicate_imm64SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
    2983           0 :   case ISD::MUL: return fastEmit_ISD_MUL_ri_Predicate_imm64SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
    2984             :   default: return 0;
    2985             :   }
    2986             : }
    2987             : 

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