LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/PowerPC - PPCGenFastISel.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 151 1188 12.7 %
Date: 2017-09-14 15:23:50 Functions: 27 118 22.9 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* "Fast" Instruction Selector for the PPC target                             *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : 
      10             : // FastEmit Immediate Predicate functions.
      11             : static bool Predicate_imm32SExt16(int64_t Imm) {
      12             : 
      13             :   // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
      14             :   // sign extended field.  Used by instructions like 'addi'.
      15          23 :   return (int32_t)Imm == (short)Imm;
      16             : 
      17             : }
      18             : static bool Predicate_imm64SExt16(int64_t Imm) {
      19             : 
      20             :   // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
      21             :   // sign extended field.  Used by instructions like 'addi'.
      22          19 :   return (int64_t)Imm == (short)Imm;
      23             : 
      24             : }
      25             : static bool Predicate_immSExt5NonZero(int64_t Imm) {
      26             :  return Imm && isInt<5>(Imm); 
      27             : }
      28             : 
      29             : 
      30             : // FastEmit functions for ISD::READCYCLECOUNTER.
      31             : 
      32             : unsigned fastEmit_ISD_READCYCLECOUNTER_MVT_i64_(MVT RetVT) {
      33           0 :   if (RetVT.SimpleTy != MVT::i64)
      34             :     return 0;
      35           0 :   return fastEmitInst_(PPC::MFTB8, &PPC::G8RCRegClass);
      36             : }
      37             : 
      38             : unsigned fastEmit_ISD_READCYCLECOUNTER_(MVT VT, MVT RetVT) {
      39           0 :   switch (VT.SimpleTy) {
      40           0 :   case MVT::i64: return fastEmit_ISD_READCYCLECOUNTER_MVT_i64_(RetVT);
      41             :   default: return 0;
      42             :   }
      43             : }
      44             : 
      45             : // FastEmit functions for PPCISD::MFFS.
      46             : 
      47             : unsigned fastEmit_PPCISD_MFFS_MVT_f64_(MVT RetVT) {
      48           0 :   if (RetVT.SimpleTy != MVT::f64)
      49             :     return 0;
      50           0 :   return fastEmitInst_(PPC::MFFS, &PPC::F8RCRegClass);
      51             : }
      52             : 
      53             : unsigned fastEmit_PPCISD_MFFS_(MVT VT, MVT RetVT) {
      54           0 :   switch (VT.SimpleTy) {
      55           0 :   case MVT::f64: return fastEmit_PPCISD_MFFS_MVT_f64_(RetVT);
      56             :   default: return 0;
      57             :   }
      58             : }
      59             : 
      60             : // FastEmit functions for PPCISD::PPC32_GOT.
      61             : 
      62             : unsigned fastEmit_PPCISD_PPC32_GOT_MVT_i32_(MVT RetVT) {
      63           0 :   if (RetVT.SimpleTy != MVT::i32)
      64             :     return 0;
      65           0 :   return fastEmitInst_(PPC::PPC32GOT, &PPC::GPRCRegClass);
      66             : }
      67             : 
      68             : unsigned fastEmit_PPCISD_PPC32_GOT_(MVT VT, MVT RetVT) {
      69           0 :   switch (VT.SimpleTy) {
      70           0 :   case MVT::i32: return fastEmit_PPCISD_PPC32_GOT_MVT_i32_(RetVT);
      71             :   default: return 0;
      72             :   }
      73             : }
      74             : 
      75             : // Top-level FastEmit function.
      76             : 
      77           0 : unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode) override {
      78           0 :   switch (Opcode) {
      79           0 :   case ISD::READCYCLECOUNTER: return fastEmit_ISD_READCYCLECOUNTER_(VT, RetVT);
      80           0 :   case PPCISD::MFFS: return fastEmit_PPCISD_MFFS_(VT, RetVT);
      81           0 :   case PPCISD::PPC32_GOT: return fastEmit_PPCISD_PPC32_GOT_(VT, RetVT);
      82             :   default: return 0;
      83             :   }
      84             : }
      85             : 
      86             : // FastEmit functions for ISD::BITCAST.
      87             : 
      88           0 : unsigned fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      89           0 :   if (RetVT.SimpleTy != MVT::f64)
      90             :     return 0;
      91           0 :   if ((PPCSubTarget->hasDirectMove()) && (PPCSubTarget->hasVSX())) {
      92           0 :     return fastEmitInst_r(PPC::MTVSRD, &PPC::VSFRCRegClass, Op0, Op0IsKill);
      93             :   }
      94             :   return 0;
      95             : }
      96             : 
      97           0 : unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      98           0 :   if (RetVT.SimpleTy != MVT::i64)
      99             :     return 0;
     100           0 :   if ((PPCSubTarget->hasDirectMove()) && (PPCSubTarget->hasVSX())) {
     101           0 :     return fastEmitInst_r(PPC::MFVSRD, &PPC::G8RCRegClass, Op0, Op0IsKill);
     102             :   }
     103             :   return 0;
     104             : }
     105             : 
     106           2 : unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     107           2 :   switch (VT.SimpleTy) {
     108           0 :   case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0, Op0IsKill);
     109           0 :   case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0, Op0IsKill);
     110             :   default: return 0;
     111             :   }
     112             : }
     113             : 
     114             : // FastEmit functions for ISD::CTLZ.
     115             : 
     116             : unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     117           0 :   if (RetVT.SimpleTy != MVT::i32)
     118             :     return 0;
     119           0 :   return fastEmitInst_r(PPC::CNTLZW, &PPC::GPRCRegClass, Op0, Op0IsKill);
     120             : }
     121             : 
     122             : unsigned fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     123           0 :   if (RetVT.SimpleTy != MVT::i64)
     124             :     return 0;
     125           0 :   return fastEmitInst_r(PPC::CNTLZD, &PPC::G8RCRegClass, Op0, Op0IsKill);
     126             : }
     127             : 
     128             : unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     129           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     130             :     return 0;
     131           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     132           0 :     return fastEmitInst_r(PPC::VCLZB, &PPC::VRRCRegClass, Op0, Op0IsKill);
     133             :   }
     134             :   return 0;
     135             : }
     136             : 
     137             : unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     138           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     139             :     return 0;
     140           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     141           0 :     return fastEmitInst_r(PPC::VCLZH, &PPC::VRRCRegClass, Op0, Op0IsKill);
     142             :   }
     143             :   return 0;
     144             : }
     145             : 
     146             : unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     147           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     148             :     return 0;
     149           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     150           0 :     return fastEmitInst_r(PPC::VCLZW, &PPC::VRRCRegClass, Op0, Op0IsKill);
     151             :   }
     152             :   return 0;
     153             : }
     154             : 
     155             : unsigned fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     156           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     157             :     return 0;
     158           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     159           0 :     return fastEmitInst_r(PPC::VCLZD, &PPC::VRRCRegClass, Op0, Op0IsKill);
     160             :   }
     161             :   return 0;
     162             : }
     163             : 
     164           0 : unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     165           0 :   switch (VT.SimpleTy) {
     166           0 :   case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
     167           0 :   case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0, Op0IsKill);
     168           0 :   case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     169           0 :   case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     170           0 :   case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     171           0 :   case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     172             :   default: return 0;
     173             :   }
     174             : }
     175             : 
     176             : // FastEmit functions for ISD::CTPOP.
     177             : 
     178             : unsigned fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     179           0 :   if (RetVT.SimpleTy != MVT::i32)
     180             :     return 0;
     181           0 :   return fastEmitInst_r(PPC::POPCNTW, &PPC::GPRCRegClass, Op0, Op0IsKill);
     182             : }
     183             : 
     184             : unsigned fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     185           0 :   if (RetVT.SimpleTy != MVT::i64)
     186             :     return 0;
     187           0 :   return fastEmitInst_r(PPC::POPCNTD, &PPC::G8RCRegClass, Op0, Op0IsKill);
     188             : }
     189             : 
     190             : unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     191           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     192             :     return 0;
     193           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     194           0 :     return fastEmitInst_r(PPC::VPOPCNTB, &PPC::VRRCRegClass, Op0, Op0IsKill);
     195             :   }
     196             :   return 0;
     197             : }
     198             : 
     199             : unsigned fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     200           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     201             :     return 0;
     202           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     203           0 :     return fastEmitInst_r(PPC::VPOPCNTH, &PPC::VRRCRegClass, Op0, Op0IsKill);
     204             :   }
     205             :   return 0;
     206             : }
     207             : 
     208             : unsigned fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     209           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     210             :     return 0;
     211           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     212           0 :     return fastEmitInst_r(PPC::VPOPCNTW, &PPC::VRRCRegClass, Op0, Op0IsKill);
     213             :   }
     214             :   return 0;
     215             : }
     216             : 
     217             : unsigned fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     218           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     219             :     return 0;
     220           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     221           0 :     return fastEmitInst_r(PPC::VPOPCNTD, &PPC::VRRCRegClass, Op0, Op0IsKill);
     222             :   }
     223             :   return 0;
     224             : }
     225             : 
     226           0 : unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     227           0 :   switch (VT.SimpleTy) {
     228           0 :   case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0, Op0IsKill);
     229           0 :   case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0, Op0IsKill);
     230           0 :   case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     231           0 :   case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     232           0 :   case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     233           0 :   case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     234             :   default: return 0;
     235             :   }
     236             : }
     237             : 
     238             : // FastEmit functions for ISD::CTTZ.
     239             : 
     240             : unsigned fastEmit_ISD_CTTZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     241           0 :   if (RetVT.SimpleTy != MVT::i32)
     242             :     return 0;
     243           0 :   if ((PPCSubTarget->isISA3_0())) {
     244           0 :     return fastEmitInst_r(PPC::CNTTZW, &PPC::GPRCRegClass, Op0, Op0IsKill);
     245             :   }
     246             :   return 0;
     247             : }
     248             : 
     249             : unsigned fastEmit_ISD_CTTZ_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     250           0 :   if (RetVT.SimpleTy != MVT::i64)
     251             :     return 0;
     252           0 :   if ((PPCSubTarget->isISA3_0())) {
     253           0 :     return fastEmitInst_r(PPC::CNTTZD, &PPC::G8RCRegClass, Op0, Op0IsKill);
     254             :   }
     255             :   return 0;
     256             : }
     257             : 
     258             : unsigned fastEmit_ISD_CTTZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     259           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     260             :     return 0;
     261           0 :   if ((PPCSubTarget->hasP9Altivec())) {
     262           0 :     return fastEmitInst_r(PPC::VCTZB, &PPC::VRRCRegClass, Op0, Op0IsKill);
     263             :   }
     264             :   return 0;
     265             : }
     266             : 
     267             : unsigned fastEmit_ISD_CTTZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     268           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     269             :     return 0;
     270           0 :   if ((PPCSubTarget->hasP9Altivec())) {
     271           0 :     return fastEmitInst_r(PPC::VCTZH, &PPC::VRRCRegClass, Op0, Op0IsKill);
     272             :   }
     273             :   return 0;
     274             : }
     275             : 
     276             : unsigned fastEmit_ISD_CTTZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     277           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     278             :     return 0;
     279           0 :   if ((PPCSubTarget->hasP9Altivec())) {
     280           0 :     return fastEmitInst_r(PPC::VCTZW, &PPC::VRRCRegClass, Op0, Op0IsKill);
     281             :   }
     282             :   return 0;
     283             : }
     284             : 
     285             : unsigned fastEmit_ISD_CTTZ_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     286           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     287             :     return 0;
     288           0 :   if ((PPCSubTarget->hasP9Altivec())) {
     289           0 :     return fastEmitInst_r(PPC::VCTZD, &PPC::VRRCRegClass, Op0, Op0IsKill);
     290             :   }
     291             :   return 0;
     292             : }
     293             : 
     294           0 : unsigned fastEmit_ISD_CTTZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     295           0 :   switch (VT.SimpleTy) {
     296           0 :   case MVT::i32: return fastEmit_ISD_CTTZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
     297           0 :   case MVT::i64: return fastEmit_ISD_CTTZ_MVT_i64_r(RetVT, Op0, Op0IsKill);
     298           0 :   case MVT::v16i8: return fastEmit_ISD_CTTZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     299           0 :   case MVT::v8i16: return fastEmit_ISD_CTTZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     300           0 :   case MVT::v4i32: return fastEmit_ISD_CTTZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     301           0 :   case MVT::v2i64: return fastEmit_ISD_CTTZ_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     302             :   default: return 0;
     303             :   }
     304             : }
     305             : 
     306             : // FastEmit functions for ISD::FABS.
     307             : 
     308             : unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     309           0 :   if (RetVT.SimpleTy != MVT::f32)
     310             :     return 0;
     311           0 :   return fastEmitInst_r(PPC::FABSS, &PPC::F4RCRegClass, Op0, Op0IsKill);
     312             : }
     313             : 
     314           0 : unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     315           0 :   if (RetVT.SimpleTy != MVT::f64)
     316             :     return 0;
     317           0 :   if ((PPCSubTarget->hasVSX())) {
     318           0 :     return fastEmitInst_r(PPC::XSABSDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     319             :   }
     320           0 :   return fastEmitInst_r(PPC::FABSD, &PPC::F8RCRegClass, Op0, Op0IsKill);
     321             : }
     322             : 
     323           0 : unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     324           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     325             :     return 0;
     326           0 :   if ((PPCSubTarget->hasVSX())) {
     327           0 :     return fastEmitInst_r(PPC::XVABSSP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     328             :   }
     329           0 :   if ((PPCSubTarget->hasQPX())) {
     330           0 :     return fastEmitInst_r(PPC::QVFABSs, &PPC::QSRCRegClass, Op0, Op0IsKill);
     331             :   }
     332             :   return 0;
     333             : }
     334             : 
     335             : unsigned fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     336           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     337             :     return 0;
     338           0 :   if ((PPCSubTarget->hasVSX())) {
     339           0 :     return fastEmitInst_r(PPC::XVABSDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     340             :   }
     341             :   return 0;
     342             : }
     343             : 
     344             : unsigned fastEmit_ISD_FABS_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     345           0 :   if (RetVT.SimpleTy != MVT::v4f64)
     346             :     return 0;
     347           0 :   if ((PPCSubTarget->hasQPX())) {
     348           0 :     return fastEmitInst_r(PPC::QVFABS, &PPC::QFRCRegClass, Op0, Op0IsKill);
     349             :   }
     350             :   return 0;
     351             : }
     352             : 
     353           0 : unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     354           0 :   switch (VT.SimpleTy) {
     355           0 :   case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill);
     356           0 :   case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0, Op0IsKill);
     357           0 :   case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     358           0 :   case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     359           0 :   case MVT::v4f64: return fastEmit_ISD_FABS_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
     360             :   default: return 0;
     361             :   }
     362             : }
     363             : 
     364             : // FastEmit functions for ISD::FCEIL.
     365             : 
     366             : unsigned fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     367           0 :   if (RetVT.SimpleTy != MVT::f32)
     368             :     return 0;
     369           0 :   return fastEmitInst_r(PPC::FRIPS, &PPC::F4RCRegClass, Op0, Op0IsKill);
     370             : }
     371             : 
     372           0 : unsigned fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     373           0 :   if (RetVT.SimpleTy != MVT::f64)
     374             :     return 0;
     375           0 :   if ((PPCSubTarget->hasVSX())) {
     376           0 :     return fastEmitInst_r(PPC::XSRDPIP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     377             :   }
     378           0 :   return fastEmitInst_r(PPC::FRIPD, &PPC::F8RCRegClass, Op0, Op0IsKill);
     379             : }
     380             : 
     381           0 : unsigned fastEmit_ISD_FCEIL_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     382           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     383             :     return 0;
     384           0 :   if ((PPCSubTarget->hasVSX())) {
     385           0 :     return fastEmitInst_r(PPC::XVRSPIP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     386             :   }
     387           0 :   if ((PPCSubTarget->hasAltivec())) {
     388           0 :     return fastEmitInst_r(PPC::VRFIP, &PPC::VRRCRegClass, Op0, Op0IsKill);
     389             :   }
     390           0 :   if ((PPCSubTarget->hasQPX())) {
     391           0 :     return fastEmitInst_r(PPC::QVFRIPs, &PPC::QSRCRegClass, Op0, Op0IsKill);
     392             :   }
     393             :   return 0;
     394             : }
     395             : 
     396             : unsigned fastEmit_ISD_FCEIL_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     397           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     398             :     return 0;
     399           0 :   if ((PPCSubTarget->hasVSX())) {
     400           0 :     return fastEmitInst_r(PPC::XVRDPIP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     401             :   }
     402             :   return 0;
     403             : }
     404             : 
     405             : unsigned fastEmit_ISD_FCEIL_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     406           0 :   if (RetVT.SimpleTy != MVT::v4f64)
     407             :     return 0;
     408           0 :   if ((PPCSubTarget->hasQPX())) {
     409           0 :     return fastEmitInst_r(PPC::QVFRIP, &PPC::QFRCRegClass, Op0, Op0IsKill);
     410             :   }
     411             :   return 0;
     412             : }
     413             : 
     414           0 : unsigned fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     415           0 :   switch (VT.SimpleTy) {
     416           0 :   case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0, Op0IsKill);
     417           0 :   case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0, Op0IsKill);
     418           0 :   case MVT::v4f32: return fastEmit_ISD_FCEIL_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     419           0 :   case MVT::v2f64: return fastEmit_ISD_FCEIL_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     420           0 :   case MVT::v4f64: return fastEmit_ISD_FCEIL_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
     421             :   default: return 0;
     422             :   }
     423             : }
     424             : 
     425             : // FastEmit functions for ISD::FFLOOR.
     426             : 
     427             : unsigned fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     428           0 :   if (RetVT.SimpleTy != MVT::f32)
     429             :     return 0;
     430           0 :   return fastEmitInst_r(PPC::FRIMS, &PPC::F4RCRegClass, Op0, Op0IsKill);
     431             : }
     432             : 
     433           0 : unsigned fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     434           0 :   if (RetVT.SimpleTy != MVT::f64)
     435             :     return 0;
     436           0 :   if ((PPCSubTarget->hasVSX())) {
     437           0 :     return fastEmitInst_r(PPC::XSRDPIM, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     438             :   }
     439           0 :   return fastEmitInst_r(PPC::FRIMD, &PPC::F8RCRegClass, Op0, Op0IsKill);
     440             : }
     441             : 
     442           0 : unsigned fastEmit_ISD_FFLOOR_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     443           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     444             :     return 0;
     445           0 :   if ((PPCSubTarget->hasVSX())) {
     446           0 :     return fastEmitInst_r(PPC::XVRSPIM, &PPC::VSRCRegClass, Op0, Op0IsKill);
     447             :   }
     448           0 :   if ((PPCSubTarget->hasAltivec())) {
     449           0 :     return fastEmitInst_r(PPC::VRFIM, &PPC::VRRCRegClass, Op0, Op0IsKill);
     450             :   }
     451           0 :   if ((PPCSubTarget->hasQPX())) {
     452           0 :     return fastEmitInst_r(PPC::QVFRIMs, &PPC::QSRCRegClass, Op0, Op0IsKill);
     453             :   }
     454             :   return 0;
     455             : }
     456             : 
     457             : unsigned fastEmit_ISD_FFLOOR_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     458           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     459             :     return 0;
     460           0 :   if ((PPCSubTarget->hasVSX())) {
     461           0 :     return fastEmitInst_r(PPC::XVRDPIM, &PPC::VSRCRegClass, Op0, Op0IsKill);
     462             :   }
     463             :   return 0;
     464             : }
     465             : 
     466             : unsigned fastEmit_ISD_FFLOOR_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     467           0 :   if (RetVT.SimpleTy != MVT::v4f64)
     468             :     return 0;
     469           0 :   if ((PPCSubTarget->hasQPX())) {
     470           0 :     return fastEmitInst_r(PPC::QVFRIM, &PPC::QFRCRegClass, Op0, Op0IsKill);
     471             :   }
     472             :   return 0;
     473             : }
     474             : 
     475           0 : unsigned fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     476           0 :   switch (VT.SimpleTy) {
     477           0 :   case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0, Op0IsKill);
     478           0 :   case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0, Op0IsKill);
     479           0 :   case MVT::v4f32: return fastEmit_ISD_FFLOOR_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     480           0 :   case MVT::v2f64: return fastEmit_ISD_FFLOOR_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     481           0 :   case MVT::v4f64: return fastEmit_ISD_FFLOOR_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
     482             :   default: return 0;
     483             :   }
     484             : }
     485             : 
     486             : // FastEmit functions for ISD::FNEARBYINT.
     487             : 
     488             : unsigned fastEmit_ISD_FNEARBYINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     489           0 :   if (RetVT.SimpleTy != MVT::f64)
     490             :     return 0;
     491           0 :   if ((PPCSubTarget->hasVSX())) {
     492           0 :     return fastEmitInst_r(PPC::XSRDPIC, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     493             :   }
     494             :   return 0;
     495             : }
     496             : 
     497           0 : unsigned fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     498           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     499             :     return 0;
     500           0 :   if ((PPCSubTarget->hasVSX())) {
     501           0 :     return fastEmitInst_r(PPC::XVRSPIC, &PPC::VSRCRegClass, Op0, Op0IsKill);
     502             :   }
     503           0 :   if ((PPCSubTarget->hasAltivec())) {
     504           0 :     return fastEmitInst_r(PPC::VRFIN, &PPC::VRRCRegClass, Op0, Op0IsKill);
     505             :   }
     506             :   return 0;
     507             : }
     508             : 
     509             : unsigned fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     510           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     511             :     return 0;
     512           0 :   if ((PPCSubTarget->hasVSX())) {
     513           0 :     return fastEmitInst_r(PPC::XVRDPIC, &PPC::VSRCRegClass, Op0, Op0IsKill);
     514             :   }
     515             :   return 0;
     516             : }
     517             : 
     518           0 : unsigned fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     519           0 :   switch (VT.SimpleTy) {
     520           0 :   case MVT::f64: return fastEmit_ISD_FNEARBYINT_MVT_f64_r(RetVT, Op0, Op0IsKill);
     521           0 :   case MVT::v4f32: return fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     522           0 :   case MVT::v2f64: return fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     523             :   default: return 0;
     524             :   }
     525             : }
     526             : 
     527             : // FastEmit functions for ISD::FNEG.
     528             : 
     529             : unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     530           0 :   if (RetVT.SimpleTy != MVT::f32)
     531             :     return 0;
     532           0 :   return fastEmitInst_r(PPC::FNEGS, &PPC::F4RCRegClass, Op0, Op0IsKill);
     533             : }
     534             : 
     535           0 : unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     536           0 :   if (RetVT.SimpleTy != MVT::f64)
     537             :     return 0;
     538           0 :   if ((PPCSubTarget->hasVSX())) {
     539           0 :     return fastEmitInst_r(PPC::XSNEGDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     540             :   }
     541           0 :   return fastEmitInst_r(PPC::FNEGD, &PPC::F8RCRegClass, Op0, Op0IsKill);
     542             : }
     543             : 
     544           0 : unsigned fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     545           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     546             :     return 0;
     547           0 :   if ((PPCSubTarget->hasVSX())) {
     548           0 :     return fastEmitInst_r(PPC::XVNEGSP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     549             :   }
     550           0 :   if ((PPCSubTarget->hasQPX())) {
     551           0 :     return fastEmitInst_r(PPC::QVFNEGs, &PPC::QSRCRegClass, Op0, Op0IsKill);
     552             :   }
     553             :   return 0;
     554             : }
     555             : 
     556             : unsigned fastEmit_ISD_FNEG_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     557           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     558             :     return 0;
     559           0 :   if ((PPCSubTarget->hasVSX())) {
     560           0 :     return fastEmitInst_r(PPC::XVNEGDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     561             :   }
     562             :   return 0;
     563             : }
     564             : 
     565             : unsigned fastEmit_ISD_FNEG_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     566           0 :   if (RetVT.SimpleTy != MVT::v4f64)
     567             :     return 0;
     568           0 :   if ((PPCSubTarget->hasQPX())) {
     569           0 :     return fastEmitInst_r(PPC::QVFNEG, &PPC::QFRCRegClass, Op0, Op0IsKill);
     570             :   }
     571             :   return 0;
     572             : }
     573             : 
     574           0 : unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     575           0 :   switch (VT.SimpleTy) {
     576           0 :   case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill);
     577           0 :   case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0, Op0IsKill);
     578           0 :   case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     579           0 :   case MVT::v2f64: return fastEmit_ISD_FNEG_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     580           0 :   case MVT::v4f64: return fastEmit_ISD_FNEG_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
     581             :   default: return 0;
     582             :   }
     583             : }
     584             : 
     585             : // FastEmit functions for ISD::FP_ROUND.
     586             : 
     587             : unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     588           0 :   if (RetVT.SimpleTy != MVT::f32)
     589             :     return 0;
     590           0 :   return fastEmitInst_r(PPC::FRSP, &PPC::F4RCRegClass, Op0, Op0IsKill);
     591             : }
     592             : 
     593             : unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     594           0 :   switch (VT.SimpleTy) {
     595           0 :   case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
     596             :   default: return 0;
     597             :   }
     598             : }
     599             : 
     600             : // FastEmit functions for ISD::FP_TO_SINT.
     601             : 
     602           0 : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     603           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     604             :     return 0;
     605           0 :   if ((PPCSubTarget->hasVSX())) {
     606           0 :     return fastEmitInst_r(PPC::XVCVSPSXWS, &PPC::VSRCRegClass, Op0, Op0IsKill);
     607             :   }
     608           0 :   if ((PPCSubTarget->hasAltivec())) {
     609           0 :     return fastEmitInst_r(PPC::VCTSXS_0, &PPC::VRRCRegClass, Op0, Op0IsKill);
     610             :   }
     611             :   return 0;
     612             : }
     613             : 
     614             : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     615           2 :   if (RetVT.SimpleTy != MVT::v2i64)
     616             :     return 0;
     617           2 :   if ((PPCSubTarget->hasVSX())) {
     618           4 :     return fastEmitInst_r(PPC::XVCVDPSXDS, &PPC::VSRCRegClass, Op0, Op0IsKill);
     619             :   }
     620             :   return 0;
     621             : }
     622             : 
     623          20 : unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     624          20 :   switch (VT.SimpleTy) {
     625           0 :   case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     626           2 :   case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     627             :   default: return 0;
     628             :   }
     629             : }
     630             : 
     631             : // FastEmit functions for ISD::FP_TO_UINT.
     632             : 
     633           0 : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     634           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     635             :     return 0;
     636           0 :   if ((PPCSubTarget->hasVSX())) {
     637           0 :     return fastEmitInst_r(PPC::XVCVSPUXWS, &PPC::VSRCRegClass, Op0, Op0IsKill);
     638             :   }
     639           0 :   if ((PPCSubTarget->hasAltivec())) {
     640           0 :     return fastEmitInst_r(PPC::VCTUXS_0, &PPC::VRRCRegClass, Op0, Op0IsKill);
     641             :   }
     642             :   return 0;
     643             : }
     644             : 
     645             : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     646           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     647             :     return 0;
     648           0 :   if ((PPCSubTarget->hasVSX())) {
     649           0 :     return fastEmitInst_r(PPC::XVCVDPUXDS, &PPC::VSRCRegClass, Op0, Op0IsKill);
     650             :   }
     651             :   return 0;
     652             : }
     653             : 
     654           0 : unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     655           0 :   switch (VT.SimpleTy) {
     656           0 :   case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     657           0 :   case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     658             :   default: return 0;
     659             :   }
     660             : }
     661             : 
     662             : // FastEmit functions for ISD::FROUND.
     663             : 
     664             : unsigned fastEmit_ISD_FROUND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     665           0 :   if (RetVT.SimpleTy != MVT::f32)
     666             :     return 0;
     667           0 :   return fastEmitInst_r(PPC::FRINS, &PPC::F4RCRegClass, Op0, Op0IsKill);
     668             : }
     669             : 
     670           0 : unsigned fastEmit_ISD_FROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     671           0 :   if (RetVT.SimpleTy != MVT::f64)
     672             :     return 0;
     673           0 :   if ((PPCSubTarget->hasVSX())) {
     674           0 :     return fastEmitInst_r(PPC::XSRDPI, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     675             :   }
     676           0 :   return fastEmitInst_r(PPC::FRIND, &PPC::F8RCRegClass, Op0, Op0IsKill);
     677             : }
     678             : 
     679           0 : unsigned fastEmit_ISD_FROUND_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     680           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     681             :     return 0;
     682           0 :   if ((PPCSubTarget->hasVSX())) {
     683           0 :     return fastEmitInst_r(PPC::XVRSPI, &PPC::VSRCRegClass, Op0, Op0IsKill);
     684             :   }
     685           0 :   if ((PPCSubTarget->hasQPX())) {
     686           0 :     return fastEmitInst_r(PPC::QVFRINs, &PPC::QSRCRegClass, Op0, Op0IsKill);
     687             :   }
     688             :   return 0;
     689             : }
     690             : 
     691             : unsigned fastEmit_ISD_FROUND_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     692           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     693             :     return 0;
     694           0 :   if ((PPCSubTarget->hasVSX())) {
     695           0 :     return fastEmitInst_r(PPC::XVRDPI, &PPC::VSRCRegClass, Op0, Op0IsKill);
     696             :   }
     697             :   return 0;
     698             : }
     699             : 
     700             : unsigned fastEmit_ISD_FROUND_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     701           0 :   if (RetVT.SimpleTy != MVT::v4f64)
     702             :     return 0;
     703           0 :   if ((PPCSubTarget->hasQPX())) {
     704           0 :     return fastEmitInst_r(PPC::QVFRIN, &PPC::QFRCRegClass, Op0, Op0IsKill);
     705             :   }
     706             :   return 0;
     707             : }
     708             : 
     709           0 : unsigned fastEmit_ISD_FROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     710           0 :   switch (VT.SimpleTy) {
     711           0 :   case MVT::f32: return fastEmit_ISD_FROUND_MVT_f32_r(RetVT, Op0, Op0IsKill);
     712           0 :   case MVT::f64: return fastEmit_ISD_FROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
     713           0 :   case MVT::v4f32: return fastEmit_ISD_FROUND_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     714           0 :   case MVT::v2f64: return fastEmit_ISD_FROUND_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     715           0 :   case MVT::v4f64: return fastEmit_ISD_FROUND_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
     716             :   default: return 0;
     717             :   }
     718             : }
     719             : 
     720             : // FastEmit functions for ISD::FSQRT.
     721             : 
     722           0 : unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     723           0 :   if (RetVT.SimpleTy != MVT::f32)
     724             :     return 0;
     725           0 :   if ((PPCSubTarget->hasP8Vector())) {
     726           0 :     return fastEmitInst_r(PPC::XSSQRTSP, &PPC::VSSRCRegClass, Op0, Op0IsKill);
     727             :   }
     728           0 :   return fastEmitInst_r(PPC::FSQRTS, &PPC::F4RCRegClass, Op0, Op0IsKill);
     729             : }
     730             : 
     731           0 : unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     732           0 :   if (RetVT.SimpleTy != MVT::f64)
     733             :     return 0;
     734           0 :   if ((PPCSubTarget->hasVSX())) {
     735           0 :     return fastEmitInst_r(PPC::XSSQRTDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     736             :   }
     737           0 :   return fastEmitInst_r(PPC::FSQRT, &PPC::F8RCRegClass, Op0, Op0IsKill);
     738             : }
     739             : 
     740             : unsigned fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     741           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     742             :     return 0;
     743           0 :   if ((PPCSubTarget->hasVSX())) {
     744           0 :     return fastEmitInst_r(PPC::XVSQRTSP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     745             :   }
     746             :   return 0;
     747             : }
     748             : 
     749             : unsigned fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     750           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     751             :     return 0;
     752           0 :   if ((PPCSubTarget->hasVSX())) {
     753           0 :     return fastEmitInst_r(PPC::XVSQRTDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     754             :   }
     755             :   return 0;
     756             : }
     757             : 
     758           0 : unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     759           0 :   switch (VT.SimpleTy) {
     760           0 :   case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill);
     761           0 :   case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0, Op0IsKill);
     762           0 :   case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     763           0 :   case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     764             :   default: return 0;
     765             :   }
     766             : }
     767             : 
     768             : // FastEmit functions for ISD::FTRUNC.
     769             : 
     770             : unsigned fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     771           0 :   if (RetVT.SimpleTy != MVT::f32)
     772             :     return 0;
     773           0 :   return fastEmitInst_r(PPC::FRIZS, &PPC::F4RCRegClass, Op0, Op0IsKill);
     774             : }
     775             : 
     776           0 : unsigned fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     777           0 :   if (RetVT.SimpleTy != MVT::f64)
     778             :     return 0;
     779           0 :   if ((PPCSubTarget->hasVSX())) {
     780           0 :     return fastEmitInst_r(PPC::XSRDPIZ, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     781             :   }
     782           0 :   return fastEmitInst_r(PPC::FRIZD, &PPC::F8RCRegClass, Op0, Op0IsKill);
     783             : }
     784             : 
     785           0 : unsigned fastEmit_ISD_FTRUNC_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     786           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     787             :     return 0;
     788           0 :   if ((PPCSubTarget->hasVSX())) {
     789           0 :     return fastEmitInst_r(PPC::XVRSPIZ, &PPC::VSRCRegClass, Op0, Op0IsKill);
     790             :   }
     791           0 :   if ((PPCSubTarget->hasAltivec())) {
     792           0 :     return fastEmitInst_r(PPC::VRFIZ, &PPC::VRRCRegClass, Op0, Op0IsKill);
     793             :   }
     794           0 :   if ((PPCSubTarget->hasQPX())) {
     795           0 :     return fastEmitInst_r(PPC::QVFRIZs, &PPC::QSRCRegClass, Op0, Op0IsKill);
     796             :   }
     797             :   return 0;
     798             : }
     799             : 
     800             : unsigned fastEmit_ISD_FTRUNC_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     801           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     802             :     return 0;
     803           0 :   if ((PPCSubTarget->hasVSX())) {
     804           0 :     return fastEmitInst_r(PPC::XVRDPIZ, &PPC::VSRCRegClass, Op0, Op0IsKill);
     805             :   }
     806             :   return 0;
     807             : }
     808             : 
     809             : unsigned fastEmit_ISD_FTRUNC_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     810           0 :   if (RetVT.SimpleTy != MVT::v4f64)
     811             :     return 0;
     812           0 :   if ((PPCSubTarget->hasQPX())) {
     813           0 :     return fastEmitInst_r(PPC::QVFRIZ, &PPC::QFRCRegClass, Op0, Op0IsKill);
     814             :   }
     815             :   return 0;
     816             : }
     817             : 
     818           0 : unsigned fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     819           0 :   switch (VT.SimpleTy) {
     820           0 :   case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0, Op0IsKill);
     821           0 :   case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0, Op0IsKill);
     822           0 :   case MVT::v4f32: return fastEmit_ISD_FTRUNC_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     823           0 :   case MVT::v2f64: return fastEmit_ISD_FTRUNC_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     824           0 :   case MVT::v4f64: return fastEmit_ISD_FTRUNC_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
     825             :   default: return 0;
     826             :   }
     827             : }
     828             : 
     829             : // FastEmit functions for ISD::SCALAR_TO_VECTOR.
     830             : 
     831             : unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     832           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     833             :     return 0;
     834           0 :   if ((PPCSubTarget->hasP9Vector())) {
     835           0 :     return fastEmitInst_r(PPC::MTVSRWS, &PPC::VSRCRegClass, Op0, Op0IsKill);
     836             :   }
     837             :   return 0;
     838             : }
     839             : 
     840           0 : unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     841           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     842             :     return 0;
     843           0 :   if ((PPCSubTarget->hasP8Vector()) && (!PPCSubTarget->isLittleEndian())) {
     844           0 :     return fastEmitInst_r(PPC::XSCVDPSPN, &PPC::VSRCRegClass, Op0, Op0IsKill);
     845             :   }
     846             :   return 0;
     847             : }
     848             : 
     849           0 : unsigned fastEmit_ISD_SCALAR_TO_VECTOR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     850           0 :   switch (VT.SimpleTy) {
     851           0 :   case MVT::i32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(RetVT, Op0, Op0IsKill);
     852           0 :   case MVT::f32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(RetVT, Op0, Op0IsKill);
     853             :   default: return 0;
     854             :   }
     855             : }
     856             : 
     857             : // FastEmit functions for ISD::SIGN_EXTEND.
     858             : 
     859             : unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     860           4 :   if (RetVT.SimpleTy != MVT::i64)
     861             :     return 0;
     862           8 :   return fastEmitInst_r(PPC::EXTSW_32_64, &PPC::G8RCRegClass, Op0, Op0IsKill);
     863             : }
     864             : 
     865             : unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     866           5 :   switch (VT.SimpleTy) {
     867           4 :   case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0, Op0IsKill);
     868             :   default: return 0;
     869             :   }
     870             : }
     871             : 
     872             : // FastEmit functions for ISD::SINT_TO_FP.
     873             : 
     874           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     875           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     876             :     return 0;
     877           0 :   if ((PPCSubTarget->hasVSX())) {
     878           0 :     return fastEmitInst_r(PPC::XVCVSXWSP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     879             :   }
     880           0 :   if ((PPCSubTarget->hasAltivec())) {
     881           0 :     return fastEmitInst_r(PPC::VCFSX_0, &PPC::VRRCRegClass, Op0, Op0IsKill);
     882             :   }
     883             :   return 0;
     884             : }
     885             : 
     886             : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     887           2 :   if (RetVT.SimpleTy != MVT::v2f64)
     888             :     return 0;
     889           2 :   if ((PPCSubTarget->hasVSX())) {
     890           4 :     return fastEmitInst_r(PPC::XVCVSXDDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     891             :   }
     892             :   return 0;
     893             : }
     894             : 
     895          16 : unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     896          16 :   switch (VT.SimpleTy) {
     897           0 :   case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     898           2 :   case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     899             :   default: return 0;
     900             :   }
     901             : }
     902             : 
     903             : // FastEmit functions for ISD::TRUNCATE.
     904             : 
     905             : unsigned fastEmit_ISD_TRUNCATE_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     906           0 :   if (RetVT.SimpleTy != MVT::i1)
     907             :     return 0;
     908           0 :   return fastEmitInst_r(PPC::ANDIo_1_GT_BIT, &PPC::CRBITRCRegClass, Op0, Op0IsKill);
     909             : }
     910             : 
     911             : unsigned fastEmit_ISD_TRUNCATE_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     912           0 :   if (RetVT.SimpleTy != MVT::i1)
     913             :     return 0;
     914           0 :   return fastEmitInst_r(PPC::ANDIo_1_GT_BIT8, &PPC::CRBITRCRegClass, Op0, Op0IsKill);
     915             : }
     916             : 
     917           0 : unsigned fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     918           0 :   switch (VT.SimpleTy) {
     919           0 :   case MVT::i32: return fastEmit_ISD_TRUNCATE_MVT_i32_r(RetVT, Op0, Op0IsKill);
     920           0 :   case MVT::i64: return fastEmit_ISD_TRUNCATE_MVT_i64_r(RetVT, Op0, Op0IsKill);
     921             :   default: return 0;
     922             :   }
     923             : }
     924             : 
     925             : // FastEmit functions for ISD::UINT_TO_FP.
     926             : 
     927           0 : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     928           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     929             :     return 0;
     930           0 :   if ((PPCSubTarget->hasVSX())) {
     931           0 :     return fastEmitInst_r(PPC::XVCVUXWSP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     932             :   }
     933           0 :   if ((PPCSubTarget->hasAltivec())) {
     934           0 :     return fastEmitInst_r(PPC::VCFUX_0, &PPC::VRRCRegClass, Op0, Op0IsKill);
     935             :   }
     936             :   return 0;
     937             : }
     938             : 
     939             : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     940           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     941             :     return 0;
     942           0 :   if ((PPCSubTarget->hasVSX())) {
     943           0 :     return fastEmitInst_r(PPC::XVCVUXDDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     944             :   }
     945             :   return 0;
     946             : }
     947             : 
     948           0 : unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     949           0 :   switch (VT.SimpleTy) {
     950           0 :   case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     951           0 :   case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     952             :   default: return 0;
     953             :   }
     954             : }
     955             : 
     956             : // FastEmit functions for PPCISD::FCFID.
     957             : 
     958           0 : unsigned fastEmit_PPCISD_FCFID_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     959           0 :   if (RetVT.SimpleTy != MVT::f64)
     960             :     return 0;
     961           0 :   if ((PPCSubTarget->hasVSX())) {
     962           0 :     return fastEmitInst_r(PPC::XSCVSXDDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     963             :   }
     964           0 :   return fastEmitInst_r(PPC::FCFID, &PPC::F8RCRegClass, Op0, Op0IsKill);
     965             : }
     966             : 
     967             : unsigned fastEmit_PPCISD_FCFID_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     968           0 :   switch (VT.SimpleTy) {
     969           0 :   case MVT::f64: return fastEmit_PPCISD_FCFID_MVT_f64_r(RetVT, Op0, Op0IsKill);
     970             :   default: return 0;
     971             :   }
     972             : }
     973             : 
     974             : // FastEmit functions for PPCISD::FCFIDS.
     975             : 
     976           0 : unsigned fastEmit_PPCISD_FCFIDS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     977           0 :   if (RetVT.SimpleTy != MVT::f32)
     978             :     return 0;
     979           0 :   if ((PPCSubTarget->hasP8Vector())) {
     980           0 :     return fastEmitInst_r(PPC::XSCVSXDSP, &PPC::VSSRCRegClass, Op0, Op0IsKill);
     981             :   }
     982           0 :   return fastEmitInst_r(PPC::FCFIDS, &PPC::F4RCRegClass, Op0, Op0IsKill);
     983             : }
     984             : 
     985             : unsigned fastEmit_PPCISD_FCFIDS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     986           0 :   switch (VT.SimpleTy) {
     987           0 :   case MVT::f64: return fastEmit_PPCISD_FCFIDS_MVT_f64_r(RetVT, Op0, Op0IsKill);
     988             :   default: return 0;
     989             :   }
     990             : }
     991             : 
     992             : // FastEmit functions for PPCISD::FCFIDU.
     993             : 
     994           0 : unsigned fastEmit_PPCISD_FCFIDU_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     995           0 :   if (RetVT.SimpleTy != MVT::f64)
     996             :     return 0;
     997           0 :   if ((PPCSubTarget->hasVSX())) {
     998           0 :     return fastEmitInst_r(PPC::XSCVUXDDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     999             :   }
    1000           0 :   return fastEmitInst_r(PPC::FCFIDU, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1001             : }
    1002             : 
    1003             : unsigned fastEmit_PPCISD_FCFIDU_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1004           0 :   switch (VT.SimpleTy) {
    1005           0 :   case MVT::f64: return fastEmit_PPCISD_FCFIDU_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1006             :   default: return 0;
    1007             :   }
    1008             : }
    1009             : 
    1010             : // FastEmit functions for PPCISD::FCFIDUS.
    1011             : 
    1012           0 : unsigned fastEmit_PPCISD_FCFIDUS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1013           0 :   if (RetVT.SimpleTy != MVT::f32)
    1014             :     return 0;
    1015           0 :   if ((PPCSubTarget->hasP8Vector())) {
    1016           0 :     return fastEmitInst_r(PPC::XSCVUXDSP, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1017             :   }
    1018           0 :   return fastEmitInst_r(PPC::FCFIDUS, &PPC::F4RCRegClass, Op0, Op0IsKill);
    1019             : }
    1020             : 
    1021             : unsigned fastEmit_PPCISD_FCFIDUS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1022           0 :   switch (VT.SimpleTy) {
    1023           0 :   case MVT::f64: return fastEmit_PPCISD_FCFIDUS_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1024             :   default: return 0;
    1025             :   }
    1026             : }
    1027             : 
    1028             : // FastEmit functions for PPCISD::FCTIDUZ.
    1029             : 
    1030             : unsigned fastEmit_PPCISD_FCTIDUZ_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1031           0 :   if (RetVT.SimpleTy != MVT::f32)
    1032             :     return 0;
    1033           0 :   if ((PPCSubTarget->hasVSX())) {
    1034           0 :     return fastEmitInst_r(PPC::XSCVDPUXDSs, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1035             :   }
    1036             :   return 0;
    1037             : }
    1038             : 
    1039           0 : unsigned fastEmit_PPCISD_FCTIDUZ_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1040           0 :   if (RetVT.SimpleTy != MVT::f64)
    1041             :     return 0;
    1042           0 :   if ((PPCSubTarget->hasVSX())) {
    1043           0 :     return fastEmitInst_r(PPC::XSCVDPUXDS, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1044             :   }
    1045           0 :   return fastEmitInst_r(PPC::FCTIDUZ, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1046             : }
    1047             : 
    1048           0 : unsigned fastEmit_PPCISD_FCTIDUZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1049           0 :   switch (VT.SimpleTy) {
    1050           0 :   case MVT::f32: return fastEmit_PPCISD_FCTIDUZ_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1051           0 :   case MVT::f64: return fastEmit_PPCISD_FCTIDUZ_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1052             :   default: return 0;
    1053             :   }
    1054             : }
    1055             : 
    1056             : // FastEmit functions for PPCISD::FCTIDZ.
    1057             : 
    1058             : unsigned fastEmit_PPCISD_FCTIDZ_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1059           0 :   if (RetVT.SimpleTy != MVT::f32)
    1060             :     return 0;
    1061           0 :   if ((PPCSubTarget->hasVSX())) {
    1062           0 :     return fastEmitInst_r(PPC::XSCVDPSXDSs, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1063             :   }
    1064             :   return 0;
    1065             : }
    1066             : 
    1067           0 : unsigned fastEmit_PPCISD_FCTIDZ_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1068           0 :   if (RetVT.SimpleTy != MVT::f64)
    1069             :     return 0;
    1070           0 :   if ((PPCSubTarget->hasVSX())) {
    1071           0 :     return fastEmitInst_r(PPC::XSCVDPSXDS, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1072             :   }
    1073           0 :   return fastEmitInst_r(PPC::FCTIDZ, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1074             : }
    1075             : 
    1076           0 : unsigned fastEmit_PPCISD_FCTIDZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1077           0 :   switch (VT.SimpleTy) {
    1078           0 :   case MVT::f32: return fastEmit_PPCISD_FCTIDZ_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1079           0 :   case MVT::f64: return fastEmit_PPCISD_FCTIDZ_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1080             :   default: return 0;
    1081             :   }
    1082             : }
    1083             : 
    1084             : // FastEmit functions for PPCISD::FCTIWUZ.
    1085             : 
    1086             : unsigned fastEmit_PPCISD_FCTIWUZ_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1087           0 :   if (RetVT.SimpleTy != MVT::f32)
    1088             :     return 0;
    1089           0 :   if ((PPCSubTarget->hasVSX())) {
    1090           0 :     return fastEmitInst_r(PPC::XSCVDPUXWSs, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1091             :   }
    1092             :   return 0;
    1093             : }
    1094             : 
    1095           0 : unsigned fastEmit_PPCISD_FCTIWUZ_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1096           0 :   if (RetVT.SimpleTy != MVT::f64)
    1097             :     return 0;
    1098           0 :   if ((PPCSubTarget->hasVSX())) {
    1099           0 :     return fastEmitInst_r(PPC::XSCVDPUXWS, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1100             :   }
    1101           0 :   return fastEmitInst_r(PPC::FCTIWUZ, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1102             : }
    1103             : 
    1104           0 : unsigned fastEmit_PPCISD_FCTIWUZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1105           0 :   switch (VT.SimpleTy) {
    1106           0 :   case MVT::f32: return fastEmit_PPCISD_FCTIWUZ_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1107           0 :   case MVT::f64: return fastEmit_PPCISD_FCTIWUZ_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1108             :   default: return 0;
    1109             :   }
    1110             : }
    1111             : 
    1112             : // FastEmit functions for PPCISD::FCTIWZ.
    1113             : 
    1114             : unsigned fastEmit_PPCISD_FCTIWZ_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1115           0 :   if (RetVT.SimpleTy != MVT::f32)
    1116             :     return 0;
    1117           0 :   if ((PPCSubTarget->hasVSX())) {
    1118           0 :     return fastEmitInst_r(PPC::XSCVDPSXWSs, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1119             :   }
    1120             :   return 0;
    1121             : }
    1122             : 
    1123           0 : unsigned fastEmit_PPCISD_FCTIWZ_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1124           0 :   if (RetVT.SimpleTy != MVT::f64)
    1125             :     return 0;
    1126           0 :   if ((PPCSubTarget->hasVSX())) {
    1127           0 :     return fastEmitInst_r(PPC::XSCVDPSXWS, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1128             :   }
    1129           0 :   return fastEmitInst_r(PPC::FCTIWZ, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1130             : }
    1131             : 
    1132           0 : unsigned fastEmit_PPCISD_FCTIWZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1133           0 :   switch (VT.SimpleTy) {
    1134           0 :   case MVT::f32: return fastEmit_PPCISD_FCTIWZ_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1135           0 :   case MVT::f64: return fastEmit_PPCISD_FCTIWZ_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1136             :   default: return 0;
    1137             :   }
    1138             : }
    1139             : 
    1140             : // FastEmit functions for PPCISD::FRE.
    1141             : 
    1142           0 : unsigned fastEmit_PPCISD_FRE_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1143           0 :   if (RetVT.SimpleTy != MVT::f32)
    1144             :     return 0;
    1145           0 :   if ((PPCSubTarget->hasP8Vector())) {
    1146           0 :     return fastEmitInst_r(PPC::XSRESP, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1147             :   }
    1148           0 :   return fastEmitInst_r(PPC::FRES, &PPC::F4RCRegClass, Op0, Op0IsKill);
    1149             : }
    1150             : 
    1151           0 : unsigned fastEmit_PPCISD_FRE_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1152           0 :   if (RetVT.SimpleTy != MVT::f64)
    1153             :     return 0;
    1154           0 :   if ((PPCSubTarget->hasVSX())) {
    1155           0 :     return fastEmitInst_r(PPC::XSREDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1156             :   }
    1157           0 :   return fastEmitInst_r(PPC::FRE, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1158             : }
    1159             : 
    1160           0 : unsigned fastEmit_PPCISD_FRE_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1161           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1162             :     return 0;
    1163           0 :   if ((PPCSubTarget->hasVSX())) {
    1164           0 :     return fastEmitInst_r(PPC::XVRESP, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1165             :   }
    1166           0 :   if ((PPCSubTarget->hasAltivec())) {
    1167           0 :     return fastEmitInst_r(PPC::VREFP, &PPC::VRRCRegClass, Op0, Op0IsKill);
    1168             :   }
    1169           0 :   if ((PPCSubTarget->hasQPX())) {
    1170           0 :     return fastEmitInst_r(PPC::QVFRESs, &PPC::QSRCRegClass, Op0, Op0IsKill);
    1171             :   }
    1172             :   return 0;
    1173             : }
    1174             : 
    1175             : unsigned fastEmit_PPCISD_FRE_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1176           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1177             :     return 0;
    1178           0 :   if ((PPCSubTarget->hasVSX())) {
    1179           0 :     return fastEmitInst_r(PPC::XVREDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1180             :   }
    1181             :   return 0;
    1182             : }
    1183             : 
    1184             : unsigned fastEmit_PPCISD_FRE_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1185           0 :   if (RetVT.SimpleTy != MVT::v4f64)
    1186             :     return 0;
    1187           0 :   if ((PPCSubTarget->hasQPX())) {
    1188           0 :     return fastEmitInst_r(PPC::QVFRE, &PPC::QFRCRegClass, Op0, Op0IsKill);
    1189             :   }
    1190             :   return 0;
    1191             : }
    1192             : 
    1193           0 : unsigned fastEmit_PPCISD_FRE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1194           0 :   switch (VT.SimpleTy) {
    1195           0 :   case MVT::f32: return fastEmit_PPCISD_FRE_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1196           0 :   case MVT::f64: return fastEmit_PPCISD_FRE_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1197           0 :   case MVT::v4f32: return fastEmit_PPCISD_FRE_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
    1198           0 :   case MVT::v2f64: return fastEmit_PPCISD_FRE_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
    1199           0 :   case MVT::v4f64: return fastEmit_PPCISD_FRE_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
    1200             :   default: return 0;
    1201             :   }
    1202             : }
    1203             : 
    1204             : // FastEmit functions for PPCISD::FRSQRTE.
    1205             : 
    1206           0 : unsigned fastEmit_PPCISD_FRSQRTE_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1207           0 :   if (RetVT.SimpleTy != MVT::f32)
    1208             :     return 0;
    1209           0 :   if ((PPCSubTarget->hasP8Vector())) {
    1210           0 :     return fastEmitInst_r(PPC::XSRSQRTESP, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1211             :   }
    1212           0 :   return fastEmitInst_r(PPC::FRSQRTES, &PPC::F4RCRegClass, Op0, Op0IsKill);
    1213             : }
    1214             : 
    1215           0 : unsigned fastEmit_PPCISD_FRSQRTE_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1216           0 :   if (RetVT.SimpleTy != MVT::f64)
    1217             :     return 0;
    1218           0 :   if ((PPCSubTarget->hasVSX())) {
    1219           0 :     return fastEmitInst_r(PPC::XSRSQRTEDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1220             :   }
    1221           0 :   return fastEmitInst_r(PPC::FRSQRTE, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1222             : }
    1223             : 
    1224           0 : unsigned fastEmit_PPCISD_FRSQRTE_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1225           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1226             :     return 0;
    1227           0 :   if ((PPCSubTarget->hasVSX())) {
    1228           0 :     return fastEmitInst_r(PPC::XVRSQRTESP, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1229             :   }
    1230           0 :   if ((PPCSubTarget->hasAltivec())) {
    1231           0 :     return fastEmitInst_r(PPC::VRSQRTEFP, &PPC::VRRCRegClass, Op0, Op0IsKill);
    1232             :   }
    1233           0 :   if ((PPCSubTarget->hasQPX())) {
    1234           0 :     return fastEmitInst_r(PPC::QVFRSQRTESs, &PPC::QSRCRegClass, Op0, Op0IsKill);
    1235             :   }
    1236             :   return 0;
    1237             : }
    1238             : 
    1239             : unsigned fastEmit_PPCISD_FRSQRTE_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1240           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1241             :     return 0;
    1242           0 :   if ((PPCSubTarget->hasVSX())) {
    1243           0 :     return fastEmitInst_r(PPC::XVRSQRTEDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1244             :   }
    1245             :   return 0;
    1246             : }
    1247             : 
    1248             : unsigned fastEmit_PPCISD_FRSQRTE_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1249           0 :   if (RetVT.SimpleTy != MVT::v4f64)
    1250             :     return 0;
    1251           0 :   if ((PPCSubTarget->hasQPX())) {
    1252           0 :     return fastEmitInst_r(PPC::QVFRSQRTE, &PPC::QFRCRegClass, Op0, Op0IsKill);
    1253             :   }
    1254             :   return 0;
    1255             : }
    1256             : 
    1257           0 : unsigned fastEmit_PPCISD_FRSQRTE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1258           0 :   switch (VT.SimpleTy) {
    1259           0 :   case MVT::f32: return fastEmit_PPCISD_FRSQRTE_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1260           0 :   case MVT::f64: return fastEmit_PPCISD_FRSQRTE_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1261           0 :   case MVT::v4f32: return fastEmit_PPCISD_FRSQRTE_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
    1262           0 :   case MVT::v2f64: return fastEmit_PPCISD_FRSQRTE_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
    1263           0 :   case MVT::v4f64: return fastEmit_PPCISD_FRSQRTE_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
    1264             :   default: return 0;
    1265             :   }
    1266             : }
    1267             : 
    1268             : // FastEmit functions for PPCISD::MFVSR.
    1269             : 
    1270             : unsigned fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i32_r(unsigned Op0, bool Op0IsKill) {
    1271           0 :   if ((PPCSubTarget->hasDirectMove())) {
    1272           0 :     return fastEmitInst_r(PPC::MFVSRWZ, &PPC::GPRCRegClass, Op0, Op0IsKill);
    1273             :   }
    1274             :   return 0;
    1275             : }
    1276             : 
    1277             : unsigned fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i64_r(unsigned Op0, bool Op0IsKill) {
    1278           0 :   if ((PPCSubTarget->hasDirectMove())) {
    1279           0 :     return fastEmitInst_r(PPC::MFVSRD, &PPC::G8RCRegClass, Op0, Op0IsKill);
    1280             :   }
    1281             :   return 0;
    1282             : }
    1283             : 
    1284           0 : unsigned fastEmit_PPCISD_MFVSR_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1285           0 : switch (RetVT.SimpleTy) {
    1286           0 :   case MVT::i32: return fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i32_r(Op0, Op0IsKill);
    1287           0 :   case MVT::i64: return fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i64_r(Op0, Op0IsKill);
    1288             :   default: return 0;
    1289             : }
    1290             : }
    1291             : 
    1292             : unsigned fastEmit_PPCISD_MFVSR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1293           0 :   switch (VT.SimpleTy) {
    1294           0 :   case MVT::f64: return fastEmit_PPCISD_MFVSR_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1295             :   default: return 0;
    1296             :   }
    1297             : }
    1298             : 
    1299             : // FastEmit functions for PPCISD::MTCTR.
    1300             : 
    1301             : unsigned fastEmit_PPCISD_MTCTR_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1302           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    1303             :     return 0;
    1304           0 :   return fastEmitInst_r(PPC::MTCTR, &PPC::GPRCRegClass, Op0, Op0IsKill);
    1305             : }
    1306             : 
    1307             : unsigned fastEmit_PPCISD_MTCTR_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1308           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    1309             :     return 0;
    1310           0 :   return fastEmitInst_r(PPC::MTCTR8, &PPC::G8RCRegClass, Op0, Op0IsKill);
    1311             : }
    1312             : 
    1313           0 : unsigned fastEmit_PPCISD_MTCTR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1314           0 :   switch (VT.SimpleTy) {
    1315           0 :   case MVT::i32: return fastEmit_PPCISD_MTCTR_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1316           0 :   case MVT::i64: return fastEmit_PPCISD_MTCTR_MVT_i64_r(RetVT, Op0, Op0IsKill);
    1317             :   default: return 0;
    1318             :   }
    1319             : }
    1320             : 
    1321             : // FastEmit functions for PPCISD::MTVSRA.
    1322             : 
    1323             : unsigned fastEmit_PPCISD_MTVSRA_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1324           0 :   if (RetVT.SimpleTy != MVT::f64)
    1325             :     return 0;
    1326           0 :   if ((PPCSubTarget->hasDirectMove())) {
    1327           0 :     return fastEmitInst_r(PPC::MTVSRWA, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1328             :   }
    1329             :   return 0;
    1330             : }
    1331             : 
    1332             : unsigned fastEmit_PPCISD_MTVSRA_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1333           0 :   if (RetVT.SimpleTy != MVT::f64)
    1334             :     return 0;
    1335           0 :   if ((PPCSubTarget->hasDirectMove())) {
    1336           0 :     return fastEmitInst_r(PPC::MTVSRD, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1337             :   }
    1338             :   return 0;
    1339             : }
    1340             : 
    1341           0 : unsigned fastEmit_PPCISD_MTVSRA_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1342           0 :   switch (VT.SimpleTy) {
    1343           0 :   case MVT::i32: return fastEmit_PPCISD_MTVSRA_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1344           0 :   case MVT::i64: return fastEmit_PPCISD_MTVSRA_MVT_i64_r(RetVT, Op0, Op0IsKill);
    1345             :   default: return 0;
    1346             :   }
    1347             : }
    1348             : 
    1349             : // FastEmit functions for PPCISD::MTVSRZ.
    1350             : 
    1351             : unsigned fastEmit_PPCISD_MTVSRZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1352           0 :   if (RetVT.SimpleTy != MVT::f64)
    1353             :     return 0;
    1354           0 :   if ((PPCSubTarget->hasDirectMove())) {
    1355           0 :     return fastEmitInst_r(PPC::MTVSRWZ, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1356             :   }
    1357             :   return 0;
    1358             : }
    1359             : 
    1360           0 : unsigned fastEmit_PPCISD_MTVSRZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1361           0 :   switch (VT.SimpleTy) {
    1362           0 :   case MVT::i32: return fastEmit_PPCISD_MTVSRZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1363             :   default: return 0;
    1364             :   }
    1365             : }
    1366             : 
    1367             : // FastEmit functions for PPCISD::SExtVElems.
    1368             : 
    1369             : unsigned fastEmit_PPCISD_SExtVElems_MVT_v16i8_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
    1370           0 :   if ((PPCSubTarget->hasP9Altivec())) {
    1371           0 :     return fastEmitInst_r(PPC::VEXTSB2W, &PPC::VRRCRegClass, Op0, Op0IsKill);
    1372             :   }
    1373             :   return 0;
    1374             : }
    1375             : 
    1376             : unsigned fastEmit_PPCISD_SExtVElems_MVT_v16i8_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
    1377           0 :   if ((PPCSubTarget->hasP9Altivec())) {
    1378           0 :     return fastEmitInst_r(PPC::VEXTSB2D, &PPC::VRRCRegClass, Op0, Op0IsKill);
    1379             :   }
    1380             :   return 0;
    1381             : }
    1382             : 
    1383           0 : unsigned fastEmit_PPCISD_SExtVElems_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1384           0 : switch (RetVT.SimpleTy) {
    1385           0 :   case MVT::v4i32: return fastEmit_PPCISD_SExtVElems_MVT_v16i8_MVT_v4i32_r(Op0, Op0IsKill);
    1386           0 :   case MVT::v2i64: return fastEmit_PPCISD_SExtVElems_MVT_v16i8_MVT_v2i64_r(Op0, Op0IsKill);
    1387             :   default: return 0;
    1388             : }
    1389             : }
    1390             : 
    1391             : unsigned fastEmit_PPCISD_SExtVElems_MVT_v8i16_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
    1392           0 :   if ((PPCSubTarget->hasP9Altivec())) {
    1393           0 :     return fastEmitInst_r(PPC::VEXTSH2W, &PPC::VRRCRegClass, Op0, Op0IsKill);
    1394             :   }
    1395             :   return 0;
    1396             : }
    1397             : 
    1398             : unsigned fastEmit_PPCISD_SExtVElems_MVT_v8i16_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
    1399           0 :   if ((PPCSubTarget->hasP9Altivec())) {
    1400           0 :     return fastEmitInst_r(PPC::VEXTSH2D, &PPC::VRRCRegClass, Op0, Op0IsKill);
    1401             :   }
    1402             :   return 0;
    1403             : }
    1404             : 
    1405           0 : unsigned fastEmit_PPCISD_SExtVElems_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1406           0 : switch (RetVT.SimpleTy) {
    1407           0 :   case MVT::v4i32: return fastEmit_PPCISD_SExtVElems_MVT_v8i16_MVT_v4i32_r(Op0, Op0IsKill);
    1408           0 :   case MVT::v2i64: return fastEmit_PPCISD_SExtVElems_MVT_v8i16_MVT_v2i64_r(Op0, Op0IsKill);
    1409             :   default: return 0;
    1410             : }
    1411             : }
    1412             : 
    1413             : unsigned fastEmit_PPCISD_SExtVElems_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1414           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1415             :     return 0;
    1416           0 :   if ((PPCSubTarget->hasP9Altivec())) {
    1417           0 :     return fastEmitInst_r(PPC::VEXTSW2D, &PPC::VRRCRegClass, Op0, Op0IsKill);
    1418             :   }
    1419             :   return 0;
    1420             : }
    1421             : 
    1422           0 : unsigned fastEmit_PPCISD_SExtVElems_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1423           0 :   switch (VT.SimpleTy) {
    1424           0 :   case MVT::v16i8: return fastEmit_PPCISD_SExtVElems_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1425           0 :   case MVT::v8i16: return fastEmit_PPCISD_SExtVElems_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    1426           0 :   case MVT::v4i32: return fastEmit_PPCISD_SExtVElems_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    1427             :   default: return 0;
    1428             :   }
    1429             : }
    1430             : 
    1431             : // FastEmit functions for PPCISD::XXREVERSE.
    1432             : 
    1433             : unsigned fastEmit_PPCISD_XXREVERSE_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1434           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1435             :     return 0;
    1436           0 :   if ((PPCSubTarget->hasP9Vector())) {
    1437           0 :     return fastEmitInst_r(PPC::XXBRW, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1438             :   }
    1439             :   return 0;
    1440             : }
    1441             : 
    1442             : unsigned fastEmit_PPCISD_XXREVERSE_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1443           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1444             :     return 0;
    1445           0 :   if ((PPCSubTarget->hasP9Vector())) {
    1446           0 :     return fastEmitInst_r(PPC::XXBRD, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1447             :   }
    1448             :   return 0;
    1449             : }
    1450             : 
    1451           0 : unsigned fastEmit_PPCISD_XXREVERSE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1452           0 :   switch (VT.SimpleTy) {
    1453           0 :   case MVT::v4i32: return fastEmit_PPCISD_XXREVERSE_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    1454           0 :   case MVT::v2i64: return fastEmit_PPCISD_XXREVERSE_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
    1455             :   default: return 0;
    1456             :   }
    1457             : }
    1458             : 
    1459             : // Top-level FastEmit function.
    1460             : 
    1461          45 : unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill) override {
    1462          45 :   switch (Opcode) {
    1463           2 :   case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0, Op0IsKill);
    1464           0 :   case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill);
    1465           0 :   case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill);
    1466           0 :   case ISD::CTTZ: return fastEmit_ISD_CTTZ_r(VT, RetVT, Op0, Op0IsKill);
    1467           0 :   case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill);
    1468           0 :   case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0, Op0IsKill);
    1469           0 :   case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0, Op0IsKill);
    1470           0 :   case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0, Op0IsKill);
    1471           0 :   case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill);
    1472           0 :   case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill);
    1473          20 :   case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill);
    1474           0 :   case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill);
    1475           0 :   case ISD::FROUND: return fastEmit_ISD_FROUND_r(VT, RetVT, Op0, Op0IsKill);
    1476           0 :   case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill);
    1477           0 :   case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0, Op0IsKill);
    1478           0 :   case ISD::SCALAR_TO_VECTOR: return fastEmit_ISD_SCALAR_TO_VECTOR_r(VT, RetVT, Op0, Op0IsKill);
    1479           5 :   case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
    1480          16 :   case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill);
    1481           0 :   case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0, Op0IsKill);
    1482           0 :   case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill);
    1483           0 :   case PPCISD::FCFID: return fastEmit_PPCISD_FCFID_r(VT, RetVT, Op0, Op0IsKill);
    1484           0 :   case PPCISD::FCFIDS: return fastEmit_PPCISD_FCFIDS_r(VT, RetVT, Op0, Op0IsKill);
    1485           0 :   case PPCISD::FCFIDU: return fastEmit_PPCISD_FCFIDU_r(VT, RetVT, Op0, Op0IsKill);
    1486           0 :   case PPCISD::FCFIDUS: return fastEmit_PPCISD_FCFIDUS_r(VT, RetVT, Op0, Op0IsKill);
    1487           0 :   case PPCISD::FCTIDUZ: return fastEmit_PPCISD_FCTIDUZ_r(VT, RetVT, Op0, Op0IsKill);
    1488           0 :   case PPCISD::FCTIDZ: return fastEmit_PPCISD_FCTIDZ_r(VT, RetVT, Op0, Op0IsKill);
    1489           0 :   case PPCISD::FCTIWUZ: return fastEmit_PPCISD_FCTIWUZ_r(VT, RetVT, Op0, Op0IsKill);
    1490           0 :   case PPCISD::FCTIWZ: return fastEmit_PPCISD_FCTIWZ_r(VT, RetVT, Op0, Op0IsKill);
    1491           0 :   case PPCISD::FRE: return fastEmit_PPCISD_FRE_r(VT, RetVT, Op0, Op0IsKill);
    1492           0 :   case PPCISD::FRSQRTE: return fastEmit_PPCISD_FRSQRTE_r(VT, RetVT, Op0, Op0IsKill);
    1493           0 :   case PPCISD::MFVSR: return fastEmit_PPCISD_MFVSR_r(VT, RetVT, Op0, Op0IsKill);
    1494           0 :   case PPCISD::MTCTR: return fastEmit_PPCISD_MTCTR_r(VT, RetVT, Op0, Op0IsKill);
    1495           0 :   case PPCISD::MTVSRA: return fastEmit_PPCISD_MTVSRA_r(VT, RetVT, Op0, Op0IsKill);
    1496           0 :   case PPCISD::MTVSRZ: return fastEmit_PPCISD_MTVSRZ_r(VT, RetVT, Op0, Op0IsKill);
    1497           0 :   case PPCISD::SExtVElems: return fastEmit_PPCISD_SExtVElems_r(VT, RetVT, Op0, Op0IsKill);
    1498           0 :   case PPCISD::XXREVERSE: return fastEmit_PPCISD_XXREVERSE_r(VT, RetVT, Op0, Op0IsKill);
    1499             :   default: return 0;
    1500             :   }
    1501             : }
    1502             : 
    1503             : // FastEmit functions for ISD::ADD.
    1504             : 
    1505             : unsigned fastEmit_ISD_ADD_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1506           0 :   if (RetVT.SimpleTy != MVT::i1)
    1507             :     return 0;
    1508           0 :   return fastEmitInst_rr(PPC::CRXOR, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1509             : }
    1510             : 
    1511             : unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1512           0 :   if (RetVT.SimpleTy != MVT::i32)
    1513             :     return 0;
    1514           0 :   return fastEmitInst_rr(PPC::ADD4, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1515             : }
    1516             : 
    1517             : unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1518           0 :   if (RetVT.SimpleTy != MVT::i64)
    1519             :     return 0;
    1520           0 :   return fastEmitInst_rr(PPC::ADD8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1521             : }
    1522             : 
    1523             : unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1524           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1525             :     return 0;
    1526           0 :   if ((PPCSubTarget->hasAltivec())) {
    1527           0 :     return fastEmitInst_rr(PPC::VADDUBM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1528             :   }
    1529             :   return 0;
    1530             : }
    1531             : 
    1532             : unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1533           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1534             :     return 0;
    1535           0 :   if ((PPCSubTarget->hasAltivec())) {
    1536           0 :     return fastEmitInst_rr(PPC::VADDUHM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1537             :   }
    1538             :   return 0;
    1539             : }
    1540             : 
    1541             : unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1542           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1543             :     return 0;
    1544           0 :   if ((PPCSubTarget->hasAltivec())) {
    1545           0 :     return fastEmitInst_rr(PPC::VADDUWM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1546             :   }
    1547             :   return 0;
    1548             : }
    1549             : 
    1550             : unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1551           2 :   if (RetVT.SimpleTy != MVT::v2i64)
    1552             :     return 0;
    1553           2 :   if ((PPCSubTarget->hasP8Altivec())) {
    1554           0 :     return fastEmitInst_rr(PPC::VADDUDM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1555             :   }
    1556             :   return 0;
    1557             : }
    1558             : 
    1559             : unsigned fastEmit_ISD_ADD_MVT_v1i128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1560           0 :   if (RetVT.SimpleTy != MVT::v1i128)
    1561             :     return 0;
    1562           0 :   if ((PPCSubTarget->hasP8Altivec())) {
    1563           0 :     return fastEmitInst_rr(PPC::VADDUQM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1564             :   }
    1565             :   return 0;
    1566             : }
    1567             : 
    1568           2 : unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1569           2 :   switch (VT.SimpleTy) {
    1570           0 :   case MVT::i1: return fastEmit_ISD_ADD_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1571           0 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1572           0 :   case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1573           0 :   case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1574           0 :   case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1575           0 :   case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1576           2 :   case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1577           0 :   case MVT::v1i128: return fastEmit_ISD_ADD_MVT_v1i128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1578             :   default: return 0;
    1579             :   }
    1580             : }
    1581             : 
    1582             : // FastEmit functions for ISD::ADDC.
    1583             : 
    1584             : unsigned fastEmit_ISD_ADDC_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1585           0 :   if (RetVT.SimpleTy != MVT::i32)
    1586             :     return 0;
    1587           0 :   return fastEmitInst_rr(PPC::ADDC, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1588             : }
    1589             : 
    1590             : unsigned fastEmit_ISD_ADDC_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1591           0 :   if (RetVT.SimpleTy != MVT::i64)
    1592             :     return 0;
    1593           0 :   return fastEmitInst_rr(PPC::ADDC8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1594             : }
    1595             : 
    1596           0 : unsigned fastEmit_ISD_ADDC_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1597           0 :   switch (VT.SimpleTy) {
    1598           0 :   case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1599           0 :   case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1600             :   default: return 0;
    1601             :   }
    1602             : }
    1603             : 
    1604             : // FastEmit functions for ISD::ADDE.
    1605             : 
    1606             : unsigned fastEmit_ISD_ADDE_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1607           0 :   if (RetVT.SimpleTy != MVT::i32)
    1608             :     return 0;
    1609           0 :   return fastEmitInst_rr(PPC::ADDE, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1610             : }
    1611             : 
    1612             : unsigned fastEmit_ISD_ADDE_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1613           0 :   if (RetVT.SimpleTy != MVT::i64)
    1614             :     return 0;
    1615           0 :   return fastEmitInst_rr(PPC::ADDE8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1616             : }
    1617             : 
    1618           0 : unsigned fastEmit_ISD_ADDE_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1619           0 :   switch (VT.SimpleTy) {
    1620           0 :   case MVT::i32: return fastEmit_ISD_ADDE_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1621           0 :   case MVT::i64: return fastEmit_ISD_ADDE_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1622             :   default: return 0;
    1623             :   }
    1624             : }
    1625             : 
    1626             : // FastEmit functions for ISD::AND.
    1627             : 
    1628             : unsigned fastEmit_ISD_AND_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1629           0 :   if (RetVT.SimpleTy != MVT::i1)
    1630             :     return 0;
    1631           0 :   return fastEmitInst_rr(PPC::CRAND, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1632             : }
    1633             : 
    1634             : unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1635           0 :   if (RetVT.SimpleTy != MVT::i32)
    1636             :     return 0;
    1637           0 :   return fastEmitInst_rr(PPC::AND, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1638             : }
    1639             : 
    1640             : unsigned fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1641           1 :   if (RetVT.SimpleTy != MVT::i64)
    1642             :     return 0;
    1643           2 :   return fastEmitInst_rr(PPC::AND8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1644             : }
    1645             : 
    1646           4 : unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1647           4 :   if (RetVT.SimpleTy != MVT::v4i32)
    1648             :     return 0;
    1649           4 :   if ((PPCSubTarget->hasVSX())) {
    1650           8 :     return fastEmitInst_rr(PPC::XXLAND, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1651             :   }
    1652           0 :   if ((PPCSubTarget->hasAltivec())) {
    1653           0 :     return fastEmitInst_rr(PPC::VAND, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1654             :   }
    1655             :   return 0;
    1656             : }
    1657             : 
    1658          15 : unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1659          15 :   switch (VT.SimpleTy) {
    1660           0 :   case MVT::i1: return fastEmit_ISD_AND_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1661           0 :   case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1662           1 :   case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1663           4 :   case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1664             :   default: return 0;
    1665             :   }
    1666             : }
    1667             : 
    1668             : // FastEmit functions for ISD::BUILD_VECTOR.
    1669             : 
    1670           0 : unsigned fastEmit_ISD_BUILD_VECTOR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1671           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1672             :     return 0;
    1673           0 :   if ((PPCSubTarget->hasDirectMove()) && (!PPCSubTarget->isLittleEndian()) && (PPCSubTarget->isISA3_0())) {
    1674           0 :     return fastEmitInst_rr(PPC::MTVSRDD, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1675             :   }
    1676             :   return 0;
    1677             : }
    1678             : 
    1679             : unsigned fastEmit_ISD_BUILD_VECTOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1680           0 :   switch (VT.SimpleTy) {
    1681           0 :   case MVT::i64: return fastEmit_ISD_BUILD_VECTOR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1682             :   default: return 0;
    1683             :   }
    1684             : }
    1685             : 
    1686             : // FastEmit functions for ISD::FADD.
    1687             : 
    1688           2 : unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1689           2 :   if (RetVT.SimpleTy != MVT::f32)
    1690             :     return 0;
    1691           2 :   if ((PPCSubTarget->hasP8Vector())) {
    1692           0 :     return fastEmitInst_rr(PPC::XSADDSP, &PPC::VSSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1693             :   }
    1694           4 :   return fastEmitInst_rr(PPC::FADDS, &PPC::F4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1695             : }
    1696             : 
    1697          10 : unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1698          10 :   if (RetVT.SimpleTy != MVT::f64)
    1699             :     return 0;
    1700          10 :   if ((PPCSubTarget->hasVSX())) {
    1701          16 :     return fastEmitInst_rr(PPC::XSADDDP, &PPC::VSFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1702             :   }
    1703           4 :   return fastEmitInst_rr(PPC::FADD, &PPC::F8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1704             : }
    1705             : 
    1706           0 : unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1707           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1708             :     return 0;
    1709           0 :   if ((PPCSubTarget->hasVSX())) {
    1710           0 :     return fastEmitInst_rr(PPC::XVADDSP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1711             :   }
    1712           0 :   if ((PPCSubTarget->hasQPX())) {
    1713           0 :     return fastEmitInst_rr(PPC::QVFADDSs, &PPC::QSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1714             :   }
    1715           0 :   if ((PPCSubTarget->hasAltivec())) {
    1716           0 :     return fastEmitInst_rr(PPC::VADDFP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1717             :   }
    1718             :   return 0;
    1719             : }
    1720             : 
    1721             : unsigned fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1722           2 :   if (RetVT.SimpleTy != MVT::v2f64)
    1723             :     return 0;
    1724           2 :   if ((PPCSubTarget->hasVSX())) {
    1725           4 :     return fastEmitInst_rr(PPC::XVADDDP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1726             :   }
    1727             :   return 0;
    1728             : }
    1729             : 
    1730             : unsigned fastEmit_ISD_FADD_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1731           0 :   if (RetVT.SimpleTy != MVT::v4f64)
    1732             :     return 0;
    1733           0 :   if ((PPCSubTarget->hasQPX())) {
    1734           0 :     return fastEmitInst_rr(PPC::QVFADD, &PPC::QFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1735             :   }
    1736             :   return 0;
    1737             : }
    1738             : 
    1739          14 : unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1740          14 :   switch (VT.SimpleTy) {
    1741           2 :   case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1742          10 :   case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1743           0 :   case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1744           2 :   case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1745           0 :   case MVT::v4f64: return fastEmit_ISD_FADD_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1746             :   default: return 0;
    1747             :   }
    1748             : }
    1749             : 
    1750             : // FastEmit functions for ISD::FDIV.
    1751             : 
    1752           0 : unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1753           0 :   if (RetVT.SimpleTy != MVT::f32)
    1754             :     return 0;
    1755           0 :   if ((PPCSubTarget->hasP8Vector())) {
    1756           0 :     return fastEmitInst_rr(PPC::XSDIVSP, &PPC::VSSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1757             :   }
    1758           0 :   return fastEmitInst_rr(PPC::FDIVS, &PPC::F4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1759             : }
    1760             : 
    1761           2 : unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1762           2 :   if (RetVT.SimpleTy != MVT::f64)
    1763             :     return 0;
    1764           2 :   if ((PPCSubTarget->hasVSX())) {
    1765           4 :     return fastEmitInst_rr(PPC::XSDIVDP, &PPC::VSFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1766             :   }
    1767           0 :   return fastEmitInst_rr(PPC::FDIV, &PPC::F8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1768             : }
    1769             : 
    1770             : unsigned fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1771           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1772             :     return 0;
    1773           0 :   if ((PPCSubTarget->hasVSX())) {
    1774           0 :     return fastEmitInst_rr(PPC::XVDIVSP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1775             :   }
    1776             :   return 0;
    1777             : }
    1778             : 
    1779             : unsigned fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1780           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1781             :     return 0;
    1782           0 :   if ((PPCSubTarget->hasVSX())) {
    1783           0 :     return fastEmitInst_rr(PPC::XVDIVDP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1784             :   }
    1785             :   return 0;
    1786             : }
    1787             : 
    1788           2 : unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1789           2 :   switch (VT.SimpleTy) {
    1790           0 :   case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1791           2 :   case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1792           0 :   case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1793           0 :   case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1794             :   default: return 0;
    1795             :   }
    1796             : }
    1797             : 
    1798             : // FastEmit functions for ISD::FMUL.
    1799             : 
    1800           0 : unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1801           0 :   if (RetVT.SimpleTy != MVT::f32)
    1802             :     return 0;
    1803           0 :   if ((PPCSubTarget->hasP8Vector())) {
    1804           0 :     return fastEmitInst_rr(PPC::XSMULSP, &PPC::VSSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1805             :   }
    1806           0 :   return fastEmitInst_rr(PPC::FMULS, &PPC::F4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1807             : }
    1808             : 
    1809           2 : unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1810           2 :   if (RetVT.SimpleTy != MVT::f64)
    1811             :     return 0;
    1812           2 :   if ((PPCSubTarget->hasVSX())) {
    1813           4 :     return fastEmitInst_rr(PPC::XSMULDP, &PPC::VSFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1814             :   }
    1815           0 :   return fastEmitInst_rr(PPC::FMUL, &PPC::F8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1816             : }
    1817             : 
    1818           0 : unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1819           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1820             :     return 0;
    1821           0 :   if ((PPCSubTarget->hasVSX())) {
    1822           0 :     return fastEmitInst_rr(PPC::XVMULSP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1823             :   }
    1824           0 :   if ((PPCSubTarget->hasQPX())) {
    1825           0 :     return fastEmitInst_rr(PPC::QVFMULSs, &PPC::QSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1826             :   }
    1827             :   return 0;
    1828             : }
    1829             : 
    1830             : unsigned fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1831           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1832             :     return 0;
    1833           0 :   if ((PPCSubTarget->hasVSX())) {
    1834           0 :     return fastEmitInst_rr(PPC::XVMULDP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1835             :   }
    1836             :   return 0;
    1837             : }
    1838             : 
    1839             : unsigned fastEmit_ISD_FMUL_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1840           0 :   if (RetVT.SimpleTy != MVT::v4f64)
    1841             :     return 0;
    1842           0 :   if ((PPCSubTarget->hasQPX())) {
    1843           0 :     return fastEmitInst_rr(PPC::QVFMUL, &PPC::QFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1844             :   }
    1845             :   return 0;
    1846             : }
    1847             : 
    1848           2 : unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1849           2 :   switch (VT.SimpleTy) {
    1850           0 :   case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1851           2 :   case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1852           0 :   case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1853           0 :   case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1854           0 :   case MVT::v4f64: return fastEmit_ISD_FMUL_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1855             :   default: return 0;
    1856             :   }
    1857             : }
    1858             : 
    1859             : // FastEmit functions for ISD::FSUB.
    1860             : 
    1861           0 : unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1862           0 :   if (RetVT.SimpleTy != MVT::f32)
    1863             :     return 0;
    1864           0 :   if ((PPCSubTarget->hasP8Vector())) {
    1865           0 :     return fastEmitInst_rr(PPC::XSSUBSP, &PPC::VSSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1866             :   }
    1867           0 :   return fastEmitInst_rr(PPC::FSUBS, &PPC::F4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1868             : }
    1869             : 
    1870           0 : unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1871           0 :   if (RetVT.SimpleTy != MVT::f64)
    1872             :     return 0;
    1873           0 :   if ((PPCSubTarget->hasVSX())) {
    1874           0 :     return fastEmitInst_rr(PPC::XSSUBDP, &PPC::VSFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1875             :   }
    1876           0 :   return fastEmitInst_rr(PPC::FSUB, &PPC::F8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1877             : }
    1878             : 
    1879           0 : unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1880           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1881             :     return 0;
    1882           0 :   if ((PPCSubTarget->hasVSX())) {
    1883           0 :     return fastEmitInst_rr(PPC::XVSUBSP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1884             :   }
    1885           0 :   if ((PPCSubTarget->hasQPX())) {
    1886           0 :     return fastEmitInst_rr(PPC::QVFSUBSs, &PPC::QSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1887             :   }
    1888           0 :   if ((PPCSubTarget->hasAltivec())) {
    1889           0 :     return fastEmitInst_rr(PPC::VSUBFP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1890             :   }
    1891             :   return 0;
    1892             : }
    1893             : 
    1894             : unsigned fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1895           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1896             :     return 0;
    1897           0 :   if ((PPCSubTarget->hasVSX())) {
    1898           0 :     return fastEmitInst_rr(PPC::XVSUBDP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1899             :   }
    1900             :   return 0;
    1901             : }
    1902             : 
    1903             : unsigned fastEmit_ISD_FSUB_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1904           0 :   if (RetVT.SimpleTy != MVT::v4f64)
    1905             :     return 0;
    1906           0 :   if ((PPCSubTarget->hasQPX())) {
    1907           0 :     return fastEmitInst_rr(PPC::QVFSUB, &PPC::QFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1908             :   }
    1909             :   return 0;
    1910             : }
    1911             : 
    1912           0 : unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1913           0 :   switch (VT.SimpleTy) {
    1914           0 :   case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1915           0 :   case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1916           0 :   case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1917           0 :   case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1918           0 :   case MVT::v4f64: return fastEmit_ISD_FSUB_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1919             :   default: return 0;
    1920             :   }
    1921             : }
    1922             : 
    1923             : // FastEmit functions for ISD::MUL.
    1924             : 
    1925             : unsigned fastEmit_ISD_MUL_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1926           0 :   if (RetVT.SimpleTy != MVT::i1)
    1927             :     return 0;
    1928           0 :   return fastEmitInst_rr(PPC::CRAND, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1929             : }
    1930             : 
    1931             : unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1932           0 :   if (RetVT.SimpleTy != MVT::i32)
    1933             :     return 0;
    1934           0 :   return fastEmitInst_rr(PPC::MULLW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1935             : }
    1936             : 
    1937             : unsigned fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1938           0 :   if (RetVT.SimpleTy != MVT::i64)
    1939             :     return 0;
    1940           0 :   return fastEmitInst_rr(PPC::MULLD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1941             : }
    1942             : 
    1943             : unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1944           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1945             :     return 0;
    1946           0 :   if ((PPCSubTarget->hasP8Altivec())) {
    1947           0 :     return fastEmitInst_rr(PPC::VMULUWM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1948             :   }
    1949             :   return 0;
    1950             : }
    1951             : 
    1952           0 : unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1953           0 :   switch (VT.SimpleTy) {
    1954           0 :   case MVT::i1: return fastEmit_ISD_MUL_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1955           0 :   case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1956           0 :   case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1957           0 :   case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1958             :   default: return 0;
    1959             :   }
    1960             : }
    1961             : 
    1962             : // FastEmit functions for ISD::MULHS.
    1963             : 
    1964             : unsigned fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1965           0 :   if (RetVT.SimpleTy != MVT::i32)
    1966             :     return 0;
    1967           0 :   return fastEmitInst_rr(PPC::MULHW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1968             : }
    1969             : 
    1970             : unsigned fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1971           0 :   if (RetVT.SimpleTy != MVT::i64)
    1972             :     return 0;
    1973           0 :   return fastEmitInst_rr(PPC::MULHD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1974             : }
    1975             : 
    1976           0 : unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1977           0 :   switch (VT.SimpleTy) {
    1978           0 :   case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1979           0 :   case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1980             :   default: return 0;
    1981             :   }
    1982             : }
    1983             : 
    1984             : // FastEmit functions for ISD::MULHU.
    1985             : 
    1986             : unsigned fastEmit_ISD_MULHU_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1987           0 :   if (RetVT.SimpleTy != MVT::i32)
    1988             :     return 0;
    1989           0 :   return fastEmitInst_rr(PPC::MULHWU, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1990             : }
    1991             : 
    1992             : unsigned fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1993           0 :   if (RetVT.SimpleTy != MVT::i64)
    1994             :     return 0;
    1995           0 :   return fastEmitInst_rr(PPC::MULHDU, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1996             : }
    1997             : 
    1998           0 : unsigned fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1999           0 :   switch (VT.SimpleTy) {
    2000           0 :   case MVT::i32: return fastEmit_ISD_MULHU_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2001           0 :   case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2002             :   default: return 0;
    2003             :   }
    2004             : }
    2005             : 
    2006             : // FastEmit functions for ISD::OR.
    2007             : 
    2008             : unsigned fastEmit_ISD_OR_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2009           0 :   if (RetVT.SimpleTy != MVT::i1)
    2010             :     return 0;
    2011           0 :   return fastEmitInst_rr(PPC::CROR, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2012             : }
    2013             : 
    2014             : unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2015           0 :   if (RetVT.SimpleTy != MVT::i32)
    2016             :     return 0;
    2017           0 :   return fastEmitInst_rr(PPC::OR, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2018             : }
    2019             : 
    2020             : unsigned fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2021           0 :   if (RetVT.SimpleTy != MVT::i64)
    2022             :     return 0;
    2023           0 :   return fastEmitInst_rr(PPC::OR8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2024             : }
    2025             : 
    2026           2 : unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2027           2 :   if (RetVT.SimpleTy != MVT::v4i32)
    2028             :     return 0;
    2029           2 :   if ((PPCSubTarget->hasVSX())) {
    2030           4 :     return fastEmitInst_rr(PPC::XXLOR, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2031             :   }
    2032           0 :   if ((PPCSubTarget->hasAltivec())) {
    2033           0 :     return fastEmitInst_rr(PPC::VOR, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2034             :   }
    2035             :   return 0;
    2036             : }
    2037             : 
    2038           6 : unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2039           6 :   switch (VT.SimpleTy) {
    2040           0 :   case MVT::i1: return fastEmit_ISD_OR_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2041           0 :   case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2042           0 :   case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2043           2 :   case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2044             :   default: return 0;
    2045             :   }
    2046             : }
    2047             : 
    2048             : // FastEmit functions for ISD::SDIV.
    2049             : 
    2050             : unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2051           0 :   if (RetVT.SimpleTy != MVT::i32)
    2052             :     return 0;
    2053           0 :   return fastEmitInst_rr(PPC::DIVW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2054             : }
    2055             : 
    2056             : unsigned fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2057           0 :   if (RetVT.SimpleTy != MVT::i64)
    2058             :     return 0;
    2059           0 :   return fastEmitInst_rr(PPC::DIVD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2060             : }
    2061             : 
    2062           0 : unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2063           0 :   switch (VT.SimpleTy) {
    2064           0 :   case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2065           0 :   case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2066             :   default: return 0;
    2067             :   }
    2068             : }
    2069             : 
    2070             : // FastEmit functions for ISD::SHL.
    2071             : 
    2072             : unsigned fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2073           2 :   if (RetVT.SimpleTy != MVT::i32)
    2074             :     return 0;
    2075           4 :   return fastEmitInst_rr(PPC::SLW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2076             : }
    2077             : 
    2078             : unsigned fastEmit_ISD_SHL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2079           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2080             :     return 0;
    2081           0 :   if ((PPCSubTarget->hasAltivec())) {
    2082           0 :     return fastEmitInst_rr(PPC::VSLB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2083             :   }
    2084             :   return 0;
    2085             : }
    2086             : 
    2087             : unsigned fastEmit_ISD_SHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2088           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2089             :     return 0;
    2090           0 :   if ((PPCSubTarget->hasAltivec())) {
    2091           0 :     return fastEmitInst_rr(PPC::VSLH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2092             :   }
    2093             :   return 0;
    2094             : }
    2095             : 
    2096             : unsigned fastEmit_ISD_SHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2097           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2098             :     return 0;
    2099           0 :   if ((PPCSubTarget->hasAltivec())) {
    2100           0 :     return fastEmitInst_rr(PPC::VSLW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2101             :   }
    2102             :   return 0;
    2103             : }
    2104             : 
    2105             : unsigned fastEmit_ISD_SHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2106           2 :   if (RetVT.SimpleTy != MVT::v2i64)
    2107             :     return 0;
    2108           2 :   if ((PPCSubTarget->hasP8Altivec())) {
    2109           0 :     return fastEmitInst_rr(PPC::VSLD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2110             :   }
    2111             :   return 0;
    2112             : }
    2113             : 
    2114           5 : unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2115           5 :   switch (VT.SimpleTy) {
    2116           2 :   case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2117           0 :   case MVT::v16i8: return fastEmit_ISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2118           0 :   case MVT::v8i16: return fastEmit_ISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2119           0 :   case MVT::v4i32: return fastEmit_ISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2120           2 :   case MVT::v2i64: return fastEmit_ISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2121             :   default: return 0;
    2122             :   }
    2123             : }
    2124             : 
    2125             : // FastEmit functions for ISD::SRA.
    2126             : 
    2127             : unsigned fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2128           1 :   if (RetVT.SimpleTy != MVT::i32)
    2129             :     return 0;
    2130           2 :   return fastEmitInst_rr(PPC::SRAW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2131             : }
    2132             : 
    2133             : unsigned fastEmit_ISD_SRA_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2134           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2135             :     return 0;
    2136           0 :   if ((PPCSubTarget->hasAltivec())) {
    2137           0 :     return fastEmitInst_rr(PPC::VSRAB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2138             :   }
    2139             :   return 0;
    2140             : }
    2141             : 
    2142             : unsigned fastEmit_ISD_SRA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2143           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2144             :     return 0;
    2145           0 :   if ((PPCSubTarget->hasAltivec())) {
    2146           0 :     return fastEmitInst_rr(PPC::VSRAH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2147             :   }
    2148             :   return 0;
    2149             : }
    2150             : 
    2151             : unsigned fastEmit_ISD_SRA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2152           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2153             :     return 0;
    2154           0 :   if ((PPCSubTarget->hasAltivec())) {
    2155           0 :     return fastEmitInst_rr(PPC::VSRAW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2156             :   }
    2157             :   return 0;
    2158             : }
    2159             : 
    2160             : unsigned fastEmit_ISD_SRA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2161           2 :   if (RetVT.SimpleTy != MVT::v2i64)
    2162             :     return 0;
    2163           2 :   if ((PPCSubTarget->hasP8Altivec())) {
    2164           0 :     return fastEmitInst_rr(PPC::VSRAD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2165             :   }
    2166             :   return 0;
    2167             : }
    2168             : 
    2169           3 : unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2170           3 :   switch (VT.SimpleTy) {
    2171           1 :   case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2172           0 :   case MVT::v16i8: return fastEmit_ISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2173           0 :   case MVT::v8i16: return fastEmit_ISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2174           0 :   case MVT::v4i32: return fastEmit_ISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2175           2 :   case MVT::v2i64: return fastEmit_ISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2176             :   default: return 0;
    2177             :   }
    2178             : }
    2179             : 
    2180             : // FastEmit functions for ISD::SREM.
    2181             : 
    2182             : unsigned fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2183           0 :   if (RetVT.SimpleTy != MVT::i32)
    2184             :     return 0;
    2185           0 :   if ((PPCSubTarget->isISA3_0())) {
    2186           0 :     return fastEmitInst_rr(PPC::MODSW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2187             :   }
    2188             :   return 0;
    2189             : }
    2190             : 
    2191             : unsigned fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2192           0 :   if (RetVT.SimpleTy != MVT::i64)
    2193             :     return 0;
    2194           0 :   if ((PPCSubTarget->isISA3_0())) {
    2195           0 :     return fastEmitInst_rr(PPC::MODSD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2196             :   }
    2197             :   return 0;
    2198             : }
    2199             : 
    2200           0 : unsigned fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2201           0 :   switch (VT.SimpleTy) {
    2202           0 :   case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2203           0 :   case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2204             :   default: return 0;
    2205             :   }
    2206             : }
    2207             : 
    2208             : // FastEmit functions for ISD::SRL.
    2209             : 
    2210             : unsigned fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2211           2 :   if (RetVT.SimpleTy != MVT::i32)
    2212             :     return 0;
    2213           4 :   return fastEmitInst_rr(PPC::SRW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2214             : }
    2215             : 
    2216             : unsigned fastEmit_ISD_SRL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2217           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2218             :     return 0;
    2219           0 :   if ((PPCSubTarget->hasAltivec())) {
    2220           0 :     return fastEmitInst_rr(PPC::VSRB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2221             :   }
    2222             :   return 0;
    2223             : }
    2224             : 
    2225             : unsigned fastEmit_ISD_SRL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2226           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2227             :     return 0;
    2228           0 :   if ((PPCSubTarget->hasAltivec())) {
    2229           0 :     return fastEmitInst_rr(PPC::VSRH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2230             :   }
    2231             :   return 0;
    2232             : }
    2233             : 
    2234             : unsigned fastEmit_ISD_SRL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2235           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2236             :     return 0;
    2237           0 :   if ((PPCSubTarget->hasAltivec())) {
    2238           0 :     return fastEmitInst_rr(PPC::VSRW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2239             :   }
    2240             :   return 0;
    2241             : }
    2242             : 
    2243             : unsigned fastEmit_ISD_SRL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2244           2 :   if (RetVT.SimpleTy != MVT::v2i64)
    2245             :     return 0;
    2246           2 :   if ((PPCSubTarget->hasP8Altivec())) {
    2247           0 :     return fastEmitInst_rr(PPC::VSRD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2248             :   }
    2249             :   return 0;
    2250             : }
    2251             : 
    2252           4 : unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2253           4 :   switch (VT.SimpleTy) {
    2254           2 :   case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2255           0 :   case MVT::v16i8: return fastEmit_ISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2256           0 :   case MVT::v8i16: return fastEmit_ISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2257           0 :   case MVT::v4i32: return fastEmit_ISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2258           2 :   case MVT::v2i64: return fastEmit_ISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2259             :   default: return 0;
    2260             :   }
    2261             : }
    2262             : 
    2263             : // FastEmit functions for ISD::SUB.
    2264             : 
    2265             : unsigned fastEmit_ISD_SUB_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2266           0 :   if (RetVT.SimpleTy != MVT::i1)
    2267             :     return 0;
    2268           0 :   return fastEmitInst_rr(PPC::CRXOR, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2269             : }
    2270             : 
    2271             : unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2272           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2273             :     return 0;
    2274           0 :   if ((PPCSubTarget->hasAltivec())) {
    2275           0 :     return fastEmitInst_rr(PPC::VSUBUBM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2276             :   }
    2277             :   return 0;
    2278             : }
    2279             : 
    2280             : unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2281           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2282             :     return 0;
    2283           0 :   if ((PPCSubTarget->hasAltivec())) {
    2284           0 :     return fastEmitInst_rr(PPC::VSUBUHM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2285             :   }
    2286             :   return 0;
    2287             : }
    2288             : 
    2289             : unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2290           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2291             :     return 0;
    2292           0 :   if ((PPCSubTarget->hasAltivec())) {
    2293           0 :     return fastEmitInst_rr(PPC::VSUBUWM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2294             :   }
    2295             :   return 0;
    2296             : }
    2297             : 
    2298             : unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2299           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2300             :     return 0;
    2301           0 :   if ((PPCSubTarget->hasP8Altivec())) {
    2302           0 :     return fastEmitInst_rr(PPC::VSUBUDM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2303             :   }
    2304             :   return 0;
    2305             : }
    2306             : 
    2307             : unsigned fastEmit_ISD_SUB_MVT_v1i128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2308           0 :   if (RetVT.SimpleTy != MVT::v1i128)
    2309             :     return 0;
    2310           0 :   if ((PPCSubTarget->hasP8Altivec())) {
    2311           0 :     return fastEmitInst_rr(PPC::VSUBUQM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2312             :   }
    2313             :   return 0;
    2314             : }
    2315             : 
    2316           1 : unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2317           1 :   switch (VT.SimpleTy) {
    2318           0 :   case MVT::i1: return fastEmit_ISD_SUB_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2319           0 :   case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2320           0 :   case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2321           0 :   case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2322           0 :   case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2323           0 :   case MVT::v1i128: return fastEmit_ISD_SUB_MVT_v1i128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2324             :   default: return 0;
    2325             :   }
    2326             : }
    2327             : 
    2328             : // FastEmit functions for ISD::UDIV.
    2329             : 
    2330             : unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2331           0 :   if (RetVT.SimpleTy != MVT::i32)
    2332             :     return 0;
    2333           0 :   return fastEmitInst_rr(PPC::DIVWU, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2334             : }
    2335             : 
    2336             : unsigned fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2337           0 :   if (RetVT.SimpleTy != MVT::i64)
    2338             :     return 0;
    2339           0 :   return fastEmitInst_rr(PPC::DIVDU, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2340             : }
    2341             : 
    2342           0 : unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2343           0 :   switch (VT.SimpleTy) {
    2344           0 :   case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2345           0 :   case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2346             :   default: return 0;
    2347             :   }
    2348             : }
    2349             : 
    2350             : // FastEmit functions for ISD::UREM.
    2351             : 
    2352             : unsigned fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2353           0 :   if (RetVT.SimpleTy != MVT::i32)
    2354             :     return 0;
    2355           0 :   if ((PPCSubTarget->isISA3_0())) {
    2356           0 :     return fastEmitInst_rr(PPC::MODUW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2357             :   }
    2358             :   return 0;
    2359             : }
    2360             : 
    2361             : unsigned fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2362           0 :   if (RetVT.SimpleTy != MVT::i64)
    2363             :     return 0;
    2364           0 :   if ((PPCSubTarget->isISA3_0())) {
    2365           0 :     return fastEmitInst_rr(PPC::MODUD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2366             :   }
    2367             :   return 0;
    2368             : }
    2369             : 
    2370           0 : unsigned fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2371           0 :   switch (VT.SimpleTy) {
    2372           0 :   case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2373           0 :   case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2374             :   default: return 0;
    2375             :   }
    2376             : }
    2377             : 
    2378             : // FastEmit functions for ISD::XOR.
    2379             : 
    2380             : unsigned fastEmit_ISD_XOR_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2381           0 :   if (RetVT.SimpleTy != MVT::i1)
    2382             :     return 0;
    2383           0 :   return fastEmitInst_rr(PPC::CRXOR, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2384             : }
    2385             : 
    2386             : unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2387           0 :   if (RetVT.SimpleTy != MVT::i32)
    2388             :     return 0;
    2389           0 :   return fastEmitInst_rr(PPC::XOR, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2390             : }
    2391             : 
    2392             : unsigned fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2393           0 :   if (RetVT.SimpleTy != MVT::i64)
    2394             :     return 0;
    2395           0 :   return fastEmitInst_rr(PPC::XOR8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2396             : }
    2397             : 
    2398           2 : unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2399           2 :   if (RetVT.SimpleTy != MVT::v4i32)
    2400             :     return 0;
    2401           2 :   if ((PPCSubTarget->hasVSX())) {
    2402           4 :     return fastEmitInst_rr(PPC::XXLXOR, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2403             :   }
    2404           0 :   if ((PPCSubTarget->hasAltivec())) {
    2405           0 :     return fastEmitInst_rr(PPC::VXOR, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2406             :   }
    2407             :   return 0;
    2408             : }
    2409             : 
    2410           6 : unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2411           6 :   switch (VT.SimpleTy) {
    2412           0 :   case MVT::i1: return fastEmit_ISD_XOR_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2413           0 :   case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2414           0 :   case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2415           2 :   case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2416             :   default: return 0;
    2417             :   }
    2418             : }
    2419             : 
    2420             : // FastEmit functions for PPCISD::CMPB.
    2421             : 
    2422             : unsigned fastEmit_PPCISD_CMPB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2423           0 :   if (RetVT.SimpleTy != MVT::i32)
    2424             :     return 0;
    2425           0 :   return fastEmitInst_rr(PPC::CMPB, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2426             : }
    2427             : 
    2428             : unsigned fastEmit_PPCISD_CMPB_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2429           0 :   if (RetVT.SimpleTy != MVT::i64)
    2430             :     return 0;
    2431           0 :   return fastEmitInst_rr(PPC::CMPB8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2432             : }
    2433             : 
    2434           0 : unsigned fastEmit_PPCISD_CMPB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2435           0 :   switch (VT.SimpleTy) {
    2436           0 :   case MVT::i32: return fastEmit_PPCISD_CMPB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2437           0 :   case MVT::i64: return fastEmit_PPCISD_CMPB_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2438             :   default: return 0;
    2439             :   }
    2440             : }
    2441             : 
    2442             : // FastEmit functions for PPCISD::FADDRTZ.
    2443             : 
    2444             : unsigned fastEmit_PPCISD_FADDRTZ_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2445           0 :   if (RetVT.SimpleTy != MVT::f64)
    2446             :     return 0;
    2447           0 :   return fastEmitInst_rr(PPC::FADDrtz, &PPC::F8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2448             : }
    2449             : 
    2450             : unsigned fastEmit_PPCISD_FADDRTZ_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2451           0 :   switch (VT.SimpleTy) {
    2452           0 :   case MVT::f64: return fastEmit_PPCISD_FADDRTZ_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2453             :   default: return 0;
    2454             :   }
    2455             : }
    2456             : 
    2457             : // FastEmit functions for PPCISD::SHL.
    2458             : 
    2459             : unsigned fastEmit_PPCISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2460           0 :   if (RetVT.SimpleTy != MVT::i32)
    2461             :     return 0;
    2462           0 :   return fastEmitInst_rr(PPC::SLW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2463             : }
    2464             : 
    2465             : unsigned fastEmit_PPCISD_SHL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2466           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2467             :     return 0;
    2468           0 :   if ((PPCSubTarget->hasAltivec())) {
    2469           0 :     return fastEmitInst_rr(PPC::VSLB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2470             :   }
    2471             :   return 0;
    2472             : }
    2473             : 
    2474             : unsigned fastEmit_PPCISD_SHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2475           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2476             :     return 0;
    2477           0 :   if ((PPCSubTarget->hasAltivec())) {
    2478           0 :     return fastEmitInst_rr(PPC::VSLH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2479             :   }
    2480             :   return 0;
    2481             : }
    2482             : 
    2483             : unsigned fastEmit_PPCISD_SHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2484           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2485             :     return 0;
    2486           0 :   if ((PPCSubTarget->hasAltivec())) {
    2487           0 :     return fastEmitInst_rr(PPC::VSLW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2488             :   }
    2489             :   return 0;
    2490             : }
    2491             : 
    2492             : unsigned fastEmit_PPCISD_SHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2493           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2494             :     return 0;
    2495           0 :   if ((PPCSubTarget->hasP8Altivec())) {
    2496           0 :     return fastEmitInst_rr(PPC::VSLD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2497             :   }
    2498             :   return 0;
    2499             : }
    2500             : 
    2501           0 : unsigned fastEmit_PPCISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2502           0 :   switch (VT.SimpleTy) {
    2503           0 :   case MVT::i32: return fastEmit_PPCISD_SHL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2504           0 :   case MVT::v16i8: return fastEmit_PPCISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2505           0 :   case MVT::v8i16: return fastEmit_PPCISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2506           0 :   case MVT::v4i32: return fastEmit_PPCISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2507           0 :   case MVT::v2i64: return fastEmit_PPCISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2508             :   default: return 0;
    2509             :   }
    2510             : }
    2511             : 
    2512             : // FastEmit functions for PPCISD::SRA.
    2513             : 
    2514             : unsigned fastEmit_PPCISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2515           0 :   if (RetVT.SimpleTy != MVT::i32)
    2516             :     return 0;
    2517           0 :   return fastEmitInst_rr(PPC::SRAW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2518             : }
    2519             : 
    2520             : unsigned fastEmit_PPCISD_SRA_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2521           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2522             :     return 0;
    2523           0 :   if ((PPCSubTarget->hasAltivec())) {
    2524           0 :     return fastEmitInst_rr(PPC::VSRAB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2525             :   }
    2526             :   return 0;
    2527             : }
    2528             : 
    2529             : unsigned fastEmit_PPCISD_SRA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2530           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2531             :     return 0;
    2532           0 :   if ((PPCSubTarget->hasAltivec())) {
    2533           0 :     return fastEmitInst_rr(PPC::VSRAH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2534             :   }
    2535             :   return 0;
    2536             : }
    2537             : 
    2538             : unsigned fastEmit_PPCISD_SRA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2539           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2540             :     return 0;
    2541           0 :   if ((PPCSubTarget->hasAltivec())) {
    2542           0 :     return fastEmitInst_rr(PPC::VSRAW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2543             :   }
    2544             :   return 0;
    2545             : }
    2546             : 
    2547             : unsigned fastEmit_PPCISD_SRA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2548           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2549             :     return 0;
    2550           0 :   if ((PPCSubTarget->hasP8Altivec())) {
    2551           0 :     return fastEmitInst_rr(PPC::VSRAD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2552             :   }
    2553             :   return 0;
    2554             : }
    2555             : 
    2556           0 : unsigned fastEmit_PPCISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2557           0 :   switch (VT.SimpleTy) {
    2558           0 :   case MVT::i32: return fastEmit_PPCISD_SRA_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2559           0 :   case MVT::v16i8: return fastEmit_PPCISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2560           0 :   case MVT::v8i16: return fastEmit_PPCISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2561           0 :   case MVT::v4i32: return fastEmit_PPCISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2562           0 :   case MVT::v2i64: return fastEmit_PPCISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2563             :   default: return 0;
    2564             :   }
    2565             : }
    2566             : 
    2567             : // FastEmit functions for PPCISD::SRL.
    2568             : 
    2569             : unsigned fastEmit_PPCISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2570           0 :   if (RetVT.SimpleTy != MVT::i32)
    2571             :     return 0;
    2572           0 :   return fastEmitInst_rr(PPC::SRW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2573             : }
    2574             : 
    2575             : unsigned fastEmit_PPCISD_SRL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2576           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2577             :     return 0;
    2578           0 :   if ((PPCSubTarget->hasAltivec())) {
    2579           0 :     return fastEmitInst_rr(PPC::VSRB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2580             :   }
    2581             :   return 0;
    2582             : }
    2583             : 
    2584             : unsigned fastEmit_PPCISD_SRL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2585           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2586             :     return 0;
    2587           0 :   if ((PPCSubTarget->hasAltivec())) {
    2588           0 :     return fastEmitInst_rr(PPC::VSRH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2589             :   }
    2590             :   return 0;
    2591             : }
    2592             : 
    2593             : unsigned fastEmit_PPCISD_SRL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2594           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2595             :     return 0;
    2596           0 :   if ((PPCSubTarget->hasAltivec())) {
    2597           0 :     return fastEmitInst_rr(PPC::VSRW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2598             :   }
    2599             :   return 0;
    2600             : }
    2601             : 
    2602             : unsigned fastEmit_PPCISD_SRL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2603           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2604             :     return 0;
    2605           0 :   if ((PPCSubTarget->hasP8Altivec())) {
    2606           0 :     return fastEmitInst_rr(PPC::VSRD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2607             :   }
    2608             :   return 0;
    2609             : }
    2610             : 
    2611           0 : unsigned fastEmit_PPCISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2612           0 :   switch (VT.SimpleTy) {
    2613           0 :   case MVT::i32: return fastEmit_PPCISD_SRL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2614           0 :   case MVT::v16i8: return fastEmit_PPCISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2615           0 :   case MVT::v8i16: return fastEmit_PPCISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2616           0 :   case MVT::v4i32: return fastEmit_PPCISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2617           0 :   case MVT::v2i64: return fastEmit_PPCISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2618             :   default: return 0;
    2619             :   }
    2620             : }
    2621             : 
    2622             : // Top-level FastEmit function.
    2623             : 
    2624          60 : unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) override {
    2625          60 :   switch (Opcode) {
    2626           2 :   case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2627           0 :   case ISD::ADDC: return fastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2628           0 :   case ISD::ADDE: return fastEmit_ISD_ADDE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2629          15 :   case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2630           0 :   case ISD::BUILD_VECTOR: return fastEmit_ISD_BUILD_VECTOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2631          14 :   case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2632           2 :   case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2633           2 :   case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2634           0 :   case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2635           0 :   case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2636           0 :   case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2637           0 :   case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2638           6 :   case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2639           0 :   case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2640           5 :   case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2641           3 :   case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2642           0 :   case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2643           4 :   case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2644           1 :   case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2645           0 :   case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2646           0 :   case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2647           6 :   case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2648           0 :   case PPCISD::CMPB: return fastEmit_PPCISD_CMPB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2649           0 :   case PPCISD::FADDRTZ: return fastEmit_PPCISD_FADDRTZ_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2650           0 :   case PPCISD::SHL: return fastEmit_PPCISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2651           0 :   case PPCISD::SRA: return fastEmit_PPCISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2652           0 :   case PPCISD::SRL: return fastEmit_PPCISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2653             :   default: return 0;
    2654             :   }
    2655             : }
    2656             : 
    2657             : // FastEmit functions for ISD::SRA.
    2658             : 
    2659             : unsigned fastEmit_ISD_SRA_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2660           1 :   if (RetVT.SimpleTy != MVT::i32)
    2661             :     return 0;
    2662           2 :   return fastEmitInst_ri(PPC::SRAWI, &PPC::GPRCRegClass, Op0, Op0IsKill, imm1);
    2663             : }
    2664             : 
    2665             : unsigned fastEmit_ISD_SRA_MVT_i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2666           0 :   if (RetVT.SimpleTy != MVT::i64)
    2667             :     return 0;
    2668           0 :   return fastEmitInst_ri(PPC::SRADI, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
    2669             : }
    2670             : 
    2671           1 : unsigned fastEmit_ISD_SRA_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2672           1 :   switch (VT.SimpleTy) {
    2673           1 :   case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1);
    2674           0 :   case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri(RetVT, Op0, Op0IsKill, imm1);
    2675             :   default: return 0;
    2676             :   }
    2677             : }
    2678             : 
    2679             : // FastEmit functions for PPCISD::QVESPLATI.
    2680             : 
    2681             : unsigned fastEmit_PPCISD_QVESPLATI_MVT_v4i1_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2682           0 :   if (RetVT.SimpleTy != MVT::v4i1)
    2683             :     return 0;
    2684           0 :   if ((PPCSubTarget->hasQPX())) {
    2685           0 :     return fastEmitInst_ri(PPC::QVESPLATIb, &PPC::QBRCRegClass, Op0, Op0IsKill, imm1);
    2686             :   }
    2687             :   return 0;
    2688             : }
    2689             : 
    2690             : unsigned fastEmit_PPCISD_QVESPLATI_MVT_v4f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2691           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    2692             :     return 0;
    2693           0 :   if ((PPCSubTarget->hasQPX())) {
    2694           0 :     return fastEmitInst_ri(PPC::QVESPLATIs, &PPC::QSRCRegClass, Op0, Op0IsKill, imm1);
    2695             :   }
    2696             :   return 0;
    2697             : }
    2698             : 
    2699             : unsigned fastEmit_PPCISD_QVESPLATI_MVT_v4f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2700           0 :   if (RetVT.SimpleTy != MVT::v4f64)
    2701             :     return 0;
    2702           0 :   if ((PPCSubTarget->hasQPX())) {
    2703           0 :     return fastEmitInst_ri(PPC::QVESPLATI, &PPC::QFRCRegClass, Op0, Op0IsKill, imm1);
    2704             :   }
    2705             :   return 0;
    2706             : }
    2707             : 
    2708           0 : unsigned fastEmit_PPCISD_QVESPLATI_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2709           0 :   switch (VT.SimpleTy) {
    2710           0 :   case MVT::v4i1: return fastEmit_PPCISD_QVESPLATI_MVT_v4i1_ri(RetVT, Op0, Op0IsKill, imm1);
    2711           0 :   case MVT::v4f32: return fastEmit_PPCISD_QVESPLATI_MVT_v4f32_ri(RetVT, Op0, Op0IsKill, imm1);
    2712           0 :   case MVT::v4f64: return fastEmit_PPCISD_QVESPLATI_MVT_v4f64_ri(RetVT, Op0, Op0IsKill, imm1);
    2713             :   default: return 0;
    2714             :   }
    2715             : }
    2716             : 
    2717             : // FastEmit functions for PPCISD::TC_RETURN.
    2718             : 
    2719             : unsigned fastEmit_PPCISD_TC_RETURN_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2720           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2721             :     return 0;
    2722           0 :   return fastEmitInst_ri(PPC::TCRETURNri, &PPC::CTRRCRegClass, Op0, Op0IsKill, imm1);
    2723             : }
    2724             : 
    2725             : unsigned fastEmit_PPCISD_TC_RETURN_MVT_i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2726           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2727             :     return 0;
    2728           0 :   return fastEmitInst_ri(PPC::TCRETURNri8, &PPC::CTRRC8RegClass, Op0, Op0IsKill, imm1);
    2729             : }
    2730             : 
    2731           0 : unsigned fastEmit_PPCISD_TC_RETURN_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2732           0 :   switch (VT.SimpleTy) {
    2733           0 :   case MVT::i32: return fastEmit_PPCISD_TC_RETURN_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1);
    2734           0 :   case MVT::i64: return fastEmit_PPCISD_TC_RETURN_MVT_i64_ri(RetVT, Op0, Op0IsKill, imm1);
    2735             :   default: return 0;
    2736             :   }
    2737             : }
    2738             : 
    2739             : // Top-level FastEmit function.
    2740             : 
    2741          42 : unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) override {
    2742          65 :   if (VT == MVT::i32 && Predicate_imm32SExt16(imm1))
    2743          23 :     if (unsigned Reg = fastEmit_ri_Predicate_imm32SExt16(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    2744             :       return Reg;
    2745             : 
    2746          41 :   if (VT == MVT::i64 && Predicate_imm64SExt16(imm1))
    2747          19 :     if (unsigned Reg = fastEmit_ri_Predicate_imm64SExt16(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    2748             :       return Reg;
    2749             : 
    2750           5 :   switch (Opcode) {
    2751           1 :   case ISD::SRA: return fastEmit_ISD_SRA_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    2752           0 :   case PPCISD::QVESPLATI: return fastEmit_PPCISD_QVESPLATI_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    2753           0 :   case PPCISD::TC_RETURN: return fastEmit_PPCISD_TC_RETURN_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    2754             :   default: return 0;
    2755             :   }
    2756             : }
    2757             : 
    2758             : // FastEmit functions for ISD::ADD.
    2759             : 
    2760             : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2761          20 :   if (RetVT.SimpleTy != MVT::i32)
    2762             :     return 0;
    2763          20 :   return fastEmitInst_ri(PPC::ADDI, &PPC::GPRCRegClass, Op0, Op0IsKill, imm1);
    2764             : }
    2765             : 
    2766             : unsigned fastEmit_ISD_ADD_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2767          20 :   switch (VT.SimpleTy) {
    2768          20 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, Op0IsKill, imm1);
    2769             :   default: return 0;
    2770             :   }
    2771             : }
    2772             : 
    2773             : // FastEmit functions for ISD::ADDC.
    2774             : 
    2775             : unsigned fastEmit_ISD_ADDC_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2776           0 :   if (RetVT.SimpleTy != MVT::i32)
    2777             :     return 0;
    2778           0 :   return fastEmitInst_ri(PPC::ADDIC, &PPC::GPRCRegClass, Op0, Op0IsKill, imm1);
    2779             : }
    2780             : 
    2781             : unsigned fastEmit_ISD_ADDC_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2782           0 :   switch (VT.SimpleTy) {
    2783           0 :   case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, Op0IsKill, imm1);
    2784             :   default: return 0;
    2785             :   }
    2786             : }
    2787             : 
    2788             : // FastEmit functions for ISD::MUL.
    2789             : 
    2790             : unsigned fastEmit_ISD_MUL_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2791           0 :   if (RetVT.SimpleTy != MVT::i32)
    2792             :     return 0;
    2793           0 :   return fastEmitInst_ri(PPC::MULLI, &PPC::GPRCRegClass, Op0, Op0IsKill, imm1);
    2794             : }
    2795             : 
    2796             : unsigned fastEmit_ISD_MUL_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2797           0 :   switch (VT.SimpleTy) {
    2798           0 :   case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, Op0IsKill, imm1);
    2799             :   default: return 0;
    2800             :   }
    2801             : }
    2802             : 
    2803             : // FastEmit functions for PPCISD::XXSPLT.
    2804             : 
    2805             : unsigned fastEmit_PPCISD_XXSPLT_MVT_v4i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2806           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2807             :     return 0;
    2808           0 :   if ((PPCSubTarget->hasVSX())) {
    2809           0 :     return fastEmitInst_ri(PPC::XXSPLTW, &PPC::VSRCRegClass, Op0, Op0IsKill, imm1);
    2810             :   }
    2811             :   return 0;
    2812             : }
    2813             : 
    2814           0 : unsigned fastEmit_PPCISD_XXSPLT_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2815           0 :   switch (VT.SimpleTy) {
    2816           0 :   case MVT::v4i32: return fastEmit_PPCISD_XXSPLT_MVT_v4i32_ri_Predicate_imm32SExt16(RetVT, Op0, Op0IsKill, imm1);
    2817             :   default: return 0;
    2818             :   }
    2819             : }
    2820             : 
    2821             : // Top-level FastEmit function.
    2822             : 
    2823          23 : unsigned fastEmit_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2824          23 :   switch (Opcode) {
    2825          20 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm32SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
    2826           0 :   case ISD::ADDC: return fastEmit_ISD_ADDC_ri_Predicate_imm32SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
    2827           0 :   case ISD::MUL: return fastEmit_ISD_MUL_ri_Predicate_imm32SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
    2828           0 :   case PPCISD::XXSPLT: return fastEmit_PPCISD_XXSPLT_ri_Predicate_imm32SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
    2829             :   default: return 0;
    2830             :   }
    2831             : }
    2832             : 
    2833             : // FastEmit functions for ISD::ADD.
    2834             : 
    2835             : unsigned fastEmit_ISD_ADD_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2836          17 :   if (RetVT.SimpleTy != MVT::i64)
    2837             :     return 0;
    2838          17 :   return fastEmitInst_ri(PPC::ADDI8, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
    2839             : }
    2840             : 
    2841             : unsigned fastEmit_ISD_ADD_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2842          17 :   switch (VT.SimpleTy) {
    2843          17 :   case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, Op0IsKill, imm1);
    2844             :   default: return 0;
    2845             :   }
    2846             : }
    2847             : 
    2848             : // FastEmit functions for ISD::ADDC.
    2849             : 
    2850             : unsigned fastEmit_ISD_ADDC_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2851           0 :   if (RetVT.SimpleTy != MVT::i64)
    2852             :     return 0;
    2853           0 :   return fastEmitInst_ri(PPC::ADDIC8, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
    2854             : }
    2855             : 
    2856             : unsigned fastEmit_ISD_ADDC_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2857           0 :   switch (VT.SimpleTy) {
    2858           0 :   case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, Op0IsKill, imm1);
    2859             :   default: return 0;
    2860             :   }
    2861             : }
    2862             : 
    2863             : // FastEmit functions for ISD::MUL.
    2864             : 
    2865             : unsigned fastEmit_ISD_MUL_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2866           0 :   if (RetVT.SimpleTy != MVT::i64)
    2867             :     return 0;
    2868           0 :   return fastEmitInst_ri(PPC::MULLI8, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
    2869             : }
    2870             : 
    2871             : unsigned fastEmit_ISD_MUL_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2872           0 :   switch (VT.SimpleTy) {
    2873           0 :   case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, Op0IsKill, imm1);
    2874             :   default: return 0;
    2875             :   }
    2876             : }
    2877             : 
    2878             : // Top-level FastEmit function.
    2879             : 
    2880          19 : unsigned fastEmit_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2881          19 :   switch (Opcode) {
    2882          17 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm64SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
    2883           0 :   case ISD::ADDC: return fastEmit_ISD_ADDC_ri_Predicate_imm64SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
    2884           0 :   case ISD::MUL: return fastEmit_ISD_MUL_ri_Predicate_imm64SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
    2885             :   default: return 0;
    2886             :   }
    2887             : }
    2888             : 

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