LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/PowerPC - PPCGenFastISel.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 142 1048 13.5 %
Date: 2018-06-17 00:07:59 Functions: 27 119 22.7 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* "Fast" Instruction Selector for the PPC target                             *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : 
      10             : // FastEmit Immediate Predicate functions.
      11             : static bool Predicate_imm32SExt16(int64_t Imm) {
      12             : 
      13             :   // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
      14             :   // sign extended field.  Used by instructions like 'addi'.
      15          23 :   return (int32_t)Imm == (short)Imm;
      16             : 
      17             : }
      18             : static bool Predicate_imm64SExt16(int64_t Imm) {
      19             : 
      20             :   // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
      21             :   // sign extended field.  Used by instructions like 'addi'.
      22          19 :   return (int64_t)Imm == (short)Imm;
      23             : 
      24             : }
      25             : static bool Predicate_immSExt5NonZero(int64_t Imm) {
      26             :  return Imm && isInt<5>(Imm); 
      27             : }
      28             : 
      29             : 
      30             : // FastEmit functions for ISD::READCYCLECOUNTER.
      31             : 
      32             : unsigned fastEmit_ISD_READCYCLECOUNTER_MVT_i64_(MVT RetVT) {
      33           0 :   if (RetVT.SimpleTy != MVT::i64)
      34             :     return 0;
      35           0 :   return fastEmitInst_(PPC::MFTB8, &PPC::G8RCRegClass);
      36             : }
      37             : 
      38             : unsigned fastEmit_ISD_READCYCLECOUNTER_(MVT VT, MVT RetVT) {
      39           0 :   switch (VT.SimpleTy) {
      40           0 :   case MVT::i64: return fastEmit_ISD_READCYCLECOUNTER_MVT_i64_(RetVT);
      41             :   default: return 0;
      42             :   }
      43             : }
      44             : 
      45             : // FastEmit functions for PPCISD::MFFS.
      46             : 
      47             : unsigned fastEmit_PPCISD_MFFS_MVT_f64_(MVT RetVT) {
      48           0 :   if (RetVT.SimpleTy != MVT::f64)
      49             :     return 0;
      50           0 :   return fastEmitInst_(PPC::MFFS, &PPC::F8RCRegClass);
      51             : }
      52             : 
      53             : unsigned fastEmit_PPCISD_MFFS_(MVT VT, MVT RetVT) {
      54           0 :   switch (VT.SimpleTy) {
      55           0 :   case MVT::f64: return fastEmit_PPCISD_MFFS_MVT_f64_(RetVT);
      56             :   default: return 0;
      57             :   }
      58             : }
      59             : 
      60             : // FastEmit functions for PPCISD::PPC32_GOT.
      61             : 
      62             : unsigned fastEmit_PPCISD_PPC32_GOT_MVT_i32_(MVT RetVT) {
      63           0 :   if (RetVT.SimpleTy != MVT::i32)
      64             :     return 0;
      65           0 :   return fastEmitInst_(PPC::PPC32GOT, &PPC::GPRCRegClass);
      66             : }
      67             : 
      68             : unsigned fastEmit_PPCISD_PPC32_GOT_(MVT VT, MVT RetVT) {
      69           0 :   switch (VT.SimpleTy) {
      70           0 :   case MVT::i32: return fastEmit_PPCISD_PPC32_GOT_MVT_i32_(RetVT);
      71             :   default: return 0;
      72             :   }
      73             : }
      74             : 
      75             : // Top-level FastEmit function.
      76             : 
      77           0 : unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode) override {
      78           0 :   switch (Opcode) {
      79           0 :   case ISD::READCYCLECOUNTER: return fastEmit_ISD_READCYCLECOUNTER_(VT, RetVT);
      80           0 :   case PPCISD::MFFS: return fastEmit_PPCISD_MFFS_(VT, RetVT);
      81           0 :   case PPCISD::PPC32_GOT: return fastEmit_PPCISD_PPC32_GOT_(VT, RetVT);
      82             :   default: return 0;
      83             :   }
      84             : }
      85             : 
      86             : // FastEmit functions for ISD::BITCAST.
      87             : 
      88           0 : unsigned fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      89           0 :   if (RetVT.SimpleTy != MVT::f64)
      90             :     return 0;
      91           0 :   if ((PPCSubTarget->hasDirectMove()) && (PPCSubTarget->hasVSX())) {
      92           0 :     return fastEmitInst_r(PPC::MTVSRD, &PPC::VSFRCRegClass, Op0, Op0IsKill);
      93             :   }
      94             :   return 0;
      95             : }
      96             : 
      97           0 : unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      98           0 :   if (RetVT.SimpleTy != MVT::i64)
      99             :     return 0;
     100           0 :   if ((PPCSubTarget->hasDirectMove()) && (PPCSubTarget->hasVSX())) {
     101           0 :     return fastEmitInst_r(PPC::MFVSRD, &PPC::G8RCRegClass, Op0, Op0IsKill);
     102             :   }
     103             :   return 0;
     104             : }
     105             : 
     106           2 : unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     107           2 :   switch (VT.SimpleTy) {
     108           0 :   case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0, Op0IsKill);
     109           0 :   case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0, Op0IsKill);
     110             :   default: return 0;
     111             :   }
     112             : }
     113             : 
     114             : // FastEmit functions for ISD::CTLZ.
     115             : 
     116             : unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     117           0 :   if (RetVT.SimpleTy != MVT::i32)
     118             :     return 0;
     119             :   return fastEmitInst_r(PPC::CNTLZW, &PPC::GPRCRegClass, Op0, Op0IsKill);
     120             : }
     121             : 
     122             : unsigned fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     123           0 :   if (RetVT.SimpleTy != MVT::i64)
     124             :     return 0;
     125             :   return fastEmitInst_r(PPC::CNTLZD, &PPC::G8RCRegClass, Op0, Op0IsKill);
     126             : }
     127             : 
     128             : unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     129           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     130             :     return 0;
     131           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     132             :     return fastEmitInst_r(PPC::VCLZB, &PPC::VRRCRegClass, Op0, Op0IsKill);
     133             :   }
     134             :   return 0;
     135             : }
     136             : 
     137             : unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     138           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     139             :     return 0;
     140           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     141             :     return fastEmitInst_r(PPC::VCLZH, &PPC::VRRCRegClass, Op0, Op0IsKill);
     142             :   }
     143             :   return 0;
     144             : }
     145             : 
     146             : unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     147           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     148             :     return 0;
     149           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     150             :     return fastEmitInst_r(PPC::VCLZW, &PPC::VRRCRegClass, Op0, Op0IsKill);
     151             :   }
     152             :   return 0;
     153             : }
     154             : 
     155             : unsigned fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     156           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     157             :     return 0;
     158           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     159             :     return fastEmitInst_r(PPC::VCLZD, &PPC::VRRCRegClass, Op0, Op0IsKill);
     160             :   }
     161             :   return 0;
     162             : }
     163             : 
     164           0 : unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     165           0 :   switch (VT.SimpleTy) {
     166           0 :   case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
     167           0 :   case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0, Op0IsKill);
     168           0 :   case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     169           0 :   case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     170           0 :   case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     171           0 :   case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     172             :   default: return 0;
     173             :   }
     174             : }
     175             : 
     176             : // FastEmit functions for ISD::CTPOP.
     177             : 
     178             : unsigned fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     179           0 :   if (RetVT.SimpleTy != MVT::i32)
     180             :     return 0;
     181             :   return fastEmitInst_r(PPC::POPCNTW, &PPC::GPRCRegClass, Op0, Op0IsKill);
     182             : }
     183             : 
     184             : unsigned fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     185           0 :   if (RetVT.SimpleTy != MVT::i64)
     186             :     return 0;
     187             :   return fastEmitInst_r(PPC::POPCNTD, &PPC::G8RCRegClass, Op0, Op0IsKill);
     188             : }
     189             : 
     190             : unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     191           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     192             :     return 0;
     193           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     194             :     return fastEmitInst_r(PPC::VPOPCNTB, &PPC::VRRCRegClass, Op0, Op0IsKill);
     195             :   }
     196             :   return 0;
     197             : }
     198             : 
     199             : unsigned fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     200           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     201             :     return 0;
     202           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     203             :     return fastEmitInst_r(PPC::VPOPCNTH, &PPC::VRRCRegClass, Op0, Op0IsKill);
     204             :   }
     205             :   return 0;
     206             : }
     207             : 
     208             : unsigned fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     209           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     210             :     return 0;
     211           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     212             :     return fastEmitInst_r(PPC::VPOPCNTW, &PPC::VRRCRegClass, Op0, Op0IsKill);
     213             :   }
     214             :   return 0;
     215             : }
     216             : 
     217             : unsigned fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     218           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     219             :     return 0;
     220           0 :   if ((PPCSubTarget->hasP8Altivec())) {
     221             :     return fastEmitInst_r(PPC::VPOPCNTD, &PPC::VRRCRegClass, Op0, Op0IsKill);
     222             :   }
     223             :   return 0;
     224             : }
     225             : 
     226           0 : unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     227           0 :   switch (VT.SimpleTy) {
     228           0 :   case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0, Op0IsKill);
     229           0 :   case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0, Op0IsKill);
     230           0 :   case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     231           0 :   case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     232           0 :   case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     233           0 :   case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     234             :   default: return 0;
     235             :   }
     236             : }
     237             : 
     238             : // FastEmit functions for ISD::CTTZ.
     239             : 
     240             : unsigned fastEmit_ISD_CTTZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     241           0 :   if (RetVT.SimpleTy != MVT::i32)
     242             :     return 0;
     243           0 :   if ((PPCSubTarget->isISA3_0())) {
     244             :     return fastEmitInst_r(PPC::CNTTZW, &PPC::GPRCRegClass, Op0, Op0IsKill);
     245             :   }
     246             :   return 0;
     247             : }
     248             : 
     249             : unsigned fastEmit_ISD_CTTZ_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     250           0 :   if (RetVT.SimpleTy != MVT::i64)
     251             :     return 0;
     252           0 :   if ((PPCSubTarget->isISA3_0())) {
     253             :     return fastEmitInst_r(PPC::CNTTZD, &PPC::G8RCRegClass, Op0, Op0IsKill);
     254             :   }
     255             :   return 0;
     256             : }
     257             : 
     258             : unsigned fastEmit_ISD_CTTZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     259           0 :   if (RetVT.SimpleTy != MVT::v16i8)
     260             :     return 0;
     261           0 :   if ((PPCSubTarget->hasP9Altivec())) {
     262             :     return fastEmitInst_r(PPC::VCTZB, &PPC::VRRCRegClass, Op0, Op0IsKill);
     263             :   }
     264             :   return 0;
     265             : }
     266             : 
     267             : unsigned fastEmit_ISD_CTTZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     268           0 :   if (RetVT.SimpleTy != MVT::v8i16)
     269             :     return 0;
     270           0 :   if ((PPCSubTarget->hasP9Altivec())) {
     271             :     return fastEmitInst_r(PPC::VCTZH, &PPC::VRRCRegClass, Op0, Op0IsKill);
     272             :   }
     273             :   return 0;
     274             : }
     275             : 
     276             : unsigned fastEmit_ISD_CTTZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     277           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     278             :     return 0;
     279           0 :   if ((PPCSubTarget->hasP9Altivec())) {
     280             :     return fastEmitInst_r(PPC::VCTZW, &PPC::VRRCRegClass, Op0, Op0IsKill);
     281             :   }
     282             :   return 0;
     283             : }
     284             : 
     285             : unsigned fastEmit_ISD_CTTZ_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     286           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     287             :     return 0;
     288           0 :   if ((PPCSubTarget->hasP9Altivec())) {
     289             :     return fastEmitInst_r(PPC::VCTZD, &PPC::VRRCRegClass, Op0, Op0IsKill);
     290             :   }
     291             :   return 0;
     292             : }
     293             : 
     294           0 : unsigned fastEmit_ISD_CTTZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     295           0 :   switch (VT.SimpleTy) {
     296           0 :   case MVT::i32: return fastEmit_ISD_CTTZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
     297           0 :   case MVT::i64: return fastEmit_ISD_CTTZ_MVT_i64_r(RetVT, Op0, Op0IsKill);
     298           0 :   case MVT::v16i8: return fastEmit_ISD_CTTZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     299           0 :   case MVT::v8i16: return fastEmit_ISD_CTTZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     300           0 :   case MVT::v4i32: return fastEmit_ISD_CTTZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     301           0 :   case MVT::v2i64: return fastEmit_ISD_CTTZ_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     302             :   default: return 0;
     303             :   }
     304             : }
     305             : 
     306             : // FastEmit functions for ISD::FABS.
     307             : 
     308             : unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     309           0 :   if (RetVT.SimpleTy != MVT::f32)
     310             :     return 0;
     311             :   return fastEmitInst_r(PPC::FABSS, &PPC::F4RCRegClass, Op0, Op0IsKill);
     312             : }
     313             : 
     314           0 : unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     315           0 :   if (RetVT.SimpleTy != MVT::f64)
     316             :     return 0;
     317           0 :   if ((PPCSubTarget->hasVSX())) {
     318           0 :     return fastEmitInst_r(PPC::XSABSDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     319             :   }
     320           0 :   return fastEmitInst_r(PPC::FABSD, &PPC::F8RCRegClass, Op0, Op0IsKill);
     321             : }
     322             : 
     323             : unsigned fastEmit_ISD_FABS_MVT_f128_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     324           0 :   if (RetVT.SimpleTy != MVT::f128)
     325             :     return 0;
     326           0 :   if ((PPCSubTarget->hasP9Vector())) {
     327             :     return fastEmitInst_r(PPC::XSABSQP, &PPC::VRRCRegClass, Op0, Op0IsKill);
     328             :   }
     329             :   return 0;
     330             : }
     331             : 
     332           0 : unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     333           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     334             :     return 0;
     335           0 :   if ((PPCSubTarget->hasVSX())) {
     336           0 :     return fastEmitInst_r(PPC::XVABSSP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     337             :   }
     338           0 :   if ((PPCSubTarget->hasQPX())) {
     339           0 :     return fastEmitInst_r(PPC::QVFABSs, &PPC::QSRCRegClass, Op0, Op0IsKill);
     340             :   }
     341             :   return 0;
     342             : }
     343             : 
     344             : unsigned fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     345           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     346             :     return 0;
     347           0 :   if ((PPCSubTarget->hasVSX())) {
     348             :     return fastEmitInst_r(PPC::XVABSDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     349             :   }
     350             :   return 0;
     351             : }
     352             : 
     353             : unsigned fastEmit_ISD_FABS_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     354           0 :   if (RetVT.SimpleTy != MVT::v4f64)
     355             :     return 0;
     356           0 :   if ((PPCSubTarget->hasQPX())) {
     357             :     return fastEmitInst_r(PPC::QVFABS, &PPC::QFRCRegClass, Op0, Op0IsKill);
     358             :   }
     359             :   return 0;
     360             : }
     361             : 
     362           0 : unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     363           0 :   switch (VT.SimpleTy) {
     364           0 :   case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill);
     365           0 :   case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0, Op0IsKill);
     366           0 :   case MVT::f128: return fastEmit_ISD_FABS_MVT_f128_r(RetVT, Op0, Op0IsKill);
     367           0 :   case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     368           0 :   case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     369           0 :   case MVT::v4f64: return fastEmit_ISD_FABS_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
     370             :   default: return 0;
     371             :   }
     372             : }
     373             : 
     374             : // FastEmit functions for ISD::FCEIL.
     375             : 
     376             : unsigned fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     377           0 :   if (RetVT.SimpleTy != MVT::f32)
     378             :     return 0;
     379             :   return fastEmitInst_r(PPC::FRIPS, &PPC::F4RCRegClass, Op0, Op0IsKill);
     380             : }
     381             : 
     382           0 : unsigned fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     383           0 :   if (RetVT.SimpleTy != MVT::f64)
     384             :     return 0;
     385           0 :   if ((PPCSubTarget->hasVSX())) {
     386           0 :     return fastEmitInst_r(PPC::XSRDPIP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     387             :   }
     388           0 :   return fastEmitInst_r(PPC::FRIPD, &PPC::F8RCRegClass, Op0, Op0IsKill);
     389             : }
     390             : 
     391           0 : unsigned fastEmit_ISD_FCEIL_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     392           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     393             :     return 0;
     394           0 :   if ((PPCSubTarget->hasVSX())) {
     395           0 :     return fastEmitInst_r(PPC::XVRSPIP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     396             :   }
     397           0 :   if ((PPCSubTarget->hasAltivec())) {
     398           0 :     return fastEmitInst_r(PPC::VRFIP, &PPC::VRRCRegClass, Op0, Op0IsKill);
     399             :   }
     400           0 :   if ((PPCSubTarget->hasQPX())) {
     401           0 :     return fastEmitInst_r(PPC::QVFRIPs, &PPC::QSRCRegClass, Op0, Op0IsKill);
     402             :   }
     403             :   return 0;
     404             : }
     405             : 
     406             : unsigned fastEmit_ISD_FCEIL_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     407           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     408             :     return 0;
     409           0 :   if ((PPCSubTarget->hasVSX())) {
     410             :     return fastEmitInst_r(PPC::XVRDPIP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     411             :   }
     412             :   return 0;
     413             : }
     414             : 
     415             : unsigned fastEmit_ISD_FCEIL_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     416           0 :   if (RetVT.SimpleTy != MVT::v4f64)
     417             :     return 0;
     418           0 :   if ((PPCSubTarget->hasQPX())) {
     419             :     return fastEmitInst_r(PPC::QVFRIP, &PPC::QFRCRegClass, Op0, Op0IsKill);
     420             :   }
     421             :   return 0;
     422             : }
     423             : 
     424           0 : unsigned fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     425           0 :   switch (VT.SimpleTy) {
     426           0 :   case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0, Op0IsKill);
     427           0 :   case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0, Op0IsKill);
     428           0 :   case MVT::v4f32: return fastEmit_ISD_FCEIL_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     429           0 :   case MVT::v2f64: return fastEmit_ISD_FCEIL_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     430           0 :   case MVT::v4f64: return fastEmit_ISD_FCEIL_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
     431             :   default: return 0;
     432             :   }
     433             : }
     434             : 
     435             : // FastEmit functions for ISD::FFLOOR.
     436             : 
     437             : unsigned fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     438           0 :   if (RetVT.SimpleTy != MVT::f32)
     439             :     return 0;
     440             :   return fastEmitInst_r(PPC::FRIMS, &PPC::F4RCRegClass, Op0, Op0IsKill);
     441             : }
     442             : 
     443           0 : unsigned fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     444           0 :   if (RetVT.SimpleTy != MVT::f64)
     445             :     return 0;
     446           0 :   if ((PPCSubTarget->hasVSX())) {
     447           0 :     return fastEmitInst_r(PPC::XSRDPIM, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     448             :   }
     449           0 :   return fastEmitInst_r(PPC::FRIMD, &PPC::F8RCRegClass, Op0, Op0IsKill);
     450             : }
     451             : 
     452           0 : unsigned fastEmit_ISD_FFLOOR_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     453           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     454             :     return 0;
     455           0 :   if ((PPCSubTarget->hasVSX())) {
     456           0 :     return fastEmitInst_r(PPC::XVRSPIM, &PPC::VSRCRegClass, Op0, Op0IsKill);
     457             :   }
     458           0 :   if ((PPCSubTarget->hasAltivec())) {
     459           0 :     return fastEmitInst_r(PPC::VRFIM, &PPC::VRRCRegClass, Op0, Op0IsKill);
     460             :   }
     461           0 :   if ((PPCSubTarget->hasQPX())) {
     462           0 :     return fastEmitInst_r(PPC::QVFRIMs, &PPC::QSRCRegClass, Op0, Op0IsKill);
     463             :   }
     464             :   return 0;
     465             : }
     466             : 
     467             : unsigned fastEmit_ISD_FFLOOR_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     468           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     469             :     return 0;
     470           0 :   if ((PPCSubTarget->hasVSX())) {
     471             :     return fastEmitInst_r(PPC::XVRDPIM, &PPC::VSRCRegClass, Op0, Op0IsKill);
     472             :   }
     473             :   return 0;
     474             : }
     475             : 
     476             : unsigned fastEmit_ISD_FFLOOR_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     477           0 :   if (RetVT.SimpleTy != MVT::v4f64)
     478             :     return 0;
     479           0 :   if ((PPCSubTarget->hasQPX())) {
     480             :     return fastEmitInst_r(PPC::QVFRIM, &PPC::QFRCRegClass, Op0, Op0IsKill);
     481             :   }
     482             :   return 0;
     483             : }
     484             : 
     485           0 : unsigned fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     486           0 :   switch (VT.SimpleTy) {
     487           0 :   case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0, Op0IsKill);
     488           0 :   case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0, Op0IsKill);
     489           0 :   case MVT::v4f32: return fastEmit_ISD_FFLOOR_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     490           0 :   case MVT::v2f64: return fastEmit_ISD_FFLOOR_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     491           0 :   case MVT::v4f64: return fastEmit_ISD_FFLOOR_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
     492             :   default: return 0;
     493             :   }
     494             : }
     495             : 
     496             : // FastEmit functions for ISD::FNEARBYINT.
     497             : 
     498             : unsigned fastEmit_ISD_FNEARBYINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     499           0 :   if (RetVT.SimpleTy != MVT::f64)
     500             :     return 0;
     501           0 :   if ((PPCSubTarget->hasVSX())) {
     502             :     return fastEmitInst_r(PPC::XSRDPIC, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     503             :   }
     504             :   return 0;
     505             : }
     506             : 
     507           0 : unsigned fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     508           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     509             :     return 0;
     510           0 :   if ((PPCSubTarget->hasVSX())) {
     511           0 :     return fastEmitInst_r(PPC::XVRSPIC, &PPC::VSRCRegClass, Op0, Op0IsKill);
     512             :   }
     513           0 :   if ((PPCSubTarget->hasAltivec())) {
     514           0 :     return fastEmitInst_r(PPC::VRFIN, &PPC::VRRCRegClass, Op0, Op0IsKill);
     515             :   }
     516             :   return 0;
     517             : }
     518             : 
     519             : unsigned fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     520           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     521             :     return 0;
     522           0 :   if ((PPCSubTarget->hasVSX())) {
     523             :     return fastEmitInst_r(PPC::XVRDPIC, &PPC::VSRCRegClass, Op0, Op0IsKill);
     524             :   }
     525             :   return 0;
     526             : }
     527             : 
     528           0 : unsigned fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     529           0 :   switch (VT.SimpleTy) {
     530           0 :   case MVT::f64: return fastEmit_ISD_FNEARBYINT_MVT_f64_r(RetVT, Op0, Op0IsKill);
     531           0 :   case MVT::v4f32: return fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     532           0 :   case MVT::v2f64: return fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     533             :   default: return 0;
     534             :   }
     535             : }
     536             : 
     537             : // FastEmit functions for ISD::FNEG.
     538             : 
     539             : unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     540           0 :   if (RetVT.SimpleTy != MVT::f32)
     541             :     return 0;
     542             :   return fastEmitInst_r(PPC::FNEGS, &PPC::F4RCRegClass, Op0, Op0IsKill);
     543             : }
     544             : 
     545           0 : unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     546           0 :   if (RetVT.SimpleTy != MVT::f64)
     547             :     return 0;
     548           0 :   if ((PPCSubTarget->hasVSX())) {
     549           0 :     return fastEmitInst_r(PPC::XSNEGDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     550             :   }
     551           0 :   return fastEmitInst_r(PPC::FNEGD, &PPC::F8RCRegClass, Op0, Op0IsKill);
     552             : }
     553             : 
     554             : unsigned fastEmit_ISD_FNEG_MVT_f128_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     555           0 :   if (RetVT.SimpleTy != MVT::f128)
     556             :     return 0;
     557           0 :   if ((PPCSubTarget->hasP9Vector())) {
     558             :     return fastEmitInst_r(PPC::XSNEGQP, &PPC::VRRCRegClass, Op0, Op0IsKill);
     559             :   }
     560             :   return 0;
     561             : }
     562             : 
     563           0 : unsigned fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     564           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     565             :     return 0;
     566           0 :   if ((PPCSubTarget->hasVSX())) {
     567           0 :     return fastEmitInst_r(PPC::XVNEGSP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     568             :   }
     569           0 :   if ((PPCSubTarget->hasQPX())) {
     570           0 :     return fastEmitInst_r(PPC::QVFNEGs, &PPC::QSRCRegClass, Op0, Op0IsKill);
     571             :   }
     572             :   return 0;
     573             : }
     574             : 
     575             : unsigned fastEmit_ISD_FNEG_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     576           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     577             :     return 0;
     578           0 :   if ((PPCSubTarget->hasVSX())) {
     579             :     return fastEmitInst_r(PPC::XVNEGDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     580             :   }
     581             :   return 0;
     582             : }
     583             : 
     584             : unsigned fastEmit_ISD_FNEG_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     585           0 :   if (RetVT.SimpleTy != MVT::v4f64)
     586             :     return 0;
     587           0 :   if ((PPCSubTarget->hasQPX())) {
     588             :     return fastEmitInst_r(PPC::QVFNEG, &PPC::QFRCRegClass, Op0, Op0IsKill);
     589             :   }
     590             :   return 0;
     591             : }
     592             : 
     593           0 : unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     594           0 :   switch (VT.SimpleTy) {
     595           0 :   case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill);
     596           0 :   case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0, Op0IsKill);
     597           0 :   case MVT::f128: return fastEmit_ISD_FNEG_MVT_f128_r(RetVT, Op0, Op0IsKill);
     598           0 :   case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     599           0 :   case MVT::v2f64: return fastEmit_ISD_FNEG_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     600           0 :   case MVT::v4f64: return fastEmit_ISD_FNEG_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
     601             :   default: return 0;
     602             :   }
     603             : }
     604             : 
     605             : // FastEmit functions for ISD::FP_EXTEND.
     606             : 
     607             : unsigned fastEmit_ISD_FP_EXTEND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     608           0 :   if (RetVT.SimpleTy != MVT::f128)
     609             :     return 0;
     610           0 :   if ((PPCSubTarget->hasP9Vector())) {
     611             :     return fastEmitInst_r(PPC::XSCVDPQP, &PPC::VRRCRegClass, Op0, Op0IsKill);
     612             :   }
     613             :   return 0;
     614             : }
     615             : 
     616           0 : unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     617           0 :   switch (VT.SimpleTy) {
     618           0 :   case MVT::f64: return fastEmit_ISD_FP_EXTEND_MVT_f64_r(RetVT, Op0, Op0IsKill);
     619             :   default: return 0;
     620             :   }
     621             : }
     622             : 
     623             : // FastEmit functions for ISD::FP_ROUND.
     624             : 
     625             : unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     626           0 :   if (RetVT.SimpleTy != MVT::f32)
     627             :     return 0;
     628             :   return fastEmitInst_r(PPC::FRSP, &PPC::F4RCRegClass, Op0, Op0IsKill);
     629             : }
     630             : 
     631             : unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     632           0 :   switch (VT.SimpleTy) {
     633           0 :   case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
     634             :   default: return 0;
     635             :   }
     636             : }
     637             : 
     638             : // FastEmit functions for ISD::FP_TO_SINT.
     639             : 
     640           0 : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     641           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     642             :     return 0;
     643           0 :   if ((PPCSubTarget->hasVSX())) {
     644           0 :     return fastEmitInst_r(PPC::XVCVSPSXWS, &PPC::VSRCRegClass, Op0, Op0IsKill);
     645             :   }
     646           0 :   if ((PPCSubTarget->hasAltivec())) {
     647           0 :     return fastEmitInst_r(PPC::VCTSXS_0, &PPC::VRRCRegClass, Op0, Op0IsKill);
     648             :   }
     649             :   return 0;
     650             : }
     651             : 
     652             : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     653           2 :   if (RetVT.SimpleTy != MVT::v2i64)
     654             :     return 0;
     655           2 :   if ((PPCSubTarget->hasVSX())) {
     656             :     return fastEmitInst_r(PPC::XVCVDPSXDS, &PPC::VSRCRegClass, Op0, Op0IsKill);
     657             :   }
     658             :   return 0;
     659             : }
     660             : 
     661          20 : unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     662          20 :   switch (VT.SimpleTy) {
     663           0 :   case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     664           2 :   case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     665             :   default: return 0;
     666             :   }
     667             : }
     668             : 
     669             : // FastEmit functions for ISD::FP_TO_UINT.
     670             : 
     671           0 : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     672           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     673             :     return 0;
     674           0 :   if ((PPCSubTarget->hasVSX())) {
     675           0 :     return fastEmitInst_r(PPC::XVCVSPUXWS, &PPC::VSRCRegClass, Op0, Op0IsKill);
     676             :   }
     677           0 :   if ((PPCSubTarget->hasAltivec())) {
     678           0 :     return fastEmitInst_r(PPC::VCTUXS_0, &PPC::VRRCRegClass, Op0, Op0IsKill);
     679             :   }
     680             :   return 0;
     681             : }
     682             : 
     683             : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     684           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     685             :     return 0;
     686           0 :   if ((PPCSubTarget->hasVSX())) {
     687             :     return fastEmitInst_r(PPC::XVCVDPUXDS, &PPC::VSRCRegClass, Op0, Op0IsKill);
     688             :   }
     689             :   return 0;
     690             : }
     691             : 
     692           0 : unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     693           0 :   switch (VT.SimpleTy) {
     694           0 :   case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     695           0 :   case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     696             :   default: return 0;
     697             :   }
     698             : }
     699             : 
     700             : // FastEmit functions for ISD::FROUND.
     701             : 
     702             : unsigned fastEmit_ISD_FROUND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     703           0 :   if (RetVT.SimpleTy != MVT::f32)
     704             :     return 0;
     705             :   return fastEmitInst_r(PPC::FRINS, &PPC::F4RCRegClass, Op0, Op0IsKill);
     706             : }
     707             : 
     708           0 : unsigned fastEmit_ISD_FROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     709           0 :   if (RetVT.SimpleTy != MVT::f64)
     710             :     return 0;
     711           0 :   if ((PPCSubTarget->hasVSX())) {
     712           0 :     return fastEmitInst_r(PPC::XSRDPI, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     713             :   }
     714           0 :   return fastEmitInst_r(PPC::FRIND, &PPC::F8RCRegClass, Op0, Op0IsKill);
     715             : }
     716             : 
     717           0 : unsigned fastEmit_ISD_FROUND_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     718           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     719             :     return 0;
     720           0 :   if ((PPCSubTarget->hasVSX())) {
     721           0 :     return fastEmitInst_r(PPC::XVRSPI, &PPC::VSRCRegClass, Op0, Op0IsKill);
     722             :   }
     723           0 :   if ((PPCSubTarget->hasQPX())) {
     724           0 :     return fastEmitInst_r(PPC::QVFRINs, &PPC::QSRCRegClass, Op0, Op0IsKill);
     725             :   }
     726             :   return 0;
     727             : }
     728             : 
     729             : unsigned fastEmit_ISD_FROUND_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     730           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     731             :     return 0;
     732           0 :   if ((PPCSubTarget->hasVSX())) {
     733             :     return fastEmitInst_r(PPC::XVRDPI, &PPC::VSRCRegClass, Op0, Op0IsKill);
     734             :   }
     735             :   return 0;
     736             : }
     737             : 
     738             : unsigned fastEmit_ISD_FROUND_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     739           0 :   if (RetVT.SimpleTy != MVT::v4f64)
     740             :     return 0;
     741           0 :   if ((PPCSubTarget->hasQPX())) {
     742             :     return fastEmitInst_r(PPC::QVFRIN, &PPC::QFRCRegClass, Op0, Op0IsKill);
     743             :   }
     744             :   return 0;
     745             : }
     746             : 
     747           0 : unsigned fastEmit_ISD_FROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     748           0 :   switch (VT.SimpleTy) {
     749           0 :   case MVT::f32: return fastEmit_ISD_FROUND_MVT_f32_r(RetVT, Op0, Op0IsKill);
     750           0 :   case MVT::f64: return fastEmit_ISD_FROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
     751           0 :   case MVT::v4f32: return fastEmit_ISD_FROUND_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     752           0 :   case MVT::v2f64: return fastEmit_ISD_FROUND_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     753           0 :   case MVT::v4f64: return fastEmit_ISD_FROUND_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
     754             :   default: return 0;
     755             :   }
     756             : }
     757             : 
     758             : // FastEmit functions for ISD::FSQRT.
     759             : 
     760           0 : unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     761           0 :   if (RetVT.SimpleTy != MVT::f32)
     762             :     return 0;
     763           0 :   if ((PPCSubTarget->hasP8Vector())) {
     764           0 :     return fastEmitInst_r(PPC::XSSQRTSP, &PPC::VSSRCRegClass, Op0, Op0IsKill);
     765             :   }
     766           0 :   return fastEmitInst_r(PPC::FSQRTS, &PPC::F4RCRegClass, Op0, Op0IsKill);
     767             : }
     768             : 
     769           0 : unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     770           0 :   if (RetVT.SimpleTy != MVT::f64)
     771             :     return 0;
     772           0 :   if ((PPCSubTarget->hasVSX())) {
     773           0 :     return fastEmitInst_r(PPC::XSSQRTDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     774             :   }
     775           0 :   return fastEmitInst_r(PPC::FSQRT, &PPC::F8RCRegClass, Op0, Op0IsKill);
     776             : }
     777             : 
     778             : unsigned fastEmit_ISD_FSQRT_MVT_f128_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     779           0 :   if (RetVT.SimpleTy != MVT::f128)
     780             :     return 0;
     781           0 :   if ((PPCSubTarget->hasP9Vector())) {
     782             :     return fastEmitInst_r(PPC::XSSQRTQP, &PPC::VRRCRegClass, Op0, Op0IsKill);
     783             :   }
     784             :   return 0;
     785             : }
     786             : 
     787             : unsigned fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     788           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     789             :     return 0;
     790           0 :   if ((PPCSubTarget->hasVSX())) {
     791             :     return fastEmitInst_r(PPC::XVSQRTSP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     792             :   }
     793             :   return 0;
     794             : }
     795             : 
     796             : unsigned fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     797           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     798             :     return 0;
     799           0 :   if ((PPCSubTarget->hasVSX())) {
     800             :     return fastEmitInst_r(PPC::XVSQRTDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     801             :   }
     802             :   return 0;
     803             : }
     804             : 
     805           0 : unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     806           0 :   switch (VT.SimpleTy) {
     807           0 :   case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill);
     808           0 :   case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0, Op0IsKill);
     809           0 :   case MVT::f128: return fastEmit_ISD_FSQRT_MVT_f128_r(RetVT, Op0, Op0IsKill);
     810           0 :   case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     811           0 :   case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     812             :   default: return 0;
     813             :   }
     814             : }
     815             : 
     816             : // FastEmit functions for ISD::FTRUNC.
     817             : 
     818             : unsigned fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     819           0 :   if (RetVT.SimpleTy != MVT::f32)
     820             :     return 0;
     821             :   return fastEmitInst_r(PPC::FRIZS, &PPC::F4RCRegClass, Op0, Op0IsKill);
     822             : }
     823             : 
     824           0 : unsigned fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     825           0 :   if (RetVT.SimpleTy != MVT::f64)
     826             :     return 0;
     827           0 :   if ((PPCSubTarget->hasVSX())) {
     828           0 :     return fastEmitInst_r(PPC::XSRDPIZ, &PPC::VSFRCRegClass, Op0, Op0IsKill);
     829             :   }
     830           0 :   return fastEmitInst_r(PPC::FRIZD, &PPC::F8RCRegClass, Op0, Op0IsKill);
     831             : }
     832             : 
     833           0 : unsigned fastEmit_ISD_FTRUNC_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     834           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     835             :     return 0;
     836           0 :   if ((PPCSubTarget->hasVSX())) {
     837           0 :     return fastEmitInst_r(PPC::XVRSPIZ, &PPC::VSRCRegClass, Op0, Op0IsKill);
     838             :   }
     839           0 :   if ((PPCSubTarget->hasAltivec())) {
     840           0 :     return fastEmitInst_r(PPC::VRFIZ, &PPC::VRRCRegClass, Op0, Op0IsKill);
     841             :   }
     842           0 :   if ((PPCSubTarget->hasQPX())) {
     843           0 :     return fastEmitInst_r(PPC::QVFRIZs, &PPC::QSRCRegClass, Op0, Op0IsKill);
     844             :   }
     845             :   return 0;
     846             : }
     847             : 
     848             : unsigned fastEmit_ISD_FTRUNC_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     849           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     850             :     return 0;
     851           0 :   if ((PPCSubTarget->hasVSX())) {
     852             :     return fastEmitInst_r(PPC::XVRDPIZ, &PPC::VSRCRegClass, Op0, Op0IsKill);
     853             :   }
     854             :   return 0;
     855             : }
     856             : 
     857             : unsigned fastEmit_ISD_FTRUNC_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     858           0 :   if (RetVT.SimpleTy != MVT::v4f64)
     859             :     return 0;
     860           0 :   if ((PPCSubTarget->hasQPX())) {
     861             :     return fastEmitInst_r(PPC::QVFRIZ, &PPC::QFRCRegClass, Op0, Op0IsKill);
     862             :   }
     863             :   return 0;
     864             : }
     865             : 
     866           0 : unsigned fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     867           0 :   switch (VT.SimpleTy) {
     868           0 :   case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0, Op0IsKill);
     869           0 :   case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0, Op0IsKill);
     870           0 :   case MVT::v4f32: return fastEmit_ISD_FTRUNC_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     871           0 :   case MVT::v2f64: return fastEmit_ISD_FTRUNC_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     872           0 :   case MVT::v4f64: return fastEmit_ISD_FTRUNC_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
     873             :   default: return 0;
     874             :   }
     875             : }
     876             : 
     877             : // FastEmit functions for ISD::SCALAR_TO_VECTOR.
     878             : 
     879             : unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     880           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     881             :     return 0;
     882           0 :   if ((PPCSubTarget->hasP9Vector())) {
     883             :     return fastEmitInst_r(PPC::MTVSRWS, &PPC::VSRCRegClass, Op0, Op0IsKill);
     884             :   }
     885             :   return 0;
     886             : }
     887             : 
     888           0 : unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     889           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     890             :     return 0;
     891           0 :   if ((PPCSubTarget->hasP8Vector()) && (!PPCSubTarget->isLittleEndian())) {
     892           0 :     return fastEmitInst_r(PPC::XSCVDPSPN, &PPC::VSRCRegClass, Op0, Op0IsKill);
     893             :   }
     894             :   return 0;
     895             : }
     896             : 
     897           0 : unsigned fastEmit_ISD_SCALAR_TO_VECTOR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     898           0 :   switch (VT.SimpleTy) {
     899           0 :   case MVT::i32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(RetVT, Op0, Op0IsKill);
     900           0 :   case MVT::f32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(RetVT, Op0, Op0IsKill);
     901             :   default: return 0;
     902             :   }
     903             : }
     904             : 
     905             : // FastEmit functions for ISD::SIGN_EXTEND.
     906             : 
     907             : unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     908           4 :   if (RetVT.SimpleTy != MVT::i64)
     909             :     return 0;
     910             :   return fastEmitInst_r(PPC::EXTSW_32_64, &PPC::G8RCRegClass, Op0, Op0IsKill);
     911             : }
     912             : 
     913             : unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     914           5 :   switch (VT.SimpleTy) {
     915           4 :   case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0, Op0IsKill);
     916             :   default: return 0;
     917             :   }
     918             : }
     919             : 
     920             : // FastEmit functions for ISD::SINT_TO_FP.
     921             : 
     922           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     923           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     924             :     return 0;
     925           0 :   if ((PPCSubTarget->hasVSX())) {
     926           0 :     return fastEmitInst_r(PPC::XVCVSXWSP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     927             :   }
     928           0 :   if ((PPCSubTarget->hasAltivec())) {
     929           0 :     return fastEmitInst_r(PPC::VCFSX_0, &PPC::VRRCRegClass, Op0, Op0IsKill);
     930             :   }
     931             :   return 0;
     932             : }
     933             : 
     934             : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     935           2 :   if (RetVT.SimpleTy != MVT::v2f64)
     936             :     return 0;
     937           2 :   if ((PPCSubTarget->hasVSX())) {
     938             :     return fastEmitInst_r(PPC::XVCVSXDDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     939             :   }
     940             :   return 0;
     941             : }
     942             : 
     943          16 : unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     944          16 :   switch (VT.SimpleTy) {
     945           0 :   case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     946           2 :   case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     947             :   default: return 0;
     948             :   }
     949             : }
     950             : 
     951             : // FastEmit functions for ISD::TRUNCATE.
     952             : 
     953             : unsigned fastEmit_ISD_TRUNCATE_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     954           0 :   if (RetVT.SimpleTy != MVT::i1)
     955             :     return 0;
     956             :   return fastEmitInst_r(PPC::ANDIo_1_GT_BIT, &PPC::CRBITRCRegClass, Op0, Op0IsKill);
     957             : }
     958             : 
     959             : unsigned fastEmit_ISD_TRUNCATE_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     960           0 :   if (RetVT.SimpleTy != MVT::i1)
     961             :     return 0;
     962             :   return fastEmitInst_r(PPC::ANDIo_1_GT_BIT8, &PPC::CRBITRCRegClass, Op0, Op0IsKill);
     963             : }
     964             : 
     965           0 : unsigned fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     966           0 :   switch (VT.SimpleTy) {
     967           0 :   case MVT::i32: return fastEmit_ISD_TRUNCATE_MVT_i32_r(RetVT, Op0, Op0IsKill);
     968           0 :   case MVT::i64: return fastEmit_ISD_TRUNCATE_MVT_i64_r(RetVT, Op0, Op0IsKill);
     969             :   default: return 0;
     970             :   }
     971             : }
     972             : 
     973             : // FastEmit functions for ISD::UINT_TO_FP.
     974             : 
     975           0 : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     976           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     977             :     return 0;
     978           0 :   if ((PPCSubTarget->hasVSX())) {
     979           0 :     return fastEmitInst_r(PPC::XVCVUXWSP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     980             :   }
     981           0 :   if ((PPCSubTarget->hasAltivec())) {
     982           0 :     return fastEmitInst_r(PPC::VCFUX_0, &PPC::VRRCRegClass, Op0, Op0IsKill);
     983             :   }
     984             :   return 0;
     985             : }
     986             : 
     987             : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     988           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     989             :     return 0;
     990           0 :   if ((PPCSubTarget->hasVSX())) {
     991             :     return fastEmitInst_r(PPC::XVCVUXDDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
     992             :   }
     993             :   return 0;
     994             : }
     995             : 
     996           0 : unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     997           0 :   switch (VT.SimpleTy) {
     998           0 :   case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     999           0 :   case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
    1000             :   default: return 0;
    1001             :   }
    1002             : }
    1003             : 
    1004             : // FastEmit functions for PPCISD::FCFID.
    1005             : 
    1006           0 : unsigned fastEmit_PPCISD_FCFID_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1007           0 :   if (RetVT.SimpleTy != MVT::f64)
    1008             :     return 0;
    1009           0 :   if ((PPCSubTarget->hasVSX())) {
    1010           0 :     return fastEmitInst_r(PPC::XSCVSXDDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1011             :   }
    1012           0 :   return fastEmitInst_r(PPC::FCFID, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1013             : }
    1014             : 
    1015             : unsigned fastEmit_PPCISD_FCFID_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1016           0 :   switch (VT.SimpleTy) {
    1017           0 :   case MVT::f64: return fastEmit_PPCISD_FCFID_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1018             :   default: return 0;
    1019             :   }
    1020             : }
    1021             : 
    1022             : // FastEmit functions for PPCISD::FCFIDS.
    1023             : 
    1024           0 : unsigned fastEmit_PPCISD_FCFIDS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1025           0 :   if (RetVT.SimpleTy != MVT::f32)
    1026             :     return 0;
    1027           0 :   if ((PPCSubTarget->hasP8Vector())) {
    1028           0 :     return fastEmitInst_r(PPC::XSCVSXDSP, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1029             :   }
    1030           0 :   return fastEmitInst_r(PPC::FCFIDS, &PPC::F4RCRegClass, Op0, Op0IsKill);
    1031             : }
    1032             : 
    1033             : unsigned fastEmit_PPCISD_FCFIDS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1034           0 :   switch (VT.SimpleTy) {
    1035           0 :   case MVT::f64: return fastEmit_PPCISD_FCFIDS_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1036             :   default: return 0;
    1037             :   }
    1038             : }
    1039             : 
    1040             : // FastEmit functions for PPCISD::FCFIDU.
    1041             : 
    1042           0 : unsigned fastEmit_PPCISD_FCFIDU_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1043           0 :   if (RetVT.SimpleTy != MVT::f64)
    1044             :     return 0;
    1045           0 :   if ((PPCSubTarget->hasVSX())) {
    1046           0 :     return fastEmitInst_r(PPC::XSCVUXDDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1047             :   }
    1048           0 :   return fastEmitInst_r(PPC::FCFIDU, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1049             : }
    1050             : 
    1051             : unsigned fastEmit_PPCISD_FCFIDU_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1052           0 :   switch (VT.SimpleTy) {
    1053           0 :   case MVT::f64: return fastEmit_PPCISD_FCFIDU_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1054             :   default: return 0;
    1055             :   }
    1056             : }
    1057             : 
    1058             : // FastEmit functions for PPCISD::FCFIDUS.
    1059             : 
    1060           0 : unsigned fastEmit_PPCISD_FCFIDUS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1061           0 :   if (RetVT.SimpleTy != MVT::f32)
    1062             :     return 0;
    1063           0 :   if ((PPCSubTarget->hasP8Vector())) {
    1064           0 :     return fastEmitInst_r(PPC::XSCVUXDSP, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1065             :   }
    1066           0 :   return fastEmitInst_r(PPC::FCFIDUS, &PPC::F4RCRegClass, Op0, Op0IsKill);
    1067             : }
    1068             : 
    1069             : unsigned fastEmit_PPCISD_FCFIDUS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1070           0 :   switch (VT.SimpleTy) {
    1071           0 :   case MVT::f64: return fastEmit_PPCISD_FCFIDUS_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1072             :   default: return 0;
    1073             :   }
    1074             : }
    1075             : 
    1076             : // FastEmit functions for PPCISD::FCTIDUZ.
    1077             : 
    1078             : unsigned fastEmit_PPCISD_FCTIDUZ_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1079           0 :   if (RetVT.SimpleTy != MVT::f32)
    1080             :     return 0;
    1081           0 :   if ((PPCSubTarget->hasVSX())) {
    1082             :     return fastEmitInst_r(PPC::XSCVDPUXDSs, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1083             :   }
    1084             :   return 0;
    1085             : }
    1086             : 
    1087           0 : unsigned fastEmit_PPCISD_FCTIDUZ_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1088           0 :   if (RetVT.SimpleTy != MVT::f64)
    1089             :     return 0;
    1090           0 :   if ((PPCSubTarget->hasVSX())) {
    1091           0 :     return fastEmitInst_r(PPC::XSCVDPUXDS, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1092             :   }
    1093           0 :   return fastEmitInst_r(PPC::FCTIDUZ, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1094             : }
    1095             : 
    1096           0 : unsigned fastEmit_PPCISD_FCTIDUZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1097           0 :   switch (VT.SimpleTy) {
    1098           0 :   case MVT::f32: return fastEmit_PPCISD_FCTIDUZ_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1099           0 :   case MVT::f64: return fastEmit_PPCISD_FCTIDUZ_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1100             :   default: return 0;
    1101             :   }
    1102             : }
    1103             : 
    1104             : // FastEmit functions for PPCISD::FCTIDZ.
    1105             : 
    1106             : unsigned fastEmit_PPCISD_FCTIDZ_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1107           0 :   if (RetVT.SimpleTy != MVT::f32)
    1108             :     return 0;
    1109           0 :   if ((PPCSubTarget->hasVSX())) {
    1110             :     return fastEmitInst_r(PPC::XSCVDPSXDSs, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1111             :   }
    1112             :   return 0;
    1113             : }
    1114             : 
    1115           0 : unsigned fastEmit_PPCISD_FCTIDZ_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1116           0 :   if (RetVT.SimpleTy != MVT::f64)
    1117             :     return 0;
    1118           0 :   if ((PPCSubTarget->hasVSX())) {
    1119           0 :     return fastEmitInst_r(PPC::XSCVDPSXDS, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1120             :   }
    1121           0 :   return fastEmitInst_r(PPC::FCTIDZ, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1122             : }
    1123             : 
    1124           0 : unsigned fastEmit_PPCISD_FCTIDZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1125           0 :   switch (VT.SimpleTy) {
    1126           0 :   case MVT::f32: return fastEmit_PPCISD_FCTIDZ_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1127           0 :   case MVT::f64: return fastEmit_PPCISD_FCTIDZ_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1128             :   default: return 0;
    1129             :   }
    1130             : }
    1131             : 
    1132             : // FastEmit functions for PPCISD::FCTIWUZ.
    1133             : 
    1134             : unsigned fastEmit_PPCISD_FCTIWUZ_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1135           0 :   if (RetVT.SimpleTy != MVT::f32)
    1136             :     return 0;
    1137           0 :   if ((PPCSubTarget->hasVSX())) {
    1138             :     return fastEmitInst_r(PPC::XSCVDPUXWSs, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1139             :   }
    1140             :   return 0;
    1141             : }
    1142             : 
    1143           0 : unsigned fastEmit_PPCISD_FCTIWUZ_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1144           0 :   if (RetVT.SimpleTy != MVT::f64)
    1145             :     return 0;
    1146           0 :   if ((PPCSubTarget->hasVSX())) {
    1147           0 :     return fastEmitInst_r(PPC::XSCVDPUXWS, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1148             :   }
    1149           0 :   return fastEmitInst_r(PPC::FCTIWUZ, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1150             : }
    1151             : 
    1152           0 : unsigned fastEmit_PPCISD_FCTIWUZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1153           0 :   switch (VT.SimpleTy) {
    1154           0 :   case MVT::f32: return fastEmit_PPCISD_FCTIWUZ_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1155           0 :   case MVT::f64: return fastEmit_PPCISD_FCTIWUZ_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1156             :   default: return 0;
    1157             :   }
    1158             : }
    1159             : 
    1160             : // FastEmit functions for PPCISD::FCTIWZ.
    1161             : 
    1162             : unsigned fastEmit_PPCISD_FCTIWZ_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1163           0 :   if (RetVT.SimpleTy != MVT::f32)
    1164             :     return 0;
    1165           0 :   if ((PPCSubTarget->hasVSX())) {
    1166             :     return fastEmitInst_r(PPC::XSCVDPSXWSs, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1167             :   }
    1168             :   return 0;
    1169             : }
    1170             : 
    1171           0 : unsigned fastEmit_PPCISD_FCTIWZ_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1172           0 :   if (RetVT.SimpleTy != MVT::f64)
    1173             :     return 0;
    1174           0 :   if ((PPCSubTarget->hasVSX())) {
    1175           0 :     return fastEmitInst_r(PPC::XSCVDPSXWS, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1176             :   }
    1177           0 :   return fastEmitInst_r(PPC::FCTIWZ, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1178             : }
    1179             : 
    1180           0 : unsigned fastEmit_PPCISD_FCTIWZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1181           0 :   switch (VT.SimpleTy) {
    1182           0 :   case MVT::f32: return fastEmit_PPCISD_FCTIWZ_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1183           0 :   case MVT::f64: return fastEmit_PPCISD_FCTIWZ_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1184             :   default: return 0;
    1185             :   }
    1186             : }
    1187             : 
    1188             : // FastEmit functions for PPCISD::FRE.
    1189             : 
    1190           0 : unsigned fastEmit_PPCISD_FRE_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1191           0 :   if (RetVT.SimpleTy != MVT::f32)
    1192             :     return 0;
    1193           0 :   if ((PPCSubTarget->hasP8Vector())) {
    1194           0 :     return fastEmitInst_r(PPC::XSRESP, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1195             :   }
    1196           0 :   return fastEmitInst_r(PPC::FRES, &PPC::F4RCRegClass, Op0, Op0IsKill);
    1197             : }
    1198             : 
    1199           0 : unsigned fastEmit_PPCISD_FRE_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1200           0 :   if (RetVT.SimpleTy != MVT::f64)
    1201             :     return 0;
    1202           0 :   if ((PPCSubTarget->hasVSX())) {
    1203           0 :     return fastEmitInst_r(PPC::XSREDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1204             :   }
    1205           0 :   return fastEmitInst_r(PPC::FRE, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1206             : }
    1207             : 
    1208           0 : unsigned fastEmit_PPCISD_FRE_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1209           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1210             :     return 0;
    1211           0 :   if ((PPCSubTarget->hasVSX())) {
    1212           0 :     return fastEmitInst_r(PPC::XVRESP, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1213             :   }
    1214           0 :   if ((PPCSubTarget->hasAltivec())) {
    1215           0 :     return fastEmitInst_r(PPC::VREFP, &PPC::VRRCRegClass, Op0, Op0IsKill);
    1216             :   }
    1217           0 :   if ((PPCSubTarget->hasQPX())) {
    1218           0 :     return fastEmitInst_r(PPC::QVFRESs, &PPC::QSRCRegClass, Op0, Op0IsKill);
    1219             :   }
    1220             :   return 0;
    1221             : }
    1222             : 
    1223             : unsigned fastEmit_PPCISD_FRE_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1224           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1225             :     return 0;
    1226           0 :   if ((PPCSubTarget->hasVSX())) {
    1227             :     return fastEmitInst_r(PPC::XVREDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1228             :   }
    1229             :   return 0;
    1230             : }
    1231             : 
    1232             : unsigned fastEmit_PPCISD_FRE_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1233           0 :   if (RetVT.SimpleTy != MVT::v4f64)
    1234             :     return 0;
    1235           0 :   if ((PPCSubTarget->hasQPX())) {
    1236             :     return fastEmitInst_r(PPC::QVFRE, &PPC::QFRCRegClass, Op0, Op0IsKill);
    1237             :   }
    1238             :   return 0;
    1239             : }
    1240             : 
    1241           0 : unsigned fastEmit_PPCISD_FRE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1242           0 :   switch (VT.SimpleTy) {
    1243           0 :   case MVT::f32: return fastEmit_PPCISD_FRE_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1244           0 :   case MVT::f64: return fastEmit_PPCISD_FRE_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1245           0 :   case MVT::v4f32: return fastEmit_PPCISD_FRE_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
    1246           0 :   case MVT::v2f64: return fastEmit_PPCISD_FRE_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
    1247           0 :   case MVT::v4f64: return fastEmit_PPCISD_FRE_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
    1248             :   default: return 0;
    1249             :   }
    1250             : }
    1251             : 
    1252             : // FastEmit functions for PPCISD::FRSQRTE.
    1253             : 
    1254           0 : unsigned fastEmit_PPCISD_FRSQRTE_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1255           0 :   if (RetVT.SimpleTy != MVT::f32)
    1256             :     return 0;
    1257           0 :   if ((PPCSubTarget->hasP8Vector())) {
    1258           0 :     return fastEmitInst_r(PPC::XSRSQRTESP, &PPC::VSSRCRegClass, Op0, Op0IsKill);
    1259             :   }
    1260           0 :   return fastEmitInst_r(PPC::FRSQRTES, &PPC::F4RCRegClass, Op0, Op0IsKill);
    1261             : }
    1262             : 
    1263           0 : unsigned fastEmit_PPCISD_FRSQRTE_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1264           0 :   if (RetVT.SimpleTy != MVT::f64)
    1265             :     return 0;
    1266           0 :   if ((PPCSubTarget->hasVSX())) {
    1267           0 :     return fastEmitInst_r(PPC::XSRSQRTEDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1268             :   }
    1269           0 :   return fastEmitInst_r(PPC::FRSQRTE, &PPC::F8RCRegClass, Op0, Op0IsKill);
    1270             : }
    1271             : 
    1272           0 : unsigned fastEmit_PPCISD_FRSQRTE_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1273           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1274             :     return 0;
    1275           0 :   if ((PPCSubTarget->hasVSX())) {
    1276           0 :     return fastEmitInst_r(PPC::XVRSQRTESP, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1277             :   }
    1278           0 :   if ((PPCSubTarget->hasAltivec())) {
    1279           0 :     return fastEmitInst_r(PPC::VRSQRTEFP, &PPC::VRRCRegClass, Op0, Op0IsKill);
    1280             :   }
    1281           0 :   if ((PPCSubTarget->hasQPX())) {
    1282           0 :     return fastEmitInst_r(PPC::QVFRSQRTESs, &PPC::QSRCRegClass, Op0, Op0IsKill);
    1283             :   }
    1284             :   return 0;
    1285             : }
    1286             : 
    1287             : unsigned fastEmit_PPCISD_FRSQRTE_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1288           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1289             :     return 0;
    1290           0 :   if ((PPCSubTarget->hasVSX())) {
    1291             :     return fastEmitInst_r(PPC::XVRSQRTEDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1292             :   }
    1293             :   return 0;
    1294             : }
    1295             : 
    1296             : unsigned fastEmit_PPCISD_FRSQRTE_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1297           0 :   if (RetVT.SimpleTy != MVT::v4f64)
    1298             :     return 0;
    1299           0 :   if ((PPCSubTarget->hasQPX())) {
    1300             :     return fastEmitInst_r(PPC::QVFRSQRTE, &PPC::QFRCRegClass, Op0, Op0IsKill);
    1301             :   }
    1302             :   return 0;
    1303             : }
    1304             : 
    1305           0 : unsigned fastEmit_PPCISD_FRSQRTE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1306           0 :   switch (VT.SimpleTy) {
    1307           0 :   case MVT::f32: return fastEmit_PPCISD_FRSQRTE_MVT_f32_r(RetVT, Op0, Op0IsKill);
    1308           0 :   case MVT::f64: return fastEmit_PPCISD_FRSQRTE_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1309           0 :   case MVT::v4f32: return fastEmit_PPCISD_FRSQRTE_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
    1310           0 :   case MVT::v2f64: return fastEmit_PPCISD_FRSQRTE_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
    1311           0 :   case MVT::v4f64: return fastEmit_PPCISD_FRSQRTE_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
    1312             :   default: return 0;
    1313             :   }
    1314             : }
    1315             : 
    1316             : // FastEmit functions for PPCISD::MFVSR.
    1317             : 
    1318             : unsigned fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i32_r(unsigned Op0, bool Op0IsKill) {
    1319           0 :   if ((PPCSubTarget->hasDirectMove())) {
    1320             :     return fastEmitInst_r(PPC::MFVSRWZ, &PPC::GPRCRegClass, Op0, Op0IsKill);
    1321             :   }
    1322             :   return 0;
    1323             : }
    1324             : 
    1325             : unsigned fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i64_r(unsigned Op0, bool Op0IsKill) {
    1326           0 :   if ((PPCSubTarget->hasDirectMove())) {
    1327             :     return fastEmitInst_r(PPC::MFVSRD, &PPC::G8RCRegClass, Op0, Op0IsKill);
    1328             :   }
    1329             :   return 0;
    1330             : }
    1331             : 
    1332           0 : unsigned fastEmit_PPCISD_MFVSR_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1333           0 : switch (RetVT.SimpleTy) {
    1334           0 :   case MVT::i32: return fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i32_r(Op0, Op0IsKill);
    1335           0 :   case MVT::i64: return fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i64_r(Op0, Op0IsKill);
    1336             :   default: return 0;
    1337             : }
    1338             : }
    1339             : 
    1340             : unsigned fastEmit_PPCISD_MFVSR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1341           0 :   switch (VT.SimpleTy) {
    1342           0 :   case MVT::f64: return fastEmit_PPCISD_MFVSR_MVT_f64_r(RetVT, Op0, Op0IsKill);
    1343             :   default: return 0;
    1344             :   }
    1345             : }
    1346             : 
    1347             : // FastEmit functions for PPCISD::MTCTR.
    1348             : 
    1349             : unsigned fastEmit_PPCISD_MTCTR_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1350           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    1351             :     return 0;
    1352             :   return fastEmitInst_r(PPC::MTCTR, &PPC::GPRCRegClass, Op0, Op0IsKill);
    1353             : }
    1354             : 
    1355             : unsigned fastEmit_PPCISD_MTCTR_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1356           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    1357             :     return 0;
    1358             :   return fastEmitInst_r(PPC::MTCTR8, &PPC::G8RCRegClass, Op0, Op0IsKill);
    1359             : }
    1360             : 
    1361           0 : unsigned fastEmit_PPCISD_MTCTR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1362           0 :   switch (VT.SimpleTy) {
    1363           0 :   case MVT::i32: return fastEmit_PPCISD_MTCTR_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1364           0 :   case MVT::i64: return fastEmit_PPCISD_MTCTR_MVT_i64_r(RetVT, Op0, Op0IsKill);
    1365             :   default: return 0;
    1366             :   }
    1367             : }
    1368             : 
    1369             : // FastEmit functions for PPCISD::MTVSRA.
    1370             : 
    1371             : unsigned fastEmit_PPCISD_MTVSRA_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1372           0 :   if (RetVT.SimpleTy != MVT::f64)
    1373             :     return 0;
    1374           0 :   if ((PPCSubTarget->hasDirectMove())) {
    1375             :     return fastEmitInst_r(PPC::MTVSRWA, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1376             :   }
    1377             :   return 0;
    1378             : }
    1379             : 
    1380             : unsigned fastEmit_PPCISD_MTVSRA_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1381           0 :   if (RetVT.SimpleTy != MVT::f64)
    1382             :     return 0;
    1383           0 :   if ((PPCSubTarget->hasDirectMove())) {
    1384             :     return fastEmitInst_r(PPC::MTVSRD, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1385             :   }
    1386             :   return 0;
    1387             : }
    1388             : 
    1389           0 : unsigned fastEmit_PPCISD_MTVSRA_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1390           0 :   switch (VT.SimpleTy) {
    1391           0 :   case MVT::i32: return fastEmit_PPCISD_MTVSRA_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1392           0 :   case MVT::i64: return fastEmit_PPCISD_MTVSRA_MVT_i64_r(RetVT, Op0, Op0IsKill);
    1393             :   default: return 0;
    1394             :   }
    1395             : }
    1396             : 
    1397             : // FastEmit functions for PPCISD::MTVSRZ.
    1398             : 
    1399             : unsigned fastEmit_PPCISD_MTVSRZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1400           0 :   if (RetVT.SimpleTy != MVT::f64)
    1401             :     return 0;
    1402           0 :   if ((PPCSubTarget->hasDirectMove())) {
    1403             :     return fastEmitInst_r(PPC::MTVSRWZ, &PPC::VSFRCRegClass, Op0, Op0IsKill);
    1404             :   }
    1405             :   return 0;
    1406             : }
    1407             : 
    1408           0 : unsigned fastEmit_PPCISD_MTVSRZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1409           0 :   switch (VT.SimpleTy) {
    1410           0 :   case MVT::i32: return fastEmit_PPCISD_MTVSRZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
    1411             :   default: return 0;
    1412             :   }
    1413             : }
    1414             : 
    1415             : // FastEmit functions for PPCISD::SExtVElems.
    1416             : 
    1417             : unsigned fastEmit_PPCISD_SExtVElems_MVT_v16i8_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
    1418           0 :   if ((PPCSubTarget->hasP9Altivec())) {
    1419             :     return fastEmitInst_r(PPC::VEXTSB2W, &PPC::VRRCRegClass, Op0, Op0IsKill);
    1420             :   }
    1421             :   return 0;
    1422             : }
    1423             : 
    1424             : unsigned fastEmit_PPCISD_SExtVElems_MVT_v16i8_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
    1425           0 :   if ((PPCSubTarget->hasP9Altivec())) {
    1426             :     return fastEmitInst_r(PPC::VEXTSB2D, &PPC::VRRCRegClass, Op0, Op0IsKill);
    1427             :   }
    1428             :   return 0;
    1429             : }
    1430             : 
    1431           0 : unsigned fastEmit_PPCISD_SExtVElems_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1432           0 : switch (RetVT.SimpleTy) {
    1433           0 :   case MVT::v4i32: return fastEmit_PPCISD_SExtVElems_MVT_v16i8_MVT_v4i32_r(Op0, Op0IsKill);
    1434           0 :   case MVT::v2i64: return fastEmit_PPCISD_SExtVElems_MVT_v16i8_MVT_v2i64_r(Op0, Op0IsKill);
    1435             :   default: return 0;
    1436             : }
    1437             : }
    1438             : 
    1439             : unsigned fastEmit_PPCISD_SExtVElems_MVT_v8i16_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
    1440           0 :   if ((PPCSubTarget->hasP9Altivec())) {
    1441             :     return fastEmitInst_r(PPC::VEXTSH2W, &PPC::VRRCRegClass, Op0, Op0IsKill);
    1442             :   }
    1443             :   return 0;
    1444             : }
    1445             : 
    1446             : unsigned fastEmit_PPCISD_SExtVElems_MVT_v8i16_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
    1447           0 :   if ((PPCSubTarget->hasP9Altivec())) {
    1448             :     return fastEmitInst_r(PPC::VEXTSH2D, &PPC::VRRCRegClass, Op0, Op0IsKill);
    1449             :   }
    1450             :   return 0;
    1451             : }
    1452             : 
    1453           0 : unsigned fastEmit_PPCISD_SExtVElems_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1454           0 : switch (RetVT.SimpleTy) {
    1455           0 :   case MVT::v4i32: return fastEmit_PPCISD_SExtVElems_MVT_v8i16_MVT_v4i32_r(Op0, Op0IsKill);
    1456           0 :   case MVT::v2i64: return fastEmit_PPCISD_SExtVElems_MVT_v8i16_MVT_v2i64_r(Op0, Op0IsKill);
    1457             :   default: return 0;
    1458             : }
    1459             : }
    1460             : 
    1461             : unsigned fastEmit_PPCISD_SExtVElems_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1462           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1463             :     return 0;
    1464           0 :   if ((PPCSubTarget->hasP9Altivec())) {
    1465             :     return fastEmitInst_r(PPC::VEXTSW2D, &PPC::VRRCRegClass, Op0, Op0IsKill);
    1466             :   }
    1467             :   return 0;
    1468             : }
    1469             : 
    1470           0 : unsigned fastEmit_PPCISD_SExtVElems_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1471           0 :   switch (VT.SimpleTy) {
    1472           0 :   case MVT::v16i8: return fastEmit_PPCISD_SExtVElems_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
    1473           0 :   case MVT::v8i16: return fastEmit_PPCISD_SExtVElems_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
    1474           0 :   case MVT::v4i32: return fastEmit_PPCISD_SExtVElems_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    1475             :   default: return 0;
    1476             :   }
    1477             : }
    1478             : 
    1479             : // FastEmit functions for PPCISD::XXREVERSE.
    1480             : 
    1481             : unsigned fastEmit_PPCISD_XXREVERSE_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1482           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1483             :     return 0;
    1484           0 :   if ((PPCSubTarget->hasP9Vector())) {
    1485             :     return fastEmitInst_r(PPC::XXBRW, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1486             :   }
    1487             :   return 0;
    1488             : }
    1489             : 
    1490             : unsigned fastEmit_PPCISD_XXREVERSE_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1491           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1492             :     return 0;
    1493           0 :   if ((PPCSubTarget->hasP9Vector())) {
    1494             :     return fastEmitInst_r(PPC::XXBRD, &PPC::VSRCRegClass, Op0, Op0IsKill);
    1495             :   }
    1496             :   return 0;
    1497             : }
    1498             : 
    1499           0 : unsigned fastEmit_PPCISD_XXREVERSE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
    1500           0 :   switch (VT.SimpleTy) {
    1501           0 :   case MVT::v4i32: return fastEmit_PPCISD_XXREVERSE_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
    1502           0 :   case MVT::v2i64: return fastEmit_PPCISD_XXREVERSE_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
    1503             :   default: return 0;
    1504             :   }
    1505             : }
    1506             : 
    1507             : // Top-level FastEmit function.
    1508             : 
    1509          45 : unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill) override {
    1510          45 :   switch (Opcode) {
    1511           2 :   case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0, Op0IsKill);
    1512           0 :   case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill);
    1513           0 :   case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill);
    1514           0 :   case ISD::CTTZ: return fastEmit_ISD_CTTZ_r(VT, RetVT, Op0, Op0IsKill);
    1515           0 :   case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill);
    1516           0 :   case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0, Op0IsKill);
    1517           0 :   case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0, Op0IsKill);
    1518           0 :   case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0, Op0IsKill);
    1519           0 :   case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill);
    1520           0 :   case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
    1521           0 :   case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill);
    1522          20 :   case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill);
    1523           0 :   case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill);
    1524           0 :   case ISD::FROUND: return fastEmit_ISD_FROUND_r(VT, RetVT, Op0, Op0IsKill);
    1525           0 :   case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill);
    1526           0 :   case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0, Op0IsKill);
    1527           0 :   case ISD::SCALAR_TO_VECTOR: return fastEmit_ISD_SCALAR_TO_VECTOR_r(VT, RetVT, Op0, Op0IsKill);
    1528           5 :   case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
    1529          16 :   case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill);
    1530           0 :   case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0, Op0IsKill);
    1531           0 :   case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill);
    1532           0 :   case PPCISD::FCFID: return fastEmit_PPCISD_FCFID_r(VT, RetVT, Op0, Op0IsKill);
    1533           0 :   case PPCISD::FCFIDS: return fastEmit_PPCISD_FCFIDS_r(VT, RetVT, Op0, Op0IsKill);
    1534           0 :   case PPCISD::FCFIDU: return fastEmit_PPCISD_FCFIDU_r(VT, RetVT, Op0, Op0IsKill);
    1535           0 :   case PPCISD::FCFIDUS: return fastEmit_PPCISD_FCFIDUS_r(VT, RetVT, Op0, Op0IsKill);
    1536           0 :   case PPCISD::FCTIDUZ: return fastEmit_PPCISD_FCTIDUZ_r(VT, RetVT, Op0, Op0IsKill);
    1537           0 :   case PPCISD::FCTIDZ: return fastEmit_PPCISD_FCTIDZ_r(VT, RetVT, Op0, Op0IsKill);
    1538           0 :   case PPCISD::FCTIWUZ: return fastEmit_PPCISD_FCTIWUZ_r(VT, RetVT, Op0, Op0IsKill);
    1539           0 :   case PPCISD::FCTIWZ: return fastEmit_PPCISD_FCTIWZ_r(VT, RetVT, Op0, Op0IsKill);
    1540           0 :   case PPCISD::FRE: return fastEmit_PPCISD_FRE_r(VT, RetVT, Op0, Op0IsKill);
    1541           0 :   case PPCISD::FRSQRTE: return fastEmit_PPCISD_FRSQRTE_r(VT, RetVT, Op0, Op0IsKill);
    1542           0 :   case PPCISD::MFVSR: return fastEmit_PPCISD_MFVSR_r(VT, RetVT, Op0, Op0IsKill);
    1543           0 :   case PPCISD::MTCTR: return fastEmit_PPCISD_MTCTR_r(VT, RetVT, Op0, Op0IsKill);
    1544           0 :   case PPCISD::MTVSRA: return fastEmit_PPCISD_MTVSRA_r(VT, RetVT, Op0, Op0IsKill);
    1545           0 :   case PPCISD::MTVSRZ: return fastEmit_PPCISD_MTVSRZ_r(VT, RetVT, Op0, Op0IsKill);
    1546           0 :   case PPCISD::SExtVElems: return fastEmit_PPCISD_SExtVElems_r(VT, RetVT, Op0, Op0IsKill);
    1547           0 :   case PPCISD::XXREVERSE: return fastEmit_PPCISD_XXREVERSE_r(VT, RetVT, Op0, Op0IsKill);
    1548             :   default: return 0;
    1549             :   }
    1550             : }
    1551             : 
    1552             : // FastEmit functions for ISD::ADD.
    1553             : 
    1554             : unsigned fastEmit_ISD_ADD_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1555           0 :   if (RetVT.SimpleTy != MVT::i1)
    1556             :     return 0;
    1557             :   return fastEmitInst_rr(PPC::CRXOR, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1558             : }
    1559             : 
    1560             : unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1561           0 :   if (RetVT.SimpleTy != MVT::i32)
    1562             :     return 0;
    1563             :   return fastEmitInst_rr(PPC::ADD4, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1564             : }
    1565             : 
    1566             : unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1567           0 :   if (RetVT.SimpleTy != MVT::i64)
    1568             :     return 0;
    1569             :   return fastEmitInst_rr(PPC::ADD8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1570             : }
    1571             : 
    1572             : unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1573           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    1574             :     return 0;
    1575           0 :   if ((PPCSubTarget->hasAltivec())) {
    1576             :     return fastEmitInst_rr(PPC::VADDUBM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1577             :   }
    1578             :   return 0;
    1579             : }
    1580             : 
    1581             : unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1582           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    1583             :     return 0;
    1584           0 :   if ((PPCSubTarget->hasAltivec())) {
    1585             :     return fastEmitInst_rr(PPC::VADDUHM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1586             :   }
    1587             :   return 0;
    1588             : }
    1589             : 
    1590             : unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1591           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    1592             :     return 0;
    1593           0 :   if ((PPCSubTarget->hasAltivec())) {
    1594             :     return fastEmitInst_rr(PPC::VADDUWM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1595             :   }
    1596             :   return 0;
    1597             : }
    1598             : 
    1599             : unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1600           2 :   if (RetVT.SimpleTy != MVT::v2i64)
    1601             :     return 0;
    1602           2 :   if ((PPCSubTarget->hasP8Altivec())) {
    1603             :     return fastEmitInst_rr(PPC::VADDUDM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1604             :   }
    1605             :   return 0;
    1606             : }
    1607             : 
    1608             : unsigned fastEmit_ISD_ADD_MVT_v1i128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1609           0 :   if (RetVT.SimpleTy != MVT::v1i128)
    1610             :     return 0;
    1611           0 :   if ((PPCSubTarget->hasP8Altivec())) {
    1612             :     return fastEmitInst_rr(PPC::VADDUQM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1613             :   }
    1614             :   return 0;
    1615             : }
    1616             : 
    1617           2 : unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1618           2 :   switch (VT.SimpleTy) {
    1619           0 :   case MVT::i1: return fastEmit_ISD_ADD_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1620           0 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1621           0 :   case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1622           0 :   case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1623           0 :   case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1624           0 :   case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1625           2 :   case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1626           0 :   case MVT::v1i128: return fastEmit_ISD_ADD_MVT_v1i128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1627             :   default: return 0;
    1628             :   }
    1629             : }
    1630             : 
    1631             : // FastEmit functions for ISD::ADDC.
    1632             : 
    1633             : unsigned fastEmit_ISD_ADDC_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1634           0 :   if (RetVT.SimpleTy != MVT::i32)
    1635             :     return 0;
    1636             :   return fastEmitInst_rr(PPC::ADDC, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1637             : }
    1638             : 
    1639             : unsigned fastEmit_ISD_ADDC_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1640           0 :   if (RetVT.SimpleTy != MVT::i64)
    1641             :     return 0;
    1642             :   return fastEmitInst_rr(PPC::ADDC8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1643             : }
    1644             : 
    1645           0 : unsigned fastEmit_ISD_ADDC_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1646           0 :   switch (VT.SimpleTy) {
    1647           0 :   case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1648           0 :   case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1649             :   default: return 0;
    1650             :   }
    1651             : }
    1652             : 
    1653             : // FastEmit functions for ISD::ADDE.
    1654             : 
    1655             : unsigned fastEmit_ISD_ADDE_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1656           0 :   if (RetVT.SimpleTy != MVT::i32)
    1657             :     return 0;
    1658             :   return fastEmitInst_rr(PPC::ADDE, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1659             : }
    1660             : 
    1661             : unsigned fastEmit_ISD_ADDE_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1662           0 :   if (RetVT.SimpleTy != MVT::i64)
    1663             :     return 0;
    1664             :   return fastEmitInst_rr(PPC::ADDE8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1665             : }
    1666             : 
    1667           0 : unsigned fastEmit_ISD_ADDE_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1668           0 :   switch (VT.SimpleTy) {
    1669           0 :   case MVT::i32: return fastEmit_ISD_ADDE_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1670           0 :   case MVT::i64: return fastEmit_ISD_ADDE_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1671             :   default: return 0;
    1672             :   }
    1673             : }
    1674             : 
    1675             : // FastEmit functions for ISD::AND.
    1676             : 
    1677             : unsigned fastEmit_ISD_AND_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1678           0 :   if (RetVT.SimpleTy != MVT::i1)
    1679             :     return 0;
    1680             :   return fastEmitInst_rr(PPC::CRAND, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1681             : }
    1682             : 
    1683             : unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1684           0 :   if (RetVT.SimpleTy != MVT::i32)
    1685             :     return 0;
    1686             :   return fastEmitInst_rr(PPC::AND, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1687             : }
    1688             : 
    1689             : unsigned fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1690           1 :   if (RetVT.SimpleTy != MVT::i64)
    1691             :     return 0;
    1692             :   return fastEmitInst_rr(PPC::AND8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1693             : }
    1694             : 
    1695           4 : unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1696           4 :   if (RetVT.SimpleTy != MVT::v4i32)
    1697             :     return 0;
    1698           4 :   if ((PPCSubTarget->hasVSX())) {
    1699           8 :     return fastEmitInst_rr(PPC::XXLAND, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1700             :   }
    1701           0 :   if ((PPCSubTarget->hasAltivec())) {
    1702           0 :     return fastEmitInst_rr(PPC::VAND, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1703             :   }
    1704             :   return 0;
    1705             : }
    1706             : 
    1707          15 : unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1708          15 :   switch (VT.SimpleTy) {
    1709           0 :   case MVT::i1: return fastEmit_ISD_AND_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1710           0 :   case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1711           1 :   case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1712           4 :   case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1713             :   default: return 0;
    1714             :   }
    1715             : }
    1716             : 
    1717             : // FastEmit functions for ISD::BUILD_VECTOR.
    1718             : 
    1719           0 : unsigned fastEmit_ISD_BUILD_VECTOR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1720           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    1721             :     return 0;
    1722           0 :   if ((PPCSubTarget->hasDirectMove()) && (!PPCSubTarget->isLittleEndian()) && (PPCSubTarget->isISA3_0())) {
    1723           0 :     return fastEmitInst_rr(PPC::MTVSRDD, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1724             :   }
    1725             :   return 0;
    1726             : }
    1727             : 
    1728             : unsigned fastEmit_ISD_BUILD_VECTOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1729           0 :   switch (VT.SimpleTy) {
    1730           0 :   case MVT::i64: return fastEmit_ISD_BUILD_VECTOR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1731             :   default: return 0;
    1732             :   }
    1733             : }
    1734             : 
    1735             : // FastEmit functions for ISD::FADD.
    1736             : 
    1737           2 : unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1738           2 :   if (RetVT.SimpleTy != MVT::f32)
    1739             :     return 0;
    1740           2 :   if ((PPCSubTarget->hasP8Vector())) {
    1741           0 :     return fastEmitInst_rr(PPC::XSADDSP, &PPC::VSSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1742             :   }
    1743           4 :   return fastEmitInst_rr(PPC::FADDS, &PPC::F4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1744             : }
    1745             : 
    1746          10 : unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1747          10 :   if (RetVT.SimpleTy != MVT::f64)
    1748             :     return 0;
    1749          10 :   if ((PPCSubTarget->hasVSX())) {
    1750          16 :     return fastEmitInst_rr(PPC::XSADDDP, &PPC::VSFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1751             :   }
    1752           4 :   return fastEmitInst_rr(PPC::FADD, &PPC::F8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1753             : }
    1754             : 
    1755             : unsigned fastEmit_ISD_FADD_MVT_f128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1756           0 :   if (RetVT.SimpleTy != MVT::f128)
    1757             :     return 0;
    1758           0 :   if ((PPCSubTarget->hasP9Vector())) {
    1759             :     return fastEmitInst_rr(PPC::XSADDQP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1760             :   }
    1761             :   return 0;
    1762             : }
    1763             : 
    1764           0 : unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1765           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1766             :     return 0;
    1767           0 :   if ((PPCSubTarget->hasVSX())) {
    1768           0 :     return fastEmitInst_rr(PPC::XVADDSP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1769             :   }
    1770           0 :   if ((PPCSubTarget->hasQPX())) {
    1771           0 :     return fastEmitInst_rr(PPC::QVFADDSs, &PPC::QSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1772             :   }
    1773           0 :   if ((PPCSubTarget->hasAltivec())) {
    1774           0 :     return fastEmitInst_rr(PPC::VADDFP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1775             :   }
    1776             :   return 0;
    1777             : }
    1778             : 
    1779             : unsigned fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1780           2 :   if (RetVT.SimpleTy != MVT::v2f64)
    1781             :     return 0;
    1782           2 :   if ((PPCSubTarget->hasVSX())) {
    1783             :     return fastEmitInst_rr(PPC::XVADDDP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1784             :   }
    1785             :   return 0;
    1786             : }
    1787             : 
    1788             : unsigned fastEmit_ISD_FADD_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1789           0 :   if (RetVT.SimpleTy != MVT::v4f64)
    1790             :     return 0;
    1791           0 :   if ((PPCSubTarget->hasQPX())) {
    1792             :     return fastEmitInst_rr(PPC::QVFADD, &PPC::QFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1793             :   }
    1794             :   return 0;
    1795             : }
    1796             : 
    1797          14 : unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1798          14 :   switch (VT.SimpleTy) {
    1799           2 :   case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1800          10 :   case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1801           0 :   case MVT::f128: return fastEmit_ISD_FADD_MVT_f128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1802           0 :   case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1803           2 :   case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1804           0 :   case MVT::v4f64: return fastEmit_ISD_FADD_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1805             :   default: return 0;
    1806             :   }
    1807             : }
    1808             : 
    1809             : // FastEmit functions for ISD::FDIV.
    1810             : 
    1811           0 : unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1812           0 :   if (RetVT.SimpleTy != MVT::f32)
    1813             :     return 0;
    1814           0 :   if ((PPCSubTarget->hasP8Vector())) {
    1815           0 :     return fastEmitInst_rr(PPC::XSDIVSP, &PPC::VSSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1816             :   }
    1817           0 :   return fastEmitInst_rr(PPC::FDIVS, &PPC::F4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1818             : }
    1819             : 
    1820           2 : unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1821           2 :   if (RetVT.SimpleTy != MVT::f64)
    1822             :     return 0;
    1823           2 :   if ((PPCSubTarget->hasVSX())) {
    1824           4 :     return fastEmitInst_rr(PPC::XSDIVDP, &PPC::VSFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1825             :   }
    1826           0 :   return fastEmitInst_rr(PPC::FDIV, &PPC::F8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1827             : }
    1828             : 
    1829             : unsigned fastEmit_ISD_FDIV_MVT_f128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1830           0 :   if (RetVT.SimpleTy != MVT::f128)
    1831             :     return 0;
    1832           0 :   if ((PPCSubTarget->hasP9Vector())) {
    1833             :     return fastEmitInst_rr(PPC::XSDIVQP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1834             :   }
    1835             :   return 0;
    1836             : }
    1837             : 
    1838             : unsigned fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1839           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1840             :     return 0;
    1841           0 :   if ((PPCSubTarget->hasVSX())) {
    1842             :     return fastEmitInst_rr(PPC::XVDIVSP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1843             :   }
    1844             :   return 0;
    1845             : }
    1846             : 
    1847             : unsigned fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1848           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1849             :     return 0;
    1850           0 :   if ((PPCSubTarget->hasVSX())) {
    1851             :     return fastEmitInst_rr(PPC::XVDIVDP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1852             :   }
    1853             :   return 0;
    1854             : }
    1855             : 
    1856           2 : unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1857           2 :   switch (VT.SimpleTy) {
    1858           0 :   case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1859           2 :   case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1860           0 :   case MVT::f128: return fastEmit_ISD_FDIV_MVT_f128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1861           0 :   case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1862           0 :   case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1863             :   default: return 0;
    1864             :   }
    1865             : }
    1866             : 
    1867             : // FastEmit functions for ISD::FMUL.
    1868             : 
    1869           0 : unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1870           0 :   if (RetVT.SimpleTy != MVT::f32)
    1871             :     return 0;
    1872           0 :   if ((PPCSubTarget->hasP8Vector())) {
    1873           0 :     return fastEmitInst_rr(PPC::XSMULSP, &PPC::VSSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1874             :   }
    1875           0 :   return fastEmitInst_rr(PPC::FMULS, &PPC::F4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1876             : }
    1877             : 
    1878           2 : unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1879           2 :   if (RetVT.SimpleTy != MVT::f64)
    1880             :     return 0;
    1881           2 :   if ((PPCSubTarget->hasVSX())) {
    1882           4 :     return fastEmitInst_rr(PPC::XSMULDP, &PPC::VSFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1883             :   }
    1884           0 :   return fastEmitInst_rr(PPC::FMUL, &PPC::F8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1885             : }
    1886             : 
    1887             : unsigned fastEmit_ISD_FMUL_MVT_f128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1888           0 :   if (RetVT.SimpleTy != MVT::f128)
    1889             :     return 0;
    1890           0 :   if ((PPCSubTarget->hasP9Vector())) {
    1891             :     return fastEmitInst_rr(PPC::XSMULQP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1892             :   }
    1893             :   return 0;
    1894             : }
    1895             : 
    1896           0 : unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1897           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1898             :     return 0;
    1899           0 :   if ((PPCSubTarget->hasVSX())) {
    1900           0 :     return fastEmitInst_rr(PPC::XVMULSP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1901             :   }
    1902           0 :   if ((PPCSubTarget->hasQPX())) {
    1903           0 :     return fastEmitInst_rr(PPC::QVFMULSs, &PPC::QSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1904             :   }
    1905             :   return 0;
    1906             : }
    1907             : 
    1908             : unsigned fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1909           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1910             :     return 0;
    1911           0 :   if ((PPCSubTarget->hasVSX())) {
    1912             :     return fastEmitInst_rr(PPC::XVMULDP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1913             :   }
    1914             :   return 0;
    1915             : }
    1916             : 
    1917             : unsigned fastEmit_ISD_FMUL_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1918           0 :   if (RetVT.SimpleTy != MVT::v4f64)
    1919             :     return 0;
    1920           0 :   if ((PPCSubTarget->hasQPX())) {
    1921             :     return fastEmitInst_rr(PPC::QVFMUL, &PPC::QFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1922             :   }
    1923             :   return 0;
    1924             : }
    1925             : 
    1926           2 : unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1927           2 :   switch (VT.SimpleTy) {
    1928           0 :   case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1929           2 :   case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1930           0 :   case MVT::f128: return fastEmit_ISD_FMUL_MVT_f128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1931           0 :   case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1932           0 :   case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1933           0 :   case MVT::v4f64: return fastEmit_ISD_FMUL_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1934             :   default: return 0;
    1935             :   }
    1936             : }
    1937             : 
    1938             : // FastEmit functions for ISD::FSUB.
    1939             : 
    1940           0 : unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1941           0 :   if (RetVT.SimpleTy != MVT::f32)
    1942             :     return 0;
    1943           0 :   if ((PPCSubTarget->hasP8Vector())) {
    1944           0 :     return fastEmitInst_rr(PPC::XSSUBSP, &PPC::VSSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1945             :   }
    1946           0 :   return fastEmitInst_rr(PPC::FSUBS, &PPC::F4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1947             : }
    1948             : 
    1949           0 : unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1950           0 :   if (RetVT.SimpleTy != MVT::f64)
    1951             :     return 0;
    1952           0 :   if ((PPCSubTarget->hasVSX())) {
    1953           0 :     return fastEmitInst_rr(PPC::XSSUBDP, &PPC::VSFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1954             :   }
    1955           0 :   return fastEmitInst_rr(PPC::FSUB, &PPC::F8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1956             : }
    1957             : 
    1958             : unsigned fastEmit_ISD_FSUB_MVT_f128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1959           0 :   if (RetVT.SimpleTy != MVT::f128)
    1960             :     return 0;
    1961           0 :   if ((PPCSubTarget->hasP9Vector())) {
    1962             :     return fastEmitInst_rr(PPC::XSSUBQP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1963             :   }
    1964             :   return 0;
    1965             : }
    1966             : 
    1967           0 : unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1968           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1969             :     return 0;
    1970           0 :   if ((PPCSubTarget->hasVSX())) {
    1971           0 :     return fastEmitInst_rr(PPC::XVSUBSP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1972             :   }
    1973           0 :   if ((PPCSubTarget->hasQPX())) {
    1974           0 :     return fastEmitInst_rr(PPC::QVFSUBSs, &PPC::QSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1975             :   }
    1976           0 :   if ((PPCSubTarget->hasAltivec())) {
    1977           0 :     return fastEmitInst_rr(PPC::VSUBFP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1978             :   }
    1979             :   return 0;
    1980             : }
    1981             : 
    1982             : unsigned fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1983           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1984             :     return 0;
    1985           0 :   if ((PPCSubTarget->hasVSX())) {
    1986             :     return fastEmitInst_rr(PPC::XVSUBDP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1987             :   }
    1988             :   return 0;
    1989             : }
    1990             : 
    1991             : unsigned fastEmit_ISD_FSUB_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1992           0 :   if (RetVT.SimpleTy != MVT::v4f64)
    1993             :     return 0;
    1994           0 :   if ((PPCSubTarget->hasQPX())) {
    1995             :     return fastEmitInst_rr(PPC::QVFSUB, &PPC::QFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1996             :   }
    1997             :   return 0;
    1998             : }
    1999             : 
    2000           0 : unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2001           0 :   switch (VT.SimpleTy) {
    2002           0 :   case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2003           0 :   case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2004           0 :   case MVT::f128: return fastEmit_ISD_FSUB_MVT_f128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2005           0 :   case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2006           0 :   case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2007           0 :   case MVT::v4f64: return fastEmit_ISD_FSUB_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2008             :   default: return 0;
    2009             :   }
    2010             : }
    2011             : 
    2012             : // FastEmit functions for ISD::MUL.
    2013             : 
    2014             : unsigned fastEmit_ISD_MUL_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2015           0 :   if (RetVT.SimpleTy != MVT::i1)
    2016             :     return 0;
    2017             :   return fastEmitInst_rr(PPC::CRAND, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2018             : }
    2019             : 
    2020             : unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2021           0 :   if (RetVT.SimpleTy != MVT::i32)
    2022             :     return 0;
    2023             :   return fastEmitInst_rr(PPC::MULLW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2024             : }
    2025             : 
    2026             : unsigned fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2027           0 :   if (RetVT.SimpleTy != MVT::i64)
    2028             :     return 0;
    2029             :   return fastEmitInst_rr(PPC::MULLD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2030             : }
    2031             : 
    2032             : unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2033           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2034             :     return 0;
    2035           0 :   if ((PPCSubTarget->hasP8Altivec())) {
    2036             :     return fastEmitInst_rr(PPC::VMULUWM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2037             :   }
    2038             :   return 0;
    2039             : }
    2040             : 
    2041           0 : unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2042           0 :   switch (VT.SimpleTy) {
    2043           0 :   case MVT::i1: return fastEmit_ISD_MUL_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2044           0 :   case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2045           0 :   case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2046           0 :   case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2047             :   default: return 0;
    2048             :   }
    2049             : }
    2050             : 
    2051             : // FastEmit functions for ISD::MULHS.
    2052             : 
    2053             : unsigned fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2054           0 :   if (RetVT.SimpleTy != MVT::i32)
    2055             :     return 0;
    2056             :   return fastEmitInst_rr(PPC::MULHW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2057             : }
    2058             : 
    2059             : unsigned fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2060           0 :   if (RetVT.SimpleTy != MVT::i64)
    2061             :     return 0;
    2062             :   return fastEmitInst_rr(PPC::MULHD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2063             : }
    2064             : 
    2065           0 : unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2066           0 :   switch (VT.SimpleTy) {
    2067           0 :   case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2068           0 :   case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2069             :   default: return 0;
    2070             :   }
    2071             : }
    2072             : 
    2073             : // FastEmit functions for ISD::MULHU.
    2074             : 
    2075             : unsigned fastEmit_ISD_MULHU_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2076           0 :   if (RetVT.SimpleTy != MVT::i32)
    2077             :     return 0;
    2078             :   return fastEmitInst_rr(PPC::MULHWU, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2079             : }
    2080             : 
    2081             : unsigned fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2082           0 :   if (RetVT.SimpleTy != MVT::i64)
    2083             :     return 0;
    2084             :   return fastEmitInst_rr(PPC::MULHDU, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2085             : }
    2086             : 
    2087           0 : unsigned fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2088           0 :   switch (VT.SimpleTy) {
    2089           0 :   case MVT::i32: return fastEmit_ISD_MULHU_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2090           0 :   case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2091             :   default: return 0;
    2092             :   }
    2093             : }
    2094             : 
    2095             : // FastEmit functions for ISD::OR.
    2096             : 
    2097             : unsigned fastEmit_ISD_OR_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2098           0 :   if (RetVT.SimpleTy != MVT::i1)
    2099             :     return 0;
    2100             :   return fastEmitInst_rr(PPC::CROR, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2101             : }
    2102             : 
    2103             : unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2104           0 :   if (RetVT.SimpleTy != MVT::i32)
    2105             :     return 0;
    2106             :   return fastEmitInst_rr(PPC::OR, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2107             : }
    2108             : 
    2109             : unsigned fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2110           0 :   if (RetVT.SimpleTy != MVT::i64)
    2111             :     return 0;
    2112             :   return fastEmitInst_rr(PPC::OR8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2113             : }
    2114             : 
    2115           2 : unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2116           2 :   if (RetVT.SimpleTy != MVT::v4i32)
    2117             :     return 0;
    2118           2 :   if ((PPCSubTarget->hasVSX())) {
    2119           4 :     return fastEmitInst_rr(PPC::XXLOR, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2120             :   }
    2121           0 :   if ((PPCSubTarget->hasAltivec())) {
    2122           0 :     return fastEmitInst_rr(PPC::VOR, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2123             :   }
    2124             :   return 0;
    2125             : }
    2126             : 
    2127           6 : unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2128           6 :   switch (VT.SimpleTy) {
    2129           0 :   case MVT::i1: return fastEmit_ISD_OR_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2130           0 :   case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2131           0 :   case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2132           2 :   case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2133             :   default: return 0;
    2134             :   }
    2135             : }
    2136             : 
    2137             : // FastEmit functions for ISD::SDIV.
    2138             : 
    2139             : unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2140           0 :   if (RetVT.SimpleTy != MVT::i32)
    2141             :     return 0;
    2142             :   return fastEmitInst_rr(PPC::DIVW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2143             : }
    2144             : 
    2145             : unsigned fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2146           0 :   if (RetVT.SimpleTy != MVT::i64)
    2147             :     return 0;
    2148             :   return fastEmitInst_rr(PPC::DIVD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2149             : }
    2150             : 
    2151           0 : unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2152           0 :   switch (VT.SimpleTy) {
    2153           0 :   case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2154           0 :   case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2155             :   default: return 0;
    2156             :   }
    2157             : }
    2158             : 
    2159             : // FastEmit functions for ISD::SHL.
    2160             : 
    2161             : unsigned fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2162           2 :   if (RetVT.SimpleTy != MVT::i32)
    2163             :     return 0;
    2164             :   return fastEmitInst_rr(PPC::SLW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2165             : }
    2166             : 
    2167             : unsigned fastEmit_ISD_SHL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2168           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2169             :     return 0;
    2170           0 :   if ((PPCSubTarget->hasAltivec())) {
    2171             :     return fastEmitInst_rr(PPC::VSLB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2172             :   }
    2173             :   return 0;
    2174             : }
    2175             : 
    2176             : unsigned fastEmit_ISD_SHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2177           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2178             :     return 0;
    2179           0 :   if ((PPCSubTarget->hasAltivec())) {
    2180             :     return fastEmitInst_rr(PPC::VSLH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2181             :   }
    2182             :   return 0;
    2183             : }
    2184             : 
    2185             : unsigned fastEmit_ISD_SHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2186           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2187             :     return 0;
    2188           0 :   if ((PPCSubTarget->hasAltivec())) {
    2189             :     return fastEmitInst_rr(PPC::VSLW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2190             :   }
    2191             :   return 0;
    2192             : }
    2193             : 
    2194             : unsigned fastEmit_ISD_SHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2195           2 :   if (RetVT.SimpleTy != MVT::v2i64)
    2196             :     return 0;
    2197           2 :   if ((PPCSubTarget->hasP8Altivec())) {
    2198             :     return fastEmitInst_rr(PPC::VSLD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2199             :   }
    2200             :   return 0;
    2201             : }
    2202             : 
    2203           5 : unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2204           5 :   switch (VT.SimpleTy) {
    2205           2 :   case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2206           0 :   case MVT::v16i8: return fastEmit_ISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2207           0 :   case MVT::v8i16: return fastEmit_ISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2208           0 :   case MVT::v4i32: return fastEmit_ISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2209           2 :   case MVT::v2i64: return fastEmit_ISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2210             :   default: return 0;
    2211             :   }
    2212             : }
    2213             : 
    2214             : // FastEmit functions for ISD::SRA.
    2215             : 
    2216             : unsigned fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2217           1 :   if (RetVT.SimpleTy != MVT::i32)
    2218             :     return 0;
    2219             :   return fastEmitInst_rr(PPC::SRAW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2220             : }
    2221             : 
    2222             : unsigned fastEmit_ISD_SRA_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2223           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2224             :     return 0;
    2225           0 :   if ((PPCSubTarget->hasAltivec())) {
    2226             :     return fastEmitInst_rr(PPC::VSRAB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2227             :   }
    2228             :   return 0;
    2229             : }
    2230             : 
    2231             : unsigned fastEmit_ISD_SRA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2232           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2233             :     return 0;
    2234           0 :   if ((PPCSubTarget->hasAltivec())) {
    2235             :     return fastEmitInst_rr(PPC::VSRAH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2236             :   }
    2237             :   return 0;
    2238             : }
    2239             : 
    2240             : unsigned fastEmit_ISD_SRA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2241           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2242             :     return 0;
    2243           0 :   if ((PPCSubTarget->hasAltivec())) {
    2244             :     return fastEmitInst_rr(PPC::VSRAW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2245             :   }
    2246             :   return 0;
    2247             : }
    2248             : 
    2249             : unsigned fastEmit_ISD_SRA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2250           2 :   if (RetVT.SimpleTy != MVT::v2i64)
    2251             :     return 0;
    2252           2 :   if ((PPCSubTarget->hasP8Altivec())) {
    2253             :     return fastEmitInst_rr(PPC::VSRAD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2254             :   }
    2255             :   return 0;
    2256             : }
    2257             : 
    2258           3 : unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2259           3 :   switch (VT.SimpleTy) {
    2260           1 :   case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2261           0 :   case MVT::v16i8: return fastEmit_ISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2262           0 :   case MVT::v8i16: return fastEmit_ISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2263           0 :   case MVT::v4i32: return fastEmit_ISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2264           2 :   case MVT::v2i64: return fastEmit_ISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2265             :   default: return 0;
    2266             :   }
    2267             : }
    2268             : 
    2269             : // FastEmit functions for ISD::SREM.
    2270             : 
    2271             : unsigned fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2272           0 :   if (RetVT.SimpleTy != MVT::i32)
    2273             :     return 0;
    2274           0 :   if ((PPCSubTarget->isISA3_0())) {
    2275             :     return fastEmitInst_rr(PPC::MODSW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2276             :   }
    2277             :   return 0;
    2278             : }
    2279             : 
    2280             : unsigned fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2281           0 :   if (RetVT.SimpleTy != MVT::i64)
    2282             :     return 0;
    2283           0 :   if ((PPCSubTarget->isISA3_0())) {
    2284             :     return fastEmitInst_rr(PPC::MODSD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2285             :   }
    2286             :   return 0;
    2287             : }
    2288             : 
    2289           0 : unsigned fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2290           0 :   switch (VT.SimpleTy) {
    2291           0 :   case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2292           0 :   case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2293             :   default: return 0;
    2294             :   }
    2295             : }
    2296             : 
    2297             : // FastEmit functions for ISD::SRL.
    2298             : 
    2299             : unsigned fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2300           2 :   if (RetVT.SimpleTy != MVT::i32)
    2301             :     return 0;
    2302             :   return fastEmitInst_rr(PPC::SRW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2303             : }
    2304             : 
    2305             : unsigned fastEmit_ISD_SRL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2306           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2307             :     return 0;
    2308           0 :   if ((PPCSubTarget->hasAltivec())) {
    2309             :     return fastEmitInst_rr(PPC::VSRB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2310             :   }
    2311             :   return 0;
    2312             : }
    2313             : 
    2314             : unsigned fastEmit_ISD_SRL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2315           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2316             :     return 0;
    2317           0 :   if ((PPCSubTarget->hasAltivec())) {
    2318             :     return fastEmitInst_rr(PPC::VSRH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2319             :   }
    2320             :   return 0;
    2321             : }
    2322             : 
    2323             : unsigned fastEmit_ISD_SRL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2324           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2325             :     return 0;
    2326           0 :   if ((PPCSubTarget->hasAltivec())) {
    2327             :     return fastEmitInst_rr(PPC::VSRW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2328             :   }
    2329             :   return 0;
    2330             : }
    2331             : 
    2332             : unsigned fastEmit_ISD_SRL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2333           2 :   if (RetVT.SimpleTy != MVT::v2i64)
    2334             :     return 0;
    2335           2 :   if ((PPCSubTarget->hasP8Altivec())) {
    2336             :     return fastEmitInst_rr(PPC::VSRD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2337             :   }
    2338             :   return 0;
    2339             : }
    2340             : 
    2341           4 : unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2342           4 :   switch (VT.SimpleTy) {
    2343           2 :   case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2344           0 :   case MVT::v16i8: return fastEmit_ISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2345           0 :   case MVT::v8i16: return fastEmit_ISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2346           0 :   case MVT::v4i32: return fastEmit_ISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2347           2 :   case MVT::v2i64: return fastEmit_ISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2348             :   default: return 0;
    2349             :   }
    2350             : }
    2351             : 
    2352             : // FastEmit functions for ISD::SUB.
    2353             : 
    2354             : unsigned fastEmit_ISD_SUB_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2355           0 :   if (RetVT.SimpleTy != MVT::i1)
    2356             :     return 0;
    2357             :   return fastEmitInst_rr(PPC::CRXOR, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2358             : }
    2359             : 
    2360             : unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2361           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2362             :     return 0;
    2363           0 :   if ((PPCSubTarget->hasAltivec())) {
    2364             :     return fastEmitInst_rr(PPC::VSUBUBM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2365             :   }
    2366             :   return 0;
    2367             : }
    2368             : 
    2369             : unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2370           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2371             :     return 0;
    2372           0 :   if ((PPCSubTarget->hasAltivec())) {
    2373             :     return fastEmitInst_rr(PPC::VSUBUHM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2374             :   }
    2375             :   return 0;
    2376             : }
    2377             : 
    2378             : unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2379           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2380             :     return 0;
    2381           0 :   if ((PPCSubTarget->hasAltivec())) {
    2382             :     return fastEmitInst_rr(PPC::VSUBUWM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2383             :   }
    2384             :   return 0;
    2385             : }
    2386             : 
    2387             : unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2388           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2389             :     return 0;
    2390           0 :   if ((PPCSubTarget->hasP8Altivec())) {
    2391             :     return fastEmitInst_rr(PPC::VSUBUDM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2392             :   }
    2393             :   return 0;
    2394             : }
    2395             : 
    2396             : unsigned fastEmit_ISD_SUB_MVT_v1i128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2397           0 :   if (RetVT.SimpleTy != MVT::v1i128)
    2398             :     return 0;
    2399           0 :   if ((PPCSubTarget->hasP8Altivec())) {
    2400             :     return fastEmitInst_rr(PPC::VSUBUQM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2401             :   }
    2402             :   return 0;
    2403             : }
    2404             : 
    2405           1 : unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2406           1 :   switch (VT.SimpleTy) {
    2407           0 :   case MVT::i1: return fastEmit_ISD_SUB_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2408           0 :   case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2409           0 :   case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2410           0 :   case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2411           0 :   case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2412           0 :   case MVT::v1i128: return fastEmit_ISD_SUB_MVT_v1i128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2413             :   default: return 0;
    2414             :   }
    2415             : }
    2416             : 
    2417             : // FastEmit functions for ISD::UDIV.
    2418             : 
    2419             : unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2420           0 :   if (RetVT.SimpleTy != MVT::i32)
    2421             :     return 0;
    2422             :   return fastEmitInst_rr(PPC::DIVWU, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2423             : }
    2424             : 
    2425             : unsigned fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2426           0 :   if (RetVT.SimpleTy != MVT::i64)
    2427             :     return 0;
    2428             :   return fastEmitInst_rr(PPC::DIVDU, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2429             : }
    2430             : 
    2431           0 : unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2432           0 :   switch (VT.SimpleTy) {
    2433           0 :   case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2434           0 :   case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2435             :   default: return 0;
    2436             :   }
    2437             : }
    2438             : 
    2439             : // FastEmit functions for ISD::UREM.
    2440             : 
    2441             : unsigned fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2442           0 :   if (RetVT.SimpleTy != MVT::i32)
    2443             :     return 0;
    2444           0 :   if ((PPCSubTarget->isISA3_0())) {
    2445             :     return fastEmitInst_rr(PPC::MODUW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2446             :   }
    2447             :   return 0;
    2448             : }
    2449             : 
    2450             : unsigned fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2451           0 :   if (RetVT.SimpleTy != MVT::i64)
    2452             :     return 0;
    2453           0 :   if ((PPCSubTarget->isISA3_0())) {
    2454             :     return fastEmitInst_rr(PPC::MODUD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2455             :   }
    2456             :   return 0;
    2457             : }
    2458             : 
    2459           0 : unsigned fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2460           0 :   switch (VT.SimpleTy) {
    2461           0 :   case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2462           0 :   case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2463             :   default: return 0;
    2464             :   }
    2465             : }
    2466             : 
    2467             : // FastEmit functions for ISD::XOR.
    2468             : 
    2469             : unsigned fastEmit_ISD_XOR_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2470           0 :   if (RetVT.SimpleTy != MVT::i1)
    2471             :     return 0;
    2472             :   return fastEmitInst_rr(PPC::CRXOR, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2473             : }
    2474             : 
    2475             : unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2476           0 :   if (RetVT.SimpleTy != MVT::i32)
    2477             :     return 0;
    2478             :   return fastEmitInst_rr(PPC::XOR, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2479             : }
    2480             : 
    2481             : unsigned fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2482           0 :   if (RetVT.SimpleTy != MVT::i64)
    2483             :     return 0;
    2484             :   return fastEmitInst_rr(PPC::XOR8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2485             : }
    2486             : 
    2487           2 : unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2488           2 :   if (RetVT.SimpleTy != MVT::v4i32)
    2489             :     return 0;
    2490           2 :   if ((PPCSubTarget->hasVSX())) {
    2491           4 :     return fastEmitInst_rr(PPC::XXLXOR, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2492             :   }
    2493           0 :   if ((PPCSubTarget->hasAltivec())) {
    2494           0 :     return fastEmitInst_rr(PPC::VXOR, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2495             :   }
    2496             :   return 0;
    2497             : }
    2498             : 
    2499           6 : unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2500           6 :   switch (VT.SimpleTy) {
    2501           0 :   case MVT::i1: return fastEmit_ISD_XOR_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2502           0 :   case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2503           0 :   case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2504           2 :   case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2505             :   default: return 0;
    2506             :   }
    2507             : }
    2508             : 
    2509             : // FastEmit functions for PPCISD::CMPB.
    2510             : 
    2511             : unsigned fastEmit_PPCISD_CMPB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2512           0 :   if (RetVT.SimpleTy != MVT::i32)
    2513             :     return 0;
    2514             :   return fastEmitInst_rr(PPC::CMPB, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2515             : }
    2516             : 
    2517             : unsigned fastEmit_PPCISD_CMPB_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2518           0 :   if (RetVT.SimpleTy != MVT::i64)
    2519             :     return 0;
    2520             :   return fastEmitInst_rr(PPC::CMPB8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2521             : }
    2522             : 
    2523           0 : unsigned fastEmit_PPCISD_CMPB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2524           0 :   switch (VT.SimpleTy) {
    2525           0 :   case MVT::i32: return fastEmit_PPCISD_CMPB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2526           0 :   case MVT::i64: return fastEmit_PPCISD_CMPB_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2527             :   default: return 0;
    2528             :   }
    2529             : }
    2530             : 
    2531             : // FastEmit functions for PPCISD::FADDRTZ.
    2532             : 
    2533             : unsigned fastEmit_PPCISD_FADDRTZ_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2534           0 :   if (RetVT.SimpleTy != MVT::f64)
    2535             :     return 0;
    2536             :   return fastEmitInst_rr(PPC::FADDrtz, &PPC::F8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2537             : }
    2538             : 
    2539             : unsigned fastEmit_PPCISD_FADDRTZ_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2540           0 :   switch (VT.SimpleTy) {
    2541           0 :   case MVT::f64: return fastEmit_PPCISD_FADDRTZ_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2542             :   default: return 0;
    2543             :   }
    2544             : }
    2545             : 
    2546             : // FastEmit functions for PPCISD::SHL.
    2547             : 
    2548             : unsigned fastEmit_PPCISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2549           0 :   if (RetVT.SimpleTy != MVT::i32)
    2550             :     return 0;
    2551             :   return fastEmitInst_rr(PPC::SLW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2552             : }
    2553             : 
    2554             : unsigned fastEmit_PPCISD_SHL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2555           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2556             :     return 0;
    2557           0 :   if ((PPCSubTarget->hasAltivec())) {
    2558             :     return fastEmitInst_rr(PPC::VSLB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2559             :   }
    2560             :   return 0;
    2561             : }
    2562             : 
    2563             : unsigned fastEmit_PPCISD_SHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2564           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2565             :     return 0;
    2566           0 :   if ((PPCSubTarget->hasAltivec())) {
    2567             :     return fastEmitInst_rr(PPC::VSLH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2568             :   }
    2569             :   return 0;
    2570             : }
    2571             : 
    2572             : unsigned fastEmit_PPCISD_SHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2573           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2574             :     return 0;
    2575           0 :   if ((PPCSubTarget->hasAltivec())) {
    2576             :     return fastEmitInst_rr(PPC::VSLW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2577             :   }
    2578             :   return 0;
    2579             : }
    2580             : 
    2581             : unsigned fastEmit_PPCISD_SHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2582           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2583             :     return 0;
    2584           0 :   if ((PPCSubTarget->hasP8Altivec())) {
    2585             :     return fastEmitInst_rr(PPC::VSLD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2586             :   }
    2587             :   return 0;
    2588             : }
    2589             : 
    2590           0 : unsigned fastEmit_PPCISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2591           0 :   switch (VT.SimpleTy) {
    2592           0 :   case MVT::i32: return fastEmit_PPCISD_SHL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2593           0 :   case MVT::v16i8: return fastEmit_PPCISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2594           0 :   case MVT::v8i16: return fastEmit_PPCISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2595           0 :   case MVT::v4i32: return fastEmit_PPCISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2596           0 :   case MVT::v2i64: return fastEmit_PPCISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2597             :   default: return 0;
    2598             :   }
    2599             : }
    2600             : 
    2601             : // FastEmit functions for PPCISD::SRA.
    2602             : 
    2603             : unsigned fastEmit_PPCISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2604           0 :   if (RetVT.SimpleTy != MVT::i32)
    2605             :     return 0;
    2606             :   return fastEmitInst_rr(PPC::SRAW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2607             : }
    2608             : 
    2609             : unsigned fastEmit_PPCISD_SRA_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2610           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2611             :     return 0;
    2612           0 :   if ((PPCSubTarget->hasAltivec())) {
    2613             :     return fastEmitInst_rr(PPC::VSRAB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2614             :   }
    2615             :   return 0;
    2616             : }
    2617             : 
    2618             : unsigned fastEmit_PPCISD_SRA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2619           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2620             :     return 0;
    2621           0 :   if ((PPCSubTarget->hasAltivec())) {
    2622             :     return fastEmitInst_rr(PPC::VSRAH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2623             :   }
    2624             :   return 0;
    2625             : }
    2626             : 
    2627             : unsigned fastEmit_PPCISD_SRA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2628           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2629             :     return 0;
    2630           0 :   if ((PPCSubTarget->hasAltivec())) {
    2631             :     return fastEmitInst_rr(PPC::VSRAW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2632             :   }
    2633             :   return 0;
    2634             : }
    2635             : 
    2636             : unsigned fastEmit_PPCISD_SRA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2637           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2638             :     return 0;
    2639           0 :   if ((PPCSubTarget->hasP8Altivec())) {
    2640             :     return fastEmitInst_rr(PPC::VSRAD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2641             :   }
    2642             :   return 0;
    2643             : }
    2644             : 
    2645           0 : unsigned fastEmit_PPCISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2646           0 :   switch (VT.SimpleTy) {
    2647           0 :   case MVT::i32: return fastEmit_PPCISD_SRA_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2648           0 :   case MVT::v16i8: return fastEmit_PPCISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2649           0 :   case MVT::v8i16: return fastEmit_PPCISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2650           0 :   case MVT::v4i32: return fastEmit_PPCISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2651           0 :   case MVT::v2i64: return fastEmit_PPCISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2652             :   default: return 0;
    2653             :   }
    2654             : }
    2655             : 
    2656             : // FastEmit functions for PPCISD::SRL.
    2657             : 
    2658             : unsigned fastEmit_PPCISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2659           0 :   if (RetVT.SimpleTy != MVT::i32)
    2660             :     return 0;
    2661             :   return fastEmitInst_rr(PPC::SRW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2662             : }
    2663             : 
    2664             : unsigned fastEmit_PPCISD_SRL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2665           0 :   if (RetVT.SimpleTy != MVT::v16i8)
    2666             :     return 0;
    2667           0 :   if ((PPCSubTarget->hasAltivec())) {
    2668             :     return fastEmitInst_rr(PPC::VSRB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2669             :   }
    2670             :   return 0;
    2671             : }
    2672             : 
    2673             : unsigned fastEmit_PPCISD_SRL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2674           0 :   if (RetVT.SimpleTy != MVT::v8i16)
    2675             :     return 0;
    2676           0 :   if ((PPCSubTarget->hasAltivec())) {
    2677             :     return fastEmitInst_rr(PPC::VSRH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2678             :   }
    2679             :   return 0;
    2680             : }
    2681             : 
    2682             : unsigned fastEmit_PPCISD_SRL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2683           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2684             :     return 0;
    2685           0 :   if ((PPCSubTarget->hasAltivec())) {
    2686             :     return fastEmitInst_rr(PPC::VSRW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2687             :   }
    2688             :   return 0;
    2689             : }
    2690             : 
    2691             : unsigned fastEmit_PPCISD_SRL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2692           0 :   if (RetVT.SimpleTy != MVT::v2i64)
    2693             :     return 0;
    2694           0 :   if ((PPCSubTarget->hasP8Altivec())) {
    2695             :     return fastEmitInst_rr(PPC::VSRD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    2696             :   }
    2697             :   return 0;
    2698             : }
    2699             : 
    2700           0 : unsigned fastEmit_PPCISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    2701           0 :   switch (VT.SimpleTy) {
    2702           0 :   case MVT::i32: return fastEmit_PPCISD_SRL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2703           0 :   case MVT::v16i8: return fastEmit_PPCISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2704           0 :   case MVT::v8i16: return fastEmit_PPCISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2705           0 :   case MVT::v4i32: return fastEmit_PPCISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2706           0 :   case MVT::v2i64: return fastEmit_PPCISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2707             :   default: return 0;
    2708             :   }
    2709             : }
    2710             : 
    2711             : // Top-level FastEmit function.
    2712             : 
    2713          60 : unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) override {
    2714          60 :   switch (Opcode) {
    2715           2 :   case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2716           0 :   case ISD::ADDC: return fastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2717           0 :   case ISD::ADDE: return fastEmit_ISD_ADDE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2718          15 :   case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2719           0 :   case ISD::BUILD_VECTOR: return fastEmit_ISD_BUILD_VECTOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2720          14 :   case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2721           2 :   case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2722           2 :   case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2723           0 :   case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2724           0 :   case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2725           0 :   case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2726           0 :   case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2727           6 :   case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2728           0 :   case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2729           5 :   case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2730           3 :   case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2731           0 :   case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2732           4 :   case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2733           1 :   case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2734           0 :   case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2735           0 :   case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2736           6 :   case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2737           0 :   case PPCISD::CMPB: return fastEmit_PPCISD_CMPB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2738           0 :   case PPCISD::FADDRTZ: return fastEmit_PPCISD_FADDRTZ_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2739           0 :   case PPCISD::SHL: return fastEmit_PPCISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2740           0 :   case PPCISD::SRA: return fastEmit_PPCISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2741           0 :   case PPCISD::SRL: return fastEmit_PPCISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    2742             :   default: return 0;
    2743             :   }
    2744             : }
    2745             : 
    2746             : // FastEmit functions for ISD::SRA.
    2747             : 
    2748             : unsigned fastEmit_ISD_SRA_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2749           1 :   if (RetVT.SimpleTy != MVT::i32)
    2750             :     return 0;
    2751             :   return fastEmitInst_ri(PPC::SRAWI, &PPC::GPRCRegClass, Op0, Op0IsKill, imm1);
    2752             : }
    2753             : 
    2754             : unsigned fastEmit_ISD_SRA_MVT_i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2755           0 :   if (RetVT.SimpleTy != MVT::i64)
    2756             :     return 0;
    2757             :   return fastEmitInst_ri(PPC::SRADI, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
    2758             : }
    2759             : 
    2760           1 : unsigned fastEmit_ISD_SRA_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2761           1 :   switch (VT.SimpleTy) {
    2762           1 :   case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1);
    2763           0 :   case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri(RetVT, Op0, Op0IsKill, imm1);
    2764             :   default: return 0;
    2765             :   }
    2766             : }
    2767             : 
    2768             : // FastEmit functions for PPCISD::QVESPLATI.
    2769             : 
    2770             : unsigned fastEmit_PPCISD_QVESPLATI_MVT_v4i1_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2771           0 :   if (RetVT.SimpleTy != MVT::v4i1)
    2772             :     return 0;
    2773           0 :   if ((PPCSubTarget->hasQPX())) {
    2774             :     return fastEmitInst_ri(PPC::QVESPLATIb, &PPC::QBRCRegClass, Op0, Op0IsKill, imm1);
    2775             :   }
    2776             :   return 0;
    2777             : }
    2778             : 
    2779             : unsigned fastEmit_PPCISD_QVESPLATI_MVT_v4f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2780           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    2781             :     return 0;
    2782           0 :   if ((PPCSubTarget->hasQPX())) {
    2783             :     return fastEmitInst_ri(PPC::QVESPLATIs, &PPC::QSRCRegClass, Op0, Op0IsKill, imm1);
    2784             :   }
    2785             :   return 0;
    2786             : }
    2787             : 
    2788             : unsigned fastEmit_PPCISD_QVESPLATI_MVT_v4f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2789           0 :   if (RetVT.SimpleTy != MVT::v4f64)
    2790             :     return 0;
    2791           0 :   if ((PPCSubTarget->hasQPX())) {
    2792             :     return fastEmitInst_ri(PPC::QVESPLATI, &PPC::QFRCRegClass, Op0, Op0IsKill, imm1);
    2793             :   }
    2794             :   return 0;
    2795             : }
    2796             : 
    2797           0 : unsigned fastEmit_PPCISD_QVESPLATI_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2798           0 :   switch (VT.SimpleTy) {
    2799           0 :   case MVT::v4i1: return fastEmit_PPCISD_QVESPLATI_MVT_v4i1_ri(RetVT, Op0, Op0IsKill, imm1);
    2800           0 :   case MVT::v4f32: return fastEmit_PPCISD_QVESPLATI_MVT_v4f32_ri(RetVT, Op0, Op0IsKill, imm1);
    2801           0 :   case MVT::v4f64: return fastEmit_PPCISD_QVESPLATI_MVT_v4f64_ri(RetVT, Op0, Op0IsKill, imm1);
    2802             :   default: return 0;
    2803             :   }
    2804             : }
    2805             : 
    2806             : // FastEmit functions for PPCISD::TC_RETURN.
    2807             : 
    2808             : unsigned fastEmit_PPCISD_TC_RETURN_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2809           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2810             :     return 0;
    2811             :   return fastEmitInst_ri(PPC::TCRETURNri, &PPC::CTRRCRegClass, Op0, Op0IsKill, imm1);
    2812             : }
    2813             : 
    2814             : unsigned fastEmit_PPCISD_TC_RETURN_MVT_i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2815           0 :   if (RetVT.SimpleTy != MVT::isVoid)
    2816             :     return 0;
    2817             :   return fastEmitInst_ri(PPC::TCRETURNri8, &PPC::CTRRC8RegClass, Op0, Op0IsKill, imm1);
    2818             : }
    2819             : 
    2820           0 : unsigned fastEmit_PPCISD_TC_RETURN_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2821           0 :   switch (VT.SimpleTy) {
    2822           0 :   case MVT::i32: return fastEmit_PPCISD_TC_RETURN_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1);
    2823           0 :   case MVT::i64: return fastEmit_PPCISD_TC_RETURN_MVT_i64_ri(RetVT, Op0, Op0IsKill, imm1);
    2824             :   default: return 0;
    2825             :   }
    2826             : }
    2827             : 
    2828             : // Top-level FastEmit function.
    2829             : 
    2830          42 : unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) override {
    2831          65 :   if (VT == MVT::i32 && Predicate_imm32SExt16(imm1))
    2832          23 :     if (unsigned Reg = fastEmit_ri_Predicate_imm32SExt16(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    2833             :       return Reg;
    2834             : 
    2835          41 :   if (VT == MVT::i64 && Predicate_imm64SExt16(imm1))
    2836          19 :     if (unsigned Reg = fastEmit_ri_Predicate_imm64SExt16(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
    2837             :       return Reg;
    2838             : 
    2839           5 :   switch (Opcode) {
    2840           1 :   case ISD::SRA: return fastEmit_ISD_SRA_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    2841           0 :   case PPCISD::QVESPLATI: return fastEmit_PPCISD_QVESPLATI_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    2842           0 :   case PPCISD::TC_RETURN: return fastEmit_PPCISD_TC_RETURN_ri(VT, RetVT, Op0, Op0IsKill, imm1);
    2843             :   default: return 0;
    2844             :   }
    2845             : }
    2846             : 
    2847             : // FastEmit functions for ISD::ADD.
    2848             : 
    2849             : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2850          20 :   if (RetVT.SimpleTy != MVT::i32)
    2851             :     return 0;
    2852          20 :   return fastEmitInst_ri(PPC::ADDI, &PPC::GPRCRegClass, Op0, Op0IsKill, imm1);
    2853             : }
    2854             : 
    2855             : unsigned fastEmit_ISD_ADD_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2856          20 :   switch (VT.SimpleTy) {
    2857          20 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, Op0IsKill, imm1);
    2858             :   default: return 0;
    2859             :   }
    2860             : }
    2861             : 
    2862             : // FastEmit functions for ISD::ADDC.
    2863             : 
    2864             : unsigned fastEmit_ISD_ADDC_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2865           0 :   if (RetVT.SimpleTy != MVT::i32)
    2866             :     return 0;
    2867             :   return fastEmitInst_ri(PPC::ADDIC, &PPC::GPRCRegClass, Op0, Op0IsKill, imm1);
    2868             : }
    2869             : 
    2870             : unsigned fastEmit_ISD_ADDC_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2871           0 :   switch (VT.SimpleTy) {
    2872           0 :   case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, Op0IsKill, imm1);
    2873             :   default: return 0;
    2874             :   }
    2875             : }
    2876             : 
    2877             : // FastEmit functions for ISD::MUL.
    2878             : 
    2879             : unsigned fastEmit_ISD_MUL_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2880           0 :   if (RetVT.SimpleTy != MVT::i32)
    2881             :     return 0;
    2882             :   return fastEmitInst_ri(PPC::MULLI, &PPC::GPRCRegClass, Op0, Op0IsKill, imm1);
    2883             : }
    2884             : 
    2885             : unsigned fastEmit_ISD_MUL_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2886           0 :   switch (VT.SimpleTy) {
    2887           0 :   case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, Op0IsKill, imm1);
    2888             :   default: return 0;
    2889             :   }
    2890             : }
    2891             : 
    2892             : // FastEmit functions for PPCISD::XXSPLT.
    2893             : 
    2894             : unsigned fastEmit_PPCISD_XXSPLT_MVT_v4i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2895           0 :   if (RetVT.SimpleTy != MVT::v4i32)
    2896             :     return 0;
    2897           0 :   if ((PPCSubTarget->hasVSX())) {
    2898             :     return fastEmitInst_ri(PPC::XXSPLTW, &PPC::VSRCRegClass, Op0, Op0IsKill, imm1);
    2899             :   }
    2900             :   return 0;
    2901             : }
    2902             : 
    2903           0 : unsigned fastEmit_PPCISD_XXSPLT_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2904           0 :   switch (VT.SimpleTy) {
    2905           0 :   case MVT::v4i32: return fastEmit_PPCISD_XXSPLT_MVT_v4i32_ri_Predicate_imm32SExt16(RetVT, Op0, Op0IsKill, imm1);
    2906             :   default: return 0;
    2907             :   }
    2908             : }
    2909             : 
    2910             : // Top-level FastEmit function.
    2911             : 
    2912          23 : unsigned fastEmit_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2913          23 :   switch (Opcode) {
    2914          20 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm32SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
    2915           0 :   case ISD::ADDC: return fastEmit_ISD_ADDC_ri_Predicate_imm32SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
    2916           0 :   case ISD::MUL: return fastEmit_ISD_MUL_ri_Predicate_imm32SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
    2917           0 :   case PPCISD::XXSPLT: return fastEmit_PPCISD_XXSPLT_ri_Predicate_imm32SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
    2918             :   default: return 0;
    2919             :   }
    2920             : }
    2921             : 
    2922             : // FastEmit functions for ISD::ADD.
    2923             : 
    2924             : unsigned fastEmit_ISD_ADD_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2925          17 :   if (RetVT.SimpleTy != MVT::i64)
    2926             :     return 0;
    2927          17 :   return fastEmitInst_ri(PPC::ADDI8, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
    2928             : }
    2929             : 
    2930             : unsigned fastEmit_ISD_ADD_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2931          17 :   switch (VT.SimpleTy) {
    2932          17 :   case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, Op0IsKill, imm1);
    2933             :   default: return 0;
    2934             :   }
    2935             : }
    2936             : 
    2937             : // FastEmit functions for ISD::ADDC.
    2938             : 
    2939             : unsigned fastEmit_ISD_ADDC_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2940           0 :   if (RetVT.SimpleTy != MVT::i64)
    2941             :     return 0;
    2942             :   return fastEmitInst_ri(PPC::ADDIC8, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
    2943             : }
    2944             : 
    2945             : unsigned fastEmit_ISD_ADDC_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2946           0 :   switch (VT.SimpleTy) {
    2947           0 :   case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, Op0IsKill, imm1);
    2948             :   default: return 0;
    2949             :   }
    2950             : }
    2951             : 
    2952             : // FastEmit functions for ISD::MUL.
    2953             : 
    2954             : unsigned fastEmit_ISD_MUL_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2955           0 :   if (RetVT.SimpleTy != MVT::i64)
    2956             :     return 0;
    2957             :   return fastEmitInst_ri(PPC::MULLI8, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
    2958             : }
    2959             : 
    2960             : unsigned fastEmit_ISD_MUL_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2961           0 :   switch (VT.SimpleTy) {
    2962           0 :   case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, Op0IsKill, imm1);
    2963             :   default: return 0;
    2964             :   }
    2965             : }
    2966             : 
    2967             : // Top-level FastEmit function.
    2968             : 
    2969          19 : unsigned fastEmit_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2970          19 :   switch (Opcode) {
    2971          17 :   case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm64SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
    2972           0 :   case ISD::ADDC: return fastEmit_ISD_ADDC_ri_Predicate_imm64SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
    2973           0 :   case ISD::MUL: return fastEmit_ISD_MUL_ri_Predicate_imm64SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
    2974             :   default: return 0;
    2975             :   }
    2976             : }
    2977             : 

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