Line data Source code
1 : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2 : |* *|
3 : |* Assembly Matcher Source Fragment *|
4 : |* *|
5 : |* Automatically generated file, do not edit! *|
6 : |* *|
7 : \*===----------------------------------------------------------------------===*/
8 :
9 :
10 : #ifdef GET_ASSEMBLER_HEADER
11 : #undef GET_ASSEMBLER_HEADER
12 : // This should be included into the middle of the declaration of
13 : // your subclasses implementation of MCTargetAsmParser.
14 : uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;
15 : void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
16 : const OperandVector &Operands);
17 : void convertToMapAndConstraints(unsigned Kind,
18 : const OperandVector &Operands) override;
19 : bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) override;
20 : unsigned MatchInstructionImpl(const OperandVector &Operands,
21 : MCInst &Inst,
22 : uint64_t &ErrorInfo, bool matchingInlineAsm,
23 : unsigned VariantID = 0);
24 :
25 : enum OperandMatchResultTy {
26 : MatchOperand_Success, // operand matched successfully
27 : MatchOperand_NoMatch, // operand did not match
28 : MatchOperand_ParseFail // operand matched but had errors
29 : };
30 : OperandMatchResultTy MatchOperandParserImpl(
31 : OperandVector &Operands,
32 : StringRef Mnemonic);
33 : OperandMatchResultTy tryCustomParseOperand(
34 : OperandVector &Operands,
35 : unsigned MCK);
36 :
37 : #endif // GET_ASSEMBLER_HEADER_INFO
38 :
39 :
40 : #ifdef GET_OPERAND_DIAGNOSTIC_TYPES
41 : #undef GET_OPERAND_DIAGNOSTIC_TYPES
42 :
43 : #endif // GET_OPERAND_DIAGNOSTIC_TYPES
44 :
45 :
46 : #ifdef GET_REGISTER_MATCHER
47 : #undef GET_REGISTER_MATCHER
48 :
49 : // Flags for subtarget features that participate in instruction matching.
50 : enum SubtargetFeatureFlag : uint8_t {
51 : Feature_isSICI = (1ULL << 3),
52 : Feature_isVI = (1ULL << 4),
53 : Feature_DisableInst = (1ULL << 0),
54 : Feature_isGCN = (1ULL << 2),
55 : Feature_isCIVI = (1ULL << 1),
56 : Feature_None = 0
57 : };
58 :
59 : #endif // GET_REGISTER_MATCHER
60 :
61 :
62 : #ifdef GET_SUBTARGET_FEATURE_NAME
63 : #undef GET_SUBTARGET_FEATURE_NAME
64 :
65 : // User-level names for subtarget features that participate in
66 : // instruction matching.
67 : static const char *getSubtargetFeatureName(uint64_t Val) {
68 : switch(Val) {
69 : case Feature_isSICI: return "";
70 : case Feature_isVI: return "";
71 : case Feature_DisableInst: return "";
72 : case Feature_isGCN: return "";
73 : case Feature_isCIVI: return "";
74 : default: return "(unknown)";
75 : }
76 : }
77 :
78 : #endif // GET_SUBTARGET_FEATURE_NAME
79 :
80 :
81 : #ifdef GET_MATCHER_IMPLEMENTATION
82 : #undef GET_MATCHER_IMPLEMENTATION
83 :
84 2266 : static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features, unsigned VariantID) {
85 2266 : switch (VariantID) {
86 : case 0:
87 2266 : switch (Mnemonic.size()) {
88 : default: break;
89 : case 9: // 3 strings to match.
90 506 : if (memcmp(Mnemonic.data()+0, "v_", 2))
91 : break;
92 780 : switch (Mnemonic[2]) {
93 : default: break;
94 : case 'a': // 1 string to match.
95 82 : if (memcmp(Mnemonic.data()+3, "dd_u32", 6))
96 : break;
97 8 : if ((Features & Feature_isGCN) == Feature_isGCN) // "v_add_u32"
98 8 : Mnemonic = "v_add_i32";
99 : return;
100 : case 'n': // 1 string to match.
101 8 : if (memcmp(Mnemonic.data()+3, "op_e32", 6))
102 : break;
103 0 : Mnemonic = "v_nop"; // "v_nop_e32"
104 0 : return;
105 : case 's': // 1 string to match.
106 58 : if (memcmp(Mnemonic.data()+3, "ub_u32", 6))
107 : break;
108 8 : if ((Features & Feature_isGCN) == Feature_isGCN) // "v_sub_u32"
109 8 : Mnemonic = "v_sub_i32";
110 : return;
111 : }
112 : break;
113 : case 12: // 3 strings to match.
114 134 : if (memcmp(Mnemonic.data()+0, "v_", 2))
115 : break;
116 180 : switch (Mnemonic[2]) {
117 : default: break;
118 : case 'o': // 2 strings to match.
119 0 : if (memcmp(Mnemonic.data()+3, "r_b32_e", 7))
120 : break;
121 0 : switch (Mnemonic[10]) {
122 : default: break;
123 : case '3': // 1 string to match.
124 0 : if (Mnemonic[11] != '2')
125 : break;
126 0 : Mnemonic = "v_or_b32"; // "v_or_b32_e32"
127 0 : return;
128 : case '6': // 1 string to match.
129 0 : if (Mnemonic[11] != '4')
130 : break;
131 0 : Mnemonic = "v_or_b32"; // "v_or_b32_e64"
132 0 : return;
133 : }
134 : break;
135 : case 's': // 1 string to match.
136 42 : if (memcmp(Mnemonic.data()+3, "ubrev_u32", 9))
137 : break;
138 8 : if ((Features & Feature_isGCN) == Feature_isGCN) // "v_subrev_u32"
139 8 : Mnemonic = "v_subrev_i32";
140 : return;
141 : }
142 : break;
143 : case 13: // 98 strings to match.
144 436 : if (memcmp(Mnemonic.data()+0, "v_", 2))
145 : break;
146 708 : switch (Mnemonic[2]) {
147 : default: break;
148 : case 'a': // 11 strings to match.
149 56 : switch (Mnemonic[3]) {
150 : default: break;
151 : case 'd': // 9 strings to match.
152 12 : if (memcmp(Mnemonic.data()+4, "d_", 2))
153 : break;
154 24 : switch (Mnemonic[6]) {
155 : default: break;
156 : case 'f': // 5 strings to match.
157 24 : switch (Mnemonic[7]) {
158 : default: break;
159 : case '1': // 2 strings to match.
160 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
161 : break;
162 0 : switch (Mnemonic[11]) {
163 : default: break;
164 : case '3': // 1 string to match.
165 0 : if (Mnemonic[12] != '2')
166 : break;
167 0 : Mnemonic = "v_add_f16"; // "v_add_f16_e32"
168 0 : return;
169 : case '6': // 1 string to match.
170 0 : if (Mnemonic[12] != '4')
171 : break;
172 0 : Mnemonic = "v_add_f16"; // "v_add_f16_e64"
173 0 : return;
174 : }
175 : break;
176 : case '3': // 2 strings to match.
177 12 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
178 : break;
179 24 : switch (Mnemonic[11]) {
180 : default: break;
181 : case '3': // 1 string to match.
182 16 : if (Mnemonic[12] != '2')
183 : break;
184 8 : Mnemonic = "v_add_f32"; // "v_add_f32_e32"
185 8 : return;
186 : case '6': // 1 string to match.
187 8 : if (Mnemonic[12] != '4')
188 : break;
189 4 : Mnemonic = "v_add_f32"; // "v_add_f32_e64"
190 4 : return;
191 : }
192 : break;
193 : case '6': // 1 string to match.
194 0 : if (memcmp(Mnemonic.data()+8, "4_e64", 5))
195 : break;
196 0 : Mnemonic = "v_add_f64"; // "v_add_f64_e64"
197 0 : return;
198 : }
199 : break;
200 : case 'i': // 2 strings to match.
201 0 : if (memcmp(Mnemonic.data()+7, "32_e", 4))
202 : break;
203 0 : switch (Mnemonic[11]) {
204 : default: break;
205 : case '3': // 1 string to match.
206 0 : if (Mnemonic[12] != '2')
207 : break;
208 0 : Mnemonic = "v_add_i32"; // "v_add_i32_e32"
209 0 : return;
210 : case '6': // 1 string to match.
211 0 : if (Mnemonic[12] != '4')
212 : break;
213 0 : Mnemonic = "v_add_i32"; // "v_add_i32_e64"
214 0 : return;
215 : }
216 : break;
217 : case 'u': // 2 strings to match.
218 0 : if (memcmp(Mnemonic.data()+7, "16_e", 4))
219 : break;
220 0 : switch (Mnemonic[11]) {
221 : default: break;
222 : case '3': // 1 string to match.
223 0 : if (Mnemonic[12] != '2')
224 : break;
225 0 : Mnemonic = "v_add_u16"; // "v_add_u16_e32"
226 0 : return;
227 : case '6': // 1 string to match.
228 0 : if (Mnemonic[12] != '4')
229 : break;
230 0 : Mnemonic = "v_add_u16"; // "v_add_u16_e64"
231 0 : return;
232 : }
233 : break;
234 : }
235 : break;
236 : case 'n': // 2 strings to match.
237 0 : if (memcmp(Mnemonic.data()+4, "d_b32_e", 7))
238 : break;
239 0 : switch (Mnemonic[11]) {
240 : default: break;
241 : case '3': // 1 string to match.
242 0 : if (Mnemonic[12] != '2')
243 : break;
244 0 : Mnemonic = "v_and_b32"; // "v_and_b32_e32"
245 0 : return;
246 : case '6': // 1 string to match.
247 0 : if (Mnemonic[12] != '4')
248 : break;
249 0 : Mnemonic = "v_and_b32"; // "v_and_b32_e64"
250 0 : return;
251 : }
252 : break;
253 : }
254 : break;
255 : case 'b': // 5 strings to match.
256 0 : if (Mnemonic[3] != 'f')
257 : break;
258 0 : switch (Mnemonic[4]) {
259 : default: break;
260 : case 'e': // 2 strings to match.
261 0 : if (Mnemonic[5] != '_')
262 : break;
263 0 : switch (Mnemonic[6]) {
264 : default: break;
265 : case 'i': // 1 string to match.
266 0 : if (memcmp(Mnemonic.data()+7, "32_e64", 6))
267 : break;
268 0 : Mnemonic = "v_bfe_i32"; // "v_bfe_i32_e64"
269 0 : return;
270 : case 'u': // 1 string to match.
271 0 : if (memcmp(Mnemonic.data()+7, "32_e64", 6))
272 : break;
273 0 : Mnemonic = "v_bfe_u32"; // "v_bfe_u32_e64"
274 0 : return;
275 : }
276 : break;
277 : case 'i': // 1 string to match.
278 0 : if (memcmp(Mnemonic.data()+5, "_b32_e64", 8))
279 : break;
280 0 : Mnemonic = "v_bfi_b32"; // "v_bfi_b32_e64"
281 0 : return;
282 : case 'm': // 2 strings to match.
283 0 : if (memcmp(Mnemonic.data()+5, "_b32_e", 6))
284 : break;
285 0 : switch (Mnemonic[11]) {
286 : default: break;
287 : case '3': // 1 string to match.
288 0 : if (Mnemonic[12] != '2')
289 : break;
290 0 : Mnemonic = "v_bfm_b32"; // "v_bfm_b32_e32"
291 0 : return;
292 : case '6': // 1 string to match.
293 0 : if (Mnemonic[12] != '4')
294 : break;
295 0 : Mnemonic = "v_bfm_b32"; // "v_bfm_b32_e64"
296 0 : return;
297 : }
298 : break;
299 : }
300 : break;
301 : case 'c': // 5 strings to match.
302 276 : switch (Mnemonic[3]) {
303 : default: break;
304 : case 'l': // 1 string to match.
305 0 : if (memcmp(Mnemonic.data()+4, "rexcp_e32", 9))
306 : break;
307 0 : Mnemonic = "v_clrexcp"; // "v_clrexcp_e32"
308 0 : return;
309 : case 'o': // 4 strings to match.
310 0 : if (memcmp(Mnemonic.data()+4, "s_f", 3))
311 : break;
312 0 : switch (Mnemonic[7]) {
313 : default: break;
314 : case '1': // 2 strings to match.
315 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
316 : break;
317 0 : switch (Mnemonic[11]) {
318 : default: break;
319 : case '3': // 1 string to match.
320 0 : if (Mnemonic[12] != '2')
321 : break;
322 0 : Mnemonic = "v_cos_f16"; // "v_cos_f16_e32"
323 0 : return;
324 : case '6': // 1 string to match.
325 0 : if (Mnemonic[12] != '4')
326 : break;
327 0 : Mnemonic = "v_cos_f16"; // "v_cos_f16_e64"
328 0 : return;
329 : }
330 : break;
331 : case '3': // 2 strings to match.
332 0 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
333 : break;
334 0 : switch (Mnemonic[11]) {
335 : default: break;
336 : case '3': // 1 string to match.
337 0 : if (Mnemonic[12] != '2')
338 : break;
339 0 : Mnemonic = "v_cos_f32"; // "v_cos_f32_e32"
340 0 : return;
341 : case '6': // 1 string to match.
342 0 : if (Mnemonic[12] != '4')
343 : break;
344 0 : Mnemonic = "v_cos_f32"; // "v_cos_f32_e64"
345 0 : return;
346 : }
347 : break;
348 : }
349 : break;
350 : }
351 : break;
352 : case 'e': // 4 strings to match.
353 0 : if (memcmp(Mnemonic.data()+3, "xp_f", 4))
354 : break;
355 0 : switch (Mnemonic[7]) {
356 : default: break;
357 : case '1': // 2 strings to match.
358 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
359 : break;
360 0 : switch (Mnemonic[11]) {
361 : default: break;
362 : case '3': // 1 string to match.
363 0 : if (Mnemonic[12] != '2')
364 : break;
365 0 : Mnemonic = "v_exp_f16"; // "v_exp_f16_e32"
366 0 : return;
367 : case '6': // 1 string to match.
368 0 : if (Mnemonic[12] != '4')
369 : break;
370 0 : Mnemonic = "v_exp_f16"; // "v_exp_f16_e64"
371 0 : return;
372 : }
373 : break;
374 : case '3': // 2 strings to match.
375 0 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
376 : break;
377 0 : switch (Mnemonic[11]) {
378 : default: break;
379 : case '3': // 1 string to match.
380 0 : if (Mnemonic[12] != '2')
381 : break;
382 0 : Mnemonic = "v_exp_f32"; // "v_exp_f32_e32"
383 0 : return;
384 : case '6': // 1 string to match.
385 0 : if (Mnemonic[12] != '4')
386 : break;
387 0 : Mnemonic = "v_exp_f32"; // "v_exp_f32_e64"
388 0 : return;
389 : }
390 : break;
391 : }
392 : break;
393 : case 'f': // 2 strings to match.
394 0 : if (memcmp(Mnemonic.data()+3, "ma_f", 4))
395 : break;
396 0 : switch (Mnemonic[7]) {
397 : default: break;
398 : case '3': // 1 string to match.
399 0 : if (memcmp(Mnemonic.data()+8, "2_e64", 5))
400 : break;
401 0 : Mnemonic = "v_fma_f32"; // "v_fma_f32_e64"
402 0 : return;
403 : case '6': // 1 string to match.
404 0 : if (memcmp(Mnemonic.data()+8, "4_e64", 5))
405 : break;
406 0 : Mnemonic = "v_fma_f64"; // "v_fma_f64_e64"
407 0 : return;
408 : }
409 : break;
410 : case 'l': // 4 strings to match.
411 32 : if (memcmp(Mnemonic.data()+3, "og_f", 4))
412 : break;
413 0 : switch (Mnemonic[7]) {
414 : default: break;
415 : case '1': // 2 strings to match.
416 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
417 : break;
418 0 : switch (Mnemonic[11]) {
419 : default: break;
420 : case '3': // 1 string to match.
421 0 : if (Mnemonic[12] != '2')
422 : break;
423 0 : Mnemonic = "v_log_f16"; // "v_log_f16_e32"
424 0 : return;
425 : case '6': // 1 string to match.
426 0 : if (Mnemonic[12] != '4')
427 : break;
428 0 : Mnemonic = "v_log_f16"; // "v_log_f16_e64"
429 0 : return;
430 : }
431 : break;
432 : case '3': // 2 strings to match.
433 0 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
434 : break;
435 0 : switch (Mnemonic[11]) {
436 : default: break;
437 : case '3': // 1 string to match.
438 0 : if (Mnemonic[12] != '2')
439 : break;
440 0 : Mnemonic = "v_log_f32"; // "v_log_f32_e32"
441 0 : return;
442 : case '6': // 1 string to match.
443 0 : if (Mnemonic[12] != '4')
444 : break;
445 0 : Mnemonic = "v_log_f32"; // "v_log_f32_e64"
446 0 : return;
447 : }
448 : break;
449 : }
450 : break;
451 : case 'm': // 38 strings to match.
452 280 : switch (Mnemonic[3]) {
453 : default: break;
454 : case 'a': // 18 strings to match.
455 0 : switch (Mnemonic[4]) {
456 : default: break;
457 : case 'c': // 4 strings to match.
458 0 : if (memcmp(Mnemonic.data()+5, "_f", 2))
459 : break;
460 0 : switch (Mnemonic[7]) {
461 : default: break;
462 : case '1': // 2 strings to match.
463 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
464 : break;
465 0 : switch (Mnemonic[11]) {
466 : default: break;
467 : case '3': // 1 string to match.
468 0 : if (Mnemonic[12] != '2')
469 : break;
470 0 : Mnemonic = "v_mac_f16"; // "v_mac_f16_e32"
471 0 : return;
472 : case '6': // 1 string to match.
473 0 : if (Mnemonic[12] != '4')
474 : break;
475 0 : Mnemonic = "v_mac_f16"; // "v_mac_f16_e64"
476 0 : return;
477 : }
478 : break;
479 : case '3': // 2 strings to match.
480 0 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
481 : break;
482 0 : switch (Mnemonic[11]) {
483 : default: break;
484 : case '3': // 1 string to match.
485 0 : if (Mnemonic[12] != '2')
486 : break;
487 0 : Mnemonic = "v_mac_f32"; // "v_mac_f32_e32"
488 0 : return;
489 : case '6': // 1 string to match.
490 0 : if (Mnemonic[12] != '4')
491 : break;
492 0 : Mnemonic = "v_mac_f32"; // "v_mac_f32_e64"
493 0 : return;
494 : }
495 : break;
496 : }
497 : break;
498 : case 'd': // 1 string to match.
499 0 : if (memcmp(Mnemonic.data()+5, "_f32_e64", 8))
500 : break;
501 0 : Mnemonic = "v_mad_f32"; // "v_mad_f32_e64"
502 0 : return;
503 : case 'x': // 13 strings to match.
504 0 : if (Mnemonic[5] != '_')
505 : break;
506 0 : switch (Mnemonic[6]) {
507 : default: break;
508 : case 'f': // 5 strings to match.
509 0 : switch (Mnemonic[7]) {
510 : default: break;
511 : case '1': // 2 strings to match.
512 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
513 : break;
514 0 : switch (Mnemonic[11]) {
515 : default: break;
516 : case '3': // 1 string to match.
517 0 : if (Mnemonic[12] != '2')
518 : break;
519 0 : Mnemonic = "v_max_f16"; // "v_max_f16_e32"
520 0 : return;
521 : case '6': // 1 string to match.
522 0 : if (Mnemonic[12] != '4')
523 : break;
524 0 : Mnemonic = "v_max_f16"; // "v_max_f16_e64"
525 0 : return;
526 : }
527 : break;
528 : case '3': // 2 strings to match.
529 0 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
530 : break;
531 0 : switch (Mnemonic[11]) {
532 : default: break;
533 : case '3': // 1 string to match.
534 0 : if (Mnemonic[12] != '2')
535 : break;
536 0 : Mnemonic = "v_max_f32"; // "v_max_f32_e32"
537 0 : return;
538 : case '6': // 1 string to match.
539 0 : if (Mnemonic[12] != '4')
540 : break;
541 0 : Mnemonic = "v_max_f32"; // "v_max_f32_e64"
542 0 : return;
543 : }
544 : break;
545 : case '6': // 1 string to match.
546 0 : if (memcmp(Mnemonic.data()+8, "4_e64", 5))
547 : break;
548 0 : Mnemonic = "v_max_f64"; // "v_max_f64_e64"
549 0 : return;
550 : }
551 : break;
552 : case 'i': // 4 strings to match.
553 0 : switch (Mnemonic[7]) {
554 : default: break;
555 : case '1': // 2 strings to match.
556 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
557 : break;
558 0 : switch (Mnemonic[11]) {
559 : default: break;
560 : case '3': // 1 string to match.
561 0 : if (Mnemonic[12] != '2')
562 : break;
563 0 : Mnemonic = "v_max_i16"; // "v_max_i16_e32"
564 0 : return;
565 : case '6': // 1 string to match.
566 0 : if (Mnemonic[12] != '4')
567 : break;
568 0 : Mnemonic = "v_max_i16"; // "v_max_i16_e64"
569 0 : return;
570 : }
571 : break;
572 : case '3': // 2 strings to match.
573 0 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
574 : break;
575 0 : switch (Mnemonic[11]) {
576 : default: break;
577 : case '3': // 1 string to match.
578 0 : if (Mnemonic[12] != '2')
579 : break;
580 0 : Mnemonic = "v_max_i32"; // "v_max_i32_e32"
581 0 : return;
582 : case '6': // 1 string to match.
583 0 : if (Mnemonic[12] != '4')
584 : break;
585 0 : Mnemonic = "v_max_i32"; // "v_max_i32_e64"
586 0 : return;
587 : }
588 : break;
589 : }
590 : break;
591 : case 'u': // 4 strings to match.
592 0 : switch (Mnemonic[7]) {
593 : default: break;
594 : case '1': // 2 strings to match.
595 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
596 : break;
597 0 : switch (Mnemonic[11]) {
598 : default: break;
599 : case '3': // 1 string to match.
600 0 : if (Mnemonic[12] != '2')
601 : break;
602 0 : Mnemonic = "v_max_u16"; // "v_max_u16_e32"
603 0 : return;
604 : case '6': // 1 string to match.
605 0 : if (Mnemonic[12] != '4')
606 : break;
607 0 : Mnemonic = "v_max_u16"; // "v_max_u16_e64"
608 0 : return;
609 : }
610 : break;
611 : case '3': // 2 strings to match.
612 0 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
613 : break;
614 0 : switch (Mnemonic[11]) {
615 : default: break;
616 : case '3': // 1 string to match.
617 0 : if (Mnemonic[12] != '2')
618 : break;
619 0 : Mnemonic = "v_max_u32"; // "v_max_u32_e32"
620 0 : return;
621 : case '6': // 1 string to match.
622 0 : if (Mnemonic[12] != '4')
623 : break;
624 0 : Mnemonic = "v_max_u32"; // "v_max_u32_e64"
625 0 : return;
626 : }
627 : break;
628 : }
629 : break;
630 : }
631 : break;
632 : }
633 : break;
634 : case 'i': // 13 strings to match.
635 8 : if (memcmp(Mnemonic.data()+4, "n_", 2))
636 : break;
637 16 : switch (Mnemonic[6]) {
638 : default: break;
639 : case 'f': // 5 strings to match.
640 16 : switch (Mnemonic[7]) {
641 : default: break;
642 : case '1': // 2 strings to match.
643 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
644 : break;
645 0 : switch (Mnemonic[11]) {
646 : default: break;
647 : case '3': // 1 string to match.
648 0 : if (Mnemonic[12] != '2')
649 : break;
650 0 : Mnemonic = "v_min_f16"; // "v_min_f16_e32"
651 0 : return;
652 : case '6': // 1 string to match.
653 0 : if (Mnemonic[12] != '4')
654 : break;
655 0 : Mnemonic = "v_min_f16"; // "v_min_f16_e64"
656 0 : return;
657 : }
658 : break;
659 : case '3': // 2 strings to match.
660 8 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
661 : break;
662 16 : switch (Mnemonic[11]) {
663 : default: break;
664 : case '3': // 1 string to match.
665 16 : if (Mnemonic[12] != '2')
666 : break;
667 8 : Mnemonic = "v_min_f32"; // "v_min_f32_e32"
668 8 : return;
669 : case '6': // 1 string to match.
670 0 : if (Mnemonic[12] != '4')
671 : break;
672 0 : Mnemonic = "v_min_f32"; // "v_min_f32_e64"
673 0 : return;
674 : }
675 : break;
676 : case '6': // 1 string to match.
677 0 : if (memcmp(Mnemonic.data()+8, "4_e64", 5))
678 : break;
679 0 : Mnemonic = "v_min_f64"; // "v_min_f64_e64"
680 0 : return;
681 : }
682 : break;
683 : case 'i': // 4 strings to match.
684 0 : switch (Mnemonic[7]) {
685 : default: break;
686 : case '1': // 2 strings to match.
687 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
688 : break;
689 0 : switch (Mnemonic[11]) {
690 : default: break;
691 : case '3': // 1 string to match.
692 0 : if (Mnemonic[12] != '2')
693 : break;
694 0 : Mnemonic = "v_min_i16"; // "v_min_i16_e32"
695 0 : return;
696 : case '6': // 1 string to match.
697 0 : if (Mnemonic[12] != '4')
698 : break;
699 0 : Mnemonic = "v_min_i16"; // "v_min_i16_e64"
700 0 : return;
701 : }
702 : break;
703 : case '3': // 2 strings to match.
704 0 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
705 : break;
706 0 : switch (Mnemonic[11]) {
707 : default: break;
708 : case '3': // 1 string to match.
709 0 : if (Mnemonic[12] != '2')
710 : break;
711 0 : Mnemonic = "v_min_i32"; // "v_min_i32_e32"
712 0 : return;
713 : case '6': // 1 string to match.
714 0 : if (Mnemonic[12] != '4')
715 : break;
716 0 : Mnemonic = "v_min_i32"; // "v_min_i32_e64"
717 0 : return;
718 : }
719 : break;
720 : }
721 : break;
722 : case 'u': // 4 strings to match.
723 0 : switch (Mnemonic[7]) {
724 : default: break;
725 : case '1': // 2 strings to match.
726 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
727 : break;
728 0 : switch (Mnemonic[11]) {
729 : default: break;
730 : case '3': // 1 string to match.
731 0 : if (Mnemonic[12] != '2')
732 : break;
733 0 : Mnemonic = "v_min_u16"; // "v_min_u16_e32"
734 0 : return;
735 : case '6': // 1 string to match.
736 0 : if (Mnemonic[12] != '4')
737 : break;
738 0 : Mnemonic = "v_min_u16"; // "v_min_u16_e64"
739 0 : return;
740 : }
741 : break;
742 : case '3': // 2 strings to match.
743 0 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
744 : break;
745 0 : switch (Mnemonic[11]) {
746 : default: break;
747 : case '3': // 1 string to match.
748 0 : if (Mnemonic[12] != '2')
749 : break;
750 0 : Mnemonic = "v_min_u32"; // "v_min_u32_e32"
751 0 : return;
752 : case '6': // 1 string to match.
753 0 : if (Mnemonic[12] != '4')
754 : break;
755 0 : Mnemonic = "v_min_u32"; // "v_min_u32_e64"
756 0 : return;
757 : }
758 : break;
759 : }
760 : break;
761 : }
762 : break;
763 : case 'o': // 2 strings to match.
764 24 : if (memcmp(Mnemonic.data()+4, "v_b32_e", 7))
765 : break;
766 0 : switch (Mnemonic[11]) {
767 : default: break;
768 : case '3': // 1 string to match.
769 0 : if (Mnemonic[12] != '2')
770 : break;
771 0 : Mnemonic = "v_mov_b32"; // "v_mov_b32_e32"
772 0 : return;
773 : case '6': // 1 string to match.
774 0 : if (Mnemonic[12] != '4')
775 : break;
776 0 : Mnemonic = "v_mov_b32"; // "v_mov_b32_e64"
777 0 : return;
778 : }
779 : break;
780 : case 'u': // 5 strings to match.
781 108 : if (memcmp(Mnemonic.data()+4, "l_f", 3))
782 : break;
783 0 : switch (Mnemonic[7]) {
784 : default: break;
785 : case '1': // 2 strings to match.
786 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
787 : break;
788 0 : switch (Mnemonic[11]) {
789 : default: break;
790 : case '3': // 1 string to match.
791 0 : if (Mnemonic[12] != '2')
792 : break;
793 0 : Mnemonic = "v_mul_f16"; // "v_mul_f16_e32"
794 0 : return;
795 : case '6': // 1 string to match.
796 0 : if (Mnemonic[12] != '4')
797 : break;
798 0 : Mnemonic = "v_mul_f16"; // "v_mul_f16_e64"
799 0 : return;
800 : }
801 : break;
802 : case '3': // 2 strings to match.
803 0 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
804 : break;
805 0 : switch (Mnemonic[11]) {
806 : default: break;
807 : case '3': // 1 string to match.
808 0 : if (Mnemonic[12] != '2')
809 : break;
810 0 : Mnemonic = "v_mul_f32"; // "v_mul_f32_e32"
811 0 : return;
812 : case '6': // 1 string to match.
813 0 : if (Mnemonic[12] != '4')
814 : break;
815 0 : Mnemonic = "v_mul_f32"; // "v_mul_f32_e64"
816 0 : return;
817 : }
818 : break;
819 : case '6': // 1 string to match.
820 0 : if (memcmp(Mnemonic.data()+8, "4_e64", 5))
821 : break;
822 0 : Mnemonic = "v_mul_f64"; // "v_mul_f64_e64"
823 0 : return;
824 : }
825 : break;
826 : }
827 : break;
828 : case 'n': // 2 strings to match.
829 0 : if (memcmp(Mnemonic.data()+3, "ot_b32_e", 8))
830 : break;
831 0 : switch (Mnemonic[11]) {
832 : default: break;
833 : case '3': // 1 string to match.
834 0 : if (Mnemonic[12] != '2')
835 : break;
836 0 : Mnemonic = "v_not_b32"; // "v_not_b32_e32"
837 0 : return;
838 : case '6': // 1 string to match.
839 0 : if (Mnemonic[12] != '4')
840 : break;
841 0 : Mnemonic = "v_not_b32"; // "v_not_b32_e64"
842 0 : return;
843 : }
844 : break;
845 : case 'r': // 12 strings to match.
846 16 : switch (Mnemonic[3]) {
847 : default: break;
848 : case 'c': // 6 strings to match.
849 0 : if (memcmp(Mnemonic.data()+4, "p_f", 3))
850 : break;
851 0 : switch (Mnemonic[7]) {
852 : default: break;
853 : case '1': // 2 strings to match.
854 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
855 : break;
856 0 : switch (Mnemonic[11]) {
857 : default: break;
858 : case '3': // 1 string to match.
859 0 : if (Mnemonic[12] != '2')
860 : break;
861 0 : Mnemonic = "v_rcp_f16"; // "v_rcp_f16_e32"
862 0 : return;
863 : case '6': // 1 string to match.
864 0 : if (Mnemonic[12] != '4')
865 : break;
866 0 : Mnemonic = "v_rcp_f16"; // "v_rcp_f16_e64"
867 0 : return;
868 : }
869 : break;
870 : case '3': // 2 strings to match.
871 0 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
872 : break;
873 0 : switch (Mnemonic[11]) {
874 : default: break;
875 : case '3': // 1 string to match.
876 0 : if (Mnemonic[12] != '2')
877 : break;
878 0 : Mnemonic = "v_rcp_f32"; // "v_rcp_f32_e32"
879 0 : return;
880 : case '6': // 1 string to match.
881 0 : if (Mnemonic[12] != '4')
882 : break;
883 0 : Mnemonic = "v_rcp_f32"; // "v_rcp_f32_e64"
884 0 : return;
885 : }
886 : break;
887 : case '6': // 2 strings to match.
888 0 : if (memcmp(Mnemonic.data()+8, "4_e", 3))
889 : break;
890 0 : switch (Mnemonic[11]) {
891 : default: break;
892 : case '3': // 1 string to match.
893 0 : if (Mnemonic[12] != '2')
894 : break;
895 0 : Mnemonic = "v_rcp_f64"; // "v_rcp_f64_e32"
896 0 : return;
897 : case '6': // 1 string to match.
898 0 : if (Mnemonic[12] != '4')
899 : break;
900 0 : Mnemonic = "v_rcp_f64"; // "v_rcp_f64_e64"
901 0 : return;
902 : }
903 : break;
904 : }
905 : break;
906 : case 's': // 6 strings to match.
907 8 : if (memcmp(Mnemonic.data()+4, "q_f", 3))
908 : break;
909 16 : switch (Mnemonic[7]) {
910 : default: break;
911 : case '1': // 2 strings to match.
912 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
913 : break;
914 0 : switch (Mnemonic[11]) {
915 : default: break;
916 : case '3': // 1 string to match.
917 0 : if (Mnemonic[12] != '2')
918 : break;
919 0 : Mnemonic = "v_rsq_f16"; // "v_rsq_f16_e32"
920 0 : return;
921 : case '6': // 1 string to match.
922 0 : if (Mnemonic[12] != '4')
923 : break;
924 0 : Mnemonic = "v_rsq_f16"; // "v_rsq_f16_e64"
925 0 : return;
926 : }
927 : break;
928 : case '3': // 2 strings to match.
929 8 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
930 : break;
931 16 : switch (Mnemonic[11]) {
932 : default: break;
933 : case '3': // 1 string to match.
934 16 : if (Mnemonic[12] != '2')
935 : break;
936 8 : Mnemonic = "v_rsq_f32"; // "v_rsq_f32_e32"
937 8 : return;
938 : case '6': // 1 string to match.
939 0 : if (Mnemonic[12] != '4')
940 : break;
941 0 : Mnemonic = "v_rsq_f32"; // "v_rsq_f32_e64"
942 0 : return;
943 : }
944 : break;
945 : case '6': // 2 strings to match.
946 0 : if (memcmp(Mnemonic.data()+8, "4_e", 3))
947 : break;
948 0 : switch (Mnemonic[11]) {
949 : default: break;
950 : case '3': // 1 string to match.
951 0 : if (Mnemonic[12] != '2')
952 : break;
953 0 : Mnemonic = "v_rsq_f64"; // "v_rsq_f64_e32"
954 0 : return;
955 : case '6': // 1 string to match.
956 0 : if (Mnemonic[12] != '4')
957 : break;
958 0 : Mnemonic = "v_rsq_f64"; // "v_rsq_f64_e64"
959 0 : return;
960 : }
961 : break;
962 : }
963 : break;
964 : }
965 : break;
966 : case 's': // 13 strings to match.
967 16 : switch (Mnemonic[3]) {
968 : default: break;
969 : case 'a': // 1 string to match.
970 0 : if (memcmp(Mnemonic.data()+4, "d_u32_e64", 9))
971 : break;
972 0 : Mnemonic = "v_sad_u32"; // "v_sad_u32_e64"
973 0 : return;
974 : case 'i': // 4 strings to match.
975 0 : if (memcmp(Mnemonic.data()+4, "n_f", 3))
976 : break;
977 0 : switch (Mnemonic[7]) {
978 : default: break;
979 : case '1': // 2 strings to match.
980 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
981 : break;
982 0 : switch (Mnemonic[11]) {
983 : default: break;
984 : case '3': // 1 string to match.
985 0 : if (Mnemonic[12] != '2')
986 : break;
987 0 : Mnemonic = "v_sin_f16"; // "v_sin_f16_e32"
988 0 : return;
989 : case '6': // 1 string to match.
990 0 : if (Mnemonic[12] != '4')
991 : break;
992 0 : Mnemonic = "v_sin_f16"; // "v_sin_f16_e64"
993 0 : return;
994 : }
995 : break;
996 : case '3': // 2 strings to match.
997 0 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
998 : break;
999 0 : switch (Mnemonic[11]) {
1000 : default: break;
1001 : case '3': // 1 string to match.
1002 0 : if (Mnemonic[12] != '2')
1003 : break;
1004 0 : Mnemonic = "v_sin_f32"; // "v_sin_f32_e32"
1005 0 : return;
1006 : case '6': // 1 string to match.
1007 0 : if (Mnemonic[12] != '4')
1008 : break;
1009 0 : Mnemonic = "v_sin_f32"; // "v_sin_f32_e64"
1010 0 : return;
1011 : }
1012 : break;
1013 : }
1014 : break;
1015 : case 'u': // 8 strings to match.
1016 8 : if (memcmp(Mnemonic.data()+4, "b_", 2))
1017 : break;
1018 0 : switch (Mnemonic[6]) {
1019 : default: break;
1020 : case 'f': // 4 strings to match.
1021 0 : switch (Mnemonic[7]) {
1022 : default: break;
1023 : case '1': // 2 strings to match.
1024 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
1025 : break;
1026 0 : switch (Mnemonic[11]) {
1027 : default: break;
1028 : case '3': // 1 string to match.
1029 0 : if (Mnemonic[12] != '2')
1030 : break;
1031 0 : Mnemonic = "v_sub_f16"; // "v_sub_f16_e32"
1032 0 : return;
1033 : case '6': // 1 string to match.
1034 0 : if (Mnemonic[12] != '4')
1035 : break;
1036 0 : Mnemonic = "v_sub_f16"; // "v_sub_f16_e64"
1037 0 : return;
1038 : }
1039 : break;
1040 : case '3': // 2 strings to match.
1041 0 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
1042 : break;
1043 0 : switch (Mnemonic[11]) {
1044 : default: break;
1045 : case '3': // 1 string to match.
1046 0 : if (Mnemonic[12] != '2')
1047 : break;
1048 0 : Mnemonic = "v_sub_f32"; // "v_sub_f32_e32"
1049 0 : return;
1050 : case '6': // 1 string to match.
1051 0 : if (Mnemonic[12] != '4')
1052 : break;
1053 0 : Mnemonic = "v_sub_f32"; // "v_sub_f32_e64"
1054 0 : return;
1055 : }
1056 : break;
1057 : }
1058 : break;
1059 : case 'i': // 2 strings to match.
1060 0 : if (memcmp(Mnemonic.data()+7, "32_e", 4))
1061 : break;
1062 0 : switch (Mnemonic[11]) {
1063 : default: break;
1064 : case '3': // 1 string to match.
1065 0 : if (Mnemonic[12] != '2')
1066 : break;
1067 0 : Mnemonic = "v_sub_i32"; // "v_sub_i32_e32"
1068 0 : return;
1069 : case '6': // 1 string to match.
1070 0 : if (Mnemonic[12] != '4')
1071 : break;
1072 0 : Mnemonic = "v_sub_i32"; // "v_sub_i32_e64"
1073 0 : return;
1074 : }
1075 : break;
1076 : case 'u': // 2 strings to match.
1077 0 : if (memcmp(Mnemonic.data()+7, "16_e", 4))
1078 : break;
1079 0 : switch (Mnemonic[11]) {
1080 : default: break;
1081 : case '3': // 1 string to match.
1082 0 : if (Mnemonic[12] != '2')
1083 : break;
1084 0 : Mnemonic = "v_sub_u16"; // "v_sub_u16_e32"
1085 0 : return;
1086 : case '6': // 1 string to match.
1087 0 : if (Mnemonic[12] != '4')
1088 : break;
1089 0 : Mnemonic = "v_sub_u16"; // "v_sub_u16_e64"
1090 0 : return;
1091 : }
1092 : break;
1093 : }
1094 : break;
1095 : }
1096 : break;
1097 : case 'x': // 2 strings to match.
1098 0 : if (memcmp(Mnemonic.data()+3, "or_b32_e", 8))
1099 : break;
1100 0 : switch (Mnemonic[11]) {
1101 : default: break;
1102 : case '3': // 1 string to match.
1103 0 : if (Mnemonic[12] != '2')
1104 : break;
1105 0 : Mnemonic = "v_xor_b32"; // "v_xor_b32_e32"
1106 0 : return;
1107 : case '6': // 1 string to match.
1108 0 : if (Mnemonic[12] != '4')
1109 : break;
1110 0 : Mnemonic = "v_xor_b32"; // "v_xor_b32_e64"
1111 0 : return;
1112 : }
1113 : break;
1114 : }
1115 : break;
1116 : case 14: // 40 strings to match.
1117 132 : if (memcmp(Mnemonic.data()+0, "v_", 2))
1118 : break;
1119 96 : switch (Mnemonic[2]) {
1120 : default: break;
1121 : case 'a': // 5 strings to match.
1122 0 : switch (Mnemonic[3]) {
1123 : default: break;
1124 : case 'd': // 2 strings to match.
1125 0 : if (memcmp(Mnemonic.data()+4, "dc_u32_e", 8))
1126 : break;
1127 0 : switch (Mnemonic[12]) {
1128 : default: break;
1129 : case '3': // 1 string to match.
1130 0 : if (Mnemonic[13] != '2')
1131 : break;
1132 0 : Mnemonic = "v_addc_u32"; // "v_addc_u32_e32"
1133 0 : return;
1134 : case '6': // 1 string to match.
1135 0 : if (Mnemonic[13] != '4')
1136 : break;
1137 0 : Mnemonic = "v_addc_u32"; // "v_addc_u32_e64"
1138 0 : return;
1139 : }
1140 : break;
1141 : case 's': // 3 strings to match.
1142 0 : if (memcmp(Mnemonic.data()+4, "hr_i", 4))
1143 : break;
1144 0 : switch (Mnemonic[8]) {
1145 : default: break;
1146 : case '3': // 2 strings to match.
1147 0 : if (memcmp(Mnemonic.data()+9, "2_e", 3))
1148 : break;
1149 0 : switch (Mnemonic[12]) {
1150 : default: break;
1151 : case '3': // 1 string to match.
1152 0 : if (Mnemonic[13] != '2')
1153 : break;
1154 0 : Mnemonic = "v_ashr_i32"; // "v_ashr_i32_e32"
1155 0 : return;
1156 : case '6': // 1 string to match.
1157 0 : if (Mnemonic[13] != '4')
1158 : break;
1159 0 : Mnemonic = "v_ashr_i32"; // "v_ashr_i32_e64"
1160 0 : return;
1161 : }
1162 : break;
1163 : case '6': // 1 string to match.
1164 0 : if (memcmp(Mnemonic.data()+9, "4_e64", 5))
1165 : break;
1166 0 : Mnemonic = "v_ashr_i64"; // "v_ashr_i64_e64"
1167 0 : return;
1168 : }
1169 : break;
1170 : }
1171 : break;
1172 : case 'c': // 6 strings to match.
1173 8 : if (memcmp(Mnemonic.data()+3, "eil_f", 5))
1174 : break;
1175 16 : switch (Mnemonic[8]) {
1176 : default: break;
1177 : case '1': // 2 strings to match.
1178 0 : if (memcmp(Mnemonic.data()+9, "6_e", 3))
1179 : break;
1180 0 : switch (Mnemonic[12]) {
1181 : default: break;
1182 : case '3': // 1 string to match.
1183 0 : if (Mnemonic[13] != '2')
1184 : break;
1185 0 : Mnemonic = "v_ceil_f16"; // "v_ceil_f16_e32"
1186 0 : return;
1187 : case '6': // 1 string to match.
1188 0 : if (Mnemonic[13] != '4')
1189 : break;
1190 0 : Mnemonic = "v_ceil_f16"; // "v_ceil_f16_e64"
1191 0 : return;
1192 : }
1193 : break;
1194 : case '3': // 2 strings to match.
1195 0 : if (memcmp(Mnemonic.data()+9, "2_e", 3))
1196 : break;
1197 0 : switch (Mnemonic[12]) {
1198 : default: break;
1199 : case '3': // 1 string to match.
1200 0 : if (Mnemonic[13] != '2')
1201 : break;
1202 0 : Mnemonic = "v_ceil_f32"; // "v_ceil_f32_e32"
1203 0 : return;
1204 : case '6': // 1 string to match.
1205 0 : if (Mnemonic[13] != '4')
1206 : break;
1207 0 : Mnemonic = "v_ceil_f32"; // "v_ceil_f32_e64"
1208 0 : return;
1209 : }
1210 : break;
1211 : case '6': // 2 strings to match.
1212 8 : if (memcmp(Mnemonic.data()+9, "4_e", 3))
1213 : break;
1214 16 : switch (Mnemonic[12]) {
1215 : default: break;
1216 : case '3': // 1 string to match.
1217 16 : if (Mnemonic[13] != '2')
1218 : break;
1219 8 : Mnemonic = "v_ceil_f64"; // "v_ceil_f64_e32"
1220 8 : return;
1221 : case '6': // 1 string to match.
1222 0 : if (Mnemonic[13] != '4')
1223 : break;
1224 0 : Mnemonic = "v_ceil_f64"; // "v_ceil_f64_e64"
1225 0 : return;
1226 : }
1227 : break;
1228 : }
1229 : break;
1230 : case 'f': // 6 strings to match.
1231 8 : if (memcmp(Mnemonic.data()+3, "fb", 2))
1232 : break;
1233 16 : switch (Mnemonic[5]) {
1234 : default: break;
1235 : case 'h': // 4 strings to match.
1236 16 : if (Mnemonic[6] != '_')
1237 : break;
1238 16 : switch (Mnemonic[7]) {
1239 : default: break;
1240 : case 'i': // 2 strings to match.
1241 8 : if (memcmp(Mnemonic.data()+8, "32_e", 4))
1242 : break;
1243 16 : switch (Mnemonic[12]) {
1244 : default: break;
1245 : case '3': // 1 string to match.
1246 16 : if (Mnemonic[13] != '2')
1247 : break;
1248 8 : Mnemonic = "v_ffbh_i32"; // "v_ffbh_i32_e32"
1249 8 : return;
1250 : case '6': // 1 string to match.
1251 0 : if (Mnemonic[13] != '4')
1252 : break;
1253 0 : Mnemonic = "v_ffbh_i32"; // "v_ffbh_i32_e64"
1254 0 : return;
1255 : }
1256 : break;
1257 : case 'u': // 2 strings to match.
1258 0 : if (memcmp(Mnemonic.data()+8, "32_e", 4))
1259 : break;
1260 0 : switch (Mnemonic[12]) {
1261 : default: break;
1262 : case '3': // 1 string to match.
1263 0 : if (Mnemonic[13] != '2')
1264 : break;
1265 0 : Mnemonic = "v_ffbh_u32"; // "v_ffbh_u32_e32"
1266 0 : return;
1267 : case '6': // 1 string to match.
1268 0 : if (Mnemonic[13] != '4')
1269 : break;
1270 0 : Mnemonic = "v_ffbh_u32"; // "v_ffbh_u32_e64"
1271 0 : return;
1272 : }
1273 : break;
1274 : }
1275 : break;
1276 : case 'l': // 2 strings to match.
1277 0 : if (memcmp(Mnemonic.data()+6, "_b32_e", 6))
1278 : break;
1279 0 : switch (Mnemonic[12]) {
1280 : default: break;
1281 : case '3': // 1 string to match.
1282 0 : if (Mnemonic[13] != '2')
1283 : break;
1284 0 : Mnemonic = "v_ffbl_b32"; // "v_ffbl_b32_e32"
1285 0 : return;
1286 : case '6': // 1 string to match.
1287 0 : if (Mnemonic[13] != '4')
1288 : break;
1289 0 : Mnemonic = "v_ffbl_b32"; // "v_ffbl_b32_e64"
1290 0 : return;
1291 : }
1292 : break;
1293 : }
1294 : break;
1295 : case 'l': // 6 strings to match.
1296 8 : if (memcmp(Mnemonic.data()+3, "sh", 2))
1297 : break;
1298 16 : switch (Mnemonic[5]) {
1299 : default: break;
1300 : case 'l': // 3 strings to match.
1301 8 : if (memcmp(Mnemonic.data()+6, "_b", 2))
1302 : break;
1303 16 : switch (Mnemonic[8]) {
1304 : default: break;
1305 : case '3': // 2 strings to match.
1306 8 : if (memcmp(Mnemonic.data()+9, "2_e", 3))
1307 : break;
1308 16 : switch (Mnemonic[12]) {
1309 : default: break;
1310 : case '3': // 1 string to match.
1311 16 : if (Mnemonic[13] != '2')
1312 : break;
1313 8 : Mnemonic = "v_lshl_b32"; // "v_lshl_b32_e32"
1314 8 : return;
1315 : case '6': // 1 string to match.
1316 0 : if (Mnemonic[13] != '4')
1317 : break;
1318 0 : Mnemonic = "v_lshl_b32"; // "v_lshl_b32_e64"
1319 0 : return;
1320 : }
1321 : break;
1322 : case '6': // 1 string to match.
1323 0 : if (memcmp(Mnemonic.data()+9, "4_e64", 5))
1324 : break;
1325 0 : Mnemonic = "v_lshl_b64"; // "v_lshl_b64_e64"
1326 0 : return;
1327 : }
1328 : break;
1329 : case 'r': // 3 strings to match.
1330 0 : if (memcmp(Mnemonic.data()+6, "_b", 2))
1331 : break;
1332 0 : switch (Mnemonic[8]) {
1333 : default: break;
1334 : case '3': // 2 strings to match.
1335 0 : if (memcmp(Mnemonic.data()+9, "2_e", 3))
1336 : break;
1337 0 : switch (Mnemonic[12]) {
1338 : default: break;
1339 : case '3': // 1 string to match.
1340 0 : if (Mnemonic[13] != '2')
1341 : break;
1342 0 : Mnemonic = "v_lshr_b32"; // "v_lshr_b32_e32"
1343 0 : return;
1344 : case '6': // 1 string to match.
1345 0 : if (Mnemonic[13] != '4')
1346 : break;
1347 0 : Mnemonic = "v_lshr_b32"; // "v_lshr_b32_e64"
1348 0 : return;
1349 : }
1350 : break;
1351 : case '6': // 1 string to match.
1352 0 : if (memcmp(Mnemonic.data()+9, "4_e64", 5))
1353 : break;
1354 0 : Mnemonic = "v_lshr_b64"; // "v_lshr_b64_e64"
1355 0 : return;
1356 : }
1357 : break;
1358 : }
1359 : break;
1360 : case 'm': // 9 strings to match.
1361 16 : switch (Mnemonic[3]) {
1362 : default: break;
1363 : case 'a': // 3 strings to match.
1364 0 : if (memcmp(Mnemonic.data()+4, "x3_", 3))
1365 : break;
1366 0 : switch (Mnemonic[7]) {
1367 : default: break;
1368 : case 'f': // 1 string to match.
1369 0 : if (memcmp(Mnemonic.data()+8, "32_e64", 6))
1370 : break;
1371 0 : Mnemonic = "v_max3_f32"; // "v_max3_f32_e64"
1372 0 : return;
1373 : case 'i': // 1 string to match.
1374 0 : if (memcmp(Mnemonic.data()+8, "32_e64", 6))
1375 : break;
1376 0 : Mnemonic = "v_max3_i32"; // "v_max3_i32_e64"
1377 0 : return;
1378 : case 'u': // 1 string to match.
1379 0 : if (memcmp(Mnemonic.data()+8, "32_e64", 6))
1380 : break;
1381 0 : Mnemonic = "v_max3_u32"; // "v_max3_u32_e64"
1382 0 : return;
1383 : }
1384 : break;
1385 : case 'e': // 3 strings to match.
1386 0 : if (memcmp(Mnemonic.data()+4, "d3_", 3))
1387 : break;
1388 0 : switch (Mnemonic[7]) {
1389 : default: break;
1390 : case 'f': // 1 string to match.
1391 0 : if (memcmp(Mnemonic.data()+8, "32_e64", 6))
1392 : break;
1393 0 : Mnemonic = "v_med3_f32"; // "v_med3_f32_e64"
1394 0 : return;
1395 : case 'i': // 1 string to match.
1396 0 : if (memcmp(Mnemonic.data()+8, "32_e64", 6))
1397 : break;
1398 0 : Mnemonic = "v_med3_i32"; // "v_med3_i32_e64"
1399 0 : return;
1400 : case 'u': // 1 string to match.
1401 0 : if (memcmp(Mnemonic.data()+8, "32_e64", 6))
1402 : break;
1403 0 : Mnemonic = "v_med3_u32"; // "v_med3_u32_e64"
1404 0 : return;
1405 : }
1406 : break;
1407 : case 'i': // 3 strings to match.
1408 0 : if (memcmp(Mnemonic.data()+4, "n3_", 3))
1409 : break;
1410 0 : switch (Mnemonic[7]) {
1411 : default: break;
1412 : case 'f': // 1 string to match.
1413 0 : if (memcmp(Mnemonic.data()+8, "32_e64", 6))
1414 : break;
1415 0 : Mnemonic = "v_min3_f32"; // "v_min3_f32_e64"
1416 0 : return;
1417 : case 'i': // 1 string to match.
1418 0 : if (memcmp(Mnemonic.data()+8, "32_e64", 6))
1419 : break;
1420 0 : Mnemonic = "v_min3_i32"; // "v_min3_i32_e64"
1421 0 : return;
1422 : case 'u': // 1 string to match.
1423 0 : if (memcmp(Mnemonic.data()+8, "32_e64", 6))
1424 : break;
1425 0 : Mnemonic = "v_min3_u32"; // "v_min3_u32_e64"
1426 0 : return;
1427 : }
1428 : break;
1429 : }
1430 : break;
1431 : case 's': // 8 strings to match.
1432 0 : switch (Mnemonic[3]) {
1433 : default: break;
1434 : case 'q': // 6 strings to match.
1435 0 : if (memcmp(Mnemonic.data()+4, "rt_f", 4))
1436 : break;
1437 0 : switch (Mnemonic[8]) {
1438 : default: break;
1439 : case '1': // 2 strings to match.
1440 0 : if (memcmp(Mnemonic.data()+9, "6_e", 3))
1441 : break;
1442 0 : switch (Mnemonic[12]) {
1443 : default: break;
1444 : case '3': // 1 string to match.
1445 0 : if (Mnemonic[13] != '2')
1446 : break;
1447 0 : Mnemonic = "v_sqrt_f16"; // "v_sqrt_f16_e32"
1448 0 : return;
1449 : case '6': // 1 string to match.
1450 0 : if (Mnemonic[13] != '4')
1451 : break;
1452 0 : Mnemonic = "v_sqrt_f16"; // "v_sqrt_f16_e64"
1453 0 : return;
1454 : }
1455 : break;
1456 : case '3': // 2 strings to match.
1457 0 : if (memcmp(Mnemonic.data()+9, "2_e", 3))
1458 : break;
1459 0 : switch (Mnemonic[12]) {
1460 : default: break;
1461 : case '3': // 1 string to match.
1462 0 : if (Mnemonic[13] != '2')
1463 : break;
1464 0 : Mnemonic = "v_sqrt_f32"; // "v_sqrt_f32_e32"
1465 0 : return;
1466 : case '6': // 1 string to match.
1467 0 : if (Mnemonic[13] != '4')
1468 : break;
1469 0 : Mnemonic = "v_sqrt_f32"; // "v_sqrt_f32_e64"
1470 0 : return;
1471 : }
1472 : break;
1473 : case '6': // 2 strings to match.
1474 0 : if (memcmp(Mnemonic.data()+9, "4_e", 3))
1475 : break;
1476 0 : switch (Mnemonic[12]) {
1477 : default: break;
1478 : case '3': // 1 string to match.
1479 0 : if (Mnemonic[13] != '2')
1480 : break;
1481 0 : Mnemonic = "v_sqrt_f64"; // "v_sqrt_f64_e32"
1482 0 : return;
1483 : case '6': // 1 string to match.
1484 0 : if (Mnemonic[13] != '4')
1485 : break;
1486 0 : Mnemonic = "v_sqrt_f64"; // "v_sqrt_f64_e64"
1487 0 : return;
1488 : }
1489 : break;
1490 : }
1491 : break;
1492 : case 'u': // 2 strings to match.
1493 0 : if (memcmp(Mnemonic.data()+4, "bb_u32_e", 8))
1494 : break;
1495 0 : switch (Mnemonic[12]) {
1496 : default: break;
1497 : case '3': // 1 string to match.
1498 0 : if (Mnemonic[13] != '2')
1499 : break;
1500 0 : Mnemonic = "v_subb_u32"; // "v_subb_u32_e32"
1501 0 : return;
1502 : case '6': // 1 string to match.
1503 0 : if (Mnemonic[13] != '4')
1504 : break;
1505 0 : Mnemonic = "v_subb_u32"; // "v_subb_u32_e64"
1506 0 : return;
1507 : }
1508 : break;
1509 : }
1510 : break;
1511 : }
1512 : break;
1513 : case 15: // 63 strings to match.
1514 118 : if (memcmp(Mnemonic.data()+0, "v_", 2))
1515 : break;
1516 184 : switch (Mnemonic[2]) {
1517 : default: break;
1518 : case 'b': // 2 strings to match.
1519 0 : if (memcmp(Mnemonic.data()+3, "frev_b32_e", 10))
1520 : break;
1521 0 : switch (Mnemonic[13]) {
1522 : default: break;
1523 : case '3': // 1 string to match.
1524 0 : if (Mnemonic[14] != '2')
1525 : break;
1526 0 : Mnemonic = "v_bfrev_b32"; // "v_bfrev_b32_e32"
1527 0 : return;
1528 : case '6': // 1 string to match.
1529 0 : if (Mnemonic[14] != '4')
1530 : break;
1531 0 : Mnemonic = "v_bfrev_b32"; // "v_bfrev_b32_e64"
1532 0 : return;
1533 : }
1534 : break;
1535 : case 'c': // 28 strings to match.
1536 0 : if (memcmp(Mnemonic.data()+3, "mp_", 3))
1537 : break;
1538 0 : switch (Mnemonic[6]) {
1539 : default: break;
1540 : case 'f': // 12 strings to match.
1541 0 : if (Mnemonic[7] != '_')
1542 : break;
1543 0 : switch (Mnemonic[8]) {
1544 : default: break;
1545 : case 'f': // 4 strings to match.
1546 0 : switch (Mnemonic[9]) {
1547 : default: break;
1548 : case '3': // 2 strings to match.
1549 0 : if (memcmp(Mnemonic.data()+10, "2_e", 3))
1550 : break;
1551 0 : switch (Mnemonic[13]) {
1552 : default: break;
1553 : case '3': // 1 string to match.
1554 0 : if (Mnemonic[14] != '2')
1555 : break;
1556 0 : Mnemonic = "v_cmp_f_f32"; // "v_cmp_f_f32_e32"
1557 0 : return;
1558 : case '6': // 1 string to match.
1559 0 : if (Mnemonic[14] != '4')
1560 : break;
1561 0 : Mnemonic = "v_cmp_f_f32"; // "v_cmp_f_f32_e64"
1562 0 : return;
1563 : }
1564 : break;
1565 : case '6': // 2 strings to match.
1566 0 : if (memcmp(Mnemonic.data()+10, "4_e", 3))
1567 : break;
1568 0 : switch (Mnemonic[13]) {
1569 : default: break;
1570 : case '3': // 1 string to match.
1571 0 : if (Mnemonic[14] != '2')
1572 : break;
1573 0 : Mnemonic = "v_cmp_f_f64"; // "v_cmp_f_f64_e32"
1574 0 : return;
1575 : case '6': // 1 string to match.
1576 0 : if (Mnemonic[14] != '4')
1577 : break;
1578 0 : Mnemonic = "v_cmp_f_f64"; // "v_cmp_f_f64_e64"
1579 0 : return;
1580 : }
1581 : break;
1582 : }
1583 : break;
1584 : case 'i': // 4 strings to match.
1585 0 : switch (Mnemonic[9]) {
1586 : default: break;
1587 : case '3': // 2 strings to match.
1588 0 : if (memcmp(Mnemonic.data()+10, "2_e", 3))
1589 : break;
1590 0 : switch (Mnemonic[13]) {
1591 : default: break;
1592 : case '3': // 1 string to match.
1593 0 : if (Mnemonic[14] != '2')
1594 : break;
1595 0 : Mnemonic = "v_cmp_f_i32"; // "v_cmp_f_i32_e32"
1596 0 : return;
1597 : case '6': // 1 string to match.
1598 0 : if (Mnemonic[14] != '4')
1599 : break;
1600 0 : Mnemonic = "v_cmp_f_i32"; // "v_cmp_f_i32_e64"
1601 0 : return;
1602 : }
1603 : break;
1604 : case '6': // 2 strings to match.
1605 0 : if (memcmp(Mnemonic.data()+10, "4_e", 3))
1606 : break;
1607 0 : switch (Mnemonic[13]) {
1608 : default: break;
1609 : case '3': // 1 string to match.
1610 0 : if (Mnemonic[14] != '2')
1611 : break;
1612 0 : Mnemonic = "v_cmp_f_i64"; // "v_cmp_f_i64_e32"
1613 0 : return;
1614 : case '6': // 1 string to match.
1615 0 : if (Mnemonic[14] != '4')
1616 : break;
1617 0 : Mnemonic = "v_cmp_f_i64"; // "v_cmp_f_i64_e64"
1618 0 : return;
1619 : }
1620 : break;
1621 : }
1622 : break;
1623 : case 'u': // 4 strings to match.
1624 0 : switch (Mnemonic[9]) {
1625 : default: break;
1626 : case '3': // 2 strings to match.
1627 0 : if (memcmp(Mnemonic.data()+10, "2_e", 3))
1628 : break;
1629 0 : switch (Mnemonic[13]) {
1630 : default: break;
1631 : case '3': // 1 string to match.
1632 0 : if (Mnemonic[14] != '2')
1633 : break;
1634 0 : Mnemonic = "v_cmp_f_u32"; // "v_cmp_f_u32_e32"
1635 0 : return;
1636 : case '6': // 1 string to match.
1637 0 : if (Mnemonic[14] != '4')
1638 : break;
1639 0 : Mnemonic = "v_cmp_f_u32"; // "v_cmp_f_u32_e64"
1640 0 : return;
1641 : }
1642 : break;
1643 : case '6': // 2 strings to match.
1644 0 : if (memcmp(Mnemonic.data()+10, "4_e", 3))
1645 : break;
1646 0 : switch (Mnemonic[13]) {
1647 : default: break;
1648 : case '3': // 1 string to match.
1649 0 : if (Mnemonic[14] != '2')
1650 : break;
1651 0 : Mnemonic = "v_cmp_f_u64"; // "v_cmp_f_u64_e32"
1652 0 : return;
1653 : case '6': // 1 string to match.
1654 0 : if (Mnemonic[14] != '4')
1655 : break;
1656 0 : Mnemonic = "v_cmp_f_u64"; // "v_cmp_f_u64_e64"
1657 0 : return;
1658 : }
1659 : break;
1660 : }
1661 : break;
1662 : }
1663 : break;
1664 : case 'o': // 4 strings to match.
1665 0 : if (memcmp(Mnemonic.data()+7, "_f", 2))
1666 : break;
1667 0 : switch (Mnemonic[9]) {
1668 : default: break;
1669 : case '3': // 2 strings to match.
1670 0 : if (memcmp(Mnemonic.data()+10, "2_e", 3))
1671 : break;
1672 0 : switch (Mnemonic[13]) {
1673 : default: break;
1674 : case '3': // 1 string to match.
1675 0 : if (Mnemonic[14] != '2')
1676 : break;
1677 0 : Mnemonic = "v_cmp_o_f32"; // "v_cmp_o_f32_e32"
1678 0 : return;
1679 : case '6': // 1 string to match.
1680 0 : if (Mnemonic[14] != '4')
1681 : break;
1682 0 : Mnemonic = "v_cmp_o_f32"; // "v_cmp_o_f32_e64"
1683 0 : return;
1684 : }
1685 : break;
1686 : case '6': // 2 strings to match.
1687 0 : if (memcmp(Mnemonic.data()+10, "4_e", 3))
1688 : break;
1689 0 : switch (Mnemonic[13]) {
1690 : default: break;
1691 : case '3': // 1 string to match.
1692 0 : if (Mnemonic[14] != '2')
1693 : break;
1694 0 : Mnemonic = "v_cmp_o_f64"; // "v_cmp_o_f64_e32"
1695 0 : return;
1696 : case '6': // 1 string to match.
1697 0 : if (Mnemonic[14] != '4')
1698 : break;
1699 0 : Mnemonic = "v_cmp_o_f64"; // "v_cmp_o_f64_e64"
1700 0 : return;
1701 : }
1702 : break;
1703 : }
1704 : break;
1705 : case 't': // 8 strings to match.
1706 0 : if (Mnemonic[7] != '_')
1707 : break;
1708 0 : switch (Mnemonic[8]) {
1709 : default: break;
1710 : case 'i': // 4 strings to match.
1711 0 : switch (Mnemonic[9]) {
1712 : default: break;
1713 : case '3': // 2 strings to match.
1714 0 : if (memcmp(Mnemonic.data()+10, "2_e", 3))
1715 : break;
1716 0 : switch (Mnemonic[13]) {
1717 : default: break;
1718 : case '3': // 1 string to match.
1719 0 : if (Mnemonic[14] != '2')
1720 : break;
1721 0 : Mnemonic = "v_cmp_t_i32"; // "v_cmp_t_i32_e32"
1722 0 : return;
1723 : case '6': // 1 string to match.
1724 0 : if (Mnemonic[14] != '4')
1725 : break;
1726 0 : Mnemonic = "v_cmp_t_i32"; // "v_cmp_t_i32_e64"
1727 0 : return;
1728 : }
1729 : break;
1730 : case '6': // 2 strings to match.
1731 0 : if (memcmp(Mnemonic.data()+10, "4_e", 3))
1732 : break;
1733 0 : switch (Mnemonic[13]) {
1734 : default: break;
1735 : case '3': // 1 string to match.
1736 0 : if (Mnemonic[14] != '2')
1737 : break;
1738 0 : Mnemonic = "v_cmp_t_i64"; // "v_cmp_t_i64_e32"
1739 0 : return;
1740 : case '6': // 1 string to match.
1741 0 : if (Mnemonic[14] != '4')
1742 : break;
1743 0 : Mnemonic = "v_cmp_t_i64"; // "v_cmp_t_i64_e64"
1744 0 : return;
1745 : }
1746 : break;
1747 : }
1748 : break;
1749 : case 'u': // 4 strings to match.
1750 0 : switch (Mnemonic[9]) {
1751 : default: break;
1752 : case '3': // 2 strings to match.
1753 0 : if (memcmp(Mnemonic.data()+10, "2_e", 3))
1754 : break;
1755 0 : switch (Mnemonic[13]) {
1756 : default: break;
1757 : case '3': // 1 string to match.
1758 0 : if (Mnemonic[14] != '2')
1759 : break;
1760 0 : Mnemonic = "v_cmp_t_u32"; // "v_cmp_t_u32_e32"
1761 0 : return;
1762 : case '6': // 1 string to match.
1763 0 : if (Mnemonic[14] != '4')
1764 : break;
1765 0 : Mnemonic = "v_cmp_t_u32"; // "v_cmp_t_u32_e64"
1766 0 : return;
1767 : }
1768 : break;
1769 : case '6': // 2 strings to match.
1770 0 : if (memcmp(Mnemonic.data()+10, "4_e", 3))
1771 : break;
1772 0 : switch (Mnemonic[13]) {
1773 : default: break;
1774 : case '3': // 1 string to match.
1775 0 : if (Mnemonic[14] != '2')
1776 : break;
1777 0 : Mnemonic = "v_cmp_t_u64"; // "v_cmp_t_u64_e32"
1778 0 : return;
1779 : case '6': // 1 string to match.
1780 0 : if (Mnemonic[14] != '4')
1781 : break;
1782 0 : Mnemonic = "v_cmp_t_u64"; // "v_cmp_t_u64_e64"
1783 0 : return;
1784 : }
1785 : break;
1786 : }
1787 : break;
1788 : }
1789 : break;
1790 : case 'u': // 4 strings to match.
1791 0 : if (memcmp(Mnemonic.data()+7, "_f", 2))
1792 : break;
1793 0 : switch (Mnemonic[9]) {
1794 : default: break;
1795 : case '3': // 2 strings to match.
1796 0 : if (memcmp(Mnemonic.data()+10, "2_e", 3))
1797 : break;
1798 0 : switch (Mnemonic[13]) {
1799 : default: break;
1800 : case '3': // 1 string to match.
1801 0 : if (Mnemonic[14] != '2')
1802 : break;
1803 0 : Mnemonic = "v_cmp_u_f32"; // "v_cmp_u_f32_e32"
1804 0 : return;
1805 : case '6': // 1 string to match.
1806 0 : if (Mnemonic[14] != '4')
1807 : break;
1808 0 : Mnemonic = "v_cmp_u_f32"; // "v_cmp_u_f32_e64"
1809 0 : return;
1810 : }
1811 : break;
1812 : case '6': // 2 strings to match.
1813 0 : if (memcmp(Mnemonic.data()+10, "4_e", 3))
1814 : break;
1815 0 : switch (Mnemonic[13]) {
1816 : default: break;
1817 : case '3': // 1 string to match.
1818 0 : if (Mnemonic[14] != '2')
1819 : break;
1820 0 : Mnemonic = "v_cmp_u_f64"; // "v_cmp_u_f64_e32"
1821 0 : return;
1822 : case '6': // 1 string to match.
1823 0 : if (Mnemonic[14] != '4')
1824 : break;
1825 0 : Mnemonic = "v_cmp_u_f64"; // "v_cmp_u_f64_e64"
1826 0 : return;
1827 : }
1828 : break;
1829 : }
1830 : break;
1831 : }
1832 : break;
1833 : case 'f': // 12 strings to match.
1834 32 : switch (Mnemonic[3]) {
1835 : default: break;
1836 : case 'l': // 6 strings to match.
1837 16 : if (memcmp(Mnemonic.data()+4, "oor_f", 5))
1838 : break;
1839 32 : switch (Mnemonic[9]) {
1840 : default: break;
1841 : case '1': // 2 strings to match.
1842 0 : if (memcmp(Mnemonic.data()+10, "6_e", 3))
1843 : break;
1844 0 : switch (Mnemonic[13]) {
1845 : default: break;
1846 : case '3': // 1 string to match.
1847 0 : if (Mnemonic[14] != '2')
1848 : break;
1849 0 : Mnemonic = "v_floor_f16"; // "v_floor_f16_e32"
1850 0 : return;
1851 : case '6': // 1 string to match.
1852 0 : if (Mnemonic[14] != '4')
1853 : break;
1854 0 : Mnemonic = "v_floor_f16"; // "v_floor_f16_e64"
1855 0 : return;
1856 : }
1857 : break;
1858 : case '3': // 2 strings to match.
1859 8 : if (memcmp(Mnemonic.data()+10, "2_e", 3))
1860 : break;
1861 16 : switch (Mnemonic[13]) {
1862 : default: break;
1863 : case '3': // 1 string to match.
1864 16 : if (Mnemonic[14] != '2')
1865 : break;
1866 8 : Mnemonic = "v_floor_f32"; // "v_floor_f32_e32"
1867 8 : return;
1868 : case '6': // 1 string to match.
1869 0 : if (Mnemonic[14] != '4')
1870 : break;
1871 0 : Mnemonic = "v_floor_f32"; // "v_floor_f32_e64"
1872 0 : return;
1873 : }
1874 : break;
1875 : case '6': // 2 strings to match.
1876 8 : if (memcmp(Mnemonic.data()+10, "4_e", 3))
1877 : break;
1878 16 : switch (Mnemonic[13]) {
1879 : default: break;
1880 : case '3': // 1 string to match.
1881 16 : if (Mnemonic[14] != '2')
1882 : break;
1883 8 : Mnemonic = "v_floor_f64"; // "v_floor_f64_e32"
1884 8 : return;
1885 : case '6': // 1 string to match.
1886 0 : if (Mnemonic[14] != '4')
1887 : break;
1888 0 : Mnemonic = "v_floor_f64"; // "v_floor_f64_e64"
1889 0 : return;
1890 : }
1891 : break;
1892 : }
1893 : break;
1894 : case 'r': // 6 strings to match.
1895 0 : if (memcmp(Mnemonic.data()+4, "act_f", 5))
1896 : break;
1897 0 : switch (Mnemonic[9]) {
1898 : default: break;
1899 : case '1': // 2 strings to match.
1900 0 : if (memcmp(Mnemonic.data()+10, "6_e", 3))
1901 : break;
1902 0 : switch (Mnemonic[13]) {
1903 : default: break;
1904 : case '3': // 1 string to match.
1905 0 : if (Mnemonic[14] != '2')
1906 : break;
1907 0 : Mnemonic = "v_fract_f16"; // "v_fract_f16_e32"
1908 0 : return;
1909 : case '6': // 1 string to match.
1910 0 : if (Mnemonic[14] != '4')
1911 : break;
1912 0 : Mnemonic = "v_fract_f16"; // "v_fract_f16_e64"
1913 0 : return;
1914 : }
1915 : break;
1916 : case '3': // 2 strings to match.
1917 0 : if (memcmp(Mnemonic.data()+10, "2_e", 3))
1918 : break;
1919 0 : switch (Mnemonic[13]) {
1920 : default: break;
1921 : case '3': // 1 string to match.
1922 0 : if (Mnemonic[14] != '2')
1923 : break;
1924 0 : Mnemonic = "v_fract_f32"; // "v_fract_f32_e32"
1925 0 : return;
1926 : case '6': // 1 string to match.
1927 0 : if (Mnemonic[14] != '4')
1928 : break;
1929 0 : Mnemonic = "v_fract_f32"; // "v_fract_f32_e64"
1930 0 : return;
1931 : }
1932 : break;
1933 : case '6': // 2 strings to match.
1934 0 : if (memcmp(Mnemonic.data()+10, "4_e", 3))
1935 : break;
1936 0 : switch (Mnemonic[13]) {
1937 : default: break;
1938 : case '3': // 1 string to match.
1939 0 : if (Mnemonic[14] != '2')
1940 : break;
1941 0 : Mnemonic = "v_fract_f64"; // "v_fract_f64_e32"
1942 0 : return;
1943 : case '6': // 1 string to match.
1944 0 : if (Mnemonic[14] != '4')
1945 : break;
1946 0 : Mnemonic = "v_fract_f64"; // "v_fract_f64_e64"
1947 0 : return;
1948 : }
1949 : break;
1950 : }
1951 : break;
1952 : }
1953 : break;
1954 : case 'l': // 5 strings to match.
1955 12 : if (memcmp(Mnemonic.data()+3, "dexp_f", 6))
1956 : break;
1957 8 : switch (Mnemonic[9]) {
1958 : default: break;
1959 : case '1': // 2 strings to match.
1960 0 : if (memcmp(Mnemonic.data()+10, "6_e", 3))
1961 : break;
1962 0 : switch (Mnemonic[13]) {
1963 : default: break;
1964 : case '3': // 1 string to match.
1965 0 : if (Mnemonic[14] != '2')
1966 : break;
1967 0 : Mnemonic = "v_ldexp_f16"; // "v_ldexp_f16_e32"
1968 0 : return;
1969 : case '6': // 1 string to match.
1970 0 : if (Mnemonic[14] != '4')
1971 : break;
1972 0 : Mnemonic = "v_ldexp_f16"; // "v_ldexp_f16_e64"
1973 0 : return;
1974 : }
1975 : break;
1976 : case '3': // 2 strings to match.
1977 4 : if (memcmp(Mnemonic.data()+10, "2_e", 3))
1978 : break;
1979 8 : switch (Mnemonic[13]) {
1980 : default: break;
1981 : case '3': // 1 string to match.
1982 0 : if (Mnemonic[14] != '2')
1983 : break;
1984 0 : Mnemonic = "v_ldexp_f32"; // "v_ldexp_f32_e32"
1985 0 : return;
1986 : case '6': // 1 string to match.
1987 8 : if (Mnemonic[14] != '4')
1988 : break;
1989 4 : Mnemonic = "v_ldexp_f32"; // "v_ldexp_f32_e64"
1990 4 : return;
1991 : }
1992 : break;
1993 : case '6': // 1 string to match.
1994 0 : if (memcmp(Mnemonic.data()+10, "4_e64", 5))
1995 : break;
1996 0 : Mnemonic = "v_ldexp_f64"; // "v_ldexp_f64_e64"
1997 0 : return;
1998 : }
1999 : break;
2000 : case 'm': // 4 strings to match.
2001 0 : if (memcmp(Mnemonic.data()+3, "ad", 2))
2002 : break;
2003 0 : switch (Mnemonic[5]) {
2004 : default: break;
2005 : case 'a': // 2 strings to match.
2006 0 : if (memcmp(Mnemonic.data()+6, "k_f", 3))
2007 : break;
2008 0 : switch (Mnemonic[9]) {
2009 : default: break;
2010 : case '1': // 1 string to match.
2011 0 : if (memcmp(Mnemonic.data()+10, "6_e32", 5))
2012 : break;
2013 0 : Mnemonic = "v_madak_f16"; // "v_madak_f16_e32"
2014 0 : return;
2015 : case '3': // 1 string to match.
2016 0 : if (memcmp(Mnemonic.data()+10, "2_e32", 5))
2017 : break;
2018 0 : Mnemonic = "v_madak_f32"; // "v_madak_f32_e32"
2019 0 : return;
2020 : }
2021 : break;
2022 : case 'm': // 2 strings to match.
2023 0 : if (memcmp(Mnemonic.data()+6, "k_f", 3))
2024 : break;
2025 0 : switch (Mnemonic[9]) {
2026 : default: break;
2027 : case '1': // 1 string to match.
2028 0 : if (memcmp(Mnemonic.data()+10, "6_e32", 5))
2029 : break;
2030 0 : Mnemonic = "v_madmk_f16"; // "v_madmk_f16_e32"
2031 0 : return;
2032 : case '3': // 1 string to match.
2033 0 : if (memcmp(Mnemonic.data()+10, "2_e32", 5))
2034 : break;
2035 0 : Mnemonic = "v_madmk_f32"; // "v_madmk_f32_e32"
2036 0 : return;
2037 : }
2038 : break;
2039 : }
2040 : break;
2041 : case 'r': // 6 strings to match.
2042 48 : if (memcmp(Mnemonic.data()+3, "ndne_f", 6))
2043 : break;
2044 16 : switch (Mnemonic[9]) {
2045 : default: break;
2046 : case '1': // 2 strings to match.
2047 0 : if (memcmp(Mnemonic.data()+10, "6_e", 3))
2048 : break;
2049 0 : switch (Mnemonic[13]) {
2050 : default: break;
2051 : case '3': // 1 string to match.
2052 0 : if (Mnemonic[14] != '2')
2053 : break;
2054 0 : Mnemonic = "v_rndne_f16"; // "v_rndne_f16_e32"
2055 0 : return;
2056 : case '6': // 1 string to match.
2057 0 : if (Mnemonic[14] != '4')
2058 : break;
2059 0 : Mnemonic = "v_rndne_f16"; // "v_rndne_f16_e64"
2060 0 : return;
2061 : }
2062 : break;
2063 : case '3': // 2 strings to match.
2064 0 : if (memcmp(Mnemonic.data()+10, "2_e", 3))
2065 : break;
2066 0 : switch (Mnemonic[13]) {
2067 : default: break;
2068 : case '3': // 1 string to match.
2069 0 : if (Mnemonic[14] != '2')
2070 : break;
2071 0 : Mnemonic = "v_rndne_f32"; // "v_rndne_f32_e32"
2072 0 : return;
2073 : case '6': // 1 string to match.
2074 0 : if (Mnemonic[14] != '4')
2075 : break;
2076 0 : Mnemonic = "v_rndne_f32"; // "v_rndne_f32_e64"
2077 0 : return;
2078 : }
2079 : break;
2080 : case '6': // 2 strings to match.
2081 8 : if (memcmp(Mnemonic.data()+10, "4_e", 3))
2082 : break;
2083 16 : switch (Mnemonic[13]) {
2084 : default: break;
2085 : case '3': // 1 string to match.
2086 16 : if (Mnemonic[14] != '2')
2087 : break;
2088 8 : Mnemonic = "v_rndne_f64"; // "v_rndne_f64_e32"
2089 8 : return;
2090 : case '6': // 1 string to match.
2091 0 : if (Mnemonic[14] != '4')
2092 : break;
2093 0 : Mnemonic = "v_rndne_f64"; // "v_rndne_f64_e64"
2094 0 : return;
2095 : }
2096 : break;
2097 : }
2098 : break;
2099 : case 't': // 6 strings to match.
2100 8 : if (memcmp(Mnemonic.data()+3, "runc_f", 6))
2101 : break;
2102 16 : switch (Mnemonic[9]) {
2103 : default: break;
2104 : case '1': // 2 strings to match.
2105 0 : if (memcmp(Mnemonic.data()+10, "6_e", 3))
2106 : break;
2107 0 : switch (Mnemonic[13]) {
2108 : default: break;
2109 : case '3': // 1 string to match.
2110 0 : if (Mnemonic[14] != '2')
2111 : break;
2112 0 : Mnemonic = "v_trunc_f16"; // "v_trunc_f16_e32"
2113 0 : return;
2114 : case '6': // 1 string to match.
2115 0 : if (Mnemonic[14] != '4')
2116 : break;
2117 0 : Mnemonic = "v_trunc_f16"; // "v_trunc_f16_e64"
2118 0 : return;
2119 : }
2120 : break;
2121 : case '3': // 2 strings to match.
2122 0 : if (memcmp(Mnemonic.data()+10, "2_e", 3))
2123 : break;
2124 0 : switch (Mnemonic[13]) {
2125 : default: break;
2126 : case '3': // 1 string to match.
2127 0 : if (Mnemonic[14] != '2')
2128 : break;
2129 0 : Mnemonic = "v_trunc_f32"; // "v_trunc_f32_e32"
2130 0 : return;
2131 : case '6': // 1 string to match.
2132 0 : if (Mnemonic[14] != '4')
2133 : break;
2134 0 : Mnemonic = "v_trunc_f32"; // "v_trunc_f32_e64"
2135 0 : return;
2136 : }
2137 : break;
2138 : case '6': // 2 strings to match.
2139 8 : if (memcmp(Mnemonic.data()+10, "4_e", 3))
2140 : break;
2141 16 : switch (Mnemonic[13]) {
2142 : default: break;
2143 : case '3': // 1 string to match.
2144 16 : if (Mnemonic[14] != '2')
2145 : break;
2146 8 : Mnemonic = "v_trunc_f64"; // "v_trunc_f64_e32"
2147 8 : return;
2148 : case '6': // 1 string to match.
2149 0 : if (Mnemonic[14] != '4')
2150 : break;
2151 0 : Mnemonic = "v_trunc_f64"; // "v_trunc_f64_e64"
2152 0 : return;
2153 : }
2154 : break;
2155 : }
2156 : break;
2157 : }
2158 : break;
2159 : case 16: // 131 strings to match.
2160 164 : if (memcmp(Mnemonic.data()+0, "v_", 2))
2161 : break;
2162 280 : switch (Mnemonic[2]) {
2163 : default: break;
2164 : case 'c': // 116 strings to match.
2165 92 : switch (Mnemonic[3]) {
2166 : default: break;
2167 : case 'm': // 112 strings to match.
2168 12 : if (Mnemonic[4] != 'p')
2169 : break;
2170 12 : switch (Mnemonic[5]) {
2171 : default: break;
2172 : case '_': // 72 strings to match.
2173 12 : switch (Mnemonic[6]) {
2174 : default: break;
2175 : case 'e': // 12 strings to match.
2176 0 : if (memcmp(Mnemonic.data()+7, "q_", 2))
2177 : break;
2178 0 : switch (Mnemonic[9]) {
2179 : default: break;
2180 : case 'f': // 4 strings to match.
2181 0 : switch (Mnemonic[10]) {
2182 : default: break;
2183 : case '3': // 2 strings to match.
2184 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
2185 : break;
2186 0 : switch (Mnemonic[14]) {
2187 : default: break;
2188 : case '3': // 1 string to match.
2189 0 : if (Mnemonic[15] != '2')
2190 : break;
2191 0 : Mnemonic = "v_cmp_eq_f32"; // "v_cmp_eq_f32_e32"
2192 0 : return;
2193 : case '6': // 1 string to match.
2194 0 : if (Mnemonic[15] != '4')
2195 : break;
2196 0 : Mnemonic = "v_cmp_eq_f32"; // "v_cmp_eq_f32_e64"
2197 0 : return;
2198 : }
2199 : break;
2200 : case '6': // 2 strings to match.
2201 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
2202 : break;
2203 0 : switch (Mnemonic[14]) {
2204 : default: break;
2205 : case '3': // 1 string to match.
2206 0 : if (Mnemonic[15] != '2')
2207 : break;
2208 0 : Mnemonic = "v_cmp_eq_f64"; // "v_cmp_eq_f64_e32"
2209 0 : return;
2210 : case '6': // 1 string to match.
2211 0 : if (Mnemonic[15] != '4')
2212 : break;
2213 0 : Mnemonic = "v_cmp_eq_f64"; // "v_cmp_eq_f64_e64"
2214 0 : return;
2215 : }
2216 : break;
2217 : }
2218 : break;
2219 : case 'i': // 4 strings to match.
2220 0 : switch (Mnemonic[10]) {
2221 : default: break;
2222 : case '3': // 2 strings to match.
2223 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
2224 : break;
2225 0 : switch (Mnemonic[14]) {
2226 : default: break;
2227 : case '3': // 1 string to match.
2228 0 : if (Mnemonic[15] != '2')
2229 : break;
2230 0 : Mnemonic = "v_cmp_eq_i32"; // "v_cmp_eq_i32_e32"
2231 0 : return;
2232 : case '6': // 1 string to match.
2233 0 : if (Mnemonic[15] != '4')
2234 : break;
2235 0 : Mnemonic = "v_cmp_eq_i32"; // "v_cmp_eq_i32_e64"
2236 0 : return;
2237 : }
2238 : break;
2239 : case '6': // 2 strings to match.
2240 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
2241 : break;
2242 0 : switch (Mnemonic[14]) {
2243 : default: break;
2244 : case '3': // 1 string to match.
2245 0 : if (Mnemonic[15] != '2')
2246 : break;
2247 0 : Mnemonic = "v_cmp_eq_i64"; // "v_cmp_eq_i64_e32"
2248 0 : return;
2249 : case '6': // 1 string to match.
2250 0 : if (Mnemonic[15] != '4')
2251 : break;
2252 0 : Mnemonic = "v_cmp_eq_i64"; // "v_cmp_eq_i64_e64"
2253 0 : return;
2254 : }
2255 : break;
2256 : }
2257 : break;
2258 : case 'u': // 4 strings to match.
2259 0 : switch (Mnemonic[10]) {
2260 : default: break;
2261 : case '3': // 2 strings to match.
2262 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
2263 : break;
2264 0 : switch (Mnemonic[14]) {
2265 : default: break;
2266 : case '3': // 1 string to match.
2267 0 : if (Mnemonic[15] != '2')
2268 : break;
2269 0 : Mnemonic = "v_cmp_eq_u32"; // "v_cmp_eq_u32_e32"
2270 0 : return;
2271 : case '6': // 1 string to match.
2272 0 : if (Mnemonic[15] != '4')
2273 : break;
2274 0 : Mnemonic = "v_cmp_eq_u32"; // "v_cmp_eq_u32_e64"
2275 0 : return;
2276 : }
2277 : break;
2278 : case '6': // 2 strings to match.
2279 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
2280 : break;
2281 0 : switch (Mnemonic[14]) {
2282 : default: break;
2283 : case '3': // 1 string to match.
2284 0 : if (Mnemonic[15] != '2')
2285 : break;
2286 0 : Mnemonic = "v_cmp_eq_u64"; // "v_cmp_eq_u64_e32"
2287 0 : return;
2288 : case '6': // 1 string to match.
2289 0 : if (Mnemonic[15] != '4')
2290 : break;
2291 0 : Mnemonic = "v_cmp_eq_u64"; // "v_cmp_eq_u64_e64"
2292 0 : return;
2293 : }
2294 : break;
2295 : }
2296 : break;
2297 : }
2298 : break;
2299 : case 'g': // 24 strings to match.
2300 0 : switch (Mnemonic[7]) {
2301 : default: break;
2302 : case 'e': // 12 strings to match.
2303 0 : if (Mnemonic[8] != '_')
2304 : break;
2305 0 : switch (Mnemonic[9]) {
2306 : default: break;
2307 : case 'f': // 4 strings to match.
2308 0 : switch (Mnemonic[10]) {
2309 : default: break;
2310 : case '3': // 2 strings to match.
2311 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
2312 : break;
2313 0 : switch (Mnemonic[14]) {
2314 : default: break;
2315 : case '3': // 1 string to match.
2316 0 : if (Mnemonic[15] != '2')
2317 : break;
2318 0 : Mnemonic = "v_cmp_ge_f32"; // "v_cmp_ge_f32_e32"
2319 0 : return;
2320 : case '6': // 1 string to match.
2321 0 : if (Mnemonic[15] != '4')
2322 : break;
2323 0 : Mnemonic = "v_cmp_ge_f32"; // "v_cmp_ge_f32_e64"
2324 0 : return;
2325 : }
2326 : break;
2327 : case '6': // 2 strings to match.
2328 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
2329 : break;
2330 0 : switch (Mnemonic[14]) {
2331 : default: break;
2332 : case '3': // 1 string to match.
2333 0 : if (Mnemonic[15] != '2')
2334 : break;
2335 0 : Mnemonic = "v_cmp_ge_f64"; // "v_cmp_ge_f64_e32"
2336 0 : return;
2337 : case '6': // 1 string to match.
2338 0 : if (Mnemonic[15] != '4')
2339 : break;
2340 0 : Mnemonic = "v_cmp_ge_f64"; // "v_cmp_ge_f64_e64"
2341 0 : return;
2342 : }
2343 : break;
2344 : }
2345 : break;
2346 : case 'i': // 4 strings to match.
2347 0 : switch (Mnemonic[10]) {
2348 : default: break;
2349 : case '3': // 2 strings to match.
2350 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
2351 : break;
2352 0 : switch (Mnemonic[14]) {
2353 : default: break;
2354 : case '3': // 1 string to match.
2355 0 : if (Mnemonic[15] != '2')
2356 : break;
2357 0 : Mnemonic = "v_cmp_ge_i32"; // "v_cmp_ge_i32_e32"
2358 0 : return;
2359 : case '6': // 1 string to match.
2360 0 : if (Mnemonic[15] != '4')
2361 : break;
2362 0 : Mnemonic = "v_cmp_ge_i32"; // "v_cmp_ge_i32_e64"
2363 0 : return;
2364 : }
2365 : break;
2366 : case '6': // 2 strings to match.
2367 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
2368 : break;
2369 0 : switch (Mnemonic[14]) {
2370 : default: break;
2371 : case '3': // 1 string to match.
2372 0 : if (Mnemonic[15] != '2')
2373 : break;
2374 0 : Mnemonic = "v_cmp_ge_i64"; // "v_cmp_ge_i64_e32"
2375 0 : return;
2376 : case '6': // 1 string to match.
2377 0 : if (Mnemonic[15] != '4')
2378 : break;
2379 0 : Mnemonic = "v_cmp_ge_i64"; // "v_cmp_ge_i64_e64"
2380 0 : return;
2381 : }
2382 : break;
2383 : }
2384 : break;
2385 : case 'u': // 4 strings to match.
2386 0 : switch (Mnemonic[10]) {
2387 : default: break;
2388 : case '3': // 2 strings to match.
2389 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
2390 : break;
2391 0 : switch (Mnemonic[14]) {
2392 : default: break;
2393 : case '3': // 1 string to match.
2394 0 : if (Mnemonic[15] != '2')
2395 : break;
2396 0 : Mnemonic = "v_cmp_ge_u32"; // "v_cmp_ge_u32_e32"
2397 0 : return;
2398 : case '6': // 1 string to match.
2399 0 : if (Mnemonic[15] != '4')
2400 : break;
2401 0 : Mnemonic = "v_cmp_ge_u32"; // "v_cmp_ge_u32_e64"
2402 0 : return;
2403 : }
2404 : break;
2405 : case '6': // 2 strings to match.
2406 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
2407 : break;
2408 0 : switch (Mnemonic[14]) {
2409 : default: break;
2410 : case '3': // 1 string to match.
2411 0 : if (Mnemonic[15] != '2')
2412 : break;
2413 0 : Mnemonic = "v_cmp_ge_u64"; // "v_cmp_ge_u64_e32"
2414 0 : return;
2415 : case '6': // 1 string to match.
2416 0 : if (Mnemonic[15] != '4')
2417 : break;
2418 0 : Mnemonic = "v_cmp_ge_u64"; // "v_cmp_ge_u64_e64"
2419 0 : return;
2420 : }
2421 : break;
2422 : }
2423 : break;
2424 : }
2425 : break;
2426 : case 't': // 12 strings to match.
2427 0 : if (Mnemonic[8] != '_')
2428 : break;
2429 0 : switch (Mnemonic[9]) {
2430 : default: break;
2431 : case 'f': // 4 strings to match.
2432 0 : switch (Mnemonic[10]) {
2433 : default: break;
2434 : case '3': // 2 strings to match.
2435 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
2436 : break;
2437 0 : switch (Mnemonic[14]) {
2438 : default: break;
2439 : case '3': // 1 string to match.
2440 0 : if (Mnemonic[15] != '2')
2441 : break;
2442 0 : Mnemonic = "v_cmp_gt_f32"; // "v_cmp_gt_f32_e32"
2443 0 : return;
2444 : case '6': // 1 string to match.
2445 0 : if (Mnemonic[15] != '4')
2446 : break;
2447 0 : Mnemonic = "v_cmp_gt_f32"; // "v_cmp_gt_f32_e64"
2448 0 : return;
2449 : }
2450 : break;
2451 : case '6': // 2 strings to match.
2452 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
2453 : break;
2454 0 : switch (Mnemonic[14]) {
2455 : default: break;
2456 : case '3': // 1 string to match.
2457 0 : if (Mnemonic[15] != '2')
2458 : break;
2459 0 : Mnemonic = "v_cmp_gt_f64"; // "v_cmp_gt_f64_e32"
2460 0 : return;
2461 : case '6': // 1 string to match.
2462 0 : if (Mnemonic[15] != '4')
2463 : break;
2464 0 : Mnemonic = "v_cmp_gt_f64"; // "v_cmp_gt_f64_e64"
2465 0 : return;
2466 : }
2467 : break;
2468 : }
2469 : break;
2470 : case 'i': // 4 strings to match.
2471 0 : switch (Mnemonic[10]) {
2472 : default: break;
2473 : case '3': // 2 strings to match.
2474 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
2475 : break;
2476 0 : switch (Mnemonic[14]) {
2477 : default: break;
2478 : case '3': // 1 string to match.
2479 0 : if (Mnemonic[15] != '2')
2480 : break;
2481 0 : Mnemonic = "v_cmp_gt_i32"; // "v_cmp_gt_i32_e32"
2482 0 : return;
2483 : case '6': // 1 string to match.
2484 0 : if (Mnemonic[15] != '4')
2485 : break;
2486 0 : Mnemonic = "v_cmp_gt_i32"; // "v_cmp_gt_i32_e64"
2487 0 : return;
2488 : }
2489 : break;
2490 : case '6': // 2 strings to match.
2491 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
2492 : break;
2493 0 : switch (Mnemonic[14]) {
2494 : default: break;
2495 : case '3': // 1 string to match.
2496 0 : if (Mnemonic[15] != '2')
2497 : break;
2498 0 : Mnemonic = "v_cmp_gt_i64"; // "v_cmp_gt_i64_e32"
2499 0 : return;
2500 : case '6': // 1 string to match.
2501 0 : if (Mnemonic[15] != '4')
2502 : break;
2503 0 : Mnemonic = "v_cmp_gt_i64"; // "v_cmp_gt_i64_e64"
2504 0 : return;
2505 : }
2506 : break;
2507 : }
2508 : break;
2509 : case 'u': // 4 strings to match.
2510 0 : switch (Mnemonic[10]) {
2511 : default: break;
2512 : case '3': // 2 strings to match.
2513 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
2514 : break;
2515 0 : switch (Mnemonic[14]) {
2516 : default: break;
2517 : case '3': // 1 string to match.
2518 0 : if (Mnemonic[15] != '2')
2519 : break;
2520 0 : Mnemonic = "v_cmp_gt_u32"; // "v_cmp_gt_u32_e32"
2521 0 : return;
2522 : case '6': // 1 string to match.
2523 0 : if (Mnemonic[15] != '4')
2524 : break;
2525 0 : Mnemonic = "v_cmp_gt_u32"; // "v_cmp_gt_u32_e64"
2526 0 : return;
2527 : }
2528 : break;
2529 : case '6': // 2 strings to match.
2530 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
2531 : break;
2532 0 : switch (Mnemonic[14]) {
2533 : default: break;
2534 : case '3': // 1 string to match.
2535 0 : if (Mnemonic[15] != '2')
2536 : break;
2537 0 : Mnemonic = "v_cmp_gt_u64"; // "v_cmp_gt_u64_e32"
2538 0 : return;
2539 : case '6': // 1 string to match.
2540 0 : if (Mnemonic[15] != '4')
2541 : break;
2542 0 : Mnemonic = "v_cmp_gt_u64"; // "v_cmp_gt_u64_e64"
2543 0 : return;
2544 : }
2545 : break;
2546 : }
2547 : break;
2548 : }
2549 : break;
2550 : }
2551 : break;
2552 : case 'l': // 28 strings to match.
2553 12 : switch (Mnemonic[7]) {
2554 : default: break;
2555 : case 'e': // 12 strings to match.
2556 0 : if (Mnemonic[8] != '_')
2557 : break;
2558 0 : switch (Mnemonic[9]) {
2559 : default: break;
2560 : case 'f': // 4 strings to match.
2561 0 : switch (Mnemonic[10]) {
2562 : default: break;
2563 : case '3': // 2 strings to match.
2564 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
2565 : break;
2566 0 : switch (Mnemonic[14]) {
2567 : default: break;
2568 : case '3': // 1 string to match.
2569 0 : if (Mnemonic[15] != '2')
2570 : break;
2571 0 : Mnemonic = "v_cmp_le_f32"; // "v_cmp_le_f32_e32"
2572 0 : return;
2573 : case '6': // 1 string to match.
2574 0 : if (Mnemonic[15] != '4')
2575 : break;
2576 0 : Mnemonic = "v_cmp_le_f32"; // "v_cmp_le_f32_e64"
2577 0 : return;
2578 : }
2579 : break;
2580 : case '6': // 2 strings to match.
2581 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
2582 : break;
2583 0 : switch (Mnemonic[14]) {
2584 : default: break;
2585 : case '3': // 1 string to match.
2586 0 : if (Mnemonic[15] != '2')
2587 : break;
2588 0 : Mnemonic = "v_cmp_le_f64"; // "v_cmp_le_f64_e32"
2589 0 : return;
2590 : case '6': // 1 string to match.
2591 0 : if (Mnemonic[15] != '4')
2592 : break;
2593 0 : Mnemonic = "v_cmp_le_f64"; // "v_cmp_le_f64_e64"
2594 0 : return;
2595 : }
2596 : break;
2597 : }
2598 : break;
2599 : case 'i': // 4 strings to match.
2600 0 : switch (Mnemonic[10]) {
2601 : default: break;
2602 : case '3': // 2 strings to match.
2603 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
2604 : break;
2605 0 : switch (Mnemonic[14]) {
2606 : default: break;
2607 : case '3': // 1 string to match.
2608 0 : if (Mnemonic[15] != '2')
2609 : break;
2610 0 : Mnemonic = "v_cmp_le_i32"; // "v_cmp_le_i32_e32"
2611 0 : return;
2612 : case '6': // 1 string to match.
2613 0 : if (Mnemonic[15] != '4')
2614 : break;
2615 0 : Mnemonic = "v_cmp_le_i32"; // "v_cmp_le_i32_e64"
2616 0 : return;
2617 : }
2618 : break;
2619 : case '6': // 2 strings to match.
2620 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
2621 : break;
2622 0 : switch (Mnemonic[14]) {
2623 : default: break;
2624 : case '3': // 1 string to match.
2625 0 : if (Mnemonic[15] != '2')
2626 : break;
2627 0 : Mnemonic = "v_cmp_le_i64"; // "v_cmp_le_i64_e32"
2628 0 : return;
2629 : case '6': // 1 string to match.
2630 0 : if (Mnemonic[15] != '4')
2631 : break;
2632 0 : Mnemonic = "v_cmp_le_i64"; // "v_cmp_le_i64_e64"
2633 0 : return;
2634 : }
2635 : break;
2636 : }
2637 : break;
2638 : case 'u': // 4 strings to match.
2639 0 : switch (Mnemonic[10]) {
2640 : default: break;
2641 : case '3': // 2 strings to match.
2642 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
2643 : break;
2644 0 : switch (Mnemonic[14]) {
2645 : default: break;
2646 : case '3': // 1 string to match.
2647 0 : if (Mnemonic[15] != '2')
2648 : break;
2649 0 : Mnemonic = "v_cmp_le_u32"; // "v_cmp_le_u32_e32"
2650 0 : return;
2651 : case '6': // 1 string to match.
2652 0 : if (Mnemonic[15] != '4')
2653 : break;
2654 0 : Mnemonic = "v_cmp_le_u32"; // "v_cmp_le_u32_e64"
2655 0 : return;
2656 : }
2657 : break;
2658 : case '6': // 2 strings to match.
2659 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
2660 : break;
2661 0 : switch (Mnemonic[14]) {
2662 : default: break;
2663 : case '3': // 1 string to match.
2664 0 : if (Mnemonic[15] != '2')
2665 : break;
2666 0 : Mnemonic = "v_cmp_le_u64"; // "v_cmp_le_u64_e32"
2667 0 : return;
2668 : case '6': // 1 string to match.
2669 0 : if (Mnemonic[15] != '4')
2670 : break;
2671 0 : Mnemonic = "v_cmp_le_u64"; // "v_cmp_le_u64_e64"
2672 0 : return;
2673 : }
2674 : break;
2675 : }
2676 : break;
2677 : }
2678 : break;
2679 : case 'g': // 4 strings to match.
2680 0 : if (memcmp(Mnemonic.data()+8, "_f", 2))
2681 : break;
2682 0 : switch (Mnemonic[10]) {
2683 : default: break;
2684 : case '3': // 2 strings to match.
2685 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
2686 : break;
2687 0 : switch (Mnemonic[14]) {
2688 : default: break;
2689 : case '3': // 1 string to match.
2690 0 : if (Mnemonic[15] != '2')
2691 : break;
2692 0 : Mnemonic = "v_cmp_lg_f32"; // "v_cmp_lg_f32_e32"
2693 0 : return;
2694 : case '6': // 1 string to match.
2695 0 : if (Mnemonic[15] != '4')
2696 : break;
2697 0 : Mnemonic = "v_cmp_lg_f32"; // "v_cmp_lg_f32_e64"
2698 0 : return;
2699 : }
2700 : break;
2701 : case '6': // 2 strings to match.
2702 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
2703 : break;
2704 0 : switch (Mnemonic[14]) {
2705 : default: break;
2706 : case '3': // 1 string to match.
2707 0 : if (Mnemonic[15] != '2')
2708 : break;
2709 0 : Mnemonic = "v_cmp_lg_f64"; // "v_cmp_lg_f64_e32"
2710 0 : return;
2711 : case '6': // 1 string to match.
2712 0 : if (Mnemonic[15] != '4')
2713 : break;
2714 0 : Mnemonic = "v_cmp_lg_f64"; // "v_cmp_lg_f64_e64"
2715 0 : return;
2716 : }
2717 : break;
2718 : }
2719 : break;
2720 : case 't': // 12 strings to match.
2721 12 : if (Mnemonic[8] != '_')
2722 : break;
2723 12 : switch (Mnemonic[9]) {
2724 : default: break;
2725 : case 'f': // 4 strings to match.
2726 12 : switch (Mnemonic[10]) {
2727 : default: break;
2728 : case '3': // 2 strings to match.
2729 6 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
2730 : break;
2731 12 : switch (Mnemonic[14]) {
2732 : default: break;
2733 : case '3': // 1 string to match.
2734 4 : if (Mnemonic[15] != '2')
2735 : break;
2736 2 : Mnemonic = "v_cmp_lt_f32"; // "v_cmp_lt_f32_e32"
2737 2 : return;
2738 : case '6': // 1 string to match.
2739 8 : if (Mnemonic[15] != '4')
2740 : break;
2741 4 : Mnemonic = "v_cmp_lt_f32"; // "v_cmp_lt_f32_e64"
2742 4 : return;
2743 : }
2744 : break;
2745 : case '6': // 2 strings to match.
2746 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
2747 : break;
2748 0 : switch (Mnemonic[14]) {
2749 : default: break;
2750 : case '3': // 1 string to match.
2751 0 : if (Mnemonic[15] != '2')
2752 : break;
2753 0 : Mnemonic = "v_cmp_lt_f64"; // "v_cmp_lt_f64_e32"
2754 0 : return;
2755 : case '6': // 1 string to match.
2756 0 : if (Mnemonic[15] != '4')
2757 : break;
2758 0 : Mnemonic = "v_cmp_lt_f64"; // "v_cmp_lt_f64_e64"
2759 0 : return;
2760 : }
2761 : break;
2762 : }
2763 : break;
2764 : case 'i': // 4 strings to match.
2765 0 : switch (Mnemonic[10]) {
2766 : default: break;
2767 : case '3': // 2 strings to match.
2768 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
2769 : break;
2770 0 : switch (Mnemonic[14]) {
2771 : default: break;
2772 : case '3': // 1 string to match.
2773 0 : if (Mnemonic[15] != '2')
2774 : break;
2775 0 : Mnemonic = "v_cmp_lt_i32"; // "v_cmp_lt_i32_e32"
2776 0 : return;
2777 : case '6': // 1 string to match.
2778 0 : if (Mnemonic[15] != '4')
2779 : break;
2780 0 : Mnemonic = "v_cmp_lt_i32"; // "v_cmp_lt_i32_e64"
2781 0 : return;
2782 : }
2783 : break;
2784 : case '6': // 2 strings to match.
2785 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
2786 : break;
2787 0 : switch (Mnemonic[14]) {
2788 : default: break;
2789 : case '3': // 1 string to match.
2790 0 : if (Mnemonic[15] != '2')
2791 : break;
2792 0 : Mnemonic = "v_cmp_lt_i64"; // "v_cmp_lt_i64_e32"
2793 0 : return;
2794 : case '6': // 1 string to match.
2795 0 : if (Mnemonic[15] != '4')
2796 : break;
2797 0 : Mnemonic = "v_cmp_lt_i64"; // "v_cmp_lt_i64_e64"
2798 0 : return;
2799 : }
2800 : break;
2801 : }
2802 : break;
2803 : case 'u': // 4 strings to match.
2804 0 : switch (Mnemonic[10]) {
2805 : default: break;
2806 : case '3': // 2 strings to match.
2807 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
2808 : break;
2809 0 : switch (Mnemonic[14]) {
2810 : default: break;
2811 : case '3': // 1 string to match.
2812 0 : if (Mnemonic[15] != '2')
2813 : break;
2814 0 : Mnemonic = "v_cmp_lt_u32"; // "v_cmp_lt_u32_e32"
2815 0 : return;
2816 : case '6': // 1 string to match.
2817 0 : if (Mnemonic[15] != '4')
2818 : break;
2819 0 : Mnemonic = "v_cmp_lt_u32"; // "v_cmp_lt_u32_e64"
2820 0 : return;
2821 : }
2822 : break;
2823 : case '6': // 2 strings to match.
2824 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
2825 : break;
2826 0 : switch (Mnemonic[14]) {
2827 : default: break;
2828 : case '3': // 1 string to match.
2829 0 : if (Mnemonic[15] != '2')
2830 : break;
2831 0 : Mnemonic = "v_cmp_lt_u64"; // "v_cmp_lt_u64_e32"
2832 0 : return;
2833 : case '6': // 1 string to match.
2834 0 : if (Mnemonic[15] != '4')
2835 : break;
2836 0 : Mnemonic = "v_cmp_lt_u64"; // "v_cmp_lt_u64_e64"
2837 0 : return;
2838 : }
2839 : break;
2840 : }
2841 : break;
2842 : }
2843 : break;
2844 : }
2845 : break;
2846 : case 'n': // 8 strings to match.
2847 0 : if (memcmp(Mnemonic.data()+7, "e_", 2))
2848 : break;
2849 0 : switch (Mnemonic[9]) {
2850 : default: break;
2851 : case 'i': // 4 strings to match.
2852 0 : switch (Mnemonic[10]) {
2853 : default: break;
2854 : case '3': // 2 strings to match.
2855 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
2856 : break;
2857 0 : switch (Mnemonic[14]) {
2858 : default: break;
2859 : case '3': // 1 string to match.
2860 0 : if (Mnemonic[15] != '2')
2861 : break;
2862 0 : Mnemonic = "v_cmp_ne_i32"; // "v_cmp_ne_i32_e32"
2863 0 : return;
2864 : case '6': // 1 string to match.
2865 0 : if (Mnemonic[15] != '4')
2866 : break;
2867 0 : Mnemonic = "v_cmp_ne_i32"; // "v_cmp_ne_i32_e64"
2868 0 : return;
2869 : }
2870 : break;
2871 : case '6': // 2 strings to match.
2872 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
2873 : break;
2874 0 : switch (Mnemonic[14]) {
2875 : default: break;
2876 : case '3': // 1 string to match.
2877 0 : if (Mnemonic[15] != '2')
2878 : break;
2879 0 : Mnemonic = "v_cmp_ne_i64"; // "v_cmp_ne_i64_e32"
2880 0 : return;
2881 : case '6': // 1 string to match.
2882 0 : if (Mnemonic[15] != '4')
2883 : break;
2884 0 : Mnemonic = "v_cmp_ne_i64"; // "v_cmp_ne_i64_e64"
2885 0 : return;
2886 : }
2887 : break;
2888 : }
2889 : break;
2890 : case 'u': // 4 strings to match.
2891 0 : switch (Mnemonic[10]) {
2892 : default: break;
2893 : case '3': // 2 strings to match.
2894 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
2895 : break;
2896 0 : switch (Mnemonic[14]) {
2897 : default: break;
2898 : case '3': // 1 string to match.
2899 0 : if (Mnemonic[15] != '2')
2900 : break;
2901 0 : Mnemonic = "v_cmp_ne_u32"; // "v_cmp_ne_u32_e32"
2902 0 : return;
2903 : case '6': // 1 string to match.
2904 0 : if (Mnemonic[15] != '4')
2905 : break;
2906 0 : Mnemonic = "v_cmp_ne_u32"; // "v_cmp_ne_u32_e64"
2907 0 : return;
2908 : }
2909 : break;
2910 : case '6': // 2 strings to match.
2911 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
2912 : break;
2913 0 : switch (Mnemonic[14]) {
2914 : default: break;
2915 : case '3': // 1 string to match.
2916 0 : if (Mnemonic[15] != '2')
2917 : break;
2918 0 : Mnemonic = "v_cmp_ne_u64"; // "v_cmp_ne_u64_e32"
2919 0 : return;
2920 : case '6': // 1 string to match.
2921 0 : if (Mnemonic[15] != '4')
2922 : break;
2923 0 : Mnemonic = "v_cmp_ne_u64"; // "v_cmp_ne_u64_e64"
2924 0 : return;
2925 : }
2926 : break;
2927 : }
2928 : break;
2929 : }
2930 : break;
2931 : }
2932 : break;
2933 : case 's': // 12 strings to match.
2934 0 : if (Mnemonic[6] != '_')
2935 : break;
2936 0 : switch (Mnemonic[7]) {
2937 : default: break;
2938 : case 'f': // 4 strings to match.
2939 0 : if (memcmp(Mnemonic.data()+8, "_f", 2))
2940 : break;
2941 0 : switch (Mnemonic[10]) {
2942 : default: break;
2943 : case '3': // 2 strings to match.
2944 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
2945 : break;
2946 0 : switch (Mnemonic[14]) {
2947 : default: break;
2948 : case '3': // 1 string to match.
2949 0 : if (Mnemonic[15] != '2')
2950 : break;
2951 0 : Mnemonic = "v_cmps_f_f32"; // "v_cmps_f_f32_e32"
2952 0 : return;
2953 : case '6': // 1 string to match.
2954 0 : if (Mnemonic[15] != '4')
2955 : break;
2956 0 : Mnemonic = "v_cmps_f_f32"; // "v_cmps_f_f32_e64"
2957 0 : return;
2958 : }
2959 : break;
2960 : case '6': // 2 strings to match.
2961 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
2962 : break;
2963 0 : switch (Mnemonic[14]) {
2964 : default: break;
2965 : case '3': // 1 string to match.
2966 0 : if (Mnemonic[15] != '2')
2967 : break;
2968 0 : Mnemonic = "v_cmps_f_f64"; // "v_cmps_f_f64_e32"
2969 0 : return;
2970 : case '6': // 1 string to match.
2971 0 : if (Mnemonic[15] != '4')
2972 : break;
2973 0 : Mnemonic = "v_cmps_f_f64"; // "v_cmps_f_f64_e64"
2974 0 : return;
2975 : }
2976 : break;
2977 : }
2978 : break;
2979 : case 'o': // 4 strings to match.
2980 0 : if (memcmp(Mnemonic.data()+8, "_f", 2))
2981 : break;
2982 0 : switch (Mnemonic[10]) {
2983 : default: break;
2984 : case '3': // 2 strings to match.
2985 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
2986 : break;
2987 0 : switch (Mnemonic[14]) {
2988 : default: break;
2989 : case '3': // 1 string to match.
2990 0 : if (Mnemonic[15] != '2')
2991 : break;
2992 0 : Mnemonic = "v_cmps_o_f32"; // "v_cmps_o_f32_e32"
2993 0 : return;
2994 : case '6': // 1 string to match.
2995 0 : if (Mnemonic[15] != '4')
2996 : break;
2997 0 : Mnemonic = "v_cmps_o_f32"; // "v_cmps_o_f32_e64"
2998 0 : return;
2999 : }
3000 : break;
3001 : case '6': // 2 strings to match.
3002 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
3003 : break;
3004 0 : switch (Mnemonic[14]) {
3005 : default: break;
3006 : case '3': // 1 string to match.
3007 0 : if (Mnemonic[15] != '2')
3008 : break;
3009 0 : Mnemonic = "v_cmps_o_f64"; // "v_cmps_o_f64_e32"
3010 0 : return;
3011 : case '6': // 1 string to match.
3012 0 : if (Mnemonic[15] != '4')
3013 : break;
3014 0 : Mnemonic = "v_cmps_o_f64"; // "v_cmps_o_f64_e64"
3015 0 : return;
3016 : }
3017 : break;
3018 : }
3019 : break;
3020 : case 'u': // 4 strings to match.
3021 0 : if (memcmp(Mnemonic.data()+8, "_f", 2))
3022 : break;
3023 0 : switch (Mnemonic[10]) {
3024 : default: break;
3025 : case '3': // 2 strings to match.
3026 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
3027 : break;
3028 0 : switch (Mnemonic[14]) {
3029 : default: break;
3030 : case '3': // 1 string to match.
3031 0 : if (Mnemonic[15] != '2')
3032 : break;
3033 0 : Mnemonic = "v_cmps_u_f32"; // "v_cmps_u_f32_e32"
3034 0 : return;
3035 : case '6': // 1 string to match.
3036 0 : if (Mnemonic[15] != '4')
3037 : break;
3038 0 : Mnemonic = "v_cmps_u_f32"; // "v_cmps_u_f32_e64"
3039 0 : return;
3040 : }
3041 : break;
3042 : case '6': // 2 strings to match.
3043 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
3044 : break;
3045 0 : switch (Mnemonic[14]) {
3046 : default: break;
3047 : case '3': // 1 string to match.
3048 0 : if (Mnemonic[15] != '2')
3049 : break;
3050 0 : Mnemonic = "v_cmps_u_f64"; // "v_cmps_u_f64_e32"
3051 0 : return;
3052 : case '6': // 1 string to match.
3053 0 : if (Mnemonic[15] != '4')
3054 : break;
3055 0 : Mnemonic = "v_cmps_u_f64"; // "v_cmps_u_f64_e64"
3056 0 : return;
3057 : }
3058 : break;
3059 : }
3060 : break;
3061 : }
3062 : break;
3063 : case 'x': // 28 strings to match.
3064 0 : if (Mnemonic[6] != '_')
3065 : break;
3066 0 : switch (Mnemonic[7]) {
3067 : default: break;
3068 : case 'f': // 12 strings to match.
3069 0 : if (Mnemonic[8] != '_')
3070 : break;
3071 0 : switch (Mnemonic[9]) {
3072 : default: break;
3073 : case 'f': // 4 strings to match.
3074 0 : switch (Mnemonic[10]) {
3075 : default: break;
3076 : case '3': // 2 strings to match.
3077 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
3078 : break;
3079 0 : switch (Mnemonic[14]) {
3080 : default: break;
3081 : case '3': // 1 string to match.
3082 0 : if (Mnemonic[15] != '2')
3083 : break;
3084 0 : Mnemonic = "v_cmpx_f_f32"; // "v_cmpx_f_f32_e32"
3085 0 : return;
3086 : case '6': // 1 string to match.
3087 0 : if (Mnemonic[15] != '4')
3088 : break;
3089 0 : Mnemonic = "v_cmpx_f_f32"; // "v_cmpx_f_f32_e64"
3090 0 : return;
3091 : }
3092 : break;
3093 : case '6': // 2 strings to match.
3094 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
3095 : break;
3096 0 : switch (Mnemonic[14]) {
3097 : default: break;
3098 : case '3': // 1 string to match.
3099 0 : if (Mnemonic[15] != '2')
3100 : break;
3101 0 : Mnemonic = "v_cmpx_f_f64"; // "v_cmpx_f_f64_e32"
3102 0 : return;
3103 : case '6': // 1 string to match.
3104 0 : if (Mnemonic[15] != '4')
3105 : break;
3106 0 : Mnemonic = "v_cmpx_f_f64"; // "v_cmpx_f_f64_e64"
3107 0 : return;
3108 : }
3109 : break;
3110 : }
3111 : break;
3112 : case 'i': // 4 strings to match.
3113 0 : switch (Mnemonic[10]) {
3114 : default: break;
3115 : case '3': // 2 strings to match.
3116 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
3117 : break;
3118 0 : switch (Mnemonic[14]) {
3119 : default: break;
3120 : case '3': // 1 string to match.
3121 0 : if (Mnemonic[15] != '2')
3122 : break;
3123 0 : Mnemonic = "v_cmpx_f_i32"; // "v_cmpx_f_i32_e32"
3124 0 : return;
3125 : case '6': // 1 string to match.
3126 0 : if (Mnemonic[15] != '4')
3127 : break;
3128 0 : Mnemonic = "v_cmpx_f_i32"; // "v_cmpx_f_i32_e64"
3129 0 : return;
3130 : }
3131 : break;
3132 : case '6': // 2 strings to match.
3133 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
3134 : break;
3135 0 : switch (Mnemonic[14]) {
3136 : default: break;
3137 : case '3': // 1 string to match.
3138 0 : if (Mnemonic[15] != '2')
3139 : break;
3140 0 : Mnemonic = "v_cmpx_f_i64"; // "v_cmpx_f_i64_e32"
3141 0 : return;
3142 : case '6': // 1 string to match.
3143 0 : if (Mnemonic[15] != '4')
3144 : break;
3145 0 : Mnemonic = "v_cmpx_f_i64"; // "v_cmpx_f_i64_e64"
3146 0 : return;
3147 : }
3148 : break;
3149 : }
3150 : break;
3151 : case 'u': // 4 strings to match.
3152 0 : switch (Mnemonic[10]) {
3153 : default: break;
3154 : case '3': // 2 strings to match.
3155 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
3156 : break;
3157 0 : switch (Mnemonic[14]) {
3158 : default: break;
3159 : case '3': // 1 string to match.
3160 0 : if (Mnemonic[15] != '2')
3161 : break;
3162 0 : Mnemonic = "v_cmpx_f_u32"; // "v_cmpx_f_u32_e32"
3163 0 : return;
3164 : case '6': // 1 string to match.
3165 0 : if (Mnemonic[15] != '4')
3166 : break;
3167 0 : Mnemonic = "v_cmpx_f_u32"; // "v_cmpx_f_u32_e64"
3168 0 : return;
3169 : }
3170 : break;
3171 : case '6': // 2 strings to match.
3172 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
3173 : break;
3174 0 : switch (Mnemonic[14]) {
3175 : default: break;
3176 : case '3': // 1 string to match.
3177 0 : if (Mnemonic[15] != '2')
3178 : break;
3179 0 : Mnemonic = "v_cmpx_f_u64"; // "v_cmpx_f_u64_e32"
3180 0 : return;
3181 : case '6': // 1 string to match.
3182 0 : if (Mnemonic[15] != '4')
3183 : break;
3184 0 : Mnemonic = "v_cmpx_f_u64"; // "v_cmpx_f_u64_e64"
3185 0 : return;
3186 : }
3187 : break;
3188 : }
3189 : break;
3190 : }
3191 : break;
3192 : case 'o': // 4 strings to match.
3193 0 : if (memcmp(Mnemonic.data()+8, "_f", 2))
3194 : break;
3195 0 : switch (Mnemonic[10]) {
3196 : default: break;
3197 : case '3': // 2 strings to match.
3198 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
3199 : break;
3200 0 : switch (Mnemonic[14]) {
3201 : default: break;
3202 : case '3': // 1 string to match.
3203 0 : if (Mnemonic[15] != '2')
3204 : break;
3205 0 : Mnemonic = "v_cmpx_o_f32"; // "v_cmpx_o_f32_e32"
3206 0 : return;
3207 : case '6': // 1 string to match.
3208 0 : if (Mnemonic[15] != '4')
3209 : break;
3210 0 : Mnemonic = "v_cmpx_o_f32"; // "v_cmpx_o_f32_e64"
3211 0 : return;
3212 : }
3213 : break;
3214 : case '6': // 2 strings to match.
3215 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
3216 : break;
3217 0 : switch (Mnemonic[14]) {
3218 : default: break;
3219 : case '3': // 1 string to match.
3220 0 : if (Mnemonic[15] != '2')
3221 : break;
3222 0 : Mnemonic = "v_cmpx_o_f64"; // "v_cmpx_o_f64_e32"
3223 0 : return;
3224 : case '6': // 1 string to match.
3225 0 : if (Mnemonic[15] != '4')
3226 : break;
3227 0 : Mnemonic = "v_cmpx_o_f64"; // "v_cmpx_o_f64_e64"
3228 0 : return;
3229 : }
3230 : break;
3231 : }
3232 : break;
3233 : case 't': // 8 strings to match.
3234 0 : if (Mnemonic[8] != '_')
3235 : break;
3236 0 : switch (Mnemonic[9]) {
3237 : default: break;
3238 : case 'i': // 4 strings to match.
3239 0 : switch (Mnemonic[10]) {
3240 : default: break;
3241 : case '3': // 2 strings to match.
3242 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
3243 : break;
3244 0 : switch (Mnemonic[14]) {
3245 : default: break;
3246 : case '3': // 1 string to match.
3247 0 : if (Mnemonic[15] != '2')
3248 : break;
3249 0 : Mnemonic = "v_cmpx_t_i32"; // "v_cmpx_t_i32_e32"
3250 0 : return;
3251 : case '6': // 1 string to match.
3252 0 : if (Mnemonic[15] != '4')
3253 : break;
3254 0 : Mnemonic = "v_cmpx_t_i32"; // "v_cmpx_t_i32_e64"
3255 0 : return;
3256 : }
3257 : break;
3258 : case '6': // 2 strings to match.
3259 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
3260 : break;
3261 0 : switch (Mnemonic[14]) {
3262 : default: break;
3263 : case '3': // 1 string to match.
3264 0 : if (Mnemonic[15] != '2')
3265 : break;
3266 0 : Mnemonic = "v_cmpx_t_i64"; // "v_cmpx_t_i64_e32"
3267 0 : return;
3268 : case '6': // 1 string to match.
3269 0 : if (Mnemonic[15] != '4')
3270 : break;
3271 0 : Mnemonic = "v_cmpx_t_i64"; // "v_cmpx_t_i64_e64"
3272 0 : return;
3273 : }
3274 : break;
3275 : }
3276 : break;
3277 : case 'u': // 4 strings to match.
3278 0 : switch (Mnemonic[10]) {
3279 : default: break;
3280 : case '3': // 2 strings to match.
3281 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
3282 : break;
3283 0 : switch (Mnemonic[14]) {
3284 : default: break;
3285 : case '3': // 1 string to match.
3286 0 : if (Mnemonic[15] != '2')
3287 : break;
3288 0 : Mnemonic = "v_cmpx_t_u32"; // "v_cmpx_t_u32_e32"
3289 0 : return;
3290 : case '6': // 1 string to match.
3291 0 : if (Mnemonic[15] != '4')
3292 : break;
3293 0 : Mnemonic = "v_cmpx_t_u32"; // "v_cmpx_t_u32_e64"
3294 0 : return;
3295 : }
3296 : break;
3297 : case '6': // 2 strings to match.
3298 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
3299 : break;
3300 0 : switch (Mnemonic[14]) {
3301 : default: break;
3302 : case '3': // 1 string to match.
3303 0 : if (Mnemonic[15] != '2')
3304 : break;
3305 0 : Mnemonic = "v_cmpx_t_u64"; // "v_cmpx_t_u64_e32"
3306 0 : return;
3307 : case '6': // 1 string to match.
3308 0 : if (Mnemonic[15] != '4')
3309 : break;
3310 0 : Mnemonic = "v_cmpx_t_u64"; // "v_cmpx_t_u64_e64"
3311 0 : return;
3312 : }
3313 : break;
3314 : }
3315 : break;
3316 : }
3317 : break;
3318 : case 'u': // 4 strings to match.
3319 0 : if (memcmp(Mnemonic.data()+8, "_f", 2))
3320 : break;
3321 0 : switch (Mnemonic[10]) {
3322 : default: break;
3323 : case '3': // 2 strings to match.
3324 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
3325 : break;
3326 0 : switch (Mnemonic[14]) {
3327 : default: break;
3328 : case '3': // 1 string to match.
3329 0 : if (Mnemonic[15] != '2')
3330 : break;
3331 0 : Mnemonic = "v_cmpx_u_f32"; // "v_cmpx_u_f32_e32"
3332 0 : return;
3333 : case '6': // 1 string to match.
3334 0 : if (Mnemonic[15] != '4')
3335 : break;
3336 0 : Mnemonic = "v_cmpx_u_f32"; // "v_cmpx_u_f32_e64"
3337 0 : return;
3338 : }
3339 : break;
3340 : case '6': // 2 strings to match.
3341 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
3342 : break;
3343 0 : switch (Mnemonic[14]) {
3344 : default: break;
3345 : case '3': // 1 string to match.
3346 0 : if (Mnemonic[15] != '2')
3347 : break;
3348 0 : Mnemonic = "v_cmpx_u_f64"; // "v_cmpx_u_f64_e32"
3349 0 : return;
3350 : case '6': // 1 string to match.
3351 0 : if (Mnemonic[15] != '4')
3352 : break;
3353 0 : Mnemonic = "v_cmpx_u_f64"; // "v_cmpx_u_f64_e64"
3354 0 : return;
3355 : }
3356 : break;
3357 : }
3358 : break;
3359 : }
3360 : break;
3361 : }
3362 : break;
3363 : case 'u': // 4 strings to match.
3364 0 : if (memcmp(Mnemonic.data()+4, "be", 2))
3365 : break;
3366 0 : switch (Mnemonic[6]) {
3367 : default: break;
3368 : case 'i': // 1 string to match.
3369 0 : if (memcmp(Mnemonic.data()+7, "d_f32_e64", 9))
3370 : break;
3371 0 : Mnemonic = "v_cubeid_f32"; // "v_cubeid_f32_e64"
3372 0 : return;
3373 : case 'm': // 1 string to match.
3374 0 : if (memcmp(Mnemonic.data()+7, "a_f32_e64", 9))
3375 : break;
3376 0 : Mnemonic = "v_cubema_f32"; // "v_cubema_f32_e64"
3377 0 : return;
3378 : case 's': // 1 string to match.
3379 0 : if (memcmp(Mnemonic.data()+7, "c_f32_e64", 9))
3380 : break;
3381 0 : Mnemonic = "v_cubesc_f32"; // "v_cubesc_f32_e64"
3382 0 : return;
3383 : case 't': // 1 string to match.
3384 0 : if (memcmp(Mnemonic.data()+7, "c_f32_e64", 9))
3385 : break;
3386 0 : Mnemonic = "v_cubetc_f32"; // "v_cubetc_f32_e64"
3387 0 : return;
3388 : }
3389 : break;
3390 : }
3391 : break;
3392 : case 'm': // 7 strings to match.
3393 38 : if (memcmp(Mnemonic.data()+3, "ul", 2))
3394 : break;
3395 36 : switch (Mnemonic[5]) {
3396 : default: break;
3397 : case '_': // 6 strings to match.
3398 36 : switch (Mnemonic[6]) {
3399 : default: break;
3400 : case 'h': // 2 strings to match.
3401 16 : if (memcmp(Mnemonic.data()+7, "i_", 2))
3402 : break;
3403 32 : switch (Mnemonic[9]) {
3404 : default: break;
3405 : case 'i': // 1 string to match.
3406 8 : if (memcmp(Mnemonic.data()+10, "32_e64", 6))
3407 : break;
3408 0 : Mnemonic = "v_mul_hi_i32"; // "v_mul_hi_i32_e64"
3409 0 : return;
3410 : case 'u': // 1 string to match.
3411 8 : if (memcmp(Mnemonic.data()+10, "32_e64", 6))
3412 : break;
3413 0 : Mnemonic = "v_mul_hi_u32"; // "v_mul_hi_u32_e64"
3414 0 : return;
3415 : }
3416 : break;
3417 : case 'l': // 4 strings to match.
3418 2 : if (memcmp(Mnemonic.data()+7, "o_", 2))
3419 : break;
3420 0 : switch (Mnemonic[9]) {
3421 : default: break;
3422 : case 'i': // 1 string to match.
3423 0 : if (memcmp(Mnemonic.data()+10, "32_e64", 6))
3424 : break;
3425 0 : Mnemonic = "v_mul_lo_i32"; // "v_mul_lo_i32_e64"
3426 0 : return;
3427 : case 'u': // 3 strings to match.
3428 0 : switch (Mnemonic[10]) {
3429 : default: break;
3430 : case '1': // 2 strings to match.
3431 0 : if (memcmp(Mnemonic.data()+11, "6_e", 3))
3432 : break;
3433 0 : switch (Mnemonic[14]) {
3434 : default: break;
3435 : case '3': // 1 string to match.
3436 0 : if (Mnemonic[15] != '2')
3437 : break;
3438 0 : Mnemonic = "v_mul_lo_u16"; // "v_mul_lo_u16_e32"
3439 0 : return;
3440 : case '6': // 1 string to match.
3441 0 : if (Mnemonic[15] != '4')
3442 : break;
3443 0 : Mnemonic = "v_mul_lo_u16"; // "v_mul_lo_u16_e64"
3444 0 : return;
3445 : }
3446 : break;
3447 : case '3': // 1 string to match.
3448 0 : if (memcmp(Mnemonic.data()+11, "2_e64", 5))
3449 : break;
3450 0 : Mnemonic = "v_mul_lo_u32"; // "v_mul_lo_u32_e64"
3451 0 : return;
3452 : }
3453 : break;
3454 : }
3455 : break;
3456 : }
3457 : break;
3458 : case 'l': // 1 string to match.
3459 0 : if (memcmp(Mnemonic.data()+6, "it_f32_e64", 10))
3460 : break;
3461 0 : Mnemonic = "v_mullit_f32"; // "v_mullit_f32_e64"
3462 0 : return;
3463 : }
3464 : break;
3465 : case 's': // 8 strings to match.
3466 0 : if (memcmp(Mnemonic.data()+3, "ubrev_", 6))
3467 : break;
3468 0 : switch (Mnemonic[9]) {
3469 : default: break;
3470 : case 'f': // 4 strings to match.
3471 0 : switch (Mnemonic[10]) {
3472 : default: break;
3473 : case '1': // 2 strings to match.
3474 0 : if (memcmp(Mnemonic.data()+11, "6_e", 3))
3475 : break;
3476 0 : switch (Mnemonic[14]) {
3477 : default: break;
3478 : case '3': // 1 string to match.
3479 0 : if (Mnemonic[15] != '2')
3480 : break;
3481 0 : Mnemonic = "v_subrev_f16"; // "v_subrev_f16_e32"
3482 0 : return;
3483 : case '6': // 1 string to match.
3484 0 : if (Mnemonic[15] != '4')
3485 : break;
3486 0 : Mnemonic = "v_subrev_f16"; // "v_subrev_f16_e64"
3487 0 : return;
3488 : }
3489 : break;
3490 : case '3': // 2 strings to match.
3491 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
3492 : break;
3493 0 : switch (Mnemonic[14]) {
3494 : default: break;
3495 : case '3': // 1 string to match.
3496 0 : if (Mnemonic[15] != '2')
3497 : break;
3498 0 : Mnemonic = "v_subrev_f32"; // "v_subrev_f32_e32"
3499 0 : return;
3500 : case '6': // 1 string to match.
3501 0 : if (Mnemonic[15] != '4')
3502 : break;
3503 0 : Mnemonic = "v_subrev_f32"; // "v_subrev_f32_e64"
3504 0 : return;
3505 : }
3506 : break;
3507 : }
3508 : break;
3509 : case 'i': // 2 strings to match.
3510 0 : if (memcmp(Mnemonic.data()+10, "32_e", 4))
3511 : break;
3512 0 : switch (Mnemonic[14]) {
3513 : default: break;
3514 : case '3': // 1 string to match.
3515 0 : if (Mnemonic[15] != '2')
3516 : break;
3517 0 : Mnemonic = "v_subrev_i32"; // "v_subrev_i32_e32"
3518 0 : return;
3519 : case '6': // 1 string to match.
3520 0 : if (Mnemonic[15] != '4')
3521 : break;
3522 0 : Mnemonic = "v_subrev_i32"; // "v_subrev_i32_e64"
3523 0 : return;
3524 : }
3525 : break;
3526 : case 'u': // 2 strings to match.
3527 0 : if (memcmp(Mnemonic.data()+10, "16_e", 4))
3528 : break;
3529 0 : switch (Mnemonic[14]) {
3530 : default: break;
3531 : case '3': // 1 string to match.
3532 0 : if (Mnemonic[15] != '2')
3533 : break;
3534 0 : Mnemonic = "v_subrev_u16"; // "v_subrev_u16_e32"
3535 0 : return;
3536 : case '6': // 1 string to match.
3537 0 : if (Mnemonic[15] != '4')
3538 : break;
3539 0 : Mnemonic = "v_subrev_u16"; // "v_subrev_u16_e64"
3540 0 : return;
3541 : }
3542 : break;
3543 : }
3544 : break;
3545 : }
3546 : break;
3547 : case 17: // 201 strings to match.
3548 138 : if (memcmp(Mnemonic.data()+0, "v_", 2))
3549 : break;
3550 80 : switch (Mnemonic[2]) {
3551 : default: break;
3552 : case 'a': // 5 strings to match.
3553 0 : if (memcmp(Mnemonic.data()+3, "shrrev_", 7))
3554 : break;
3555 0 : switch (Mnemonic[10]) {
3556 : default: break;
3557 : case 'b': // 2 strings to match.
3558 0 : if (memcmp(Mnemonic.data()+11, "16_e", 4))
3559 : break;
3560 0 : switch (Mnemonic[15]) {
3561 : default: break;
3562 : case '3': // 1 string to match.
3563 0 : if (Mnemonic[16] != '2')
3564 : break;
3565 0 : Mnemonic = "v_ashrrev_b16"; // "v_ashrrev_b16_e32"
3566 0 : return;
3567 : case '6': // 1 string to match.
3568 0 : if (Mnemonic[16] != '4')
3569 : break;
3570 0 : Mnemonic = "v_ashrrev_b16"; // "v_ashrrev_b16_e64"
3571 0 : return;
3572 : }
3573 : break;
3574 : case 'i': // 3 strings to match.
3575 0 : switch (Mnemonic[11]) {
3576 : default: break;
3577 : case '3': // 2 strings to match.
3578 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
3579 : break;
3580 0 : switch (Mnemonic[15]) {
3581 : default: break;
3582 : case '3': // 1 string to match.
3583 0 : if (Mnemonic[16] != '2')
3584 : break;
3585 0 : Mnemonic = "v_ashrrev_i32"; // "v_ashrrev_i32_e32"
3586 0 : return;
3587 : case '6': // 1 string to match.
3588 0 : if (Mnemonic[16] != '4')
3589 : break;
3590 0 : Mnemonic = "v_ashrrev_i32"; // "v_ashrrev_i32_e64"
3591 0 : return;
3592 : }
3593 : break;
3594 : case '6': // 1 string to match.
3595 0 : if (memcmp(Mnemonic.data()+12, "4_e64", 5))
3596 : break;
3597 0 : Mnemonic = "v_ashrrev_i64"; // "v_ashrrev_i64_e64"
3598 0 : return;
3599 : }
3600 : break;
3601 : }
3602 : break;
3603 : case 'c': // 170 strings to match.
3604 32 : switch (Mnemonic[3]) {
3605 : default: break;
3606 : case 'm': // 136 strings to match.
3607 0 : if (Mnemonic[4] != 'p')
3608 : break;
3609 0 : switch (Mnemonic[5]) {
3610 : default: break;
3611 : case '_': // 28 strings to match.
3612 0 : switch (Mnemonic[6]) {
3613 : default: break;
3614 : case 'n': // 24 strings to match.
3615 0 : switch (Mnemonic[7]) {
3616 : default: break;
3617 : case 'e': // 4 strings to match.
3618 0 : if (memcmp(Mnemonic.data()+8, "q_f", 3))
3619 : break;
3620 0 : switch (Mnemonic[11]) {
3621 : default: break;
3622 : case '3': // 2 strings to match.
3623 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
3624 : break;
3625 0 : switch (Mnemonic[15]) {
3626 : default: break;
3627 : case '3': // 1 string to match.
3628 0 : if (Mnemonic[16] != '2')
3629 : break;
3630 0 : Mnemonic = "v_cmp_neq_f32"; // "v_cmp_neq_f32_e32"
3631 0 : return;
3632 : case '6': // 1 string to match.
3633 0 : if (Mnemonic[16] != '4')
3634 : break;
3635 0 : Mnemonic = "v_cmp_neq_f32"; // "v_cmp_neq_f32_e64"
3636 0 : return;
3637 : }
3638 : break;
3639 : case '6': // 2 strings to match.
3640 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
3641 : break;
3642 0 : switch (Mnemonic[15]) {
3643 : default: break;
3644 : case '3': // 1 string to match.
3645 0 : if (Mnemonic[16] != '2')
3646 : break;
3647 0 : Mnemonic = "v_cmp_neq_f64"; // "v_cmp_neq_f64_e32"
3648 0 : return;
3649 : case '6': // 1 string to match.
3650 0 : if (Mnemonic[16] != '4')
3651 : break;
3652 0 : Mnemonic = "v_cmp_neq_f64"; // "v_cmp_neq_f64_e64"
3653 0 : return;
3654 : }
3655 : break;
3656 : }
3657 : break;
3658 : case 'g': // 8 strings to match.
3659 0 : switch (Mnemonic[8]) {
3660 : default: break;
3661 : case 'e': // 4 strings to match.
3662 0 : if (memcmp(Mnemonic.data()+9, "_f", 2))
3663 : break;
3664 0 : switch (Mnemonic[11]) {
3665 : default: break;
3666 : case '3': // 2 strings to match.
3667 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
3668 : break;
3669 0 : switch (Mnemonic[15]) {
3670 : default: break;
3671 : case '3': // 1 string to match.
3672 0 : if (Mnemonic[16] != '2')
3673 : break;
3674 0 : Mnemonic = "v_cmp_nge_f32"; // "v_cmp_nge_f32_e32"
3675 0 : return;
3676 : case '6': // 1 string to match.
3677 0 : if (Mnemonic[16] != '4')
3678 : break;
3679 0 : Mnemonic = "v_cmp_nge_f32"; // "v_cmp_nge_f32_e64"
3680 0 : return;
3681 : }
3682 : break;
3683 : case '6': // 2 strings to match.
3684 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
3685 : break;
3686 0 : switch (Mnemonic[15]) {
3687 : default: break;
3688 : case '3': // 1 string to match.
3689 0 : if (Mnemonic[16] != '2')
3690 : break;
3691 0 : Mnemonic = "v_cmp_nge_f64"; // "v_cmp_nge_f64_e32"
3692 0 : return;
3693 : case '6': // 1 string to match.
3694 0 : if (Mnemonic[16] != '4')
3695 : break;
3696 0 : Mnemonic = "v_cmp_nge_f64"; // "v_cmp_nge_f64_e64"
3697 0 : return;
3698 : }
3699 : break;
3700 : }
3701 : break;
3702 : case 't': // 4 strings to match.
3703 0 : if (memcmp(Mnemonic.data()+9, "_f", 2))
3704 : break;
3705 0 : switch (Mnemonic[11]) {
3706 : default: break;
3707 : case '3': // 2 strings to match.
3708 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
3709 : break;
3710 0 : switch (Mnemonic[15]) {
3711 : default: break;
3712 : case '3': // 1 string to match.
3713 0 : if (Mnemonic[16] != '2')
3714 : break;
3715 0 : Mnemonic = "v_cmp_ngt_f32"; // "v_cmp_ngt_f32_e32"
3716 0 : return;
3717 : case '6': // 1 string to match.
3718 0 : if (Mnemonic[16] != '4')
3719 : break;
3720 0 : Mnemonic = "v_cmp_ngt_f32"; // "v_cmp_ngt_f32_e64"
3721 0 : return;
3722 : }
3723 : break;
3724 : case '6': // 2 strings to match.
3725 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
3726 : break;
3727 0 : switch (Mnemonic[15]) {
3728 : default: break;
3729 : case '3': // 1 string to match.
3730 0 : if (Mnemonic[16] != '2')
3731 : break;
3732 0 : Mnemonic = "v_cmp_ngt_f64"; // "v_cmp_ngt_f64_e32"
3733 0 : return;
3734 : case '6': // 1 string to match.
3735 0 : if (Mnemonic[16] != '4')
3736 : break;
3737 0 : Mnemonic = "v_cmp_ngt_f64"; // "v_cmp_ngt_f64_e64"
3738 0 : return;
3739 : }
3740 : break;
3741 : }
3742 : break;
3743 : }
3744 : break;
3745 : case 'l': // 12 strings to match.
3746 0 : switch (Mnemonic[8]) {
3747 : default: break;
3748 : case 'e': // 4 strings to match.
3749 0 : if (memcmp(Mnemonic.data()+9, "_f", 2))
3750 : break;
3751 0 : switch (Mnemonic[11]) {
3752 : default: break;
3753 : case '3': // 2 strings to match.
3754 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
3755 : break;
3756 0 : switch (Mnemonic[15]) {
3757 : default: break;
3758 : case '3': // 1 string to match.
3759 0 : if (Mnemonic[16] != '2')
3760 : break;
3761 0 : Mnemonic = "v_cmp_nle_f32"; // "v_cmp_nle_f32_e32"
3762 0 : return;
3763 : case '6': // 1 string to match.
3764 0 : if (Mnemonic[16] != '4')
3765 : break;
3766 0 : Mnemonic = "v_cmp_nle_f32"; // "v_cmp_nle_f32_e64"
3767 0 : return;
3768 : }
3769 : break;
3770 : case '6': // 2 strings to match.
3771 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
3772 : break;
3773 0 : switch (Mnemonic[15]) {
3774 : default: break;
3775 : case '3': // 1 string to match.
3776 0 : if (Mnemonic[16] != '2')
3777 : break;
3778 0 : Mnemonic = "v_cmp_nle_f64"; // "v_cmp_nle_f64_e32"
3779 0 : return;
3780 : case '6': // 1 string to match.
3781 0 : if (Mnemonic[16] != '4')
3782 : break;
3783 0 : Mnemonic = "v_cmp_nle_f64"; // "v_cmp_nle_f64_e64"
3784 0 : return;
3785 : }
3786 : break;
3787 : }
3788 : break;
3789 : case 'g': // 4 strings to match.
3790 0 : if (memcmp(Mnemonic.data()+9, "_f", 2))
3791 : break;
3792 0 : switch (Mnemonic[11]) {
3793 : default: break;
3794 : case '3': // 2 strings to match.
3795 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
3796 : break;
3797 0 : switch (Mnemonic[15]) {
3798 : default: break;
3799 : case '3': // 1 string to match.
3800 0 : if (Mnemonic[16] != '2')
3801 : break;
3802 0 : Mnemonic = "v_cmp_nlg_f32"; // "v_cmp_nlg_f32_e32"
3803 0 : return;
3804 : case '6': // 1 string to match.
3805 0 : if (Mnemonic[16] != '4')
3806 : break;
3807 0 : Mnemonic = "v_cmp_nlg_f32"; // "v_cmp_nlg_f32_e64"
3808 0 : return;
3809 : }
3810 : break;
3811 : case '6': // 2 strings to match.
3812 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
3813 : break;
3814 0 : switch (Mnemonic[15]) {
3815 : default: break;
3816 : case '3': // 1 string to match.
3817 0 : if (Mnemonic[16] != '2')
3818 : break;
3819 0 : Mnemonic = "v_cmp_nlg_f64"; // "v_cmp_nlg_f64_e32"
3820 0 : return;
3821 : case '6': // 1 string to match.
3822 0 : if (Mnemonic[16] != '4')
3823 : break;
3824 0 : Mnemonic = "v_cmp_nlg_f64"; // "v_cmp_nlg_f64_e64"
3825 0 : return;
3826 : }
3827 : break;
3828 : }
3829 : break;
3830 : case 't': // 4 strings to match.
3831 0 : if (memcmp(Mnemonic.data()+9, "_f", 2))
3832 : break;
3833 0 : switch (Mnemonic[11]) {
3834 : default: break;
3835 : case '3': // 2 strings to match.
3836 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
3837 : break;
3838 0 : switch (Mnemonic[15]) {
3839 : default: break;
3840 : case '3': // 1 string to match.
3841 0 : if (Mnemonic[16] != '2')
3842 : break;
3843 0 : Mnemonic = "v_cmp_nlt_f32"; // "v_cmp_nlt_f32_e32"
3844 0 : return;
3845 : case '6': // 1 string to match.
3846 0 : if (Mnemonic[16] != '4')
3847 : break;
3848 0 : Mnemonic = "v_cmp_nlt_f32"; // "v_cmp_nlt_f32_e64"
3849 0 : return;
3850 : }
3851 : break;
3852 : case '6': // 2 strings to match.
3853 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
3854 : break;
3855 0 : switch (Mnemonic[15]) {
3856 : default: break;
3857 : case '3': // 1 string to match.
3858 0 : if (Mnemonic[16] != '2')
3859 : break;
3860 0 : Mnemonic = "v_cmp_nlt_f64"; // "v_cmp_nlt_f64_e32"
3861 0 : return;
3862 : case '6': // 1 string to match.
3863 0 : if (Mnemonic[16] != '4')
3864 : break;
3865 0 : Mnemonic = "v_cmp_nlt_f64"; // "v_cmp_nlt_f64_e64"
3866 0 : return;
3867 : }
3868 : break;
3869 : }
3870 : break;
3871 : }
3872 : break;
3873 : }
3874 : break;
3875 : case 't': // 4 strings to match.
3876 0 : if (memcmp(Mnemonic.data()+7, "ru_f", 4))
3877 : break;
3878 0 : switch (Mnemonic[11]) {
3879 : default: break;
3880 : case '3': // 2 strings to match.
3881 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
3882 : break;
3883 0 : switch (Mnemonic[15]) {
3884 : default: break;
3885 : case '3': // 1 string to match.
3886 0 : if (Mnemonic[16] != '2')
3887 : break;
3888 0 : Mnemonic = "v_cmp_tru_f32"; // "v_cmp_tru_f32_e32"
3889 0 : return;
3890 : case '6': // 1 string to match.
3891 0 : if (Mnemonic[16] != '4')
3892 : break;
3893 0 : Mnemonic = "v_cmp_tru_f32"; // "v_cmp_tru_f32_e64"
3894 0 : return;
3895 : }
3896 : break;
3897 : case '6': // 2 strings to match.
3898 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
3899 : break;
3900 0 : switch (Mnemonic[15]) {
3901 : default: break;
3902 : case '3': // 1 string to match.
3903 0 : if (Mnemonic[16] != '2')
3904 : break;
3905 0 : Mnemonic = "v_cmp_tru_f64"; // "v_cmp_tru_f64_e32"
3906 0 : return;
3907 : case '6': // 1 string to match.
3908 0 : if (Mnemonic[16] != '4')
3909 : break;
3910 0 : Mnemonic = "v_cmp_tru_f64"; // "v_cmp_tru_f64_e64"
3911 0 : return;
3912 : }
3913 : break;
3914 : }
3915 : break;
3916 : }
3917 : break;
3918 : case 's': // 36 strings to match.
3919 0 : switch (Mnemonic[6]) {
3920 : default: break;
3921 : case '_': // 24 strings to match.
3922 0 : switch (Mnemonic[7]) {
3923 : default: break;
3924 : case 'e': // 4 strings to match.
3925 0 : if (memcmp(Mnemonic.data()+8, "q_f", 3))
3926 : break;
3927 0 : switch (Mnemonic[11]) {
3928 : default: break;
3929 : case '3': // 2 strings to match.
3930 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
3931 : break;
3932 0 : switch (Mnemonic[15]) {
3933 : default: break;
3934 : case '3': // 1 string to match.
3935 0 : if (Mnemonic[16] != '2')
3936 : break;
3937 0 : Mnemonic = "v_cmps_eq_f32"; // "v_cmps_eq_f32_e32"
3938 0 : return;
3939 : case '6': // 1 string to match.
3940 0 : if (Mnemonic[16] != '4')
3941 : break;
3942 0 : Mnemonic = "v_cmps_eq_f32"; // "v_cmps_eq_f32_e64"
3943 0 : return;
3944 : }
3945 : break;
3946 : case '6': // 2 strings to match.
3947 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
3948 : break;
3949 0 : switch (Mnemonic[15]) {
3950 : default: break;
3951 : case '3': // 1 string to match.
3952 0 : if (Mnemonic[16] != '2')
3953 : break;
3954 0 : Mnemonic = "v_cmps_eq_f64"; // "v_cmps_eq_f64_e32"
3955 0 : return;
3956 : case '6': // 1 string to match.
3957 0 : if (Mnemonic[16] != '4')
3958 : break;
3959 0 : Mnemonic = "v_cmps_eq_f64"; // "v_cmps_eq_f64_e64"
3960 0 : return;
3961 : }
3962 : break;
3963 : }
3964 : break;
3965 : case 'g': // 8 strings to match.
3966 0 : switch (Mnemonic[8]) {
3967 : default: break;
3968 : case 'e': // 4 strings to match.
3969 0 : if (memcmp(Mnemonic.data()+9, "_f", 2))
3970 : break;
3971 0 : switch (Mnemonic[11]) {
3972 : default: break;
3973 : case '3': // 2 strings to match.
3974 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
3975 : break;
3976 0 : switch (Mnemonic[15]) {
3977 : default: break;
3978 : case '3': // 1 string to match.
3979 0 : if (Mnemonic[16] != '2')
3980 : break;
3981 0 : Mnemonic = "v_cmps_ge_f32"; // "v_cmps_ge_f32_e32"
3982 0 : return;
3983 : case '6': // 1 string to match.
3984 0 : if (Mnemonic[16] != '4')
3985 : break;
3986 0 : Mnemonic = "v_cmps_ge_f32"; // "v_cmps_ge_f32_e64"
3987 0 : return;
3988 : }
3989 : break;
3990 : case '6': // 2 strings to match.
3991 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
3992 : break;
3993 0 : switch (Mnemonic[15]) {
3994 : default: break;
3995 : case '3': // 1 string to match.
3996 0 : if (Mnemonic[16] != '2')
3997 : break;
3998 0 : Mnemonic = "v_cmps_ge_f64"; // "v_cmps_ge_f64_e32"
3999 0 : return;
4000 : case '6': // 1 string to match.
4001 0 : if (Mnemonic[16] != '4')
4002 : break;
4003 0 : Mnemonic = "v_cmps_ge_f64"; // "v_cmps_ge_f64_e64"
4004 0 : return;
4005 : }
4006 : break;
4007 : }
4008 : break;
4009 : case 't': // 4 strings to match.
4010 0 : if (memcmp(Mnemonic.data()+9, "_f", 2))
4011 : break;
4012 0 : switch (Mnemonic[11]) {
4013 : default: break;
4014 : case '3': // 2 strings to match.
4015 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
4016 : break;
4017 0 : switch (Mnemonic[15]) {
4018 : default: break;
4019 : case '3': // 1 string to match.
4020 0 : if (Mnemonic[16] != '2')
4021 : break;
4022 0 : Mnemonic = "v_cmps_gt_f32"; // "v_cmps_gt_f32_e32"
4023 0 : return;
4024 : case '6': // 1 string to match.
4025 0 : if (Mnemonic[16] != '4')
4026 : break;
4027 0 : Mnemonic = "v_cmps_gt_f32"; // "v_cmps_gt_f32_e64"
4028 0 : return;
4029 : }
4030 : break;
4031 : case '6': // 2 strings to match.
4032 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
4033 : break;
4034 0 : switch (Mnemonic[15]) {
4035 : default: break;
4036 : case '3': // 1 string to match.
4037 0 : if (Mnemonic[16] != '2')
4038 : break;
4039 0 : Mnemonic = "v_cmps_gt_f64"; // "v_cmps_gt_f64_e32"
4040 0 : return;
4041 : case '6': // 1 string to match.
4042 0 : if (Mnemonic[16] != '4')
4043 : break;
4044 0 : Mnemonic = "v_cmps_gt_f64"; // "v_cmps_gt_f64_e64"
4045 0 : return;
4046 : }
4047 : break;
4048 : }
4049 : break;
4050 : }
4051 : break;
4052 : case 'l': // 12 strings to match.
4053 0 : switch (Mnemonic[8]) {
4054 : default: break;
4055 : case 'e': // 4 strings to match.
4056 0 : if (memcmp(Mnemonic.data()+9, "_f", 2))
4057 : break;
4058 0 : switch (Mnemonic[11]) {
4059 : default: break;
4060 : case '3': // 2 strings to match.
4061 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
4062 : break;
4063 0 : switch (Mnemonic[15]) {
4064 : default: break;
4065 : case '3': // 1 string to match.
4066 0 : if (Mnemonic[16] != '2')
4067 : break;
4068 0 : Mnemonic = "v_cmps_le_f32"; // "v_cmps_le_f32_e32"
4069 0 : return;
4070 : case '6': // 1 string to match.
4071 0 : if (Mnemonic[16] != '4')
4072 : break;
4073 0 : Mnemonic = "v_cmps_le_f32"; // "v_cmps_le_f32_e64"
4074 0 : return;
4075 : }
4076 : break;
4077 : case '6': // 2 strings to match.
4078 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
4079 : break;
4080 0 : switch (Mnemonic[15]) {
4081 : default: break;
4082 : case '3': // 1 string to match.
4083 0 : if (Mnemonic[16] != '2')
4084 : break;
4085 0 : Mnemonic = "v_cmps_le_f64"; // "v_cmps_le_f64_e32"
4086 0 : return;
4087 : case '6': // 1 string to match.
4088 0 : if (Mnemonic[16] != '4')
4089 : break;
4090 0 : Mnemonic = "v_cmps_le_f64"; // "v_cmps_le_f64_e64"
4091 0 : return;
4092 : }
4093 : break;
4094 : }
4095 : break;
4096 : case 'g': // 4 strings to match.
4097 0 : if (memcmp(Mnemonic.data()+9, "_f", 2))
4098 : break;
4099 0 : switch (Mnemonic[11]) {
4100 : default: break;
4101 : case '3': // 2 strings to match.
4102 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
4103 : break;
4104 0 : switch (Mnemonic[15]) {
4105 : default: break;
4106 : case '3': // 1 string to match.
4107 0 : if (Mnemonic[16] != '2')
4108 : break;
4109 0 : Mnemonic = "v_cmps_lg_f32"; // "v_cmps_lg_f32_e32"
4110 0 : return;
4111 : case '6': // 1 string to match.
4112 0 : if (Mnemonic[16] != '4')
4113 : break;
4114 0 : Mnemonic = "v_cmps_lg_f32"; // "v_cmps_lg_f32_e64"
4115 0 : return;
4116 : }
4117 : break;
4118 : case '6': // 2 strings to match.
4119 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
4120 : break;
4121 0 : switch (Mnemonic[15]) {
4122 : default: break;
4123 : case '3': // 1 string to match.
4124 0 : if (Mnemonic[16] != '2')
4125 : break;
4126 0 : Mnemonic = "v_cmps_lg_f64"; // "v_cmps_lg_f64_e32"
4127 0 : return;
4128 : case '6': // 1 string to match.
4129 0 : if (Mnemonic[16] != '4')
4130 : break;
4131 0 : Mnemonic = "v_cmps_lg_f64"; // "v_cmps_lg_f64_e64"
4132 0 : return;
4133 : }
4134 : break;
4135 : }
4136 : break;
4137 : case 't': // 4 strings to match.
4138 0 : if (memcmp(Mnemonic.data()+9, "_f", 2))
4139 : break;
4140 0 : switch (Mnemonic[11]) {
4141 : default: break;
4142 : case '3': // 2 strings to match.
4143 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
4144 : break;
4145 0 : switch (Mnemonic[15]) {
4146 : default: break;
4147 : case '3': // 1 string to match.
4148 0 : if (Mnemonic[16] != '2')
4149 : break;
4150 0 : Mnemonic = "v_cmps_lt_f32"; // "v_cmps_lt_f32_e32"
4151 0 : return;
4152 : case '6': // 1 string to match.
4153 0 : if (Mnemonic[16] != '4')
4154 : break;
4155 0 : Mnemonic = "v_cmps_lt_f32"; // "v_cmps_lt_f32_e64"
4156 0 : return;
4157 : }
4158 : break;
4159 : case '6': // 2 strings to match.
4160 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
4161 : break;
4162 0 : switch (Mnemonic[15]) {
4163 : default: break;
4164 : case '3': // 1 string to match.
4165 0 : if (Mnemonic[16] != '2')
4166 : break;
4167 0 : Mnemonic = "v_cmps_lt_f64"; // "v_cmps_lt_f64_e32"
4168 0 : return;
4169 : case '6': // 1 string to match.
4170 0 : if (Mnemonic[16] != '4')
4171 : break;
4172 0 : Mnemonic = "v_cmps_lt_f64"; // "v_cmps_lt_f64_e64"
4173 0 : return;
4174 : }
4175 : break;
4176 : }
4177 : break;
4178 : }
4179 : break;
4180 : }
4181 : break;
4182 : case 'x': // 12 strings to match.
4183 0 : if (Mnemonic[7] != '_')
4184 : break;
4185 0 : switch (Mnemonic[8]) {
4186 : default: break;
4187 : case 'f': // 4 strings to match.
4188 0 : if (memcmp(Mnemonic.data()+9, "_f", 2))
4189 : break;
4190 0 : switch (Mnemonic[11]) {
4191 : default: break;
4192 : case '3': // 2 strings to match.
4193 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
4194 : break;
4195 0 : switch (Mnemonic[15]) {
4196 : default: break;
4197 : case '3': // 1 string to match.
4198 0 : if (Mnemonic[16] != '2')
4199 : break;
4200 0 : Mnemonic = "v_cmpsx_f_f32"; // "v_cmpsx_f_f32_e32"
4201 0 : return;
4202 : case '6': // 1 string to match.
4203 0 : if (Mnemonic[16] != '4')
4204 : break;
4205 0 : Mnemonic = "v_cmpsx_f_f32"; // "v_cmpsx_f_f32_e64"
4206 0 : return;
4207 : }
4208 : break;
4209 : case '6': // 2 strings to match.
4210 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
4211 : break;
4212 0 : switch (Mnemonic[15]) {
4213 : default: break;
4214 : case '3': // 1 string to match.
4215 0 : if (Mnemonic[16] != '2')
4216 : break;
4217 0 : Mnemonic = "v_cmpsx_f_f64"; // "v_cmpsx_f_f64_e32"
4218 0 : return;
4219 : case '6': // 1 string to match.
4220 0 : if (Mnemonic[16] != '4')
4221 : break;
4222 0 : Mnemonic = "v_cmpsx_f_f64"; // "v_cmpsx_f_f64_e64"
4223 0 : return;
4224 : }
4225 : break;
4226 : }
4227 : break;
4228 : case 'o': // 4 strings to match.
4229 0 : if (memcmp(Mnemonic.data()+9, "_f", 2))
4230 : break;
4231 0 : switch (Mnemonic[11]) {
4232 : default: break;
4233 : case '3': // 2 strings to match.
4234 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
4235 : break;
4236 0 : switch (Mnemonic[15]) {
4237 : default: break;
4238 : case '3': // 1 string to match.
4239 0 : if (Mnemonic[16] != '2')
4240 : break;
4241 0 : Mnemonic = "v_cmpsx_o_f32"; // "v_cmpsx_o_f32_e32"
4242 0 : return;
4243 : case '6': // 1 string to match.
4244 0 : if (Mnemonic[16] != '4')
4245 : break;
4246 0 : Mnemonic = "v_cmpsx_o_f32"; // "v_cmpsx_o_f32_e64"
4247 0 : return;
4248 : }
4249 : break;
4250 : case '6': // 2 strings to match.
4251 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
4252 : break;
4253 0 : switch (Mnemonic[15]) {
4254 : default: break;
4255 : case '3': // 1 string to match.
4256 0 : if (Mnemonic[16] != '2')
4257 : break;
4258 0 : Mnemonic = "v_cmpsx_o_f64"; // "v_cmpsx_o_f64_e32"
4259 0 : return;
4260 : case '6': // 1 string to match.
4261 0 : if (Mnemonic[16] != '4')
4262 : break;
4263 0 : Mnemonic = "v_cmpsx_o_f64"; // "v_cmpsx_o_f64_e64"
4264 0 : return;
4265 : }
4266 : break;
4267 : }
4268 : break;
4269 : case 'u': // 4 strings to match.
4270 0 : if (memcmp(Mnemonic.data()+9, "_f", 2))
4271 : break;
4272 0 : switch (Mnemonic[11]) {
4273 : default: break;
4274 : case '3': // 2 strings to match.
4275 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
4276 : break;
4277 0 : switch (Mnemonic[15]) {
4278 : default: break;
4279 : case '3': // 1 string to match.
4280 0 : if (Mnemonic[16] != '2')
4281 : break;
4282 0 : Mnemonic = "v_cmpsx_u_f32"; // "v_cmpsx_u_f32_e32"
4283 0 : return;
4284 : case '6': // 1 string to match.
4285 0 : if (Mnemonic[16] != '4')
4286 : break;
4287 0 : Mnemonic = "v_cmpsx_u_f32"; // "v_cmpsx_u_f32_e64"
4288 0 : return;
4289 : }
4290 : break;
4291 : case '6': // 2 strings to match.
4292 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
4293 : break;
4294 0 : switch (Mnemonic[15]) {
4295 : default: break;
4296 : case '3': // 1 string to match.
4297 0 : if (Mnemonic[16] != '2')
4298 : break;
4299 0 : Mnemonic = "v_cmpsx_u_f64"; // "v_cmpsx_u_f64_e32"
4300 0 : return;
4301 : case '6': // 1 string to match.
4302 0 : if (Mnemonic[16] != '4')
4303 : break;
4304 0 : Mnemonic = "v_cmpsx_u_f64"; // "v_cmpsx_u_f64_e64"
4305 0 : return;
4306 : }
4307 : break;
4308 : }
4309 : break;
4310 : }
4311 : break;
4312 : }
4313 : break;
4314 : case 'x': // 72 strings to match.
4315 0 : if (Mnemonic[6] != '_')
4316 : break;
4317 0 : switch (Mnemonic[7]) {
4318 : default: break;
4319 : case 'e': // 12 strings to match.
4320 0 : if (memcmp(Mnemonic.data()+8, "q_", 2))
4321 : break;
4322 0 : switch (Mnemonic[10]) {
4323 : default: break;
4324 : case 'f': // 4 strings to match.
4325 0 : switch (Mnemonic[11]) {
4326 : default: break;
4327 : case '3': // 2 strings to match.
4328 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
4329 : break;
4330 0 : switch (Mnemonic[15]) {
4331 : default: break;
4332 : case '3': // 1 string to match.
4333 0 : if (Mnemonic[16] != '2')
4334 : break;
4335 0 : Mnemonic = "v_cmpx_eq_f32"; // "v_cmpx_eq_f32_e32"
4336 0 : return;
4337 : case '6': // 1 string to match.
4338 0 : if (Mnemonic[16] != '4')
4339 : break;
4340 0 : Mnemonic = "v_cmpx_eq_f32"; // "v_cmpx_eq_f32_e64"
4341 0 : return;
4342 : }
4343 : break;
4344 : case '6': // 2 strings to match.
4345 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
4346 : break;
4347 0 : switch (Mnemonic[15]) {
4348 : default: break;
4349 : case '3': // 1 string to match.
4350 0 : if (Mnemonic[16] != '2')
4351 : break;
4352 0 : Mnemonic = "v_cmpx_eq_f64"; // "v_cmpx_eq_f64_e32"
4353 0 : return;
4354 : case '6': // 1 string to match.
4355 0 : if (Mnemonic[16] != '4')
4356 : break;
4357 0 : Mnemonic = "v_cmpx_eq_f64"; // "v_cmpx_eq_f64_e64"
4358 0 : return;
4359 : }
4360 : break;
4361 : }
4362 : break;
4363 : case 'i': // 4 strings to match.
4364 0 : switch (Mnemonic[11]) {
4365 : default: break;
4366 : case '3': // 2 strings to match.
4367 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
4368 : break;
4369 0 : switch (Mnemonic[15]) {
4370 : default: break;
4371 : case '3': // 1 string to match.
4372 0 : if (Mnemonic[16] != '2')
4373 : break;
4374 0 : Mnemonic = "v_cmpx_eq_i32"; // "v_cmpx_eq_i32_e32"
4375 0 : return;
4376 : case '6': // 1 string to match.
4377 0 : if (Mnemonic[16] != '4')
4378 : break;
4379 0 : Mnemonic = "v_cmpx_eq_i32"; // "v_cmpx_eq_i32_e64"
4380 0 : return;
4381 : }
4382 : break;
4383 : case '6': // 2 strings to match.
4384 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
4385 : break;
4386 0 : switch (Mnemonic[15]) {
4387 : default: break;
4388 : case '3': // 1 string to match.
4389 0 : if (Mnemonic[16] != '2')
4390 : break;
4391 0 : Mnemonic = "v_cmpx_eq_i64"; // "v_cmpx_eq_i64_e32"
4392 0 : return;
4393 : case '6': // 1 string to match.
4394 0 : if (Mnemonic[16] != '4')
4395 : break;
4396 0 : Mnemonic = "v_cmpx_eq_i64"; // "v_cmpx_eq_i64_e64"
4397 0 : return;
4398 : }
4399 : break;
4400 : }
4401 : break;
4402 : case 'u': // 4 strings to match.
4403 0 : switch (Mnemonic[11]) {
4404 : default: break;
4405 : case '3': // 2 strings to match.
4406 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
4407 : break;
4408 0 : switch (Mnemonic[15]) {
4409 : default: break;
4410 : case '3': // 1 string to match.
4411 0 : if (Mnemonic[16] != '2')
4412 : break;
4413 0 : Mnemonic = "v_cmpx_eq_u32"; // "v_cmpx_eq_u32_e32"
4414 0 : return;
4415 : case '6': // 1 string to match.
4416 0 : if (Mnemonic[16] != '4')
4417 : break;
4418 0 : Mnemonic = "v_cmpx_eq_u32"; // "v_cmpx_eq_u32_e64"
4419 0 : return;
4420 : }
4421 : break;
4422 : case '6': // 2 strings to match.
4423 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
4424 : break;
4425 0 : switch (Mnemonic[15]) {
4426 : default: break;
4427 : case '3': // 1 string to match.
4428 0 : if (Mnemonic[16] != '2')
4429 : break;
4430 0 : Mnemonic = "v_cmpx_eq_u64"; // "v_cmpx_eq_u64_e32"
4431 0 : return;
4432 : case '6': // 1 string to match.
4433 0 : if (Mnemonic[16] != '4')
4434 : break;
4435 0 : Mnemonic = "v_cmpx_eq_u64"; // "v_cmpx_eq_u64_e64"
4436 0 : return;
4437 : }
4438 : break;
4439 : }
4440 : break;
4441 : }
4442 : break;
4443 : case 'g': // 24 strings to match.
4444 0 : switch (Mnemonic[8]) {
4445 : default: break;
4446 : case 'e': // 12 strings to match.
4447 0 : if (Mnemonic[9] != '_')
4448 : break;
4449 0 : switch (Mnemonic[10]) {
4450 : default: break;
4451 : case 'f': // 4 strings to match.
4452 0 : switch (Mnemonic[11]) {
4453 : default: break;
4454 : case '3': // 2 strings to match.
4455 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
4456 : break;
4457 0 : switch (Mnemonic[15]) {
4458 : default: break;
4459 : case '3': // 1 string to match.
4460 0 : if (Mnemonic[16] != '2')
4461 : break;
4462 0 : Mnemonic = "v_cmpx_ge_f32"; // "v_cmpx_ge_f32_e32"
4463 0 : return;
4464 : case '6': // 1 string to match.
4465 0 : if (Mnemonic[16] != '4')
4466 : break;
4467 0 : Mnemonic = "v_cmpx_ge_f32"; // "v_cmpx_ge_f32_e64"
4468 0 : return;
4469 : }
4470 : break;
4471 : case '6': // 2 strings to match.
4472 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
4473 : break;
4474 0 : switch (Mnemonic[15]) {
4475 : default: break;
4476 : case '3': // 1 string to match.
4477 0 : if (Mnemonic[16] != '2')
4478 : break;
4479 0 : Mnemonic = "v_cmpx_ge_f64"; // "v_cmpx_ge_f64_e32"
4480 0 : return;
4481 : case '6': // 1 string to match.
4482 0 : if (Mnemonic[16] != '4')
4483 : break;
4484 0 : Mnemonic = "v_cmpx_ge_f64"; // "v_cmpx_ge_f64_e64"
4485 0 : return;
4486 : }
4487 : break;
4488 : }
4489 : break;
4490 : case 'i': // 4 strings to match.
4491 0 : switch (Mnemonic[11]) {
4492 : default: break;
4493 : case '3': // 2 strings to match.
4494 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
4495 : break;
4496 0 : switch (Mnemonic[15]) {
4497 : default: break;
4498 : case '3': // 1 string to match.
4499 0 : if (Mnemonic[16] != '2')
4500 : break;
4501 0 : Mnemonic = "v_cmpx_ge_i32"; // "v_cmpx_ge_i32_e32"
4502 0 : return;
4503 : case '6': // 1 string to match.
4504 0 : if (Mnemonic[16] != '4')
4505 : break;
4506 0 : Mnemonic = "v_cmpx_ge_i32"; // "v_cmpx_ge_i32_e64"
4507 0 : return;
4508 : }
4509 : break;
4510 : case '6': // 2 strings to match.
4511 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
4512 : break;
4513 0 : switch (Mnemonic[15]) {
4514 : default: break;
4515 : case '3': // 1 string to match.
4516 0 : if (Mnemonic[16] != '2')
4517 : break;
4518 0 : Mnemonic = "v_cmpx_ge_i64"; // "v_cmpx_ge_i64_e32"
4519 0 : return;
4520 : case '6': // 1 string to match.
4521 0 : if (Mnemonic[16] != '4')
4522 : break;
4523 0 : Mnemonic = "v_cmpx_ge_i64"; // "v_cmpx_ge_i64_e64"
4524 0 : return;
4525 : }
4526 : break;
4527 : }
4528 : break;
4529 : case 'u': // 4 strings to match.
4530 0 : switch (Mnemonic[11]) {
4531 : default: break;
4532 : case '3': // 2 strings to match.
4533 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
4534 : break;
4535 0 : switch (Mnemonic[15]) {
4536 : default: break;
4537 : case '3': // 1 string to match.
4538 0 : if (Mnemonic[16] != '2')
4539 : break;
4540 0 : Mnemonic = "v_cmpx_ge_u32"; // "v_cmpx_ge_u32_e32"
4541 0 : return;
4542 : case '6': // 1 string to match.
4543 0 : if (Mnemonic[16] != '4')
4544 : break;
4545 0 : Mnemonic = "v_cmpx_ge_u32"; // "v_cmpx_ge_u32_e64"
4546 0 : return;
4547 : }
4548 : break;
4549 : case '6': // 2 strings to match.
4550 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
4551 : break;
4552 0 : switch (Mnemonic[15]) {
4553 : default: break;
4554 : case '3': // 1 string to match.
4555 0 : if (Mnemonic[16] != '2')
4556 : break;
4557 0 : Mnemonic = "v_cmpx_ge_u64"; // "v_cmpx_ge_u64_e32"
4558 0 : return;
4559 : case '6': // 1 string to match.
4560 0 : if (Mnemonic[16] != '4')
4561 : break;
4562 0 : Mnemonic = "v_cmpx_ge_u64"; // "v_cmpx_ge_u64_e64"
4563 0 : return;
4564 : }
4565 : break;
4566 : }
4567 : break;
4568 : }
4569 : break;
4570 : case 't': // 12 strings to match.
4571 0 : if (Mnemonic[9] != '_')
4572 : break;
4573 0 : switch (Mnemonic[10]) {
4574 : default: break;
4575 : case 'f': // 4 strings to match.
4576 0 : switch (Mnemonic[11]) {
4577 : default: break;
4578 : case '3': // 2 strings to match.
4579 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
4580 : break;
4581 0 : switch (Mnemonic[15]) {
4582 : default: break;
4583 : case '3': // 1 string to match.
4584 0 : if (Mnemonic[16] != '2')
4585 : break;
4586 0 : Mnemonic = "v_cmpx_gt_f32"; // "v_cmpx_gt_f32_e32"
4587 0 : return;
4588 : case '6': // 1 string to match.
4589 0 : if (Mnemonic[16] != '4')
4590 : break;
4591 0 : Mnemonic = "v_cmpx_gt_f32"; // "v_cmpx_gt_f32_e64"
4592 0 : return;
4593 : }
4594 : break;
4595 : case '6': // 2 strings to match.
4596 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
4597 : break;
4598 0 : switch (Mnemonic[15]) {
4599 : default: break;
4600 : case '3': // 1 string to match.
4601 0 : if (Mnemonic[16] != '2')
4602 : break;
4603 0 : Mnemonic = "v_cmpx_gt_f64"; // "v_cmpx_gt_f64_e32"
4604 0 : return;
4605 : case '6': // 1 string to match.
4606 0 : if (Mnemonic[16] != '4')
4607 : break;
4608 0 : Mnemonic = "v_cmpx_gt_f64"; // "v_cmpx_gt_f64_e64"
4609 0 : return;
4610 : }
4611 : break;
4612 : }
4613 : break;
4614 : case 'i': // 4 strings to match.
4615 0 : switch (Mnemonic[11]) {
4616 : default: break;
4617 : case '3': // 2 strings to match.
4618 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
4619 : break;
4620 0 : switch (Mnemonic[15]) {
4621 : default: break;
4622 : case '3': // 1 string to match.
4623 0 : if (Mnemonic[16] != '2')
4624 : break;
4625 0 : Mnemonic = "v_cmpx_gt_i32"; // "v_cmpx_gt_i32_e32"
4626 0 : return;
4627 : case '6': // 1 string to match.
4628 0 : if (Mnemonic[16] != '4')
4629 : break;
4630 0 : Mnemonic = "v_cmpx_gt_i32"; // "v_cmpx_gt_i32_e64"
4631 0 : return;
4632 : }
4633 : break;
4634 : case '6': // 2 strings to match.
4635 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
4636 : break;
4637 0 : switch (Mnemonic[15]) {
4638 : default: break;
4639 : case '3': // 1 string to match.
4640 0 : if (Mnemonic[16] != '2')
4641 : break;
4642 0 : Mnemonic = "v_cmpx_gt_i64"; // "v_cmpx_gt_i64_e32"
4643 0 : return;
4644 : case '6': // 1 string to match.
4645 0 : if (Mnemonic[16] != '4')
4646 : break;
4647 0 : Mnemonic = "v_cmpx_gt_i64"; // "v_cmpx_gt_i64_e64"
4648 0 : return;
4649 : }
4650 : break;
4651 : }
4652 : break;
4653 : case 'u': // 4 strings to match.
4654 0 : switch (Mnemonic[11]) {
4655 : default: break;
4656 : case '3': // 2 strings to match.
4657 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
4658 : break;
4659 0 : switch (Mnemonic[15]) {
4660 : default: break;
4661 : case '3': // 1 string to match.
4662 0 : if (Mnemonic[16] != '2')
4663 : break;
4664 0 : Mnemonic = "v_cmpx_gt_u32"; // "v_cmpx_gt_u32_e32"
4665 0 : return;
4666 : case '6': // 1 string to match.
4667 0 : if (Mnemonic[16] != '4')
4668 : break;
4669 0 : Mnemonic = "v_cmpx_gt_u32"; // "v_cmpx_gt_u32_e64"
4670 0 : return;
4671 : }
4672 : break;
4673 : case '6': // 2 strings to match.
4674 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
4675 : break;
4676 0 : switch (Mnemonic[15]) {
4677 : default: break;
4678 : case '3': // 1 string to match.
4679 0 : if (Mnemonic[16] != '2')
4680 : break;
4681 0 : Mnemonic = "v_cmpx_gt_u64"; // "v_cmpx_gt_u64_e32"
4682 0 : return;
4683 : case '6': // 1 string to match.
4684 0 : if (Mnemonic[16] != '4')
4685 : break;
4686 0 : Mnemonic = "v_cmpx_gt_u64"; // "v_cmpx_gt_u64_e64"
4687 0 : return;
4688 : }
4689 : break;
4690 : }
4691 : break;
4692 : }
4693 : break;
4694 : }
4695 : break;
4696 : case 'l': // 28 strings to match.
4697 0 : switch (Mnemonic[8]) {
4698 : default: break;
4699 : case 'e': // 12 strings to match.
4700 0 : if (Mnemonic[9] != '_')
4701 : break;
4702 0 : switch (Mnemonic[10]) {
4703 : default: break;
4704 : case 'f': // 4 strings to match.
4705 0 : switch (Mnemonic[11]) {
4706 : default: break;
4707 : case '3': // 2 strings to match.
4708 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
4709 : break;
4710 0 : switch (Mnemonic[15]) {
4711 : default: break;
4712 : case '3': // 1 string to match.
4713 0 : if (Mnemonic[16] != '2')
4714 : break;
4715 0 : Mnemonic = "v_cmpx_le_f32"; // "v_cmpx_le_f32_e32"
4716 0 : return;
4717 : case '6': // 1 string to match.
4718 0 : if (Mnemonic[16] != '4')
4719 : break;
4720 0 : Mnemonic = "v_cmpx_le_f32"; // "v_cmpx_le_f32_e64"
4721 0 : return;
4722 : }
4723 : break;
4724 : case '6': // 2 strings to match.
4725 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
4726 : break;
4727 0 : switch (Mnemonic[15]) {
4728 : default: break;
4729 : case '3': // 1 string to match.
4730 0 : if (Mnemonic[16] != '2')
4731 : break;
4732 0 : Mnemonic = "v_cmpx_le_f64"; // "v_cmpx_le_f64_e32"
4733 0 : return;
4734 : case '6': // 1 string to match.
4735 0 : if (Mnemonic[16] != '4')
4736 : break;
4737 0 : Mnemonic = "v_cmpx_le_f64"; // "v_cmpx_le_f64_e64"
4738 0 : return;
4739 : }
4740 : break;
4741 : }
4742 : break;
4743 : case 'i': // 4 strings to match.
4744 0 : switch (Mnemonic[11]) {
4745 : default: break;
4746 : case '3': // 2 strings to match.
4747 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
4748 : break;
4749 0 : switch (Mnemonic[15]) {
4750 : default: break;
4751 : case '3': // 1 string to match.
4752 0 : if (Mnemonic[16] != '2')
4753 : break;
4754 0 : Mnemonic = "v_cmpx_le_i32"; // "v_cmpx_le_i32_e32"
4755 0 : return;
4756 : case '6': // 1 string to match.
4757 0 : if (Mnemonic[16] != '4')
4758 : break;
4759 0 : Mnemonic = "v_cmpx_le_i32"; // "v_cmpx_le_i32_e64"
4760 0 : return;
4761 : }
4762 : break;
4763 : case '6': // 2 strings to match.
4764 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
4765 : break;
4766 0 : switch (Mnemonic[15]) {
4767 : default: break;
4768 : case '3': // 1 string to match.
4769 0 : if (Mnemonic[16] != '2')
4770 : break;
4771 0 : Mnemonic = "v_cmpx_le_i64"; // "v_cmpx_le_i64_e32"
4772 0 : return;
4773 : case '6': // 1 string to match.
4774 0 : if (Mnemonic[16] != '4')
4775 : break;
4776 0 : Mnemonic = "v_cmpx_le_i64"; // "v_cmpx_le_i64_e64"
4777 0 : return;
4778 : }
4779 : break;
4780 : }
4781 : break;
4782 : case 'u': // 4 strings to match.
4783 0 : switch (Mnemonic[11]) {
4784 : default: break;
4785 : case '3': // 2 strings to match.
4786 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
4787 : break;
4788 0 : switch (Mnemonic[15]) {
4789 : default: break;
4790 : case '3': // 1 string to match.
4791 0 : if (Mnemonic[16] != '2')
4792 : break;
4793 0 : Mnemonic = "v_cmpx_le_u32"; // "v_cmpx_le_u32_e32"
4794 0 : return;
4795 : case '6': // 1 string to match.
4796 0 : if (Mnemonic[16] != '4')
4797 : break;
4798 0 : Mnemonic = "v_cmpx_le_u32"; // "v_cmpx_le_u32_e64"
4799 0 : return;
4800 : }
4801 : break;
4802 : case '6': // 2 strings to match.
4803 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
4804 : break;
4805 0 : switch (Mnemonic[15]) {
4806 : default: break;
4807 : case '3': // 1 string to match.
4808 0 : if (Mnemonic[16] != '2')
4809 : break;
4810 0 : Mnemonic = "v_cmpx_le_u64"; // "v_cmpx_le_u64_e32"
4811 0 : return;
4812 : case '6': // 1 string to match.
4813 0 : if (Mnemonic[16] != '4')
4814 : break;
4815 0 : Mnemonic = "v_cmpx_le_u64"; // "v_cmpx_le_u64_e64"
4816 0 : return;
4817 : }
4818 : break;
4819 : }
4820 : break;
4821 : }
4822 : break;
4823 : case 'g': // 4 strings to match.
4824 0 : if (memcmp(Mnemonic.data()+9, "_f", 2))
4825 : break;
4826 0 : switch (Mnemonic[11]) {
4827 : default: break;
4828 : case '3': // 2 strings to match.
4829 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
4830 : break;
4831 0 : switch (Mnemonic[15]) {
4832 : default: break;
4833 : case '3': // 1 string to match.
4834 0 : if (Mnemonic[16] != '2')
4835 : break;
4836 0 : Mnemonic = "v_cmpx_lg_f32"; // "v_cmpx_lg_f32_e32"
4837 0 : return;
4838 : case '6': // 1 string to match.
4839 0 : if (Mnemonic[16] != '4')
4840 : break;
4841 0 : Mnemonic = "v_cmpx_lg_f32"; // "v_cmpx_lg_f32_e64"
4842 0 : return;
4843 : }
4844 : break;
4845 : case '6': // 2 strings to match.
4846 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
4847 : break;
4848 0 : switch (Mnemonic[15]) {
4849 : default: break;
4850 : case '3': // 1 string to match.
4851 0 : if (Mnemonic[16] != '2')
4852 : break;
4853 0 : Mnemonic = "v_cmpx_lg_f64"; // "v_cmpx_lg_f64_e32"
4854 0 : return;
4855 : case '6': // 1 string to match.
4856 0 : if (Mnemonic[16] != '4')
4857 : break;
4858 0 : Mnemonic = "v_cmpx_lg_f64"; // "v_cmpx_lg_f64_e64"
4859 0 : return;
4860 : }
4861 : break;
4862 : }
4863 : break;
4864 : case 't': // 12 strings to match.
4865 0 : if (Mnemonic[9] != '_')
4866 : break;
4867 0 : switch (Mnemonic[10]) {
4868 : default: break;
4869 : case 'f': // 4 strings to match.
4870 0 : switch (Mnemonic[11]) {
4871 : default: break;
4872 : case '3': // 2 strings to match.
4873 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
4874 : break;
4875 0 : switch (Mnemonic[15]) {
4876 : default: break;
4877 : case '3': // 1 string to match.
4878 0 : if (Mnemonic[16] != '2')
4879 : break;
4880 0 : Mnemonic = "v_cmpx_lt_f32"; // "v_cmpx_lt_f32_e32"
4881 0 : return;
4882 : case '6': // 1 string to match.
4883 0 : if (Mnemonic[16] != '4')
4884 : break;
4885 0 : Mnemonic = "v_cmpx_lt_f32"; // "v_cmpx_lt_f32_e64"
4886 0 : return;
4887 : }
4888 : break;
4889 : case '6': // 2 strings to match.
4890 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
4891 : break;
4892 0 : switch (Mnemonic[15]) {
4893 : default: break;
4894 : case '3': // 1 string to match.
4895 0 : if (Mnemonic[16] != '2')
4896 : break;
4897 0 : Mnemonic = "v_cmpx_lt_f64"; // "v_cmpx_lt_f64_e32"
4898 0 : return;
4899 : case '6': // 1 string to match.
4900 0 : if (Mnemonic[16] != '4')
4901 : break;
4902 0 : Mnemonic = "v_cmpx_lt_f64"; // "v_cmpx_lt_f64_e64"
4903 0 : return;
4904 : }
4905 : break;
4906 : }
4907 : break;
4908 : case 'i': // 4 strings to match.
4909 0 : switch (Mnemonic[11]) {
4910 : default: break;
4911 : case '3': // 2 strings to match.
4912 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
4913 : break;
4914 0 : switch (Mnemonic[15]) {
4915 : default: break;
4916 : case '3': // 1 string to match.
4917 0 : if (Mnemonic[16] != '2')
4918 : break;
4919 0 : Mnemonic = "v_cmpx_lt_i32"; // "v_cmpx_lt_i32_e32"
4920 0 : return;
4921 : case '6': // 1 string to match.
4922 0 : if (Mnemonic[16] != '4')
4923 : break;
4924 0 : Mnemonic = "v_cmpx_lt_i32"; // "v_cmpx_lt_i32_e64"
4925 0 : return;
4926 : }
4927 : break;
4928 : case '6': // 2 strings to match.
4929 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
4930 : break;
4931 0 : switch (Mnemonic[15]) {
4932 : default: break;
4933 : case '3': // 1 string to match.
4934 0 : if (Mnemonic[16] != '2')
4935 : break;
4936 0 : Mnemonic = "v_cmpx_lt_i64"; // "v_cmpx_lt_i64_e32"
4937 0 : return;
4938 : case '6': // 1 string to match.
4939 0 : if (Mnemonic[16] != '4')
4940 : break;
4941 0 : Mnemonic = "v_cmpx_lt_i64"; // "v_cmpx_lt_i64_e64"
4942 0 : return;
4943 : }
4944 : break;
4945 : }
4946 : break;
4947 : case 'u': // 4 strings to match.
4948 0 : switch (Mnemonic[11]) {
4949 : default: break;
4950 : case '3': // 2 strings to match.
4951 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
4952 : break;
4953 0 : switch (Mnemonic[15]) {
4954 : default: break;
4955 : case '3': // 1 string to match.
4956 0 : if (Mnemonic[16] != '2')
4957 : break;
4958 0 : Mnemonic = "v_cmpx_lt_u32"; // "v_cmpx_lt_u32_e32"
4959 0 : return;
4960 : case '6': // 1 string to match.
4961 0 : if (Mnemonic[16] != '4')
4962 : break;
4963 0 : Mnemonic = "v_cmpx_lt_u32"; // "v_cmpx_lt_u32_e64"
4964 0 : return;
4965 : }
4966 : break;
4967 : case '6': // 2 strings to match.
4968 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
4969 : break;
4970 0 : switch (Mnemonic[15]) {
4971 : default: break;
4972 : case '3': // 1 string to match.
4973 0 : if (Mnemonic[16] != '2')
4974 : break;
4975 0 : Mnemonic = "v_cmpx_lt_u64"; // "v_cmpx_lt_u64_e32"
4976 0 : return;
4977 : case '6': // 1 string to match.
4978 0 : if (Mnemonic[16] != '4')
4979 : break;
4980 0 : Mnemonic = "v_cmpx_lt_u64"; // "v_cmpx_lt_u64_e64"
4981 0 : return;
4982 : }
4983 : break;
4984 : }
4985 : break;
4986 : }
4987 : break;
4988 : }
4989 : break;
4990 : case 'n': // 8 strings to match.
4991 0 : if (memcmp(Mnemonic.data()+8, "e_", 2))
4992 : break;
4993 0 : switch (Mnemonic[10]) {
4994 : default: break;
4995 : case 'i': // 4 strings to match.
4996 0 : switch (Mnemonic[11]) {
4997 : default: break;
4998 : case '3': // 2 strings to match.
4999 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
5000 : break;
5001 0 : switch (Mnemonic[15]) {
5002 : default: break;
5003 : case '3': // 1 string to match.
5004 0 : if (Mnemonic[16] != '2')
5005 : break;
5006 0 : Mnemonic = "v_cmpx_ne_i32"; // "v_cmpx_ne_i32_e32"
5007 0 : return;
5008 : case '6': // 1 string to match.
5009 0 : if (Mnemonic[16] != '4')
5010 : break;
5011 0 : Mnemonic = "v_cmpx_ne_i32"; // "v_cmpx_ne_i32_e64"
5012 0 : return;
5013 : }
5014 : break;
5015 : case '6': // 2 strings to match.
5016 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
5017 : break;
5018 0 : switch (Mnemonic[15]) {
5019 : default: break;
5020 : case '3': // 1 string to match.
5021 0 : if (Mnemonic[16] != '2')
5022 : break;
5023 0 : Mnemonic = "v_cmpx_ne_i64"; // "v_cmpx_ne_i64_e32"
5024 0 : return;
5025 : case '6': // 1 string to match.
5026 0 : if (Mnemonic[16] != '4')
5027 : break;
5028 0 : Mnemonic = "v_cmpx_ne_i64"; // "v_cmpx_ne_i64_e64"
5029 0 : return;
5030 : }
5031 : break;
5032 : }
5033 : break;
5034 : case 'u': // 4 strings to match.
5035 0 : switch (Mnemonic[11]) {
5036 : default: break;
5037 : case '3': // 2 strings to match.
5038 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
5039 : break;
5040 0 : switch (Mnemonic[15]) {
5041 : default: break;
5042 : case '3': // 1 string to match.
5043 0 : if (Mnemonic[16] != '2')
5044 : break;
5045 0 : Mnemonic = "v_cmpx_ne_u32"; // "v_cmpx_ne_u32_e32"
5046 0 : return;
5047 : case '6': // 1 string to match.
5048 0 : if (Mnemonic[16] != '4')
5049 : break;
5050 0 : Mnemonic = "v_cmpx_ne_u32"; // "v_cmpx_ne_u32_e64"
5051 0 : return;
5052 : }
5053 : break;
5054 : case '6': // 2 strings to match.
5055 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
5056 : break;
5057 0 : switch (Mnemonic[15]) {
5058 : default: break;
5059 : case '3': // 1 string to match.
5060 0 : if (Mnemonic[16] != '2')
5061 : break;
5062 0 : Mnemonic = "v_cmpx_ne_u64"; // "v_cmpx_ne_u64_e32"
5063 0 : return;
5064 : case '6': // 1 string to match.
5065 0 : if (Mnemonic[16] != '4')
5066 : break;
5067 0 : Mnemonic = "v_cmpx_ne_u64"; // "v_cmpx_ne_u64_e64"
5068 0 : return;
5069 : }
5070 : break;
5071 : }
5072 : break;
5073 : }
5074 : break;
5075 : }
5076 : break;
5077 : }
5078 : break;
5079 : case 'n': // 2 strings to match.
5080 0 : if (memcmp(Mnemonic.data()+4, "dmask_b32_e", 11))
5081 : break;
5082 0 : switch (Mnemonic[15]) {
5083 : default: break;
5084 : case '3': // 1 string to match.
5085 0 : if (Mnemonic[16] != '2')
5086 : break;
5087 0 : Mnemonic = "v_cndmask_b32"; // "v_cndmask_b32_e32"
5088 0 : return;
5089 : case '6': // 1 string to match.
5090 0 : if (Mnemonic[16] != '4')
5091 : break;
5092 0 : Mnemonic = "v_cndmask_b32"; // "v_cndmask_b32_e64"
5093 0 : return;
5094 : }
5095 : break;
5096 : case 'v': // 32 strings to match.
5097 16 : if (memcmp(Mnemonic.data()+4, "t_", 2))
5098 : break;
5099 32 : switch (Mnemonic[6]) {
5100 : default: break;
5101 : case 'f': // 20 strings to match.
5102 16 : switch (Mnemonic[7]) {
5103 : default: break;
5104 : case '1': // 6 strings to match.
5105 0 : if (memcmp(Mnemonic.data()+8, "6_", 2))
5106 : break;
5107 0 : switch (Mnemonic[10]) {
5108 : default: break;
5109 : case 'f': // 2 strings to match.
5110 0 : if (memcmp(Mnemonic.data()+11, "32_e", 4))
5111 : break;
5112 0 : switch (Mnemonic[15]) {
5113 : default: break;
5114 : case '3': // 1 string to match.
5115 0 : if (Mnemonic[16] != '2')
5116 : break;
5117 0 : Mnemonic = "v_cvt_f16_f32"; // "v_cvt_f16_f32_e32"
5118 0 : return;
5119 : case '6': // 1 string to match.
5120 0 : if (Mnemonic[16] != '4')
5121 : break;
5122 0 : Mnemonic = "v_cvt_f16_f32"; // "v_cvt_f16_f32_e64"
5123 0 : return;
5124 : }
5125 : break;
5126 : case 'i': // 2 strings to match.
5127 0 : if (memcmp(Mnemonic.data()+11, "16_e", 4))
5128 : break;
5129 0 : switch (Mnemonic[15]) {
5130 : default: break;
5131 : case '3': // 1 string to match.
5132 0 : if (Mnemonic[16] != '2')
5133 : break;
5134 0 : Mnemonic = "v_cvt_f16_i16"; // "v_cvt_f16_i16_e32"
5135 0 : return;
5136 : case '6': // 1 string to match.
5137 0 : if (Mnemonic[16] != '4')
5138 : break;
5139 0 : Mnemonic = "v_cvt_f16_i16"; // "v_cvt_f16_i16_e64"
5140 0 : return;
5141 : }
5142 : break;
5143 : case 'u': // 2 strings to match.
5144 0 : if (memcmp(Mnemonic.data()+11, "16_e", 4))
5145 : break;
5146 0 : switch (Mnemonic[15]) {
5147 : default: break;
5148 : case '3': // 1 string to match.
5149 0 : if (Mnemonic[16] != '2')
5150 : break;
5151 0 : Mnemonic = "v_cvt_f16_u16"; // "v_cvt_f16_u16_e32"
5152 0 : return;
5153 : case '6': // 1 string to match.
5154 0 : if (Mnemonic[16] != '4')
5155 : break;
5156 0 : Mnemonic = "v_cvt_f16_u16"; // "v_cvt_f16_u16_e64"
5157 0 : return;
5158 : }
5159 : break;
5160 : }
5161 : break;
5162 : case '3': // 8 strings to match.
5163 0 : if (memcmp(Mnemonic.data()+8, "2_", 2))
5164 : break;
5165 0 : switch (Mnemonic[10]) {
5166 : default: break;
5167 : case 'f': // 4 strings to match.
5168 0 : switch (Mnemonic[11]) {
5169 : default: break;
5170 : case '1': // 2 strings to match.
5171 0 : if (memcmp(Mnemonic.data()+12, "6_e", 3))
5172 : break;
5173 0 : switch (Mnemonic[15]) {
5174 : default: break;
5175 : case '3': // 1 string to match.
5176 0 : if (Mnemonic[16] != '2')
5177 : break;
5178 0 : Mnemonic = "v_cvt_f32_f16"; // "v_cvt_f32_f16_e32"
5179 0 : return;
5180 : case '6': // 1 string to match.
5181 0 : if (Mnemonic[16] != '4')
5182 : break;
5183 0 : Mnemonic = "v_cvt_f32_f16"; // "v_cvt_f32_f16_e64"
5184 0 : return;
5185 : }
5186 : break;
5187 : case '6': // 2 strings to match.
5188 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
5189 : break;
5190 0 : switch (Mnemonic[15]) {
5191 : default: break;
5192 : case '3': // 1 string to match.
5193 0 : if (Mnemonic[16] != '2')
5194 : break;
5195 0 : Mnemonic = "v_cvt_f32_f64"; // "v_cvt_f32_f64_e32"
5196 0 : return;
5197 : case '6': // 1 string to match.
5198 0 : if (Mnemonic[16] != '4')
5199 : break;
5200 0 : Mnemonic = "v_cvt_f32_f64"; // "v_cvt_f32_f64_e64"
5201 0 : return;
5202 : }
5203 : break;
5204 : }
5205 : break;
5206 : case 'i': // 2 strings to match.
5207 0 : if (memcmp(Mnemonic.data()+11, "32_e", 4))
5208 : break;
5209 0 : switch (Mnemonic[15]) {
5210 : default: break;
5211 : case '3': // 1 string to match.
5212 0 : if (Mnemonic[16] != '2')
5213 : break;
5214 0 : Mnemonic = "v_cvt_f32_i32"; // "v_cvt_f32_i32_e32"
5215 0 : return;
5216 : case '6': // 1 string to match.
5217 0 : if (Mnemonic[16] != '4')
5218 : break;
5219 0 : Mnemonic = "v_cvt_f32_i32"; // "v_cvt_f32_i32_e64"
5220 0 : return;
5221 : }
5222 : break;
5223 : case 'u': // 2 strings to match.
5224 0 : if (memcmp(Mnemonic.data()+11, "32_e", 4))
5225 : break;
5226 0 : switch (Mnemonic[15]) {
5227 : default: break;
5228 : case '3': // 1 string to match.
5229 0 : if (Mnemonic[16] != '2')
5230 : break;
5231 0 : Mnemonic = "v_cvt_f32_u32"; // "v_cvt_f32_u32_e32"
5232 0 : return;
5233 : case '6': // 1 string to match.
5234 0 : if (Mnemonic[16] != '4')
5235 : break;
5236 0 : Mnemonic = "v_cvt_f32_u32"; // "v_cvt_f32_u32_e64"
5237 0 : return;
5238 : }
5239 : break;
5240 : }
5241 : break;
5242 : case '6': // 6 strings to match.
5243 0 : if (memcmp(Mnemonic.data()+8, "4_", 2))
5244 : break;
5245 0 : switch (Mnemonic[10]) {
5246 : default: break;
5247 : case 'f': // 2 strings to match.
5248 0 : if (memcmp(Mnemonic.data()+11, "32_e", 4))
5249 : break;
5250 0 : switch (Mnemonic[15]) {
5251 : default: break;
5252 : case '3': // 1 string to match.
5253 0 : if (Mnemonic[16] != '2')
5254 : break;
5255 0 : Mnemonic = "v_cvt_f64_f32"; // "v_cvt_f64_f32_e32"
5256 0 : return;
5257 : case '6': // 1 string to match.
5258 0 : if (Mnemonic[16] != '4')
5259 : break;
5260 0 : Mnemonic = "v_cvt_f64_f32"; // "v_cvt_f64_f32_e64"
5261 0 : return;
5262 : }
5263 : break;
5264 : case 'i': // 2 strings to match.
5265 0 : if (memcmp(Mnemonic.data()+11, "32_e", 4))
5266 : break;
5267 0 : switch (Mnemonic[15]) {
5268 : default: break;
5269 : case '3': // 1 string to match.
5270 0 : if (Mnemonic[16] != '2')
5271 : break;
5272 0 : Mnemonic = "v_cvt_f64_i32"; // "v_cvt_f64_i32_e32"
5273 0 : return;
5274 : case '6': // 1 string to match.
5275 0 : if (Mnemonic[16] != '4')
5276 : break;
5277 0 : Mnemonic = "v_cvt_f64_i32"; // "v_cvt_f64_i32_e64"
5278 0 : return;
5279 : }
5280 : break;
5281 : case 'u': // 2 strings to match.
5282 0 : if (memcmp(Mnemonic.data()+11, "32_e", 4))
5283 : break;
5284 0 : switch (Mnemonic[15]) {
5285 : default: break;
5286 : case '3': // 1 string to match.
5287 0 : if (Mnemonic[16] != '2')
5288 : break;
5289 0 : Mnemonic = "v_cvt_f64_u32"; // "v_cvt_f64_u32_e32"
5290 0 : return;
5291 : case '6': // 1 string to match.
5292 0 : if (Mnemonic[16] != '4')
5293 : break;
5294 0 : Mnemonic = "v_cvt_f64_u32"; // "v_cvt_f64_u32_e64"
5295 0 : return;
5296 : }
5297 : break;
5298 : }
5299 : break;
5300 : }
5301 : break;
5302 : case 'i': // 6 strings to match.
5303 0 : switch (Mnemonic[7]) {
5304 : default: break;
5305 : case '1': // 2 strings to match.
5306 0 : if (memcmp(Mnemonic.data()+8, "6_f16_e", 7))
5307 : break;
5308 0 : switch (Mnemonic[15]) {
5309 : default: break;
5310 : case '3': // 1 string to match.
5311 0 : if (Mnemonic[16] != '2')
5312 : break;
5313 0 : Mnemonic = "v_cvt_i16_f16"; // "v_cvt_i16_f16_e32"
5314 0 : return;
5315 : case '6': // 1 string to match.
5316 0 : if (Mnemonic[16] != '4')
5317 : break;
5318 0 : Mnemonic = "v_cvt_i16_f16"; // "v_cvt_i16_f16_e64"
5319 0 : return;
5320 : }
5321 : break;
5322 : case '3': // 4 strings to match.
5323 0 : if (memcmp(Mnemonic.data()+8, "2_f", 3))
5324 : break;
5325 0 : switch (Mnemonic[11]) {
5326 : default: break;
5327 : case '3': // 2 strings to match.
5328 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
5329 : break;
5330 0 : switch (Mnemonic[15]) {
5331 : default: break;
5332 : case '3': // 1 string to match.
5333 0 : if (Mnemonic[16] != '2')
5334 : break;
5335 0 : Mnemonic = "v_cvt_i32_f32"; // "v_cvt_i32_f32_e32"
5336 0 : return;
5337 : case '6': // 1 string to match.
5338 0 : if (Mnemonic[16] != '4')
5339 : break;
5340 0 : Mnemonic = "v_cvt_i32_f32"; // "v_cvt_i32_f32_e64"
5341 0 : return;
5342 : }
5343 : break;
5344 : case '6': // 2 strings to match.
5345 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
5346 : break;
5347 0 : switch (Mnemonic[15]) {
5348 : default: break;
5349 : case '3': // 1 string to match.
5350 0 : if (Mnemonic[16] != '2')
5351 : break;
5352 0 : Mnemonic = "v_cvt_i32_f64"; // "v_cvt_i32_f64_e32"
5353 0 : return;
5354 : case '6': // 1 string to match.
5355 0 : if (Mnemonic[16] != '4')
5356 : break;
5357 0 : Mnemonic = "v_cvt_i32_f64"; // "v_cvt_i32_f64_e64"
5358 0 : return;
5359 : }
5360 : break;
5361 : }
5362 : break;
5363 : }
5364 : break;
5365 : case 'u': // 6 strings to match.
5366 0 : switch (Mnemonic[7]) {
5367 : default: break;
5368 : case '1': // 2 strings to match.
5369 0 : if (memcmp(Mnemonic.data()+8, "6_f16_e", 7))
5370 : break;
5371 0 : switch (Mnemonic[15]) {
5372 : default: break;
5373 : case '3': // 1 string to match.
5374 0 : if (Mnemonic[16] != '2')
5375 : break;
5376 0 : Mnemonic = "v_cvt_u16_f16"; // "v_cvt_u16_f16_e32"
5377 0 : return;
5378 : case '6': // 1 string to match.
5379 0 : if (Mnemonic[16] != '4')
5380 : break;
5381 0 : Mnemonic = "v_cvt_u16_f16"; // "v_cvt_u16_f16_e64"
5382 0 : return;
5383 : }
5384 : break;
5385 : case '3': // 4 strings to match.
5386 0 : if (memcmp(Mnemonic.data()+8, "2_f", 3))
5387 : break;
5388 0 : switch (Mnemonic[11]) {
5389 : default: break;
5390 : case '3': // 2 strings to match.
5391 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
5392 : break;
5393 0 : switch (Mnemonic[15]) {
5394 : default: break;
5395 : case '3': // 1 string to match.
5396 0 : if (Mnemonic[16] != '2')
5397 : break;
5398 0 : Mnemonic = "v_cvt_u32_f32"; // "v_cvt_u32_f32_e32"
5399 0 : return;
5400 : case '6': // 1 string to match.
5401 0 : if (Mnemonic[16] != '4')
5402 : break;
5403 0 : Mnemonic = "v_cvt_u32_f32"; // "v_cvt_u32_f32_e64"
5404 0 : return;
5405 : }
5406 : break;
5407 : case '6': // 2 strings to match.
5408 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
5409 : break;
5410 0 : switch (Mnemonic[15]) {
5411 : default: break;
5412 : case '3': // 1 string to match.
5413 0 : if (Mnemonic[16] != '2')
5414 : break;
5415 0 : Mnemonic = "v_cvt_u32_f64"; // "v_cvt_u32_f64_e32"
5416 0 : return;
5417 : case '6': // 1 string to match.
5418 0 : if (Mnemonic[16] != '4')
5419 : break;
5420 0 : Mnemonic = "v_cvt_u32_f64"; // "v_cvt_u32_f64_e64"
5421 0 : return;
5422 : }
5423 : break;
5424 : }
5425 : break;
5426 : }
5427 : break;
5428 : }
5429 : break;
5430 : }
5431 : break;
5432 : case 'l': // 10 strings to match.
5433 0 : if (memcmp(Mnemonic.data()+3, "sh", 2))
5434 : break;
5435 0 : switch (Mnemonic[5]) {
5436 : default: break;
5437 : case 'l': // 5 strings to match.
5438 0 : if (memcmp(Mnemonic.data()+6, "rev_b", 5))
5439 : break;
5440 0 : switch (Mnemonic[11]) {
5441 : default: break;
5442 : case '1': // 2 strings to match.
5443 0 : if (memcmp(Mnemonic.data()+12, "6_e", 3))
5444 : break;
5445 0 : switch (Mnemonic[15]) {
5446 : default: break;
5447 : case '3': // 1 string to match.
5448 0 : if (Mnemonic[16] != '2')
5449 : break;
5450 0 : Mnemonic = "v_lshlrev_b16"; // "v_lshlrev_b16_e32"
5451 0 : return;
5452 : case '6': // 1 string to match.
5453 0 : if (Mnemonic[16] != '4')
5454 : break;
5455 0 : Mnemonic = "v_lshlrev_b16"; // "v_lshlrev_b16_e64"
5456 0 : return;
5457 : }
5458 : break;
5459 : case '3': // 2 strings to match.
5460 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
5461 : break;
5462 0 : switch (Mnemonic[15]) {
5463 : default: break;
5464 : case '3': // 1 string to match.
5465 0 : if (Mnemonic[16] != '2')
5466 : break;
5467 0 : Mnemonic = "v_lshlrev_b32"; // "v_lshlrev_b32_e32"
5468 0 : return;
5469 : case '6': // 1 string to match.
5470 0 : if (Mnemonic[16] != '4')
5471 : break;
5472 0 : Mnemonic = "v_lshlrev_b32"; // "v_lshlrev_b32_e64"
5473 0 : return;
5474 : }
5475 : break;
5476 : case '6': // 1 string to match.
5477 0 : if (memcmp(Mnemonic.data()+12, "4_e64", 5))
5478 : break;
5479 0 : Mnemonic = "v_lshlrev_b64"; // "v_lshlrev_b64_e64"
5480 0 : return;
5481 : }
5482 : break;
5483 : case 'r': // 5 strings to match.
5484 0 : if (memcmp(Mnemonic.data()+6, "rev_b", 5))
5485 : break;
5486 0 : switch (Mnemonic[11]) {
5487 : default: break;
5488 : case '1': // 2 strings to match.
5489 0 : if (memcmp(Mnemonic.data()+12, "6_e", 3))
5490 : break;
5491 0 : switch (Mnemonic[15]) {
5492 : default: break;
5493 : case '3': // 1 string to match.
5494 0 : if (Mnemonic[16] != '2')
5495 : break;
5496 0 : Mnemonic = "v_lshrrev_b16"; // "v_lshrrev_b16_e32"
5497 0 : return;
5498 : case '6': // 1 string to match.
5499 0 : if (Mnemonic[16] != '4')
5500 : break;
5501 0 : Mnemonic = "v_lshrrev_b16"; // "v_lshrrev_b16_e64"
5502 0 : return;
5503 : }
5504 : break;
5505 : case '3': // 2 strings to match.
5506 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
5507 : break;
5508 0 : switch (Mnemonic[15]) {
5509 : default: break;
5510 : case '3': // 1 string to match.
5511 0 : if (Mnemonic[16] != '2')
5512 : break;
5513 0 : Mnemonic = "v_lshrrev_b32"; // "v_lshrrev_b32_e32"
5514 0 : return;
5515 : case '6': // 1 string to match.
5516 0 : if (Mnemonic[16] != '4')
5517 : break;
5518 0 : Mnemonic = "v_lshrrev_b32"; // "v_lshrrev_b32_e64"
5519 0 : return;
5520 : }
5521 : break;
5522 : case '6': // 1 string to match.
5523 0 : if (memcmp(Mnemonic.data()+12, "4_e64", 5))
5524 : break;
5525 0 : Mnemonic = "v_lshrrev_b64"; // "v_lshrrev_b64_e64"
5526 0 : return;
5527 : }
5528 : break;
5529 : }
5530 : break;
5531 : case 'm': // 14 strings to match.
5532 48 : switch (Mnemonic[3]) {
5533 : default: break;
5534 : case 'a': // 4 strings to match.
5535 0 : if (memcmp(Mnemonic.data()+4, "d_", 2))
5536 : break;
5537 0 : switch (Mnemonic[6]) {
5538 : default: break;
5539 : case 'i': // 2 strings to match.
5540 0 : switch (Mnemonic[7]) {
5541 : default: break;
5542 : case '3': // 1 string to match.
5543 0 : if (memcmp(Mnemonic.data()+8, "2_i24_e64", 9))
5544 : break;
5545 0 : Mnemonic = "v_mad_i32_i24"; // "v_mad_i32_i24_e64"
5546 0 : return;
5547 : case '6': // 1 string to match.
5548 0 : if (memcmp(Mnemonic.data()+8, "4_i32_e64", 9))
5549 : break;
5550 0 : if ((Features & Feature_isGCN) == Feature_isGCN) // "v_mad_i64_i32_e64"
5551 0 : Mnemonic = "v_mad_i64_i32";
5552 : return;
5553 : }
5554 : break;
5555 : case 'u': // 2 strings to match.
5556 0 : switch (Mnemonic[7]) {
5557 : default: break;
5558 : case '3': // 1 string to match.
5559 0 : if (memcmp(Mnemonic.data()+8, "2_u24_e64", 9))
5560 : break;
5561 0 : Mnemonic = "v_mad_u32_u24"; // "v_mad_u32_u24_e64"
5562 0 : return;
5563 : case '6': // 1 string to match.
5564 0 : if (memcmp(Mnemonic.data()+8, "4_u32_e64", 9))
5565 : break;
5566 0 : if ((Features & Feature_isGCN) == Feature_isGCN) // "v_mad_u64_u32_e64"
5567 0 : Mnemonic = "v_mad_u64_u32";
5568 : return;
5569 : }
5570 : break;
5571 : }
5572 : break;
5573 : case 'o': // 6 strings to match.
5574 0 : if (Mnemonic[4] != 'v')
5575 : break;
5576 0 : switch (Mnemonic[5]) {
5577 : default: break;
5578 : case '_': // 2 strings to match.
5579 0 : if (memcmp(Mnemonic.data()+6, "fed_b32_e", 9))
5580 : break;
5581 0 : switch (Mnemonic[15]) {
5582 : default: break;
5583 : case '3': // 1 string to match.
5584 0 : if (Mnemonic[16] != '2')
5585 : break;
5586 0 : Mnemonic = "v_mov_fed_b32"; // "v_mov_fed_b32_e32"
5587 0 : return;
5588 : case '6': // 1 string to match.
5589 0 : if (Mnemonic[16] != '4')
5590 : break;
5591 0 : Mnemonic = "v_mov_fed_b32"; // "v_mov_fed_b32_e64"
5592 0 : return;
5593 : }
5594 : break;
5595 : case 'r': // 4 strings to match.
5596 0 : if (memcmp(Mnemonic.data()+6, "el", 2))
5597 : break;
5598 0 : switch (Mnemonic[8]) {
5599 : default: break;
5600 : case 'd': // 2 strings to match.
5601 0 : if (memcmp(Mnemonic.data()+9, "_b32_e", 6))
5602 : break;
5603 0 : switch (Mnemonic[15]) {
5604 : default: break;
5605 : case '3': // 1 string to match.
5606 0 : if (Mnemonic[16] != '2')
5607 : break;
5608 0 : Mnemonic = "v_movreld_b32"; // "v_movreld_b32_e32"
5609 0 : return;
5610 : case '6': // 1 string to match.
5611 0 : if (Mnemonic[16] != '4')
5612 : break;
5613 0 : Mnemonic = "v_movreld_b32"; // "v_movreld_b32_e64"
5614 0 : return;
5615 : }
5616 : break;
5617 : case 's': // 2 strings to match.
5618 0 : if (memcmp(Mnemonic.data()+9, "_b32_e", 6))
5619 : break;
5620 0 : switch (Mnemonic[15]) {
5621 : default: break;
5622 : case '3': // 1 string to match.
5623 0 : if (Mnemonic[16] != '2')
5624 : break;
5625 0 : Mnemonic = "v_movrels_b32"; // "v_movrels_b32_e32"
5626 0 : return;
5627 : case '6': // 1 string to match.
5628 0 : if (Mnemonic[16] != '4')
5629 : break;
5630 0 : Mnemonic = "v_movrels_b32"; // "v_movrels_b32_e64"
5631 0 : return;
5632 : }
5633 : break;
5634 : }
5635 : break;
5636 : }
5637 : break;
5638 : case 'u': // 4 strings to match.
5639 24 : if (memcmp(Mnemonic.data()+4, "l_", 2))
5640 : break;
5641 48 : switch (Mnemonic[6]) {
5642 : default: break;
5643 : case 'i': // 2 strings to match.
5644 24 : if (memcmp(Mnemonic.data()+7, "32_i24_e", 8))
5645 : break;
5646 48 : switch (Mnemonic[15]) {
5647 : default: break;
5648 : case '3': // 1 string to match.
5649 24 : if (Mnemonic[16] != '2')
5650 : break;
5651 12 : Mnemonic = "v_mul_i32_i24"; // "v_mul_i32_i24_e32"
5652 12 : return;
5653 : case '6': // 1 string to match.
5654 24 : if (Mnemonic[16] != '4')
5655 : break;
5656 12 : Mnemonic = "v_mul_i32_i24"; // "v_mul_i32_i24_e64"
5657 12 : return;
5658 : }
5659 : break;
5660 : case 'u': // 2 strings to match.
5661 0 : if (memcmp(Mnemonic.data()+7, "32_u24_e", 8))
5662 : break;
5663 0 : switch (Mnemonic[15]) {
5664 : default: break;
5665 : case '3': // 1 string to match.
5666 0 : if (Mnemonic[16] != '2')
5667 : break;
5668 0 : Mnemonic = "v_mul_u32_u24"; // "v_mul_u32_u24_e32"
5669 0 : return;
5670 : case '6': // 1 string to match.
5671 0 : if (Mnemonic[16] != '4')
5672 : break;
5673 0 : Mnemonic = "v_mul_u32_u24"; // "v_mul_u32_u24_e64"
5674 0 : return;
5675 : }
5676 : break;
5677 : }
5678 : break;
5679 : }
5680 : break;
5681 : case 's': // 2 strings to match.
5682 0 : if (memcmp(Mnemonic.data()+3, "ubbrev_u32_e", 12))
5683 : break;
5684 0 : switch (Mnemonic[15]) {
5685 : default: break;
5686 : case '3': // 1 string to match.
5687 0 : if (Mnemonic[16] != '2')
5688 : break;
5689 0 : Mnemonic = "v_subbrev_u32"; // "v_subbrev_u32_e32"
5690 0 : return;
5691 : case '6': // 1 string to match.
5692 0 : if (Mnemonic[16] != '4')
5693 : break;
5694 0 : Mnemonic = "v_subbrev_u32"; // "v_subbrev_u32_e64"
5695 0 : return;
5696 : }
5697 : break;
5698 : }
5699 : break;
5700 : case 18: // 89 strings to match.
5701 116 : if (memcmp(Mnemonic.data()+0, "v_", 2))
5702 : break;
5703 32 : switch (Mnemonic[2]) {
5704 : default: break;
5705 : case 'a': // 1 string to match.
5706 0 : if (memcmp(Mnemonic.data()+3, "lignbit_b32_e64", 15))
5707 : break;
5708 0 : Mnemonic = "v_alignbit_b32"; // "v_alignbit_b32_e64"
5709 0 : return;
5710 : case 'b': // 2 strings to match.
5711 0 : if (memcmp(Mnemonic.data()+3, "cnt_u32_b32_e", 13))
5712 : break;
5713 0 : switch (Mnemonic[16]) {
5714 : default: break;
5715 : case '3': // 1 string to match.
5716 0 : if (Mnemonic[17] != '2')
5717 : break;
5718 0 : Mnemonic = "v_bcnt_u32_b32"; // "v_bcnt_u32_b32_e32"
5719 0 : return;
5720 : case '6': // 1 string to match.
5721 0 : if (Mnemonic[17] != '4')
5722 : break;
5723 0 : Mnemonic = "v_bcnt_u32_b32"; // "v_bcnt_u32_b32_e64"
5724 0 : return;
5725 : }
5726 : break;
5727 : case 'c': // 80 strings to match.
5728 0 : if (memcmp(Mnemonic.data()+3, "mp", 2))
5729 : break;
5730 0 : switch (Mnemonic[5]) {
5731 : default: break;
5732 : case 's': // 52 strings to match.
5733 0 : switch (Mnemonic[6]) {
5734 : default: break;
5735 : case '_': // 28 strings to match.
5736 0 : switch (Mnemonic[7]) {
5737 : default: break;
5738 : case 'n': // 24 strings to match.
5739 0 : switch (Mnemonic[8]) {
5740 : default: break;
5741 : case 'e': // 4 strings to match.
5742 0 : if (memcmp(Mnemonic.data()+9, "q_f", 3))
5743 : break;
5744 0 : switch (Mnemonic[12]) {
5745 : default: break;
5746 : case '3': // 2 strings to match.
5747 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
5748 : break;
5749 0 : switch (Mnemonic[16]) {
5750 : default: break;
5751 : case '3': // 1 string to match.
5752 0 : if (Mnemonic[17] != '2')
5753 : break;
5754 0 : Mnemonic = "v_cmps_neq_f32"; // "v_cmps_neq_f32_e32"
5755 0 : return;
5756 : case '6': // 1 string to match.
5757 0 : if (Mnemonic[17] != '4')
5758 : break;
5759 0 : Mnemonic = "v_cmps_neq_f32"; // "v_cmps_neq_f32_e64"
5760 0 : return;
5761 : }
5762 : break;
5763 : case '6': // 2 strings to match.
5764 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
5765 : break;
5766 0 : switch (Mnemonic[16]) {
5767 : default: break;
5768 : case '3': // 1 string to match.
5769 0 : if (Mnemonic[17] != '2')
5770 : break;
5771 0 : Mnemonic = "v_cmps_neq_f64"; // "v_cmps_neq_f64_e32"
5772 0 : return;
5773 : case '6': // 1 string to match.
5774 0 : if (Mnemonic[17] != '4')
5775 : break;
5776 0 : Mnemonic = "v_cmps_neq_f64"; // "v_cmps_neq_f64_e64"
5777 0 : return;
5778 : }
5779 : break;
5780 : }
5781 : break;
5782 : case 'g': // 8 strings to match.
5783 0 : switch (Mnemonic[9]) {
5784 : default: break;
5785 : case 'e': // 4 strings to match.
5786 0 : if (memcmp(Mnemonic.data()+10, "_f", 2))
5787 : break;
5788 0 : switch (Mnemonic[12]) {
5789 : default: break;
5790 : case '3': // 2 strings to match.
5791 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
5792 : break;
5793 0 : switch (Mnemonic[16]) {
5794 : default: break;
5795 : case '3': // 1 string to match.
5796 0 : if (Mnemonic[17] != '2')
5797 : break;
5798 0 : Mnemonic = "v_cmps_nge_f32"; // "v_cmps_nge_f32_e32"
5799 0 : return;
5800 : case '6': // 1 string to match.
5801 0 : if (Mnemonic[17] != '4')
5802 : break;
5803 0 : Mnemonic = "v_cmps_nge_f32"; // "v_cmps_nge_f32_e64"
5804 0 : return;
5805 : }
5806 : break;
5807 : case '6': // 2 strings to match.
5808 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
5809 : break;
5810 0 : switch (Mnemonic[16]) {
5811 : default: break;
5812 : case '3': // 1 string to match.
5813 0 : if (Mnemonic[17] != '2')
5814 : break;
5815 0 : Mnemonic = "v_cmps_nge_f64"; // "v_cmps_nge_f64_e32"
5816 0 : return;
5817 : case '6': // 1 string to match.
5818 0 : if (Mnemonic[17] != '4')
5819 : break;
5820 0 : Mnemonic = "v_cmps_nge_f64"; // "v_cmps_nge_f64_e64"
5821 0 : return;
5822 : }
5823 : break;
5824 : }
5825 : break;
5826 : case 't': // 4 strings to match.
5827 0 : if (memcmp(Mnemonic.data()+10, "_f", 2))
5828 : break;
5829 0 : switch (Mnemonic[12]) {
5830 : default: break;
5831 : case '3': // 2 strings to match.
5832 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
5833 : break;
5834 0 : switch (Mnemonic[16]) {
5835 : default: break;
5836 : case '3': // 1 string to match.
5837 0 : if (Mnemonic[17] != '2')
5838 : break;
5839 0 : Mnemonic = "v_cmps_ngt_f32"; // "v_cmps_ngt_f32_e32"
5840 0 : return;
5841 : case '6': // 1 string to match.
5842 0 : if (Mnemonic[17] != '4')
5843 : break;
5844 0 : Mnemonic = "v_cmps_ngt_f32"; // "v_cmps_ngt_f32_e64"
5845 0 : return;
5846 : }
5847 : break;
5848 : case '6': // 2 strings to match.
5849 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
5850 : break;
5851 0 : switch (Mnemonic[16]) {
5852 : default: break;
5853 : case '3': // 1 string to match.
5854 0 : if (Mnemonic[17] != '2')
5855 : break;
5856 0 : Mnemonic = "v_cmps_ngt_f64"; // "v_cmps_ngt_f64_e32"
5857 0 : return;
5858 : case '6': // 1 string to match.
5859 0 : if (Mnemonic[17] != '4')
5860 : break;
5861 0 : Mnemonic = "v_cmps_ngt_f64"; // "v_cmps_ngt_f64_e64"
5862 0 : return;
5863 : }
5864 : break;
5865 : }
5866 : break;
5867 : }
5868 : break;
5869 : case 'l': // 12 strings to match.
5870 0 : switch (Mnemonic[9]) {
5871 : default: break;
5872 : case 'e': // 4 strings to match.
5873 0 : if (memcmp(Mnemonic.data()+10, "_f", 2))
5874 : break;
5875 0 : switch (Mnemonic[12]) {
5876 : default: break;
5877 : case '3': // 2 strings to match.
5878 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
5879 : break;
5880 0 : switch (Mnemonic[16]) {
5881 : default: break;
5882 : case '3': // 1 string to match.
5883 0 : if (Mnemonic[17] != '2')
5884 : break;
5885 0 : Mnemonic = "v_cmps_nle_f32"; // "v_cmps_nle_f32_e32"
5886 0 : return;
5887 : case '6': // 1 string to match.
5888 0 : if (Mnemonic[17] != '4')
5889 : break;
5890 0 : Mnemonic = "v_cmps_nle_f32"; // "v_cmps_nle_f32_e64"
5891 0 : return;
5892 : }
5893 : break;
5894 : case '6': // 2 strings to match.
5895 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
5896 : break;
5897 0 : switch (Mnemonic[16]) {
5898 : default: break;
5899 : case '3': // 1 string to match.
5900 0 : if (Mnemonic[17] != '2')
5901 : break;
5902 0 : Mnemonic = "v_cmps_nle_f64"; // "v_cmps_nle_f64_e32"
5903 0 : return;
5904 : case '6': // 1 string to match.
5905 0 : if (Mnemonic[17] != '4')
5906 : break;
5907 0 : Mnemonic = "v_cmps_nle_f64"; // "v_cmps_nle_f64_e64"
5908 0 : return;
5909 : }
5910 : break;
5911 : }
5912 : break;
5913 : case 'g': // 4 strings to match.
5914 0 : if (memcmp(Mnemonic.data()+10, "_f", 2))
5915 : break;
5916 0 : switch (Mnemonic[12]) {
5917 : default: break;
5918 : case '3': // 2 strings to match.
5919 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
5920 : break;
5921 0 : switch (Mnemonic[16]) {
5922 : default: break;
5923 : case '3': // 1 string to match.
5924 0 : if (Mnemonic[17] != '2')
5925 : break;
5926 0 : Mnemonic = "v_cmps_nlg_f32"; // "v_cmps_nlg_f32_e32"
5927 0 : return;
5928 : case '6': // 1 string to match.
5929 0 : if (Mnemonic[17] != '4')
5930 : break;
5931 0 : Mnemonic = "v_cmps_nlg_f32"; // "v_cmps_nlg_f32_e64"
5932 0 : return;
5933 : }
5934 : break;
5935 : case '6': // 2 strings to match.
5936 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
5937 : break;
5938 0 : switch (Mnemonic[16]) {
5939 : default: break;
5940 : case '3': // 1 string to match.
5941 0 : if (Mnemonic[17] != '2')
5942 : break;
5943 0 : Mnemonic = "v_cmps_nlg_f64"; // "v_cmps_nlg_f64_e32"
5944 0 : return;
5945 : case '6': // 1 string to match.
5946 0 : if (Mnemonic[17] != '4')
5947 : break;
5948 0 : Mnemonic = "v_cmps_nlg_f64"; // "v_cmps_nlg_f64_e64"
5949 0 : return;
5950 : }
5951 : break;
5952 : }
5953 : break;
5954 : case 't': // 4 strings to match.
5955 0 : if (memcmp(Mnemonic.data()+10, "_f", 2))
5956 : break;
5957 0 : switch (Mnemonic[12]) {
5958 : default: break;
5959 : case '3': // 2 strings to match.
5960 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
5961 : break;
5962 0 : switch (Mnemonic[16]) {
5963 : default: break;
5964 : case '3': // 1 string to match.
5965 0 : if (Mnemonic[17] != '2')
5966 : break;
5967 0 : Mnemonic = "v_cmps_nlt_f32"; // "v_cmps_nlt_f32_e32"
5968 0 : return;
5969 : case '6': // 1 string to match.
5970 0 : if (Mnemonic[17] != '4')
5971 : break;
5972 0 : Mnemonic = "v_cmps_nlt_f32"; // "v_cmps_nlt_f32_e64"
5973 0 : return;
5974 : }
5975 : break;
5976 : case '6': // 2 strings to match.
5977 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
5978 : break;
5979 0 : switch (Mnemonic[16]) {
5980 : default: break;
5981 : case '3': // 1 string to match.
5982 0 : if (Mnemonic[17] != '2')
5983 : break;
5984 0 : Mnemonic = "v_cmps_nlt_f64"; // "v_cmps_nlt_f64_e32"
5985 0 : return;
5986 : case '6': // 1 string to match.
5987 0 : if (Mnemonic[17] != '4')
5988 : break;
5989 0 : Mnemonic = "v_cmps_nlt_f64"; // "v_cmps_nlt_f64_e64"
5990 0 : return;
5991 : }
5992 : break;
5993 : }
5994 : break;
5995 : }
5996 : break;
5997 : }
5998 : break;
5999 : case 't': // 4 strings to match.
6000 0 : if (memcmp(Mnemonic.data()+8, "ru_f", 4))
6001 : break;
6002 0 : switch (Mnemonic[12]) {
6003 : default: break;
6004 : case '3': // 2 strings to match.
6005 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
6006 : break;
6007 0 : switch (Mnemonic[16]) {
6008 : default: break;
6009 : case '3': // 1 string to match.
6010 0 : if (Mnemonic[17] != '2')
6011 : break;
6012 0 : Mnemonic = "v_cmps_tru_f32"; // "v_cmps_tru_f32_e32"
6013 0 : return;
6014 : case '6': // 1 string to match.
6015 0 : if (Mnemonic[17] != '4')
6016 : break;
6017 0 : Mnemonic = "v_cmps_tru_f32"; // "v_cmps_tru_f32_e64"
6018 0 : return;
6019 : }
6020 : break;
6021 : case '6': // 2 strings to match.
6022 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
6023 : break;
6024 0 : switch (Mnemonic[16]) {
6025 : default: break;
6026 : case '3': // 1 string to match.
6027 0 : if (Mnemonic[17] != '2')
6028 : break;
6029 0 : Mnemonic = "v_cmps_tru_f64"; // "v_cmps_tru_f64_e32"
6030 0 : return;
6031 : case '6': // 1 string to match.
6032 0 : if (Mnemonic[17] != '4')
6033 : break;
6034 0 : Mnemonic = "v_cmps_tru_f64"; // "v_cmps_tru_f64_e64"
6035 0 : return;
6036 : }
6037 : break;
6038 : }
6039 : break;
6040 : }
6041 : break;
6042 : case 'x': // 24 strings to match.
6043 0 : if (Mnemonic[7] != '_')
6044 : break;
6045 0 : switch (Mnemonic[8]) {
6046 : default: break;
6047 : case 'e': // 4 strings to match.
6048 0 : if (memcmp(Mnemonic.data()+9, "q_f", 3))
6049 : break;
6050 0 : switch (Mnemonic[12]) {
6051 : default: break;
6052 : case '3': // 2 strings to match.
6053 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
6054 : break;
6055 0 : switch (Mnemonic[16]) {
6056 : default: break;
6057 : case '3': // 1 string to match.
6058 0 : if (Mnemonic[17] != '2')
6059 : break;
6060 0 : Mnemonic = "v_cmpsx_eq_f32"; // "v_cmpsx_eq_f32_e32"
6061 0 : return;
6062 : case '6': // 1 string to match.
6063 0 : if (Mnemonic[17] != '4')
6064 : break;
6065 0 : Mnemonic = "v_cmpsx_eq_f32"; // "v_cmpsx_eq_f32_e64"
6066 0 : return;
6067 : }
6068 : break;
6069 : case '6': // 2 strings to match.
6070 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
6071 : break;
6072 0 : switch (Mnemonic[16]) {
6073 : default: break;
6074 : case '3': // 1 string to match.
6075 0 : if (Mnemonic[17] != '2')
6076 : break;
6077 0 : Mnemonic = "v_cmpsx_eq_f64"; // "v_cmpsx_eq_f64_e32"
6078 0 : return;
6079 : case '6': // 1 string to match.
6080 0 : if (Mnemonic[17] != '4')
6081 : break;
6082 0 : Mnemonic = "v_cmpsx_eq_f64"; // "v_cmpsx_eq_f64_e64"
6083 0 : return;
6084 : }
6085 : break;
6086 : }
6087 : break;
6088 : case 'g': // 8 strings to match.
6089 0 : switch (Mnemonic[9]) {
6090 : default: break;
6091 : case 'e': // 4 strings to match.
6092 0 : if (memcmp(Mnemonic.data()+10, "_f", 2))
6093 : break;
6094 0 : switch (Mnemonic[12]) {
6095 : default: break;
6096 : case '3': // 2 strings to match.
6097 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
6098 : break;
6099 0 : switch (Mnemonic[16]) {
6100 : default: break;
6101 : case '3': // 1 string to match.
6102 0 : if (Mnemonic[17] != '2')
6103 : break;
6104 0 : Mnemonic = "v_cmpsx_ge_f32"; // "v_cmpsx_ge_f32_e32"
6105 0 : return;
6106 : case '6': // 1 string to match.
6107 0 : if (Mnemonic[17] != '4')
6108 : break;
6109 0 : Mnemonic = "v_cmpsx_ge_f32"; // "v_cmpsx_ge_f32_e64"
6110 0 : return;
6111 : }
6112 : break;
6113 : case '6': // 2 strings to match.
6114 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
6115 : break;
6116 0 : switch (Mnemonic[16]) {
6117 : default: break;
6118 : case '3': // 1 string to match.
6119 0 : if (Mnemonic[17] != '2')
6120 : break;
6121 0 : Mnemonic = "v_cmpsx_ge_f64"; // "v_cmpsx_ge_f64_e32"
6122 0 : return;
6123 : case '6': // 1 string to match.
6124 0 : if (Mnemonic[17] != '4')
6125 : break;
6126 0 : Mnemonic = "v_cmpsx_ge_f64"; // "v_cmpsx_ge_f64_e64"
6127 0 : return;
6128 : }
6129 : break;
6130 : }
6131 : break;
6132 : case 't': // 4 strings to match.
6133 0 : if (memcmp(Mnemonic.data()+10, "_f", 2))
6134 : break;
6135 0 : switch (Mnemonic[12]) {
6136 : default: break;
6137 : case '3': // 2 strings to match.
6138 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
6139 : break;
6140 0 : switch (Mnemonic[16]) {
6141 : default: break;
6142 : case '3': // 1 string to match.
6143 0 : if (Mnemonic[17] != '2')
6144 : break;
6145 0 : Mnemonic = "v_cmpsx_gt_f32"; // "v_cmpsx_gt_f32_e32"
6146 0 : return;
6147 : case '6': // 1 string to match.
6148 0 : if (Mnemonic[17] != '4')
6149 : break;
6150 0 : Mnemonic = "v_cmpsx_gt_f32"; // "v_cmpsx_gt_f32_e64"
6151 0 : return;
6152 : }
6153 : break;
6154 : case '6': // 2 strings to match.
6155 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
6156 : break;
6157 0 : switch (Mnemonic[16]) {
6158 : default: break;
6159 : case '3': // 1 string to match.
6160 0 : if (Mnemonic[17] != '2')
6161 : break;
6162 0 : Mnemonic = "v_cmpsx_gt_f64"; // "v_cmpsx_gt_f64_e32"
6163 0 : return;
6164 : case '6': // 1 string to match.
6165 0 : if (Mnemonic[17] != '4')
6166 : break;
6167 0 : Mnemonic = "v_cmpsx_gt_f64"; // "v_cmpsx_gt_f64_e64"
6168 0 : return;
6169 : }
6170 : break;
6171 : }
6172 : break;
6173 : }
6174 : break;
6175 : case 'l': // 12 strings to match.
6176 0 : switch (Mnemonic[9]) {
6177 : default: break;
6178 : case 'e': // 4 strings to match.
6179 0 : if (memcmp(Mnemonic.data()+10, "_f", 2))
6180 : break;
6181 0 : switch (Mnemonic[12]) {
6182 : default: break;
6183 : case '3': // 2 strings to match.
6184 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
6185 : break;
6186 0 : switch (Mnemonic[16]) {
6187 : default: break;
6188 : case '3': // 1 string to match.
6189 0 : if (Mnemonic[17] != '2')
6190 : break;
6191 0 : Mnemonic = "v_cmpsx_le_f32"; // "v_cmpsx_le_f32_e32"
6192 0 : return;
6193 : case '6': // 1 string to match.
6194 0 : if (Mnemonic[17] != '4')
6195 : break;
6196 0 : Mnemonic = "v_cmpsx_le_f32"; // "v_cmpsx_le_f32_e64"
6197 0 : return;
6198 : }
6199 : break;
6200 : case '6': // 2 strings to match.
6201 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
6202 : break;
6203 0 : switch (Mnemonic[16]) {
6204 : default: break;
6205 : case '3': // 1 string to match.
6206 0 : if (Mnemonic[17] != '2')
6207 : break;
6208 0 : Mnemonic = "v_cmpsx_le_f64"; // "v_cmpsx_le_f64_e32"
6209 0 : return;
6210 : case '6': // 1 string to match.
6211 0 : if (Mnemonic[17] != '4')
6212 : break;
6213 0 : Mnemonic = "v_cmpsx_le_f64"; // "v_cmpsx_le_f64_e64"
6214 0 : return;
6215 : }
6216 : break;
6217 : }
6218 : break;
6219 : case 'g': // 4 strings to match.
6220 0 : if (memcmp(Mnemonic.data()+10, "_f", 2))
6221 : break;
6222 0 : switch (Mnemonic[12]) {
6223 : default: break;
6224 : case '3': // 2 strings to match.
6225 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
6226 : break;
6227 0 : switch (Mnemonic[16]) {
6228 : default: break;
6229 : case '3': // 1 string to match.
6230 0 : if (Mnemonic[17] != '2')
6231 : break;
6232 0 : Mnemonic = "v_cmpsx_lg_f32"; // "v_cmpsx_lg_f32_e32"
6233 0 : return;
6234 : case '6': // 1 string to match.
6235 0 : if (Mnemonic[17] != '4')
6236 : break;
6237 0 : Mnemonic = "v_cmpsx_lg_f32"; // "v_cmpsx_lg_f32_e64"
6238 0 : return;
6239 : }
6240 : break;
6241 : case '6': // 2 strings to match.
6242 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
6243 : break;
6244 0 : switch (Mnemonic[16]) {
6245 : default: break;
6246 : case '3': // 1 string to match.
6247 0 : if (Mnemonic[17] != '2')
6248 : break;
6249 0 : Mnemonic = "v_cmpsx_lg_f64"; // "v_cmpsx_lg_f64_e32"
6250 0 : return;
6251 : case '6': // 1 string to match.
6252 0 : if (Mnemonic[17] != '4')
6253 : break;
6254 0 : Mnemonic = "v_cmpsx_lg_f64"; // "v_cmpsx_lg_f64_e64"
6255 0 : return;
6256 : }
6257 : break;
6258 : }
6259 : break;
6260 : case 't': // 4 strings to match.
6261 0 : if (memcmp(Mnemonic.data()+10, "_f", 2))
6262 : break;
6263 0 : switch (Mnemonic[12]) {
6264 : default: break;
6265 : case '3': // 2 strings to match.
6266 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
6267 : break;
6268 0 : switch (Mnemonic[16]) {
6269 : default: break;
6270 : case '3': // 1 string to match.
6271 0 : if (Mnemonic[17] != '2')
6272 : break;
6273 0 : Mnemonic = "v_cmpsx_lt_f32"; // "v_cmpsx_lt_f32_e32"
6274 0 : return;
6275 : case '6': // 1 string to match.
6276 0 : if (Mnemonic[17] != '4')
6277 : break;
6278 0 : Mnemonic = "v_cmpsx_lt_f32"; // "v_cmpsx_lt_f32_e64"
6279 0 : return;
6280 : }
6281 : break;
6282 : case '6': // 2 strings to match.
6283 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
6284 : break;
6285 0 : switch (Mnemonic[16]) {
6286 : default: break;
6287 : case '3': // 1 string to match.
6288 0 : if (Mnemonic[17] != '2')
6289 : break;
6290 0 : Mnemonic = "v_cmpsx_lt_f64"; // "v_cmpsx_lt_f64_e32"
6291 0 : return;
6292 : case '6': // 1 string to match.
6293 0 : if (Mnemonic[17] != '4')
6294 : break;
6295 0 : Mnemonic = "v_cmpsx_lt_f64"; // "v_cmpsx_lt_f64_e64"
6296 0 : return;
6297 : }
6298 : break;
6299 : }
6300 : break;
6301 : }
6302 : break;
6303 : }
6304 : break;
6305 : }
6306 : break;
6307 : case 'x': // 28 strings to match.
6308 0 : if (Mnemonic[6] != '_')
6309 : break;
6310 0 : switch (Mnemonic[7]) {
6311 : default: break;
6312 : case 'n': // 24 strings to match.
6313 0 : switch (Mnemonic[8]) {
6314 : default: break;
6315 : case 'e': // 4 strings to match.
6316 0 : if (memcmp(Mnemonic.data()+9, "q_f", 3))
6317 : break;
6318 0 : switch (Mnemonic[12]) {
6319 : default: break;
6320 : case '3': // 2 strings to match.
6321 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
6322 : break;
6323 0 : switch (Mnemonic[16]) {
6324 : default: break;
6325 : case '3': // 1 string to match.
6326 0 : if (Mnemonic[17] != '2')
6327 : break;
6328 0 : Mnemonic = "v_cmpx_neq_f32"; // "v_cmpx_neq_f32_e32"
6329 0 : return;
6330 : case '6': // 1 string to match.
6331 0 : if (Mnemonic[17] != '4')
6332 : break;
6333 0 : Mnemonic = "v_cmpx_neq_f32"; // "v_cmpx_neq_f32_e64"
6334 0 : return;
6335 : }
6336 : break;
6337 : case '6': // 2 strings to match.
6338 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
6339 : break;
6340 0 : switch (Mnemonic[16]) {
6341 : default: break;
6342 : case '3': // 1 string to match.
6343 0 : if (Mnemonic[17] != '2')
6344 : break;
6345 0 : Mnemonic = "v_cmpx_neq_f64"; // "v_cmpx_neq_f64_e32"
6346 0 : return;
6347 : case '6': // 1 string to match.
6348 0 : if (Mnemonic[17] != '4')
6349 : break;
6350 0 : Mnemonic = "v_cmpx_neq_f64"; // "v_cmpx_neq_f64_e64"
6351 0 : return;
6352 : }
6353 : break;
6354 : }
6355 : break;
6356 : case 'g': // 8 strings to match.
6357 0 : switch (Mnemonic[9]) {
6358 : default: break;
6359 : case 'e': // 4 strings to match.
6360 0 : if (memcmp(Mnemonic.data()+10, "_f", 2))
6361 : break;
6362 0 : switch (Mnemonic[12]) {
6363 : default: break;
6364 : case '3': // 2 strings to match.
6365 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
6366 : break;
6367 0 : switch (Mnemonic[16]) {
6368 : default: break;
6369 : case '3': // 1 string to match.
6370 0 : if (Mnemonic[17] != '2')
6371 : break;
6372 0 : Mnemonic = "v_cmpx_nge_f32"; // "v_cmpx_nge_f32_e32"
6373 0 : return;
6374 : case '6': // 1 string to match.
6375 0 : if (Mnemonic[17] != '4')
6376 : break;
6377 0 : Mnemonic = "v_cmpx_nge_f32"; // "v_cmpx_nge_f32_e64"
6378 0 : return;
6379 : }
6380 : break;
6381 : case '6': // 2 strings to match.
6382 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
6383 : break;
6384 0 : switch (Mnemonic[16]) {
6385 : default: break;
6386 : case '3': // 1 string to match.
6387 0 : if (Mnemonic[17] != '2')
6388 : break;
6389 0 : Mnemonic = "v_cmpx_nge_f64"; // "v_cmpx_nge_f64_e32"
6390 0 : return;
6391 : case '6': // 1 string to match.
6392 0 : if (Mnemonic[17] != '4')
6393 : break;
6394 0 : Mnemonic = "v_cmpx_nge_f64"; // "v_cmpx_nge_f64_e64"
6395 0 : return;
6396 : }
6397 : break;
6398 : }
6399 : break;
6400 : case 't': // 4 strings to match.
6401 0 : if (memcmp(Mnemonic.data()+10, "_f", 2))
6402 : break;
6403 0 : switch (Mnemonic[12]) {
6404 : default: break;
6405 : case '3': // 2 strings to match.
6406 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
6407 : break;
6408 0 : switch (Mnemonic[16]) {
6409 : default: break;
6410 : case '3': // 1 string to match.
6411 0 : if (Mnemonic[17] != '2')
6412 : break;
6413 0 : Mnemonic = "v_cmpx_ngt_f32"; // "v_cmpx_ngt_f32_e32"
6414 0 : return;
6415 : case '6': // 1 string to match.
6416 0 : if (Mnemonic[17] != '4')
6417 : break;
6418 0 : Mnemonic = "v_cmpx_ngt_f32"; // "v_cmpx_ngt_f32_e64"
6419 0 : return;
6420 : }
6421 : break;
6422 : case '6': // 2 strings to match.
6423 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
6424 : break;
6425 0 : switch (Mnemonic[16]) {
6426 : default: break;
6427 : case '3': // 1 string to match.
6428 0 : if (Mnemonic[17] != '2')
6429 : break;
6430 0 : Mnemonic = "v_cmpx_ngt_f64"; // "v_cmpx_ngt_f64_e32"
6431 0 : return;
6432 : case '6': // 1 string to match.
6433 0 : if (Mnemonic[17] != '4')
6434 : break;
6435 0 : Mnemonic = "v_cmpx_ngt_f64"; // "v_cmpx_ngt_f64_e64"
6436 0 : return;
6437 : }
6438 : break;
6439 : }
6440 : break;
6441 : }
6442 : break;
6443 : case 'l': // 12 strings to match.
6444 0 : switch (Mnemonic[9]) {
6445 : default: break;
6446 : case 'e': // 4 strings to match.
6447 0 : if (memcmp(Mnemonic.data()+10, "_f", 2))
6448 : break;
6449 0 : switch (Mnemonic[12]) {
6450 : default: break;
6451 : case '3': // 2 strings to match.
6452 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
6453 : break;
6454 0 : switch (Mnemonic[16]) {
6455 : default: break;
6456 : case '3': // 1 string to match.
6457 0 : if (Mnemonic[17] != '2')
6458 : break;
6459 0 : Mnemonic = "v_cmpx_nle_f32"; // "v_cmpx_nle_f32_e32"
6460 0 : return;
6461 : case '6': // 1 string to match.
6462 0 : if (Mnemonic[17] != '4')
6463 : break;
6464 0 : Mnemonic = "v_cmpx_nle_f32"; // "v_cmpx_nle_f32_e64"
6465 0 : return;
6466 : }
6467 : break;
6468 : case '6': // 2 strings to match.
6469 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
6470 : break;
6471 0 : switch (Mnemonic[16]) {
6472 : default: break;
6473 : case '3': // 1 string to match.
6474 0 : if (Mnemonic[17] != '2')
6475 : break;
6476 0 : Mnemonic = "v_cmpx_nle_f64"; // "v_cmpx_nle_f64_e32"
6477 0 : return;
6478 : case '6': // 1 string to match.
6479 0 : if (Mnemonic[17] != '4')
6480 : break;
6481 0 : Mnemonic = "v_cmpx_nle_f64"; // "v_cmpx_nle_f64_e64"
6482 0 : return;
6483 : }
6484 : break;
6485 : }
6486 : break;
6487 : case 'g': // 4 strings to match.
6488 0 : if (memcmp(Mnemonic.data()+10, "_f", 2))
6489 : break;
6490 0 : switch (Mnemonic[12]) {
6491 : default: break;
6492 : case '3': // 2 strings to match.
6493 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
6494 : break;
6495 0 : switch (Mnemonic[16]) {
6496 : default: break;
6497 : case '3': // 1 string to match.
6498 0 : if (Mnemonic[17] != '2')
6499 : break;
6500 0 : Mnemonic = "v_cmpx_nlg_f32"; // "v_cmpx_nlg_f32_e32"
6501 0 : return;
6502 : case '6': // 1 string to match.
6503 0 : if (Mnemonic[17] != '4')
6504 : break;
6505 0 : Mnemonic = "v_cmpx_nlg_f32"; // "v_cmpx_nlg_f32_e64"
6506 0 : return;
6507 : }
6508 : break;
6509 : case '6': // 2 strings to match.
6510 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
6511 : break;
6512 0 : switch (Mnemonic[16]) {
6513 : default: break;
6514 : case '3': // 1 string to match.
6515 0 : if (Mnemonic[17] != '2')
6516 : break;
6517 0 : Mnemonic = "v_cmpx_nlg_f64"; // "v_cmpx_nlg_f64_e32"
6518 0 : return;
6519 : case '6': // 1 string to match.
6520 0 : if (Mnemonic[17] != '4')
6521 : break;
6522 0 : Mnemonic = "v_cmpx_nlg_f64"; // "v_cmpx_nlg_f64_e64"
6523 0 : return;
6524 : }
6525 : break;
6526 : }
6527 : break;
6528 : case 't': // 4 strings to match.
6529 0 : if (memcmp(Mnemonic.data()+10, "_f", 2))
6530 : break;
6531 0 : switch (Mnemonic[12]) {
6532 : default: break;
6533 : case '3': // 2 strings to match.
6534 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
6535 : break;
6536 0 : switch (Mnemonic[16]) {
6537 : default: break;
6538 : case '3': // 1 string to match.
6539 0 : if (Mnemonic[17] != '2')
6540 : break;
6541 0 : Mnemonic = "v_cmpx_nlt_f32"; // "v_cmpx_nlt_f32_e32"
6542 0 : return;
6543 : case '6': // 1 string to match.
6544 0 : if (Mnemonic[17] != '4')
6545 : break;
6546 0 : Mnemonic = "v_cmpx_nlt_f32"; // "v_cmpx_nlt_f32_e64"
6547 0 : return;
6548 : }
6549 : break;
6550 : case '6': // 2 strings to match.
6551 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
6552 : break;
6553 0 : switch (Mnemonic[16]) {
6554 : default: break;
6555 : case '3': // 1 string to match.
6556 0 : if (Mnemonic[17] != '2')
6557 : break;
6558 0 : Mnemonic = "v_cmpx_nlt_f64"; // "v_cmpx_nlt_f64_e32"
6559 0 : return;
6560 : case '6': // 1 string to match.
6561 0 : if (Mnemonic[17] != '4')
6562 : break;
6563 0 : Mnemonic = "v_cmpx_nlt_f64"; // "v_cmpx_nlt_f64_e64"
6564 0 : return;
6565 : }
6566 : break;
6567 : }
6568 : break;
6569 : }
6570 : break;
6571 : }
6572 : break;
6573 : case 't': // 4 strings to match.
6574 0 : if (memcmp(Mnemonic.data()+8, "ru_f", 4))
6575 : break;
6576 0 : switch (Mnemonic[12]) {
6577 : default: break;
6578 : case '3': // 2 strings to match.
6579 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
6580 : break;
6581 0 : switch (Mnemonic[16]) {
6582 : default: break;
6583 : case '3': // 1 string to match.
6584 0 : if (Mnemonic[17] != '2')
6585 : break;
6586 0 : Mnemonic = "v_cmpx_tru_f32"; // "v_cmpx_tru_f32_e32"
6587 0 : return;
6588 : case '6': // 1 string to match.
6589 0 : if (Mnemonic[17] != '4')
6590 : break;
6591 0 : Mnemonic = "v_cmpx_tru_f32"; // "v_cmpx_tru_f32_e64"
6592 0 : return;
6593 : }
6594 : break;
6595 : case '6': // 2 strings to match.
6596 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
6597 : break;
6598 0 : switch (Mnemonic[16]) {
6599 : default: break;
6600 : case '3': // 1 string to match.
6601 0 : if (Mnemonic[17] != '2')
6602 : break;
6603 0 : Mnemonic = "v_cmpx_tru_f64"; // "v_cmpx_tru_f64_e32"
6604 0 : return;
6605 : case '6': // 1 string to match.
6606 0 : if (Mnemonic[17] != '4')
6607 : break;
6608 0 : Mnemonic = "v_cmpx_tru_f64"; // "v_cmpx_tru_f64_e64"
6609 0 : return;
6610 : }
6611 : break;
6612 : }
6613 : break;
6614 : }
6615 : break;
6616 : }
6617 : break;
6618 : case 'd': // 2 strings to match.
6619 0 : if (memcmp(Mnemonic.data()+3, "iv_fmas_f", 9))
6620 : break;
6621 0 : switch (Mnemonic[12]) {
6622 : default: break;
6623 : case '3': // 1 string to match.
6624 0 : if (memcmp(Mnemonic.data()+13, "2_e64", 5))
6625 : break;
6626 0 : Mnemonic = "v_div_fmas_f32"; // "v_div_fmas_f32_e64"
6627 0 : return;
6628 : case '6': // 1 string to match.
6629 0 : if (memcmp(Mnemonic.data()+13, "4_e64", 5))
6630 : break;
6631 0 : Mnemonic = "v_div_fmas_f64"; // "v_div_fmas_f64_e64"
6632 0 : return;
6633 : }
6634 : break;
6635 : case 'm': // 4 strings to match.
6636 32 : switch (Mnemonic[3]) {
6637 : default: break;
6638 : case 'o': // 2 strings to match.
6639 0 : if (memcmp(Mnemonic.data()+4, "vrelsd_b32_e", 12))
6640 : break;
6641 0 : switch (Mnemonic[16]) {
6642 : default: break;
6643 : case '3': // 1 string to match.
6644 0 : if (Mnemonic[17] != '2')
6645 : break;
6646 0 : Mnemonic = "v_movrelsd_b32"; // "v_movrelsd_b32_e32"
6647 0 : return;
6648 : case '6': // 1 string to match.
6649 0 : if (Mnemonic[17] != '4')
6650 : break;
6651 0 : Mnemonic = "v_movrelsd_b32"; // "v_movrelsd_b32_e64"
6652 0 : return;
6653 : }
6654 : break;
6655 : case 'q': // 2 strings to match.
6656 0 : if (memcmp(Mnemonic.data()+4, "sad_u", 5))
6657 : break;
6658 0 : switch (Mnemonic[9]) {
6659 : default: break;
6660 : case '1': // 1 string to match.
6661 0 : if (memcmp(Mnemonic.data()+10, "6_u8_e64", 8))
6662 : break;
6663 0 : if ((Features & Feature_isGCN) == Feature_isGCN) // "v_mqsad_u16_u8_e64"
6664 0 : Mnemonic = "v_mqsad_u16_u8";
6665 : return;
6666 : case '3': // 1 string to match.
6667 0 : if (memcmp(Mnemonic.data()+10, "2_u8_e64", 8))
6668 : break;
6669 0 : if ((Features & Feature_isGCN) == Feature_isGCN) // "v_mqsad_u32_u8_e64"
6670 0 : Mnemonic = "v_mqsad_u32_u8";
6671 : return;
6672 : }
6673 : break;
6674 : }
6675 : break;
6676 : }
6677 : break;
6678 : case 19: // 49 strings to match.
6679 50 : if (memcmp(Mnemonic.data()+0, "v_", 2))
6680 : break;
6681 80 : switch (Mnemonic[2]) {
6682 : default: break;
6683 : case 'a': // 1 string to match.
6684 0 : if (memcmp(Mnemonic.data()+3, "lignbyte_b32_e64", 16))
6685 : break;
6686 0 : Mnemonic = "v_alignbyte_b32"; // "v_alignbyte_b32_e64"
6687 0 : return;
6688 : case 'c': // 32 strings to match.
6689 8 : if (memcmp(Mnemonic.data()+3, "mp", 2))
6690 : break;
6691 0 : switch (Mnemonic[5]) {
6692 : default: break;
6693 : case '_': // 4 strings to match.
6694 0 : if (memcmp(Mnemonic.data()+6, "class_f", 7))
6695 : break;
6696 0 : switch (Mnemonic[13]) {
6697 : default: break;
6698 : case '3': // 2 strings to match.
6699 0 : if (memcmp(Mnemonic.data()+14, "2_e", 3))
6700 : break;
6701 0 : switch (Mnemonic[17]) {
6702 : default: break;
6703 : case '3': // 1 string to match.
6704 0 : if (Mnemonic[18] != '2')
6705 : break;
6706 0 : Mnemonic = "v_cmp_class_f32"; // "v_cmp_class_f32_e32"
6707 0 : return;
6708 : case '6': // 1 string to match.
6709 0 : if (Mnemonic[18] != '4')
6710 : break;
6711 0 : Mnemonic = "v_cmp_class_f32"; // "v_cmp_class_f32_e64"
6712 0 : return;
6713 : }
6714 : break;
6715 : case '6': // 2 strings to match.
6716 0 : if (memcmp(Mnemonic.data()+14, "4_e", 3))
6717 : break;
6718 0 : switch (Mnemonic[17]) {
6719 : default: break;
6720 : case '3': // 1 string to match.
6721 0 : if (Mnemonic[18] != '2')
6722 : break;
6723 0 : Mnemonic = "v_cmp_class_f64"; // "v_cmp_class_f64_e32"
6724 0 : return;
6725 : case '6': // 1 string to match.
6726 0 : if (Mnemonic[18] != '4')
6727 : break;
6728 0 : Mnemonic = "v_cmp_class_f64"; // "v_cmp_class_f64_e64"
6729 0 : return;
6730 : }
6731 : break;
6732 : }
6733 : break;
6734 : case 's': // 28 strings to match.
6735 0 : if (memcmp(Mnemonic.data()+6, "x_", 2))
6736 : break;
6737 0 : switch (Mnemonic[8]) {
6738 : default: break;
6739 : case 'n': // 24 strings to match.
6740 0 : switch (Mnemonic[9]) {
6741 : default: break;
6742 : case 'e': // 4 strings to match.
6743 0 : if (memcmp(Mnemonic.data()+10, "q_f", 3))
6744 : break;
6745 0 : switch (Mnemonic[13]) {
6746 : default: break;
6747 : case '3': // 2 strings to match.
6748 0 : if (memcmp(Mnemonic.data()+14, "2_e", 3))
6749 : break;
6750 0 : switch (Mnemonic[17]) {
6751 : default: break;
6752 : case '3': // 1 string to match.
6753 0 : if (Mnemonic[18] != '2')
6754 : break;
6755 0 : Mnemonic = "v_cmpsx_neq_f32"; // "v_cmpsx_neq_f32_e32"
6756 0 : return;
6757 : case '6': // 1 string to match.
6758 0 : if (Mnemonic[18] != '4')
6759 : break;
6760 0 : Mnemonic = "v_cmpsx_neq_f32"; // "v_cmpsx_neq_f32_e64"
6761 0 : return;
6762 : }
6763 : break;
6764 : case '6': // 2 strings to match.
6765 0 : if (memcmp(Mnemonic.data()+14, "4_e", 3))
6766 : break;
6767 0 : switch (Mnemonic[17]) {
6768 : default: break;
6769 : case '3': // 1 string to match.
6770 0 : if (Mnemonic[18] != '2')
6771 : break;
6772 0 : Mnemonic = "v_cmpsx_neq_f64"; // "v_cmpsx_neq_f64_e32"
6773 0 : return;
6774 : case '6': // 1 string to match.
6775 0 : if (Mnemonic[18] != '4')
6776 : break;
6777 0 : Mnemonic = "v_cmpsx_neq_f64"; // "v_cmpsx_neq_f64_e64"
6778 0 : return;
6779 : }
6780 : break;
6781 : }
6782 : break;
6783 : case 'g': // 8 strings to match.
6784 0 : switch (Mnemonic[10]) {
6785 : default: break;
6786 : case 'e': // 4 strings to match.
6787 0 : if (memcmp(Mnemonic.data()+11, "_f", 2))
6788 : break;
6789 0 : switch (Mnemonic[13]) {
6790 : default: break;
6791 : case '3': // 2 strings to match.
6792 0 : if (memcmp(Mnemonic.data()+14, "2_e", 3))
6793 : break;
6794 0 : switch (Mnemonic[17]) {
6795 : default: break;
6796 : case '3': // 1 string to match.
6797 0 : if (Mnemonic[18] != '2')
6798 : break;
6799 0 : Mnemonic = "v_cmpsx_nge_f32"; // "v_cmpsx_nge_f32_e32"
6800 0 : return;
6801 : case '6': // 1 string to match.
6802 0 : if (Mnemonic[18] != '4')
6803 : break;
6804 0 : Mnemonic = "v_cmpsx_nge_f32"; // "v_cmpsx_nge_f32_e64"
6805 0 : return;
6806 : }
6807 : break;
6808 : case '6': // 2 strings to match.
6809 0 : if (memcmp(Mnemonic.data()+14, "4_e", 3))
6810 : break;
6811 0 : switch (Mnemonic[17]) {
6812 : default: break;
6813 : case '3': // 1 string to match.
6814 0 : if (Mnemonic[18] != '2')
6815 : break;
6816 0 : Mnemonic = "v_cmpsx_nge_f64"; // "v_cmpsx_nge_f64_e32"
6817 0 : return;
6818 : case '6': // 1 string to match.
6819 0 : if (Mnemonic[18] != '4')
6820 : break;
6821 0 : Mnemonic = "v_cmpsx_nge_f64"; // "v_cmpsx_nge_f64_e64"
6822 0 : return;
6823 : }
6824 : break;
6825 : }
6826 : break;
6827 : case 't': // 4 strings to match.
6828 0 : if (memcmp(Mnemonic.data()+11, "_f", 2))
6829 : break;
6830 0 : switch (Mnemonic[13]) {
6831 : default: break;
6832 : case '3': // 2 strings to match.
6833 0 : if (memcmp(Mnemonic.data()+14, "2_e", 3))
6834 : break;
6835 0 : switch (Mnemonic[17]) {
6836 : default: break;
6837 : case '3': // 1 string to match.
6838 0 : if (Mnemonic[18] != '2')
6839 : break;
6840 0 : Mnemonic = "v_cmpsx_ngt_f32"; // "v_cmpsx_ngt_f32_e32"
6841 0 : return;
6842 : case '6': // 1 string to match.
6843 0 : if (Mnemonic[18] != '4')
6844 : break;
6845 0 : Mnemonic = "v_cmpsx_ngt_f32"; // "v_cmpsx_ngt_f32_e64"
6846 0 : return;
6847 : }
6848 : break;
6849 : case '6': // 2 strings to match.
6850 0 : if (memcmp(Mnemonic.data()+14, "4_e", 3))
6851 : break;
6852 0 : switch (Mnemonic[17]) {
6853 : default: break;
6854 : case '3': // 1 string to match.
6855 0 : if (Mnemonic[18] != '2')
6856 : break;
6857 0 : Mnemonic = "v_cmpsx_ngt_f64"; // "v_cmpsx_ngt_f64_e32"
6858 0 : return;
6859 : case '6': // 1 string to match.
6860 0 : if (Mnemonic[18] != '4')
6861 : break;
6862 0 : Mnemonic = "v_cmpsx_ngt_f64"; // "v_cmpsx_ngt_f64_e64"
6863 0 : return;
6864 : }
6865 : break;
6866 : }
6867 : break;
6868 : }
6869 : break;
6870 : case 'l': // 12 strings to match.
6871 0 : switch (Mnemonic[10]) {
6872 : default: break;
6873 : case 'e': // 4 strings to match.
6874 0 : if (memcmp(Mnemonic.data()+11, "_f", 2))
6875 : break;
6876 0 : switch (Mnemonic[13]) {
6877 : default: break;
6878 : case '3': // 2 strings to match.
6879 0 : if (memcmp(Mnemonic.data()+14, "2_e", 3))
6880 : break;
6881 0 : switch (Mnemonic[17]) {
6882 : default: break;
6883 : case '3': // 1 string to match.
6884 0 : if (Mnemonic[18] != '2')
6885 : break;
6886 0 : Mnemonic = "v_cmpsx_nle_f32"; // "v_cmpsx_nle_f32_e32"
6887 0 : return;
6888 : case '6': // 1 string to match.
6889 0 : if (Mnemonic[18] != '4')
6890 : break;
6891 0 : Mnemonic = "v_cmpsx_nle_f32"; // "v_cmpsx_nle_f32_e64"
6892 0 : return;
6893 : }
6894 : break;
6895 : case '6': // 2 strings to match.
6896 0 : if (memcmp(Mnemonic.data()+14, "4_e", 3))
6897 : break;
6898 0 : switch (Mnemonic[17]) {
6899 : default: break;
6900 : case '3': // 1 string to match.
6901 0 : if (Mnemonic[18] != '2')
6902 : break;
6903 0 : Mnemonic = "v_cmpsx_nle_f64"; // "v_cmpsx_nle_f64_e32"
6904 0 : return;
6905 : case '6': // 1 string to match.
6906 0 : if (Mnemonic[18] != '4')
6907 : break;
6908 0 : Mnemonic = "v_cmpsx_nle_f64"; // "v_cmpsx_nle_f64_e64"
6909 0 : return;
6910 : }
6911 : break;
6912 : }
6913 : break;
6914 : case 'g': // 4 strings to match.
6915 0 : if (memcmp(Mnemonic.data()+11, "_f", 2))
6916 : break;
6917 0 : switch (Mnemonic[13]) {
6918 : default: break;
6919 : case '3': // 2 strings to match.
6920 0 : if (memcmp(Mnemonic.data()+14, "2_e", 3))
6921 : break;
6922 0 : switch (Mnemonic[17]) {
6923 : default: break;
6924 : case '3': // 1 string to match.
6925 0 : if (Mnemonic[18] != '2')
6926 : break;
6927 0 : Mnemonic = "v_cmpsx_nlg_f32"; // "v_cmpsx_nlg_f32_e32"
6928 0 : return;
6929 : case '6': // 1 string to match.
6930 0 : if (Mnemonic[18] != '4')
6931 : break;
6932 0 : Mnemonic = "v_cmpsx_nlg_f32"; // "v_cmpsx_nlg_f32_e64"
6933 0 : return;
6934 : }
6935 : break;
6936 : case '6': // 2 strings to match.
6937 0 : if (memcmp(Mnemonic.data()+14, "4_e", 3))
6938 : break;
6939 0 : switch (Mnemonic[17]) {
6940 : default: break;
6941 : case '3': // 1 string to match.
6942 0 : if (Mnemonic[18] != '2')
6943 : break;
6944 0 : Mnemonic = "v_cmpsx_nlg_f64"; // "v_cmpsx_nlg_f64_e32"
6945 0 : return;
6946 : case '6': // 1 string to match.
6947 0 : if (Mnemonic[18] != '4')
6948 : break;
6949 0 : Mnemonic = "v_cmpsx_nlg_f64"; // "v_cmpsx_nlg_f64_e64"
6950 0 : return;
6951 : }
6952 : break;
6953 : }
6954 : break;
6955 : case 't': // 4 strings to match.
6956 0 : if (memcmp(Mnemonic.data()+11, "_f", 2))
6957 : break;
6958 0 : switch (Mnemonic[13]) {
6959 : default: break;
6960 : case '3': // 2 strings to match.
6961 0 : if (memcmp(Mnemonic.data()+14, "2_e", 3))
6962 : break;
6963 0 : switch (Mnemonic[17]) {
6964 : default: break;
6965 : case '3': // 1 string to match.
6966 0 : if (Mnemonic[18] != '2')
6967 : break;
6968 0 : Mnemonic = "v_cmpsx_nlt_f32"; // "v_cmpsx_nlt_f32_e32"
6969 0 : return;
6970 : case '6': // 1 string to match.
6971 0 : if (Mnemonic[18] != '4')
6972 : break;
6973 0 : Mnemonic = "v_cmpsx_nlt_f32"; // "v_cmpsx_nlt_f32_e64"
6974 0 : return;
6975 : }
6976 : break;
6977 : case '6': // 2 strings to match.
6978 0 : if (memcmp(Mnemonic.data()+14, "4_e", 3))
6979 : break;
6980 0 : switch (Mnemonic[17]) {
6981 : default: break;
6982 : case '3': // 1 string to match.
6983 0 : if (Mnemonic[18] != '2')
6984 : break;
6985 0 : Mnemonic = "v_cmpsx_nlt_f64"; // "v_cmpsx_nlt_f64_e32"
6986 0 : return;
6987 : case '6': // 1 string to match.
6988 0 : if (Mnemonic[18] != '4')
6989 : break;
6990 0 : Mnemonic = "v_cmpsx_nlt_f64"; // "v_cmpsx_nlt_f64_e64"
6991 0 : return;
6992 : }
6993 : break;
6994 : }
6995 : break;
6996 : }
6997 : break;
6998 : }
6999 : break;
7000 : case 't': // 4 strings to match.
7001 0 : if (memcmp(Mnemonic.data()+9, "ru_f", 4))
7002 : break;
7003 0 : switch (Mnemonic[13]) {
7004 : default: break;
7005 : case '3': // 2 strings to match.
7006 0 : if (memcmp(Mnemonic.data()+14, "2_e", 3))
7007 : break;
7008 0 : switch (Mnemonic[17]) {
7009 : default: break;
7010 : case '3': // 1 string to match.
7011 0 : if (Mnemonic[18] != '2')
7012 : break;
7013 0 : Mnemonic = "v_cmpsx_tru_f32"; // "v_cmpsx_tru_f32_e32"
7014 0 : return;
7015 : case '6': // 1 string to match.
7016 0 : if (Mnemonic[18] != '4')
7017 : break;
7018 0 : Mnemonic = "v_cmpsx_tru_f32"; // "v_cmpsx_tru_f32_e64"
7019 0 : return;
7020 : }
7021 : break;
7022 : case '6': // 2 strings to match.
7023 0 : if (memcmp(Mnemonic.data()+14, "4_e", 3))
7024 : break;
7025 0 : switch (Mnemonic[17]) {
7026 : default: break;
7027 : case '3': // 1 string to match.
7028 0 : if (Mnemonic[18] != '2')
7029 : break;
7030 0 : Mnemonic = "v_cmpsx_tru_f64"; // "v_cmpsx_tru_f64_e32"
7031 0 : return;
7032 : case '6': // 1 string to match.
7033 0 : if (Mnemonic[18] != '4')
7034 : break;
7035 0 : Mnemonic = "v_cmpsx_tru_f64"; // "v_cmpsx_tru_f64_e64"
7036 0 : return;
7037 : }
7038 : break;
7039 : }
7040 : break;
7041 : }
7042 : break;
7043 : }
7044 : break;
7045 : case 'd': // 4 strings to match.
7046 0 : if (memcmp(Mnemonic.data()+3, "iv_", 3))
7047 : break;
7048 0 : switch (Mnemonic[6]) {
7049 : default: break;
7050 : case 'f': // 2 strings to match.
7051 0 : if (memcmp(Mnemonic.data()+7, "ixup_f", 6))
7052 : break;
7053 0 : switch (Mnemonic[13]) {
7054 : default: break;
7055 : case '3': // 1 string to match.
7056 0 : if (memcmp(Mnemonic.data()+14, "2_e64", 5))
7057 : break;
7058 0 : Mnemonic = "v_div_fixup_f32"; // "v_div_fixup_f32_e64"
7059 0 : return;
7060 : case '6': // 1 string to match.
7061 0 : if (memcmp(Mnemonic.data()+14, "4_e64", 5))
7062 : break;
7063 0 : Mnemonic = "v_div_fixup_f64"; // "v_div_fixup_f64_e64"
7064 0 : return;
7065 : }
7066 : break;
7067 : case 's': // 2 strings to match.
7068 0 : if (memcmp(Mnemonic.data()+7, "cale_f", 6))
7069 : break;
7070 0 : switch (Mnemonic[13]) {
7071 : default: break;
7072 : case '3': // 1 string to match.
7073 0 : if (memcmp(Mnemonic.data()+14, "2_e64", 5))
7074 : break;
7075 0 : Mnemonic = "v_div_scale_f32"; // "v_div_scale_f32_e64"
7076 0 : return;
7077 : case '6': // 1 string to match.
7078 0 : if (memcmp(Mnemonic.data()+14, "4_e64", 5))
7079 : break;
7080 0 : Mnemonic = "v_div_scale_f64"; // "v_div_scale_f64_e64"
7081 0 : return;
7082 : }
7083 : break;
7084 : }
7085 : break;
7086 : case 'l': // 2 strings to match.
7087 0 : if (memcmp(Mnemonic.data()+3, "og_clamp_f32_e", 14))
7088 : break;
7089 0 : switch (Mnemonic[17]) {
7090 : default: break;
7091 : case '3': // 1 string to match.
7092 0 : if (Mnemonic[18] != '2')
7093 : break;
7094 0 : Mnemonic = "v_log_clamp_f32"; // "v_log_clamp_f32_e32"
7095 0 : return;
7096 : case '6': // 1 string to match.
7097 0 : if (Mnemonic[18] != '4')
7098 : break;
7099 0 : Mnemonic = "v_log_clamp_f32"; // "v_log_clamp_f32_e64"
7100 0 : return;
7101 : }
7102 : break;
7103 : case 'r': // 10 strings to match.
7104 16 : switch (Mnemonic[3]) {
7105 : default: break;
7106 : case 'c': // 6 strings to match.
7107 0 : if (memcmp(Mnemonic.data()+4, "p_", 2))
7108 : break;
7109 0 : switch (Mnemonic[6]) {
7110 : default: break;
7111 : case 'c': // 4 strings to match.
7112 0 : if (memcmp(Mnemonic.data()+7, "lamp_f", 6))
7113 : break;
7114 0 : switch (Mnemonic[13]) {
7115 : default: break;
7116 : case '3': // 2 strings to match.
7117 0 : if (memcmp(Mnemonic.data()+14, "2_e", 3))
7118 : break;
7119 0 : switch (Mnemonic[17]) {
7120 : default: break;
7121 : case '3': // 1 string to match.
7122 0 : if (Mnemonic[18] != '2')
7123 : break;
7124 0 : Mnemonic = "v_rcp_clamp_f32"; // "v_rcp_clamp_f32_e32"
7125 0 : return;
7126 : case '6': // 1 string to match.
7127 0 : if (Mnemonic[18] != '4')
7128 : break;
7129 0 : Mnemonic = "v_rcp_clamp_f32"; // "v_rcp_clamp_f32_e64"
7130 0 : return;
7131 : }
7132 : break;
7133 : case '6': // 2 strings to match.
7134 0 : if (memcmp(Mnemonic.data()+14, "4_e", 3))
7135 : break;
7136 0 : switch (Mnemonic[17]) {
7137 : default: break;
7138 : case '3': // 1 string to match.
7139 0 : if (Mnemonic[18] != '2')
7140 : break;
7141 0 : Mnemonic = "v_rcp_clamp_f64"; // "v_rcp_clamp_f64_e32"
7142 0 : return;
7143 : case '6': // 1 string to match.
7144 0 : if (Mnemonic[18] != '4')
7145 : break;
7146 0 : Mnemonic = "v_rcp_clamp_f64"; // "v_rcp_clamp_f64_e64"
7147 0 : return;
7148 : }
7149 : break;
7150 : }
7151 : break;
7152 : case 'i': // 2 strings to match.
7153 0 : if (memcmp(Mnemonic.data()+7, "flag_f32_e", 10))
7154 : break;
7155 0 : switch (Mnemonic[17]) {
7156 : default: break;
7157 : case '3': // 1 string to match.
7158 0 : if (Mnemonic[18] != '2')
7159 : break;
7160 0 : Mnemonic = "v_rcp_iflag_f32"; // "v_rcp_iflag_f32_e32"
7161 0 : return;
7162 : case '6': // 1 string to match.
7163 0 : if (Mnemonic[18] != '4')
7164 : break;
7165 0 : Mnemonic = "v_rcp_iflag_f32"; // "v_rcp_iflag_f32_e64"
7166 0 : return;
7167 : }
7168 : break;
7169 : }
7170 : break;
7171 : case 's': // 4 strings to match.
7172 0 : if (memcmp(Mnemonic.data()+4, "q_clamp_f", 9))
7173 : break;
7174 0 : switch (Mnemonic[13]) {
7175 : default: break;
7176 : case '3': // 2 strings to match.
7177 0 : if (memcmp(Mnemonic.data()+14, "2_e", 3))
7178 : break;
7179 0 : switch (Mnemonic[17]) {
7180 : default: break;
7181 : case '3': // 1 string to match.
7182 0 : if (Mnemonic[18] != '2')
7183 : break;
7184 0 : Mnemonic = "v_rsq_clamp_f32"; // "v_rsq_clamp_f32_e32"
7185 0 : return;
7186 : case '6': // 1 string to match.
7187 0 : if (Mnemonic[18] != '4')
7188 : break;
7189 0 : Mnemonic = "v_rsq_clamp_f32"; // "v_rsq_clamp_f32_e64"
7190 0 : return;
7191 : }
7192 : break;
7193 : case '6': // 2 strings to match.
7194 0 : if (memcmp(Mnemonic.data()+14, "4_e", 3))
7195 : break;
7196 0 : switch (Mnemonic[17]) {
7197 : default: break;
7198 : case '3': // 1 string to match.
7199 0 : if (Mnemonic[18] != '2')
7200 : break;
7201 0 : Mnemonic = "v_rsq_clamp_f64"; // "v_rsq_clamp_f64_e32"
7202 0 : return;
7203 : case '6': // 1 string to match.
7204 0 : if (Mnemonic[18] != '4')
7205 : break;
7206 0 : Mnemonic = "v_rsq_clamp_f64"; // "v_rsq_clamp_f64_e64"
7207 0 : return;
7208 : }
7209 : break;
7210 : }
7211 : break;
7212 : }
7213 : break;
7214 : }
7215 : break;
7216 : case 20: // 47 strings to match.
7217 64 : if (memcmp(Mnemonic.data()+0, "v_", 2))
7218 : break;
7219 112 : switch (Mnemonic[2]) {
7220 : default: break;
7221 : case 'c': // 18 strings to match.
7222 80 : switch (Mnemonic[3]) {
7223 : default: break;
7224 : case 'm': // 4 strings to match.
7225 0 : if (memcmp(Mnemonic.data()+4, "px_class_f", 10))
7226 : break;
7227 0 : switch (Mnemonic[14]) {
7228 : default: break;
7229 : case '3': // 2 strings to match.
7230 0 : if (memcmp(Mnemonic.data()+15, "2_e", 3))
7231 : break;
7232 0 : switch (Mnemonic[18]) {
7233 : default: break;
7234 : case '3': // 1 string to match.
7235 0 : if (Mnemonic[19] != '2')
7236 : break;
7237 0 : Mnemonic = "v_cmpx_class_f32"; // "v_cmpx_class_f32_e32"
7238 0 : return;
7239 : case '6': // 1 string to match.
7240 0 : if (Mnemonic[19] != '4')
7241 : break;
7242 0 : Mnemonic = "v_cmpx_class_f32"; // "v_cmpx_class_f32_e64"
7243 0 : return;
7244 : }
7245 : break;
7246 : case '6': // 2 strings to match.
7247 0 : if (memcmp(Mnemonic.data()+15, "4_e", 3))
7248 : break;
7249 0 : switch (Mnemonic[18]) {
7250 : default: break;
7251 : case '3': // 1 string to match.
7252 0 : if (Mnemonic[19] != '2')
7253 : break;
7254 0 : Mnemonic = "v_cmpx_class_f64"; // "v_cmpx_class_f64_e32"
7255 0 : return;
7256 : case '6': // 1 string to match.
7257 0 : if (Mnemonic[19] != '4')
7258 : break;
7259 0 : Mnemonic = "v_cmpx_class_f64"; // "v_cmpx_class_f64_e64"
7260 0 : return;
7261 : }
7262 : break;
7263 : }
7264 : break;
7265 : case 'v': // 14 strings to match.
7266 40 : if (memcmp(Mnemonic.data()+4, "t_", 2))
7267 : break;
7268 80 : switch (Mnemonic[6]) {
7269 : default: break;
7270 : case 'f': // 8 strings to match.
7271 8 : if (memcmp(Mnemonic.data()+7, "32_ubyte", 8))
7272 : break;
7273 16 : switch (Mnemonic[15]) {
7274 : default: break;
7275 : case '0': // 2 strings to match.
7276 0 : if (memcmp(Mnemonic.data()+16, "_e", 2))
7277 : break;
7278 0 : switch (Mnemonic[18]) {
7279 : default: break;
7280 : case '3': // 1 string to match.
7281 0 : if (Mnemonic[19] != '2')
7282 : break;
7283 0 : Mnemonic = "v_cvt_f32_ubyte0"; // "v_cvt_f32_ubyte0_e32"
7284 0 : return;
7285 : case '6': // 1 string to match.
7286 0 : if (Mnemonic[19] != '4')
7287 : break;
7288 0 : Mnemonic = "v_cvt_f32_ubyte0"; // "v_cvt_f32_ubyte0_e64"
7289 0 : return;
7290 : }
7291 : break;
7292 : case '1': // 2 strings to match.
7293 8 : if (memcmp(Mnemonic.data()+16, "_e", 2))
7294 : break;
7295 16 : switch (Mnemonic[18]) {
7296 : default: break;
7297 : case '3': // 1 string to match.
7298 16 : if (Mnemonic[19] != '2')
7299 : break;
7300 8 : Mnemonic = "v_cvt_f32_ubyte1"; // "v_cvt_f32_ubyte1_e32"
7301 8 : return;
7302 : case '6': // 1 string to match.
7303 0 : if (Mnemonic[19] != '4')
7304 : break;
7305 0 : Mnemonic = "v_cvt_f32_ubyte1"; // "v_cvt_f32_ubyte1_e64"
7306 0 : return;
7307 : }
7308 : break;
7309 : case '2': // 2 strings to match.
7310 0 : if (memcmp(Mnemonic.data()+16, "_e", 2))
7311 : break;
7312 0 : switch (Mnemonic[18]) {
7313 : default: break;
7314 : case '3': // 1 string to match.
7315 0 : if (Mnemonic[19] != '2')
7316 : break;
7317 0 : Mnemonic = "v_cvt_f32_ubyte2"; // "v_cvt_f32_ubyte2_e32"
7318 0 : return;
7319 : case '6': // 1 string to match.
7320 0 : if (Mnemonic[19] != '4')
7321 : break;
7322 0 : Mnemonic = "v_cvt_f32_ubyte2"; // "v_cvt_f32_ubyte2_e64"
7323 0 : return;
7324 : }
7325 : break;
7326 : case '3': // 2 strings to match.
7327 0 : if (memcmp(Mnemonic.data()+16, "_e", 2))
7328 : break;
7329 0 : switch (Mnemonic[18]) {
7330 : default: break;
7331 : case '3': // 1 string to match.
7332 0 : if (Mnemonic[19] != '2')
7333 : break;
7334 0 : Mnemonic = "v_cvt_f32_ubyte3"; // "v_cvt_f32_ubyte3_e32"
7335 0 : return;
7336 : case '6': // 1 string to match.
7337 0 : if (Mnemonic[19] != '4')
7338 : break;
7339 0 : Mnemonic = "v_cvt_f32_ubyte3"; // "v_cvt_f32_ubyte3_e64"
7340 0 : return;
7341 : }
7342 : break;
7343 : }
7344 : break;
7345 : case 'o': // 2 strings to match.
7346 8 : if (memcmp(Mnemonic.data()+7, "ff_f32_i4_e", 11))
7347 : break;
7348 16 : switch (Mnemonic[18]) {
7349 : default: break;
7350 : case '3': // 1 string to match.
7351 16 : if (Mnemonic[19] != '2')
7352 : break;
7353 8 : Mnemonic = "v_cvt_off_f32_i4"; // "v_cvt_off_f32_i4_e32"
7354 8 : return;
7355 : case '6': // 1 string to match.
7356 0 : if (Mnemonic[19] != '4')
7357 : break;
7358 0 : Mnemonic = "v_cvt_off_f32_i4"; // "v_cvt_off_f32_i4_e64"
7359 0 : return;
7360 : }
7361 : break;
7362 : case 'p': // 4 strings to match.
7363 24 : if (memcmp(Mnemonic.data()+7, "k_", 2))
7364 : break;
7365 0 : switch (Mnemonic[9]) {
7366 : default: break;
7367 : case 'i': // 2 strings to match.
7368 0 : if (memcmp(Mnemonic.data()+10, "16_i32_e", 8))
7369 : break;
7370 0 : switch (Mnemonic[18]) {
7371 : default: break;
7372 : case '3': // 1 string to match.
7373 0 : if (Mnemonic[19] != '2')
7374 : break;
7375 0 : Mnemonic = "v_cvt_pk_i16_i32"; // "v_cvt_pk_i16_i32_e32"
7376 0 : return;
7377 : case '6': // 1 string to match.
7378 0 : if (Mnemonic[19] != '4')
7379 : break;
7380 0 : Mnemonic = "v_cvt_pk_i16_i32"; // "v_cvt_pk_i16_i32_e64"
7381 0 : return;
7382 : }
7383 : break;
7384 : case 'u': // 2 strings to match.
7385 0 : if (memcmp(Mnemonic.data()+10, "16_u32_e", 8))
7386 : break;
7387 0 : switch (Mnemonic[18]) {
7388 : default: break;
7389 : case '3': // 1 string to match.
7390 0 : if (Mnemonic[19] != '2')
7391 : break;
7392 0 : Mnemonic = "v_cvt_pk_u16_u32"; // "v_cvt_pk_u16_u32_e32"
7393 0 : return;
7394 : case '6': // 1 string to match.
7395 0 : if (Mnemonic[19] != '4')
7396 : break;
7397 0 : Mnemonic = "v_cvt_pk_u16_u32"; // "v_cvt_pk_u16_u32_e64"
7398 0 : return;
7399 : }
7400 : break;
7401 : }
7402 : break;
7403 : }
7404 : break;
7405 : }
7406 : break;
7407 : case 'e': // 2 strings to match.
7408 0 : if (memcmp(Mnemonic.data()+3, "xp_legacy_f32_e", 15))
7409 : break;
7410 0 : switch (Mnemonic[18]) {
7411 : default: break;
7412 : case '3': // 1 string to match.
7413 0 : if (Mnemonic[19] != '2')
7414 : break;
7415 0 : Mnemonic = "v_exp_legacy_f32"; // "v_exp_legacy_f32_e32"
7416 0 : return;
7417 : case '6': // 1 string to match.
7418 0 : if (Mnemonic[19] != '4')
7419 : break;
7420 0 : Mnemonic = "v_exp_legacy_f32"; // "v_exp_legacy_f32_e64"
7421 0 : return;
7422 : }
7423 : break;
7424 : case 'f': // 6 strings to match.
7425 0 : if (memcmp(Mnemonic.data()+3, "rexp_mant_f", 11))
7426 : break;
7427 0 : switch (Mnemonic[14]) {
7428 : default: break;
7429 : case '1': // 2 strings to match.
7430 0 : if (memcmp(Mnemonic.data()+15, "6_e", 3))
7431 : break;
7432 0 : switch (Mnemonic[18]) {
7433 : default: break;
7434 : case '3': // 1 string to match.
7435 0 : if (Mnemonic[19] != '2')
7436 : break;
7437 0 : Mnemonic = "v_frexp_mant_f16"; // "v_frexp_mant_f16_e32"
7438 0 : return;
7439 : case '6': // 1 string to match.
7440 0 : if (Mnemonic[19] != '4')
7441 : break;
7442 0 : Mnemonic = "v_frexp_mant_f16"; // "v_frexp_mant_f16_e64"
7443 0 : return;
7444 : }
7445 : break;
7446 : case '3': // 2 strings to match.
7447 0 : if (memcmp(Mnemonic.data()+15, "2_e", 3))
7448 : break;
7449 0 : switch (Mnemonic[18]) {
7450 : default: break;
7451 : case '3': // 1 string to match.
7452 0 : if (Mnemonic[19] != '2')
7453 : break;
7454 0 : Mnemonic = "v_frexp_mant_f32"; // "v_frexp_mant_f32_e32"
7455 0 : return;
7456 : case '6': // 1 string to match.
7457 0 : if (Mnemonic[19] != '4')
7458 : break;
7459 0 : Mnemonic = "v_frexp_mant_f32"; // "v_frexp_mant_f32_e64"
7460 0 : return;
7461 : }
7462 : break;
7463 : case '6': // 2 strings to match.
7464 0 : if (memcmp(Mnemonic.data()+15, "4_e", 3))
7465 : break;
7466 0 : switch (Mnemonic[18]) {
7467 : default: break;
7468 : case '3': // 1 string to match.
7469 0 : if (Mnemonic[19] != '2')
7470 : break;
7471 0 : Mnemonic = "v_frexp_mant_f64"; // "v_frexp_mant_f64_e32"
7472 0 : return;
7473 : case '6': // 1 string to match.
7474 0 : if (Mnemonic[19] != '4')
7475 : break;
7476 0 : Mnemonic = "v_frexp_mant_f64"; // "v_frexp_mant_f64_e64"
7477 0 : return;
7478 : }
7479 : break;
7480 : }
7481 : break;
7482 : case 'l': // 2 strings to match.
7483 0 : if (memcmp(Mnemonic.data()+3, "og_legacy_f32_e", 15))
7484 : break;
7485 0 : switch (Mnemonic[18]) {
7486 : default: break;
7487 : case '3': // 1 string to match.
7488 0 : if (Mnemonic[19] != '2')
7489 : break;
7490 0 : Mnemonic = "v_log_legacy_f32"; // "v_log_legacy_f32_e32"
7491 0 : return;
7492 : case '6': // 1 string to match.
7493 0 : if (Mnemonic[19] != '4')
7494 : break;
7495 0 : Mnemonic = "v_log_legacy_f32"; // "v_log_legacy_f32_e64"
7496 0 : return;
7497 : }
7498 : break;
7499 : case 'm': // 13 strings to match.
7500 32 : switch (Mnemonic[3]) {
7501 : default: break;
7502 : case 'a': // 5 strings to match.
7503 0 : switch (Mnemonic[4]) {
7504 : default: break;
7505 : case 'c': // 2 strings to match.
7506 0 : if (memcmp(Mnemonic.data()+5, "_legacy_f32_e", 13))
7507 : break;
7508 0 : switch (Mnemonic[18]) {
7509 : default: break;
7510 : case '3': // 1 string to match.
7511 0 : if (Mnemonic[19] != '2')
7512 : break;
7513 0 : Mnemonic = "v_mac_legacy_f32"; // "v_mac_legacy_f32_e32"
7514 0 : return;
7515 : case '6': // 1 string to match.
7516 0 : if (Mnemonic[19] != '4')
7517 : break;
7518 0 : Mnemonic = "v_mac_legacy_f32"; // "v_mac_legacy_f32_e64"
7519 0 : return;
7520 : }
7521 : break;
7522 : case 'd': // 1 string to match.
7523 0 : if (memcmp(Mnemonic.data()+5, "_legacy_f32_e64", 15))
7524 : break;
7525 0 : Mnemonic = "v_mad_legacy_f32"; // "v_mad_legacy_f32_e64"
7526 0 : return;
7527 : case 'x': // 2 strings to match.
7528 0 : if (memcmp(Mnemonic.data()+5, "_legacy_f32_e", 13))
7529 : break;
7530 0 : switch (Mnemonic[18]) {
7531 : default: break;
7532 : case '3': // 1 string to match.
7533 0 : if (Mnemonic[19] != '2')
7534 : break;
7535 0 : Mnemonic = "v_max_legacy_f32"; // "v_max_legacy_f32_e32"
7536 0 : return;
7537 : case '6': // 1 string to match.
7538 0 : if (Mnemonic[19] != '4')
7539 : break;
7540 0 : Mnemonic = "v_max_legacy_f32"; // "v_max_legacy_f32_e64"
7541 0 : return;
7542 : }
7543 : break;
7544 : }
7545 : break;
7546 : case 'i': // 2 strings to match.
7547 8 : if (memcmp(Mnemonic.data()+4, "n_legacy_f32_e", 14))
7548 : break;
7549 16 : switch (Mnemonic[18]) {
7550 : default: break;
7551 : case '3': // 1 string to match.
7552 16 : if (Mnemonic[19] != '2')
7553 : break;
7554 8 : Mnemonic = "v_min_legacy_f32"; // "v_min_legacy_f32_e32"
7555 8 : return;
7556 : case '6': // 1 string to match.
7557 0 : if (Mnemonic[19] != '4')
7558 : break;
7559 0 : Mnemonic = "v_min_legacy_f32"; // "v_min_legacy_f32_e64"
7560 0 : return;
7561 : }
7562 : break;
7563 : case 'u': // 6 strings to match.
7564 8 : if (memcmp(Mnemonic.data()+4, "l_", 2))
7565 : break;
7566 16 : switch (Mnemonic[6]) {
7567 : default: break;
7568 : case 'h': // 4 strings to match.
7569 0 : if (memcmp(Mnemonic.data()+7, "i_", 2))
7570 : break;
7571 0 : switch (Mnemonic[9]) {
7572 : default: break;
7573 : case 'i': // 2 strings to match.
7574 0 : if (memcmp(Mnemonic.data()+10, "32_i24_e", 8))
7575 : break;
7576 0 : switch (Mnemonic[18]) {
7577 : default: break;
7578 : case '3': // 1 string to match.
7579 0 : if (Mnemonic[19] != '2')
7580 : break;
7581 0 : Mnemonic = "v_mul_hi_i32_i24"; // "v_mul_hi_i32_i24_e32"
7582 0 : return;
7583 : case '6': // 1 string to match.
7584 0 : if (Mnemonic[19] != '4')
7585 : break;
7586 0 : Mnemonic = "v_mul_hi_i32_i24"; // "v_mul_hi_i32_i24_e64"
7587 0 : return;
7588 : }
7589 : break;
7590 : case 'u': // 2 strings to match.
7591 0 : if (memcmp(Mnemonic.data()+10, "32_u24_e", 8))
7592 : break;
7593 0 : switch (Mnemonic[18]) {
7594 : default: break;
7595 : case '3': // 1 string to match.
7596 0 : if (Mnemonic[19] != '2')
7597 : break;
7598 0 : Mnemonic = "v_mul_hi_u32_u24"; // "v_mul_hi_u32_u24_e32"
7599 0 : return;
7600 : case '6': // 1 string to match.
7601 0 : if (Mnemonic[19] != '4')
7602 : break;
7603 0 : Mnemonic = "v_mul_hi_u32_u24"; // "v_mul_hi_u32_u24_e64"
7604 0 : return;
7605 : }
7606 : break;
7607 : }
7608 : break;
7609 : case 'l': // 2 strings to match.
7610 8 : if (memcmp(Mnemonic.data()+7, "egacy_f32_e", 11))
7611 : break;
7612 16 : switch (Mnemonic[18]) {
7613 : default: break;
7614 : case '3': // 1 string to match.
7615 16 : if (Mnemonic[19] != '2')
7616 : break;
7617 8 : Mnemonic = "v_mul_legacy_f32"; // "v_mul_legacy_f32_e32"
7618 8 : return;
7619 : case '6': // 1 string to match.
7620 0 : if (Mnemonic[19] != '4')
7621 : break;
7622 0 : Mnemonic = "v_mul_legacy_f32"; // "v_mul_legacy_f32_e64"
7623 0 : return;
7624 : }
7625 : break;
7626 : }
7627 : break;
7628 : }
7629 : break;
7630 : case 'q': // 1 string to match.
7631 0 : if (memcmp(Mnemonic.data()+3, "sad_pk_u16_u8_e64", 17))
7632 : break;
7633 0 : if ((Features & Feature_isGCN) == Feature_isGCN) // "v_qsad_pk_u16_u8_e64"
7634 0 : Mnemonic = "v_qsad_pk_u16_u8";
7635 : return;
7636 : case 'r': // 4 strings to match.
7637 0 : switch (Mnemonic[3]) {
7638 : default: break;
7639 : case 'c': // 2 strings to match.
7640 0 : if (memcmp(Mnemonic.data()+4, "p_legacy_f32_e", 14))
7641 : break;
7642 0 : switch (Mnemonic[18]) {
7643 : default: break;
7644 : case '3': // 1 string to match.
7645 0 : if (Mnemonic[19] != '2')
7646 : break;
7647 0 : Mnemonic = "v_rcp_legacy_f32"; // "v_rcp_legacy_f32_e32"
7648 0 : return;
7649 : case '6': // 1 string to match.
7650 0 : if (Mnemonic[19] != '4')
7651 : break;
7652 0 : Mnemonic = "v_rcp_legacy_f32"; // "v_rcp_legacy_f32_e64"
7653 0 : return;
7654 : }
7655 : break;
7656 : case 's': // 2 strings to match.
7657 0 : if (memcmp(Mnemonic.data()+4, "q_legacy_f32_e", 14))
7658 : break;
7659 0 : switch (Mnemonic[18]) {
7660 : default: break;
7661 : case '3': // 1 string to match.
7662 0 : if (Mnemonic[19] != '2')
7663 : break;
7664 0 : Mnemonic = "v_rsq_legacy_f32"; // "v_rsq_legacy_f32_e32"
7665 0 : return;
7666 : case '6': // 1 string to match.
7667 0 : if (Mnemonic[19] != '4')
7668 : break;
7669 0 : Mnemonic = "v_rsq_legacy_f32"; // "v_rsq_legacy_f32_e64"
7670 0 : return;
7671 : }
7672 : break;
7673 : }
7674 : break;
7675 : case 't': // 1 string to match.
7676 0 : if (memcmp(Mnemonic.data()+3, "rig_preop_f64_e64", 17))
7677 : break;
7678 0 : Mnemonic = "v_trig_preop_f64"; // "v_trig_preop_f64_e64"
7679 0 : return;
7680 : }
7681 : break;
7682 : case 21: // 4 strings to match.
7683 4 : if (memcmp(Mnemonic.data()+0, "v_cvt_", 6))
7684 : break;
7685 0 : switch (Mnemonic[6]) {
7686 : default: break;
7687 : case 'f': // 2 strings to match.
7688 0 : if (memcmp(Mnemonic.data()+7, "lr_i32_f32_e", 12))
7689 : break;
7690 0 : switch (Mnemonic[19]) {
7691 : default: break;
7692 : case '3': // 1 string to match.
7693 0 : if (Mnemonic[20] != '2')
7694 : break;
7695 0 : Mnemonic = "v_cvt_flr_i32_f32"; // "v_cvt_flr_i32_f32_e32"
7696 0 : return;
7697 : case '6': // 1 string to match.
7698 0 : if (Mnemonic[20] != '4')
7699 : break;
7700 0 : Mnemonic = "v_cvt_flr_i32_f32"; // "v_cvt_flr_i32_f32_e64"
7701 0 : return;
7702 : }
7703 : break;
7704 : case 'r': // 2 strings to match.
7705 0 : if (memcmp(Mnemonic.data()+7, "pi_i32_f32_e", 12))
7706 : break;
7707 0 : switch (Mnemonic[19]) {
7708 : default: break;
7709 : case '3': // 1 string to match.
7710 0 : if (Mnemonic[20] != '2')
7711 : break;
7712 0 : Mnemonic = "v_cvt_rpi_i32_f32"; // "v_cvt_rpi_i32_f32_e32"
7713 0 : return;
7714 : case '6': // 1 string to match.
7715 0 : if (Mnemonic[20] != '4')
7716 : break;
7717 0 : Mnemonic = "v_cvt_rpi_i32_f32"; // "v_cvt_rpi_i32_f32_e64"
7718 0 : return;
7719 : }
7720 : break;
7721 : }
7722 : break;
7723 : case 22: // 4 strings to match.
7724 8 : if (memcmp(Mnemonic.data()+0, "v_mbcnt_", 8))
7725 : break;
7726 0 : switch (Mnemonic[8]) {
7727 : default: break;
7728 : case 'h': // 2 strings to match.
7729 0 : if (memcmp(Mnemonic.data()+9, "i_u32_b32_e", 11))
7730 : break;
7731 0 : switch (Mnemonic[20]) {
7732 : default: break;
7733 : case '3': // 1 string to match.
7734 0 : if (Mnemonic[21] != '2')
7735 : break;
7736 0 : Mnemonic = "v_mbcnt_hi_u32_b32"; // "v_mbcnt_hi_u32_b32_e32"
7737 0 : return;
7738 : case '6': // 1 string to match.
7739 0 : if (Mnemonic[21] != '4')
7740 : break;
7741 0 : Mnemonic = "v_mbcnt_hi_u32_b32"; // "v_mbcnt_hi_u32_b32_e64"
7742 0 : return;
7743 : }
7744 : break;
7745 : case 'l': // 2 strings to match.
7746 0 : if (memcmp(Mnemonic.data()+9, "o_u32_b32_e", 11))
7747 : break;
7748 0 : switch (Mnemonic[20]) {
7749 : default: break;
7750 : case '3': // 1 string to match.
7751 0 : if (Mnemonic[21] != '2')
7752 : break;
7753 0 : Mnemonic = "v_mbcnt_lo_u32_b32"; // "v_mbcnt_lo_u32_b32_e32"
7754 0 : return;
7755 : case '6': // 1 string to match.
7756 0 : if (Mnemonic[21] != '4')
7757 : break;
7758 0 : Mnemonic = "v_mbcnt_lo_u32_b32"; // "v_mbcnt_lo_u32_b32_e64"
7759 0 : return;
7760 : }
7761 : break;
7762 : }
7763 : break;
7764 : case 23: // 8 strings to match.
7765 4 : if (memcmp(Mnemonic.data()+0, "v_", 2))
7766 : break;
7767 0 : switch (Mnemonic[2]) {
7768 : default: break;
7769 : case 'c': // 2 strings to match.
7770 0 : if (memcmp(Mnemonic.data()+3, "vt_pkrtz_f16_f32_e", 18))
7771 : break;
7772 0 : switch (Mnemonic[21]) {
7773 : default: break;
7774 : case '3': // 1 string to match.
7775 0 : if (Mnemonic[22] != '2')
7776 : break;
7777 0 : Mnemonic = "v_cvt_pkrtz_f16_f32"; // "v_cvt_pkrtz_f16_f32_e32"
7778 0 : return;
7779 : case '6': // 1 string to match.
7780 0 : if (Mnemonic[22] != '4')
7781 : break;
7782 0 : Mnemonic = "v_cvt_pkrtz_f16_f32"; // "v_cvt_pkrtz_f16_f32_e64"
7783 0 : return;
7784 : }
7785 : break;
7786 : case 'f': // 6 strings to match.
7787 0 : if (memcmp(Mnemonic.data()+3, "rexp_exp_i", 10))
7788 : break;
7789 0 : switch (Mnemonic[13]) {
7790 : default: break;
7791 : case '1': // 2 strings to match.
7792 0 : if (memcmp(Mnemonic.data()+14, "6_f16_e", 7))
7793 : break;
7794 0 : switch (Mnemonic[21]) {
7795 : default: break;
7796 : case '3': // 1 string to match.
7797 0 : if (Mnemonic[22] != '2')
7798 : break;
7799 0 : Mnemonic = "v_frexp_exp_i16_f16"; // "v_frexp_exp_i16_f16_e32"
7800 0 : return;
7801 : case '6': // 1 string to match.
7802 0 : if (Mnemonic[22] != '4')
7803 : break;
7804 0 : Mnemonic = "v_frexp_exp_i16_f16"; // "v_frexp_exp_i16_f16_e64"
7805 0 : return;
7806 : }
7807 : break;
7808 : case '3': // 4 strings to match.
7809 0 : if (memcmp(Mnemonic.data()+14, "2_f", 3))
7810 : break;
7811 0 : switch (Mnemonic[17]) {
7812 : default: break;
7813 : case '3': // 2 strings to match.
7814 0 : if (memcmp(Mnemonic.data()+18, "2_e", 3))
7815 : break;
7816 0 : switch (Mnemonic[21]) {
7817 : default: break;
7818 : case '3': // 1 string to match.
7819 0 : if (Mnemonic[22] != '2')
7820 : break;
7821 0 : Mnemonic = "v_frexp_exp_i32_f32"; // "v_frexp_exp_i32_f32_e32"
7822 0 : return;
7823 : case '6': // 1 string to match.
7824 0 : if (Mnemonic[22] != '4')
7825 : break;
7826 0 : Mnemonic = "v_frexp_exp_i32_f32"; // "v_frexp_exp_i32_f32_e64"
7827 0 : return;
7828 : }
7829 : break;
7830 : case '6': // 2 strings to match.
7831 0 : if (memcmp(Mnemonic.data()+18, "4_e", 3))
7832 : break;
7833 0 : switch (Mnemonic[21]) {
7834 : default: break;
7835 : case '3': // 1 string to match.
7836 0 : if (Mnemonic[22] != '2')
7837 : break;
7838 0 : Mnemonic = "v_frexp_exp_i32_f64"; // "v_frexp_exp_i32_f64_e32"
7839 0 : return;
7840 : case '6': // 1 string to match.
7841 0 : if (Mnemonic[22] != '4')
7842 : break;
7843 0 : Mnemonic = "v_frexp_exp_i32_f64"; // "v_frexp_exp_i32_f64_e64"
7844 0 : return;
7845 : }
7846 : break;
7847 : }
7848 : break;
7849 : }
7850 : break;
7851 : }
7852 : break;
7853 : case 24: // 6 strings to match.
7854 2 : if (memcmp(Mnemonic.data()+0, "v_cvt_pk", 8))
7855 : break;
7856 0 : switch (Mnemonic[8]) {
7857 : default: break;
7858 : case 'a': // 2 strings to match.
7859 0 : if (memcmp(Mnemonic.data()+9, "ccum_u8_f32_e", 13))
7860 : break;
7861 0 : switch (Mnemonic[22]) {
7862 : default: break;
7863 : case '3': // 1 string to match.
7864 0 : if (Mnemonic[23] != '2')
7865 : break;
7866 0 : Mnemonic = "v_cvt_pkaccum_u8_f32"; // "v_cvt_pkaccum_u8_f32_e32"
7867 0 : return;
7868 : case '6': // 1 string to match.
7869 0 : if (Mnemonic[23] != '4')
7870 : break;
7871 0 : Mnemonic = "v_cvt_pkaccum_u8_f32"; // "v_cvt_pkaccum_u8_f32_e64"
7872 0 : return;
7873 : }
7874 : break;
7875 : case 'n': // 4 strings to match.
7876 0 : if (memcmp(Mnemonic.data()+9, "orm_", 4))
7877 : break;
7878 0 : switch (Mnemonic[13]) {
7879 : default: break;
7880 : case 'i': // 2 strings to match.
7881 0 : if (memcmp(Mnemonic.data()+14, "16_f32_e", 8))
7882 : break;
7883 0 : switch (Mnemonic[22]) {
7884 : default: break;
7885 : case '3': // 1 string to match.
7886 0 : if (Mnemonic[23] != '2')
7887 : break;
7888 0 : Mnemonic = "v_cvt_pknorm_i16_f32"; // "v_cvt_pknorm_i16_f32_e32"
7889 0 : return;
7890 : case '6': // 1 string to match.
7891 0 : if (Mnemonic[23] != '4')
7892 : break;
7893 0 : Mnemonic = "v_cvt_pknorm_i16_f32"; // "v_cvt_pknorm_i16_f32_e64"
7894 0 : return;
7895 : }
7896 : break;
7897 : case 'u': // 2 strings to match.
7898 0 : if (memcmp(Mnemonic.data()+14, "16_f32_e", 8))
7899 : break;
7900 0 : switch (Mnemonic[22]) {
7901 : default: break;
7902 : case '3': // 1 string to match.
7903 0 : if (Mnemonic[23] != '2')
7904 : break;
7905 0 : Mnemonic = "v_cvt_pknorm_u16_f32"; // "v_cvt_pknorm_u16_f32_e32"
7906 0 : return;
7907 : case '6': // 1 string to match.
7908 0 : if (Mnemonic[23] != '4')
7909 : break;
7910 0 : Mnemonic = "v_cvt_pknorm_u16_f32"; // "v_cvt_pknorm_u16_f32_e64"
7911 0 : return;
7912 : }
7913 : break;
7914 : }
7915 : break;
7916 : }
7917 : break;
7918 : }
7919 : break;
7920 : }
7921 2092 : switch (Mnemonic.size()) {
7922 : default: break;
7923 : case 9: // 3 strings to match.
7924 490 : if (memcmp(Mnemonic.data()+0, "v_", 2))
7925 : break;
7926 748 : switch (Mnemonic[2]) {
7927 : default: break;
7928 : case 'a': // 1 string to match.
7929 74 : if (memcmp(Mnemonic.data()+3, "dd_u32", 6))
7930 : break;
7931 0 : if ((Features & Feature_isGCN) == Feature_isGCN) // "v_add_u32"
7932 0 : Mnemonic = "v_add_i32";
7933 : return;
7934 : case 'n': // 1 string to match.
7935 8 : if (memcmp(Mnemonic.data()+3, "op_e32", 6))
7936 : break;
7937 0 : Mnemonic = "v_nop"; // "v_nop_e32"
7938 0 : return;
7939 : case 's': // 1 string to match.
7940 50 : if (memcmp(Mnemonic.data()+3, "ub_u32", 6))
7941 : break;
7942 0 : if ((Features & Feature_isGCN) == Feature_isGCN) // "v_sub_u32"
7943 0 : Mnemonic = "v_sub_i32";
7944 : return;
7945 : }
7946 : break;
7947 : case 12: // 3 strings to match.
7948 126 : if (memcmp(Mnemonic.data()+0, "v_", 2))
7949 : break;
7950 164 : switch (Mnemonic[2]) {
7951 : default: break;
7952 : case 'o': // 2 strings to match.
7953 0 : if (memcmp(Mnemonic.data()+3, "r_b32_e", 7))
7954 : break;
7955 0 : switch (Mnemonic[10]) {
7956 : default: break;
7957 : case '3': // 1 string to match.
7958 0 : if (Mnemonic[11] != '2')
7959 : break;
7960 0 : Mnemonic = "v_or_b32"; // "v_or_b32_e32"
7961 0 : return;
7962 : case '6': // 1 string to match.
7963 0 : if (Mnemonic[11] != '4')
7964 : break;
7965 0 : Mnemonic = "v_or_b32"; // "v_or_b32_e64"
7966 0 : return;
7967 : }
7968 : break;
7969 : case 's': // 1 string to match.
7970 34 : if (memcmp(Mnemonic.data()+3, "ubrev_u32", 9))
7971 : break;
7972 0 : if ((Features & Feature_isGCN) == Feature_isGCN) // "v_subrev_u32"
7973 0 : Mnemonic = "v_subrev_i32";
7974 : return;
7975 : }
7976 : break;
7977 : case 13: // 98 strings to match.
7978 408 : if (memcmp(Mnemonic.data()+0, "v_", 2))
7979 : break;
7980 652 : switch (Mnemonic[2]) {
7981 : default: break;
7982 : case 'a': // 11 strings to match.
7983 32 : switch (Mnemonic[3]) {
7984 : default: break;
7985 : case 'd': // 9 strings to match.
7986 0 : if (memcmp(Mnemonic.data()+4, "d_", 2))
7987 : break;
7988 0 : switch (Mnemonic[6]) {
7989 : default: break;
7990 : case 'f': // 5 strings to match.
7991 0 : switch (Mnemonic[7]) {
7992 : default: break;
7993 : case '1': // 2 strings to match.
7994 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
7995 : break;
7996 0 : switch (Mnemonic[11]) {
7997 : default: break;
7998 : case '3': // 1 string to match.
7999 0 : if (Mnemonic[12] != '2')
8000 : break;
8001 0 : Mnemonic = "v_add_f16"; // "v_add_f16_e32"
8002 0 : return;
8003 : case '6': // 1 string to match.
8004 0 : if (Mnemonic[12] != '4')
8005 : break;
8006 0 : Mnemonic = "v_add_f16"; // "v_add_f16_e64"
8007 0 : return;
8008 : }
8009 : break;
8010 : case '3': // 2 strings to match.
8011 0 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
8012 : break;
8013 0 : switch (Mnemonic[11]) {
8014 : default: break;
8015 : case '3': // 1 string to match.
8016 0 : if (Mnemonic[12] != '2')
8017 : break;
8018 0 : Mnemonic = "v_add_f32"; // "v_add_f32_e32"
8019 0 : return;
8020 : case '6': // 1 string to match.
8021 0 : if (Mnemonic[12] != '4')
8022 : break;
8023 0 : Mnemonic = "v_add_f32"; // "v_add_f32_e64"
8024 0 : return;
8025 : }
8026 : break;
8027 : case '6': // 1 string to match.
8028 0 : if (memcmp(Mnemonic.data()+8, "4_e64", 5))
8029 : break;
8030 0 : Mnemonic = "v_add_f64"; // "v_add_f64_e64"
8031 0 : return;
8032 : }
8033 : break;
8034 : case 'i': // 2 strings to match.
8035 0 : if (memcmp(Mnemonic.data()+7, "32_e", 4))
8036 : break;
8037 0 : switch (Mnemonic[11]) {
8038 : default: break;
8039 : case '3': // 1 string to match.
8040 0 : if (Mnemonic[12] != '2')
8041 : break;
8042 0 : Mnemonic = "v_add_i32"; // "v_add_i32_e32"
8043 0 : return;
8044 : case '6': // 1 string to match.
8045 0 : if (Mnemonic[12] != '4')
8046 : break;
8047 0 : Mnemonic = "v_add_i32"; // "v_add_i32_e64"
8048 0 : return;
8049 : }
8050 : break;
8051 : case 'u': // 2 strings to match.
8052 0 : if (memcmp(Mnemonic.data()+7, "16_e", 4))
8053 : break;
8054 0 : switch (Mnemonic[11]) {
8055 : default: break;
8056 : case '3': // 1 string to match.
8057 0 : if (Mnemonic[12] != '2')
8058 : break;
8059 0 : Mnemonic = "v_add_u16"; // "v_add_u16_e32"
8060 0 : return;
8061 : case '6': // 1 string to match.
8062 0 : if (Mnemonic[12] != '4')
8063 : break;
8064 0 : Mnemonic = "v_add_u16"; // "v_add_u16_e64"
8065 0 : return;
8066 : }
8067 : break;
8068 : }
8069 : break;
8070 : case 'n': // 2 strings to match.
8071 0 : if (memcmp(Mnemonic.data()+4, "d_b32_e", 7))
8072 : break;
8073 0 : switch (Mnemonic[11]) {
8074 : default: break;
8075 : case '3': // 1 string to match.
8076 0 : if (Mnemonic[12] != '2')
8077 : break;
8078 0 : Mnemonic = "v_and_b32"; // "v_and_b32_e32"
8079 0 : return;
8080 : case '6': // 1 string to match.
8081 0 : if (Mnemonic[12] != '4')
8082 : break;
8083 0 : Mnemonic = "v_and_b32"; // "v_and_b32_e64"
8084 0 : return;
8085 : }
8086 : break;
8087 : }
8088 : break;
8089 : case 'b': // 5 strings to match.
8090 0 : if (Mnemonic[3] != 'f')
8091 : break;
8092 0 : switch (Mnemonic[4]) {
8093 : default: break;
8094 : case 'e': // 2 strings to match.
8095 0 : if (Mnemonic[5] != '_')
8096 : break;
8097 0 : switch (Mnemonic[6]) {
8098 : default: break;
8099 : case 'i': // 1 string to match.
8100 0 : if (memcmp(Mnemonic.data()+7, "32_e64", 6))
8101 : break;
8102 0 : Mnemonic = "v_bfe_i32"; // "v_bfe_i32_e64"
8103 0 : return;
8104 : case 'u': // 1 string to match.
8105 0 : if (memcmp(Mnemonic.data()+7, "32_e64", 6))
8106 : break;
8107 0 : Mnemonic = "v_bfe_u32"; // "v_bfe_u32_e64"
8108 0 : return;
8109 : }
8110 : break;
8111 : case 'i': // 1 string to match.
8112 0 : if (memcmp(Mnemonic.data()+5, "_b32_e64", 8))
8113 : break;
8114 0 : Mnemonic = "v_bfi_b32"; // "v_bfi_b32_e64"
8115 0 : return;
8116 : case 'm': // 2 strings to match.
8117 0 : if (memcmp(Mnemonic.data()+5, "_b32_e", 6))
8118 : break;
8119 0 : switch (Mnemonic[11]) {
8120 : default: break;
8121 : case '3': // 1 string to match.
8122 0 : if (Mnemonic[12] != '2')
8123 : break;
8124 0 : Mnemonic = "v_bfm_b32"; // "v_bfm_b32_e32"
8125 0 : return;
8126 : case '6': // 1 string to match.
8127 0 : if (Mnemonic[12] != '4')
8128 : break;
8129 0 : Mnemonic = "v_bfm_b32"; // "v_bfm_b32_e64"
8130 0 : return;
8131 : }
8132 : break;
8133 : }
8134 : break;
8135 : case 'c': // 5 strings to match.
8136 276 : switch (Mnemonic[3]) {
8137 : default: break;
8138 : case 'l': // 1 string to match.
8139 0 : if (memcmp(Mnemonic.data()+4, "rexcp_e32", 9))
8140 : break;
8141 0 : Mnemonic = "v_clrexcp"; // "v_clrexcp_e32"
8142 0 : return;
8143 : case 'o': // 4 strings to match.
8144 0 : if (memcmp(Mnemonic.data()+4, "s_f", 3))
8145 : break;
8146 0 : switch (Mnemonic[7]) {
8147 : default: break;
8148 : case '1': // 2 strings to match.
8149 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
8150 : break;
8151 0 : switch (Mnemonic[11]) {
8152 : default: break;
8153 : case '3': // 1 string to match.
8154 0 : if (Mnemonic[12] != '2')
8155 : break;
8156 0 : Mnemonic = "v_cos_f16"; // "v_cos_f16_e32"
8157 0 : return;
8158 : case '6': // 1 string to match.
8159 0 : if (Mnemonic[12] != '4')
8160 : break;
8161 0 : Mnemonic = "v_cos_f16"; // "v_cos_f16_e64"
8162 0 : return;
8163 : }
8164 : break;
8165 : case '3': // 2 strings to match.
8166 0 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
8167 : break;
8168 0 : switch (Mnemonic[11]) {
8169 : default: break;
8170 : case '3': // 1 string to match.
8171 0 : if (Mnemonic[12] != '2')
8172 : break;
8173 0 : Mnemonic = "v_cos_f32"; // "v_cos_f32_e32"
8174 0 : return;
8175 : case '6': // 1 string to match.
8176 0 : if (Mnemonic[12] != '4')
8177 : break;
8178 0 : Mnemonic = "v_cos_f32"; // "v_cos_f32_e64"
8179 0 : return;
8180 : }
8181 : break;
8182 : }
8183 : break;
8184 : }
8185 : break;
8186 : case 'e': // 4 strings to match.
8187 0 : if (memcmp(Mnemonic.data()+3, "xp_f", 4))
8188 : break;
8189 0 : switch (Mnemonic[7]) {
8190 : default: break;
8191 : case '1': // 2 strings to match.
8192 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
8193 : break;
8194 0 : switch (Mnemonic[11]) {
8195 : default: break;
8196 : case '3': // 1 string to match.
8197 0 : if (Mnemonic[12] != '2')
8198 : break;
8199 0 : Mnemonic = "v_exp_f16"; // "v_exp_f16_e32"
8200 0 : return;
8201 : case '6': // 1 string to match.
8202 0 : if (Mnemonic[12] != '4')
8203 : break;
8204 0 : Mnemonic = "v_exp_f16"; // "v_exp_f16_e64"
8205 0 : return;
8206 : }
8207 : break;
8208 : case '3': // 2 strings to match.
8209 0 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
8210 : break;
8211 0 : switch (Mnemonic[11]) {
8212 : default: break;
8213 : case '3': // 1 string to match.
8214 0 : if (Mnemonic[12] != '2')
8215 : break;
8216 0 : Mnemonic = "v_exp_f32"; // "v_exp_f32_e32"
8217 0 : return;
8218 : case '6': // 1 string to match.
8219 0 : if (Mnemonic[12] != '4')
8220 : break;
8221 0 : Mnemonic = "v_exp_f32"; // "v_exp_f32_e64"
8222 0 : return;
8223 : }
8224 : break;
8225 : }
8226 : break;
8227 : case 'f': // 2 strings to match.
8228 0 : if (memcmp(Mnemonic.data()+3, "ma_f", 4))
8229 : break;
8230 0 : switch (Mnemonic[7]) {
8231 : default: break;
8232 : case '3': // 1 string to match.
8233 0 : if (memcmp(Mnemonic.data()+8, "2_e64", 5))
8234 : break;
8235 0 : Mnemonic = "v_fma_f32"; // "v_fma_f32_e64"
8236 0 : return;
8237 : case '6': // 1 string to match.
8238 0 : if (memcmp(Mnemonic.data()+8, "4_e64", 5))
8239 : break;
8240 0 : Mnemonic = "v_fma_f64"; // "v_fma_f64_e64"
8241 0 : return;
8242 : }
8243 : break;
8244 : case 'l': // 4 strings to match.
8245 32 : if (memcmp(Mnemonic.data()+3, "og_f", 4))
8246 : break;
8247 0 : switch (Mnemonic[7]) {
8248 : default: break;
8249 : case '1': // 2 strings to match.
8250 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
8251 : break;
8252 0 : switch (Mnemonic[11]) {
8253 : default: break;
8254 : case '3': // 1 string to match.
8255 0 : if (Mnemonic[12] != '2')
8256 : break;
8257 0 : Mnemonic = "v_log_f16"; // "v_log_f16_e32"
8258 0 : return;
8259 : case '6': // 1 string to match.
8260 0 : if (Mnemonic[12] != '4')
8261 : break;
8262 0 : Mnemonic = "v_log_f16"; // "v_log_f16_e64"
8263 0 : return;
8264 : }
8265 : break;
8266 : case '3': // 2 strings to match.
8267 0 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
8268 : break;
8269 0 : switch (Mnemonic[11]) {
8270 : default: break;
8271 : case '3': // 1 string to match.
8272 0 : if (Mnemonic[12] != '2')
8273 : break;
8274 0 : Mnemonic = "v_log_f32"; // "v_log_f32_e32"
8275 0 : return;
8276 : case '6': // 1 string to match.
8277 0 : if (Mnemonic[12] != '4')
8278 : break;
8279 0 : Mnemonic = "v_log_f32"; // "v_log_f32_e64"
8280 0 : return;
8281 : }
8282 : break;
8283 : }
8284 : break;
8285 : case 'm': // 38 strings to match.
8286 264 : switch (Mnemonic[3]) {
8287 : default: break;
8288 : case 'a': // 18 strings to match.
8289 0 : switch (Mnemonic[4]) {
8290 : default: break;
8291 : case 'c': // 4 strings to match.
8292 0 : if (memcmp(Mnemonic.data()+5, "_f", 2))
8293 : break;
8294 0 : switch (Mnemonic[7]) {
8295 : default: break;
8296 : case '1': // 2 strings to match.
8297 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
8298 : break;
8299 0 : switch (Mnemonic[11]) {
8300 : default: break;
8301 : case '3': // 1 string to match.
8302 0 : if (Mnemonic[12] != '2')
8303 : break;
8304 0 : Mnemonic = "v_mac_f16"; // "v_mac_f16_e32"
8305 0 : return;
8306 : case '6': // 1 string to match.
8307 0 : if (Mnemonic[12] != '4')
8308 : break;
8309 0 : Mnemonic = "v_mac_f16"; // "v_mac_f16_e64"
8310 0 : return;
8311 : }
8312 : break;
8313 : case '3': // 2 strings to match.
8314 0 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
8315 : break;
8316 0 : switch (Mnemonic[11]) {
8317 : default: break;
8318 : case '3': // 1 string to match.
8319 0 : if (Mnemonic[12] != '2')
8320 : break;
8321 0 : Mnemonic = "v_mac_f32"; // "v_mac_f32_e32"
8322 0 : return;
8323 : case '6': // 1 string to match.
8324 0 : if (Mnemonic[12] != '4')
8325 : break;
8326 0 : Mnemonic = "v_mac_f32"; // "v_mac_f32_e64"
8327 0 : return;
8328 : }
8329 : break;
8330 : }
8331 : break;
8332 : case 'd': // 1 string to match.
8333 0 : if (memcmp(Mnemonic.data()+5, "_f32_e64", 8))
8334 : break;
8335 0 : Mnemonic = "v_mad_f32"; // "v_mad_f32_e64"
8336 0 : return;
8337 : case 'x': // 13 strings to match.
8338 0 : if (Mnemonic[5] != '_')
8339 : break;
8340 0 : switch (Mnemonic[6]) {
8341 : default: break;
8342 : case 'f': // 5 strings to match.
8343 0 : switch (Mnemonic[7]) {
8344 : default: break;
8345 : case '1': // 2 strings to match.
8346 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
8347 : break;
8348 0 : switch (Mnemonic[11]) {
8349 : default: break;
8350 : case '3': // 1 string to match.
8351 0 : if (Mnemonic[12] != '2')
8352 : break;
8353 0 : Mnemonic = "v_max_f16"; // "v_max_f16_e32"
8354 0 : return;
8355 : case '6': // 1 string to match.
8356 0 : if (Mnemonic[12] != '4')
8357 : break;
8358 0 : Mnemonic = "v_max_f16"; // "v_max_f16_e64"
8359 0 : return;
8360 : }
8361 : break;
8362 : case '3': // 2 strings to match.
8363 0 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
8364 : break;
8365 0 : switch (Mnemonic[11]) {
8366 : default: break;
8367 : case '3': // 1 string to match.
8368 0 : if (Mnemonic[12] != '2')
8369 : break;
8370 0 : Mnemonic = "v_max_f32"; // "v_max_f32_e32"
8371 0 : return;
8372 : case '6': // 1 string to match.
8373 0 : if (Mnemonic[12] != '4')
8374 : break;
8375 0 : Mnemonic = "v_max_f32"; // "v_max_f32_e64"
8376 0 : return;
8377 : }
8378 : break;
8379 : case '6': // 1 string to match.
8380 0 : if (memcmp(Mnemonic.data()+8, "4_e64", 5))
8381 : break;
8382 0 : Mnemonic = "v_max_f64"; // "v_max_f64_e64"
8383 0 : return;
8384 : }
8385 : break;
8386 : case 'i': // 4 strings to match.
8387 0 : switch (Mnemonic[7]) {
8388 : default: break;
8389 : case '1': // 2 strings to match.
8390 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
8391 : break;
8392 0 : switch (Mnemonic[11]) {
8393 : default: break;
8394 : case '3': // 1 string to match.
8395 0 : if (Mnemonic[12] != '2')
8396 : break;
8397 0 : Mnemonic = "v_max_i16"; // "v_max_i16_e32"
8398 0 : return;
8399 : case '6': // 1 string to match.
8400 0 : if (Mnemonic[12] != '4')
8401 : break;
8402 0 : Mnemonic = "v_max_i16"; // "v_max_i16_e64"
8403 0 : return;
8404 : }
8405 : break;
8406 : case '3': // 2 strings to match.
8407 0 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
8408 : break;
8409 0 : switch (Mnemonic[11]) {
8410 : default: break;
8411 : case '3': // 1 string to match.
8412 0 : if (Mnemonic[12] != '2')
8413 : break;
8414 0 : Mnemonic = "v_max_i32"; // "v_max_i32_e32"
8415 0 : return;
8416 : case '6': // 1 string to match.
8417 0 : if (Mnemonic[12] != '4')
8418 : break;
8419 0 : Mnemonic = "v_max_i32"; // "v_max_i32_e64"
8420 0 : return;
8421 : }
8422 : break;
8423 : }
8424 : break;
8425 : case 'u': // 4 strings to match.
8426 0 : switch (Mnemonic[7]) {
8427 : default: break;
8428 : case '1': // 2 strings to match.
8429 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
8430 : break;
8431 0 : switch (Mnemonic[11]) {
8432 : default: break;
8433 : case '3': // 1 string to match.
8434 0 : if (Mnemonic[12] != '2')
8435 : break;
8436 0 : Mnemonic = "v_max_u16"; // "v_max_u16_e32"
8437 0 : return;
8438 : case '6': // 1 string to match.
8439 0 : if (Mnemonic[12] != '4')
8440 : break;
8441 0 : Mnemonic = "v_max_u16"; // "v_max_u16_e64"
8442 0 : return;
8443 : }
8444 : break;
8445 : case '3': // 2 strings to match.
8446 0 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
8447 : break;
8448 0 : switch (Mnemonic[11]) {
8449 : default: break;
8450 : case '3': // 1 string to match.
8451 0 : if (Mnemonic[12] != '2')
8452 : break;
8453 0 : Mnemonic = "v_max_u32"; // "v_max_u32_e32"
8454 0 : return;
8455 : case '6': // 1 string to match.
8456 0 : if (Mnemonic[12] != '4')
8457 : break;
8458 0 : Mnemonic = "v_max_u32"; // "v_max_u32_e64"
8459 0 : return;
8460 : }
8461 : break;
8462 : }
8463 : break;
8464 : }
8465 : break;
8466 : }
8467 : break;
8468 : case 'i': // 13 strings to match.
8469 0 : if (memcmp(Mnemonic.data()+4, "n_", 2))
8470 : break;
8471 0 : switch (Mnemonic[6]) {
8472 : default: break;
8473 : case 'f': // 5 strings to match.
8474 0 : switch (Mnemonic[7]) {
8475 : default: break;
8476 : case '1': // 2 strings to match.
8477 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
8478 : break;
8479 0 : switch (Mnemonic[11]) {
8480 : default: break;
8481 : case '3': // 1 string to match.
8482 0 : if (Mnemonic[12] != '2')
8483 : break;
8484 0 : Mnemonic = "v_min_f16"; // "v_min_f16_e32"
8485 0 : return;
8486 : case '6': // 1 string to match.
8487 0 : if (Mnemonic[12] != '4')
8488 : break;
8489 0 : Mnemonic = "v_min_f16"; // "v_min_f16_e64"
8490 0 : return;
8491 : }
8492 : break;
8493 : case '3': // 2 strings to match.
8494 0 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
8495 : break;
8496 0 : switch (Mnemonic[11]) {
8497 : default: break;
8498 : case '3': // 1 string to match.
8499 0 : if (Mnemonic[12] != '2')
8500 : break;
8501 0 : Mnemonic = "v_min_f32"; // "v_min_f32_e32"
8502 0 : return;
8503 : case '6': // 1 string to match.
8504 0 : if (Mnemonic[12] != '4')
8505 : break;
8506 0 : Mnemonic = "v_min_f32"; // "v_min_f32_e64"
8507 0 : return;
8508 : }
8509 : break;
8510 : case '6': // 1 string to match.
8511 0 : if (memcmp(Mnemonic.data()+8, "4_e64", 5))
8512 : break;
8513 0 : Mnemonic = "v_min_f64"; // "v_min_f64_e64"
8514 0 : return;
8515 : }
8516 : break;
8517 : case 'i': // 4 strings to match.
8518 0 : switch (Mnemonic[7]) {
8519 : default: break;
8520 : case '1': // 2 strings to match.
8521 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
8522 : break;
8523 0 : switch (Mnemonic[11]) {
8524 : default: break;
8525 : case '3': // 1 string to match.
8526 0 : if (Mnemonic[12] != '2')
8527 : break;
8528 0 : Mnemonic = "v_min_i16"; // "v_min_i16_e32"
8529 0 : return;
8530 : case '6': // 1 string to match.
8531 0 : if (Mnemonic[12] != '4')
8532 : break;
8533 0 : Mnemonic = "v_min_i16"; // "v_min_i16_e64"
8534 0 : return;
8535 : }
8536 : break;
8537 : case '3': // 2 strings to match.
8538 0 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
8539 : break;
8540 0 : switch (Mnemonic[11]) {
8541 : default: break;
8542 : case '3': // 1 string to match.
8543 0 : if (Mnemonic[12] != '2')
8544 : break;
8545 0 : Mnemonic = "v_min_i32"; // "v_min_i32_e32"
8546 0 : return;
8547 : case '6': // 1 string to match.
8548 0 : if (Mnemonic[12] != '4')
8549 : break;
8550 0 : Mnemonic = "v_min_i32"; // "v_min_i32_e64"
8551 0 : return;
8552 : }
8553 : break;
8554 : }
8555 : break;
8556 : case 'u': // 4 strings to match.
8557 0 : switch (Mnemonic[7]) {
8558 : default: break;
8559 : case '1': // 2 strings to match.
8560 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
8561 : break;
8562 0 : switch (Mnemonic[11]) {
8563 : default: break;
8564 : case '3': // 1 string to match.
8565 0 : if (Mnemonic[12] != '2')
8566 : break;
8567 0 : Mnemonic = "v_min_u16"; // "v_min_u16_e32"
8568 0 : return;
8569 : case '6': // 1 string to match.
8570 0 : if (Mnemonic[12] != '4')
8571 : break;
8572 0 : Mnemonic = "v_min_u16"; // "v_min_u16_e64"
8573 0 : return;
8574 : }
8575 : break;
8576 : case '3': // 2 strings to match.
8577 0 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
8578 : break;
8579 0 : switch (Mnemonic[11]) {
8580 : default: break;
8581 : case '3': // 1 string to match.
8582 0 : if (Mnemonic[12] != '2')
8583 : break;
8584 0 : Mnemonic = "v_min_u32"; // "v_min_u32_e32"
8585 0 : return;
8586 : case '6': // 1 string to match.
8587 0 : if (Mnemonic[12] != '4')
8588 : break;
8589 0 : Mnemonic = "v_min_u32"; // "v_min_u32_e64"
8590 0 : return;
8591 : }
8592 : break;
8593 : }
8594 : break;
8595 : }
8596 : break;
8597 : case 'o': // 2 strings to match.
8598 24 : if (memcmp(Mnemonic.data()+4, "v_b32_e", 7))
8599 : break;
8600 0 : switch (Mnemonic[11]) {
8601 : default: break;
8602 : case '3': // 1 string to match.
8603 0 : if (Mnemonic[12] != '2')
8604 : break;
8605 0 : Mnemonic = "v_mov_b32"; // "v_mov_b32_e32"
8606 0 : return;
8607 : case '6': // 1 string to match.
8608 0 : if (Mnemonic[12] != '4')
8609 : break;
8610 0 : Mnemonic = "v_mov_b32"; // "v_mov_b32_e64"
8611 0 : return;
8612 : }
8613 : break;
8614 : case 'u': // 5 strings to match.
8615 108 : if (memcmp(Mnemonic.data()+4, "l_f", 3))
8616 : break;
8617 0 : switch (Mnemonic[7]) {
8618 : default: break;
8619 : case '1': // 2 strings to match.
8620 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
8621 : break;
8622 0 : switch (Mnemonic[11]) {
8623 : default: break;
8624 : case '3': // 1 string to match.
8625 0 : if (Mnemonic[12] != '2')
8626 : break;
8627 0 : Mnemonic = "v_mul_f16"; // "v_mul_f16_e32"
8628 0 : return;
8629 : case '6': // 1 string to match.
8630 0 : if (Mnemonic[12] != '4')
8631 : break;
8632 0 : Mnemonic = "v_mul_f16"; // "v_mul_f16_e64"
8633 0 : return;
8634 : }
8635 : break;
8636 : case '3': // 2 strings to match.
8637 0 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
8638 : break;
8639 0 : switch (Mnemonic[11]) {
8640 : default: break;
8641 : case '3': // 1 string to match.
8642 0 : if (Mnemonic[12] != '2')
8643 : break;
8644 0 : Mnemonic = "v_mul_f32"; // "v_mul_f32_e32"
8645 0 : return;
8646 : case '6': // 1 string to match.
8647 0 : if (Mnemonic[12] != '4')
8648 : break;
8649 0 : Mnemonic = "v_mul_f32"; // "v_mul_f32_e64"
8650 0 : return;
8651 : }
8652 : break;
8653 : case '6': // 1 string to match.
8654 0 : if (memcmp(Mnemonic.data()+8, "4_e64", 5))
8655 : break;
8656 0 : Mnemonic = "v_mul_f64"; // "v_mul_f64_e64"
8657 0 : return;
8658 : }
8659 : break;
8660 : }
8661 : break;
8662 : case 'n': // 2 strings to match.
8663 0 : if (memcmp(Mnemonic.data()+3, "ot_b32_e", 8))
8664 : break;
8665 0 : switch (Mnemonic[11]) {
8666 : default: break;
8667 : case '3': // 1 string to match.
8668 0 : if (Mnemonic[12] != '2')
8669 : break;
8670 0 : Mnemonic = "v_not_b32"; // "v_not_b32_e32"
8671 0 : return;
8672 : case '6': // 1 string to match.
8673 0 : if (Mnemonic[12] != '4')
8674 : break;
8675 0 : Mnemonic = "v_not_b32"; // "v_not_b32_e64"
8676 0 : return;
8677 : }
8678 : break;
8679 : case 'r': // 12 strings to match.
8680 0 : switch (Mnemonic[3]) {
8681 : default: break;
8682 : case 'c': // 6 strings to match.
8683 0 : if (memcmp(Mnemonic.data()+4, "p_f", 3))
8684 : break;
8685 0 : switch (Mnemonic[7]) {
8686 : default: break;
8687 : case '1': // 2 strings to match.
8688 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
8689 : break;
8690 0 : switch (Mnemonic[11]) {
8691 : default: break;
8692 : case '3': // 1 string to match.
8693 0 : if (Mnemonic[12] != '2')
8694 : break;
8695 0 : Mnemonic = "v_rcp_f16"; // "v_rcp_f16_e32"
8696 0 : return;
8697 : case '6': // 1 string to match.
8698 0 : if (Mnemonic[12] != '4')
8699 : break;
8700 0 : Mnemonic = "v_rcp_f16"; // "v_rcp_f16_e64"
8701 0 : return;
8702 : }
8703 : break;
8704 : case '3': // 2 strings to match.
8705 0 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
8706 : break;
8707 0 : switch (Mnemonic[11]) {
8708 : default: break;
8709 : case '3': // 1 string to match.
8710 0 : if (Mnemonic[12] != '2')
8711 : break;
8712 0 : Mnemonic = "v_rcp_f32"; // "v_rcp_f32_e32"
8713 0 : return;
8714 : case '6': // 1 string to match.
8715 0 : if (Mnemonic[12] != '4')
8716 : break;
8717 0 : Mnemonic = "v_rcp_f32"; // "v_rcp_f32_e64"
8718 0 : return;
8719 : }
8720 : break;
8721 : case '6': // 2 strings to match.
8722 0 : if (memcmp(Mnemonic.data()+8, "4_e", 3))
8723 : break;
8724 0 : switch (Mnemonic[11]) {
8725 : default: break;
8726 : case '3': // 1 string to match.
8727 0 : if (Mnemonic[12] != '2')
8728 : break;
8729 0 : Mnemonic = "v_rcp_f64"; // "v_rcp_f64_e32"
8730 0 : return;
8731 : case '6': // 1 string to match.
8732 0 : if (Mnemonic[12] != '4')
8733 : break;
8734 0 : Mnemonic = "v_rcp_f64"; // "v_rcp_f64_e64"
8735 0 : return;
8736 : }
8737 : break;
8738 : }
8739 : break;
8740 : case 's': // 6 strings to match.
8741 0 : if (memcmp(Mnemonic.data()+4, "q_f", 3))
8742 : break;
8743 0 : switch (Mnemonic[7]) {
8744 : default: break;
8745 : case '1': // 2 strings to match.
8746 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
8747 : break;
8748 0 : switch (Mnemonic[11]) {
8749 : default: break;
8750 : case '3': // 1 string to match.
8751 0 : if (Mnemonic[12] != '2')
8752 : break;
8753 0 : Mnemonic = "v_rsq_f16"; // "v_rsq_f16_e32"
8754 0 : return;
8755 : case '6': // 1 string to match.
8756 0 : if (Mnemonic[12] != '4')
8757 : break;
8758 0 : Mnemonic = "v_rsq_f16"; // "v_rsq_f16_e64"
8759 0 : return;
8760 : }
8761 : break;
8762 : case '3': // 2 strings to match.
8763 0 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
8764 : break;
8765 0 : switch (Mnemonic[11]) {
8766 : default: break;
8767 : case '3': // 1 string to match.
8768 0 : if (Mnemonic[12] != '2')
8769 : break;
8770 0 : Mnemonic = "v_rsq_f32"; // "v_rsq_f32_e32"
8771 0 : return;
8772 : case '6': // 1 string to match.
8773 0 : if (Mnemonic[12] != '4')
8774 : break;
8775 0 : Mnemonic = "v_rsq_f32"; // "v_rsq_f32_e64"
8776 0 : return;
8777 : }
8778 : break;
8779 : case '6': // 2 strings to match.
8780 0 : if (memcmp(Mnemonic.data()+8, "4_e", 3))
8781 : break;
8782 0 : switch (Mnemonic[11]) {
8783 : default: break;
8784 : case '3': // 1 string to match.
8785 0 : if (Mnemonic[12] != '2')
8786 : break;
8787 0 : Mnemonic = "v_rsq_f64"; // "v_rsq_f64_e32"
8788 0 : return;
8789 : case '6': // 1 string to match.
8790 0 : if (Mnemonic[12] != '4')
8791 : break;
8792 0 : Mnemonic = "v_rsq_f64"; // "v_rsq_f64_e64"
8793 0 : return;
8794 : }
8795 : break;
8796 : }
8797 : break;
8798 : }
8799 : break;
8800 : case 's': // 13 strings to match.
8801 16 : switch (Mnemonic[3]) {
8802 : default: break;
8803 : case 'a': // 1 string to match.
8804 0 : if (memcmp(Mnemonic.data()+4, "d_u32_e64", 9))
8805 : break;
8806 0 : Mnemonic = "v_sad_u32"; // "v_sad_u32_e64"
8807 0 : return;
8808 : case 'i': // 4 strings to match.
8809 0 : if (memcmp(Mnemonic.data()+4, "n_f", 3))
8810 : break;
8811 0 : switch (Mnemonic[7]) {
8812 : default: break;
8813 : case '1': // 2 strings to match.
8814 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
8815 : break;
8816 0 : switch (Mnemonic[11]) {
8817 : default: break;
8818 : case '3': // 1 string to match.
8819 0 : if (Mnemonic[12] != '2')
8820 : break;
8821 0 : Mnemonic = "v_sin_f16"; // "v_sin_f16_e32"
8822 0 : return;
8823 : case '6': // 1 string to match.
8824 0 : if (Mnemonic[12] != '4')
8825 : break;
8826 0 : Mnemonic = "v_sin_f16"; // "v_sin_f16_e64"
8827 0 : return;
8828 : }
8829 : break;
8830 : case '3': // 2 strings to match.
8831 0 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
8832 : break;
8833 0 : switch (Mnemonic[11]) {
8834 : default: break;
8835 : case '3': // 1 string to match.
8836 0 : if (Mnemonic[12] != '2')
8837 : break;
8838 0 : Mnemonic = "v_sin_f32"; // "v_sin_f32_e32"
8839 0 : return;
8840 : case '6': // 1 string to match.
8841 0 : if (Mnemonic[12] != '4')
8842 : break;
8843 0 : Mnemonic = "v_sin_f32"; // "v_sin_f32_e64"
8844 0 : return;
8845 : }
8846 : break;
8847 : }
8848 : break;
8849 : case 'u': // 8 strings to match.
8850 8 : if (memcmp(Mnemonic.data()+4, "b_", 2))
8851 : break;
8852 0 : switch (Mnemonic[6]) {
8853 : default: break;
8854 : case 'f': // 4 strings to match.
8855 0 : switch (Mnemonic[7]) {
8856 : default: break;
8857 : case '1': // 2 strings to match.
8858 0 : if (memcmp(Mnemonic.data()+8, "6_e", 3))
8859 : break;
8860 0 : switch (Mnemonic[11]) {
8861 : default: break;
8862 : case '3': // 1 string to match.
8863 0 : if (Mnemonic[12] != '2')
8864 : break;
8865 0 : Mnemonic = "v_sub_f16"; // "v_sub_f16_e32"
8866 0 : return;
8867 : case '6': // 1 string to match.
8868 0 : if (Mnemonic[12] != '4')
8869 : break;
8870 0 : Mnemonic = "v_sub_f16"; // "v_sub_f16_e64"
8871 0 : return;
8872 : }
8873 : break;
8874 : case '3': // 2 strings to match.
8875 0 : if (memcmp(Mnemonic.data()+8, "2_e", 3))
8876 : break;
8877 0 : switch (Mnemonic[11]) {
8878 : default: break;
8879 : case '3': // 1 string to match.
8880 0 : if (Mnemonic[12] != '2')
8881 : break;
8882 0 : Mnemonic = "v_sub_f32"; // "v_sub_f32_e32"
8883 0 : return;
8884 : case '6': // 1 string to match.
8885 0 : if (Mnemonic[12] != '4')
8886 : break;
8887 0 : Mnemonic = "v_sub_f32"; // "v_sub_f32_e64"
8888 0 : return;
8889 : }
8890 : break;
8891 : }
8892 : break;
8893 : case 'i': // 2 strings to match.
8894 0 : if (memcmp(Mnemonic.data()+7, "32_e", 4))
8895 : break;
8896 0 : switch (Mnemonic[11]) {
8897 : default: break;
8898 : case '3': // 1 string to match.
8899 0 : if (Mnemonic[12] != '2')
8900 : break;
8901 0 : Mnemonic = "v_sub_i32"; // "v_sub_i32_e32"
8902 0 : return;
8903 : case '6': // 1 string to match.
8904 0 : if (Mnemonic[12] != '4')
8905 : break;
8906 0 : Mnemonic = "v_sub_i32"; // "v_sub_i32_e64"
8907 0 : return;
8908 : }
8909 : break;
8910 : case 'u': // 2 strings to match.
8911 0 : if (memcmp(Mnemonic.data()+7, "16_e", 4))
8912 : break;
8913 0 : switch (Mnemonic[11]) {
8914 : default: break;
8915 : case '3': // 1 string to match.
8916 0 : if (Mnemonic[12] != '2')
8917 : break;
8918 0 : Mnemonic = "v_sub_u16"; // "v_sub_u16_e32"
8919 0 : return;
8920 : case '6': // 1 string to match.
8921 0 : if (Mnemonic[12] != '4')
8922 : break;
8923 0 : Mnemonic = "v_sub_u16"; // "v_sub_u16_e64"
8924 0 : return;
8925 : }
8926 : break;
8927 : }
8928 : break;
8929 : }
8930 : break;
8931 : case 'x': // 2 strings to match.
8932 0 : if (memcmp(Mnemonic.data()+3, "or_b32_e", 8))
8933 : break;
8934 0 : switch (Mnemonic[11]) {
8935 : default: break;
8936 : case '3': // 1 string to match.
8937 0 : if (Mnemonic[12] != '2')
8938 : break;
8939 0 : Mnemonic = "v_xor_b32"; // "v_xor_b32_e32"
8940 0 : return;
8941 : case '6': // 1 string to match.
8942 0 : if (Mnemonic[12] != '4')
8943 : break;
8944 0 : Mnemonic = "v_xor_b32"; // "v_xor_b32_e64"
8945 0 : return;
8946 : }
8947 : break;
8948 : }
8949 : break;
8950 : case 14: // 40 strings to match.
8951 108 : if (memcmp(Mnemonic.data()+0, "v_", 2))
8952 : break;
8953 48 : switch (Mnemonic[2]) {
8954 : default: break;
8955 : case 'a': // 5 strings to match.
8956 0 : switch (Mnemonic[3]) {
8957 : default: break;
8958 : case 'd': // 2 strings to match.
8959 0 : if (memcmp(Mnemonic.data()+4, "dc_u32_e", 8))
8960 : break;
8961 0 : switch (Mnemonic[12]) {
8962 : default: break;
8963 : case '3': // 1 string to match.
8964 0 : if (Mnemonic[13] != '2')
8965 : break;
8966 0 : Mnemonic = "v_addc_u32"; // "v_addc_u32_e32"
8967 0 : return;
8968 : case '6': // 1 string to match.
8969 0 : if (Mnemonic[13] != '4')
8970 : break;
8971 0 : Mnemonic = "v_addc_u32"; // "v_addc_u32_e64"
8972 0 : return;
8973 : }
8974 : break;
8975 : case 's': // 3 strings to match.
8976 0 : if (memcmp(Mnemonic.data()+4, "hr_i", 4))
8977 : break;
8978 0 : switch (Mnemonic[8]) {
8979 : default: break;
8980 : case '3': // 2 strings to match.
8981 0 : if (memcmp(Mnemonic.data()+9, "2_e", 3))
8982 : break;
8983 0 : switch (Mnemonic[12]) {
8984 : default: break;
8985 : case '3': // 1 string to match.
8986 0 : if (Mnemonic[13] != '2')
8987 : break;
8988 0 : Mnemonic = "v_ashr_i32"; // "v_ashr_i32_e32"
8989 0 : return;
8990 : case '6': // 1 string to match.
8991 0 : if (Mnemonic[13] != '4')
8992 : break;
8993 0 : Mnemonic = "v_ashr_i32"; // "v_ashr_i32_e64"
8994 0 : return;
8995 : }
8996 : break;
8997 : case '6': // 1 string to match.
8998 0 : if (memcmp(Mnemonic.data()+9, "4_e64", 5))
8999 : break;
9000 0 : Mnemonic = "v_ashr_i64"; // "v_ashr_i64_e64"
9001 0 : return;
9002 : }
9003 : break;
9004 : }
9005 : break;
9006 : case 'c': // 6 strings to match.
9007 0 : if (memcmp(Mnemonic.data()+3, "eil_f", 5))
9008 : break;
9009 0 : switch (Mnemonic[8]) {
9010 : default: break;
9011 : case '1': // 2 strings to match.
9012 0 : if (memcmp(Mnemonic.data()+9, "6_e", 3))
9013 : break;
9014 0 : switch (Mnemonic[12]) {
9015 : default: break;
9016 : case '3': // 1 string to match.
9017 0 : if (Mnemonic[13] != '2')
9018 : break;
9019 0 : Mnemonic = "v_ceil_f16"; // "v_ceil_f16_e32"
9020 0 : return;
9021 : case '6': // 1 string to match.
9022 0 : if (Mnemonic[13] != '4')
9023 : break;
9024 0 : Mnemonic = "v_ceil_f16"; // "v_ceil_f16_e64"
9025 0 : return;
9026 : }
9027 : break;
9028 : case '3': // 2 strings to match.
9029 0 : if (memcmp(Mnemonic.data()+9, "2_e", 3))
9030 : break;
9031 0 : switch (Mnemonic[12]) {
9032 : default: break;
9033 : case '3': // 1 string to match.
9034 0 : if (Mnemonic[13] != '2')
9035 : break;
9036 0 : Mnemonic = "v_ceil_f32"; // "v_ceil_f32_e32"
9037 0 : return;
9038 : case '6': // 1 string to match.
9039 0 : if (Mnemonic[13] != '4')
9040 : break;
9041 0 : Mnemonic = "v_ceil_f32"; // "v_ceil_f32_e64"
9042 0 : return;
9043 : }
9044 : break;
9045 : case '6': // 2 strings to match.
9046 0 : if (memcmp(Mnemonic.data()+9, "4_e", 3))
9047 : break;
9048 0 : switch (Mnemonic[12]) {
9049 : default: break;
9050 : case '3': // 1 string to match.
9051 0 : if (Mnemonic[13] != '2')
9052 : break;
9053 0 : Mnemonic = "v_ceil_f64"; // "v_ceil_f64_e32"
9054 0 : return;
9055 : case '6': // 1 string to match.
9056 0 : if (Mnemonic[13] != '4')
9057 : break;
9058 0 : Mnemonic = "v_ceil_f64"; // "v_ceil_f64_e64"
9059 0 : return;
9060 : }
9061 : break;
9062 : }
9063 : break;
9064 : case 'f': // 6 strings to match.
9065 0 : if (memcmp(Mnemonic.data()+3, "fb", 2))
9066 : break;
9067 0 : switch (Mnemonic[5]) {
9068 : default: break;
9069 : case 'h': // 4 strings to match.
9070 0 : if (Mnemonic[6] != '_')
9071 : break;
9072 0 : switch (Mnemonic[7]) {
9073 : default: break;
9074 : case 'i': // 2 strings to match.
9075 0 : if (memcmp(Mnemonic.data()+8, "32_e", 4))
9076 : break;
9077 0 : switch (Mnemonic[12]) {
9078 : default: break;
9079 : case '3': // 1 string to match.
9080 0 : if (Mnemonic[13] != '2')
9081 : break;
9082 0 : Mnemonic = "v_ffbh_i32"; // "v_ffbh_i32_e32"
9083 0 : return;
9084 : case '6': // 1 string to match.
9085 0 : if (Mnemonic[13] != '4')
9086 : break;
9087 0 : Mnemonic = "v_ffbh_i32"; // "v_ffbh_i32_e64"
9088 0 : return;
9089 : }
9090 : break;
9091 : case 'u': // 2 strings to match.
9092 0 : if (memcmp(Mnemonic.data()+8, "32_e", 4))
9093 : break;
9094 0 : switch (Mnemonic[12]) {
9095 : default: break;
9096 : case '3': // 1 string to match.
9097 0 : if (Mnemonic[13] != '2')
9098 : break;
9099 0 : Mnemonic = "v_ffbh_u32"; // "v_ffbh_u32_e32"
9100 0 : return;
9101 : case '6': // 1 string to match.
9102 0 : if (Mnemonic[13] != '4')
9103 : break;
9104 0 : Mnemonic = "v_ffbh_u32"; // "v_ffbh_u32_e64"
9105 0 : return;
9106 : }
9107 : break;
9108 : }
9109 : break;
9110 : case 'l': // 2 strings to match.
9111 0 : if (memcmp(Mnemonic.data()+6, "_b32_e", 6))
9112 : break;
9113 0 : switch (Mnemonic[12]) {
9114 : default: break;
9115 : case '3': // 1 string to match.
9116 0 : if (Mnemonic[13] != '2')
9117 : break;
9118 0 : Mnemonic = "v_ffbl_b32"; // "v_ffbl_b32_e32"
9119 0 : return;
9120 : case '6': // 1 string to match.
9121 0 : if (Mnemonic[13] != '4')
9122 : break;
9123 0 : Mnemonic = "v_ffbl_b32"; // "v_ffbl_b32_e64"
9124 0 : return;
9125 : }
9126 : break;
9127 : }
9128 : break;
9129 : case 'l': // 6 strings to match.
9130 0 : if (memcmp(Mnemonic.data()+3, "sh", 2))
9131 : break;
9132 0 : switch (Mnemonic[5]) {
9133 : default: break;
9134 : case 'l': // 3 strings to match.
9135 0 : if (memcmp(Mnemonic.data()+6, "_b", 2))
9136 : break;
9137 0 : switch (Mnemonic[8]) {
9138 : default: break;
9139 : case '3': // 2 strings to match.
9140 0 : if (memcmp(Mnemonic.data()+9, "2_e", 3))
9141 : break;
9142 0 : switch (Mnemonic[12]) {
9143 : default: break;
9144 : case '3': // 1 string to match.
9145 0 : if (Mnemonic[13] != '2')
9146 : break;
9147 0 : Mnemonic = "v_lshl_b32"; // "v_lshl_b32_e32"
9148 0 : return;
9149 : case '6': // 1 string to match.
9150 0 : if (Mnemonic[13] != '4')
9151 : break;
9152 0 : Mnemonic = "v_lshl_b32"; // "v_lshl_b32_e64"
9153 0 : return;
9154 : }
9155 : break;
9156 : case '6': // 1 string to match.
9157 0 : if (memcmp(Mnemonic.data()+9, "4_e64", 5))
9158 : break;
9159 0 : Mnemonic = "v_lshl_b64"; // "v_lshl_b64_e64"
9160 0 : return;
9161 : }
9162 : break;
9163 : case 'r': // 3 strings to match.
9164 0 : if (memcmp(Mnemonic.data()+6, "_b", 2))
9165 : break;
9166 0 : switch (Mnemonic[8]) {
9167 : default: break;
9168 : case '3': // 2 strings to match.
9169 0 : if (memcmp(Mnemonic.data()+9, "2_e", 3))
9170 : break;
9171 0 : switch (Mnemonic[12]) {
9172 : default: break;
9173 : case '3': // 1 string to match.
9174 0 : if (Mnemonic[13] != '2')
9175 : break;
9176 0 : Mnemonic = "v_lshr_b32"; // "v_lshr_b32_e32"
9177 0 : return;
9178 : case '6': // 1 string to match.
9179 0 : if (Mnemonic[13] != '4')
9180 : break;
9181 0 : Mnemonic = "v_lshr_b32"; // "v_lshr_b32_e64"
9182 0 : return;
9183 : }
9184 : break;
9185 : case '6': // 1 string to match.
9186 0 : if (memcmp(Mnemonic.data()+9, "4_e64", 5))
9187 : break;
9188 0 : Mnemonic = "v_lshr_b64"; // "v_lshr_b64_e64"
9189 0 : return;
9190 : }
9191 : break;
9192 : }
9193 : break;
9194 : case 'm': // 9 strings to match.
9195 16 : switch (Mnemonic[3]) {
9196 : default: break;
9197 : case 'a': // 3 strings to match.
9198 0 : if (memcmp(Mnemonic.data()+4, "x3_", 3))
9199 : break;
9200 0 : switch (Mnemonic[7]) {
9201 : default: break;
9202 : case 'f': // 1 string to match.
9203 0 : if (memcmp(Mnemonic.data()+8, "32_e64", 6))
9204 : break;
9205 0 : Mnemonic = "v_max3_f32"; // "v_max3_f32_e64"
9206 0 : return;
9207 : case 'i': // 1 string to match.
9208 0 : if (memcmp(Mnemonic.data()+8, "32_e64", 6))
9209 : break;
9210 0 : Mnemonic = "v_max3_i32"; // "v_max3_i32_e64"
9211 0 : return;
9212 : case 'u': // 1 string to match.
9213 0 : if (memcmp(Mnemonic.data()+8, "32_e64", 6))
9214 : break;
9215 0 : Mnemonic = "v_max3_u32"; // "v_max3_u32_e64"
9216 0 : return;
9217 : }
9218 : break;
9219 : case 'e': // 3 strings to match.
9220 0 : if (memcmp(Mnemonic.data()+4, "d3_", 3))
9221 : break;
9222 0 : switch (Mnemonic[7]) {
9223 : default: break;
9224 : case 'f': // 1 string to match.
9225 0 : if (memcmp(Mnemonic.data()+8, "32_e64", 6))
9226 : break;
9227 0 : Mnemonic = "v_med3_f32"; // "v_med3_f32_e64"
9228 0 : return;
9229 : case 'i': // 1 string to match.
9230 0 : if (memcmp(Mnemonic.data()+8, "32_e64", 6))
9231 : break;
9232 0 : Mnemonic = "v_med3_i32"; // "v_med3_i32_e64"
9233 0 : return;
9234 : case 'u': // 1 string to match.
9235 0 : if (memcmp(Mnemonic.data()+8, "32_e64", 6))
9236 : break;
9237 0 : Mnemonic = "v_med3_u32"; // "v_med3_u32_e64"
9238 0 : return;
9239 : }
9240 : break;
9241 : case 'i': // 3 strings to match.
9242 0 : if (memcmp(Mnemonic.data()+4, "n3_", 3))
9243 : break;
9244 0 : switch (Mnemonic[7]) {
9245 : default: break;
9246 : case 'f': // 1 string to match.
9247 0 : if (memcmp(Mnemonic.data()+8, "32_e64", 6))
9248 : break;
9249 0 : Mnemonic = "v_min3_f32"; // "v_min3_f32_e64"
9250 0 : return;
9251 : case 'i': // 1 string to match.
9252 0 : if (memcmp(Mnemonic.data()+8, "32_e64", 6))
9253 : break;
9254 0 : Mnemonic = "v_min3_i32"; // "v_min3_i32_e64"
9255 0 : return;
9256 : case 'u': // 1 string to match.
9257 0 : if (memcmp(Mnemonic.data()+8, "32_e64", 6))
9258 : break;
9259 0 : Mnemonic = "v_min3_u32"; // "v_min3_u32_e64"
9260 0 : return;
9261 : }
9262 : break;
9263 : }
9264 : break;
9265 : case 's': // 8 strings to match.
9266 0 : switch (Mnemonic[3]) {
9267 : default: break;
9268 : case 'q': // 6 strings to match.
9269 0 : if (memcmp(Mnemonic.data()+4, "rt_f", 4))
9270 : break;
9271 0 : switch (Mnemonic[8]) {
9272 : default: break;
9273 : case '1': // 2 strings to match.
9274 0 : if (memcmp(Mnemonic.data()+9, "6_e", 3))
9275 : break;
9276 0 : switch (Mnemonic[12]) {
9277 : default: break;
9278 : case '3': // 1 string to match.
9279 0 : if (Mnemonic[13] != '2')
9280 : break;
9281 0 : Mnemonic = "v_sqrt_f16"; // "v_sqrt_f16_e32"
9282 0 : return;
9283 : case '6': // 1 string to match.
9284 0 : if (Mnemonic[13] != '4')
9285 : break;
9286 0 : Mnemonic = "v_sqrt_f16"; // "v_sqrt_f16_e64"
9287 0 : return;
9288 : }
9289 : break;
9290 : case '3': // 2 strings to match.
9291 0 : if (memcmp(Mnemonic.data()+9, "2_e", 3))
9292 : break;
9293 0 : switch (Mnemonic[12]) {
9294 : default: break;
9295 : case '3': // 1 string to match.
9296 0 : if (Mnemonic[13] != '2')
9297 : break;
9298 0 : Mnemonic = "v_sqrt_f32"; // "v_sqrt_f32_e32"
9299 0 : return;
9300 : case '6': // 1 string to match.
9301 0 : if (Mnemonic[13] != '4')
9302 : break;
9303 0 : Mnemonic = "v_sqrt_f32"; // "v_sqrt_f32_e64"
9304 0 : return;
9305 : }
9306 : break;
9307 : case '6': // 2 strings to match.
9308 0 : if (memcmp(Mnemonic.data()+9, "4_e", 3))
9309 : break;
9310 0 : switch (Mnemonic[12]) {
9311 : default: break;
9312 : case '3': // 1 string to match.
9313 0 : if (Mnemonic[13] != '2')
9314 : break;
9315 0 : Mnemonic = "v_sqrt_f64"; // "v_sqrt_f64_e32"
9316 0 : return;
9317 : case '6': // 1 string to match.
9318 0 : if (Mnemonic[13] != '4')
9319 : break;
9320 0 : Mnemonic = "v_sqrt_f64"; // "v_sqrt_f64_e64"
9321 0 : return;
9322 : }
9323 : break;
9324 : }
9325 : break;
9326 : case 'u': // 2 strings to match.
9327 0 : if (memcmp(Mnemonic.data()+4, "bb_u32_e", 8))
9328 : break;
9329 0 : switch (Mnemonic[12]) {
9330 : default: break;
9331 : case '3': // 1 string to match.
9332 0 : if (Mnemonic[13] != '2')
9333 : break;
9334 0 : Mnemonic = "v_subb_u32"; // "v_subb_u32_e32"
9335 0 : return;
9336 : case '6': // 1 string to match.
9337 0 : if (Mnemonic[13] != '4')
9338 : break;
9339 0 : Mnemonic = "v_subb_u32"; // "v_subb_u32_e64"
9340 0 : return;
9341 : }
9342 : break;
9343 : }
9344 : break;
9345 : }
9346 : break;
9347 : case 15: // 63 strings to match.
9348 82 : if (memcmp(Mnemonic.data()+0, "v_", 2))
9349 : break;
9350 112 : switch (Mnemonic[2]) {
9351 : default: break;
9352 : case 'b': // 2 strings to match.
9353 0 : if (memcmp(Mnemonic.data()+3, "frev_b32_e", 10))
9354 : break;
9355 0 : switch (Mnemonic[13]) {
9356 : default: break;
9357 : case '3': // 1 string to match.
9358 0 : if (Mnemonic[14] != '2')
9359 : break;
9360 0 : Mnemonic = "v_bfrev_b32"; // "v_bfrev_b32_e32"
9361 0 : return;
9362 : case '6': // 1 string to match.
9363 0 : if (Mnemonic[14] != '4')
9364 : break;
9365 0 : Mnemonic = "v_bfrev_b32"; // "v_bfrev_b32_e64"
9366 0 : return;
9367 : }
9368 : break;
9369 : case 'c': // 28 strings to match.
9370 0 : if (memcmp(Mnemonic.data()+3, "mp_", 3))
9371 : break;
9372 0 : switch (Mnemonic[6]) {
9373 : default: break;
9374 : case 'f': // 12 strings to match.
9375 0 : if (Mnemonic[7] != '_')
9376 : break;
9377 0 : switch (Mnemonic[8]) {
9378 : default: break;
9379 : case 'f': // 4 strings to match.
9380 0 : switch (Mnemonic[9]) {
9381 : default: break;
9382 : case '3': // 2 strings to match.
9383 0 : if (memcmp(Mnemonic.data()+10, "2_e", 3))
9384 : break;
9385 0 : switch (Mnemonic[13]) {
9386 : default: break;
9387 : case '3': // 1 string to match.
9388 0 : if (Mnemonic[14] != '2')
9389 : break;
9390 0 : Mnemonic = "v_cmp_f_f32"; // "v_cmp_f_f32_e32"
9391 0 : return;
9392 : case '6': // 1 string to match.
9393 0 : if (Mnemonic[14] != '4')
9394 : break;
9395 0 : Mnemonic = "v_cmp_f_f32"; // "v_cmp_f_f32_e64"
9396 0 : return;
9397 : }
9398 : break;
9399 : case '6': // 2 strings to match.
9400 0 : if (memcmp(Mnemonic.data()+10, "4_e", 3))
9401 : break;
9402 0 : switch (Mnemonic[13]) {
9403 : default: break;
9404 : case '3': // 1 string to match.
9405 0 : if (Mnemonic[14] != '2')
9406 : break;
9407 0 : Mnemonic = "v_cmp_f_f64"; // "v_cmp_f_f64_e32"
9408 0 : return;
9409 : case '6': // 1 string to match.
9410 0 : if (Mnemonic[14] != '4')
9411 : break;
9412 0 : Mnemonic = "v_cmp_f_f64"; // "v_cmp_f_f64_e64"
9413 0 : return;
9414 : }
9415 : break;
9416 : }
9417 : break;
9418 : case 'i': // 4 strings to match.
9419 0 : switch (Mnemonic[9]) {
9420 : default: break;
9421 : case '3': // 2 strings to match.
9422 0 : if (memcmp(Mnemonic.data()+10, "2_e", 3))
9423 : break;
9424 0 : switch (Mnemonic[13]) {
9425 : default: break;
9426 : case '3': // 1 string to match.
9427 0 : if (Mnemonic[14] != '2')
9428 : break;
9429 0 : Mnemonic = "v_cmp_f_i32"; // "v_cmp_f_i32_e32"
9430 0 : return;
9431 : case '6': // 1 string to match.
9432 0 : if (Mnemonic[14] != '4')
9433 : break;
9434 0 : Mnemonic = "v_cmp_f_i32"; // "v_cmp_f_i32_e64"
9435 0 : return;
9436 : }
9437 : break;
9438 : case '6': // 2 strings to match.
9439 0 : if (memcmp(Mnemonic.data()+10, "4_e", 3))
9440 : break;
9441 0 : switch (Mnemonic[13]) {
9442 : default: break;
9443 : case '3': // 1 string to match.
9444 0 : if (Mnemonic[14] != '2')
9445 : break;
9446 0 : Mnemonic = "v_cmp_f_i64"; // "v_cmp_f_i64_e32"
9447 0 : return;
9448 : case '6': // 1 string to match.
9449 0 : if (Mnemonic[14] != '4')
9450 : break;
9451 0 : Mnemonic = "v_cmp_f_i64"; // "v_cmp_f_i64_e64"
9452 0 : return;
9453 : }
9454 : break;
9455 : }
9456 : break;
9457 : case 'u': // 4 strings to match.
9458 0 : switch (Mnemonic[9]) {
9459 : default: break;
9460 : case '3': // 2 strings to match.
9461 0 : if (memcmp(Mnemonic.data()+10, "2_e", 3))
9462 : break;
9463 0 : switch (Mnemonic[13]) {
9464 : default: break;
9465 : case '3': // 1 string to match.
9466 0 : if (Mnemonic[14] != '2')
9467 : break;
9468 0 : Mnemonic = "v_cmp_f_u32"; // "v_cmp_f_u32_e32"
9469 0 : return;
9470 : case '6': // 1 string to match.
9471 0 : if (Mnemonic[14] != '4')
9472 : break;
9473 0 : Mnemonic = "v_cmp_f_u32"; // "v_cmp_f_u32_e64"
9474 0 : return;
9475 : }
9476 : break;
9477 : case '6': // 2 strings to match.
9478 0 : if (memcmp(Mnemonic.data()+10, "4_e", 3))
9479 : break;
9480 0 : switch (Mnemonic[13]) {
9481 : default: break;
9482 : case '3': // 1 string to match.
9483 0 : if (Mnemonic[14] != '2')
9484 : break;
9485 0 : Mnemonic = "v_cmp_f_u64"; // "v_cmp_f_u64_e32"
9486 0 : return;
9487 : case '6': // 1 string to match.
9488 0 : if (Mnemonic[14] != '4')
9489 : break;
9490 0 : Mnemonic = "v_cmp_f_u64"; // "v_cmp_f_u64_e64"
9491 0 : return;
9492 : }
9493 : break;
9494 : }
9495 : break;
9496 : }
9497 : break;
9498 : case 'o': // 4 strings to match.
9499 0 : if (memcmp(Mnemonic.data()+7, "_f", 2))
9500 : break;
9501 0 : switch (Mnemonic[9]) {
9502 : default: break;
9503 : case '3': // 2 strings to match.
9504 0 : if (memcmp(Mnemonic.data()+10, "2_e", 3))
9505 : break;
9506 0 : switch (Mnemonic[13]) {
9507 : default: break;
9508 : case '3': // 1 string to match.
9509 0 : if (Mnemonic[14] != '2')
9510 : break;
9511 0 : Mnemonic = "v_cmp_o_f32"; // "v_cmp_o_f32_e32"
9512 0 : return;
9513 : case '6': // 1 string to match.
9514 0 : if (Mnemonic[14] != '4')
9515 : break;
9516 0 : Mnemonic = "v_cmp_o_f32"; // "v_cmp_o_f32_e64"
9517 0 : return;
9518 : }
9519 : break;
9520 : case '6': // 2 strings to match.
9521 0 : if (memcmp(Mnemonic.data()+10, "4_e", 3))
9522 : break;
9523 0 : switch (Mnemonic[13]) {
9524 : default: break;
9525 : case '3': // 1 string to match.
9526 0 : if (Mnemonic[14] != '2')
9527 : break;
9528 0 : Mnemonic = "v_cmp_o_f64"; // "v_cmp_o_f64_e32"
9529 0 : return;
9530 : case '6': // 1 string to match.
9531 0 : if (Mnemonic[14] != '4')
9532 : break;
9533 0 : Mnemonic = "v_cmp_o_f64"; // "v_cmp_o_f64_e64"
9534 0 : return;
9535 : }
9536 : break;
9537 : }
9538 : break;
9539 : case 't': // 8 strings to match.
9540 0 : if (Mnemonic[7] != '_')
9541 : break;
9542 0 : switch (Mnemonic[8]) {
9543 : default: break;
9544 : case 'i': // 4 strings to match.
9545 0 : switch (Mnemonic[9]) {
9546 : default: break;
9547 : case '3': // 2 strings to match.
9548 0 : if (memcmp(Mnemonic.data()+10, "2_e", 3))
9549 : break;
9550 0 : switch (Mnemonic[13]) {
9551 : default: break;
9552 : case '3': // 1 string to match.
9553 0 : if (Mnemonic[14] != '2')
9554 : break;
9555 0 : Mnemonic = "v_cmp_t_i32"; // "v_cmp_t_i32_e32"
9556 0 : return;
9557 : case '6': // 1 string to match.
9558 0 : if (Mnemonic[14] != '4')
9559 : break;
9560 0 : Mnemonic = "v_cmp_t_i32"; // "v_cmp_t_i32_e64"
9561 0 : return;
9562 : }
9563 : break;
9564 : case '6': // 2 strings to match.
9565 0 : if (memcmp(Mnemonic.data()+10, "4_e", 3))
9566 : break;
9567 0 : switch (Mnemonic[13]) {
9568 : default: break;
9569 : case '3': // 1 string to match.
9570 0 : if (Mnemonic[14] != '2')
9571 : break;
9572 0 : Mnemonic = "v_cmp_t_i64"; // "v_cmp_t_i64_e32"
9573 0 : return;
9574 : case '6': // 1 string to match.
9575 0 : if (Mnemonic[14] != '4')
9576 : break;
9577 0 : Mnemonic = "v_cmp_t_i64"; // "v_cmp_t_i64_e64"
9578 0 : return;
9579 : }
9580 : break;
9581 : }
9582 : break;
9583 : case 'u': // 4 strings to match.
9584 0 : switch (Mnemonic[9]) {
9585 : default: break;
9586 : case '3': // 2 strings to match.
9587 0 : if (memcmp(Mnemonic.data()+10, "2_e", 3))
9588 : break;
9589 0 : switch (Mnemonic[13]) {
9590 : default: break;
9591 : case '3': // 1 string to match.
9592 0 : if (Mnemonic[14] != '2')
9593 : break;
9594 0 : Mnemonic = "v_cmp_t_u32"; // "v_cmp_t_u32_e32"
9595 0 : return;
9596 : case '6': // 1 string to match.
9597 0 : if (Mnemonic[14] != '4')
9598 : break;
9599 0 : Mnemonic = "v_cmp_t_u32"; // "v_cmp_t_u32_e64"
9600 0 : return;
9601 : }
9602 : break;
9603 : case '6': // 2 strings to match.
9604 0 : if (memcmp(Mnemonic.data()+10, "4_e", 3))
9605 : break;
9606 0 : switch (Mnemonic[13]) {
9607 : default: break;
9608 : case '3': // 1 string to match.
9609 0 : if (Mnemonic[14] != '2')
9610 : break;
9611 0 : Mnemonic = "v_cmp_t_u64"; // "v_cmp_t_u64_e32"
9612 0 : return;
9613 : case '6': // 1 string to match.
9614 0 : if (Mnemonic[14] != '4')
9615 : break;
9616 0 : Mnemonic = "v_cmp_t_u64"; // "v_cmp_t_u64_e64"
9617 0 : return;
9618 : }
9619 : break;
9620 : }
9621 : break;
9622 : }
9623 : break;
9624 : case 'u': // 4 strings to match.
9625 0 : if (memcmp(Mnemonic.data()+7, "_f", 2))
9626 : break;
9627 0 : switch (Mnemonic[9]) {
9628 : default: break;
9629 : case '3': // 2 strings to match.
9630 0 : if (memcmp(Mnemonic.data()+10, "2_e", 3))
9631 : break;
9632 0 : switch (Mnemonic[13]) {
9633 : default: break;
9634 : case '3': // 1 string to match.
9635 0 : if (Mnemonic[14] != '2')
9636 : break;
9637 0 : Mnemonic = "v_cmp_u_f32"; // "v_cmp_u_f32_e32"
9638 0 : return;
9639 : case '6': // 1 string to match.
9640 0 : if (Mnemonic[14] != '4')
9641 : break;
9642 0 : Mnemonic = "v_cmp_u_f32"; // "v_cmp_u_f32_e64"
9643 0 : return;
9644 : }
9645 : break;
9646 : case '6': // 2 strings to match.
9647 0 : if (memcmp(Mnemonic.data()+10, "4_e", 3))
9648 : break;
9649 0 : switch (Mnemonic[13]) {
9650 : default: break;
9651 : case '3': // 1 string to match.
9652 0 : if (Mnemonic[14] != '2')
9653 : break;
9654 0 : Mnemonic = "v_cmp_u_f64"; // "v_cmp_u_f64_e32"
9655 0 : return;
9656 : case '6': // 1 string to match.
9657 0 : if (Mnemonic[14] != '4')
9658 : break;
9659 0 : Mnemonic = "v_cmp_u_f64"; // "v_cmp_u_f64_e64"
9660 0 : return;
9661 : }
9662 : break;
9663 : }
9664 : break;
9665 : }
9666 : break;
9667 : case 'f': // 12 strings to match.
9668 0 : switch (Mnemonic[3]) {
9669 : default: break;
9670 : case 'l': // 6 strings to match.
9671 0 : if (memcmp(Mnemonic.data()+4, "oor_f", 5))
9672 : break;
9673 0 : switch (Mnemonic[9]) {
9674 : default: break;
9675 : case '1': // 2 strings to match.
9676 0 : if (memcmp(Mnemonic.data()+10, "6_e", 3))
9677 : break;
9678 0 : switch (Mnemonic[13]) {
9679 : default: break;
9680 : case '3': // 1 string to match.
9681 0 : if (Mnemonic[14] != '2')
9682 : break;
9683 0 : Mnemonic = "v_floor_f16"; // "v_floor_f16_e32"
9684 0 : return;
9685 : case '6': // 1 string to match.
9686 0 : if (Mnemonic[14] != '4')
9687 : break;
9688 0 : Mnemonic = "v_floor_f16"; // "v_floor_f16_e64"
9689 0 : return;
9690 : }
9691 : break;
9692 : case '3': // 2 strings to match.
9693 0 : if (memcmp(Mnemonic.data()+10, "2_e", 3))
9694 : break;
9695 0 : switch (Mnemonic[13]) {
9696 : default: break;
9697 : case '3': // 1 string to match.
9698 0 : if (Mnemonic[14] != '2')
9699 : break;
9700 0 : Mnemonic = "v_floor_f32"; // "v_floor_f32_e32"
9701 0 : return;
9702 : case '6': // 1 string to match.
9703 0 : if (Mnemonic[14] != '4')
9704 : break;
9705 0 : Mnemonic = "v_floor_f32"; // "v_floor_f32_e64"
9706 0 : return;
9707 : }
9708 : break;
9709 : case '6': // 2 strings to match.
9710 0 : if (memcmp(Mnemonic.data()+10, "4_e", 3))
9711 : break;
9712 0 : switch (Mnemonic[13]) {
9713 : default: break;
9714 : case '3': // 1 string to match.
9715 0 : if (Mnemonic[14] != '2')
9716 : break;
9717 0 : Mnemonic = "v_floor_f64"; // "v_floor_f64_e32"
9718 0 : return;
9719 : case '6': // 1 string to match.
9720 0 : if (Mnemonic[14] != '4')
9721 : break;
9722 0 : Mnemonic = "v_floor_f64"; // "v_floor_f64_e64"
9723 0 : return;
9724 : }
9725 : break;
9726 : }
9727 : break;
9728 : case 'r': // 6 strings to match.
9729 0 : if (memcmp(Mnemonic.data()+4, "act_f", 5))
9730 : break;
9731 0 : switch (Mnemonic[9]) {
9732 : default: break;
9733 : case '1': // 2 strings to match.
9734 0 : if (memcmp(Mnemonic.data()+10, "6_e", 3))
9735 : break;
9736 0 : switch (Mnemonic[13]) {
9737 : default: break;
9738 : case '3': // 1 string to match.
9739 0 : if (Mnemonic[14] != '2')
9740 : break;
9741 0 : Mnemonic = "v_fract_f16"; // "v_fract_f16_e32"
9742 0 : return;
9743 : case '6': // 1 string to match.
9744 0 : if (Mnemonic[14] != '4')
9745 : break;
9746 0 : Mnemonic = "v_fract_f16"; // "v_fract_f16_e64"
9747 0 : return;
9748 : }
9749 : break;
9750 : case '3': // 2 strings to match.
9751 0 : if (memcmp(Mnemonic.data()+10, "2_e", 3))
9752 : break;
9753 0 : switch (Mnemonic[13]) {
9754 : default: break;
9755 : case '3': // 1 string to match.
9756 0 : if (Mnemonic[14] != '2')
9757 : break;
9758 0 : Mnemonic = "v_fract_f32"; // "v_fract_f32_e32"
9759 0 : return;
9760 : case '6': // 1 string to match.
9761 0 : if (Mnemonic[14] != '4')
9762 : break;
9763 0 : Mnemonic = "v_fract_f32"; // "v_fract_f32_e64"
9764 0 : return;
9765 : }
9766 : break;
9767 : case '6': // 2 strings to match.
9768 0 : if (memcmp(Mnemonic.data()+10, "4_e", 3))
9769 : break;
9770 0 : switch (Mnemonic[13]) {
9771 : default: break;
9772 : case '3': // 1 string to match.
9773 0 : if (Mnemonic[14] != '2')
9774 : break;
9775 0 : Mnemonic = "v_fract_f64"; // "v_fract_f64_e32"
9776 0 : return;
9777 : case '6': // 1 string to match.
9778 0 : if (Mnemonic[14] != '4')
9779 : break;
9780 0 : Mnemonic = "v_fract_f64"; // "v_fract_f64_e64"
9781 0 : return;
9782 : }
9783 : break;
9784 : }
9785 : break;
9786 : }
9787 : break;
9788 : case 'l': // 5 strings to match.
9789 8 : if (memcmp(Mnemonic.data()+3, "dexp_f", 6))
9790 : break;
9791 0 : switch (Mnemonic[9]) {
9792 : default: break;
9793 : case '1': // 2 strings to match.
9794 0 : if (memcmp(Mnemonic.data()+10, "6_e", 3))
9795 : break;
9796 0 : switch (Mnemonic[13]) {
9797 : default: break;
9798 : case '3': // 1 string to match.
9799 0 : if (Mnemonic[14] != '2')
9800 : break;
9801 0 : Mnemonic = "v_ldexp_f16"; // "v_ldexp_f16_e32"
9802 0 : return;
9803 : case '6': // 1 string to match.
9804 0 : if (Mnemonic[14] != '4')
9805 : break;
9806 0 : Mnemonic = "v_ldexp_f16"; // "v_ldexp_f16_e64"
9807 0 : return;
9808 : }
9809 : break;
9810 : case '3': // 2 strings to match.
9811 0 : if (memcmp(Mnemonic.data()+10, "2_e", 3))
9812 : break;
9813 0 : switch (Mnemonic[13]) {
9814 : default: break;
9815 : case '3': // 1 string to match.
9816 0 : if (Mnemonic[14] != '2')
9817 : break;
9818 0 : Mnemonic = "v_ldexp_f32"; // "v_ldexp_f32_e32"
9819 0 : return;
9820 : case '6': // 1 string to match.
9821 0 : if (Mnemonic[14] != '4')
9822 : break;
9823 0 : Mnemonic = "v_ldexp_f32"; // "v_ldexp_f32_e64"
9824 0 : return;
9825 : }
9826 : break;
9827 : case '6': // 1 string to match.
9828 0 : if (memcmp(Mnemonic.data()+10, "4_e64", 5))
9829 : break;
9830 0 : Mnemonic = "v_ldexp_f64"; // "v_ldexp_f64_e64"
9831 0 : return;
9832 : }
9833 : break;
9834 : case 'm': // 4 strings to match.
9835 0 : if (memcmp(Mnemonic.data()+3, "ad", 2))
9836 : break;
9837 0 : switch (Mnemonic[5]) {
9838 : default: break;
9839 : case 'a': // 2 strings to match.
9840 0 : if (memcmp(Mnemonic.data()+6, "k_f", 3))
9841 : break;
9842 0 : switch (Mnemonic[9]) {
9843 : default: break;
9844 : case '1': // 1 string to match.
9845 0 : if (memcmp(Mnemonic.data()+10, "6_e32", 5))
9846 : break;
9847 0 : Mnemonic = "v_madak_f16"; // "v_madak_f16_e32"
9848 0 : return;
9849 : case '3': // 1 string to match.
9850 0 : if (memcmp(Mnemonic.data()+10, "2_e32", 5))
9851 : break;
9852 0 : Mnemonic = "v_madak_f32"; // "v_madak_f32_e32"
9853 0 : return;
9854 : }
9855 : break;
9856 : case 'm': // 2 strings to match.
9857 0 : if (memcmp(Mnemonic.data()+6, "k_f", 3))
9858 : break;
9859 0 : switch (Mnemonic[9]) {
9860 : default: break;
9861 : case '1': // 1 string to match.
9862 0 : if (memcmp(Mnemonic.data()+10, "6_e32", 5))
9863 : break;
9864 0 : Mnemonic = "v_madmk_f16"; // "v_madmk_f16_e32"
9865 0 : return;
9866 : case '3': // 1 string to match.
9867 0 : if (memcmp(Mnemonic.data()+10, "2_e32", 5))
9868 : break;
9869 0 : Mnemonic = "v_madmk_f32"; // "v_madmk_f32_e32"
9870 0 : return;
9871 : }
9872 : break;
9873 : }
9874 : break;
9875 : case 'r': // 6 strings to match.
9876 40 : if (memcmp(Mnemonic.data()+3, "ndne_f", 6))
9877 : break;
9878 0 : switch (Mnemonic[9]) {
9879 : default: break;
9880 : case '1': // 2 strings to match.
9881 0 : if (memcmp(Mnemonic.data()+10, "6_e", 3))
9882 : break;
9883 0 : switch (Mnemonic[13]) {
9884 : default: break;
9885 : case '3': // 1 string to match.
9886 0 : if (Mnemonic[14] != '2')
9887 : break;
9888 0 : Mnemonic = "v_rndne_f16"; // "v_rndne_f16_e32"
9889 0 : return;
9890 : case '6': // 1 string to match.
9891 0 : if (Mnemonic[14] != '4')
9892 : break;
9893 0 : Mnemonic = "v_rndne_f16"; // "v_rndne_f16_e64"
9894 0 : return;
9895 : }
9896 : break;
9897 : case '3': // 2 strings to match.
9898 0 : if (memcmp(Mnemonic.data()+10, "2_e", 3))
9899 : break;
9900 0 : switch (Mnemonic[13]) {
9901 : default: break;
9902 : case '3': // 1 string to match.
9903 0 : if (Mnemonic[14] != '2')
9904 : break;
9905 0 : Mnemonic = "v_rndne_f32"; // "v_rndne_f32_e32"
9906 0 : return;
9907 : case '6': // 1 string to match.
9908 0 : if (Mnemonic[14] != '4')
9909 : break;
9910 0 : Mnemonic = "v_rndne_f32"; // "v_rndne_f32_e64"
9911 0 : return;
9912 : }
9913 : break;
9914 : case '6': // 2 strings to match.
9915 0 : if (memcmp(Mnemonic.data()+10, "4_e", 3))
9916 : break;
9917 0 : switch (Mnemonic[13]) {
9918 : default: break;
9919 : case '3': // 1 string to match.
9920 0 : if (Mnemonic[14] != '2')
9921 : break;
9922 0 : Mnemonic = "v_rndne_f64"; // "v_rndne_f64_e32"
9923 0 : return;
9924 : case '6': // 1 string to match.
9925 0 : if (Mnemonic[14] != '4')
9926 : break;
9927 0 : Mnemonic = "v_rndne_f64"; // "v_rndne_f64_e64"
9928 0 : return;
9929 : }
9930 : break;
9931 : }
9932 : break;
9933 : case 't': // 6 strings to match.
9934 0 : if (memcmp(Mnemonic.data()+3, "runc_f", 6))
9935 : break;
9936 0 : switch (Mnemonic[9]) {
9937 : default: break;
9938 : case '1': // 2 strings to match.
9939 0 : if (memcmp(Mnemonic.data()+10, "6_e", 3))
9940 : break;
9941 0 : switch (Mnemonic[13]) {
9942 : default: break;
9943 : case '3': // 1 string to match.
9944 0 : if (Mnemonic[14] != '2')
9945 : break;
9946 0 : Mnemonic = "v_trunc_f16"; // "v_trunc_f16_e32"
9947 0 : return;
9948 : case '6': // 1 string to match.
9949 0 : if (Mnemonic[14] != '4')
9950 : break;
9951 0 : Mnemonic = "v_trunc_f16"; // "v_trunc_f16_e64"
9952 0 : return;
9953 : }
9954 : break;
9955 : case '3': // 2 strings to match.
9956 0 : if (memcmp(Mnemonic.data()+10, "2_e", 3))
9957 : break;
9958 0 : switch (Mnemonic[13]) {
9959 : default: break;
9960 : case '3': // 1 string to match.
9961 0 : if (Mnemonic[14] != '2')
9962 : break;
9963 0 : Mnemonic = "v_trunc_f32"; // "v_trunc_f32_e32"
9964 0 : return;
9965 : case '6': // 1 string to match.
9966 0 : if (Mnemonic[14] != '4')
9967 : break;
9968 0 : Mnemonic = "v_trunc_f32"; // "v_trunc_f32_e64"
9969 0 : return;
9970 : }
9971 : break;
9972 : case '6': // 2 strings to match.
9973 0 : if (memcmp(Mnemonic.data()+10, "4_e", 3))
9974 : break;
9975 0 : switch (Mnemonic[13]) {
9976 : default: break;
9977 : case '3': // 1 string to match.
9978 0 : if (Mnemonic[14] != '2')
9979 : break;
9980 0 : Mnemonic = "v_trunc_f64"; // "v_trunc_f64_e32"
9981 0 : return;
9982 : case '6': // 1 string to match.
9983 0 : if (Mnemonic[14] != '4')
9984 : break;
9985 0 : Mnemonic = "v_trunc_f64"; // "v_trunc_f64_e64"
9986 0 : return;
9987 : }
9988 : break;
9989 : }
9990 : break;
9991 : }
9992 : break;
9993 : case 16: // 131 strings to match.
9994 158 : if (memcmp(Mnemonic.data()+0, "v_", 2))
9995 : break;
9996 268 : switch (Mnemonic[2]) {
9997 : default: break;
9998 : case 'c': // 116 strings to match.
9999 80 : switch (Mnemonic[3]) {
10000 : default: break;
10001 : case 'm': // 112 strings to match.
10002 0 : if (Mnemonic[4] != 'p')
10003 : break;
10004 0 : switch (Mnemonic[5]) {
10005 : default: break;
10006 : case '_': // 72 strings to match.
10007 0 : switch (Mnemonic[6]) {
10008 : default: break;
10009 : case 'e': // 12 strings to match.
10010 0 : if (memcmp(Mnemonic.data()+7, "q_", 2))
10011 : break;
10012 0 : switch (Mnemonic[9]) {
10013 : default: break;
10014 : case 'f': // 4 strings to match.
10015 0 : switch (Mnemonic[10]) {
10016 : default: break;
10017 : case '3': // 2 strings to match.
10018 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
10019 : break;
10020 0 : switch (Mnemonic[14]) {
10021 : default: break;
10022 : case '3': // 1 string to match.
10023 0 : if (Mnemonic[15] != '2')
10024 : break;
10025 0 : Mnemonic = "v_cmp_eq_f32"; // "v_cmp_eq_f32_e32"
10026 0 : return;
10027 : case '6': // 1 string to match.
10028 0 : if (Mnemonic[15] != '4')
10029 : break;
10030 0 : Mnemonic = "v_cmp_eq_f32"; // "v_cmp_eq_f32_e64"
10031 0 : return;
10032 : }
10033 : break;
10034 : case '6': // 2 strings to match.
10035 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
10036 : break;
10037 0 : switch (Mnemonic[14]) {
10038 : default: break;
10039 : case '3': // 1 string to match.
10040 0 : if (Mnemonic[15] != '2')
10041 : break;
10042 0 : Mnemonic = "v_cmp_eq_f64"; // "v_cmp_eq_f64_e32"
10043 0 : return;
10044 : case '6': // 1 string to match.
10045 0 : if (Mnemonic[15] != '4')
10046 : break;
10047 0 : Mnemonic = "v_cmp_eq_f64"; // "v_cmp_eq_f64_e64"
10048 0 : return;
10049 : }
10050 : break;
10051 : }
10052 : break;
10053 : case 'i': // 4 strings to match.
10054 0 : switch (Mnemonic[10]) {
10055 : default: break;
10056 : case '3': // 2 strings to match.
10057 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
10058 : break;
10059 0 : switch (Mnemonic[14]) {
10060 : default: break;
10061 : case '3': // 1 string to match.
10062 0 : if (Mnemonic[15] != '2')
10063 : break;
10064 0 : Mnemonic = "v_cmp_eq_i32"; // "v_cmp_eq_i32_e32"
10065 0 : return;
10066 : case '6': // 1 string to match.
10067 0 : if (Mnemonic[15] != '4')
10068 : break;
10069 0 : Mnemonic = "v_cmp_eq_i32"; // "v_cmp_eq_i32_e64"
10070 0 : return;
10071 : }
10072 : break;
10073 : case '6': // 2 strings to match.
10074 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
10075 : break;
10076 0 : switch (Mnemonic[14]) {
10077 : default: break;
10078 : case '3': // 1 string to match.
10079 0 : if (Mnemonic[15] != '2')
10080 : break;
10081 0 : Mnemonic = "v_cmp_eq_i64"; // "v_cmp_eq_i64_e32"
10082 0 : return;
10083 : case '6': // 1 string to match.
10084 0 : if (Mnemonic[15] != '4')
10085 : break;
10086 0 : Mnemonic = "v_cmp_eq_i64"; // "v_cmp_eq_i64_e64"
10087 0 : return;
10088 : }
10089 : break;
10090 : }
10091 : break;
10092 : case 'u': // 4 strings to match.
10093 0 : switch (Mnemonic[10]) {
10094 : default: break;
10095 : case '3': // 2 strings to match.
10096 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
10097 : break;
10098 0 : switch (Mnemonic[14]) {
10099 : default: break;
10100 : case '3': // 1 string to match.
10101 0 : if (Mnemonic[15] != '2')
10102 : break;
10103 0 : Mnemonic = "v_cmp_eq_u32"; // "v_cmp_eq_u32_e32"
10104 0 : return;
10105 : case '6': // 1 string to match.
10106 0 : if (Mnemonic[15] != '4')
10107 : break;
10108 0 : Mnemonic = "v_cmp_eq_u32"; // "v_cmp_eq_u32_e64"
10109 0 : return;
10110 : }
10111 : break;
10112 : case '6': // 2 strings to match.
10113 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
10114 : break;
10115 0 : switch (Mnemonic[14]) {
10116 : default: break;
10117 : case '3': // 1 string to match.
10118 0 : if (Mnemonic[15] != '2')
10119 : break;
10120 0 : Mnemonic = "v_cmp_eq_u64"; // "v_cmp_eq_u64_e32"
10121 0 : return;
10122 : case '6': // 1 string to match.
10123 0 : if (Mnemonic[15] != '4')
10124 : break;
10125 0 : Mnemonic = "v_cmp_eq_u64"; // "v_cmp_eq_u64_e64"
10126 0 : return;
10127 : }
10128 : break;
10129 : }
10130 : break;
10131 : }
10132 : break;
10133 : case 'g': // 24 strings to match.
10134 0 : switch (Mnemonic[7]) {
10135 : default: break;
10136 : case 'e': // 12 strings to match.
10137 0 : if (Mnemonic[8] != '_')
10138 : break;
10139 0 : switch (Mnemonic[9]) {
10140 : default: break;
10141 : case 'f': // 4 strings to match.
10142 0 : switch (Mnemonic[10]) {
10143 : default: break;
10144 : case '3': // 2 strings to match.
10145 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
10146 : break;
10147 0 : switch (Mnemonic[14]) {
10148 : default: break;
10149 : case '3': // 1 string to match.
10150 0 : if (Mnemonic[15] != '2')
10151 : break;
10152 0 : Mnemonic = "v_cmp_ge_f32"; // "v_cmp_ge_f32_e32"
10153 0 : return;
10154 : case '6': // 1 string to match.
10155 0 : if (Mnemonic[15] != '4')
10156 : break;
10157 0 : Mnemonic = "v_cmp_ge_f32"; // "v_cmp_ge_f32_e64"
10158 0 : return;
10159 : }
10160 : break;
10161 : case '6': // 2 strings to match.
10162 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
10163 : break;
10164 0 : switch (Mnemonic[14]) {
10165 : default: break;
10166 : case '3': // 1 string to match.
10167 0 : if (Mnemonic[15] != '2')
10168 : break;
10169 0 : Mnemonic = "v_cmp_ge_f64"; // "v_cmp_ge_f64_e32"
10170 0 : return;
10171 : case '6': // 1 string to match.
10172 0 : if (Mnemonic[15] != '4')
10173 : break;
10174 0 : Mnemonic = "v_cmp_ge_f64"; // "v_cmp_ge_f64_e64"
10175 0 : return;
10176 : }
10177 : break;
10178 : }
10179 : break;
10180 : case 'i': // 4 strings to match.
10181 0 : switch (Mnemonic[10]) {
10182 : default: break;
10183 : case '3': // 2 strings to match.
10184 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
10185 : break;
10186 0 : switch (Mnemonic[14]) {
10187 : default: break;
10188 : case '3': // 1 string to match.
10189 0 : if (Mnemonic[15] != '2')
10190 : break;
10191 0 : Mnemonic = "v_cmp_ge_i32"; // "v_cmp_ge_i32_e32"
10192 0 : return;
10193 : case '6': // 1 string to match.
10194 0 : if (Mnemonic[15] != '4')
10195 : break;
10196 0 : Mnemonic = "v_cmp_ge_i32"; // "v_cmp_ge_i32_e64"
10197 0 : return;
10198 : }
10199 : break;
10200 : case '6': // 2 strings to match.
10201 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
10202 : break;
10203 0 : switch (Mnemonic[14]) {
10204 : default: break;
10205 : case '3': // 1 string to match.
10206 0 : if (Mnemonic[15] != '2')
10207 : break;
10208 0 : Mnemonic = "v_cmp_ge_i64"; // "v_cmp_ge_i64_e32"
10209 0 : return;
10210 : case '6': // 1 string to match.
10211 0 : if (Mnemonic[15] != '4')
10212 : break;
10213 0 : Mnemonic = "v_cmp_ge_i64"; // "v_cmp_ge_i64_e64"
10214 0 : return;
10215 : }
10216 : break;
10217 : }
10218 : break;
10219 : case 'u': // 4 strings to match.
10220 0 : switch (Mnemonic[10]) {
10221 : default: break;
10222 : case '3': // 2 strings to match.
10223 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
10224 : break;
10225 0 : switch (Mnemonic[14]) {
10226 : default: break;
10227 : case '3': // 1 string to match.
10228 0 : if (Mnemonic[15] != '2')
10229 : break;
10230 0 : Mnemonic = "v_cmp_ge_u32"; // "v_cmp_ge_u32_e32"
10231 0 : return;
10232 : case '6': // 1 string to match.
10233 0 : if (Mnemonic[15] != '4')
10234 : break;
10235 0 : Mnemonic = "v_cmp_ge_u32"; // "v_cmp_ge_u32_e64"
10236 0 : return;
10237 : }
10238 : break;
10239 : case '6': // 2 strings to match.
10240 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
10241 : break;
10242 0 : switch (Mnemonic[14]) {
10243 : default: break;
10244 : case '3': // 1 string to match.
10245 0 : if (Mnemonic[15] != '2')
10246 : break;
10247 0 : Mnemonic = "v_cmp_ge_u64"; // "v_cmp_ge_u64_e32"
10248 0 : return;
10249 : case '6': // 1 string to match.
10250 0 : if (Mnemonic[15] != '4')
10251 : break;
10252 0 : Mnemonic = "v_cmp_ge_u64"; // "v_cmp_ge_u64_e64"
10253 0 : return;
10254 : }
10255 : break;
10256 : }
10257 : break;
10258 : }
10259 : break;
10260 : case 't': // 12 strings to match.
10261 0 : if (Mnemonic[8] != '_')
10262 : break;
10263 0 : switch (Mnemonic[9]) {
10264 : default: break;
10265 : case 'f': // 4 strings to match.
10266 0 : switch (Mnemonic[10]) {
10267 : default: break;
10268 : case '3': // 2 strings to match.
10269 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
10270 : break;
10271 0 : switch (Mnemonic[14]) {
10272 : default: break;
10273 : case '3': // 1 string to match.
10274 0 : if (Mnemonic[15] != '2')
10275 : break;
10276 0 : Mnemonic = "v_cmp_gt_f32"; // "v_cmp_gt_f32_e32"
10277 0 : return;
10278 : case '6': // 1 string to match.
10279 0 : if (Mnemonic[15] != '4')
10280 : break;
10281 0 : Mnemonic = "v_cmp_gt_f32"; // "v_cmp_gt_f32_e64"
10282 0 : return;
10283 : }
10284 : break;
10285 : case '6': // 2 strings to match.
10286 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
10287 : break;
10288 0 : switch (Mnemonic[14]) {
10289 : default: break;
10290 : case '3': // 1 string to match.
10291 0 : if (Mnemonic[15] != '2')
10292 : break;
10293 0 : Mnemonic = "v_cmp_gt_f64"; // "v_cmp_gt_f64_e32"
10294 0 : return;
10295 : case '6': // 1 string to match.
10296 0 : if (Mnemonic[15] != '4')
10297 : break;
10298 0 : Mnemonic = "v_cmp_gt_f64"; // "v_cmp_gt_f64_e64"
10299 0 : return;
10300 : }
10301 : break;
10302 : }
10303 : break;
10304 : case 'i': // 4 strings to match.
10305 0 : switch (Mnemonic[10]) {
10306 : default: break;
10307 : case '3': // 2 strings to match.
10308 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
10309 : break;
10310 0 : switch (Mnemonic[14]) {
10311 : default: break;
10312 : case '3': // 1 string to match.
10313 0 : if (Mnemonic[15] != '2')
10314 : break;
10315 0 : Mnemonic = "v_cmp_gt_i32"; // "v_cmp_gt_i32_e32"
10316 0 : return;
10317 : case '6': // 1 string to match.
10318 0 : if (Mnemonic[15] != '4')
10319 : break;
10320 0 : Mnemonic = "v_cmp_gt_i32"; // "v_cmp_gt_i32_e64"
10321 0 : return;
10322 : }
10323 : break;
10324 : case '6': // 2 strings to match.
10325 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
10326 : break;
10327 0 : switch (Mnemonic[14]) {
10328 : default: break;
10329 : case '3': // 1 string to match.
10330 0 : if (Mnemonic[15] != '2')
10331 : break;
10332 0 : Mnemonic = "v_cmp_gt_i64"; // "v_cmp_gt_i64_e32"
10333 0 : return;
10334 : case '6': // 1 string to match.
10335 0 : if (Mnemonic[15] != '4')
10336 : break;
10337 0 : Mnemonic = "v_cmp_gt_i64"; // "v_cmp_gt_i64_e64"
10338 0 : return;
10339 : }
10340 : break;
10341 : }
10342 : break;
10343 : case 'u': // 4 strings to match.
10344 0 : switch (Mnemonic[10]) {
10345 : default: break;
10346 : case '3': // 2 strings to match.
10347 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
10348 : break;
10349 0 : switch (Mnemonic[14]) {
10350 : default: break;
10351 : case '3': // 1 string to match.
10352 0 : if (Mnemonic[15] != '2')
10353 : break;
10354 0 : Mnemonic = "v_cmp_gt_u32"; // "v_cmp_gt_u32_e32"
10355 0 : return;
10356 : case '6': // 1 string to match.
10357 0 : if (Mnemonic[15] != '4')
10358 : break;
10359 0 : Mnemonic = "v_cmp_gt_u32"; // "v_cmp_gt_u32_e64"
10360 0 : return;
10361 : }
10362 : break;
10363 : case '6': // 2 strings to match.
10364 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
10365 : break;
10366 0 : switch (Mnemonic[14]) {
10367 : default: break;
10368 : case '3': // 1 string to match.
10369 0 : if (Mnemonic[15] != '2')
10370 : break;
10371 0 : Mnemonic = "v_cmp_gt_u64"; // "v_cmp_gt_u64_e32"
10372 0 : return;
10373 : case '6': // 1 string to match.
10374 0 : if (Mnemonic[15] != '4')
10375 : break;
10376 0 : Mnemonic = "v_cmp_gt_u64"; // "v_cmp_gt_u64_e64"
10377 0 : return;
10378 : }
10379 : break;
10380 : }
10381 : break;
10382 : }
10383 : break;
10384 : }
10385 : break;
10386 : case 'l': // 28 strings to match.
10387 0 : switch (Mnemonic[7]) {
10388 : default: break;
10389 : case 'e': // 12 strings to match.
10390 0 : if (Mnemonic[8] != '_')
10391 : break;
10392 0 : switch (Mnemonic[9]) {
10393 : default: break;
10394 : case 'f': // 4 strings to match.
10395 0 : switch (Mnemonic[10]) {
10396 : default: break;
10397 : case '3': // 2 strings to match.
10398 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
10399 : break;
10400 0 : switch (Mnemonic[14]) {
10401 : default: break;
10402 : case '3': // 1 string to match.
10403 0 : if (Mnemonic[15] != '2')
10404 : break;
10405 0 : Mnemonic = "v_cmp_le_f32"; // "v_cmp_le_f32_e32"
10406 0 : return;
10407 : case '6': // 1 string to match.
10408 0 : if (Mnemonic[15] != '4')
10409 : break;
10410 0 : Mnemonic = "v_cmp_le_f32"; // "v_cmp_le_f32_e64"
10411 0 : return;
10412 : }
10413 : break;
10414 : case '6': // 2 strings to match.
10415 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
10416 : break;
10417 0 : switch (Mnemonic[14]) {
10418 : default: break;
10419 : case '3': // 1 string to match.
10420 0 : if (Mnemonic[15] != '2')
10421 : break;
10422 0 : Mnemonic = "v_cmp_le_f64"; // "v_cmp_le_f64_e32"
10423 0 : return;
10424 : case '6': // 1 string to match.
10425 0 : if (Mnemonic[15] != '4')
10426 : break;
10427 0 : Mnemonic = "v_cmp_le_f64"; // "v_cmp_le_f64_e64"
10428 0 : return;
10429 : }
10430 : break;
10431 : }
10432 : break;
10433 : case 'i': // 4 strings to match.
10434 0 : switch (Mnemonic[10]) {
10435 : default: break;
10436 : case '3': // 2 strings to match.
10437 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
10438 : break;
10439 0 : switch (Mnemonic[14]) {
10440 : default: break;
10441 : case '3': // 1 string to match.
10442 0 : if (Mnemonic[15] != '2')
10443 : break;
10444 0 : Mnemonic = "v_cmp_le_i32"; // "v_cmp_le_i32_e32"
10445 0 : return;
10446 : case '6': // 1 string to match.
10447 0 : if (Mnemonic[15] != '4')
10448 : break;
10449 0 : Mnemonic = "v_cmp_le_i32"; // "v_cmp_le_i32_e64"
10450 0 : return;
10451 : }
10452 : break;
10453 : case '6': // 2 strings to match.
10454 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
10455 : break;
10456 0 : switch (Mnemonic[14]) {
10457 : default: break;
10458 : case '3': // 1 string to match.
10459 0 : if (Mnemonic[15] != '2')
10460 : break;
10461 0 : Mnemonic = "v_cmp_le_i64"; // "v_cmp_le_i64_e32"
10462 0 : return;
10463 : case '6': // 1 string to match.
10464 0 : if (Mnemonic[15] != '4')
10465 : break;
10466 0 : Mnemonic = "v_cmp_le_i64"; // "v_cmp_le_i64_e64"
10467 0 : return;
10468 : }
10469 : break;
10470 : }
10471 : break;
10472 : case 'u': // 4 strings to match.
10473 0 : switch (Mnemonic[10]) {
10474 : default: break;
10475 : case '3': // 2 strings to match.
10476 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
10477 : break;
10478 0 : switch (Mnemonic[14]) {
10479 : default: break;
10480 : case '3': // 1 string to match.
10481 0 : if (Mnemonic[15] != '2')
10482 : break;
10483 0 : Mnemonic = "v_cmp_le_u32"; // "v_cmp_le_u32_e32"
10484 0 : return;
10485 : case '6': // 1 string to match.
10486 0 : if (Mnemonic[15] != '4')
10487 : break;
10488 0 : Mnemonic = "v_cmp_le_u32"; // "v_cmp_le_u32_e64"
10489 0 : return;
10490 : }
10491 : break;
10492 : case '6': // 2 strings to match.
10493 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
10494 : break;
10495 0 : switch (Mnemonic[14]) {
10496 : default: break;
10497 : case '3': // 1 string to match.
10498 0 : if (Mnemonic[15] != '2')
10499 : break;
10500 0 : Mnemonic = "v_cmp_le_u64"; // "v_cmp_le_u64_e32"
10501 0 : return;
10502 : case '6': // 1 string to match.
10503 0 : if (Mnemonic[15] != '4')
10504 : break;
10505 0 : Mnemonic = "v_cmp_le_u64"; // "v_cmp_le_u64_e64"
10506 0 : return;
10507 : }
10508 : break;
10509 : }
10510 : break;
10511 : }
10512 : break;
10513 : case 'g': // 4 strings to match.
10514 0 : if (memcmp(Mnemonic.data()+8, "_f", 2))
10515 : break;
10516 0 : switch (Mnemonic[10]) {
10517 : default: break;
10518 : case '3': // 2 strings to match.
10519 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
10520 : break;
10521 0 : switch (Mnemonic[14]) {
10522 : default: break;
10523 : case '3': // 1 string to match.
10524 0 : if (Mnemonic[15] != '2')
10525 : break;
10526 0 : Mnemonic = "v_cmp_lg_f32"; // "v_cmp_lg_f32_e32"
10527 0 : return;
10528 : case '6': // 1 string to match.
10529 0 : if (Mnemonic[15] != '4')
10530 : break;
10531 0 : Mnemonic = "v_cmp_lg_f32"; // "v_cmp_lg_f32_e64"
10532 0 : return;
10533 : }
10534 : break;
10535 : case '6': // 2 strings to match.
10536 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
10537 : break;
10538 0 : switch (Mnemonic[14]) {
10539 : default: break;
10540 : case '3': // 1 string to match.
10541 0 : if (Mnemonic[15] != '2')
10542 : break;
10543 0 : Mnemonic = "v_cmp_lg_f64"; // "v_cmp_lg_f64_e32"
10544 0 : return;
10545 : case '6': // 1 string to match.
10546 0 : if (Mnemonic[15] != '4')
10547 : break;
10548 0 : Mnemonic = "v_cmp_lg_f64"; // "v_cmp_lg_f64_e64"
10549 0 : return;
10550 : }
10551 : break;
10552 : }
10553 : break;
10554 : case 't': // 12 strings to match.
10555 0 : if (Mnemonic[8] != '_')
10556 : break;
10557 0 : switch (Mnemonic[9]) {
10558 : default: break;
10559 : case 'f': // 4 strings to match.
10560 0 : switch (Mnemonic[10]) {
10561 : default: break;
10562 : case '3': // 2 strings to match.
10563 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
10564 : break;
10565 0 : switch (Mnemonic[14]) {
10566 : default: break;
10567 : case '3': // 1 string to match.
10568 0 : if (Mnemonic[15] != '2')
10569 : break;
10570 0 : Mnemonic = "v_cmp_lt_f32"; // "v_cmp_lt_f32_e32"
10571 0 : return;
10572 : case '6': // 1 string to match.
10573 0 : if (Mnemonic[15] != '4')
10574 : break;
10575 0 : Mnemonic = "v_cmp_lt_f32"; // "v_cmp_lt_f32_e64"
10576 0 : return;
10577 : }
10578 : break;
10579 : case '6': // 2 strings to match.
10580 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
10581 : break;
10582 0 : switch (Mnemonic[14]) {
10583 : default: break;
10584 : case '3': // 1 string to match.
10585 0 : if (Mnemonic[15] != '2')
10586 : break;
10587 0 : Mnemonic = "v_cmp_lt_f64"; // "v_cmp_lt_f64_e32"
10588 0 : return;
10589 : case '6': // 1 string to match.
10590 0 : if (Mnemonic[15] != '4')
10591 : break;
10592 0 : Mnemonic = "v_cmp_lt_f64"; // "v_cmp_lt_f64_e64"
10593 0 : return;
10594 : }
10595 : break;
10596 : }
10597 : break;
10598 : case 'i': // 4 strings to match.
10599 0 : switch (Mnemonic[10]) {
10600 : default: break;
10601 : case '3': // 2 strings to match.
10602 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
10603 : break;
10604 0 : switch (Mnemonic[14]) {
10605 : default: break;
10606 : case '3': // 1 string to match.
10607 0 : if (Mnemonic[15] != '2')
10608 : break;
10609 0 : Mnemonic = "v_cmp_lt_i32"; // "v_cmp_lt_i32_e32"
10610 0 : return;
10611 : case '6': // 1 string to match.
10612 0 : if (Mnemonic[15] != '4')
10613 : break;
10614 0 : Mnemonic = "v_cmp_lt_i32"; // "v_cmp_lt_i32_e64"
10615 0 : return;
10616 : }
10617 : break;
10618 : case '6': // 2 strings to match.
10619 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
10620 : break;
10621 0 : switch (Mnemonic[14]) {
10622 : default: break;
10623 : case '3': // 1 string to match.
10624 0 : if (Mnemonic[15] != '2')
10625 : break;
10626 0 : Mnemonic = "v_cmp_lt_i64"; // "v_cmp_lt_i64_e32"
10627 0 : return;
10628 : case '6': // 1 string to match.
10629 0 : if (Mnemonic[15] != '4')
10630 : break;
10631 0 : Mnemonic = "v_cmp_lt_i64"; // "v_cmp_lt_i64_e64"
10632 0 : return;
10633 : }
10634 : break;
10635 : }
10636 : break;
10637 : case 'u': // 4 strings to match.
10638 0 : switch (Mnemonic[10]) {
10639 : default: break;
10640 : case '3': // 2 strings to match.
10641 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
10642 : break;
10643 0 : switch (Mnemonic[14]) {
10644 : default: break;
10645 : case '3': // 1 string to match.
10646 0 : if (Mnemonic[15] != '2')
10647 : break;
10648 0 : Mnemonic = "v_cmp_lt_u32"; // "v_cmp_lt_u32_e32"
10649 0 : return;
10650 : case '6': // 1 string to match.
10651 0 : if (Mnemonic[15] != '4')
10652 : break;
10653 0 : Mnemonic = "v_cmp_lt_u32"; // "v_cmp_lt_u32_e64"
10654 0 : return;
10655 : }
10656 : break;
10657 : case '6': // 2 strings to match.
10658 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
10659 : break;
10660 0 : switch (Mnemonic[14]) {
10661 : default: break;
10662 : case '3': // 1 string to match.
10663 0 : if (Mnemonic[15] != '2')
10664 : break;
10665 0 : Mnemonic = "v_cmp_lt_u64"; // "v_cmp_lt_u64_e32"
10666 0 : return;
10667 : case '6': // 1 string to match.
10668 0 : if (Mnemonic[15] != '4')
10669 : break;
10670 0 : Mnemonic = "v_cmp_lt_u64"; // "v_cmp_lt_u64_e64"
10671 0 : return;
10672 : }
10673 : break;
10674 : }
10675 : break;
10676 : }
10677 : break;
10678 : }
10679 : break;
10680 : case 'n': // 8 strings to match.
10681 0 : if (memcmp(Mnemonic.data()+7, "e_", 2))
10682 : break;
10683 0 : switch (Mnemonic[9]) {
10684 : default: break;
10685 : case 'i': // 4 strings to match.
10686 0 : switch (Mnemonic[10]) {
10687 : default: break;
10688 : case '3': // 2 strings to match.
10689 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
10690 : break;
10691 0 : switch (Mnemonic[14]) {
10692 : default: break;
10693 : case '3': // 1 string to match.
10694 0 : if (Mnemonic[15] != '2')
10695 : break;
10696 0 : Mnemonic = "v_cmp_ne_i32"; // "v_cmp_ne_i32_e32"
10697 0 : return;
10698 : case '6': // 1 string to match.
10699 0 : if (Mnemonic[15] != '4')
10700 : break;
10701 0 : Mnemonic = "v_cmp_ne_i32"; // "v_cmp_ne_i32_e64"
10702 0 : return;
10703 : }
10704 : break;
10705 : case '6': // 2 strings to match.
10706 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
10707 : break;
10708 0 : switch (Mnemonic[14]) {
10709 : default: break;
10710 : case '3': // 1 string to match.
10711 0 : if (Mnemonic[15] != '2')
10712 : break;
10713 0 : Mnemonic = "v_cmp_ne_i64"; // "v_cmp_ne_i64_e32"
10714 0 : return;
10715 : case '6': // 1 string to match.
10716 0 : if (Mnemonic[15] != '4')
10717 : break;
10718 0 : Mnemonic = "v_cmp_ne_i64"; // "v_cmp_ne_i64_e64"
10719 0 : return;
10720 : }
10721 : break;
10722 : }
10723 : break;
10724 : case 'u': // 4 strings to match.
10725 0 : switch (Mnemonic[10]) {
10726 : default: break;
10727 : case '3': // 2 strings to match.
10728 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
10729 : break;
10730 0 : switch (Mnemonic[14]) {
10731 : default: break;
10732 : case '3': // 1 string to match.
10733 0 : if (Mnemonic[15] != '2')
10734 : break;
10735 0 : Mnemonic = "v_cmp_ne_u32"; // "v_cmp_ne_u32_e32"
10736 0 : return;
10737 : case '6': // 1 string to match.
10738 0 : if (Mnemonic[15] != '4')
10739 : break;
10740 0 : Mnemonic = "v_cmp_ne_u32"; // "v_cmp_ne_u32_e64"
10741 0 : return;
10742 : }
10743 : break;
10744 : case '6': // 2 strings to match.
10745 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
10746 : break;
10747 0 : switch (Mnemonic[14]) {
10748 : default: break;
10749 : case '3': // 1 string to match.
10750 0 : if (Mnemonic[15] != '2')
10751 : break;
10752 0 : Mnemonic = "v_cmp_ne_u64"; // "v_cmp_ne_u64_e32"
10753 0 : return;
10754 : case '6': // 1 string to match.
10755 0 : if (Mnemonic[15] != '4')
10756 : break;
10757 0 : Mnemonic = "v_cmp_ne_u64"; // "v_cmp_ne_u64_e64"
10758 0 : return;
10759 : }
10760 : break;
10761 : }
10762 : break;
10763 : }
10764 : break;
10765 : }
10766 : break;
10767 : case 's': // 12 strings to match.
10768 0 : if (Mnemonic[6] != '_')
10769 : break;
10770 0 : switch (Mnemonic[7]) {
10771 : default: break;
10772 : case 'f': // 4 strings to match.
10773 0 : if (memcmp(Mnemonic.data()+8, "_f", 2))
10774 : break;
10775 0 : switch (Mnemonic[10]) {
10776 : default: break;
10777 : case '3': // 2 strings to match.
10778 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
10779 : break;
10780 0 : switch (Mnemonic[14]) {
10781 : default: break;
10782 : case '3': // 1 string to match.
10783 0 : if (Mnemonic[15] != '2')
10784 : break;
10785 0 : Mnemonic = "v_cmps_f_f32"; // "v_cmps_f_f32_e32"
10786 0 : return;
10787 : case '6': // 1 string to match.
10788 0 : if (Mnemonic[15] != '4')
10789 : break;
10790 0 : Mnemonic = "v_cmps_f_f32"; // "v_cmps_f_f32_e64"
10791 0 : return;
10792 : }
10793 : break;
10794 : case '6': // 2 strings to match.
10795 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
10796 : break;
10797 0 : switch (Mnemonic[14]) {
10798 : default: break;
10799 : case '3': // 1 string to match.
10800 0 : if (Mnemonic[15] != '2')
10801 : break;
10802 0 : Mnemonic = "v_cmps_f_f64"; // "v_cmps_f_f64_e32"
10803 0 : return;
10804 : case '6': // 1 string to match.
10805 0 : if (Mnemonic[15] != '4')
10806 : break;
10807 0 : Mnemonic = "v_cmps_f_f64"; // "v_cmps_f_f64_e64"
10808 0 : return;
10809 : }
10810 : break;
10811 : }
10812 : break;
10813 : case 'o': // 4 strings to match.
10814 0 : if (memcmp(Mnemonic.data()+8, "_f", 2))
10815 : break;
10816 0 : switch (Mnemonic[10]) {
10817 : default: break;
10818 : case '3': // 2 strings to match.
10819 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
10820 : break;
10821 0 : switch (Mnemonic[14]) {
10822 : default: break;
10823 : case '3': // 1 string to match.
10824 0 : if (Mnemonic[15] != '2')
10825 : break;
10826 0 : Mnemonic = "v_cmps_o_f32"; // "v_cmps_o_f32_e32"
10827 0 : return;
10828 : case '6': // 1 string to match.
10829 0 : if (Mnemonic[15] != '4')
10830 : break;
10831 0 : Mnemonic = "v_cmps_o_f32"; // "v_cmps_o_f32_e64"
10832 0 : return;
10833 : }
10834 : break;
10835 : case '6': // 2 strings to match.
10836 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
10837 : break;
10838 0 : switch (Mnemonic[14]) {
10839 : default: break;
10840 : case '3': // 1 string to match.
10841 0 : if (Mnemonic[15] != '2')
10842 : break;
10843 0 : Mnemonic = "v_cmps_o_f64"; // "v_cmps_o_f64_e32"
10844 0 : return;
10845 : case '6': // 1 string to match.
10846 0 : if (Mnemonic[15] != '4')
10847 : break;
10848 0 : Mnemonic = "v_cmps_o_f64"; // "v_cmps_o_f64_e64"
10849 0 : return;
10850 : }
10851 : break;
10852 : }
10853 : break;
10854 : case 'u': // 4 strings to match.
10855 0 : if (memcmp(Mnemonic.data()+8, "_f", 2))
10856 : break;
10857 0 : switch (Mnemonic[10]) {
10858 : default: break;
10859 : case '3': // 2 strings to match.
10860 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
10861 : break;
10862 0 : switch (Mnemonic[14]) {
10863 : default: break;
10864 : case '3': // 1 string to match.
10865 0 : if (Mnemonic[15] != '2')
10866 : break;
10867 0 : Mnemonic = "v_cmps_u_f32"; // "v_cmps_u_f32_e32"
10868 0 : return;
10869 : case '6': // 1 string to match.
10870 0 : if (Mnemonic[15] != '4')
10871 : break;
10872 0 : Mnemonic = "v_cmps_u_f32"; // "v_cmps_u_f32_e64"
10873 0 : return;
10874 : }
10875 : break;
10876 : case '6': // 2 strings to match.
10877 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
10878 : break;
10879 0 : switch (Mnemonic[14]) {
10880 : default: break;
10881 : case '3': // 1 string to match.
10882 0 : if (Mnemonic[15] != '2')
10883 : break;
10884 0 : Mnemonic = "v_cmps_u_f64"; // "v_cmps_u_f64_e32"
10885 0 : return;
10886 : case '6': // 1 string to match.
10887 0 : if (Mnemonic[15] != '4')
10888 : break;
10889 0 : Mnemonic = "v_cmps_u_f64"; // "v_cmps_u_f64_e64"
10890 0 : return;
10891 : }
10892 : break;
10893 : }
10894 : break;
10895 : }
10896 : break;
10897 : case 'x': // 28 strings to match.
10898 0 : if (Mnemonic[6] != '_')
10899 : break;
10900 0 : switch (Mnemonic[7]) {
10901 : default: break;
10902 : case 'f': // 12 strings to match.
10903 0 : if (Mnemonic[8] != '_')
10904 : break;
10905 0 : switch (Mnemonic[9]) {
10906 : default: break;
10907 : case 'f': // 4 strings to match.
10908 0 : switch (Mnemonic[10]) {
10909 : default: break;
10910 : case '3': // 2 strings to match.
10911 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
10912 : break;
10913 0 : switch (Mnemonic[14]) {
10914 : default: break;
10915 : case '3': // 1 string to match.
10916 0 : if (Mnemonic[15] != '2')
10917 : break;
10918 0 : Mnemonic = "v_cmpx_f_f32"; // "v_cmpx_f_f32_e32"
10919 0 : return;
10920 : case '6': // 1 string to match.
10921 0 : if (Mnemonic[15] != '4')
10922 : break;
10923 0 : Mnemonic = "v_cmpx_f_f32"; // "v_cmpx_f_f32_e64"
10924 0 : return;
10925 : }
10926 : break;
10927 : case '6': // 2 strings to match.
10928 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
10929 : break;
10930 0 : switch (Mnemonic[14]) {
10931 : default: break;
10932 : case '3': // 1 string to match.
10933 0 : if (Mnemonic[15] != '2')
10934 : break;
10935 0 : Mnemonic = "v_cmpx_f_f64"; // "v_cmpx_f_f64_e32"
10936 0 : return;
10937 : case '6': // 1 string to match.
10938 0 : if (Mnemonic[15] != '4')
10939 : break;
10940 0 : Mnemonic = "v_cmpx_f_f64"; // "v_cmpx_f_f64_e64"
10941 0 : return;
10942 : }
10943 : break;
10944 : }
10945 : break;
10946 : case 'i': // 4 strings to match.
10947 0 : switch (Mnemonic[10]) {
10948 : default: break;
10949 : case '3': // 2 strings to match.
10950 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
10951 : break;
10952 0 : switch (Mnemonic[14]) {
10953 : default: break;
10954 : case '3': // 1 string to match.
10955 0 : if (Mnemonic[15] != '2')
10956 : break;
10957 0 : Mnemonic = "v_cmpx_f_i32"; // "v_cmpx_f_i32_e32"
10958 0 : return;
10959 : case '6': // 1 string to match.
10960 0 : if (Mnemonic[15] != '4')
10961 : break;
10962 0 : Mnemonic = "v_cmpx_f_i32"; // "v_cmpx_f_i32_e64"
10963 0 : return;
10964 : }
10965 : break;
10966 : case '6': // 2 strings to match.
10967 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
10968 : break;
10969 0 : switch (Mnemonic[14]) {
10970 : default: break;
10971 : case '3': // 1 string to match.
10972 0 : if (Mnemonic[15] != '2')
10973 : break;
10974 0 : Mnemonic = "v_cmpx_f_i64"; // "v_cmpx_f_i64_e32"
10975 0 : return;
10976 : case '6': // 1 string to match.
10977 0 : if (Mnemonic[15] != '4')
10978 : break;
10979 0 : Mnemonic = "v_cmpx_f_i64"; // "v_cmpx_f_i64_e64"
10980 0 : return;
10981 : }
10982 : break;
10983 : }
10984 : break;
10985 : case 'u': // 4 strings to match.
10986 0 : switch (Mnemonic[10]) {
10987 : default: break;
10988 : case '3': // 2 strings to match.
10989 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
10990 : break;
10991 0 : switch (Mnemonic[14]) {
10992 : default: break;
10993 : case '3': // 1 string to match.
10994 0 : if (Mnemonic[15] != '2')
10995 : break;
10996 0 : Mnemonic = "v_cmpx_f_u32"; // "v_cmpx_f_u32_e32"
10997 0 : return;
10998 : case '6': // 1 string to match.
10999 0 : if (Mnemonic[15] != '4')
11000 : break;
11001 0 : Mnemonic = "v_cmpx_f_u32"; // "v_cmpx_f_u32_e64"
11002 0 : return;
11003 : }
11004 : break;
11005 : case '6': // 2 strings to match.
11006 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
11007 : break;
11008 0 : switch (Mnemonic[14]) {
11009 : default: break;
11010 : case '3': // 1 string to match.
11011 0 : if (Mnemonic[15] != '2')
11012 : break;
11013 0 : Mnemonic = "v_cmpx_f_u64"; // "v_cmpx_f_u64_e32"
11014 0 : return;
11015 : case '6': // 1 string to match.
11016 0 : if (Mnemonic[15] != '4')
11017 : break;
11018 0 : Mnemonic = "v_cmpx_f_u64"; // "v_cmpx_f_u64_e64"
11019 0 : return;
11020 : }
11021 : break;
11022 : }
11023 : break;
11024 : }
11025 : break;
11026 : case 'o': // 4 strings to match.
11027 0 : if (memcmp(Mnemonic.data()+8, "_f", 2))
11028 : break;
11029 0 : switch (Mnemonic[10]) {
11030 : default: break;
11031 : case '3': // 2 strings to match.
11032 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
11033 : break;
11034 0 : switch (Mnemonic[14]) {
11035 : default: break;
11036 : case '3': // 1 string to match.
11037 0 : if (Mnemonic[15] != '2')
11038 : break;
11039 0 : Mnemonic = "v_cmpx_o_f32"; // "v_cmpx_o_f32_e32"
11040 0 : return;
11041 : case '6': // 1 string to match.
11042 0 : if (Mnemonic[15] != '4')
11043 : break;
11044 0 : Mnemonic = "v_cmpx_o_f32"; // "v_cmpx_o_f32_e64"
11045 0 : return;
11046 : }
11047 : break;
11048 : case '6': // 2 strings to match.
11049 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
11050 : break;
11051 0 : switch (Mnemonic[14]) {
11052 : default: break;
11053 : case '3': // 1 string to match.
11054 0 : if (Mnemonic[15] != '2')
11055 : break;
11056 0 : Mnemonic = "v_cmpx_o_f64"; // "v_cmpx_o_f64_e32"
11057 0 : return;
11058 : case '6': // 1 string to match.
11059 0 : if (Mnemonic[15] != '4')
11060 : break;
11061 0 : Mnemonic = "v_cmpx_o_f64"; // "v_cmpx_o_f64_e64"
11062 0 : return;
11063 : }
11064 : break;
11065 : }
11066 : break;
11067 : case 't': // 8 strings to match.
11068 0 : if (Mnemonic[8] != '_')
11069 : break;
11070 0 : switch (Mnemonic[9]) {
11071 : default: break;
11072 : case 'i': // 4 strings to match.
11073 0 : switch (Mnemonic[10]) {
11074 : default: break;
11075 : case '3': // 2 strings to match.
11076 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
11077 : break;
11078 0 : switch (Mnemonic[14]) {
11079 : default: break;
11080 : case '3': // 1 string to match.
11081 0 : if (Mnemonic[15] != '2')
11082 : break;
11083 0 : Mnemonic = "v_cmpx_t_i32"; // "v_cmpx_t_i32_e32"
11084 0 : return;
11085 : case '6': // 1 string to match.
11086 0 : if (Mnemonic[15] != '4')
11087 : break;
11088 0 : Mnemonic = "v_cmpx_t_i32"; // "v_cmpx_t_i32_e64"
11089 0 : return;
11090 : }
11091 : break;
11092 : case '6': // 2 strings to match.
11093 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
11094 : break;
11095 0 : switch (Mnemonic[14]) {
11096 : default: break;
11097 : case '3': // 1 string to match.
11098 0 : if (Mnemonic[15] != '2')
11099 : break;
11100 0 : Mnemonic = "v_cmpx_t_i64"; // "v_cmpx_t_i64_e32"
11101 0 : return;
11102 : case '6': // 1 string to match.
11103 0 : if (Mnemonic[15] != '4')
11104 : break;
11105 0 : Mnemonic = "v_cmpx_t_i64"; // "v_cmpx_t_i64_e64"
11106 0 : return;
11107 : }
11108 : break;
11109 : }
11110 : break;
11111 : case 'u': // 4 strings to match.
11112 0 : switch (Mnemonic[10]) {
11113 : default: break;
11114 : case '3': // 2 strings to match.
11115 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
11116 : break;
11117 0 : switch (Mnemonic[14]) {
11118 : default: break;
11119 : case '3': // 1 string to match.
11120 0 : if (Mnemonic[15] != '2')
11121 : break;
11122 0 : Mnemonic = "v_cmpx_t_u32"; // "v_cmpx_t_u32_e32"
11123 0 : return;
11124 : case '6': // 1 string to match.
11125 0 : if (Mnemonic[15] != '4')
11126 : break;
11127 0 : Mnemonic = "v_cmpx_t_u32"; // "v_cmpx_t_u32_e64"
11128 0 : return;
11129 : }
11130 : break;
11131 : case '6': // 2 strings to match.
11132 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
11133 : break;
11134 0 : switch (Mnemonic[14]) {
11135 : default: break;
11136 : case '3': // 1 string to match.
11137 0 : if (Mnemonic[15] != '2')
11138 : break;
11139 0 : Mnemonic = "v_cmpx_t_u64"; // "v_cmpx_t_u64_e32"
11140 0 : return;
11141 : case '6': // 1 string to match.
11142 0 : if (Mnemonic[15] != '4')
11143 : break;
11144 0 : Mnemonic = "v_cmpx_t_u64"; // "v_cmpx_t_u64_e64"
11145 0 : return;
11146 : }
11147 : break;
11148 : }
11149 : break;
11150 : }
11151 : break;
11152 : case 'u': // 4 strings to match.
11153 0 : if (memcmp(Mnemonic.data()+8, "_f", 2))
11154 : break;
11155 0 : switch (Mnemonic[10]) {
11156 : default: break;
11157 : case '3': // 2 strings to match.
11158 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
11159 : break;
11160 0 : switch (Mnemonic[14]) {
11161 : default: break;
11162 : case '3': // 1 string to match.
11163 0 : if (Mnemonic[15] != '2')
11164 : break;
11165 0 : Mnemonic = "v_cmpx_u_f32"; // "v_cmpx_u_f32_e32"
11166 0 : return;
11167 : case '6': // 1 string to match.
11168 0 : if (Mnemonic[15] != '4')
11169 : break;
11170 0 : Mnemonic = "v_cmpx_u_f32"; // "v_cmpx_u_f32_e64"
11171 0 : return;
11172 : }
11173 : break;
11174 : case '6': // 2 strings to match.
11175 0 : if (memcmp(Mnemonic.data()+11, "4_e", 3))
11176 : break;
11177 0 : switch (Mnemonic[14]) {
11178 : default: break;
11179 : case '3': // 1 string to match.
11180 0 : if (Mnemonic[15] != '2')
11181 : break;
11182 0 : Mnemonic = "v_cmpx_u_f64"; // "v_cmpx_u_f64_e32"
11183 0 : return;
11184 : case '6': // 1 string to match.
11185 0 : if (Mnemonic[15] != '4')
11186 : break;
11187 0 : Mnemonic = "v_cmpx_u_f64"; // "v_cmpx_u_f64_e64"
11188 0 : return;
11189 : }
11190 : break;
11191 : }
11192 : break;
11193 : }
11194 : break;
11195 : }
11196 : break;
11197 : case 'u': // 4 strings to match.
11198 0 : if (memcmp(Mnemonic.data()+4, "be", 2))
11199 : break;
11200 0 : switch (Mnemonic[6]) {
11201 : default: break;
11202 : case 'i': // 1 string to match.
11203 0 : if (memcmp(Mnemonic.data()+7, "d_f32_e64", 9))
11204 : break;
11205 0 : Mnemonic = "v_cubeid_f32"; // "v_cubeid_f32_e64"
11206 0 : return;
11207 : case 'm': // 1 string to match.
11208 0 : if (memcmp(Mnemonic.data()+7, "a_f32_e64", 9))
11209 : break;
11210 0 : Mnemonic = "v_cubema_f32"; // "v_cubema_f32_e64"
11211 0 : return;
11212 : case 's': // 1 string to match.
11213 0 : if (memcmp(Mnemonic.data()+7, "c_f32_e64", 9))
11214 : break;
11215 0 : Mnemonic = "v_cubesc_f32"; // "v_cubesc_f32_e64"
11216 0 : return;
11217 : case 't': // 1 string to match.
11218 0 : if (memcmp(Mnemonic.data()+7, "c_f32_e64", 9))
11219 : break;
11220 0 : Mnemonic = "v_cubetc_f32"; // "v_cubetc_f32_e64"
11221 0 : return;
11222 : }
11223 : break;
11224 : }
11225 : break;
11226 : case 'm': // 7 strings to match.
11227 38 : if (memcmp(Mnemonic.data()+3, "ul", 2))
11228 : break;
11229 36 : switch (Mnemonic[5]) {
11230 : default: break;
11231 : case '_': // 6 strings to match.
11232 36 : switch (Mnemonic[6]) {
11233 : default: break;
11234 : case 'h': // 2 strings to match.
11235 16 : if (memcmp(Mnemonic.data()+7, "i_", 2))
11236 : break;
11237 32 : switch (Mnemonic[9]) {
11238 : default: break;
11239 : case 'i': // 1 string to match.
11240 8 : if (memcmp(Mnemonic.data()+10, "32_e64", 6))
11241 : break;
11242 0 : Mnemonic = "v_mul_hi_i32"; // "v_mul_hi_i32_e64"
11243 0 : return;
11244 : case 'u': // 1 string to match.
11245 8 : if (memcmp(Mnemonic.data()+10, "32_e64", 6))
11246 : break;
11247 0 : Mnemonic = "v_mul_hi_u32"; // "v_mul_hi_u32_e64"
11248 0 : return;
11249 : }
11250 : break;
11251 : case 'l': // 4 strings to match.
11252 2 : if (memcmp(Mnemonic.data()+7, "o_", 2))
11253 : break;
11254 0 : switch (Mnemonic[9]) {
11255 : default: break;
11256 : case 'i': // 1 string to match.
11257 0 : if (memcmp(Mnemonic.data()+10, "32_e64", 6))
11258 : break;
11259 0 : Mnemonic = "v_mul_lo_i32"; // "v_mul_lo_i32_e64"
11260 0 : return;
11261 : case 'u': // 3 strings to match.
11262 0 : switch (Mnemonic[10]) {
11263 : default: break;
11264 : case '1': // 2 strings to match.
11265 0 : if (memcmp(Mnemonic.data()+11, "6_e", 3))
11266 : break;
11267 0 : switch (Mnemonic[14]) {
11268 : default: break;
11269 : case '3': // 1 string to match.
11270 0 : if (Mnemonic[15] != '2')
11271 : break;
11272 0 : Mnemonic = "v_mul_lo_u16"; // "v_mul_lo_u16_e32"
11273 0 : return;
11274 : case '6': // 1 string to match.
11275 0 : if (Mnemonic[15] != '4')
11276 : break;
11277 0 : Mnemonic = "v_mul_lo_u16"; // "v_mul_lo_u16_e64"
11278 0 : return;
11279 : }
11280 : break;
11281 : case '3': // 1 string to match.
11282 0 : if (memcmp(Mnemonic.data()+11, "2_e64", 5))
11283 : break;
11284 0 : Mnemonic = "v_mul_lo_u32"; // "v_mul_lo_u32_e64"
11285 0 : return;
11286 : }
11287 : break;
11288 : }
11289 : break;
11290 : }
11291 : break;
11292 : case 'l': // 1 string to match.
11293 0 : if (memcmp(Mnemonic.data()+6, "it_f32_e64", 10))
11294 : break;
11295 0 : Mnemonic = "v_mullit_f32"; // "v_mullit_f32_e64"
11296 0 : return;
11297 : }
11298 : break;
11299 : case 's': // 8 strings to match.
11300 0 : if (memcmp(Mnemonic.data()+3, "ubrev_", 6))
11301 : break;
11302 0 : switch (Mnemonic[9]) {
11303 : default: break;
11304 : case 'f': // 4 strings to match.
11305 0 : switch (Mnemonic[10]) {
11306 : default: break;
11307 : case '1': // 2 strings to match.
11308 0 : if (memcmp(Mnemonic.data()+11, "6_e", 3))
11309 : break;
11310 0 : switch (Mnemonic[14]) {
11311 : default: break;
11312 : case '3': // 1 string to match.
11313 0 : if (Mnemonic[15] != '2')
11314 : break;
11315 0 : Mnemonic = "v_subrev_f16"; // "v_subrev_f16_e32"
11316 0 : return;
11317 : case '6': // 1 string to match.
11318 0 : if (Mnemonic[15] != '4')
11319 : break;
11320 0 : Mnemonic = "v_subrev_f16"; // "v_subrev_f16_e64"
11321 0 : return;
11322 : }
11323 : break;
11324 : case '3': // 2 strings to match.
11325 0 : if (memcmp(Mnemonic.data()+11, "2_e", 3))
11326 : break;
11327 0 : switch (Mnemonic[14]) {
11328 : default: break;
11329 : case '3': // 1 string to match.
11330 0 : if (Mnemonic[15] != '2')
11331 : break;
11332 0 : Mnemonic = "v_subrev_f32"; // "v_subrev_f32_e32"
11333 0 : return;
11334 : case '6': // 1 string to match.
11335 0 : if (Mnemonic[15] != '4')
11336 : break;
11337 0 : Mnemonic = "v_subrev_f32"; // "v_subrev_f32_e64"
11338 0 : return;
11339 : }
11340 : break;
11341 : }
11342 : break;
11343 : case 'i': // 2 strings to match.
11344 0 : if (memcmp(Mnemonic.data()+10, "32_e", 4))
11345 : break;
11346 0 : switch (Mnemonic[14]) {
11347 : default: break;
11348 : case '3': // 1 string to match.
11349 0 : if (Mnemonic[15] != '2')
11350 : break;
11351 0 : Mnemonic = "v_subrev_i32"; // "v_subrev_i32_e32"
11352 0 : return;
11353 : case '6': // 1 string to match.
11354 0 : if (Mnemonic[15] != '4')
11355 : break;
11356 0 : Mnemonic = "v_subrev_i32"; // "v_subrev_i32_e64"
11357 0 : return;
11358 : }
11359 : break;
11360 : case 'u': // 2 strings to match.
11361 0 : if (memcmp(Mnemonic.data()+10, "16_e", 4))
11362 : break;
11363 0 : switch (Mnemonic[14]) {
11364 : default: break;
11365 : case '3': // 1 string to match.
11366 0 : if (Mnemonic[15] != '2')
11367 : break;
11368 0 : Mnemonic = "v_subrev_u16"; // "v_subrev_u16_e32"
11369 0 : return;
11370 : case '6': // 1 string to match.
11371 0 : if (Mnemonic[15] != '4')
11372 : break;
11373 0 : Mnemonic = "v_subrev_u16"; // "v_subrev_u16_e64"
11374 0 : return;
11375 : }
11376 : break;
11377 : }
11378 : break;
11379 : }
11380 : break;
11381 : case 17: // 201 strings to match.
11382 114 : if (memcmp(Mnemonic.data()+0, "v_", 2))
11383 : break;
11384 32 : switch (Mnemonic[2]) {
11385 : default: break;
11386 : case 'a': // 5 strings to match.
11387 0 : if (memcmp(Mnemonic.data()+3, "shrrev_", 7))
11388 : break;
11389 0 : switch (Mnemonic[10]) {
11390 : default: break;
11391 : case 'b': // 2 strings to match.
11392 0 : if (memcmp(Mnemonic.data()+11, "16_e", 4))
11393 : break;
11394 0 : switch (Mnemonic[15]) {
11395 : default: break;
11396 : case '3': // 1 string to match.
11397 0 : if (Mnemonic[16] != '2')
11398 : break;
11399 0 : Mnemonic = "v_ashrrev_b16"; // "v_ashrrev_b16_e32"
11400 0 : return;
11401 : case '6': // 1 string to match.
11402 0 : if (Mnemonic[16] != '4')
11403 : break;
11404 0 : Mnemonic = "v_ashrrev_b16"; // "v_ashrrev_b16_e64"
11405 0 : return;
11406 : }
11407 : break;
11408 : case 'i': // 3 strings to match.
11409 0 : switch (Mnemonic[11]) {
11410 : default: break;
11411 : case '3': // 2 strings to match.
11412 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
11413 : break;
11414 0 : switch (Mnemonic[15]) {
11415 : default: break;
11416 : case '3': // 1 string to match.
11417 0 : if (Mnemonic[16] != '2')
11418 : break;
11419 0 : Mnemonic = "v_ashrrev_i32"; // "v_ashrrev_i32_e32"
11420 0 : return;
11421 : case '6': // 1 string to match.
11422 0 : if (Mnemonic[16] != '4')
11423 : break;
11424 0 : Mnemonic = "v_ashrrev_i32"; // "v_ashrrev_i32_e64"
11425 0 : return;
11426 : }
11427 : break;
11428 : case '6': // 1 string to match.
11429 0 : if (memcmp(Mnemonic.data()+12, "4_e64", 5))
11430 : break;
11431 0 : Mnemonic = "v_ashrrev_i64"; // "v_ashrrev_i64_e64"
11432 0 : return;
11433 : }
11434 : break;
11435 : }
11436 : break;
11437 : case 'c': // 170 strings to match.
11438 32 : switch (Mnemonic[3]) {
11439 : default: break;
11440 : case 'm': // 136 strings to match.
11441 0 : if (Mnemonic[4] != 'p')
11442 : break;
11443 0 : switch (Mnemonic[5]) {
11444 : default: break;
11445 : case '_': // 28 strings to match.
11446 0 : switch (Mnemonic[6]) {
11447 : default: break;
11448 : case 'n': // 24 strings to match.
11449 0 : switch (Mnemonic[7]) {
11450 : default: break;
11451 : case 'e': // 4 strings to match.
11452 0 : if (memcmp(Mnemonic.data()+8, "q_f", 3))
11453 : break;
11454 0 : switch (Mnemonic[11]) {
11455 : default: break;
11456 : case '3': // 2 strings to match.
11457 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
11458 : break;
11459 0 : switch (Mnemonic[15]) {
11460 : default: break;
11461 : case '3': // 1 string to match.
11462 0 : if (Mnemonic[16] != '2')
11463 : break;
11464 0 : Mnemonic = "v_cmp_neq_f32"; // "v_cmp_neq_f32_e32"
11465 0 : return;
11466 : case '6': // 1 string to match.
11467 0 : if (Mnemonic[16] != '4')
11468 : break;
11469 0 : Mnemonic = "v_cmp_neq_f32"; // "v_cmp_neq_f32_e64"
11470 0 : return;
11471 : }
11472 : break;
11473 : case '6': // 2 strings to match.
11474 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
11475 : break;
11476 0 : switch (Mnemonic[15]) {
11477 : default: break;
11478 : case '3': // 1 string to match.
11479 0 : if (Mnemonic[16] != '2')
11480 : break;
11481 0 : Mnemonic = "v_cmp_neq_f64"; // "v_cmp_neq_f64_e32"
11482 0 : return;
11483 : case '6': // 1 string to match.
11484 0 : if (Mnemonic[16] != '4')
11485 : break;
11486 0 : Mnemonic = "v_cmp_neq_f64"; // "v_cmp_neq_f64_e64"
11487 0 : return;
11488 : }
11489 : break;
11490 : }
11491 : break;
11492 : case 'g': // 8 strings to match.
11493 0 : switch (Mnemonic[8]) {
11494 : default: break;
11495 : case 'e': // 4 strings to match.
11496 0 : if (memcmp(Mnemonic.data()+9, "_f", 2))
11497 : break;
11498 0 : switch (Mnemonic[11]) {
11499 : default: break;
11500 : case '3': // 2 strings to match.
11501 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
11502 : break;
11503 0 : switch (Mnemonic[15]) {
11504 : default: break;
11505 : case '3': // 1 string to match.
11506 0 : if (Mnemonic[16] != '2')
11507 : break;
11508 0 : Mnemonic = "v_cmp_nge_f32"; // "v_cmp_nge_f32_e32"
11509 0 : return;
11510 : case '6': // 1 string to match.
11511 0 : if (Mnemonic[16] != '4')
11512 : break;
11513 0 : Mnemonic = "v_cmp_nge_f32"; // "v_cmp_nge_f32_e64"
11514 0 : return;
11515 : }
11516 : break;
11517 : case '6': // 2 strings to match.
11518 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
11519 : break;
11520 0 : switch (Mnemonic[15]) {
11521 : default: break;
11522 : case '3': // 1 string to match.
11523 0 : if (Mnemonic[16] != '2')
11524 : break;
11525 0 : Mnemonic = "v_cmp_nge_f64"; // "v_cmp_nge_f64_e32"
11526 0 : return;
11527 : case '6': // 1 string to match.
11528 0 : if (Mnemonic[16] != '4')
11529 : break;
11530 0 : Mnemonic = "v_cmp_nge_f64"; // "v_cmp_nge_f64_e64"
11531 0 : return;
11532 : }
11533 : break;
11534 : }
11535 : break;
11536 : case 't': // 4 strings to match.
11537 0 : if (memcmp(Mnemonic.data()+9, "_f", 2))
11538 : break;
11539 0 : switch (Mnemonic[11]) {
11540 : default: break;
11541 : case '3': // 2 strings to match.
11542 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
11543 : break;
11544 0 : switch (Mnemonic[15]) {
11545 : default: break;
11546 : case '3': // 1 string to match.
11547 0 : if (Mnemonic[16] != '2')
11548 : break;
11549 0 : Mnemonic = "v_cmp_ngt_f32"; // "v_cmp_ngt_f32_e32"
11550 0 : return;
11551 : case '6': // 1 string to match.
11552 0 : if (Mnemonic[16] != '4')
11553 : break;
11554 0 : Mnemonic = "v_cmp_ngt_f32"; // "v_cmp_ngt_f32_e64"
11555 0 : return;
11556 : }
11557 : break;
11558 : case '6': // 2 strings to match.
11559 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
11560 : break;
11561 0 : switch (Mnemonic[15]) {
11562 : default: break;
11563 : case '3': // 1 string to match.
11564 0 : if (Mnemonic[16] != '2')
11565 : break;
11566 0 : Mnemonic = "v_cmp_ngt_f64"; // "v_cmp_ngt_f64_e32"
11567 0 : return;
11568 : case '6': // 1 string to match.
11569 0 : if (Mnemonic[16] != '4')
11570 : break;
11571 0 : Mnemonic = "v_cmp_ngt_f64"; // "v_cmp_ngt_f64_e64"
11572 0 : return;
11573 : }
11574 : break;
11575 : }
11576 : break;
11577 : }
11578 : break;
11579 : case 'l': // 12 strings to match.
11580 0 : switch (Mnemonic[8]) {
11581 : default: break;
11582 : case 'e': // 4 strings to match.
11583 0 : if (memcmp(Mnemonic.data()+9, "_f", 2))
11584 : break;
11585 0 : switch (Mnemonic[11]) {
11586 : default: break;
11587 : case '3': // 2 strings to match.
11588 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
11589 : break;
11590 0 : switch (Mnemonic[15]) {
11591 : default: break;
11592 : case '3': // 1 string to match.
11593 0 : if (Mnemonic[16] != '2')
11594 : break;
11595 0 : Mnemonic = "v_cmp_nle_f32"; // "v_cmp_nle_f32_e32"
11596 0 : return;
11597 : case '6': // 1 string to match.
11598 0 : if (Mnemonic[16] != '4')
11599 : break;
11600 0 : Mnemonic = "v_cmp_nle_f32"; // "v_cmp_nle_f32_e64"
11601 0 : return;
11602 : }
11603 : break;
11604 : case '6': // 2 strings to match.
11605 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
11606 : break;
11607 0 : switch (Mnemonic[15]) {
11608 : default: break;
11609 : case '3': // 1 string to match.
11610 0 : if (Mnemonic[16] != '2')
11611 : break;
11612 0 : Mnemonic = "v_cmp_nle_f64"; // "v_cmp_nle_f64_e32"
11613 0 : return;
11614 : case '6': // 1 string to match.
11615 0 : if (Mnemonic[16] != '4')
11616 : break;
11617 0 : Mnemonic = "v_cmp_nle_f64"; // "v_cmp_nle_f64_e64"
11618 0 : return;
11619 : }
11620 : break;
11621 : }
11622 : break;
11623 : case 'g': // 4 strings to match.
11624 0 : if (memcmp(Mnemonic.data()+9, "_f", 2))
11625 : break;
11626 0 : switch (Mnemonic[11]) {
11627 : default: break;
11628 : case '3': // 2 strings to match.
11629 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
11630 : break;
11631 0 : switch (Mnemonic[15]) {
11632 : default: break;
11633 : case '3': // 1 string to match.
11634 0 : if (Mnemonic[16] != '2')
11635 : break;
11636 0 : Mnemonic = "v_cmp_nlg_f32"; // "v_cmp_nlg_f32_e32"
11637 0 : return;
11638 : case '6': // 1 string to match.
11639 0 : if (Mnemonic[16] != '4')
11640 : break;
11641 0 : Mnemonic = "v_cmp_nlg_f32"; // "v_cmp_nlg_f32_e64"
11642 0 : return;
11643 : }
11644 : break;
11645 : case '6': // 2 strings to match.
11646 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
11647 : break;
11648 0 : switch (Mnemonic[15]) {
11649 : default: break;
11650 : case '3': // 1 string to match.
11651 0 : if (Mnemonic[16] != '2')
11652 : break;
11653 0 : Mnemonic = "v_cmp_nlg_f64"; // "v_cmp_nlg_f64_e32"
11654 0 : return;
11655 : case '6': // 1 string to match.
11656 0 : if (Mnemonic[16] != '4')
11657 : break;
11658 0 : Mnemonic = "v_cmp_nlg_f64"; // "v_cmp_nlg_f64_e64"
11659 0 : return;
11660 : }
11661 : break;
11662 : }
11663 : break;
11664 : case 't': // 4 strings to match.
11665 0 : if (memcmp(Mnemonic.data()+9, "_f", 2))
11666 : break;
11667 0 : switch (Mnemonic[11]) {
11668 : default: break;
11669 : case '3': // 2 strings to match.
11670 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
11671 : break;
11672 0 : switch (Mnemonic[15]) {
11673 : default: break;
11674 : case '3': // 1 string to match.
11675 0 : if (Mnemonic[16] != '2')
11676 : break;
11677 0 : Mnemonic = "v_cmp_nlt_f32"; // "v_cmp_nlt_f32_e32"
11678 0 : return;
11679 : case '6': // 1 string to match.
11680 0 : if (Mnemonic[16] != '4')
11681 : break;
11682 0 : Mnemonic = "v_cmp_nlt_f32"; // "v_cmp_nlt_f32_e64"
11683 0 : return;
11684 : }
11685 : break;
11686 : case '6': // 2 strings to match.
11687 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
11688 : break;
11689 0 : switch (Mnemonic[15]) {
11690 : default: break;
11691 : case '3': // 1 string to match.
11692 0 : if (Mnemonic[16] != '2')
11693 : break;
11694 0 : Mnemonic = "v_cmp_nlt_f64"; // "v_cmp_nlt_f64_e32"
11695 0 : return;
11696 : case '6': // 1 string to match.
11697 0 : if (Mnemonic[16] != '4')
11698 : break;
11699 0 : Mnemonic = "v_cmp_nlt_f64"; // "v_cmp_nlt_f64_e64"
11700 0 : return;
11701 : }
11702 : break;
11703 : }
11704 : break;
11705 : }
11706 : break;
11707 : }
11708 : break;
11709 : case 't': // 4 strings to match.
11710 0 : if (memcmp(Mnemonic.data()+7, "ru_f", 4))
11711 : break;
11712 0 : switch (Mnemonic[11]) {
11713 : default: break;
11714 : case '3': // 2 strings to match.
11715 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
11716 : break;
11717 0 : switch (Mnemonic[15]) {
11718 : default: break;
11719 : case '3': // 1 string to match.
11720 0 : if (Mnemonic[16] != '2')
11721 : break;
11722 0 : Mnemonic = "v_cmp_tru_f32"; // "v_cmp_tru_f32_e32"
11723 0 : return;
11724 : case '6': // 1 string to match.
11725 0 : if (Mnemonic[16] != '4')
11726 : break;
11727 0 : Mnemonic = "v_cmp_tru_f32"; // "v_cmp_tru_f32_e64"
11728 0 : return;
11729 : }
11730 : break;
11731 : case '6': // 2 strings to match.
11732 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
11733 : break;
11734 0 : switch (Mnemonic[15]) {
11735 : default: break;
11736 : case '3': // 1 string to match.
11737 0 : if (Mnemonic[16] != '2')
11738 : break;
11739 0 : Mnemonic = "v_cmp_tru_f64"; // "v_cmp_tru_f64_e32"
11740 0 : return;
11741 : case '6': // 1 string to match.
11742 0 : if (Mnemonic[16] != '4')
11743 : break;
11744 0 : Mnemonic = "v_cmp_tru_f64"; // "v_cmp_tru_f64_e64"
11745 0 : return;
11746 : }
11747 : break;
11748 : }
11749 : break;
11750 : }
11751 : break;
11752 : case 's': // 36 strings to match.
11753 0 : switch (Mnemonic[6]) {
11754 : default: break;
11755 : case '_': // 24 strings to match.
11756 0 : switch (Mnemonic[7]) {
11757 : default: break;
11758 : case 'e': // 4 strings to match.
11759 0 : if (memcmp(Mnemonic.data()+8, "q_f", 3))
11760 : break;
11761 0 : switch (Mnemonic[11]) {
11762 : default: break;
11763 : case '3': // 2 strings to match.
11764 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
11765 : break;
11766 0 : switch (Mnemonic[15]) {
11767 : default: break;
11768 : case '3': // 1 string to match.
11769 0 : if (Mnemonic[16] != '2')
11770 : break;
11771 0 : Mnemonic = "v_cmps_eq_f32"; // "v_cmps_eq_f32_e32"
11772 0 : return;
11773 : case '6': // 1 string to match.
11774 0 : if (Mnemonic[16] != '4')
11775 : break;
11776 0 : Mnemonic = "v_cmps_eq_f32"; // "v_cmps_eq_f32_e64"
11777 0 : return;
11778 : }
11779 : break;
11780 : case '6': // 2 strings to match.
11781 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
11782 : break;
11783 0 : switch (Mnemonic[15]) {
11784 : default: break;
11785 : case '3': // 1 string to match.
11786 0 : if (Mnemonic[16] != '2')
11787 : break;
11788 0 : Mnemonic = "v_cmps_eq_f64"; // "v_cmps_eq_f64_e32"
11789 0 : return;
11790 : case '6': // 1 string to match.
11791 0 : if (Mnemonic[16] != '4')
11792 : break;
11793 0 : Mnemonic = "v_cmps_eq_f64"; // "v_cmps_eq_f64_e64"
11794 0 : return;
11795 : }
11796 : break;
11797 : }
11798 : break;
11799 : case 'g': // 8 strings to match.
11800 0 : switch (Mnemonic[8]) {
11801 : default: break;
11802 : case 'e': // 4 strings to match.
11803 0 : if (memcmp(Mnemonic.data()+9, "_f", 2))
11804 : break;
11805 0 : switch (Mnemonic[11]) {
11806 : default: break;
11807 : case '3': // 2 strings to match.
11808 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
11809 : break;
11810 0 : switch (Mnemonic[15]) {
11811 : default: break;
11812 : case '3': // 1 string to match.
11813 0 : if (Mnemonic[16] != '2')
11814 : break;
11815 0 : Mnemonic = "v_cmps_ge_f32"; // "v_cmps_ge_f32_e32"
11816 0 : return;
11817 : case '6': // 1 string to match.
11818 0 : if (Mnemonic[16] != '4')
11819 : break;
11820 0 : Mnemonic = "v_cmps_ge_f32"; // "v_cmps_ge_f32_e64"
11821 0 : return;
11822 : }
11823 : break;
11824 : case '6': // 2 strings to match.
11825 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
11826 : break;
11827 0 : switch (Mnemonic[15]) {
11828 : default: break;
11829 : case '3': // 1 string to match.
11830 0 : if (Mnemonic[16] != '2')
11831 : break;
11832 0 : Mnemonic = "v_cmps_ge_f64"; // "v_cmps_ge_f64_e32"
11833 0 : return;
11834 : case '6': // 1 string to match.
11835 0 : if (Mnemonic[16] != '4')
11836 : break;
11837 0 : Mnemonic = "v_cmps_ge_f64"; // "v_cmps_ge_f64_e64"
11838 0 : return;
11839 : }
11840 : break;
11841 : }
11842 : break;
11843 : case 't': // 4 strings to match.
11844 0 : if (memcmp(Mnemonic.data()+9, "_f", 2))
11845 : break;
11846 0 : switch (Mnemonic[11]) {
11847 : default: break;
11848 : case '3': // 2 strings to match.
11849 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
11850 : break;
11851 0 : switch (Mnemonic[15]) {
11852 : default: break;
11853 : case '3': // 1 string to match.
11854 0 : if (Mnemonic[16] != '2')
11855 : break;
11856 0 : Mnemonic = "v_cmps_gt_f32"; // "v_cmps_gt_f32_e32"
11857 0 : return;
11858 : case '6': // 1 string to match.
11859 0 : if (Mnemonic[16] != '4')
11860 : break;
11861 0 : Mnemonic = "v_cmps_gt_f32"; // "v_cmps_gt_f32_e64"
11862 0 : return;
11863 : }
11864 : break;
11865 : case '6': // 2 strings to match.
11866 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
11867 : break;
11868 0 : switch (Mnemonic[15]) {
11869 : default: break;
11870 : case '3': // 1 string to match.
11871 0 : if (Mnemonic[16] != '2')
11872 : break;
11873 0 : Mnemonic = "v_cmps_gt_f64"; // "v_cmps_gt_f64_e32"
11874 0 : return;
11875 : case '6': // 1 string to match.
11876 0 : if (Mnemonic[16] != '4')
11877 : break;
11878 0 : Mnemonic = "v_cmps_gt_f64"; // "v_cmps_gt_f64_e64"
11879 0 : return;
11880 : }
11881 : break;
11882 : }
11883 : break;
11884 : }
11885 : break;
11886 : case 'l': // 12 strings to match.
11887 0 : switch (Mnemonic[8]) {
11888 : default: break;
11889 : case 'e': // 4 strings to match.
11890 0 : if (memcmp(Mnemonic.data()+9, "_f", 2))
11891 : break;
11892 0 : switch (Mnemonic[11]) {
11893 : default: break;
11894 : case '3': // 2 strings to match.
11895 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
11896 : break;
11897 0 : switch (Mnemonic[15]) {
11898 : default: break;
11899 : case '3': // 1 string to match.
11900 0 : if (Mnemonic[16] != '2')
11901 : break;
11902 0 : Mnemonic = "v_cmps_le_f32"; // "v_cmps_le_f32_e32"
11903 0 : return;
11904 : case '6': // 1 string to match.
11905 0 : if (Mnemonic[16] != '4')
11906 : break;
11907 0 : Mnemonic = "v_cmps_le_f32"; // "v_cmps_le_f32_e64"
11908 0 : return;
11909 : }
11910 : break;
11911 : case '6': // 2 strings to match.
11912 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
11913 : break;
11914 0 : switch (Mnemonic[15]) {
11915 : default: break;
11916 : case '3': // 1 string to match.
11917 0 : if (Mnemonic[16] != '2')
11918 : break;
11919 0 : Mnemonic = "v_cmps_le_f64"; // "v_cmps_le_f64_e32"
11920 0 : return;
11921 : case '6': // 1 string to match.
11922 0 : if (Mnemonic[16] != '4')
11923 : break;
11924 0 : Mnemonic = "v_cmps_le_f64"; // "v_cmps_le_f64_e64"
11925 0 : return;
11926 : }
11927 : break;
11928 : }
11929 : break;
11930 : case 'g': // 4 strings to match.
11931 0 : if (memcmp(Mnemonic.data()+9, "_f", 2))
11932 : break;
11933 0 : switch (Mnemonic[11]) {
11934 : default: break;
11935 : case '3': // 2 strings to match.
11936 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
11937 : break;
11938 0 : switch (Mnemonic[15]) {
11939 : default: break;
11940 : case '3': // 1 string to match.
11941 0 : if (Mnemonic[16] != '2')
11942 : break;
11943 0 : Mnemonic = "v_cmps_lg_f32"; // "v_cmps_lg_f32_e32"
11944 0 : return;
11945 : case '6': // 1 string to match.
11946 0 : if (Mnemonic[16] != '4')
11947 : break;
11948 0 : Mnemonic = "v_cmps_lg_f32"; // "v_cmps_lg_f32_e64"
11949 0 : return;
11950 : }
11951 : break;
11952 : case '6': // 2 strings to match.
11953 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
11954 : break;
11955 0 : switch (Mnemonic[15]) {
11956 : default: break;
11957 : case '3': // 1 string to match.
11958 0 : if (Mnemonic[16] != '2')
11959 : break;
11960 0 : Mnemonic = "v_cmps_lg_f64"; // "v_cmps_lg_f64_e32"
11961 0 : return;
11962 : case '6': // 1 string to match.
11963 0 : if (Mnemonic[16] != '4')
11964 : break;
11965 0 : Mnemonic = "v_cmps_lg_f64"; // "v_cmps_lg_f64_e64"
11966 0 : return;
11967 : }
11968 : break;
11969 : }
11970 : break;
11971 : case 't': // 4 strings to match.
11972 0 : if (memcmp(Mnemonic.data()+9, "_f", 2))
11973 : break;
11974 0 : switch (Mnemonic[11]) {
11975 : default: break;
11976 : case '3': // 2 strings to match.
11977 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
11978 : break;
11979 0 : switch (Mnemonic[15]) {
11980 : default: break;
11981 : case '3': // 1 string to match.
11982 0 : if (Mnemonic[16] != '2')
11983 : break;
11984 0 : Mnemonic = "v_cmps_lt_f32"; // "v_cmps_lt_f32_e32"
11985 0 : return;
11986 : case '6': // 1 string to match.
11987 0 : if (Mnemonic[16] != '4')
11988 : break;
11989 0 : Mnemonic = "v_cmps_lt_f32"; // "v_cmps_lt_f32_e64"
11990 0 : return;
11991 : }
11992 : break;
11993 : case '6': // 2 strings to match.
11994 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
11995 : break;
11996 0 : switch (Mnemonic[15]) {
11997 : default: break;
11998 : case '3': // 1 string to match.
11999 0 : if (Mnemonic[16] != '2')
12000 : break;
12001 0 : Mnemonic = "v_cmps_lt_f64"; // "v_cmps_lt_f64_e32"
12002 0 : return;
12003 : case '6': // 1 string to match.
12004 0 : if (Mnemonic[16] != '4')
12005 : break;
12006 0 : Mnemonic = "v_cmps_lt_f64"; // "v_cmps_lt_f64_e64"
12007 0 : return;
12008 : }
12009 : break;
12010 : }
12011 : break;
12012 : }
12013 : break;
12014 : }
12015 : break;
12016 : case 'x': // 12 strings to match.
12017 0 : if (Mnemonic[7] != '_')
12018 : break;
12019 0 : switch (Mnemonic[8]) {
12020 : default: break;
12021 : case 'f': // 4 strings to match.
12022 0 : if (memcmp(Mnemonic.data()+9, "_f", 2))
12023 : break;
12024 0 : switch (Mnemonic[11]) {
12025 : default: break;
12026 : case '3': // 2 strings to match.
12027 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
12028 : break;
12029 0 : switch (Mnemonic[15]) {
12030 : default: break;
12031 : case '3': // 1 string to match.
12032 0 : if (Mnemonic[16] != '2')
12033 : break;
12034 0 : Mnemonic = "v_cmpsx_f_f32"; // "v_cmpsx_f_f32_e32"
12035 0 : return;
12036 : case '6': // 1 string to match.
12037 0 : if (Mnemonic[16] != '4')
12038 : break;
12039 0 : Mnemonic = "v_cmpsx_f_f32"; // "v_cmpsx_f_f32_e64"
12040 0 : return;
12041 : }
12042 : break;
12043 : case '6': // 2 strings to match.
12044 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
12045 : break;
12046 0 : switch (Mnemonic[15]) {
12047 : default: break;
12048 : case '3': // 1 string to match.
12049 0 : if (Mnemonic[16] != '2')
12050 : break;
12051 0 : Mnemonic = "v_cmpsx_f_f64"; // "v_cmpsx_f_f64_e32"
12052 0 : return;
12053 : case '6': // 1 string to match.
12054 0 : if (Mnemonic[16] != '4')
12055 : break;
12056 0 : Mnemonic = "v_cmpsx_f_f64"; // "v_cmpsx_f_f64_e64"
12057 0 : return;
12058 : }
12059 : break;
12060 : }
12061 : break;
12062 : case 'o': // 4 strings to match.
12063 0 : if (memcmp(Mnemonic.data()+9, "_f", 2))
12064 : break;
12065 0 : switch (Mnemonic[11]) {
12066 : default: break;
12067 : case '3': // 2 strings to match.
12068 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
12069 : break;
12070 0 : switch (Mnemonic[15]) {
12071 : default: break;
12072 : case '3': // 1 string to match.
12073 0 : if (Mnemonic[16] != '2')
12074 : break;
12075 0 : Mnemonic = "v_cmpsx_o_f32"; // "v_cmpsx_o_f32_e32"
12076 0 : return;
12077 : case '6': // 1 string to match.
12078 0 : if (Mnemonic[16] != '4')
12079 : break;
12080 0 : Mnemonic = "v_cmpsx_o_f32"; // "v_cmpsx_o_f32_e64"
12081 0 : return;
12082 : }
12083 : break;
12084 : case '6': // 2 strings to match.
12085 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
12086 : break;
12087 0 : switch (Mnemonic[15]) {
12088 : default: break;
12089 : case '3': // 1 string to match.
12090 0 : if (Mnemonic[16] != '2')
12091 : break;
12092 0 : Mnemonic = "v_cmpsx_o_f64"; // "v_cmpsx_o_f64_e32"
12093 0 : return;
12094 : case '6': // 1 string to match.
12095 0 : if (Mnemonic[16] != '4')
12096 : break;
12097 0 : Mnemonic = "v_cmpsx_o_f64"; // "v_cmpsx_o_f64_e64"
12098 0 : return;
12099 : }
12100 : break;
12101 : }
12102 : break;
12103 : case 'u': // 4 strings to match.
12104 0 : if (memcmp(Mnemonic.data()+9, "_f", 2))
12105 : break;
12106 0 : switch (Mnemonic[11]) {
12107 : default: break;
12108 : case '3': // 2 strings to match.
12109 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
12110 : break;
12111 0 : switch (Mnemonic[15]) {
12112 : default: break;
12113 : case '3': // 1 string to match.
12114 0 : if (Mnemonic[16] != '2')
12115 : break;
12116 0 : Mnemonic = "v_cmpsx_u_f32"; // "v_cmpsx_u_f32_e32"
12117 0 : return;
12118 : case '6': // 1 string to match.
12119 0 : if (Mnemonic[16] != '4')
12120 : break;
12121 0 : Mnemonic = "v_cmpsx_u_f32"; // "v_cmpsx_u_f32_e64"
12122 0 : return;
12123 : }
12124 : break;
12125 : case '6': // 2 strings to match.
12126 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
12127 : break;
12128 0 : switch (Mnemonic[15]) {
12129 : default: break;
12130 : case '3': // 1 string to match.
12131 0 : if (Mnemonic[16] != '2')
12132 : break;
12133 0 : Mnemonic = "v_cmpsx_u_f64"; // "v_cmpsx_u_f64_e32"
12134 0 : return;
12135 : case '6': // 1 string to match.
12136 0 : if (Mnemonic[16] != '4')
12137 : break;
12138 0 : Mnemonic = "v_cmpsx_u_f64"; // "v_cmpsx_u_f64_e64"
12139 0 : return;
12140 : }
12141 : break;
12142 : }
12143 : break;
12144 : }
12145 : break;
12146 : }
12147 : break;
12148 : case 'x': // 72 strings to match.
12149 0 : if (Mnemonic[6] != '_')
12150 : break;
12151 0 : switch (Mnemonic[7]) {
12152 : default: break;
12153 : case 'e': // 12 strings to match.
12154 0 : if (memcmp(Mnemonic.data()+8, "q_", 2))
12155 : break;
12156 0 : switch (Mnemonic[10]) {
12157 : default: break;
12158 : case 'f': // 4 strings to match.
12159 0 : switch (Mnemonic[11]) {
12160 : default: break;
12161 : case '3': // 2 strings to match.
12162 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
12163 : break;
12164 0 : switch (Mnemonic[15]) {
12165 : default: break;
12166 : case '3': // 1 string to match.
12167 0 : if (Mnemonic[16] != '2')
12168 : break;
12169 0 : Mnemonic = "v_cmpx_eq_f32"; // "v_cmpx_eq_f32_e32"
12170 0 : return;
12171 : case '6': // 1 string to match.
12172 0 : if (Mnemonic[16] != '4')
12173 : break;
12174 0 : Mnemonic = "v_cmpx_eq_f32"; // "v_cmpx_eq_f32_e64"
12175 0 : return;
12176 : }
12177 : break;
12178 : case '6': // 2 strings to match.
12179 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
12180 : break;
12181 0 : switch (Mnemonic[15]) {
12182 : default: break;
12183 : case '3': // 1 string to match.
12184 0 : if (Mnemonic[16] != '2')
12185 : break;
12186 0 : Mnemonic = "v_cmpx_eq_f64"; // "v_cmpx_eq_f64_e32"
12187 0 : return;
12188 : case '6': // 1 string to match.
12189 0 : if (Mnemonic[16] != '4')
12190 : break;
12191 0 : Mnemonic = "v_cmpx_eq_f64"; // "v_cmpx_eq_f64_e64"
12192 0 : return;
12193 : }
12194 : break;
12195 : }
12196 : break;
12197 : case 'i': // 4 strings to match.
12198 0 : switch (Mnemonic[11]) {
12199 : default: break;
12200 : case '3': // 2 strings to match.
12201 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
12202 : break;
12203 0 : switch (Mnemonic[15]) {
12204 : default: break;
12205 : case '3': // 1 string to match.
12206 0 : if (Mnemonic[16] != '2')
12207 : break;
12208 0 : Mnemonic = "v_cmpx_eq_i32"; // "v_cmpx_eq_i32_e32"
12209 0 : return;
12210 : case '6': // 1 string to match.
12211 0 : if (Mnemonic[16] != '4')
12212 : break;
12213 0 : Mnemonic = "v_cmpx_eq_i32"; // "v_cmpx_eq_i32_e64"
12214 0 : return;
12215 : }
12216 : break;
12217 : case '6': // 2 strings to match.
12218 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
12219 : break;
12220 0 : switch (Mnemonic[15]) {
12221 : default: break;
12222 : case '3': // 1 string to match.
12223 0 : if (Mnemonic[16] != '2')
12224 : break;
12225 0 : Mnemonic = "v_cmpx_eq_i64"; // "v_cmpx_eq_i64_e32"
12226 0 : return;
12227 : case '6': // 1 string to match.
12228 0 : if (Mnemonic[16] != '4')
12229 : break;
12230 0 : Mnemonic = "v_cmpx_eq_i64"; // "v_cmpx_eq_i64_e64"
12231 0 : return;
12232 : }
12233 : break;
12234 : }
12235 : break;
12236 : case 'u': // 4 strings to match.
12237 0 : switch (Mnemonic[11]) {
12238 : default: break;
12239 : case '3': // 2 strings to match.
12240 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
12241 : break;
12242 0 : switch (Mnemonic[15]) {
12243 : default: break;
12244 : case '3': // 1 string to match.
12245 0 : if (Mnemonic[16] != '2')
12246 : break;
12247 0 : Mnemonic = "v_cmpx_eq_u32"; // "v_cmpx_eq_u32_e32"
12248 0 : return;
12249 : case '6': // 1 string to match.
12250 0 : if (Mnemonic[16] != '4')
12251 : break;
12252 0 : Mnemonic = "v_cmpx_eq_u32"; // "v_cmpx_eq_u32_e64"
12253 0 : return;
12254 : }
12255 : break;
12256 : case '6': // 2 strings to match.
12257 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
12258 : break;
12259 0 : switch (Mnemonic[15]) {
12260 : default: break;
12261 : case '3': // 1 string to match.
12262 0 : if (Mnemonic[16] != '2')
12263 : break;
12264 0 : Mnemonic = "v_cmpx_eq_u64"; // "v_cmpx_eq_u64_e32"
12265 0 : return;
12266 : case '6': // 1 string to match.
12267 0 : if (Mnemonic[16] != '4')
12268 : break;
12269 0 : Mnemonic = "v_cmpx_eq_u64"; // "v_cmpx_eq_u64_e64"
12270 0 : return;
12271 : }
12272 : break;
12273 : }
12274 : break;
12275 : }
12276 : break;
12277 : case 'g': // 24 strings to match.
12278 0 : switch (Mnemonic[8]) {
12279 : default: break;
12280 : case 'e': // 12 strings to match.
12281 0 : if (Mnemonic[9] != '_')
12282 : break;
12283 0 : switch (Mnemonic[10]) {
12284 : default: break;
12285 : case 'f': // 4 strings to match.
12286 0 : switch (Mnemonic[11]) {
12287 : default: break;
12288 : case '3': // 2 strings to match.
12289 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
12290 : break;
12291 0 : switch (Mnemonic[15]) {
12292 : default: break;
12293 : case '3': // 1 string to match.
12294 0 : if (Mnemonic[16] != '2')
12295 : break;
12296 0 : Mnemonic = "v_cmpx_ge_f32"; // "v_cmpx_ge_f32_e32"
12297 0 : return;
12298 : case '6': // 1 string to match.
12299 0 : if (Mnemonic[16] != '4')
12300 : break;
12301 0 : Mnemonic = "v_cmpx_ge_f32"; // "v_cmpx_ge_f32_e64"
12302 0 : return;
12303 : }
12304 : break;
12305 : case '6': // 2 strings to match.
12306 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
12307 : break;
12308 0 : switch (Mnemonic[15]) {
12309 : default: break;
12310 : case '3': // 1 string to match.
12311 0 : if (Mnemonic[16] != '2')
12312 : break;
12313 0 : Mnemonic = "v_cmpx_ge_f64"; // "v_cmpx_ge_f64_e32"
12314 0 : return;
12315 : case '6': // 1 string to match.
12316 0 : if (Mnemonic[16] != '4')
12317 : break;
12318 0 : Mnemonic = "v_cmpx_ge_f64"; // "v_cmpx_ge_f64_e64"
12319 0 : return;
12320 : }
12321 : break;
12322 : }
12323 : break;
12324 : case 'i': // 4 strings to match.
12325 0 : switch (Mnemonic[11]) {
12326 : default: break;
12327 : case '3': // 2 strings to match.
12328 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
12329 : break;
12330 0 : switch (Mnemonic[15]) {
12331 : default: break;
12332 : case '3': // 1 string to match.
12333 0 : if (Mnemonic[16] != '2')
12334 : break;
12335 0 : Mnemonic = "v_cmpx_ge_i32"; // "v_cmpx_ge_i32_e32"
12336 0 : return;
12337 : case '6': // 1 string to match.
12338 0 : if (Mnemonic[16] != '4')
12339 : break;
12340 0 : Mnemonic = "v_cmpx_ge_i32"; // "v_cmpx_ge_i32_e64"
12341 0 : return;
12342 : }
12343 : break;
12344 : case '6': // 2 strings to match.
12345 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
12346 : break;
12347 0 : switch (Mnemonic[15]) {
12348 : default: break;
12349 : case '3': // 1 string to match.
12350 0 : if (Mnemonic[16] != '2')
12351 : break;
12352 0 : Mnemonic = "v_cmpx_ge_i64"; // "v_cmpx_ge_i64_e32"
12353 0 : return;
12354 : case '6': // 1 string to match.
12355 0 : if (Mnemonic[16] != '4')
12356 : break;
12357 0 : Mnemonic = "v_cmpx_ge_i64"; // "v_cmpx_ge_i64_e64"
12358 0 : return;
12359 : }
12360 : break;
12361 : }
12362 : break;
12363 : case 'u': // 4 strings to match.
12364 0 : switch (Mnemonic[11]) {
12365 : default: break;
12366 : case '3': // 2 strings to match.
12367 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
12368 : break;
12369 0 : switch (Mnemonic[15]) {
12370 : default: break;
12371 : case '3': // 1 string to match.
12372 0 : if (Mnemonic[16] != '2')
12373 : break;
12374 0 : Mnemonic = "v_cmpx_ge_u32"; // "v_cmpx_ge_u32_e32"
12375 0 : return;
12376 : case '6': // 1 string to match.
12377 0 : if (Mnemonic[16] != '4')
12378 : break;
12379 0 : Mnemonic = "v_cmpx_ge_u32"; // "v_cmpx_ge_u32_e64"
12380 0 : return;
12381 : }
12382 : break;
12383 : case '6': // 2 strings to match.
12384 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
12385 : break;
12386 0 : switch (Mnemonic[15]) {
12387 : default: break;
12388 : case '3': // 1 string to match.
12389 0 : if (Mnemonic[16] != '2')
12390 : break;
12391 0 : Mnemonic = "v_cmpx_ge_u64"; // "v_cmpx_ge_u64_e32"
12392 0 : return;
12393 : case '6': // 1 string to match.
12394 0 : if (Mnemonic[16] != '4')
12395 : break;
12396 0 : Mnemonic = "v_cmpx_ge_u64"; // "v_cmpx_ge_u64_e64"
12397 0 : return;
12398 : }
12399 : break;
12400 : }
12401 : break;
12402 : }
12403 : break;
12404 : case 't': // 12 strings to match.
12405 0 : if (Mnemonic[9] != '_')
12406 : break;
12407 0 : switch (Mnemonic[10]) {
12408 : default: break;
12409 : case 'f': // 4 strings to match.
12410 0 : switch (Mnemonic[11]) {
12411 : default: break;
12412 : case '3': // 2 strings to match.
12413 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
12414 : break;
12415 0 : switch (Mnemonic[15]) {
12416 : default: break;
12417 : case '3': // 1 string to match.
12418 0 : if (Mnemonic[16] != '2')
12419 : break;
12420 0 : Mnemonic = "v_cmpx_gt_f32"; // "v_cmpx_gt_f32_e32"
12421 0 : return;
12422 : case '6': // 1 string to match.
12423 0 : if (Mnemonic[16] != '4')
12424 : break;
12425 0 : Mnemonic = "v_cmpx_gt_f32"; // "v_cmpx_gt_f32_e64"
12426 0 : return;
12427 : }
12428 : break;
12429 : case '6': // 2 strings to match.
12430 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
12431 : break;
12432 0 : switch (Mnemonic[15]) {
12433 : default: break;
12434 : case '3': // 1 string to match.
12435 0 : if (Mnemonic[16] != '2')
12436 : break;
12437 0 : Mnemonic = "v_cmpx_gt_f64"; // "v_cmpx_gt_f64_e32"
12438 0 : return;
12439 : case '6': // 1 string to match.
12440 0 : if (Mnemonic[16] != '4')
12441 : break;
12442 0 : Mnemonic = "v_cmpx_gt_f64"; // "v_cmpx_gt_f64_e64"
12443 0 : return;
12444 : }
12445 : break;
12446 : }
12447 : break;
12448 : case 'i': // 4 strings to match.
12449 0 : switch (Mnemonic[11]) {
12450 : default: break;
12451 : case '3': // 2 strings to match.
12452 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
12453 : break;
12454 0 : switch (Mnemonic[15]) {
12455 : default: break;
12456 : case '3': // 1 string to match.
12457 0 : if (Mnemonic[16] != '2')
12458 : break;
12459 0 : Mnemonic = "v_cmpx_gt_i32"; // "v_cmpx_gt_i32_e32"
12460 0 : return;
12461 : case '6': // 1 string to match.
12462 0 : if (Mnemonic[16] != '4')
12463 : break;
12464 0 : Mnemonic = "v_cmpx_gt_i32"; // "v_cmpx_gt_i32_e64"
12465 0 : return;
12466 : }
12467 : break;
12468 : case '6': // 2 strings to match.
12469 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
12470 : break;
12471 0 : switch (Mnemonic[15]) {
12472 : default: break;
12473 : case '3': // 1 string to match.
12474 0 : if (Mnemonic[16] != '2')
12475 : break;
12476 0 : Mnemonic = "v_cmpx_gt_i64"; // "v_cmpx_gt_i64_e32"
12477 0 : return;
12478 : case '6': // 1 string to match.
12479 0 : if (Mnemonic[16] != '4')
12480 : break;
12481 0 : Mnemonic = "v_cmpx_gt_i64"; // "v_cmpx_gt_i64_e64"
12482 0 : return;
12483 : }
12484 : break;
12485 : }
12486 : break;
12487 : case 'u': // 4 strings to match.
12488 0 : switch (Mnemonic[11]) {
12489 : default: break;
12490 : case '3': // 2 strings to match.
12491 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
12492 : break;
12493 0 : switch (Mnemonic[15]) {
12494 : default: break;
12495 : case '3': // 1 string to match.
12496 0 : if (Mnemonic[16] != '2')
12497 : break;
12498 0 : Mnemonic = "v_cmpx_gt_u32"; // "v_cmpx_gt_u32_e32"
12499 0 : return;
12500 : case '6': // 1 string to match.
12501 0 : if (Mnemonic[16] != '4')
12502 : break;
12503 0 : Mnemonic = "v_cmpx_gt_u32"; // "v_cmpx_gt_u32_e64"
12504 0 : return;
12505 : }
12506 : break;
12507 : case '6': // 2 strings to match.
12508 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
12509 : break;
12510 0 : switch (Mnemonic[15]) {
12511 : default: break;
12512 : case '3': // 1 string to match.
12513 0 : if (Mnemonic[16] != '2')
12514 : break;
12515 0 : Mnemonic = "v_cmpx_gt_u64"; // "v_cmpx_gt_u64_e32"
12516 0 : return;
12517 : case '6': // 1 string to match.
12518 0 : if (Mnemonic[16] != '4')
12519 : break;
12520 0 : Mnemonic = "v_cmpx_gt_u64"; // "v_cmpx_gt_u64_e64"
12521 0 : return;
12522 : }
12523 : break;
12524 : }
12525 : break;
12526 : }
12527 : break;
12528 : }
12529 : break;
12530 : case 'l': // 28 strings to match.
12531 0 : switch (Mnemonic[8]) {
12532 : default: break;
12533 : case 'e': // 12 strings to match.
12534 0 : if (Mnemonic[9] != '_')
12535 : break;
12536 0 : switch (Mnemonic[10]) {
12537 : default: break;
12538 : case 'f': // 4 strings to match.
12539 0 : switch (Mnemonic[11]) {
12540 : default: break;
12541 : case '3': // 2 strings to match.
12542 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
12543 : break;
12544 0 : switch (Mnemonic[15]) {
12545 : default: break;
12546 : case '3': // 1 string to match.
12547 0 : if (Mnemonic[16] != '2')
12548 : break;
12549 0 : Mnemonic = "v_cmpx_le_f32"; // "v_cmpx_le_f32_e32"
12550 0 : return;
12551 : case '6': // 1 string to match.
12552 0 : if (Mnemonic[16] != '4')
12553 : break;
12554 0 : Mnemonic = "v_cmpx_le_f32"; // "v_cmpx_le_f32_e64"
12555 0 : return;
12556 : }
12557 : break;
12558 : case '6': // 2 strings to match.
12559 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
12560 : break;
12561 0 : switch (Mnemonic[15]) {
12562 : default: break;
12563 : case '3': // 1 string to match.
12564 0 : if (Mnemonic[16] != '2')
12565 : break;
12566 0 : Mnemonic = "v_cmpx_le_f64"; // "v_cmpx_le_f64_e32"
12567 0 : return;
12568 : case '6': // 1 string to match.
12569 0 : if (Mnemonic[16] != '4')
12570 : break;
12571 0 : Mnemonic = "v_cmpx_le_f64"; // "v_cmpx_le_f64_e64"
12572 0 : return;
12573 : }
12574 : break;
12575 : }
12576 : break;
12577 : case 'i': // 4 strings to match.
12578 0 : switch (Mnemonic[11]) {
12579 : default: break;
12580 : case '3': // 2 strings to match.
12581 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
12582 : break;
12583 0 : switch (Mnemonic[15]) {
12584 : default: break;
12585 : case '3': // 1 string to match.
12586 0 : if (Mnemonic[16] != '2')
12587 : break;
12588 0 : Mnemonic = "v_cmpx_le_i32"; // "v_cmpx_le_i32_e32"
12589 0 : return;
12590 : case '6': // 1 string to match.
12591 0 : if (Mnemonic[16] != '4')
12592 : break;
12593 0 : Mnemonic = "v_cmpx_le_i32"; // "v_cmpx_le_i32_e64"
12594 0 : return;
12595 : }
12596 : break;
12597 : case '6': // 2 strings to match.
12598 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
12599 : break;
12600 0 : switch (Mnemonic[15]) {
12601 : default: break;
12602 : case '3': // 1 string to match.
12603 0 : if (Mnemonic[16] != '2')
12604 : break;
12605 0 : Mnemonic = "v_cmpx_le_i64"; // "v_cmpx_le_i64_e32"
12606 0 : return;
12607 : case '6': // 1 string to match.
12608 0 : if (Mnemonic[16] != '4')
12609 : break;
12610 0 : Mnemonic = "v_cmpx_le_i64"; // "v_cmpx_le_i64_e64"
12611 0 : return;
12612 : }
12613 : break;
12614 : }
12615 : break;
12616 : case 'u': // 4 strings to match.
12617 0 : switch (Mnemonic[11]) {
12618 : default: break;
12619 : case '3': // 2 strings to match.
12620 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
12621 : break;
12622 0 : switch (Mnemonic[15]) {
12623 : default: break;
12624 : case '3': // 1 string to match.
12625 0 : if (Mnemonic[16] != '2')
12626 : break;
12627 0 : Mnemonic = "v_cmpx_le_u32"; // "v_cmpx_le_u32_e32"
12628 0 : return;
12629 : case '6': // 1 string to match.
12630 0 : if (Mnemonic[16] != '4')
12631 : break;
12632 0 : Mnemonic = "v_cmpx_le_u32"; // "v_cmpx_le_u32_e64"
12633 0 : return;
12634 : }
12635 : break;
12636 : case '6': // 2 strings to match.
12637 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
12638 : break;
12639 0 : switch (Mnemonic[15]) {
12640 : default: break;
12641 : case '3': // 1 string to match.
12642 0 : if (Mnemonic[16] != '2')
12643 : break;
12644 0 : Mnemonic = "v_cmpx_le_u64"; // "v_cmpx_le_u64_e32"
12645 0 : return;
12646 : case '6': // 1 string to match.
12647 0 : if (Mnemonic[16] != '4')
12648 : break;
12649 0 : Mnemonic = "v_cmpx_le_u64"; // "v_cmpx_le_u64_e64"
12650 0 : return;
12651 : }
12652 : break;
12653 : }
12654 : break;
12655 : }
12656 : break;
12657 : case 'g': // 4 strings to match.
12658 0 : if (memcmp(Mnemonic.data()+9, "_f", 2))
12659 : break;
12660 0 : switch (Mnemonic[11]) {
12661 : default: break;
12662 : case '3': // 2 strings to match.
12663 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
12664 : break;
12665 0 : switch (Mnemonic[15]) {
12666 : default: break;
12667 : case '3': // 1 string to match.
12668 0 : if (Mnemonic[16] != '2')
12669 : break;
12670 0 : Mnemonic = "v_cmpx_lg_f32"; // "v_cmpx_lg_f32_e32"
12671 0 : return;
12672 : case '6': // 1 string to match.
12673 0 : if (Mnemonic[16] != '4')
12674 : break;
12675 0 : Mnemonic = "v_cmpx_lg_f32"; // "v_cmpx_lg_f32_e64"
12676 0 : return;
12677 : }
12678 : break;
12679 : case '6': // 2 strings to match.
12680 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
12681 : break;
12682 0 : switch (Mnemonic[15]) {
12683 : default: break;
12684 : case '3': // 1 string to match.
12685 0 : if (Mnemonic[16] != '2')
12686 : break;
12687 0 : Mnemonic = "v_cmpx_lg_f64"; // "v_cmpx_lg_f64_e32"
12688 0 : return;
12689 : case '6': // 1 string to match.
12690 0 : if (Mnemonic[16] != '4')
12691 : break;
12692 0 : Mnemonic = "v_cmpx_lg_f64"; // "v_cmpx_lg_f64_e64"
12693 0 : return;
12694 : }
12695 : break;
12696 : }
12697 : break;
12698 : case 't': // 12 strings to match.
12699 0 : if (Mnemonic[9] != '_')
12700 : break;
12701 0 : switch (Mnemonic[10]) {
12702 : default: break;
12703 : case 'f': // 4 strings to match.
12704 0 : switch (Mnemonic[11]) {
12705 : default: break;
12706 : case '3': // 2 strings to match.
12707 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
12708 : break;
12709 0 : switch (Mnemonic[15]) {
12710 : default: break;
12711 : case '3': // 1 string to match.
12712 0 : if (Mnemonic[16] != '2')
12713 : break;
12714 0 : Mnemonic = "v_cmpx_lt_f32"; // "v_cmpx_lt_f32_e32"
12715 0 : return;
12716 : case '6': // 1 string to match.
12717 0 : if (Mnemonic[16] != '4')
12718 : break;
12719 0 : Mnemonic = "v_cmpx_lt_f32"; // "v_cmpx_lt_f32_e64"
12720 0 : return;
12721 : }
12722 : break;
12723 : case '6': // 2 strings to match.
12724 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
12725 : break;
12726 0 : switch (Mnemonic[15]) {
12727 : default: break;
12728 : case '3': // 1 string to match.
12729 0 : if (Mnemonic[16] != '2')
12730 : break;
12731 0 : Mnemonic = "v_cmpx_lt_f64"; // "v_cmpx_lt_f64_e32"
12732 0 : return;
12733 : case '6': // 1 string to match.
12734 0 : if (Mnemonic[16] != '4')
12735 : break;
12736 0 : Mnemonic = "v_cmpx_lt_f64"; // "v_cmpx_lt_f64_e64"
12737 0 : return;
12738 : }
12739 : break;
12740 : }
12741 : break;
12742 : case 'i': // 4 strings to match.
12743 0 : switch (Mnemonic[11]) {
12744 : default: break;
12745 : case '3': // 2 strings to match.
12746 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
12747 : break;
12748 0 : switch (Mnemonic[15]) {
12749 : default: break;
12750 : case '3': // 1 string to match.
12751 0 : if (Mnemonic[16] != '2')
12752 : break;
12753 0 : Mnemonic = "v_cmpx_lt_i32"; // "v_cmpx_lt_i32_e32"
12754 0 : return;
12755 : case '6': // 1 string to match.
12756 0 : if (Mnemonic[16] != '4')
12757 : break;
12758 0 : Mnemonic = "v_cmpx_lt_i32"; // "v_cmpx_lt_i32_e64"
12759 0 : return;
12760 : }
12761 : break;
12762 : case '6': // 2 strings to match.
12763 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
12764 : break;
12765 0 : switch (Mnemonic[15]) {
12766 : default: break;
12767 : case '3': // 1 string to match.
12768 0 : if (Mnemonic[16] != '2')
12769 : break;
12770 0 : Mnemonic = "v_cmpx_lt_i64"; // "v_cmpx_lt_i64_e32"
12771 0 : return;
12772 : case '6': // 1 string to match.
12773 0 : if (Mnemonic[16] != '4')
12774 : break;
12775 0 : Mnemonic = "v_cmpx_lt_i64"; // "v_cmpx_lt_i64_e64"
12776 0 : return;
12777 : }
12778 : break;
12779 : }
12780 : break;
12781 : case 'u': // 4 strings to match.
12782 0 : switch (Mnemonic[11]) {
12783 : default: break;
12784 : case '3': // 2 strings to match.
12785 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
12786 : break;
12787 0 : switch (Mnemonic[15]) {
12788 : default: break;
12789 : case '3': // 1 string to match.
12790 0 : if (Mnemonic[16] != '2')
12791 : break;
12792 0 : Mnemonic = "v_cmpx_lt_u32"; // "v_cmpx_lt_u32_e32"
12793 0 : return;
12794 : case '6': // 1 string to match.
12795 0 : if (Mnemonic[16] != '4')
12796 : break;
12797 0 : Mnemonic = "v_cmpx_lt_u32"; // "v_cmpx_lt_u32_e64"
12798 0 : return;
12799 : }
12800 : break;
12801 : case '6': // 2 strings to match.
12802 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
12803 : break;
12804 0 : switch (Mnemonic[15]) {
12805 : default: break;
12806 : case '3': // 1 string to match.
12807 0 : if (Mnemonic[16] != '2')
12808 : break;
12809 0 : Mnemonic = "v_cmpx_lt_u64"; // "v_cmpx_lt_u64_e32"
12810 0 : return;
12811 : case '6': // 1 string to match.
12812 0 : if (Mnemonic[16] != '4')
12813 : break;
12814 0 : Mnemonic = "v_cmpx_lt_u64"; // "v_cmpx_lt_u64_e64"
12815 0 : return;
12816 : }
12817 : break;
12818 : }
12819 : break;
12820 : }
12821 : break;
12822 : }
12823 : break;
12824 : case 'n': // 8 strings to match.
12825 0 : if (memcmp(Mnemonic.data()+8, "e_", 2))
12826 : break;
12827 0 : switch (Mnemonic[10]) {
12828 : default: break;
12829 : case 'i': // 4 strings to match.
12830 0 : switch (Mnemonic[11]) {
12831 : default: break;
12832 : case '3': // 2 strings to match.
12833 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
12834 : break;
12835 0 : switch (Mnemonic[15]) {
12836 : default: break;
12837 : case '3': // 1 string to match.
12838 0 : if (Mnemonic[16] != '2')
12839 : break;
12840 0 : Mnemonic = "v_cmpx_ne_i32"; // "v_cmpx_ne_i32_e32"
12841 0 : return;
12842 : case '6': // 1 string to match.
12843 0 : if (Mnemonic[16] != '4')
12844 : break;
12845 0 : Mnemonic = "v_cmpx_ne_i32"; // "v_cmpx_ne_i32_e64"
12846 0 : return;
12847 : }
12848 : break;
12849 : case '6': // 2 strings to match.
12850 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
12851 : break;
12852 0 : switch (Mnemonic[15]) {
12853 : default: break;
12854 : case '3': // 1 string to match.
12855 0 : if (Mnemonic[16] != '2')
12856 : break;
12857 0 : Mnemonic = "v_cmpx_ne_i64"; // "v_cmpx_ne_i64_e32"
12858 0 : return;
12859 : case '6': // 1 string to match.
12860 0 : if (Mnemonic[16] != '4')
12861 : break;
12862 0 : Mnemonic = "v_cmpx_ne_i64"; // "v_cmpx_ne_i64_e64"
12863 0 : return;
12864 : }
12865 : break;
12866 : }
12867 : break;
12868 : case 'u': // 4 strings to match.
12869 0 : switch (Mnemonic[11]) {
12870 : default: break;
12871 : case '3': // 2 strings to match.
12872 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
12873 : break;
12874 0 : switch (Mnemonic[15]) {
12875 : default: break;
12876 : case '3': // 1 string to match.
12877 0 : if (Mnemonic[16] != '2')
12878 : break;
12879 0 : Mnemonic = "v_cmpx_ne_u32"; // "v_cmpx_ne_u32_e32"
12880 0 : return;
12881 : case '6': // 1 string to match.
12882 0 : if (Mnemonic[16] != '4')
12883 : break;
12884 0 : Mnemonic = "v_cmpx_ne_u32"; // "v_cmpx_ne_u32_e64"
12885 0 : return;
12886 : }
12887 : break;
12888 : case '6': // 2 strings to match.
12889 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
12890 : break;
12891 0 : switch (Mnemonic[15]) {
12892 : default: break;
12893 : case '3': // 1 string to match.
12894 0 : if (Mnemonic[16] != '2')
12895 : break;
12896 0 : Mnemonic = "v_cmpx_ne_u64"; // "v_cmpx_ne_u64_e32"
12897 0 : return;
12898 : case '6': // 1 string to match.
12899 0 : if (Mnemonic[16] != '4')
12900 : break;
12901 0 : Mnemonic = "v_cmpx_ne_u64"; // "v_cmpx_ne_u64_e64"
12902 0 : return;
12903 : }
12904 : break;
12905 : }
12906 : break;
12907 : }
12908 : break;
12909 : }
12910 : break;
12911 : }
12912 : break;
12913 : case 'n': // 2 strings to match.
12914 0 : if (memcmp(Mnemonic.data()+4, "dmask_b32_e", 11))
12915 : break;
12916 0 : switch (Mnemonic[15]) {
12917 : default: break;
12918 : case '3': // 1 string to match.
12919 0 : if (Mnemonic[16] != '2')
12920 : break;
12921 0 : Mnemonic = "v_cndmask_b32"; // "v_cndmask_b32_e32"
12922 0 : return;
12923 : case '6': // 1 string to match.
12924 0 : if (Mnemonic[16] != '4')
12925 : break;
12926 0 : Mnemonic = "v_cndmask_b32"; // "v_cndmask_b32_e64"
12927 0 : return;
12928 : }
12929 : break;
12930 : case 'v': // 32 strings to match.
12931 16 : if (memcmp(Mnemonic.data()+4, "t_", 2))
12932 : break;
12933 32 : switch (Mnemonic[6]) {
12934 : default: break;
12935 : case 'f': // 20 strings to match.
12936 16 : switch (Mnemonic[7]) {
12937 : default: break;
12938 : case '1': // 6 strings to match.
12939 0 : if (memcmp(Mnemonic.data()+8, "6_", 2))
12940 : break;
12941 0 : switch (Mnemonic[10]) {
12942 : default: break;
12943 : case 'f': // 2 strings to match.
12944 0 : if (memcmp(Mnemonic.data()+11, "32_e", 4))
12945 : break;
12946 0 : switch (Mnemonic[15]) {
12947 : default: break;
12948 : case '3': // 1 string to match.
12949 0 : if (Mnemonic[16] != '2')
12950 : break;
12951 0 : Mnemonic = "v_cvt_f16_f32"; // "v_cvt_f16_f32_e32"
12952 0 : return;
12953 : case '6': // 1 string to match.
12954 0 : if (Mnemonic[16] != '4')
12955 : break;
12956 0 : Mnemonic = "v_cvt_f16_f32"; // "v_cvt_f16_f32_e64"
12957 0 : return;
12958 : }
12959 : break;
12960 : case 'i': // 2 strings to match.
12961 0 : if (memcmp(Mnemonic.data()+11, "16_e", 4))
12962 : break;
12963 0 : switch (Mnemonic[15]) {
12964 : default: break;
12965 : case '3': // 1 string to match.
12966 0 : if (Mnemonic[16] != '2')
12967 : break;
12968 0 : Mnemonic = "v_cvt_f16_i16"; // "v_cvt_f16_i16_e32"
12969 0 : return;
12970 : case '6': // 1 string to match.
12971 0 : if (Mnemonic[16] != '4')
12972 : break;
12973 0 : Mnemonic = "v_cvt_f16_i16"; // "v_cvt_f16_i16_e64"
12974 0 : return;
12975 : }
12976 : break;
12977 : case 'u': // 2 strings to match.
12978 0 : if (memcmp(Mnemonic.data()+11, "16_e", 4))
12979 : break;
12980 0 : switch (Mnemonic[15]) {
12981 : default: break;
12982 : case '3': // 1 string to match.
12983 0 : if (Mnemonic[16] != '2')
12984 : break;
12985 0 : Mnemonic = "v_cvt_f16_u16"; // "v_cvt_f16_u16_e32"
12986 0 : return;
12987 : case '6': // 1 string to match.
12988 0 : if (Mnemonic[16] != '4')
12989 : break;
12990 0 : Mnemonic = "v_cvt_f16_u16"; // "v_cvt_f16_u16_e64"
12991 0 : return;
12992 : }
12993 : break;
12994 : }
12995 : break;
12996 : case '3': // 8 strings to match.
12997 0 : if (memcmp(Mnemonic.data()+8, "2_", 2))
12998 : break;
12999 0 : switch (Mnemonic[10]) {
13000 : default: break;
13001 : case 'f': // 4 strings to match.
13002 0 : switch (Mnemonic[11]) {
13003 : default: break;
13004 : case '1': // 2 strings to match.
13005 0 : if (memcmp(Mnemonic.data()+12, "6_e", 3))
13006 : break;
13007 0 : switch (Mnemonic[15]) {
13008 : default: break;
13009 : case '3': // 1 string to match.
13010 0 : if (Mnemonic[16] != '2')
13011 : break;
13012 0 : Mnemonic = "v_cvt_f32_f16"; // "v_cvt_f32_f16_e32"
13013 0 : return;
13014 : case '6': // 1 string to match.
13015 0 : if (Mnemonic[16] != '4')
13016 : break;
13017 0 : Mnemonic = "v_cvt_f32_f16"; // "v_cvt_f32_f16_e64"
13018 0 : return;
13019 : }
13020 : break;
13021 : case '6': // 2 strings to match.
13022 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
13023 : break;
13024 0 : switch (Mnemonic[15]) {
13025 : default: break;
13026 : case '3': // 1 string to match.
13027 0 : if (Mnemonic[16] != '2')
13028 : break;
13029 0 : Mnemonic = "v_cvt_f32_f64"; // "v_cvt_f32_f64_e32"
13030 0 : return;
13031 : case '6': // 1 string to match.
13032 0 : if (Mnemonic[16] != '4')
13033 : break;
13034 0 : Mnemonic = "v_cvt_f32_f64"; // "v_cvt_f32_f64_e64"
13035 0 : return;
13036 : }
13037 : break;
13038 : }
13039 : break;
13040 : case 'i': // 2 strings to match.
13041 0 : if (memcmp(Mnemonic.data()+11, "32_e", 4))
13042 : break;
13043 0 : switch (Mnemonic[15]) {
13044 : default: break;
13045 : case '3': // 1 string to match.
13046 0 : if (Mnemonic[16] != '2')
13047 : break;
13048 0 : Mnemonic = "v_cvt_f32_i32"; // "v_cvt_f32_i32_e32"
13049 0 : return;
13050 : case '6': // 1 string to match.
13051 0 : if (Mnemonic[16] != '4')
13052 : break;
13053 0 : Mnemonic = "v_cvt_f32_i32"; // "v_cvt_f32_i32_e64"
13054 0 : return;
13055 : }
13056 : break;
13057 : case 'u': // 2 strings to match.
13058 0 : if (memcmp(Mnemonic.data()+11, "32_e", 4))
13059 : break;
13060 0 : switch (Mnemonic[15]) {
13061 : default: break;
13062 : case '3': // 1 string to match.
13063 0 : if (Mnemonic[16] != '2')
13064 : break;
13065 0 : Mnemonic = "v_cvt_f32_u32"; // "v_cvt_f32_u32_e32"
13066 0 : return;
13067 : case '6': // 1 string to match.
13068 0 : if (Mnemonic[16] != '4')
13069 : break;
13070 0 : Mnemonic = "v_cvt_f32_u32"; // "v_cvt_f32_u32_e64"
13071 0 : return;
13072 : }
13073 : break;
13074 : }
13075 : break;
13076 : case '6': // 6 strings to match.
13077 0 : if (memcmp(Mnemonic.data()+8, "4_", 2))
13078 : break;
13079 0 : switch (Mnemonic[10]) {
13080 : default: break;
13081 : case 'f': // 2 strings to match.
13082 0 : if (memcmp(Mnemonic.data()+11, "32_e", 4))
13083 : break;
13084 0 : switch (Mnemonic[15]) {
13085 : default: break;
13086 : case '3': // 1 string to match.
13087 0 : if (Mnemonic[16] != '2')
13088 : break;
13089 0 : Mnemonic = "v_cvt_f64_f32"; // "v_cvt_f64_f32_e32"
13090 0 : return;
13091 : case '6': // 1 string to match.
13092 0 : if (Mnemonic[16] != '4')
13093 : break;
13094 0 : Mnemonic = "v_cvt_f64_f32"; // "v_cvt_f64_f32_e64"
13095 0 : return;
13096 : }
13097 : break;
13098 : case 'i': // 2 strings to match.
13099 0 : if (memcmp(Mnemonic.data()+11, "32_e", 4))
13100 : break;
13101 0 : switch (Mnemonic[15]) {
13102 : default: break;
13103 : case '3': // 1 string to match.
13104 0 : if (Mnemonic[16] != '2')
13105 : break;
13106 0 : Mnemonic = "v_cvt_f64_i32"; // "v_cvt_f64_i32_e32"
13107 0 : return;
13108 : case '6': // 1 string to match.
13109 0 : if (Mnemonic[16] != '4')
13110 : break;
13111 0 : Mnemonic = "v_cvt_f64_i32"; // "v_cvt_f64_i32_e64"
13112 0 : return;
13113 : }
13114 : break;
13115 : case 'u': // 2 strings to match.
13116 0 : if (memcmp(Mnemonic.data()+11, "32_e", 4))
13117 : break;
13118 0 : switch (Mnemonic[15]) {
13119 : default: break;
13120 : case '3': // 1 string to match.
13121 0 : if (Mnemonic[16] != '2')
13122 : break;
13123 0 : Mnemonic = "v_cvt_f64_u32"; // "v_cvt_f64_u32_e32"
13124 0 : return;
13125 : case '6': // 1 string to match.
13126 0 : if (Mnemonic[16] != '4')
13127 : break;
13128 0 : Mnemonic = "v_cvt_f64_u32"; // "v_cvt_f64_u32_e64"
13129 0 : return;
13130 : }
13131 : break;
13132 : }
13133 : break;
13134 : }
13135 : break;
13136 : case 'i': // 6 strings to match.
13137 0 : switch (Mnemonic[7]) {
13138 : default: break;
13139 : case '1': // 2 strings to match.
13140 0 : if (memcmp(Mnemonic.data()+8, "6_f16_e", 7))
13141 : break;
13142 0 : switch (Mnemonic[15]) {
13143 : default: break;
13144 : case '3': // 1 string to match.
13145 0 : if (Mnemonic[16] != '2')
13146 : break;
13147 0 : Mnemonic = "v_cvt_i16_f16"; // "v_cvt_i16_f16_e32"
13148 0 : return;
13149 : case '6': // 1 string to match.
13150 0 : if (Mnemonic[16] != '4')
13151 : break;
13152 0 : Mnemonic = "v_cvt_i16_f16"; // "v_cvt_i16_f16_e64"
13153 0 : return;
13154 : }
13155 : break;
13156 : case '3': // 4 strings to match.
13157 0 : if (memcmp(Mnemonic.data()+8, "2_f", 3))
13158 : break;
13159 0 : switch (Mnemonic[11]) {
13160 : default: break;
13161 : case '3': // 2 strings to match.
13162 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
13163 : break;
13164 0 : switch (Mnemonic[15]) {
13165 : default: break;
13166 : case '3': // 1 string to match.
13167 0 : if (Mnemonic[16] != '2')
13168 : break;
13169 0 : Mnemonic = "v_cvt_i32_f32"; // "v_cvt_i32_f32_e32"
13170 0 : return;
13171 : case '6': // 1 string to match.
13172 0 : if (Mnemonic[16] != '4')
13173 : break;
13174 0 : Mnemonic = "v_cvt_i32_f32"; // "v_cvt_i32_f32_e64"
13175 0 : return;
13176 : }
13177 : break;
13178 : case '6': // 2 strings to match.
13179 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
13180 : break;
13181 0 : switch (Mnemonic[15]) {
13182 : default: break;
13183 : case '3': // 1 string to match.
13184 0 : if (Mnemonic[16] != '2')
13185 : break;
13186 0 : Mnemonic = "v_cvt_i32_f64"; // "v_cvt_i32_f64_e32"
13187 0 : return;
13188 : case '6': // 1 string to match.
13189 0 : if (Mnemonic[16] != '4')
13190 : break;
13191 0 : Mnemonic = "v_cvt_i32_f64"; // "v_cvt_i32_f64_e64"
13192 0 : return;
13193 : }
13194 : break;
13195 : }
13196 : break;
13197 : }
13198 : break;
13199 : case 'u': // 6 strings to match.
13200 0 : switch (Mnemonic[7]) {
13201 : default: break;
13202 : case '1': // 2 strings to match.
13203 0 : if (memcmp(Mnemonic.data()+8, "6_f16_e", 7))
13204 : break;
13205 0 : switch (Mnemonic[15]) {
13206 : default: break;
13207 : case '3': // 1 string to match.
13208 0 : if (Mnemonic[16] != '2')
13209 : break;
13210 0 : Mnemonic = "v_cvt_u16_f16"; // "v_cvt_u16_f16_e32"
13211 0 : return;
13212 : case '6': // 1 string to match.
13213 0 : if (Mnemonic[16] != '4')
13214 : break;
13215 0 : Mnemonic = "v_cvt_u16_f16"; // "v_cvt_u16_f16_e64"
13216 0 : return;
13217 : }
13218 : break;
13219 : case '3': // 4 strings to match.
13220 0 : if (memcmp(Mnemonic.data()+8, "2_f", 3))
13221 : break;
13222 0 : switch (Mnemonic[11]) {
13223 : default: break;
13224 : case '3': // 2 strings to match.
13225 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
13226 : break;
13227 0 : switch (Mnemonic[15]) {
13228 : default: break;
13229 : case '3': // 1 string to match.
13230 0 : if (Mnemonic[16] != '2')
13231 : break;
13232 0 : Mnemonic = "v_cvt_u32_f32"; // "v_cvt_u32_f32_e32"
13233 0 : return;
13234 : case '6': // 1 string to match.
13235 0 : if (Mnemonic[16] != '4')
13236 : break;
13237 0 : Mnemonic = "v_cvt_u32_f32"; // "v_cvt_u32_f32_e64"
13238 0 : return;
13239 : }
13240 : break;
13241 : case '6': // 2 strings to match.
13242 0 : if (memcmp(Mnemonic.data()+12, "4_e", 3))
13243 : break;
13244 0 : switch (Mnemonic[15]) {
13245 : default: break;
13246 : case '3': // 1 string to match.
13247 0 : if (Mnemonic[16] != '2')
13248 : break;
13249 0 : Mnemonic = "v_cvt_u32_f64"; // "v_cvt_u32_f64_e32"
13250 0 : return;
13251 : case '6': // 1 string to match.
13252 0 : if (Mnemonic[16] != '4')
13253 : break;
13254 0 : Mnemonic = "v_cvt_u32_f64"; // "v_cvt_u32_f64_e64"
13255 0 : return;
13256 : }
13257 : break;
13258 : }
13259 : break;
13260 : }
13261 : break;
13262 : }
13263 : break;
13264 : }
13265 : break;
13266 : case 'l': // 10 strings to match.
13267 0 : if (memcmp(Mnemonic.data()+3, "sh", 2))
13268 : break;
13269 0 : switch (Mnemonic[5]) {
13270 : default: break;
13271 : case 'l': // 5 strings to match.
13272 0 : if (memcmp(Mnemonic.data()+6, "rev_b", 5))
13273 : break;
13274 0 : switch (Mnemonic[11]) {
13275 : default: break;
13276 : case '1': // 2 strings to match.
13277 0 : if (memcmp(Mnemonic.data()+12, "6_e", 3))
13278 : break;
13279 0 : switch (Mnemonic[15]) {
13280 : default: break;
13281 : case '3': // 1 string to match.
13282 0 : if (Mnemonic[16] != '2')
13283 : break;
13284 0 : Mnemonic = "v_lshlrev_b16"; // "v_lshlrev_b16_e32"
13285 0 : return;
13286 : case '6': // 1 string to match.
13287 0 : if (Mnemonic[16] != '4')
13288 : break;
13289 0 : Mnemonic = "v_lshlrev_b16"; // "v_lshlrev_b16_e64"
13290 0 : return;
13291 : }
13292 : break;
13293 : case '3': // 2 strings to match.
13294 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
13295 : break;
13296 0 : switch (Mnemonic[15]) {
13297 : default: break;
13298 : case '3': // 1 string to match.
13299 0 : if (Mnemonic[16] != '2')
13300 : break;
13301 0 : Mnemonic = "v_lshlrev_b32"; // "v_lshlrev_b32_e32"
13302 0 : return;
13303 : case '6': // 1 string to match.
13304 0 : if (Mnemonic[16] != '4')
13305 : break;
13306 0 : Mnemonic = "v_lshlrev_b32"; // "v_lshlrev_b32_e64"
13307 0 : return;
13308 : }
13309 : break;
13310 : case '6': // 1 string to match.
13311 0 : if (memcmp(Mnemonic.data()+12, "4_e64", 5))
13312 : break;
13313 0 : Mnemonic = "v_lshlrev_b64"; // "v_lshlrev_b64_e64"
13314 0 : return;
13315 : }
13316 : break;
13317 : case 'r': // 5 strings to match.
13318 0 : if (memcmp(Mnemonic.data()+6, "rev_b", 5))
13319 : break;
13320 0 : switch (Mnemonic[11]) {
13321 : default: break;
13322 : case '1': // 2 strings to match.
13323 0 : if (memcmp(Mnemonic.data()+12, "6_e", 3))
13324 : break;
13325 0 : switch (Mnemonic[15]) {
13326 : default: break;
13327 : case '3': // 1 string to match.
13328 0 : if (Mnemonic[16] != '2')
13329 : break;
13330 0 : Mnemonic = "v_lshrrev_b16"; // "v_lshrrev_b16_e32"
13331 0 : return;
13332 : case '6': // 1 string to match.
13333 0 : if (Mnemonic[16] != '4')
13334 : break;
13335 0 : Mnemonic = "v_lshrrev_b16"; // "v_lshrrev_b16_e64"
13336 0 : return;
13337 : }
13338 : break;
13339 : case '3': // 2 strings to match.
13340 0 : if (memcmp(Mnemonic.data()+12, "2_e", 3))
13341 : break;
13342 0 : switch (Mnemonic[15]) {
13343 : default: break;
13344 : case '3': // 1 string to match.
13345 0 : if (Mnemonic[16] != '2')
13346 : break;
13347 0 : Mnemonic = "v_lshrrev_b32"; // "v_lshrrev_b32_e32"
13348 0 : return;
13349 : case '6': // 1 string to match.
13350 0 : if (Mnemonic[16] != '4')
13351 : break;
13352 0 : Mnemonic = "v_lshrrev_b32"; // "v_lshrrev_b32_e64"
13353 0 : return;
13354 : }
13355 : break;
13356 : case '6': // 1 string to match.
13357 0 : if (memcmp(Mnemonic.data()+12, "4_e64", 5))
13358 : break;
13359 0 : Mnemonic = "v_lshrrev_b64"; // "v_lshrrev_b64_e64"
13360 0 : return;
13361 : }
13362 : break;
13363 : }
13364 : break;
13365 : case 'm': // 14 strings to match.
13366 0 : switch (Mnemonic[3]) {
13367 : default: break;
13368 : case 'a': // 4 strings to match.
13369 0 : if (memcmp(Mnemonic.data()+4, "d_", 2))
13370 : break;
13371 0 : switch (Mnemonic[6]) {
13372 : default: break;
13373 : case 'i': // 2 strings to match.
13374 0 : switch (Mnemonic[7]) {
13375 : default: break;
13376 : case '3': // 1 string to match.
13377 0 : if (memcmp(Mnemonic.data()+8, "2_i24_e64", 9))
13378 : break;
13379 0 : Mnemonic = "v_mad_i32_i24"; // "v_mad_i32_i24_e64"
13380 0 : return;
13381 : case '6': // 1 string to match.
13382 0 : if (memcmp(Mnemonic.data()+8, "4_i32_e64", 9))
13383 : break;
13384 0 : if ((Features & Feature_isGCN) == Feature_isGCN) // "v_mad_i64_i32_e64"
13385 0 : Mnemonic = "v_mad_i64_i32";
13386 : return;
13387 : }
13388 : break;
13389 : case 'u': // 2 strings to match.
13390 0 : switch (Mnemonic[7]) {
13391 : default: break;
13392 : case '3': // 1 string to match.
13393 0 : if (memcmp(Mnemonic.data()+8, "2_u24_e64", 9))
13394 : break;
13395 0 : Mnemonic = "v_mad_u32_u24"; // "v_mad_u32_u24_e64"
13396 0 : return;
13397 : case '6': // 1 string to match.
13398 0 : if (memcmp(Mnemonic.data()+8, "4_u32_e64", 9))
13399 : break;
13400 0 : if ((Features & Feature_isGCN) == Feature_isGCN) // "v_mad_u64_u32_e64"
13401 0 : Mnemonic = "v_mad_u64_u32";
13402 : return;
13403 : }
13404 : break;
13405 : }
13406 : break;
13407 : case 'o': // 6 strings to match.
13408 0 : if (Mnemonic[4] != 'v')
13409 : break;
13410 0 : switch (Mnemonic[5]) {
13411 : default: break;
13412 : case '_': // 2 strings to match.
13413 0 : if (memcmp(Mnemonic.data()+6, "fed_b32_e", 9))
13414 : break;
13415 0 : switch (Mnemonic[15]) {
13416 : default: break;
13417 : case '3': // 1 string to match.
13418 0 : if (Mnemonic[16] != '2')
13419 : break;
13420 0 : Mnemonic = "v_mov_fed_b32"; // "v_mov_fed_b32_e32"
13421 0 : return;
13422 : case '6': // 1 string to match.
13423 0 : if (Mnemonic[16] != '4')
13424 : break;
13425 0 : Mnemonic = "v_mov_fed_b32"; // "v_mov_fed_b32_e64"
13426 0 : return;
13427 : }
13428 : break;
13429 : case 'r': // 4 strings to match.
13430 0 : if (memcmp(Mnemonic.data()+6, "el", 2))
13431 : break;
13432 0 : switch (Mnemonic[8]) {
13433 : default: break;
13434 : case 'd': // 2 strings to match.
13435 0 : if (memcmp(Mnemonic.data()+9, "_b32_e", 6))
13436 : break;
13437 0 : switch (Mnemonic[15]) {
13438 : default: break;
13439 : case '3': // 1 string to match.
13440 0 : if (Mnemonic[16] != '2')
13441 : break;
13442 0 : Mnemonic = "v_movreld_b32"; // "v_movreld_b32_e32"
13443 0 : return;
13444 : case '6': // 1 string to match.
13445 0 : if (Mnemonic[16] != '4')
13446 : break;
13447 0 : Mnemonic = "v_movreld_b32"; // "v_movreld_b32_e64"
13448 0 : return;
13449 : }
13450 : break;
13451 : case 's': // 2 strings to match.
13452 0 : if (memcmp(Mnemonic.data()+9, "_b32_e", 6))
13453 : break;
13454 0 : switch (Mnemonic[15]) {
13455 : default: break;
13456 : case '3': // 1 string to match.
13457 0 : if (Mnemonic[16] != '2')
13458 : break;
13459 0 : Mnemonic = "v_movrels_b32"; // "v_movrels_b32_e32"
13460 0 : return;
13461 : case '6': // 1 string to match.
13462 0 : if (Mnemonic[16] != '4')
13463 : break;
13464 0 : Mnemonic = "v_movrels_b32"; // "v_movrels_b32_e64"
13465 0 : return;
13466 : }
13467 : break;
13468 : }
13469 : break;
13470 : }
13471 : break;
13472 : case 'u': // 4 strings to match.
13473 0 : if (memcmp(Mnemonic.data()+4, "l_", 2))
13474 : break;
13475 0 : switch (Mnemonic[6]) {
13476 : default: break;
13477 : case 'i': // 2 strings to match.
13478 0 : if (memcmp(Mnemonic.data()+7, "32_i24_e", 8))
13479 : break;
13480 0 : switch (Mnemonic[15]) {
13481 : default: break;
13482 : case '3': // 1 string to match.
13483 0 : if (Mnemonic[16] != '2')
13484 : break;
13485 0 : Mnemonic = "v_mul_i32_i24"; // "v_mul_i32_i24_e32"
13486 0 : return;
13487 : case '6': // 1 string to match.
13488 0 : if (Mnemonic[16] != '4')
13489 : break;
13490 0 : Mnemonic = "v_mul_i32_i24"; // "v_mul_i32_i24_e64"
13491 0 : return;
13492 : }
13493 : break;
13494 : case 'u': // 2 strings to match.
13495 0 : if (memcmp(Mnemonic.data()+7, "32_u24_e", 8))
13496 : break;
13497 0 : switch (Mnemonic[15]) {
13498 : default: break;
13499 : case '3': // 1 string to match.
13500 0 : if (Mnemonic[16] != '2')
13501 : break;
13502 0 : Mnemonic = "v_mul_u32_u24"; // "v_mul_u32_u24_e32"
13503 0 : return;
13504 : case '6': // 1 string to match.
13505 0 : if (Mnemonic[16] != '4')
13506 : break;
13507 0 : Mnemonic = "v_mul_u32_u24"; // "v_mul_u32_u24_e64"
13508 0 : return;
13509 : }
13510 : break;
13511 : }
13512 : break;
13513 : }
13514 : break;
13515 : case 's': // 2 strings to match.
13516 0 : if (memcmp(Mnemonic.data()+3, "ubbrev_u32_e", 12))
13517 : break;
13518 0 : switch (Mnemonic[15]) {
13519 : default: break;
13520 : case '3': // 1 string to match.
13521 0 : if (Mnemonic[16] != '2')
13522 : break;
13523 0 : Mnemonic = "v_subbrev_u32"; // "v_subbrev_u32_e32"
13524 0 : return;
13525 : case '6': // 1 string to match.
13526 0 : if (Mnemonic[16] != '4')
13527 : break;
13528 0 : Mnemonic = "v_subbrev_u32"; // "v_subbrev_u32_e64"
13529 0 : return;
13530 : }
13531 : break;
13532 : }
13533 : break;
13534 : case 18: // 89 strings to match.
13535 116 : if (memcmp(Mnemonic.data()+0, "v_", 2))
13536 : break;
13537 32 : switch (Mnemonic[2]) {
13538 : default: break;
13539 : case 'a': // 1 string to match.
13540 0 : if (memcmp(Mnemonic.data()+3, "lignbit_b32_e64", 15))
13541 : break;
13542 0 : Mnemonic = "v_alignbit_b32"; // "v_alignbit_b32_e64"
13543 0 : return;
13544 : case 'b': // 2 strings to match.
13545 0 : if (memcmp(Mnemonic.data()+3, "cnt_u32_b32_e", 13))
13546 : break;
13547 0 : switch (Mnemonic[16]) {
13548 : default: break;
13549 : case '3': // 1 string to match.
13550 0 : if (Mnemonic[17] != '2')
13551 : break;
13552 0 : Mnemonic = "v_bcnt_u32_b32"; // "v_bcnt_u32_b32_e32"
13553 0 : return;
13554 : case '6': // 1 string to match.
13555 0 : if (Mnemonic[17] != '4')
13556 : break;
13557 0 : Mnemonic = "v_bcnt_u32_b32"; // "v_bcnt_u32_b32_e64"
13558 0 : return;
13559 : }
13560 : break;
13561 : case 'c': // 80 strings to match.
13562 0 : if (memcmp(Mnemonic.data()+3, "mp", 2))
13563 : break;
13564 0 : switch (Mnemonic[5]) {
13565 : default: break;
13566 : case 's': // 52 strings to match.
13567 0 : switch (Mnemonic[6]) {
13568 : default: break;
13569 : case '_': // 28 strings to match.
13570 0 : switch (Mnemonic[7]) {
13571 : default: break;
13572 : case 'n': // 24 strings to match.
13573 0 : switch (Mnemonic[8]) {
13574 : default: break;
13575 : case 'e': // 4 strings to match.
13576 0 : if (memcmp(Mnemonic.data()+9, "q_f", 3))
13577 : break;
13578 0 : switch (Mnemonic[12]) {
13579 : default: break;
13580 : case '3': // 2 strings to match.
13581 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
13582 : break;
13583 0 : switch (Mnemonic[16]) {
13584 : default: break;
13585 : case '3': // 1 string to match.
13586 0 : if (Mnemonic[17] != '2')
13587 : break;
13588 0 : Mnemonic = "v_cmps_neq_f32"; // "v_cmps_neq_f32_e32"
13589 0 : return;
13590 : case '6': // 1 string to match.
13591 0 : if (Mnemonic[17] != '4')
13592 : break;
13593 0 : Mnemonic = "v_cmps_neq_f32"; // "v_cmps_neq_f32_e64"
13594 0 : return;
13595 : }
13596 : break;
13597 : case '6': // 2 strings to match.
13598 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
13599 : break;
13600 0 : switch (Mnemonic[16]) {
13601 : default: break;
13602 : case '3': // 1 string to match.
13603 0 : if (Mnemonic[17] != '2')
13604 : break;
13605 0 : Mnemonic = "v_cmps_neq_f64"; // "v_cmps_neq_f64_e32"
13606 0 : return;
13607 : case '6': // 1 string to match.
13608 0 : if (Mnemonic[17] != '4')
13609 : break;
13610 0 : Mnemonic = "v_cmps_neq_f64"; // "v_cmps_neq_f64_e64"
13611 0 : return;
13612 : }
13613 : break;
13614 : }
13615 : break;
13616 : case 'g': // 8 strings to match.
13617 0 : switch (Mnemonic[9]) {
13618 : default: break;
13619 : case 'e': // 4 strings to match.
13620 0 : if (memcmp(Mnemonic.data()+10, "_f", 2))
13621 : break;
13622 0 : switch (Mnemonic[12]) {
13623 : default: break;
13624 : case '3': // 2 strings to match.
13625 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
13626 : break;
13627 0 : switch (Mnemonic[16]) {
13628 : default: break;
13629 : case '3': // 1 string to match.
13630 0 : if (Mnemonic[17] != '2')
13631 : break;
13632 0 : Mnemonic = "v_cmps_nge_f32"; // "v_cmps_nge_f32_e32"
13633 0 : return;
13634 : case '6': // 1 string to match.
13635 0 : if (Mnemonic[17] != '4')
13636 : break;
13637 0 : Mnemonic = "v_cmps_nge_f32"; // "v_cmps_nge_f32_e64"
13638 0 : return;
13639 : }
13640 : break;
13641 : case '6': // 2 strings to match.
13642 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
13643 : break;
13644 0 : switch (Mnemonic[16]) {
13645 : default: break;
13646 : case '3': // 1 string to match.
13647 0 : if (Mnemonic[17] != '2')
13648 : break;
13649 0 : Mnemonic = "v_cmps_nge_f64"; // "v_cmps_nge_f64_e32"
13650 0 : return;
13651 : case '6': // 1 string to match.
13652 0 : if (Mnemonic[17] != '4')
13653 : break;
13654 0 : Mnemonic = "v_cmps_nge_f64"; // "v_cmps_nge_f64_e64"
13655 0 : return;
13656 : }
13657 : break;
13658 : }
13659 : break;
13660 : case 't': // 4 strings to match.
13661 0 : if (memcmp(Mnemonic.data()+10, "_f", 2))
13662 : break;
13663 0 : switch (Mnemonic[12]) {
13664 : default: break;
13665 : case '3': // 2 strings to match.
13666 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
13667 : break;
13668 0 : switch (Mnemonic[16]) {
13669 : default: break;
13670 : case '3': // 1 string to match.
13671 0 : if (Mnemonic[17] != '2')
13672 : break;
13673 0 : Mnemonic = "v_cmps_ngt_f32"; // "v_cmps_ngt_f32_e32"
13674 0 : return;
13675 : case '6': // 1 string to match.
13676 0 : if (Mnemonic[17] != '4')
13677 : break;
13678 0 : Mnemonic = "v_cmps_ngt_f32"; // "v_cmps_ngt_f32_e64"
13679 0 : return;
13680 : }
13681 : break;
13682 : case '6': // 2 strings to match.
13683 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
13684 : break;
13685 0 : switch (Mnemonic[16]) {
13686 : default: break;
13687 : case '3': // 1 string to match.
13688 0 : if (Mnemonic[17] != '2')
13689 : break;
13690 0 : Mnemonic = "v_cmps_ngt_f64"; // "v_cmps_ngt_f64_e32"
13691 0 : return;
13692 : case '6': // 1 string to match.
13693 0 : if (Mnemonic[17] != '4')
13694 : break;
13695 0 : Mnemonic = "v_cmps_ngt_f64"; // "v_cmps_ngt_f64_e64"
13696 0 : return;
13697 : }
13698 : break;
13699 : }
13700 : break;
13701 : }
13702 : break;
13703 : case 'l': // 12 strings to match.
13704 0 : switch (Mnemonic[9]) {
13705 : default: break;
13706 : case 'e': // 4 strings to match.
13707 0 : if (memcmp(Mnemonic.data()+10, "_f", 2))
13708 : break;
13709 0 : switch (Mnemonic[12]) {
13710 : default: break;
13711 : case '3': // 2 strings to match.
13712 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
13713 : break;
13714 0 : switch (Mnemonic[16]) {
13715 : default: break;
13716 : case '3': // 1 string to match.
13717 0 : if (Mnemonic[17] != '2')
13718 : break;
13719 0 : Mnemonic = "v_cmps_nle_f32"; // "v_cmps_nle_f32_e32"
13720 0 : return;
13721 : case '6': // 1 string to match.
13722 0 : if (Mnemonic[17] != '4')
13723 : break;
13724 0 : Mnemonic = "v_cmps_nle_f32"; // "v_cmps_nle_f32_e64"
13725 0 : return;
13726 : }
13727 : break;
13728 : case '6': // 2 strings to match.
13729 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
13730 : break;
13731 0 : switch (Mnemonic[16]) {
13732 : default: break;
13733 : case '3': // 1 string to match.
13734 0 : if (Mnemonic[17] != '2')
13735 : break;
13736 0 : Mnemonic = "v_cmps_nle_f64"; // "v_cmps_nle_f64_e32"
13737 0 : return;
13738 : case '6': // 1 string to match.
13739 0 : if (Mnemonic[17] != '4')
13740 : break;
13741 0 : Mnemonic = "v_cmps_nle_f64"; // "v_cmps_nle_f64_e64"
13742 0 : return;
13743 : }
13744 : break;
13745 : }
13746 : break;
13747 : case 'g': // 4 strings to match.
13748 0 : if (memcmp(Mnemonic.data()+10, "_f", 2))
13749 : break;
13750 0 : switch (Mnemonic[12]) {
13751 : default: break;
13752 : case '3': // 2 strings to match.
13753 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
13754 : break;
13755 0 : switch (Mnemonic[16]) {
13756 : default: break;
13757 : case '3': // 1 string to match.
13758 0 : if (Mnemonic[17] != '2')
13759 : break;
13760 0 : Mnemonic = "v_cmps_nlg_f32"; // "v_cmps_nlg_f32_e32"
13761 0 : return;
13762 : case '6': // 1 string to match.
13763 0 : if (Mnemonic[17] != '4')
13764 : break;
13765 0 : Mnemonic = "v_cmps_nlg_f32"; // "v_cmps_nlg_f32_e64"
13766 0 : return;
13767 : }
13768 : break;
13769 : case '6': // 2 strings to match.
13770 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
13771 : break;
13772 0 : switch (Mnemonic[16]) {
13773 : default: break;
13774 : case '3': // 1 string to match.
13775 0 : if (Mnemonic[17] != '2')
13776 : break;
13777 0 : Mnemonic = "v_cmps_nlg_f64"; // "v_cmps_nlg_f64_e32"
13778 0 : return;
13779 : case '6': // 1 string to match.
13780 0 : if (Mnemonic[17] != '4')
13781 : break;
13782 0 : Mnemonic = "v_cmps_nlg_f64"; // "v_cmps_nlg_f64_e64"
13783 0 : return;
13784 : }
13785 : break;
13786 : }
13787 : break;
13788 : case 't': // 4 strings to match.
13789 0 : if (memcmp(Mnemonic.data()+10, "_f", 2))
13790 : break;
13791 0 : switch (Mnemonic[12]) {
13792 : default: break;
13793 : case '3': // 2 strings to match.
13794 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
13795 : break;
13796 0 : switch (Mnemonic[16]) {
13797 : default: break;
13798 : case '3': // 1 string to match.
13799 0 : if (Mnemonic[17] != '2')
13800 : break;
13801 0 : Mnemonic = "v_cmps_nlt_f32"; // "v_cmps_nlt_f32_e32"
13802 0 : return;
13803 : case '6': // 1 string to match.
13804 0 : if (Mnemonic[17] != '4')
13805 : break;
13806 0 : Mnemonic = "v_cmps_nlt_f32"; // "v_cmps_nlt_f32_e64"
13807 0 : return;
13808 : }
13809 : break;
13810 : case '6': // 2 strings to match.
13811 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
13812 : break;
13813 0 : switch (Mnemonic[16]) {
13814 : default: break;
13815 : case '3': // 1 string to match.
13816 0 : if (Mnemonic[17] != '2')
13817 : break;
13818 0 : Mnemonic = "v_cmps_nlt_f64"; // "v_cmps_nlt_f64_e32"
13819 0 : return;
13820 : case '6': // 1 string to match.
13821 0 : if (Mnemonic[17] != '4')
13822 : break;
13823 0 : Mnemonic = "v_cmps_nlt_f64"; // "v_cmps_nlt_f64_e64"
13824 0 : return;
13825 : }
13826 : break;
13827 : }
13828 : break;
13829 : }
13830 : break;
13831 : }
13832 : break;
13833 : case 't': // 4 strings to match.
13834 0 : if (memcmp(Mnemonic.data()+8, "ru_f", 4))
13835 : break;
13836 0 : switch (Mnemonic[12]) {
13837 : default: break;
13838 : case '3': // 2 strings to match.
13839 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
13840 : break;
13841 0 : switch (Mnemonic[16]) {
13842 : default: break;
13843 : case '3': // 1 string to match.
13844 0 : if (Mnemonic[17] != '2')
13845 : break;
13846 0 : Mnemonic = "v_cmps_tru_f32"; // "v_cmps_tru_f32_e32"
13847 0 : return;
13848 : case '6': // 1 string to match.
13849 0 : if (Mnemonic[17] != '4')
13850 : break;
13851 0 : Mnemonic = "v_cmps_tru_f32"; // "v_cmps_tru_f32_e64"
13852 0 : return;
13853 : }
13854 : break;
13855 : case '6': // 2 strings to match.
13856 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
13857 : break;
13858 0 : switch (Mnemonic[16]) {
13859 : default: break;
13860 : case '3': // 1 string to match.
13861 0 : if (Mnemonic[17] != '2')
13862 : break;
13863 0 : Mnemonic = "v_cmps_tru_f64"; // "v_cmps_tru_f64_e32"
13864 0 : return;
13865 : case '6': // 1 string to match.
13866 0 : if (Mnemonic[17] != '4')
13867 : break;
13868 0 : Mnemonic = "v_cmps_tru_f64"; // "v_cmps_tru_f64_e64"
13869 0 : return;
13870 : }
13871 : break;
13872 : }
13873 : break;
13874 : }
13875 : break;
13876 : case 'x': // 24 strings to match.
13877 0 : if (Mnemonic[7] != '_')
13878 : break;
13879 0 : switch (Mnemonic[8]) {
13880 : default: break;
13881 : case 'e': // 4 strings to match.
13882 0 : if (memcmp(Mnemonic.data()+9, "q_f", 3))
13883 : break;
13884 0 : switch (Mnemonic[12]) {
13885 : default: break;
13886 : case '3': // 2 strings to match.
13887 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
13888 : break;
13889 0 : switch (Mnemonic[16]) {
13890 : default: break;
13891 : case '3': // 1 string to match.
13892 0 : if (Mnemonic[17] != '2')
13893 : break;
13894 0 : Mnemonic = "v_cmpsx_eq_f32"; // "v_cmpsx_eq_f32_e32"
13895 0 : return;
13896 : case '6': // 1 string to match.
13897 0 : if (Mnemonic[17] != '4')
13898 : break;
13899 0 : Mnemonic = "v_cmpsx_eq_f32"; // "v_cmpsx_eq_f32_e64"
13900 0 : return;
13901 : }
13902 : break;
13903 : case '6': // 2 strings to match.
13904 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
13905 : break;
13906 0 : switch (Mnemonic[16]) {
13907 : default: break;
13908 : case '3': // 1 string to match.
13909 0 : if (Mnemonic[17] != '2')
13910 : break;
13911 0 : Mnemonic = "v_cmpsx_eq_f64"; // "v_cmpsx_eq_f64_e32"
13912 0 : return;
13913 : case '6': // 1 string to match.
13914 0 : if (Mnemonic[17] != '4')
13915 : break;
13916 0 : Mnemonic = "v_cmpsx_eq_f64"; // "v_cmpsx_eq_f64_e64"
13917 0 : return;
13918 : }
13919 : break;
13920 : }
13921 : break;
13922 : case 'g': // 8 strings to match.
13923 0 : switch (Mnemonic[9]) {
13924 : default: break;
13925 : case 'e': // 4 strings to match.
13926 0 : if (memcmp(Mnemonic.data()+10, "_f", 2))
13927 : break;
13928 0 : switch (Mnemonic[12]) {
13929 : default: break;
13930 : case '3': // 2 strings to match.
13931 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
13932 : break;
13933 0 : switch (Mnemonic[16]) {
13934 : default: break;
13935 : case '3': // 1 string to match.
13936 0 : if (Mnemonic[17] != '2')
13937 : break;
13938 0 : Mnemonic = "v_cmpsx_ge_f32"; // "v_cmpsx_ge_f32_e32"
13939 0 : return;
13940 : case '6': // 1 string to match.
13941 0 : if (Mnemonic[17] != '4')
13942 : break;
13943 0 : Mnemonic = "v_cmpsx_ge_f32"; // "v_cmpsx_ge_f32_e64"
13944 0 : return;
13945 : }
13946 : break;
13947 : case '6': // 2 strings to match.
13948 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
13949 : break;
13950 0 : switch (Mnemonic[16]) {
13951 : default: break;
13952 : case '3': // 1 string to match.
13953 0 : if (Mnemonic[17] != '2')
13954 : break;
13955 0 : Mnemonic = "v_cmpsx_ge_f64"; // "v_cmpsx_ge_f64_e32"
13956 0 : return;
13957 : case '6': // 1 string to match.
13958 0 : if (Mnemonic[17] != '4')
13959 : break;
13960 0 : Mnemonic = "v_cmpsx_ge_f64"; // "v_cmpsx_ge_f64_e64"
13961 0 : return;
13962 : }
13963 : break;
13964 : }
13965 : break;
13966 : case 't': // 4 strings to match.
13967 0 : if (memcmp(Mnemonic.data()+10, "_f", 2))
13968 : break;
13969 0 : switch (Mnemonic[12]) {
13970 : default: break;
13971 : case '3': // 2 strings to match.
13972 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
13973 : break;
13974 0 : switch (Mnemonic[16]) {
13975 : default: break;
13976 : case '3': // 1 string to match.
13977 0 : if (Mnemonic[17] != '2')
13978 : break;
13979 0 : Mnemonic = "v_cmpsx_gt_f32"; // "v_cmpsx_gt_f32_e32"
13980 0 : return;
13981 : case '6': // 1 string to match.
13982 0 : if (Mnemonic[17] != '4')
13983 : break;
13984 0 : Mnemonic = "v_cmpsx_gt_f32"; // "v_cmpsx_gt_f32_e64"
13985 0 : return;
13986 : }
13987 : break;
13988 : case '6': // 2 strings to match.
13989 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
13990 : break;
13991 0 : switch (Mnemonic[16]) {
13992 : default: break;
13993 : case '3': // 1 string to match.
13994 0 : if (Mnemonic[17] != '2')
13995 : break;
13996 0 : Mnemonic = "v_cmpsx_gt_f64"; // "v_cmpsx_gt_f64_e32"
13997 0 : return;
13998 : case '6': // 1 string to match.
13999 0 : if (Mnemonic[17] != '4')
14000 : break;
14001 0 : Mnemonic = "v_cmpsx_gt_f64"; // "v_cmpsx_gt_f64_e64"
14002 0 : return;
14003 : }
14004 : break;
14005 : }
14006 : break;
14007 : }
14008 : break;
14009 : case 'l': // 12 strings to match.
14010 0 : switch (Mnemonic[9]) {
14011 : default: break;
14012 : case 'e': // 4 strings to match.
14013 0 : if (memcmp(Mnemonic.data()+10, "_f", 2))
14014 : break;
14015 0 : switch (Mnemonic[12]) {
14016 : default: break;
14017 : case '3': // 2 strings to match.
14018 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
14019 : break;
14020 0 : switch (Mnemonic[16]) {
14021 : default: break;
14022 : case '3': // 1 string to match.
14023 0 : if (Mnemonic[17] != '2')
14024 : break;
14025 0 : Mnemonic = "v_cmpsx_le_f32"; // "v_cmpsx_le_f32_e32"
14026 0 : return;
14027 : case '6': // 1 string to match.
14028 0 : if (Mnemonic[17] != '4')
14029 : break;
14030 0 : Mnemonic = "v_cmpsx_le_f32"; // "v_cmpsx_le_f32_e64"
14031 0 : return;
14032 : }
14033 : break;
14034 : case '6': // 2 strings to match.
14035 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
14036 : break;
14037 0 : switch (Mnemonic[16]) {
14038 : default: break;
14039 : case '3': // 1 string to match.
14040 0 : if (Mnemonic[17] != '2')
14041 : break;
14042 0 : Mnemonic = "v_cmpsx_le_f64"; // "v_cmpsx_le_f64_e32"
14043 0 : return;
14044 : case '6': // 1 string to match.
14045 0 : if (Mnemonic[17] != '4')
14046 : break;
14047 0 : Mnemonic = "v_cmpsx_le_f64"; // "v_cmpsx_le_f64_e64"
14048 0 : return;
14049 : }
14050 : break;
14051 : }
14052 : break;
14053 : case 'g': // 4 strings to match.
14054 0 : if (memcmp(Mnemonic.data()+10, "_f", 2))
14055 : break;
14056 0 : switch (Mnemonic[12]) {
14057 : default: break;
14058 : case '3': // 2 strings to match.
14059 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
14060 : break;
14061 0 : switch (Mnemonic[16]) {
14062 : default: break;
14063 : case '3': // 1 string to match.
14064 0 : if (Mnemonic[17] != '2')
14065 : break;
14066 0 : Mnemonic = "v_cmpsx_lg_f32"; // "v_cmpsx_lg_f32_e32"
14067 0 : return;
14068 : case '6': // 1 string to match.
14069 0 : if (Mnemonic[17] != '4')
14070 : break;
14071 0 : Mnemonic = "v_cmpsx_lg_f32"; // "v_cmpsx_lg_f32_e64"
14072 0 : return;
14073 : }
14074 : break;
14075 : case '6': // 2 strings to match.
14076 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
14077 : break;
14078 0 : switch (Mnemonic[16]) {
14079 : default: break;
14080 : case '3': // 1 string to match.
14081 0 : if (Mnemonic[17] != '2')
14082 : break;
14083 0 : Mnemonic = "v_cmpsx_lg_f64"; // "v_cmpsx_lg_f64_e32"
14084 0 : return;
14085 : case '6': // 1 string to match.
14086 0 : if (Mnemonic[17] != '4')
14087 : break;
14088 0 : Mnemonic = "v_cmpsx_lg_f64"; // "v_cmpsx_lg_f64_e64"
14089 0 : return;
14090 : }
14091 : break;
14092 : }
14093 : break;
14094 : case 't': // 4 strings to match.
14095 0 : if (memcmp(Mnemonic.data()+10, "_f", 2))
14096 : break;
14097 0 : switch (Mnemonic[12]) {
14098 : default: break;
14099 : case '3': // 2 strings to match.
14100 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
14101 : break;
14102 0 : switch (Mnemonic[16]) {
14103 : default: break;
14104 : case '3': // 1 string to match.
14105 0 : if (Mnemonic[17] != '2')
14106 : break;
14107 0 : Mnemonic = "v_cmpsx_lt_f32"; // "v_cmpsx_lt_f32_e32"
14108 0 : return;
14109 : case '6': // 1 string to match.
14110 0 : if (Mnemonic[17] != '4')
14111 : break;
14112 0 : Mnemonic = "v_cmpsx_lt_f32"; // "v_cmpsx_lt_f32_e64"
14113 0 : return;
14114 : }
14115 : break;
14116 : case '6': // 2 strings to match.
14117 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
14118 : break;
14119 0 : switch (Mnemonic[16]) {
14120 : default: break;
14121 : case '3': // 1 string to match.
14122 0 : if (Mnemonic[17] != '2')
14123 : break;
14124 0 : Mnemonic = "v_cmpsx_lt_f64"; // "v_cmpsx_lt_f64_e32"
14125 0 : return;
14126 : case '6': // 1 string to match.
14127 0 : if (Mnemonic[17] != '4')
14128 : break;
14129 0 : Mnemonic = "v_cmpsx_lt_f64"; // "v_cmpsx_lt_f64_e64"
14130 0 : return;
14131 : }
14132 : break;
14133 : }
14134 : break;
14135 : }
14136 : break;
14137 : }
14138 : break;
14139 : }
14140 : break;
14141 : case 'x': // 28 strings to match.
14142 0 : if (Mnemonic[6] != '_')
14143 : break;
14144 0 : switch (Mnemonic[7]) {
14145 : default: break;
14146 : case 'n': // 24 strings to match.
14147 0 : switch (Mnemonic[8]) {
14148 : default: break;
14149 : case 'e': // 4 strings to match.
14150 0 : if (memcmp(Mnemonic.data()+9, "q_f", 3))
14151 : break;
14152 0 : switch (Mnemonic[12]) {
14153 : default: break;
14154 : case '3': // 2 strings to match.
14155 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
14156 : break;
14157 0 : switch (Mnemonic[16]) {
14158 : default: break;
14159 : case '3': // 1 string to match.
14160 0 : if (Mnemonic[17] != '2')
14161 : break;
14162 0 : Mnemonic = "v_cmpx_neq_f32"; // "v_cmpx_neq_f32_e32"
14163 0 : return;
14164 : case '6': // 1 string to match.
14165 0 : if (Mnemonic[17] != '4')
14166 : break;
14167 0 : Mnemonic = "v_cmpx_neq_f32"; // "v_cmpx_neq_f32_e64"
14168 0 : return;
14169 : }
14170 : break;
14171 : case '6': // 2 strings to match.
14172 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
14173 : break;
14174 0 : switch (Mnemonic[16]) {
14175 : default: break;
14176 : case '3': // 1 string to match.
14177 0 : if (Mnemonic[17] != '2')
14178 : break;
14179 0 : Mnemonic = "v_cmpx_neq_f64"; // "v_cmpx_neq_f64_e32"
14180 0 : return;
14181 : case '6': // 1 string to match.
14182 0 : if (Mnemonic[17] != '4')
14183 : break;
14184 0 : Mnemonic = "v_cmpx_neq_f64"; // "v_cmpx_neq_f64_e64"
14185 0 : return;
14186 : }
14187 : break;
14188 : }
14189 : break;
14190 : case 'g': // 8 strings to match.
14191 0 : switch (Mnemonic[9]) {
14192 : default: break;
14193 : case 'e': // 4 strings to match.
14194 0 : if (memcmp(Mnemonic.data()+10, "_f", 2))
14195 : break;
14196 0 : switch (Mnemonic[12]) {
14197 : default: break;
14198 : case '3': // 2 strings to match.
14199 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
14200 : break;
14201 0 : switch (Mnemonic[16]) {
14202 : default: break;
14203 : case '3': // 1 string to match.
14204 0 : if (Mnemonic[17] != '2')
14205 : break;
14206 0 : Mnemonic = "v_cmpx_nge_f32"; // "v_cmpx_nge_f32_e32"
14207 0 : return;
14208 : case '6': // 1 string to match.
14209 0 : if (Mnemonic[17] != '4')
14210 : break;
14211 0 : Mnemonic = "v_cmpx_nge_f32"; // "v_cmpx_nge_f32_e64"
14212 0 : return;
14213 : }
14214 : break;
14215 : case '6': // 2 strings to match.
14216 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
14217 : break;
14218 0 : switch (Mnemonic[16]) {
14219 : default: break;
14220 : case '3': // 1 string to match.
14221 0 : if (Mnemonic[17] != '2')
14222 : break;
14223 0 : Mnemonic = "v_cmpx_nge_f64"; // "v_cmpx_nge_f64_e32"
14224 0 : return;
14225 : case '6': // 1 string to match.
14226 0 : if (Mnemonic[17] != '4')
14227 : break;
14228 0 : Mnemonic = "v_cmpx_nge_f64"; // "v_cmpx_nge_f64_e64"
14229 0 : return;
14230 : }
14231 : break;
14232 : }
14233 : break;
14234 : case 't': // 4 strings to match.
14235 0 : if (memcmp(Mnemonic.data()+10, "_f", 2))
14236 : break;
14237 0 : switch (Mnemonic[12]) {
14238 : default: break;
14239 : case '3': // 2 strings to match.
14240 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
14241 : break;
14242 0 : switch (Mnemonic[16]) {
14243 : default: break;
14244 : case '3': // 1 string to match.
14245 0 : if (Mnemonic[17] != '2')
14246 : break;
14247 0 : Mnemonic = "v_cmpx_ngt_f32"; // "v_cmpx_ngt_f32_e32"
14248 0 : return;
14249 : case '6': // 1 string to match.
14250 0 : if (Mnemonic[17] != '4')
14251 : break;
14252 0 : Mnemonic = "v_cmpx_ngt_f32"; // "v_cmpx_ngt_f32_e64"
14253 0 : return;
14254 : }
14255 : break;
14256 : case '6': // 2 strings to match.
14257 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
14258 : break;
14259 0 : switch (Mnemonic[16]) {
14260 : default: break;
14261 : case '3': // 1 string to match.
14262 0 : if (Mnemonic[17] != '2')
14263 : break;
14264 0 : Mnemonic = "v_cmpx_ngt_f64"; // "v_cmpx_ngt_f64_e32"
14265 0 : return;
14266 : case '6': // 1 string to match.
14267 0 : if (Mnemonic[17] != '4')
14268 : break;
14269 0 : Mnemonic = "v_cmpx_ngt_f64"; // "v_cmpx_ngt_f64_e64"
14270 0 : return;
14271 : }
14272 : break;
14273 : }
14274 : break;
14275 : }
14276 : break;
14277 : case 'l': // 12 strings to match.
14278 0 : switch (Mnemonic[9]) {
14279 : default: break;
14280 : case 'e': // 4 strings to match.
14281 0 : if (memcmp(Mnemonic.data()+10, "_f", 2))
14282 : break;
14283 0 : switch (Mnemonic[12]) {
14284 : default: break;
14285 : case '3': // 2 strings to match.
14286 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
14287 : break;
14288 0 : switch (Mnemonic[16]) {
14289 : default: break;
14290 : case '3': // 1 string to match.
14291 0 : if (Mnemonic[17] != '2')
14292 : break;
14293 0 : Mnemonic = "v_cmpx_nle_f32"; // "v_cmpx_nle_f32_e32"
14294 0 : return;
14295 : case '6': // 1 string to match.
14296 0 : if (Mnemonic[17] != '4')
14297 : break;
14298 0 : Mnemonic = "v_cmpx_nle_f32"; // "v_cmpx_nle_f32_e64"
14299 0 : return;
14300 : }
14301 : break;
14302 : case '6': // 2 strings to match.
14303 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
14304 : break;
14305 0 : switch (Mnemonic[16]) {
14306 : default: break;
14307 : case '3': // 1 string to match.
14308 0 : if (Mnemonic[17] != '2')
14309 : break;
14310 0 : Mnemonic = "v_cmpx_nle_f64"; // "v_cmpx_nle_f64_e32"
14311 0 : return;
14312 : case '6': // 1 string to match.
14313 0 : if (Mnemonic[17] != '4')
14314 : break;
14315 0 : Mnemonic = "v_cmpx_nle_f64"; // "v_cmpx_nle_f64_e64"
14316 0 : return;
14317 : }
14318 : break;
14319 : }
14320 : break;
14321 : case 'g': // 4 strings to match.
14322 0 : if (memcmp(Mnemonic.data()+10, "_f", 2))
14323 : break;
14324 0 : switch (Mnemonic[12]) {
14325 : default: break;
14326 : case '3': // 2 strings to match.
14327 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
14328 : break;
14329 0 : switch (Mnemonic[16]) {
14330 : default: break;
14331 : case '3': // 1 string to match.
14332 0 : if (Mnemonic[17] != '2')
14333 : break;
14334 0 : Mnemonic = "v_cmpx_nlg_f32"; // "v_cmpx_nlg_f32_e32"
14335 0 : return;
14336 : case '6': // 1 string to match.
14337 0 : if (Mnemonic[17] != '4')
14338 : break;
14339 0 : Mnemonic = "v_cmpx_nlg_f32"; // "v_cmpx_nlg_f32_e64"
14340 0 : return;
14341 : }
14342 : break;
14343 : case '6': // 2 strings to match.
14344 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
14345 : break;
14346 0 : switch (Mnemonic[16]) {
14347 : default: break;
14348 : case '3': // 1 string to match.
14349 0 : if (Mnemonic[17] != '2')
14350 : break;
14351 0 : Mnemonic = "v_cmpx_nlg_f64"; // "v_cmpx_nlg_f64_e32"
14352 0 : return;
14353 : case '6': // 1 string to match.
14354 0 : if (Mnemonic[17] != '4')
14355 : break;
14356 0 : Mnemonic = "v_cmpx_nlg_f64"; // "v_cmpx_nlg_f64_e64"
14357 0 : return;
14358 : }
14359 : break;
14360 : }
14361 : break;
14362 : case 't': // 4 strings to match.
14363 0 : if (memcmp(Mnemonic.data()+10, "_f", 2))
14364 : break;
14365 0 : switch (Mnemonic[12]) {
14366 : default: break;
14367 : case '3': // 2 strings to match.
14368 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
14369 : break;
14370 0 : switch (Mnemonic[16]) {
14371 : default: break;
14372 : case '3': // 1 string to match.
14373 0 : if (Mnemonic[17] != '2')
14374 : break;
14375 0 : Mnemonic = "v_cmpx_nlt_f32"; // "v_cmpx_nlt_f32_e32"
14376 0 : return;
14377 : case '6': // 1 string to match.
14378 0 : if (Mnemonic[17] != '4')
14379 : break;
14380 0 : Mnemonic = "v_cmpx_nlt_f32"; // "v_cmpx_nlt_f32_e64"
14381 0 : return;
14382 : }
14383 : break;
14384 : case '6': // 2 strings to match.
14385 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
14386 : break;
14387 0 : switch (Mnemonic[16]) {
14388 : default: break;
14389 : case '3': // 1 string to match.
14390 0 : if (Mnemonic[17] != '2')
14391 : break;
14392 0 : Mnemonic = "v_cmpx_nlt_f64"; // "v_cmpx_nlt_f64_e32"
14393 0 : return;
14394 : case '6': // 1 string to match.
14395 0 : if (Mnemonic[17] != '4')
14396 : break;
14397 0 : Mnemonic = "v_cmpx_nlt_f64"; // "v_cmpx_nlt_f64_e64"
14398 0 : return;
14399 : }
14400 : break;
14401 : }
14402 : break;
14403 : }
14404 : break;
14405 : }
14406 : break;
14407 : case 't': // 4 strings to match.
14408 0 : if (memcmp(Mnemonic.data()+8, "ru_f", 4))
14409 : break;
14410 0 : switch (Mnemonic[12]) {
14411 : default: break;
14412 : case '3': // 2 strings to match.
14413 0 : if (memcmp(Mnemonic.data()+13, "2_e", 3))
14414 : break;
14415 0 : switch (Mnemonic[16]) {
14416 : default: break;
14417 : case '3': // 1 string to match.
14418 0 : if (Mnemonic[17] != '2')
14419 : break;
14420 0 : Mnemonic = "v_cmpx_tru_f32"; // "v_cmpx_tru_f32_e32"
14421 0 : return;
14422 : case '6': // 1 string to match.
14423 0 : if (Mnemonic[17] != '4')
14424 : break;
14425 0 : Mnemonic = "v_cmpx_tru_f32"; // "v_cmpx_tru_f32_e64"
14426 0 : return;
14427 : }
14428 : break;
14429 : case '6': // 2 strings to match.
14430 0 : if (memcmp(Mnemonic.data()+13, "4_e", 3))
14431 : break;
14432 0 : switch (Mnemonic[16]) {
14433 : default: break;
14434 : case '3': // 1 string to match.
14435 0 : if (Mnemonic[17] != '2')
14436 : break;
14437 0 : Mnemonic = "v_cmpx_tru_f64"; // "v_cmpx_tru_f64_e32"
14438 0 : return;
14439 : case '6': // 1 string to match.
14440 0 : if (Mnemonic[17] != '4')
14441 : break;
14442 0 : Mnemonic = "v_cmpx_tru_f64"; // "v_cmpx_tru_f64_e64"
14443 0 : return;
14444 : }
14445 : break;
14446 : }
14447 : break;
14448 : }
14449 : break;
14450 : }
14451 : break;
14452 : case 'd': // 2 strings to match.
14453 0 : if (memcmp(Mnemonic.data()+3, "iv_fmas_f", 9))
14454 : break;
14455 0 : switch (Mnemonic[12]) {
14456 : default: break;
14457 : case '3': // 1 string to match.
14458 0 : if (memcmp(Mnemonic.data()+13, "2_e64", 5))
14459 : break;
14460 0 : Mnemonic = "v_div_fmas_f32"; // "v_div_fmas_f32_e64"
14461 0 : return;
14462 : case '6': // 1 string to match.
14463 0 : if (memcmp(Mnemonic.data()+13, "4_e64", 5))
14464 : break;
14465 0 : Mnemonic = "v_div_fmas_f64"; // "v_div_fmas_f64_e64"
14466 0 : return;
14467 : }
14468 : break;
14469 : case 'm': // 4 strings to match.
14470 32 : switch (Mnemonic[3]) {
14471 : default: break;
14472 : case 'o': // 2 strings to match.
14473 0 : if (memcmp(Mnemonic.data()+4, "vrelsd_b32_e", 12))
14474 : break;
14475 0 : switch (Mnemonic[16]) {
14476 : default: break;
14477 : case '3': // 1 string to match.
14478 0 : if (Mnemonic[17] != '2')
14479 : break;
14480 0 : Mnemonic = "v_movrelsd_b32"; // "v_movrelsd_b32_e32"
14481 0 : return;
14482 : case '6': // 1 string to match.
14483 0 : if (Mnemonic[17] != '4')
14484 : break;
14485 0 : Mnemonic = "v_movrelsd_b32"; // "v_movrelsd_b32_e64"
14486 0 : return;
14487 : }
14488 : break;
14489 : case 'q': // 2 strings to match.
14490 0 : if (memcmp(Mnemonic.data()+4, "sad_u", 5))
14491 : break;
14492 0 : switch (Mnemonic[9]) {
14493 : default: break;
14494 : case '1': // 1 string to match.
14495 0 : if (memcmp(Mnemonic.data()+10, "6_u8_e64", 8))
14496 : break;
14497 0 : if ((Features & Feature_isGCN) == Feature_isGCN) // "v_mqsad_u16_u8_e64"
14498 0 : Mnemonic = "v_mqsad_u16_u8";
14499 : return;
14500 : case '3': // 1 string to match.
14501 0 : if (memcmp(Mnemonic.data()+10, "2_u8_e64", 8))
14502 : break;
14503 0 : if ((Features & Feature_isGCN) == Feature_isGCN) // "v_mqsad_u32_u8_e64"
14504 0 : Mnemonic = "v_mqsad_u32_u8";
14505 : return;
14506 : }
14507 : break;
14508 : }
14509 : break;
14510 : }
14511 : break;
14512 : case 19: // 49 strings to match.
14513 50 : if (memcmp(Mnemonic.data()+0, "v_", 2))
14514 : break;
14515 80 : switch (Mnemonic[2]) {
14516 : default: break;
14517 : case 'a': // 1 string to match.
14518 0 : if (memcmp(Mnemonic.data()+3, "lignbyte_b32_e64", 16))
14519 : break;
14520 0 : Mnemonic = "v_alignbyte_b32"; // "v_alignbyte_b32_e64"
14521 0 : return;
14522 : case 'c': // 32 strings to match.
14523 8 : if (memcmp(Mnemonic.data()+3, "mp", 2))
14524 : break;
14525 0 : switch (Mnemonic[5]) {
14526 : default: break;
14527 : case '_': // 4 strings to match.
14528 0 : if (memcmp(Mnemonic.data()+6, "class_f", 7))
14529 : break;
14530 0 : switch (Mnemonic[13]) {
14531 : default: break;
14532 : case '3': // 2 strings to match.
14533 0 : if (memcmp(Mnemonic.data()+14, "2_e", 3))
14534 : break;
14535 0 : switch (Mnemonic[17]) {
14536 : default: break;
14537 : case '3': // 1 string to match.
14538 0 : if (Mnemonic[18] != '2')
14539 : break;
14540 0 : Mnemonic = "v_cmp_class_f32"; // "v_cmp_class_f32_e32"
14541 0 : return;
14542 : case '6': // 1 string to match.
14543 0 : if (Mnemonic[18] != '4')
14544 : break;
14545 0 : Mnemonic = "v_cmp_class_f32"; // "v_cmp_class_f32_e64"
14546 0 : return;
14547 : }
14548 : break;
14549 : case '6': // 2 strings to match.
14550 0 : if (memcmp(Mnemonic.data()+14, "4_e", 3))
14551 : break;
14552 0 : switch (Mnemonic[17]) {
14553 : default: break;
14554 : case '3': // 1 string to match.
14555 0 : if (Mnemonic[18] != '2')
14556 : break;
14557 0 : Mnemonic = "v_cmp_class_f64"; // "v_cmp_class_f64_e32"
14558 0 : return;
14559 : case '6': // 1 string to match.
14560 0 : if (Mnemonic[18] != '4')
14561 : break;
14562 0 : Mnemonic = "v_cmp_class_f64"; // "v_cmp_class_f64_e64"
14563 0 : return;
14564 : }
14565 : break;
14566 : }
14567 : break;
14568 : case 's': // 28 strings to match.
14569 0 : if (memcmp(Mnemonic.data()+6, "x_", 2))
14570 : break;
14571 0 : switch (Mnemonic[8]) {
14572 : default: break;
14573 : case 'n': // 24 strings to match.
14574 0 : switch (Mnemonic[9]) {
14575 : default: break;
14576 : case 'e': // 4 strings to match.
14577 0 : if (memcmp(Mnemonic.data()+10, "q_f", 3))
14578 : break;
14579 0 : switch (Mnemonic[13]) {
14580 : default: break;
14581 : case '3': // 2 strings to match.
14582 0 : if (memcmp(Mnemonic.data()+14, "2_e", 3))
14583 : break;
14584 0 : switch (Mnemonic[17]) {
14585 : default: break;
14586 : case '3': // 1 string to match.
14587 0 : if (Mnemonic[18] != '2')
14588 : break;
14589 0 : Mnemonic = "v_cmpsx_neq_f32"; // "v_cmpsx_neq_f32_e32"
14590 0 : return;
14591 : case '6': // 1 string to match.
14592 0 : if (Mnemonic[18] != '4')
14593 : break;
14594 0 : Mnemonic = "v_cmpsx_neq_f32"; // "v_cmpsx_neq_f32_e64"
14595 0 : return;
14596 : }
14597 : break;
14598 : case '6': // 2 strings to match.
14599 0 : if (memcmp(Mnemonic.data()+14, "4_e", 3))
14600 : break;
14601 0 : switch (Mnemonic[17]) {
14602 : default: break;
14603 : case '3': // 1 string to match.
14604 0 : if (Mnemonic[18] != '2')
14605 : break;
14606 0 : Mnemonic = "v_cmpsx_neq_f64"; // "v_cmpsx_neq_f64_e32"
14607 0 : return;
14608 : case '6': // 1 string to match.
14609 0 : if (Mnemonic[18] != '4')
14610 : break;
14611 0 : Mnemonic = "v_cmpsx_neq_f64"; // "v_cmpsx_neq_f64_e64"
14612 0 : return;
14613 : }
14614 : break;
14615 : }
14616 : break;
14617 : case 'g': // 8 strings to match.
14618 0 : switch (Mnemonic[10]) {
14619 : default: break;
14620 : case 'e': // 4 strings to match.
14621 0 : if (memcmp(Mnemonic.data()+11, "_f", 2))
14622 : break;
14623 0 : switch (Mnemonic[13]) {
14624 : default: break;
14625 : case '3': // 2 strings to match.
14626 0 : if (memcmp(Mnemonic.data()+14, "2_e", 3))
14627 : break;
14628 0 : switch (Mnemonic[17]) {
14629 : default: break;
14630 : case '3': // 1 string to match.
14631 0 : if (Mnemonic[18] != '2')
14632 : break;
14633 0 : Mnemonic = "v_cmpsx_nge_f32"; // "v_cmpsx_nge_f32_e32"
14634 0 : return;
14635 : case '6': // 1 string to match.
14636 0 : if (Mnemonic[18] != '4')
14637 : break;
14638 0 : Mnemonic = "v_cmpsx_nge_f32"; // "v_cmpsx_nge_f32_e64"
14639 0 : return;
14640 : }
14641 : break;
14642 : case '6': // 2 strings to match.
14643 0 : if (memcmp(Mnemonic.data()+14, "4_e", 3))
14644 : break;
14645 0 : switch (Mnemonic[17]) {
14646 : default: break;
14647 : case '3': // 1 string to match.
14648 0 : if (Mnemonic[18] != '2')
14649 : break;
14650 0 : Mnemonic = "v_cmpsx_nge_f64"; // "v_cmpsx_nge_f64_e32"
14651 0 : return;
14652 : case '6': // 1 string to match.
14653 0 : if (Mnemonic[18] != '4')
14654 : break;
14655 0 : Mnemonic = "v_cmpsx_nge_f64"; // "v_cmpsx_nge_f64_e64"
14656 0 : return;
14657 : }
14658 : break;
14659 : }
14660 : break;
14661 : case 't': // 4 strings to match.
14662 0 : if (memcmp(Mnemonic.data()+11, "_f", 2))
14663 : break;
14664 0 : switch (Mnemonic[13]) {
14665 : default: break;
14666 : case '3': // 2 strings to match.
14667 0 : if (memcmp(Mnemonic.data()+14, "2_e", 3))
14668 : break;
14669 0 : switch (Mnemonic[17]) {
14670 : default: break;
14671 : case '3': // 1 string to match.
14672 0 : if (Mnemonic[18] != '2')
14673 : break;
14674 0 : Mnemonic = "v_cmpsx_ngt_f32"; // "v_cmpsx_ngt_f32_e32"
14675 0 : return;
14676 : case '6': // 1 string to match.
14677 0 : if (Mnemonic[18] != '4')
14678 : break;
14679 0 : Mnemonic = "v_cmpsx_ngt_f32"; // "v_cmpsx_ngt_f32_e64"
14680 0 : return;
14681 : }
14682 : break;
14683 : case '6': // 2 strings to match.
14684 0 : if (memcmp(Mnemonic.data()+14, "4_e", 3))
14685 : break;
14686 0 : switch (Mnemonic[17]) {
14687 : default: break;
14688 : case '3': // 1 string to match.
14689 0 : if (Mnemonic[18] != '2')
14690 : break;
14691 0 : Mnemonic = "v_cmpsx_ngt_f64"; // "v_cmpsx_ngt_f64_e32"
14692 0 : return;
14693 : case '6': // 1 string to match.
14694 0 : if (Mnemonic[18] != '4')
14695 : break;
14696 0 : Mnemonic = "v_cmpsx_ngt_f64"; // "v_cmpsx_ngt_f64_e64"
14697 0 : return;
14698 : }
14699 : break;
14700 : }
14701 : break;
14702 : }
14703 : break;
14704 : case 'l': // 12 strings to match.
14705 0 : switch (Mnemonic[10]) {
14706 : default: break;
14707 : case 'e': // 4 strings to match.
14708 0 : if (memcmp(Mnemonic.data()+11, "_f", 2))
14709 : break;
14710 0 : switch (Mnemonic[13]) {
14711 : default: break;
14712 : case '3': // 2 strings to match.
14713 0 : if (memcmp(Mnemonic.data()+14, "2_e", 3))
14714 : break;
14715 0 : switch (Mnemonic[17]) {
14716 : default: break;
14717 : case '3': // 1 string to match.
14718 0 : if (Mnemonic[18] != '2')
14719 : break;
14720 0 : Mnemonic = "v_cmpsx_nle_f32"; // "v_cmpsx_nle_f32_e32"
14721 0 : return;
14722 : case '6': // 1 string to match.
14723 0 : if (Mnemonic[18] != '4')
14724 : break;
14725 0 : Mnemonic = "v_cmpsx_nle_f32"; // "v_cmpsx_nle_f32_e64"
14726 0 : return;
14727 : }
14728 : break;
14729 : case '6': // 2 strings to match.
14730 0 : if (memcmp(Mnemonic.data()+14, "4_e", 3))
14731 : break;
14732 0 : switch (Mnemonic[17]) {
14733 : default: break;
14734 : case '3': // 1 string to match.
14735 0 : if (Mnemonic[18] != '2')
14736 : break;
14737 0 : Mnemonic = "v_cmpsx_nle_f64"; // "v_cmpsx_nle_f64_e32"
14738 0 : return;
14739 : case '6': // 1 string to match.
14740 0 : if (Mnemonic[18] != '4')
14741 : break;
14742 0 : Mnemonic = "v_cmpsx_nle_f64"; // "v_cmpsx_nle_f64_e64"
14743 0 : return;
14744 : }
14745 : break;
14746 : }
14747 : break;
14748 : case 'g': // 4 strings to match.
14749 0 : if (memcmp(Mnemonic.data()+11, "_f", 2))
14750 : break;
14751 0 : switch (Mnemonic[13]) {
14752 : default: break;
14753 : case '3': // 2 strings to match.
14754 0 : if (memcmp(Mnemonic.data()+14, "2_e", 3))
14755 : break;
14756 0 : switch (Mnemonic[17]) {
14757 : default: break;
14758 : case '3': // 1 string to match.
14759 0 : if (Mnemonic[18] != '2')
14760 : break;
14761 0 : Mnemonic = "v_cmpsx_nlg_f32"; // "v_cmpsx_nlg_f32_e32"
14762 0 : return;
14763 : case '6': // 1 string to match.
14764 0 : if (Mnemonic[18] != '4')
14765 : break;
14766 0 : Mnemonic = "v_cmpsx_nlg_f32"; // "v_cmpsx_nlg_f32_e64"
14767 0 : return;
14768 : }
14769 : break;
14770 : case '6': // 2 strings to match.
14771 0 : if (memcmp(Mnemonic.data()+14, "4_e", 3))
14772 : break;
14773 0 : switch (Mnemonic[17]) {
14774 : default: break;
14775 : case '3': // 1 string to match.
14776 0 : if (Mnemonic[18] != '2')
14777 : break;
14778 0 : Mnemonic = "v_cmpsx_nlg_f64"; // "v_cmpsx_nlg_f64_e32"
14779 0 : return;
14780 : case '6': // 1 string to match.
14781 0 : if (Mnemonic[18] != '4')
14782 : break;
14783 0 : Mnemonic = "v_cmpsx_nlg_f64"; // "v_cmpsx_nlg_f64_e64"
14784 0 : return;
14785 : }
14786 : break;
14787 : }
14788 : break;
14789 : case 't': // 4 strings to match.
14790 0 : if (memcmp(Mnemonic.data()+11, "_f", 2))
14791 : break;
14792 0 : switch (Mnemonic[13]) {
14793 : default: break;
14794 : case '3': // 2 strings to match.
14795 0 : if (memcmp(Mnemonic.data()+14, "2_e", 3))
14796 : break;
14797 0 : switch (Mnemonic[17]) {
14798 : default: break;
14799 : case '3': // 1 string to match.
14800 0 : if (Mnemonic[18] != '2')
14801 : break;
14802 0 : Mnemonic = "v_cmpsx_nlt_f32"; // "v_cmpsx_nlt_f32_e32"
14803 0 : return;
14804 : case '6': // 1 string to match.
14805 0 : if (Mnemonic[18] != '4')
14806 : break;
14807 0 : Mnemonic = "v_cmpsx_nlt_f32"; // "v_cmpsx_nlt_f32_e64"
14808 0 : return;
14809 : }
14810 : break;
14811 : case '6': // 2 strings to match.
14812 0 : if (memcmp(Mnemonic.data()+14, "4_e", 3))
14813 : break;
14814 0 : switch (Mnemonic[17]) {
14815 : default: break;
14816 : case '3': // 1 string to match.
14817 0 : if (Mnemonic[18] != '2')
14818 : break;
14819 0 : Mnemonic = "v_cmpsx_nlt_f64"; // "v_cmpsx_nlt_f64_e32"
14820 0 : return;
14821 : case '6': // 1 string to match.
14822 0 : if (Mnemonic[18] != '4')
14823 : break;
14824 0 : Mnemonic = "v_cmpsx_nlt_f64"; // "v_cmpsx_nlt_f64_e64"
14825 0 : return;
14826 : }
14827 : break;
14828 : }
14829 : break;
14830 : }
14831 : break;
14832 : }
14833 : break;
14834 : case 't': // 4 strings to match.
14835 0 : if (memcmp(Mnemonic.data()+9, "ru_f", 4))
14836 : break;
14837 0 : switch (Mnemonic[13]) {
14838 : default: break;
14839 : case '3': // 2 strings to match.
14840 0 : if (memcmp(Mnemonic.data()+14, "2_e", 3))
14841 : break;
14842 0 : switch (Mnemonic[17]) {
14843 : default: break;
14844 : case '3': // 1 string to match.
14845 0 : if (Mnemonic[18] != '2')
14846 : break;
14847 0 : Mnemonic = "v_cmpsx_tru_f32"; // "v_cmpsx_tru_f32_e32"
14848 0 : return;
14849 : case '6': // 1 string to match.
14850 0 : if (Mnemonic[18] != '4')
14851 : break;
14852 0 : Mnemonic = "v_cmpsx_tru_f32"; // "v_cmpsx_tru_f32_e64"
14853 0 : return;
14854 : }
14855 : break;
14856 : case '6': // 2 strings to match.
14857 0 : if (memcmp(Mnemonic.data()+14, "4_e", 3))
14858 : break;
14859 0 : switch (Mnemonic[17]) {
14860 : default: break;
14861 : case '3': // 1 string to match.
14862 0 : if (Mnemonic[18] != '2')
14863 : break;
14864 0 : Mnemonic = "v_cmpsx_tru_f64"; // "v_cmpsx_tru_f64_e32"
14865 0 : return;
14866 : case '6': // 1 string to match.
14867 0 : if (Mnemonic[18] != '4')
14868 : break;
14869 0 : Mnemonic = "v_cmpsx_tru_f64"; // "v_cmpsx_tru_f64_e64"
14870 0 : return;
14871 : }
14872 : break;
14873 : }
14874 : break;
14875 : }
14876 : break;
14877 : }
14878 : break;
14879 : case 'd': // 4 strings to match.
14880 0 : if (memcmp(Mnemonic.data()+3, "iv_", 3))
14881 : break;
14882 0 : switch (Mnemonic[6]) {
14883 : default: break;
14884 : case 'f': // 2 strings to match.
14885 0 : if (memcmp(Mnemonic.data()+7, "ixup_f", 6))
14886 : break;
14887 0 : switch (Mnemonic[13]) {
14888 : default: break;
14889 : case '3': // 1 string to match.
14890 0 : if (memcmp(Mnemonic.data()+14, "2_e64", 5))
14891 : break;
14892 0 : Mnemonic = "v_div_fixup_f32"; // "v_div_fixup_f32_e64"
14893 0 : return;
14894 : case '6': // 1 string to match.
14895 0 : if (memcmp(Mnemonic.data()+14, "4_e64", 5))
14896 : break;
14897 0 : Mnemonic = "v_div_fixup_f64"; // "v_div_fixup_f64_e64"
14898 0 : return;
14899 : }
14900 : break;
14901 : case 's': // 2 strings to match.
14902 0 : if (memcmp(Mnemonic.data()+7, "cale_f", 6))
14903 : break;
14904 0 : switch (Mnemonic[13]) {
14905 : default: break;
14906 : case '3': // 1 string to match.
14907 0 : if (memcmp(Mnemonic.data()+14, "2_e64", 5))
14908 : break;
14909 0 : Mnemonic = "v_div_scale_f32"; // "v_div_scale_f32_e64"
14910 0 : return;
14911 : case '6': // 1 string to match.
14912 0 : if (memcmp(Mnemonic.data()+14, "4_e64", 5))
14913 : break;
14914 0 : Mnemonic = "v_div_scale_f64"; // "v_div_scale_f64_e64"
14915 0 : return;
14916 : }
14917 : break;
14918 : }
14919 : break;
14920 : case 'l': // 2 strings to match.
14921 0 : if (memcmp(Mnemonic.data()+3, "og_clamp_f32_e", 14))
14922 : break;
14923 0 : switch (Mnemonic[17]) {
14924 : default: break;
14925 : case '3': // 1 string to match.
14926 0 : if (Mnemonic[18] != '2')
14927 : break;
14928 0 : Mnemonic = "v_log_clamp_f32"; // "v_log_clamp_f32_e32"
14929 0 : return;
14930 : case '6': // 1 string to match.
14931 0 : if (Mnemonic[18] != '4')
14932 : break;
14933 0 : Mnemonic = "v_log_clamp_f32"; // "v_log_clamp_f32_e64"
14934 0 : return;
14935 : }
14936 : break;
14937 : case 'r': // 10 strings to match.
14938 16 : switch (Mnemonic[3]) {
14939 : default: break;
14940 : case 'c': // 6 strings to match.
14941 0 : if (memcmp(Mnemonic.data()+4, "p_", 2))
14942 : break;
14943 0 : switch (Mnemonic[6]) {
14944 : default: break;
14945 : case 'c': // 4 strings to match.
14946 0 : if (memcmp(Mnemonic.data()+7, "lamp_f", 6))
14947 : break;
14948 0 : switch (Mnemonic[13]) {
14949 : default: break;
14950 : case '3': // 2 strings to match.
14951 0 : if (memcmp(Mnemonic.data()+14, "2_e", 3))
14952 : break;
14953 0 : switch (Mnemonic[17]) {
14954 : default: break;
14955 : case '3': // 1 string to match.
14956 0 : if (Mnemonic[18] != '2')
14957 : break;
14958 0 : Mnemonic = "v_rcp_clamp_f32"; // "v_rcp_clamp_f32_e32"
14959 0 : return;
14960 : case '6': // 1 string to match.
14961 0 : if (Mnemonic[18] != '4')
14962 : break;
14963 0 : Mnemonic = "v_rcp_clamp_f32"; // "v_rcp_clamp_f32_e64"
14964 0 : return;
14965 : }
14966 : break;
14967 : case '6': // 2 strings to match.
14968 0 : if (memcmp(Mnemonic.data()+14, "4_e", 3))
14969 : break;
14970 0 : switch (Mnemonic[17]) {
14971 : default: break;
14972 : case '3': // 1 string to match.
14973 0 : if (Mnemonic[18] != '2')
14974 : break;
14975 0 : Mnemonic = "v_rcp_clamp_f64"; // "v_rcp_clamp_f64_e32"
14976 0 : return;
14977 : case '6': // 1 string to match.
14978 0 : if (Mnemonic[18] != '4')
14979 : break;
14980 0 : Mnemonic = "v_rcp_clamp_f64"; // "v_rcp_clamp_f64_e64"
14981 0 : return;
14982 : }
14983 : break;
14984 : }
14985 : break;
14986 : case 'i': // 2 strings to match.
14987 0 : if (memcmp(Mnemonic.data()+7, "flag_f32_e", 10))
14988 : break;
14989 0 : switch (Mnemonic[17]) {
14990 : default: break;
14991 : case '3': // 1 string to match.
14992 0 : if (Mnemonic[18] != '2')
14993 : break;
14994 0 : Mnemonic = "v_rcp_iflag_f32"; // "v_rcp_iflag_f32_e32"
14995 0 : return;
14996 : case '6': // 1 string to match.
14997 0 : if (Mnemonic[18] != '4')
14998 : break;
14999 0 : Mnemonic = "v_rcp_iflag_f32"; // "v_rcp_iflag_f32_e64"
15000 0 : return;
15001 : }
15002 : break;
15003 : }
15004 : break;
15005 : case 's': // 4 strings to match.
15006 0 : if (memcmp(Mnemonic.data()+4, "q_clamp_f", 9))
15007 : break;
15008 0 : switch (Mnemonic[13]) {
15009 : default: break;
15010 : case '3': // 2 strings to match.
15011 0 : if (memcmp(Mnemonic.data()+14, "2_e", 3))
15012 : break;
15013 0 : switch (Mnemonic[17]) {
15014 : default: break;
15015 : case '3': // 1 string to match.
15016 0 : if (Mnemonic[18] != '2')
15017 : break;
15018 0 : Mnemonic = "v_rsq_clamp_f32"; // "v_rsq_clamp_f32_e32"
15019 0 : return;
15020 : case '6': // 1 string to match.
15021 0 : if (Mnemonic[18] != '4')
15022 : break;
15023 0 : Mnemonic = "v_rsq_clamp_f32"; // "v_rsq_clamp_f32_e64"
15024 0 : return;
15025 : }
15026 : break;
15027 : case '6': // 2 strings to match.
15028 0 : if (memcmp(Mnemonic.data()+14, "4_e", 3))
15029 : break;
15030 0 : switch (Mnemonic[17]) {
15031 : default: break;
15032 : case '3': // 1 string to match.
15033 0 : if (Mnemonic[18] != '2')
15034 : break;
15035 0 : Mnemonic = "v_rsq_clamp_f64"; // "v_rsq_clamp_f64_e32"
15036 0 : return;
15037 : case '6': // 1 string to match.
15038 0 : if (Mnemonic[18] != '4')
15039 : break;
15040 0 : Mnemonic = "v_rsq_clamp_f64"; // "v_rsq_clamp_f64_e64"
15041 0 : return;
15042 : }
15043 : break;
15044 : }
15045 : break;
15046 : }
15047 : break;
15048 : }
15049 : break;
15050 : case 20: // 47 strings to match.
15051 32 : if (memcmp(Mnemonic.data()+0, "v_", 2))
15052 : break;
15053 48 : switch (Mnemonic[2]) {
15054 : default: break;
15055 : case 'c': // 18 strings to match.
15056 48 : switch (Mnemonic[3]) {
15057 : default: break;
15058 : case 'm': // 4 strings to match.
15059 0 : if (memcmp(Mnemonic.data()+4, "px_class_f", 10))
15060 : break;
15061 0 : switch (Mnemonic[14]) {
15062 : default: break;
15063 : case '3': // 2 strings to match.
15064 0 : if (memcmp(Mnemonic.data()+15, "2_e", 3))
15065 : break;
15066 0 : switch (Mnemonic[18]) {
15067 : default: break;
15068 : case '3': // 1 string to match.
15069 0 : if (Mnemonic[19] != '2')
15070 : break;
15071 0 : Mnemonic = "v_cmpx_class_f32"; // "v_cmpx_class_f32_e32"
15072 0 : return;
15073 : case '6': // 1 string to match.
15074 0 : if (Mnemonic[19] != '4')
15075 : break;
15076 0 : Mnemonic = "v_cmpx_class_f32"; // "v_cmpx_class_f32_e64"
15077 0 : return;
15078 : }
15079 : break;
15080 : case '6': // 2 strings to match.
15081 0 : if (memcmp(Mnemonic.data()+15, "4_e", 3))
15082 : break;
15083 0 : switch (Mnemonic[18]) {
15084 : default: break;
15085 : case '3': // 1 string to match.
15086 0 : if (Mnemonic[19] != '2')
15087 : break;
15088 0 : Mnemonic = "v_cmpx_class_f64"; // "v_cmpx_class_f64_e32"
15089 0 : return;
15090 : case '6': // 1 string to match.
15091 0 : if (Mnemonic[19] != '4')
15092 : break;
15093 0 : Mnemonic = "v_cmpx_class_f64"; // "v_cmpx_class_f64_e64"
15094 0 : return;
15095 : }
15096 : break;
15097 : }
15098 : break;
15099 : case 'v': // 14 strings to match.
15100 24 : if (memcmp(Mnemonic.data()+4, "t_", 2))
15101 : break;
15102 48 : switch (Mnemonic[6]) {
15103 : default: break;
15104 : case 'f': // 8 strings to match.
15105 0 : if (memcmp(Mnemonic.data()+7, "32_ubyte", 8))
15106 : break;
15107 0 : switch (Mnemonic[15]) {
15108 : default: break;
15109 : case '0': // 2 strings to match.
15110 0 : if (memcmp(Mnemonic.data()+16, "_e", 2))
15111 : break;
15112 0 : switch (Mnemonic[18]) {
15113 : default: break;
15114 : case '3': // 1 string to match.
15115 0 : if (Mnemonic[19] != '2')
15116 : break;
15117 0 : Mnemonic = "v_cvt_f32_ubyte0"; // "v_cvt_f32_ubyte0_e32"
15118 0 : return;
15119 : case '6': // 1 string to match.
15120 0 : if (Mnemonic[19] != '4')
15121 : break;
15122 0 : Mnemonic = "v_cvt_f32_ubyte0"; // "v_cvt_f32_ubyte0_e64"
15123 0 : return;
15124 : }
15125 : break;
15126 : case '1': // 2 strings to match.
15127 0 : if (memcmp(Mnemonic.data()+16, "_e", 2))
15128 : break;
15129 0 : switch (Mnemonic[18]) {
15130 : default: break;
15131 : case '3': // 1 string to match.
15132 0 : if (Mnemonic[19] != '2')
15133 : break;
15134 0 : Mnemonic = "v_cvt_f32_ubyte1"; // "v_cvt_f32_ubyte1_e32"
15135 0 : return;
15136 : case '6': // 1 string to match.
15137 0 : if (Mnemonic[19] != '4')
15138 : break;
15139 0 : Mnemonic = "v_cvt_f32_ubyte1"; // "v_cvt_f32_ubyte1_e64"
15140 0 : return;
15141 : }
15142 : break;
15143 : case '2': // 2 strings to match.
15144 0 : if (memcmp(Mnemonic.data()+16, "_e", 2))
15145 : break;
15146 0 : switch (Mnemonic[18]) {
15147 : default: break;
15148 : case '3': // 1 string to match.
15149 0 : if (Mnemonic[19] != '2')
15150 : break;
15151 0 : Mnemonic = "v_cvt_f32_ubyte2"; // "v_cvt_f32_ubyte2_e32"
15152 0 : return;
15153 : case '6': // 1 string to match.
15154 0 : if (Mnemonic[19] != '4')
15155 : break;
15156 0 : Mnemonic = "v_cvt_f32_ubyte2"; // "v_cvt_f32_ubyte2_e64"
15157 0 : return;
15158 : }
15159 : break;
15160 : case '3': // 2 strings to match.
15161 0 : if (memcmp(Mnemonic.data()+16, "_e", 2))
15162 : break;
15163 0 : switch (Mnemonic[18]) {
15164 : default: break;
15165 : case '3': // 1 string to match.
15166 0 : if (Mnemonic[19] != '2')
15167 : break;
15168 0 : Mnemonic = "v_cvt_f32_ubyte3"; // "v_cvt_f32_ubyte3_e32"
15169 0 : return;
15170 : case '6': // 1 string to match.
15171 0 : if (Mnemonic[19] != '4')
15172 : break;
15173 0 : Mnemonic = "v_cvt_f32_ubyte3"; // "v_cvt_f32_ubyte3_e64"
15174 0 : return;
15175 : }
15176 : break;
15177 : }
15178 : break;
15179 : case 'o': // 2 strings to match.
15180 0 : if (memcmp(Mnemonic.data()+7, "ff_f32_i4_e", 11))
15181 : break;
15182 0 : switch (Mnemonic[18]) {
15183 : default: break;
15184 : case '3': // 1 string to match.
15185 0 : if (Mnemonic[19] != '2')
15186 : break;
15187 0 : Mnemonic = "v_cvt_off_f32_i4"; // "v_cvt_off_f32_i4_e32"
15188 0 : return;
15189 : case '6': // 1 string to match.
15190 0 : if (Mnemonic[19] != '4')
15191 : break;
15192 0 : Mnemonic = "v_cvt_off_f32_i4"; // "v_cvt_off_f32_i4_e64"
15193 0 : return;
15194 : }
15195 : break;
15196 : case 'p': // 4 strings to match.
15197 24 : if (memcmp(Mnemonic.data()+7, "k_", 2))
15198 : break;
15199 0 : switch (Mnemonic[9]) {
15200 : default: break;
15201 : case 'i': // 2 strings to match.
15202 0 : if (memcmp(Mnemonic.data()+10, "16_i32_e", 8))
15203 : break;
15204 0 : switch (Mnemonic[18]) {
15205 : default: break;
15206 : case '3': // 1 string to match.
15207 0 : if (Mnemonic[19] != '2')
15208 : break;
15209 0 : Mnemonic = "v_cvt_pk_i16_i32"; // "v_cvt_pk_i16_i32_e32"
15210 0 : return;
15211 : case '6': // 1 string to match.
15212 0 : if (Mnemonic[19] != '4')
15213 : break;
15214 0 : Mnemonic = "v_cvt_pk_i16_i32"; // "v_cvt_pk_i16_i32_e64"
15215 0 : return;
15216 : }
15217 : break;
15218 : case 'u': // 2 strings to match.
15219 0 : if (memcmp(Mnemonic.data()+10, "16_u32_e", 8))
15220 : break;
15221 0 : switch (Mnemonic[18]) {
15222 : default: break;
15223 : case '3': // 1 string to match.
15224 0 : if (Mnemonic[19] != '2')
15225 : break;
15226 0 : Mnemonic = "v_cvt_pk_u16_u32"; // "v_cvt_pk_u16_u32_e32"
15227 0 : return;
15228 : case '6': // 1 string to match.
15229 0 : if (Mnemonic[19] != '4')
15230 : break;
15231 0 : Mnemonic = "v_cvt_pk_u16_u32"; // "v_cvt_pk_u16_u32_e64"
15232 0 : return;
15233 : }
15234 : break;
15235 : }
15236 : break;
15237 : }
15238 : break;
15239 : }
15240 : break;
15241 : case 'e': // 2 strings to match.
15242 0 : if (memcmp(Mnemonic.data()+3, "xp_legacy_f32_e", 15))
15243 : break;
15244 0 : switch (Mnemonic[18]) {
15245 : default: break;
15246 : case '3': // 1 string to match.
15247 0 : if (Mnemonic[19] != '2')
15248 : break;
15249 0 : Mnemonic = "v_exp_legacy_f32"; // "v_exp_legacy_f32_e32"
15250 0 : return;
15251 : case '6': // 1 string to match.
15252 0 : if (Mnemonic[19] != '4')
15253 : break;
15254 0 : Mnemonic = "v_exp_legacy_f32"; // "v_exp_legacy_f32_e64"
15255 0 : return;
15256 : }
15257 : break;
15258 : case 'f': // 6 strings to match.
15259 0 : if (memcmp(Mnemonic.data()+3, "rexp_mant_f", 11))
15260 : break;
15261 0 : switch (Mnemonic[14]) {
15262 : default: break;
15263 : case '1': // 2 strings to match.
15264 0 : if (memcmp(Mnemonic.data()+15, "6_e", 3))
15265 : break;
15266 0 : switch (Mnemonic[18]) {
15267 : default: break;
15268 : case '3': // 1 string to match.
15269 0 : if (Mnemonic[19] != '2')
15270 : break;
15271 0 : Mnemonic = "v_frexp_mant_f16"; // "v_frexp_mant_f16_e32"
15272 0 : return;
15273 : case '6': // 1 string to match.
15274 0 : if (Mnemonic[19] != '4')
15275 : break;
15276 0 : Mnemonic = "v_frexp_mant_f16"; // "v_frexp_mant_f16_e64"
15277 0 : return;
15278 : }
15279 : break;
15280 : case '3': // 2 strings to match.
15281 0 : if (memcmp(Mnemonic.data()+15, "2_e", 3))
15282 : break;
15283 0 : switch (Mnemonic[18]) {
15284 : default: break;
15285 : case '3': // 1 string to match.
15286 0 : if (Mnemonic[19] != '2')
15287 : break;
15288 0 : Mnemonic = "v_frexp_mant_f32"; // "v_frexp_mant_f32_e32"
15289 0 : return;
15290 : case '6': // 1 string to match.
15291 0 : if (Mnemonic[19] != '4')
15292 : break;
15293 0 : Mnemonic = "v_frexp_mant_f32"; // "v_frexp_mant_f32_e64"
15294 0 : return;
15295 : }
15296 : break;
15297 : case '6': // 2 strings to match.
15298 0 : if (memcmp(Mnemonic.data()+15, "4_e", 3))
15299 : break;
15300 0 : switch (Mnemonic[18]) {
15301 : default: break;
15302 : case '3': // 1 string to match.
15303 0 : if (Mnemonic[19] != '2')
15304 : break;
15305 0 : Mnemonic = "v_frexp_mant_f64"; // "v_frexp_mant_f64_e32"
15306 0 : return;
15307 : case '6': // 1 string to match.
15308 0 : if (Mnemonic[19] != '4')
15309 : break;
15310 0 : Mnemonic = "v_frexp_mant_f64"; // "v_frexp_mant_f64_e64"
15311 0 : return;
15312 : }
15313 : break;
15314 : }
15315 : break;
15316 : case 'l': // 2 strings to match.
15317 0 : if (memcmp(Mnemonic.data()+3, "og_legacy_f32_e", 15))
15318 : break;
15319 0 : switch (Mnemonic[18]) {
15320 : default: break;
15321 : case '3': // 1 string to match.
15322 0 : if (Mnemonic[19] != '2')
15323 : break;
15324 0 : Mnemonic = "v_log_legacy_f32"; // "v_log_legacy_f32_e32"
15325 0 : return;
15326 : case '6': // 1 string to match.
15327 0 : if (Mnemonic[19] != '4')
15328 : break;
15329 0 : Mnemonic = "v_log_legacy_f32"; // "v_log_legacy_f32_e64"
15330 0 : return;
15331 : }
15332 : break;
15333 : case 'm': // 13 strings to match.
15334 0 : switch (Mnemonic[3]) {
15335 : default: break;
15336 : case 'a': // 5 strings to match.
15337 0 : switch (Mnemonic[4]) {
15338 : default: break;
15339 : case 'c': // 2 strings to match.
15340 0 : if (memcmp(Mnemonic.data()+5, "_legacy_f32_e", 13))
15341 : break;
15342 0 : switch (Mnemonic[18]) {
15343 : default: break;
15344 : case '3': // 1 string to match.
15345 0 : if (Mnemonic[19] != '2')
15346 : break;
15347 0 : Mnemonic = "v_mac_legacy_f32"; // "v_mac_legacy_f32_e32"
15348 0 : return;
15349 : case '6': // 1 string to match.
15350 0 : if (Mnemonic[19] != '4')
15351 : break;
15352 0 : Mnemonic = "v_mac_legacy_f32"; // "v_mac_legacy_f32_e64"
15353 0 : return;
15354 : }
15355 : break;
15356 : case 'd': // 1 string to match.
15357 0 : if (memcmp(Mnemonic.data()+5, "_legacy_f32_e64", 15))
15358 : break;
15359 0 : Mnemonic = "v_mad_legacy_f32"; // "v_mad_legacy_f32_e64"
15360 0 : return;
15361 : case 'x': // 2 strings to match.
15362 0 : if (memcmp(Mnemonic.data()+5, "_legacy_f32_e", 13))
15363 : break;
15364 0 : switch (Mnemonic[18]) {
15365 : default: break;
15366 : case '3': // 1 string to match.
15367 0 : if (Mnemonic[19] != '2')
15368 : break;
15369 0 : Mnemonic = "v_max_legacy_f32"; // "v_max_legacy_f32_e32"
15370 0 : return;
15371 : case '6': // 1 string to match.
15372 0 : if (Mnemonic[19] != '4')
15373 : break;
15374 0 : Mnemonic = "v_max_legacy_f32"; // "v_max_legacy_f32_e64"
15375 0 : return;
15376 : }
15377 : break;
15378 : }
15379 : break;
15380 : case 'i': // 2 strings to match.
15381 0 : if (memcmp(Mnemonic.data()+4, "n_legacy_f32_e", 14))
15382 : break;
15383 0 : switch (Mnemonic[18]) {
15384 : default: break;
15385 : case '3': // 1 string to match.
15386 0 : if (Mnemonic[19] != '2')
15387 : break;
15388 0 : Mnemonic = "v_min_legacy_f32"; // "v_min_legacy_f32_e32"
15389 0 : return;
15390 : case '6': // 1 string to match.
15391 0 : if (Mnemonic[19] != '4')
15392 : break;
15393 0 : Mnemonic = "v_min_legacy_f32"; // "v_min_legacy_f32_e64"
15394 0 : return;
15395 : }
15396 : break;
15397 : case 'u': // 6 strings to match.
15398 0 : if (memcmp(Mnemonic.data()+4, "l_", 2))
15399 : break;
15400 0 : switch (Mnemonic[6]) {
15401 : default: break;
15402 : case 'h': // 4 strings to match.
15403 0 : if (memcmp(Mnemonic.data()+7, "i_", 2))
15404 : break;
15405 0 : switch (Mnemonic[9]) {
15406 : default: break;
15407 : case 'i': // 2 strings to match.
15408 0 : if (memcmp(Mnemonic.data()+10, "32_i24_e", 8))
15409 : break;
15410 0 : switch (Mnemonic[18]) {
15411 : default: break;
15412 : case '3': // 1 string to match.
15413 0 : if (Mnemonic[19] != '2')
15414 : break;
15415 0 : Mnemonic = "v_mul_hi_i32_i24"; // "v_mul_hi_i32_i24_e32"
15416 0 : return;
15417 : case '6': // 1 string to match.
15418 0 : if (Mnemonic[19] != '4')
15419 : break;
15420 0 : Mnemonic = "v_mul_hi_i32_i24"; // "v_mul_hi_i32_i24_e64"
15421 0 : return;
15422 : }
15423 : break;
15424 : case 'u': // 2 strings to match.
15425 0 : if (memcmp(Mnemonic.data()+10, "32_u24_e", 8))
15426 : break;
15427 0 : switch (Mnemonic[18]) {
15428 : default: break;
15429 : case '3': // 1 string to match.
15430 0 : if (Mnemonic[19] != '2')
15431 : break;
15432 0 : Mnemonic = "v_mul_hi_u32_u24"; // "v_mul_hi_u32_u24_e32"
15433 0 : return;
15434 : case '6': // 1 string to match.
15435 0 : if (Mnemonic[19] != '4')
15436 : break;
15437 0 : Mnemonic = "v_mul_hi_u32_u24"; // "v_mul_hi_u32_u24_e64"
15438 0 : return;
15439 : }
15440 : break;
15441 : }
15442 : break;
15443 : case 'l': // 2 strings to match.
15444 0 : if (memcmp(Mnemonic.data()+7, "egacy_f32_e", 11))
15445 : break;
15446 0 : switch (Mnemonic[18]) {
15447 : default: break;
15448 : case '3': // 1 string to match.
15449 0 : if (Mnemonic[19] != '2')
15450 : break;
15451 0 : Mnemonic = "v_mul_legacy_f32"; // "v_mul_legacy_f32_e32"
15452 0 : return;
15453 : case '6': // 1 string to match.
15454 0 : if (Mnemonic[19] != '4')
15455 : break;
15456 0 : Mnemonic = "v_mul_legacy_f32"; // "v_mul_legacy_f32_e64"
15457 0 : return;
15458 : }
15459 : break;
15460 : }
15461 : break;
15462 : }
15463 : break;
15464 : case 'q': // 1 string to match.
15465 0 : if (memcmp(Mnemonic.data()+3, "sad_pk_u16_u8_e64", 17))
15466 : break;
15467 0 : if ((Features & Feature_isGCN) == Feature_isGCN) // "v_qsad_pk_u16_u8_e64"
15468 0 : Mnemonic = "v_qsad_pk_u16_u8";
15469 : return;
15470 : case 'r': // 4 strings to match.
15471 0 : switch (Mnemonic[3]) {
15472 : default: break;
15473 : case 'c': // 2 strings to match.
15474 0 : if (memcmp(Mnemonic.data()+4, "p_legacy_f32_e", 14))
15475 : break;
15476 0 : switch (Mnemonic[18]) {
15477 : default: break;
15478 : case '3': // 1 string to match.
15479 0 : if (Mnemonic[19] != '2')
15480 : break;
15481 0 : Mnemonic = "v_rcp_legacy_f32"; // "v_rcp_legacy_f32_e32"
15482 0 : return;
15483 : case '6': // 1 string to match.
15484 0 : if (Mnemonic[19] != '4')
15485 : break;
15486 0 : Mnemonic = "v_rcp_legacy_f32"; // "v_rcp_legacy_f32_e64"
15487 0 : return;
15488 : }
15489 : break;
15490 : case 's': // 2 strings to match.
15491 0 : if (memcmp(Mnemonic.data()+4, "q_legacy_f32_e", 14))
15492 : break;
15493 0 : switch (Mnemonic[18]) {
15494 : default: break;
15495 : case '3': // 1 string to match.
15496 0 : if (Mnemonic[19] != '2')
15497 : break;
15498 0 : Mnemonic = "v_rsq_legacy_f32"; // "v_rsq_legacy_f32_e32"
15499 0 : return;
15500 : case '6': // 1 string to match.
15501 0 : if (Mnemonic[19] != '4')
15502 : break;
15503 0 : Mnemonic = "v_rsq_legacy_f32"; // "v_rsq_legacy_f32_e64"
15504 0 : return;
15505 : }
15506 : break;
15507 : }
15508 : break;
15509 : case 't': // 1 string to match.
15510 0 : if (memcmp(Mnemonic.data()+3, "rig_preop_f64_e64", 17))
15511 : break;
15512 0 : Mnemonic = "v_trig_preop_f64"; // "v_trig_preop_f64_e64"
15513 0 : return;
15514 : }
15515 : break;
15516 : case 21: // 4 strings to match.
15517 4 : if (memcmp(Mnemonic.data()+0, "v_cvt_", 6))
15518 : break;
15519 0 : switch (Mnemonic[6]) {
15520 : default: break;
15521 : case 'f': // 2 strings to match.
15522 0 : if (memcmp(Mnemonic.data()+7, "lr_i32_f32_e", 12))
15523 : break;
15524 0 : switch (Mnemonic[19]) {
15525 : default: break;
15526 : case '3': // 1 string to match.
15527 0 : if (Mnemonic[20] != '2')
15528 : break;
15529 0 : Mnemonic = "v_cvt_flr_i32_f32"; // "v_cvt_flr_i32_f32_e32"
15530 0 : return;
15531 : case '6': // 1 string to match.
15532 0 : if (Mnemonic[20] != '4')
15533 : break;
15534 0 : Mnemonic = "v_cvt_flr_i32_f32"; // "v_cvt_flr_i32_f32_e64"
15535 0 : return;
15536 : }
15537 : break;
15538 : case 'r': // 2 strings to match.
15539 0 : if (memcmp(Mnemonic.data()+7, "pi_i32_f32_e", 12))
15540 : break;
15541 0 : switch (Mnemonic[19]) {
15542 : default: break;
15543 : case '3': // 1 string to match.
15544 0 : if (Mnemonic[20] != '2')
15545 : break;
15546 0 : Mnemonic = "v_cvt_rpi_i32_f32"; // "v_cvt_rpi_i32_f32_e32"
15547 0 : return;
15548 : case '6': // 1 string to match.
15549 0 : if (Mnemonic[20] != '4')
15550 : break;
15551 0 : Mnemonic = "v_cvt_rpi_i32_f32"; // "v_cvt_rpi_i32_f32_e64"
15552 0 : return;
15553 : }
15554 : break;
15555 : }
15556 : break;
15557 : case 22: // 4 strings to match.
15558 8 : if (memcmp(Mnemonic.data()+0, "v_mbcnt_", 8))
15559 : break;
15560 0 : switch (Mnemonic[8]) {
15561 : default: break;
15562 : case 'h': // 2 strings to match.
15563 0 : if (memcmp(Mnemonic.data()+9, "i_u32_b32_e", 11))
15564 : break;
15565 0 : switch (Mnemonic[20]) {
15566 : default: break;
15567 : case '3': // 1 string to match.
15568 0 : if (Mnemonic[21] != '2')
15569 : break;
15570 0 : Mnemonic = "v_mbcnt_hi_u32_b32"; // "v_mbcnt_hi_u32_b32_e32"
15571 0 : return;
15572 : case '6': // 1 string to match.
15573 0 : if (Mnemonic[21] != '4')
15574 : break;
15575 0 : Mnemonic = "v_mbcnt_hi_u32_b32"; // "v_mbcnt_hi_u32_b32_e64"
15576 0 : return;
15577 : }
15578 : break;
15579 : case 'l': // 2 strings to match.
15580 0 : if (memcmp(Mnemonic.data()+9, "o_u32_b32_e", 11))
15581 : break;
15582 0 : switch (Mnemonic[20]) {
15583 : default: break;
15584 : case '3': // 1 string to match.
15585 0 : if (Mnemonic[21] != '2')
15586 : break;
15587 0 : Mnemonic = "v_mbcnt_lo_u32_b32"; // "v_mbcnt_lo_u32_b32_e32"
15588 0 : return;
15589 : case '6': // 1 string to match.
15590 0 : if (Mnemonic[21] != '4')
15591 : break;
15592 0 : Mnemonic = "v_mbcnt_lo_u32_b32"; // "v_mbcnt_lo_u32_b32_e64"
15593 0 : return;
15594 : }
15595 : break;
15596 : }
15597 : break;
15598 : case 23: // 8 strings to match.
15599 4 : if (memcmp(Mnemonic.data()+0, "v_", 2))
15600 : break;
15601 0 : switch (Mnemonic[2]) {
15602 : default: break;
15603 : case 'c': // 2 strings to match.
15604 0 : if (memcmp(Mnemonic.data()+3, "vt_pkrtz_f16_f32_e", 18))
15605 : break;
15606 0 : switch (Mnemonic[21]) {
15607 : default: break;
15608 : case '3': // 1 string to match.
15609 0 : if (Mnemonic[22] != '2')
15610 : break;
15611 0 : Mnemonic = "v_cvt_pkrtz_f16_f32"; // "v_cvt_pkrtz_f16_f32_e32"
15612 0 : return;
15613 : case '6': // 1 string to match.
15614 0 : if (Mnemonic[22] != '4')
15615 : break;
15616 0 : Mnemonic = "v_cvt_pkrtz_f16_f32"; // "v_cvt_pkrtz_f16_f32_e64"
15617 0 : return;
15618 : }
15619 : break;
15620 : case 'f': // 6 strings to match.
15621 0 : if (memcmp(Mnemonic.data()+3, "rexp_exp_i", 10))
15622 : break;
15623 0 : switch (Mnemonic[13]) {
15624 : default: break;
15625 : case '1': // 2 strings to match.
15626 0 : if (memcmp(Mnemonic.data()+14, "6_f16_e", 7))
15627 : break;
15628 0 : switch (Mnemonic[21]) {
15629 : default: break;
15630 : case '3': // 1 string to match.
15631 0 : if (Mnemonic[22] != '2')
15632 : break;
15633 0 : Mnemonic = "v_frexp_exp_i16_f16"; // "v_frexp_exp_i16_f16_e32"
15634 0 : return;
15635 : case '6': // 1 string to match.
15636 0 : if (Mnemonic[22] != '4')
15637 : break;
15638 0 : Mnemonic = "v_frexp_exp_i16_f16"; // "v_frexp_exp_i16_f16_e64"
15639 0 : return;
15640 : }
15641 : break;
15642 : case '3': // 4 strings to match.
15643 0 : if (memcmp(Mnemonic.data()+14, "2_f", 3))
15644 : break;
15645 0 : switch (Mnemonic[17]) {
15646 : default: break;
15647 : case '3': // 2 strings to match.
15648 0 : if (memcmp(Mnemonic.data()+18, "2_e", 3))
15649 : break;
15650 0 : switch (Mnemonic[21]) {
15651 : default: break;
15652 : case '3': // 1 string to match.
15653 0 : if (Mnemonic[22] != '2')
15654 : break;
15655 0 : Mnemonic = "v_frexp_exp_i32_f32"; // "v_frexp_exp_i32_f32_e32"
15656 0 : return;
15657 : case '6': // 1 string to match.
15658 0 : if (Mnemonic[22] != '4')
15659 : break;
15660 0 : Mnemonic = "v_frexp_exp_i32_f32"; // "v_frexp_exp_i32_f32_e64"
15661 0 : return;
15662 : }
15663 : break;
15664 : case '6': // 2 strings to match.
15665 0 : if (memcmp(Mnemonic.data()+18, "4_e", 3))
15666 : break;
15667 0 : switch (Mnemonic[21]) {
15668 : default: break;
15669 : case '3': // 1 string to match.
15670 0 : if (Mnemonic[22] != '2')
15671 : break;
15672 0 : Mnemonic = "v_frexp_exp_i32_f64"; // "v_frexp_exp_i32_f64_e32"
15673 0 : return;
15674 : case '6': // 1 string to match.
15675 0 : if (Mnemonic[22] != '4')
15676 : break;
15677 0 : Mnemonic = "v_frexp_exp_i32_f64"; // "v_frexp_exp_i32_f64_e64"
15678 0 : return;
15679 : }
15680 : break;
15681 : }
15682 : break;
15683 : }
15684 : break;
15685 : }
15686 : break;
15687 : case 24: // 6 strings to match.
15688 2 : if (memcmp(Mnemonic.data()+0, "v_cvt_pk", 8))
15689 : break;
15690 0 : switch (Mnemonic[8]) {
15691 : default: break;
15692 : case 'a': // 2 strings to match.
15693 0 : if (memcmp(Mnemonic.data()+9, "ccum_u8_f32_e", 13))
15694 : break;
15695 0 : switch (Mnemonic[22]) {
15696 : default: break;
15697 : case '3': // 1 string to match.
15698 0 : if (Mnemonic[23] != '2')
15699 : break;
15700 0 : Mnemonic = "v_cvt_pkaccum_u8_f32"; // "v_cvt_pkaccum_u8_f32_e32"
15701 0 : return;
15702 : case '6': // 1 string to match.
15703 0 : if (Mnemonic[23] != '4')
15704 : break;
15705 0 : Mnemonic = "v_cvt_pkaccum_u8_f32"; // "v_cvt_pkaccum_u8_f32_e64"
15706 0 : return;
15707 : }
15708 : break;
15709 : case 'n': // 4 strings to match.
15710 0 : if (memcmp(Mnemonic.data()+9, "orm_", 4))
15711 : break;
15712 0 : switch (Mnemonic[13]) {
15713 : default: break;
15714 : case 'i': // 2 strings to match.
15715 0 : if (memcmp(Mnemonic.data()+14, "16_f32_e", 8))
15716 : break;
15717 0 : switch (Mnemonic[22]) {
15718 : default: break;
15719 : case '3': // 1 string to match.
15720 0 : if (Mnemonic[23] != '2')
15721 : break;
15722 0 : Mnemonic = "v_cvt_pknorm_i16_f32"; // "v_cvt_pknorm_i16_f32_e32"
15723 0 : return;
15724 : case '6': // 1 string to match.
15725 0 : if (Mnemonic[23] != '4')
15726 : break;
15727 0 : Mnemonic = "v_cvt_pknorm_i16_f32"; // "v_cvt_pknorm_i16_f32_e64"
15728 0 : return;
15729 : }
15730 : break;
15731 : case 'u': // 2 strings to match.
15732 0 : if (memcmp(Mnemonic.data()+14, "16_f32_e", 8))
15733 : break;
15734 0 : switch (Mnemonic[22]) {
15735 : default: break;
15736 : case '3': // 1 string to match.
15737 0 : if (Mnemonic[23] != '2')
15738 : break;
15739 0 : Mnemonic = "v_cvt_pknorm_u16_f32"; // "v_cvt_pknorm_u16_f32_e32"
15740 0 : return;
15741 : case '6': // 1 string to match.
15742 0 : if (Mnemonic[23] != '4')
15743 : break;
15744 0 : Mnemonic = "v_cvt_pknorm_u16_f32"; // "v_cvt_pknorm_u16_f32_e64"
15745 0 : return;
15746 : }
15747 : break;
15748 : }
15749 : break;
15750 : }
15751 : break;
15752 : }
15753 : }
15754 :
15755 : namespace {
15756 : enum OperatorConversionKind {
15757 : CVT_Done,
15758 : CVT_Reg,
15759 : CVT_Tied,
15760 : CVT_95_addImmOperands,
15761 : CVT_95_Reg,
15762 : CVT_imm_95_0,
15763 : CVT_cvtMubuf,
15764 : CVT_cvtDS,
15765 : CVT_cvtDSOffset01,
15766 : CVT_95_addRegOrImmOperands,
15767 : CVT_95_addSoppBrTargetOperands,
15768 : CVT_cvtVOP3,
15769 : CVT_NUM_CONVERTERS
15770 : };
15771 :
15772 : enum InstructionConversionKind {
15773 : Convert_NoOperands,
15774 : Convert__Imm1_1,
15775 : Convert__Imm1_1__Imm1_3,
15776 : Convert__Reg1_2__Imm1_0,
15777 : Convert__Reg1_4__imm_95_0__Imm1_0__Reg1_1__Reg1_2,
15778 : Convert__Reg1_0,
15779 : Convert__Imm1_2__Imm1_0,
15780 : ConvertCustom_cvtMubuf,
15781 : ConvertCustom_cvtDS,
15782 : ConvertCustom_cvtDSOffset01,
15783 : Convert__Imm1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Reg1_5__Reg1_6__Reg1_7__Reg1_8,
15784 : Convert__Reg1_0__Reg1_1,
15785 : Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11,
15786 : Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10,
15787 : Convert__Reg1_0__SSrc321_1,
15788 : Convert__Reg1_0__SSrc321_1__SSrc321_2,
15789 : Convert__Reg1_0__Tie0__Imm1_1,
15790 : Convert__Reg1_0__SSrc641_1__SSrc641_2,
15791 : Convert__Reg1_0__SSrc641_1,
15792 : Convert__Reg1_0__SSrc641_1__SSrc321_2,
15793 : Convert__SoppBrTarget1_0,
15794 : Convert__Reg1_0__Reg1_1__Reg1_2,
15795 : Convert__Reg1_0__Reg1_1__Imm1_2,
15796 : Convert__SoppBrTarget1_0__imm_95_0,
15797 : Convert__Reg1_0__Imm1_1,
15798 : Convert__imm_95_0__SSrc321_0__SSrc321_1,
15799 : Convert__imm_95_0__Reg1_0__Imm1_1,
15800 : Convert__Imm1_0,
15801 : Convert__Imm1_0__Imm1_1,
15802 : Convert__SWaitCnt1_0,
15803 : Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Reg1_8__Reg1_9__Imm1_10__Imm1_11__SCSrc321_12,
15804 : Convert__Reg1_0__VSrc321_1__Reg1_2,
15805 : ConvertCustom_cvtVOP3,
15806 : Convert__Reg1_0__VCSrc321_1__Reg1_2,
15807 : Convert__Reg1_0__VSrc321_1,
15808 : Convert__Reg1_0__VSrc641_1,
15809 : Convert__Reg1_0__VSrc641_1__Reg1_2,
15810 : Convert__Reg1_0__VSrc321_1__Reg1_2__imm_95_0,
15811 : Convert__Reg1_0__imm_95_0__VCSrc321_1__imm_95_0__VCSrc321_2__imm_95_0__imm_95_0,
15812 : Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3,
15813 : Convert__Reg1_0__Reg1_1__Imm1_2__Imm1_3,
15814 : Convert__Reg1_0__Tie0__Reg1_4__Imm1_5__Imm1_6,
15815 : Convert__Reg1_0__VCSrc321_1__Reg1_2__Imm1_3,
15816 : Convert__Reg1_0__Reg1_1__SCSrc321_2,
15817 : CVT_NUM_SIGNATURES
15818 : };
15819 :
15820 : } // end anonymous namespace
15821 :
15822 : static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][27] = {
15823 : // Convert_NoOperands
15824 : { CVT_Done },
15825 : // Convert__Imm1_1
15826 : { CVT_95_addImmOperands, 2, CVT_Done },
15827 : // Convert__Imm1_1__Imm1_3
15828 : { CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
15829 : // Convert__Reg1_2__Imm1_0
15830 : { CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
15831 : // Convert__Reg1_4__imm_95_0__Imm1_0__Reg1_1__Reg1_2
15832 : { CVT_95_Reg, 5, CVT_imm_95_0, 0, CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
15833 : // Convert__Reg1_0
15834 : { CVT_95_Reg, 1, CVT_Done },
15835 : // Convert__Imm1_2__Imm1_0
15836 : { CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
15837 : // ConvertCustom_cvtMubuf
15838 : { CVT_cvtMubuf, 0, CVT_Done },
15839 : // ConvertCustom_cvtDS
15840 : { CVT_cvtDS, 0, CVT_Done },
15841 : // ConvertCustom_cvtDSOffset01
15842 : { CVT_cvtDSOffset01, 0, CVT_Done },
15843 : // Convert__Imm1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Reg1_5__Reg1_6__Reg1_7__Reg1_8
15844 : { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_Reg, 8, CVT_95_Reg, 9, CVT_Done },
15845 : // Convert__Reg1_0__Reg1_1
15846 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
15847 : // Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11
15848 : { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addImmOperands, 8, CVT_95_addImmOperands, 9, CVT_95_Reg, 10, CVT_95_Reg, 11, CVT_95_Reg, 12, CVT_Done },
15849 : // Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10
15850 : { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addImmOperands, 8, CVT_95_addImmOperands, 9, CVT_95_Reg, 10, CVT_95_Reg, 11, CVT_Done },
15851 : // Convert__Reg1_0__SSrc321_1
15852 : { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_Done },
15853 : // Convert__Reg1_0__SSrc321_1__SSrc321_2
15854 : { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_addRegOrImmOperands, 3, CVT_Done },
15855 : // Convert__Reg1_0__Tie0__Imm1_1
15856 : { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addImmOperands, 2, CVT_Done },
15857 : // Convert__Reg1_0__SSrc641_1__SSrc641_2
15858 : { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_addRegOrImmOperands, 3, CVT_Done },
15859 : // Convert__Reg1_0__SSrc641_1
15860 : { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_Done },
15861 : // Convert__Reg1_0__SSrc641_1__SSrc321_2
15862 : { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_addRegOrImmOperands, 3, CVT_Done },
15863 : // Convert__SoppBrTarget1_0
15864 : { CVT_95_addSoppBrTargetOperands, 1, CVT_Done },
15865 : // Convert__Reg1_0__Reg1_1__Reg1_2
15866 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
15867 : // Convert__Reg1_0__Reg1_1__Imm1_2
15868 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
15869 : // Convert__SoppBrTarget1_0__imm_95_0
15870 : { CVT_95_addSoppBrTargetOperands, 1, CVT_imm_95_0, 0, CVT_Done },
15871 : // Convert__Reg1_0__Imm1_1
15872 : { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
15873 : // Convert__imm_95_0__SSrc321_0__SSrc321_1
15874 : { CVT_imm_95_0, 0, CVT_95_addRegOrImmOperands, 1, CVT_95_addRegOrImmOperands, 2, CVT_Done },
15875 : // Convert__imm_95_0__Reg1_0__Imm1_1
15876 : { CVT_imm_95_0, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
15877 : // Convert__Imm1_0
15878 : { CVT_95_addImmOperands, 1, CVT_Done },
15879 : // Convert__Imm1_0__Imm1_1
15880 : { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
15881 : // Convert__SWaitCnt1_0
15882 : { CVT_95_addImmOperands, 1, CVT_Done },
15883 : // Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Reg1_8__Reg1_9__Imm1_10__Imm1_11__SCSrc321_12
15884 : { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addImmOperands, 8, CVT_95_Reg, 9, CVT_95_Reg, 10, CVT_95_addImmOperands, 11, CVT_95_addImmOperands, 12, CVT_95_addRegOrImmOperands, 13, CVT_Done },
15885 : // Convert__Reg1_0__VSrc321_1__Reg1_2
15886 : { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_Reg, 3, CVT_Done },
15887 : // ConvertCustom_cvtVOP3
15888 : { CVT_cvtVOP3, 0, CVT_Done },
15889 : // Convert__Reg1_0__VCSrc321_1__Reg1_2
15890 : { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_Reg, 3, CVT_Done },
15891 : // Convert__Reg1_0__VSrc321_1
15892 : { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_Done },
15893 : // Convert__Reg1_0__VSrc641_1
15894 : { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_Done },
15895 : // Convert__Reg1_0__VSrc641_1__Reg1_2
15896 : { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_Reg, 3, CVT_Done },
15897 : // Convert__Reg1_0__VSrc321_1__Reg1_2__imm_95_0
15898 : { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
15899 : // Convert__Reg1_0__imm_95_0__VCSrc321_1__imm_95_0__VCSrc321_2__imm_95_0__imm_95_0
15900 : { CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_95_addRegOrImmOperands, 2, CVT_imm_95_0, 0, CVT_95_addRegOrImmOperands, 3, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
15901 : // Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3
15902 : { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
15903 : // Convert__Reg1_0__Reg1_1__Imm1_2__Imm1_3
15904 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
15905 : // Convert__Reg1_0__Tie0__Reg1_4__Imm1_5__Imm1_6
15906 : { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
15907 : // Convert__Reg1_0__VCSrc321_1__Reg1_2__Imm1_3
15908 : { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
15909 : // Convert__Reg1_0__Reg1_1__SCSrc321_2
15910 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addRegOrImmOperands, 3, CVT_Done },
15911 : };
15912 :
15913 1952 : void AMDGPUAsmParser::
15914 : convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
15915 : const OperandVector &Operands) {
15916 : assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
15917 1952 : const uint8_t *Converter = ConversionTable[Kind];
15918 1952 : Inst.setOpcode(Opcode);
15919 5962 : for (const uint8_t *p = Converter; *p; p+= 2) {
15920 4010 : switch (*p) {
15921 0 : default: llvm_unreachable("invalid conversion entry!");
15922 : case CVT_Reg:
15923 0 : static_cast<AMDGPUOperand&>(*Operands[*(p + 1)]).addRegOperands(Inst, 1);
15924 : break;
15925 : case CVT_Tied:
15926 8 : Inst.addOperand(Inst.getOperand(*(p + 1)));
15927 : break;
15928 : case CVT_95_addImmOperands:
15929 330 : static_cast<AMDGPUOperand&>(*Operands[*(p + 1)]).addImmOperands(Inst, 1);
15930 : break;
15931 : case CVT_95_Reg:
15932 5694 : static_cast<AMDGPUOperand&>(*Operands[*(p + 1)]).addRegOperands(Inst, 1);
15933 : break;
15934 : case CVT_imm_95_0:
15935 172 : Inst.addOperand(MCOperand::createImm(0));
15936 : break;
15937 : case CVT_cvtMubuf:
15938 200 : cvtMubuf(Inst, Operands);
15939 : break;
15940 : case CVT_cvtDS:
15941 188 : cvtDS(Inst, Operands);
15942 : break;
15943 : case CVT_cvtDSOffset01:
15944 28 : cvtDSOffset01(Inst, Operands);
15945 : break;
15946 : case CVT_95_addRegOrImmOperands:
15947 4026 : static_cast<AMDGPUOperand&>(*Operands[*(p + 1)]).addRegOrImmOperands(Inst, 1);
15948 : break;
15949 : case CVT_95_addSoppBrTargetOperands:
15950 42 : static_cast<AMDGPUOperand&>(*Operands[*(p + 1)]).addSoppBrTargetOperands(Inst, 1);
15951 : break;
15952 : case CVT_cvtVOP3:
15953 140 : cvtVOP3(Inst, Operands);
15954 : break;
15955 : }
15956 : }
15957 1952 : }
15958 :
15959 0 : void AMDGPUAsmParser::
15960 : convertToMapAndConstraints(unsigned Kind,
15961 : const OperandVector &Operands) {
15962 : assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
15963 0 : unsigned NumMCOperands = 0;
15964 0 : const uint8_t *Converter = ConversionTable[Kind];
15965 0 : for (const uint8_t *p = Converter; *p; p+= 2) {
15966 0 : switch (*p) {
15967 0 : default: llvm_unreachable("invalid conversion entry!");
15968 : case CVT_Reg:
15969 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
15970 0 : Operands[*(p + 1)]->setConstraint("r");
15971 0 : ++NumMCOperands;
15972 0 : break;
15973 : case CVT_Tied:
15974 0 : ++NumMCOperands;
15975 0 : break;
15976 : case CVT_95_addImmOperands:
15977 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
15978 0 : Operands[*(p + 1)]->setConstraint("m");
15979 0 : NumMCOperands += 1;
15980 0 : break;
15981 : case CVT_95_Reg:
15982 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
15983 0 : Operands[*(p + 1)]->setConstraint("r");
15984 0 : NumMCOperands += 1;
15985 0 : break;
15986 : case CVT_imm_95_0:
15987 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
15988 0 : Operands[*(p + 1)]->setConstraint("");
15989 0 : ++NumMCOperands;
15990 0 : break;
15991 : case CVT_95_addRegOrImmOperands:
15992 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
15993 0 : Operands[*(p + 1)]->setConstraint("m");
15994 0 : NumMCOperands += 1;
15995 0 : break;
15996 : case CVT_95_addSoppBrTargetOperands:
15997 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
15998 0 : Operands[*(p + 1)]->setConstraint("m");
15999 0 : NumMCOperands += 1;
16000 0 : break;
16001 : }
16002 : }
16003 0 : }
16004 :
16005 : namespace {
16006 :
16007 : /// MatchClassKind - The kinds of classes which participate in
16008 : /// instruction matching.
16009 : enum MatchClassKind {
16010 : InvalidMatchClass = 0,
16011 : MCK__COLON_, // ':'
16012 : MCK__64_, // '@'
16013 : MCK_FLAT_95_SCRATCH, // 'FLAT_SCRATCH'
16014 : MCK_POP_COLON_, // 'POP:'
16015 : MCK__91_, // '['
16016 : MCK__93_, // ']'
16017 : MCK_addr64, // 'addr64'
16018 : MCK_dst1, // 'dst1'
16019 : MCK_gds, // 'gds'
16020 : MCK_glc, // 'glc'
16021 : MCK_idxen, // 'idxen'
16022 : MCK_offen, // 'offen'
16023 : MCK_R600_TReg32_X, // register class 'R600_TReg32_X'
16024 : MCK_R600_TReg32_Y, // register class 'R600_TReg32_Y'
16025 : MCK_R600_TReg32_Z, // register class 'R600_TReg32_Z'
16026 : MCK_R600_TReg32_W, // register class 'R600_TReg32_W'
16027 : MCK_R600_TReg32, // register class 'R600_TReg32'
16028 : MCK_R600_Addr, // register class 'R600_Addr'
16029 : MCK_R600_KC0_W, // register class 'R600_KC0_W'
16030 : MCK_R600_KC1_X, // register class 'R600_KC1_X'
16031 : MCK_R600_KC1_Y, // register class 'R600_KC1_Y'
16032 : MCK_R600_KC1_Z, // register class 'R600_KC1_Z'
16033 : MCK_R600_KC1_W, // register class 'R600_KC1_W'
16034 : MCK_R600_KC1, // register class 'R600_KC1'
16035 : MCK_R600_ArrayBase, // register class 'R600_ArrayBase'
16036 : MCK_Reg34, // derived register class
16037 : MCK_R600_LDS_SRC_REG, // register class 'R600_LDS_SRC_REG'
16038 : MCK_R600_Reg32, // register class 'R600_Reg32'
16039 : MCK_R600_Addr_Y, // register class 'R600_Addr_Y'
16040 : MCK_R600_Addr_Z, // register class 'R600_Addr_Z'
16041 : MCK_R600_Addr_W, // register class 'R600_Addr_W'
16042 : MCK_R600_Reg128, // register class 'R600_Reg128'
16043 : MCK_R600_Reg64, // register class 'R600_Reg64'
16044 : MCK_Reg12, // derived register class
16045 : MCK_Reg14, // derived register class
16046 : MCK_Reg15, // derived register class
16047 : MCK_Reg16, // derived register class
16048 : MCK_R600_Reg128Vertical, // register class 'R600_Reg128Vertical'
16049 : MCK_Reg18, // derived register class
16050 : MCK_Reg19, // derived register class
16051 : MCK_Reg20, // derived register class
16052 : MCK_Reg21, // derived register class
16053 : MCK_R600_Reg64Vertical, // register class 'R600_Reg64Vertical'
16054 : MCK_R600_KC0_X, // register class 'R600_KC0_X'
16055 : MCK_R600_KC0_Y, // register class 'R600_KC0_Y'
16056 : MCK_R600_KC0_Z, // register class 'R600_KC0_Z'
16057 : MCK_R600_KC0, // register class 'R600_KC0'
16058 : MCK_R600_Predicate_Bit, // register class 'R600_Predicate_Bit'
16059 : MCK_R600_Predicate, // register class 'R600_Predicate'
16060 : MCK_SReg_32, // register class 'SReg_32'
16061 : MCK_VS_32, // register class 'VS_32'
16062 : MCK_VCCReg, // register class 'VCCReg'
16063 : MCK_EXECReg, // register class 'EXECReg'
16064 : MCK_SReg_64, // register class 'SReg_64'
16065 : MCK_VS_64, // register class 'VS_64'
16066 : MCK_SCCReg, // register class 'SCCReg'
16067 : MCK_M0, // register class 'M0'
16068 : MCK_SGPR_32, // register class 'SGPR_32'
16069 : MCK_VGPR_32, // register class 'VGPR_32,VReg_1'
16070 : MCK_SReg_128, // register class 'SReg_128'
16071 : MCK_SReg_256, // register class 'SReg_256'
16072 : MCK_SReg_512, // register class 'SReg_512'
16073 : MCK_SGPR_64, // register class 'SGPR_64'
16074 : MCK_VReg_128, // register class 'VReg_128'
16075 : MCK_VReg_256, // register class 'VReg_256'
16076 : MCK_VReg_512, // register class 'VReg_512'
16077 : MCK_VReg_64, // register class 'VReg_64'
16078 : MCK_VReg_96, // register class 'VReg_96'
16079 : MCK_Clamp, // user defined class 'ClampMatchClass'
16080 : MCK_DSOffset1, // user defined class 'DSOffset01MatchClass'
16081 : MCK_DSOffsetparseDSOffsetOptional, // user defined class 'DSOffsetGDSMatchClass'
16082 : MCK_DSOffsetparseDSOptionalOps, // user defined class 'DSOffsetMatchClass'
16083 : MCK_GDSparseDSOff01OptionalOps, // user defined class 'GDS01MatchClass'
16084 : MCK_GDSparseDSOptionalOps, // user defined class 'GDSMatchClass'
16085 : MCK_GLC, // user defined class 'GLCMatchClass'
16086 : MCK_Imm, // user defined class 'ImmAsmOperand'
16087 : MCK_RegWithInputMods, // user defined class 'InputModsMatchClass'
16088 : MCK_MubufOffset, // user defined class 'MubufOffsetMatchClass'
16089 : MCK_OMod, // user defined class 'OModMatchClass'
16090 : MCK_SLC, // user defined class 'SLCMatchClass'
16091 : MCK_SWaitCnt, // user defined class 'SWaitMatchClass'
16092 : MCK_SoppBrTarget, // user defined class 'SoppBrTarget'
16093 : MCK_TFE, // user defined class 'TFEMatchClass'
16094 : MCK_SSrc32, // user defined class 'anonymous_590'
16095 : MCK_SSrc64, // user defined class 'anonymous_591'
16096 : MCK_SCSrc32, // user defined class 'anonymous_592'
16097 : MCK_VSrc32, // user defined class 'anonymous_593'
16098 : MCK_VSrc64, // user defined class 'anonymous_594'
16099 : MCK_VCSrc32, // user defined class 'anonymous_595'
16100 : MCK_VCSrc64, // user defined class 'anonymous_596'
16101 : NumMatchClassKinds
16102 : };
16103 :
16104 : }
16105 :
16106 280 : static MatchClassKind matchTokenString(StringRef Name) {
16107 280 : switch (Name.size()) {
16108 : default: break;
16109 : case 1: // 4 strings to match.
16110 24 : switch (Name[0]) {
16111 : default: break;
16112 : case ':': // 1 string to match.
16113 : return MCK__COLON_; // ":"
16114 : case '@': // 1 string to match.
16115 0 : return MCK__64_; // "@"
16116 : case '[': // 1 string to match.
16117 0 : return MCK__91_; // "["
16118 : case ']': // 1 string to match.
16119 0 : return MCK__93_; // "]"
16120 : }
16121 : break;
16122 : case 3: // 2 strings to match.
16123 24 : if (Name[0] != 'g')
16124 : break;
16125 24 : switch (Name[1]) {
16126 : default: break;
16127 : case 'd': // 1 string to match.
16128 24 : if (Name[2] != 's')
16129 : break;
16130 : return MCK_gds; // "gds"
16131 : case 'l': // 1 string to match.
16132 0 : if (Name[2] != 'c')
16133 : break;
16134 : return MCK_glc; // "glc"
16135 : }
16136 : break;
16137 : case 4: // 2 strings to match.
16138 0 : switch (Name[0]) {
16139 : default: break;
16140 : case 'P': // 1 string to match.
16141 0 : if (memcmp(Name.data()+1, "OP:", 3))
16142 : break;
16143 : return MCK_POP_COLON_; // "POP:"
16144 : case 'd': // 1 string to match.
16145 0 : if (memcmp(Name.data()+1, "st1", 3))
16146 : break;
16147 : return MCK_dst1; // "dst1"
16148 : }
16149 : break;
16150 : case 5: // 2 strings to match.
16151 448 : switch (Name[0]) {
16152 : default: break;
16153 : case 'i': // 1 string to match.
16154 96 : if (memcmp(Name.data()+1, "dxen", 4))
16155 : break;
16156 : return MCK_idxen; // "idxen"
16157 : case 'o': // 1 string to match.
16158 128 : if (memcmp(Name.data()+1, "ffen", 4))
16159 : break;
16160 : return MCK_offen; // "offen"
16161 : }
16162 : break;
16163 : case 6: // 1 string to match.
16164 32 : if (memcmp(Name.data()+0, "addr64", 6))
16165 : break;
16166 : return MCK_addr64; // "addr64"
16167 : case 12: // 1 string to match.
16168 0 : if (memcmp(Name.data()+0, "FLAT_SCRATCH", 12))
16169 : break;
16170 : return MCK_FLAT_95_SCRATCH; // "FLAT_SCRATCH"
16171 : }
16172 12 : return InvalidMatchClass;
16173 : }
16174 :
16175 : /// isSubclass - Compute whether \p A is a subclass of \p B.
16176 7434 : static bool isSubclass(MatchClassKind A, MatchClassKind B) {
16177 7434 : if (A == B)
16178 : return true;
16179 :
16180 1540 : switch (A) {
16181 : default:
16182 : return false;
16183 :
16184 : case MCK_R600_TReg32_X:
16185 0 : switch (B) {
16186 : default: return false;
16187 0 : case MCK_R600_TReg32: return true;
16188 0 : case MCK_R600_Reg32: return true;
16189 : }
16190 :
16191 : case MCK_R600_TReg32_Y:
16192 0 : switch (B) {
16193 : default: return false;
16194 0 : case MCK_R600_TReg32: return true;
16195 0 : case MCK_R600_Reg32: return true;
16196 : }
16197 :
16198 : case MCK_R600_TReg32_Z:
16199 0 : switch (B) {
16200 : default: return false;
16201 0 : case MCK_R600_TReg32: return true;
16202 0 : case MCK_R600_Reg32: return true;
16203 : }
16204 :
16205 : case MCK_R600_TReg32_W:
16206 0 : switch (B) {
16207 : default: return false;
16208 0 : case MCK_R600_TReg32: return true;
16209 0 : case MCK_R600_Reg32: return true;
16210 : }
16211 :
16212 : case MCK_R600_TReg32:
16213 0 : return B == MCK_R600_Reg32;
16214 :
16215 : case MCK_R600_Addr:
16216 0 : return B == MCK_R600_Reg32;
16217 :
16218 : case MCK_R600_KC0_W:
16219 0 : switch (B) {
16220 : default: return false;
16221 0 : case MCK_R600_Reg32: return true;
16222 0 : case MCK_R600_KC0: return true;
16223 : }
16224 :
16225 : case MCK_R600_KC1_X:
16226 0 : switch (B) {
16227 : default: return false;
16228 0 : case MCK_R600_KC1: return true;
16229 0 : case MCK_R600_Reg32: return true;
16230 : }
16231 :
16232 : case MCK_R600_KC1_Y:
16233 0 : switch (B) {
16234 : default: return false;
16235 0 : case MCK_R600_KC1: return true;
16236 0 : case MCK_R600_Reg32: return true;
16237 : }
16238 :
16239 : case MCK_R600_KC1_Z:
16240 0 : switch (B) {
16241 : default: return false;
16242 0 : case MCK_R600_KC1: return true;
16243 0 : case MCK_R600_Reg32: return true;
16244 : }
16245 :
16246 : case MCK_R600_KC1_W:
16247 0 : switch (B) {
16248 : default: return false;
16249 0 : case MCK_R600_KC1: return true;
16250 0 : case MCK_R600_Reg32: return true;
16251 : }
16252 :
16253 : case MCK_R600_KC1:
16254 0 : return B == MCK_R600_Reg32;
16255 :
16256 : case MCK_R600_ArrayBase:
16257 0 : return B == MCK_R600_Reg32;
16258 :
16259 : case MCK_Reg34:
16260 0 : switch (B) {
16261 : default: return false;
16262 0 : case MCK_R600_LDS_SRC_REG: return true;
16263 0 : case MCK_R600_Reg32: return true;
16264 : }
16265 :
16266 : case MCK_Reg12:
16267 0 : return B == MCK_R600_Reg128Vertical;
16268 :
16269 : case MCK_Reg14:
16270 0 : return B == MCK_R600_Reg128Vertical;
16271 :
16272 : case MCK_Reg15:
16273 0 : return B == MCK_R600_Reg128Vertical;
16274 :
16275 : case MCK_Reg16:
16276 0 : return B == MCK_R600_Reg128Vertical;
16277 :
16278 : case MCK_Reg18:
16279 0 : return B == MCK_R600_Reg64Vertical;
16280 :
16281 : case MCK_Reg19:
16282 0 : return B == MCK_R600_Reg64Vertical;
16283 :
16284 : case MCK_Reg20:
16285 0 : return B == MCK_R600_Reg64Vertical;
16286 :
16287 : case MCK_Reg21:
16288 0 : return B == MCK_R600_Reg64Vertical;
16289 :
16290 : case MCK_R600_KC0_X:
16291 0 : switch (B) {
16292 : default: return false;
16293 0 : case MCK_R600_Reg32: return true;
16294 0 : case MCK_R600_KC0: return true;
16295 : }
16296 :
16297 : case MCK_R600_KC0_Y:
16298 0 : switch (B) {
16299 : default: return false;
16300 0 : case MCK_R600_Reg32: return true;
16301 0 : case MCK_R600_KC0: return true;
16302 : }
16303 :
16304 : case MCK_R600_KC0_Z:
16305 0 : switch (B) {
16306 : default: return false;
16307 0 : case MCK_R600_Reg32: return true;
16308 0 : case MCK_R600_KC0: return true;
16309 : }
16310 :
16311 : case MCK_R600_KC0:
16312 0 : return B == MCK_R600_Reg32;
16313 :
16314 : case MCK_SReg_32:
16315 0 : return B == MCK_VS_32;
16316 :
16317 : case MCK_VCCReg:
16318 0 : switch (B) {
16319 : default: return false;
16320 0 : case MCK_SReg_64: return true;
16321 0 : case MCK_VS_64: return true;
16322 : }
16323 :
16324 : case MCK_EXECReg:
16325 0 : switch (B) {
16326 : default: return false;
16327 0 : case MCK_SReg_64: return true;
16328 0 : case MCK_VS_64: return true;
16329 : }
16330 :
16331 : case MCK_SReg_64:
16332 0 : return B == MCK_VS_64;
16333 :
16334 : case MCK_M0:
16335 0 : switch (B) {
16336 : default: return false;
16337 0 : case MCK_SReg_32: return true;
16338 0 : case MCK_VS_32: return true;
16339 : }
16340 :
16341 : case MCK_SGPR_32:
16342 266 : switch (B) {
16343 : default: return false;
16344 202 : case MCK_SReg_32: return true;
16345 0 : case MCK_VS_32: return true;
16346 : }
16347 :
16348 : case MCK_VGPR_32:
16349 458 : return B == MCK_VS_32;
16350 :
16351 : case MCK_SGPR_64:
16352 256 : switch (B) {
16353 : default: return false;
16354 176 : case MCK_SReg_64: return true;
16355 0 : case MCK_VS_64: return true;
16356 : }
16357 :
16358 : case MCK_VReg_64:
16359 452 : return B == MCK_VS_64;
16360 : }
16361 : }
16362 :
16363 12418 : static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
16364 12418 : AMDGPUOperand &Operand = (AMDGPUOperand&)GOp;
16365 12418 : if (Kind == InvalidMatchClass)
16366 : return MCTargetAsmParser::Match_InvalidOperand;
16367 :
16368 24820 : if (Operand.isToken())
16369 560 : return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
16370 : MCTargetAsmParser::Match_Success :
16371 280 : MCTargetAsmParser::Match_InvalidOperand;
16372 :
16373 : // 'Clamp' class
16374 12130 : if (Kind == MCK_Clamp) {
16375 62 : if (Operand.isImm())
16376 : return MCTargetAsmParser::Match_Success;
16377 : }
16378 :
16379 : // 'DSOffset1' class
16380 12068 : if (Kind == MCK_DSOffset1) {
16381 64 : if (Operand.isDSOffset01())
16382 : return MCTargetAsmParser::Match_Success;
16383 : }
16384 :
16385 : // 'DSOffsetparseDSOffsetOptional' class
16386 12012 : if (Kind == MCK_DSOffsetparseDSOffsetOptional) {
16387 2 : if (Operand.isDSOffset())
16388 : return MCTargetAsmParser::Match_Success;
16389 : }
16390 :
16391 : // 'DSOffsetparseDSOptionalOps' class
16392 12010 : if (Kind == MCK_DSOffsetparseDSOptionalOps) {
16393 180 : if (Operand.isDSOffset())
16394 : return MCTargetAsmParser::Match_Success;
16395 : }
16396 :
16397 : // 'GDSparseDSOff01OptionalOps' class
16398 11834 : if (Kind == MCK_GDSparseDSOff01OptionalOps) {
16399 28 : if (Operand.isImm())
16400 : return MCTargetAsmParser::Match_Success;
16401 : }
16402 :
16403 : // 'GDSparseDSOptionalOps' class
16404 11806 : if (Kind == MCK_GDSparseDSOptionalOps) {
16405 176 : if (Operand.isImm())
16406 : return MCTargetAsmParser::Match_Success;
16407 : }
16408 :
16409 : // 'GLC' class
16410 11630 : if (Kind == MCK_GLC) {
16411 200 : if (Operand.isImm())
16412 : return MCTargetAsmParser::Match_Success;
16413 : }
16414 :
16415 : // 'Imm' class
16416 11430 : if (Kind == MCK_Imm) {
16417 126 : if (Operand.isImm())
16418 : return MCTargetAsmParser::Match_Success;
16419 : }
16420 :
16421 : // 'RegWithInputMods' class
16422 11304 : if (Kind == MCK_RegWithInputMods) {
16423 500 : if (Operand.isRegWithInputMods())
16424 : return MCTargetAsmParser::Match_Success;
16425 : }
16426 :
16427 : // 'MubufOffset' class
16428 11166 : if (Kind == MCK_MubufOffset) {
16429 200 : if (Operand.isMubufOffset())
16430 : return MCTargetAsmParser::Match_Success;
16431 : }
16432 :
16433 : // 'OMod' class
16434 10966 : if (Kind == MCK_OMod) {
16435 62 : if (Operand.isImm())
16436 : return MCTargetAsmParser::Match_Success;
16437 : }
16438 :
16439 : // 'SLC' class
16440 10904 : if (Kind == MCK_SLC) {
16441 200 : if (Operand.isImm())
16442 : return MCTargetAsmParser::Match_Success;
16443 : }
16444 :
16445 : // 'SWaitCnt' class
16446 10704 : if (Kind == MCK_SWaitCnt) {
16447 32 : if (Operand.isSWaitCnt())
16448 : return MCTargetAsmParser::Match_Success;
16449 : }
16450 :
16451 : // 'SoppBrTarget' class
16452 10688 : if (Kind == MCK_SoppBrTarget) {
16453 14 : if (Operand.isSoppBrTarget())
16454 : return MCTargetAsmParser::Match_Success;
16455 : }
16456 :
16457 : // 'TFE' class
16458 10674 : if (Kind == MCK_TFE) {
16459 200 : if (Operand.isImm())
16460 : return MCTargetAsmParser::Match_Success;
16461 : }
16462 :
16463 : // 'SSrc32' class
16464 10474 : if (Kind == MCK_SSrc32) {
16465 178 : if (Operand.isSSrc32())
16466 : return MCTargetAsmParser::Match_Success;
16467 : }
16468 :
16469 : // 'SSrc64' class
16470 10304 : if (Kind == MCK_SSrc64) {
16471 116 : if (Operand.isSSrc64())
16472 : return MCTargetAsmParser::Match_Success;
16473 : }
16474 :
16475 : // 'SCSrc32' class
16476 10192 : if (Kind == MCK_SCSrc32) {
16477 316 : if (Operand.isSCSrc32())
16478 : return MCTargetAsmParser::Match_Success;
16479 : }
16480 :
16481 : // 'VSrc32' class
16482 9876 : if (Kind == MCK_VSrc32) {
16483 1816 : if (Operand.isVSrc32())
16484 : return MCTargetAsmParser::Match_Success;
16485 : }
16486 :
16487 : // 'VSrc64' class
16488 8106 : if (Kind == MCK_VSrc64) {
16489 162 : if (Operand.isVSrc64())
16490 : return MCTargetAsmParser::Match_Success;
16491 : }
16492 :
16493 : // 'VCSrc32' class
16494 7944 : if (Kind == MCK_VCSrc32) {
16495 644 : if (Operand.isVCSrc32())
16496 : return MCTargetAsmParser::Match_Success;
16497 : }
16498 :
16499 : // 'VCSrc64' class
16500 7316 : if (Kind == MCK_VCSrc64) {
16501 0 : if (Operand.isVCSrc64())
16502 : return MCTargetAsmParser::Match_Success;
16503 : }
16504 :
16505 14632 : if (Operand.isReg()) {
16506 : MatchClassKind OpKind;
16507 7154 : switch (Operand.getReg()) {
16508 : default: OpKind = InvalidMatchClass; break;
16509 : case AMDGPU::T0_X: OpKind = MCK_R600_TReg32_X; break;
16510 : case AMDGPU::T0_Y: OpKind = MCK_R600_TReg32_Y; break;
16511 : case AMDGPU::T0_Z: OpKind = MCK_R600_TReg32_Z; break;
16512 : case AMDGPU::T0_W: OpKind = MCK_R600_TReg32_W; break;
16513 : case AMDGPU::T1_X: OpKind = MCK_R600_TReg32_X; break;
16514 : case AMDGPU::T1_Y: OpKind = MCK_R600_TReg32_Y; break;
16515 : case AMDGPU::T1_Z: OpKind = MCK_R600_TReg32_Z; break;
16516 : case AMDGPU::T1_W: OpKind = MCK_R600_TReg32_W; break;
16517 : case AMDGPU::T2_X: OpKind = MCK_R600_TReg32_X; break;
16518 : case AMDGPU::T2_Y: OpKind = MCK_R600_TReg32_Y; break;
16519 : case AMDGPU::T2_Z: OpKind = MCK_R600_TReg32_Z; break;
16520 : case AMDGPU::T2_W: OpKind = MCK_R600_TReg32_W; break;
16521 : case AMDGPU::T3_X: OpKind = MCK_R600_TReg32_X; break;
16522 : case AMDGPU::T3_Y: OpKind = MCK_R600_TReg32_Y; break;
16523 : case AMDGPU::T3_Z: OpKind = MCK_R600_TReg32_Z; break;
16524 : case AMDGPU::T3_W: OpKind = MCK_R600_TReg32_W; break;
16525 : case AMDGPU::T4_X: OpKind = MCK_R600_TReg32_X; break;
16526 : case AMDGPU::T4_Y: OpKind = MCK_R600_TReg32_Y; break;
16527 : case AMDGPU::T4_Z: OpKind = MCK_R600_TReg32_Z; break;
16528 : case AMDGPU::T4_W: OpKind = MCK_R600_TReg32_W; break;
16529 : case AMDGPU::T5_X: OpKind = MCK_R600_TReg32_X; break;
16530 : case AMDGPU::T5_Y: OpKind = MCK_R600_TReg32_Y; break;
16531 : case AMDGPU::T5_Z: OpKind = MCK_R600_TReg32_Z; break;
16532 : case AMDGPU::T5_W: OpKind = MCK_R600_TReg32_W; break;
16533 : case AMDGPU::T6_X: OpKind = MCK_R600_TReg32_X; break;
16534 : case AMDGPU::T6_Y: OpKind = MCK_R600_TReg32_Y; break;
16535 : case AMDGPU::T6_Z: OpKind = MCK_R600_TReg32_Z; break;
16536 : case AMDGPU::T6_W: OpKind = MCK_R600_TReg32_W; break;
16537 : case AMDGPU::T7_X: OpKind = MCK_R600_TReg32_X; break;
16538 : case AMDGPU::T7_Y: OpKind = MCK_R600_TReg32_Y; break;
16539 : case AMDGPU::T7_Z: OpKind = MCK_R600_TReg32_Z; break;
16540 : case AMDGPU::T7_W: OpKind = MCK_R600_TReg32_W; break;
16541 : case AMDGPU::T8_X: OpKind = MCK_R600_TReg32_X; break;
16542 : case AMDGPU::T8_Y: OpKind = MCK_R600_TReg32_Y; break;
16543 : case AMDGPU::T8_Z: OpKind = MCK_R600_TReg32_Z; break;
16544 : case AMDGPU::T8_W: OpKind = MCK_R600_TReg32_W; break;
16545 : case AMDGPU::T9_X: OpKind = MCK_R600_TReg32_X; break;
16546 : case AMDGPU::T9_Y: OpKind = MCK_R600_TReg32_Y; break;
16547 : case AMDGPU::T9_Z: OpKind = MCK_R600_TReg32_Z; break;
16548 : case AMDGPU::T9_W: OpKind = MCK_R600_TReg32_W; break;
16549 : case AMDGPU::T10_X: OpKind = MCK_R600_TReg32_X; break;
16550 : case AMDGPU::T10_Y: OpKind = MCK_R600_TReg32_Y; break;
16551 : case AMDGPU::T10_Z: OpKind = MCK_R600_TReg32_Z; break;
16552 : case AMDGPU::T10_W: OpKind = MCK_R600_TReg32_W; break;
16553 : case AMDGPU::T11_X: OpKind = MCK_R600_TReg32_X; break;
16554 : case AMDGPU::T11_Y: OpKind = MCK_R600_TReg32_Y; break;
16555 : case AMDGPU::T11_Z: OpKind = MCK_R600_TReg32_Z; break;
16556 : case AMDGPU::T11_W: OpKind = MCK_R600_TReg32_W; break;
16557 : case AMDGPU::T12_X: OpKind = MCK_R600_TReg32_X; break;
16558 : case AMDGPU::T12_Y: OpKind = MCK_R600_TReg32_Y; break;
16559 : case AMDGPU::T12_Z: OpKind = MCK_R600_TReg32_Z; break;
16560 : case AMDGPU::T12_W: OpKind = MCK_R600_TReg32_W; break;
16561 : case AMDGPU::T13_X: OpKind = MCK_R600_TReg32_X; break;
16562 : case AMDGPU::T13_Y: OpKind = MCK_R600_TReg32_Y; break;
16563 : case AMDGPU::T13_Z: OpKind = MCK_R600_TReg32_Z; break;
16564 : case AMDGPU::T13_W: OpKind = MCK_R600_TReg32_W; break;
16565 : case AMDGPU::T14_X: OpKind = MCK_R600_TReg32_X; break;
16566 : case AMDGPU::T14_Y: OpKind = MCK_R600_TReg32_Y; break;
16567 : case AMDGPU::T14_Z: OpKind = MCK_R600_TReg32_Z; break;
16568 : case AMDGPU::T14_W: OpKind = MCK_R600_TReg32_W; break;
16569 : case AMDGPU::T15_X: OpKind = MCK_R600_TReg32_X; break;
16570 : case AMDGPU::T15_Y: OpKind = MCK_R600_TReg32_Y; break;
16571 : case AMDGPU::T15_Z: OpKind = MCK_R600_TReg32_Z; break;
16572 : case AMDGPU::T15_W: OpKind = MCK_R600_TReg32_W; break;
16573 : case AMDGPU::T16_X: OpKind = MCK_R600_TReg32_X; break;
16574 : case AMDGPU::T16_Y: OpKind = MCK_R600_TReg32_Y; break;
16575 : case AMDGPU::T16_Z: OpKind = MCK_R600_TReg32_Z; break;
16576 : case AMDGPU::T16_W: OpKind = MCK_R600_TReg32_W; break;
16577 : case AMDGPU::T17_X: OpKind = MCK_R600_TReg32_X; break;
16578 : case AMDGPU::T17_Y: OpKind = MCK_R600_TReg32_Y; break;
16579 : case AMDGPU::T17_Z: OpKind = MCK_R600_TReg32_Z; break;
16580 : case AMDGPU::T17_W: OpKind = MCK_R600_TReg32_W; break;
16581 : case AMDGPU::T18_X: OpKind = MCK_R600_TReg32_X; break;
16582 : case AMDGPU::T18_Y: OpKind = MCK_R600_TReg32_Y; break;
16583 : case AMDGPU::T18_Z: OpKind = MCK_R600_TReg32_Z; break;
16584 : case AMDGPU::T18_W: OpKind = MCK_R600_TReg32_W; break;
16585 : case AMDGPU::T19_X: OpKind = MCK_R600_TReg32_X; break;
16586 : case AMDGPU::T19_Y: OpKind = MCK_R600_TReg32_Y; break;
16587 : case AMDGPU::T19_Z: OpKind = MCK_R600_TReg32_Z; break;
16588 : case AMDGPU::T19_W: OpKind = MCK_R600_TReg32_W; break;
16589 : case AMDGPU::T20_X: OpKind = MCK_R600_TReg32_X; break;
16590 : case AMDGPU::T20_Y: OpKind = MCK_R600_TReg32_Y; break;
16591 : case AMDGPU::T20_Z: OpKind = MCK_R600_TReg32_Z; break;
16592 : case AMDGPU::T20_W: OpKind = MCK_R600_TReg32_W; break;
16593 : case AMDGPU::T21_X: OpKind = MCK_R600_TReg32_X; break;
16594 : case AMDGPU::T21_Y: OpKind = MCK_R600_TReg32_Y; break;
16595 : case AMDGPU::T21_Z: OpKind = MCK_R600_TReg32_Z; break;
16596 : case AMDGPU::T21_W: OpKind = MCK_R600_TReg32_W; break;
16597 : case AMDGPU::T22_X: OpKind = MCK_R600_TReg32_X; break;
16598 : case AMDGPU::T22_Y: OpKind = MCK_R600_TReg32_Y; break;
16599 : case AMDGPU::T22_Z: OpKind = MCK_R600_TReg32_Z; break;
16600 : case AMDGPU::T22_W: OpKind = MCK_R600_TReg32_W; break;
16601 : case AMDGPU::T23_X: OpKind = MCK_R600_TReg32_X; break;
16602 : case AMDGPU::T23_Y: OpKind = MCK_R600_TReg32_Y; break;
16603 : case AMDGPU::T23_Z: OpKind = MCK_R600_TReg32_Z; break;
16604 : case AMDGPU::T23_W: OpKind = MCK_R600_TReg32_W; break;
16605 : case AMDGPU::T24_X: OpKind = MCK_R600_TReg32_X; break;
16606 : case AMDGPU::T24_Y: OpKind = MCK_R600_TReg32_Y; break;
16607 : case AMDGPU::T24_Z: OpKind = MCK_R600_TReg32_Z; break;
16608 : case AMDGPU::T24_W: OpKind = MCK_R600_TReg32_W; break;
16609 : case AMDGPU::T25_X: OpKind = MCK_R600_TReg32_X; break;
16610 : case AMDGPU::T25_Y: OpKind = MCK_R600_TReg32_Y; break;
16611 : case AMDGPU::T25_Z: OpKind = MCK_R600_TReg32_Z; break;
16612 : case AMDGPU::T25_W: OpKind = MCK_R600_TReg32_W; break;
16613 : case AMDGPU::T26_X: OpKind = MCK_R600_TReg32_X; break;
16614 : case AMDGPU::T26_Y: OpKind = MCK_R600_TReg32_Y; break;
16615 : case AMDGPU::T26_Z: OpKind = MCK_R600_TReg32_Z; break;
16616 : case AMDGPU::T26_W: OpKind = MCK_R600_TReg32_W; break;
16617 : case AMDGPU::T27_X: OpKind = MCK_R600_TReg32_X; break;
16618 : case AMDGPU::T27_Y: OpKind = MCK_R600_TReg32_Y; break;
16619 : case AMDGPU::T27_Z: OpKind = MCK_R600_TReg32_Z; break;
16620 : case AMDGPU::T27_W: OpKind = MCK_R600_TReg32_W; break;
16621 : case AMDGPU::T28_X: OpKind = MCK_R600_TReg32_X; break;
16622 : case AMDGPU::T28_Y: OpKind = MCK_R600_TReg32_Y; break;
16623 : case AMDGPU::T28_Z: OpKind = MCK_R600_TReg32_Z; break;
16624 : case AMDGPU::T28_W: OpKind = MCK_R600_TReg32_W; break;
16625 : case AMDGPU::T29_X: OpKind = MCK_R600_TReg32_X; break;
16626 : case AMDGPU::T29_Y: OpKind = MCK_R600_TReg32_Y; break;
16627 : case AMDGPU::T29_Z: OpKind = MCK_R600_TReg32_Z; break;
16628 : case AMDGPU::T29_W: OpKind = MCK_R600_TReg32_W; break;
16629 : case AMDGPU::T30_X: OpKind = MCK_R600_TReg32_X; break;
16630 : case AMDGPU::T30_Y: OpKind = MCK_R600_TReg32_Y; break;
16631 : case AMDGPU::T30_Z: OpKind = MCK_R600_TReg32_Z; break;
16632 : case AMDGPU::T30_W: OpKind = MCK_R600_TReg32_W; break;
16633 : case AMDGPU::T31_X: OpKind = MCK_R600_TReg32_X; break;
16634 : case AMDGPU::T31_Y: OpKind = MCK_R600_TReg32_Y; break;
16635 : case AMDGPU::T31_Z: OpKind = MCK_R600_TReg32_Z; break;
16636 : case AMDGPU::T31_W: OpKind = MCK_R600_TReg32_W; break;
16637 : case AMDGPU::T32_X: OpKind = MCK_R600_TReg32_X; break;
16638 : case AMDGPU::T32_Y: OpKind = MCK_R600_TReg32_Y; break;
16639 : case AMDGPU::T32_Z: OpKind = MCK_R600_TReg32_Z; break;
16640 : case AMDGPU::T32_W: OpKind = MCK_R600_TReg32_W; break;
16641 : case AMDGPU::T33_X: OpKind = MCK_R600_TReg32_X; break;
16642 : case AMDGPU::T33_Y: OpKind = MCK_R600_TReg32_Y; break;
16643 : case AMDGPU::T33_Z: OpKind = MCK_R600_TReg32_Z; break;
16644 : case AMDGPU::T33_W: OpKind = MCK_R600_TReg32_W; break;
16645 : case AMDGPU::T34_X: OpKind = MCK_R600_TReg32_X; break;
16646 : case AMDGPU::T34_Y: OpKind = MCK_R600_TReg32_Y; break;
16647 : case AMDGPU::T34_Z: OpKind = MCK_R600_TReg32_Z; break;
16648 : case AMDGPU::T34_W: OpKind = MCK_R600_TReg32_W; break;
16649 : case AMDGPU::T35_X: OpKind = MCK_R600_TReg32_X; break;
16650 : case AMDGPU::T35_Y: OpKind = MCK_R600_TReg32_Y; break;
16651 : case AMDGPU::T35_Z: OpKind = MCK_R600_TReg32_Z; break;
16652 : case AMDGPU::T35_W: OpKind = MCK_R600_TReg32_W; break;
16653 : case AMDGPU::T36_X: OpKind = MCK_R600_TReg32_X; break;
16654 : case AMDGPU::T36_Y: OpKind = MCK_R600_TReg32_Y; break;
16655 : case AMDGPU::T36_Z: OpKind = MCK_R600_TReg32_Z; break;
16656 : case AMDGPU::T36_W: OpKind = MCK_R600_TReg32_W; break;
16657 : case AMDGPU::T37_X: OpKind = MCK_R600_TReg32_X; break;
16658 : case AMDGPU::T37_Y: OpKind = MCK_R600_TReg32_Y; break;
16659 : case AMDGPU::T37_Z: OpKind = MCK_R600_TReg32_Z; break;
16660 : case AMDGPU::T37_W: OpKind = MCK_R600_TReg32_W; break;
16661 : case AMDGPU::T38_X: OpKind = MCK_R600_TReg32_X; break;
16662 : case AMDGPU::T38_Y: OpKind = MCK_R600_TReg32_Y; break;
16663 : case AMDGPU::T38_Z: OpKind = MCK_R600_TReg32_Z; break;
16664 : case AMDGPU::T38_W: OpKind = MCK_R600_TReg32_W; break;
16665 : case AMDGPU::T39_X: OpKind = MCK_R600_TReg32_X; break;
16666 : case AMDGPU::T39_Y: OpKind = MCK_R600_TReg32_Y; break;
16667 : case AMDGPU::T39_Z: OpKind = MCK_R600_TReg32_Z; break;
16668 : case AMDGPU::T39_W: OpKind = MCK_R600_TReg32_W; break;
16669 : case AMDGPU::T40_X: OpKind = MCK_R600_TReg32_X; break;
16670 : case AMDGPU::T40_Y: OpKind = MCK_R600_TReg32_Y; break;
16671 : case AMDGPU::T40_Z: OpKind = MCK_R600_TReg32_Z; break;
16672 : case AMDGPU::T40_W: OpKind = MCK_R600_TReg32_W; break;
16673 : case AMDGPU::T41_X: OpKind = MCK_R600_TReg32_X; break;
16674 : case AMDGPU::T41_Y: OpKind = MCK_R600_TReg32_Y; break;
16675 : case AMDGPU::T41_Z: OpKind = MCK_R600_TReg32_Z; break;
16676 : case AMDGPU::T41_W: OpKind = MCK_R600_TReg32_W; break;
16677 : case AMDGPU::T42_X: OpKind = MCK_R600_TReg32_X; break;
16678 : case AMDGPU::T42_Y: OpKind = MCK_R600_TReg32_Y; break;
16679 : case AMDGPU::T42_Z: OpKind = MCK_R600_TReg32_Z; break;
16680 : case AMDGPU::T42_W: OpKind = MCK_R600_TReg32_W; break;
16681 : case AMDGPU::T43_X: OpKind = MCK_R600_TReg32_X; break;
16682 : case AMDGPU::T43_Y: OpKind = MCK_R600_TReg32_Y; break;
16683 : case AMDGPU::T43_Z: OpKind = MCK_R600_TReg32_Z; break;
16684 : case AMDGPU::T43_W: OpKind = MCK_R600_TReg32_W; break;
16685 : case AMDGPU::T44_X: OpKind = MCK_R600_TReg32_X; break;
16686 : case AMDGPU::T44_Y: OpKind = MCK_R600_TReg32_Y; break;
16687 : case AMDGPU::T44_Z: OpKind = MCK_R600_TReg32_Z; break;
16688 : case AMDGPU::T44_W: OpKind = MCK_R600_TReg32_W; break;
16689 : case AMDGPU::T45_X: OpKind = MCK_R600_TReg32_X; break;
16690 : case AMDGPU::T45_Y: OpKind = MCK_R600_TReg32_Y; break;
16691 : case AMDGPU::T45_Z: OpKind = MCK_R600_TReg32_Z; break;
16692 : case AMDGPU::T45_W: OpKind = MCK_R600_TReg32_W; break;
16693 : case AMDGPU::T46_X: OpKind = MCK_R600_TReg32_X; break;
16694 : case AMDGPU::T46_Y: OpKind = MCK_R600_TReg32_Y; break;
16695 : case AMDGPU::T46_Z: OpKind = MCK_R600_TReg32_Z; break;
16696 : case AMDGPU::T46_W: OpKind = MCK_R600_TReg32_W; break;
16697 : case AMDGPU::T47_X: OpKind = MCK_R600_TReg32_X; break;
16698 : case AMDGPU::T47_Y: OpKind = MCK_R600_TReg32_Y; break;
16699 : case AMDGPU::T47_Z: OpKind = MCK_R600_TReg32_Z; break;
16700 : case AMDGPU::T47_W: OpKind = MCK_R600_TReg32_W; break;
16701 : case AMDGPU::T48_X: OpKind = MCK_R600_TReg32_X; break;
16702 : case AMDGPU::T48_Y: OpKind = MCK_R600_TReg32_Y; break;
16703 : case AMDGPU::T48_Z: OpKind = MCK_R600_TReg32_Z; break;
16704 : case AMDGPU::T48_W: OpKind = MCK_R600_TReg32_W; break;
16705 : case AMDGPU::T49_X: OpKind = MCK_R600_TReg32_X; break;
16706 : case AMDGPU::T49_Y: OpKind = MCK_R600_TReg32_Y; break;
16707 : case AMDGPU::T49_Z: OpKind = MCK_R600_TReg32_Z; break;
16708 : case AMDGPU::T49_W: OpKind = MCK_R600_TReg32_W; break;
16709 : case AMDGPU::T50_X: OpKind = MCK_R600_TReg32_X; break;
16710 : case AMDGPU::T50_Y: OpKind = MCK_R600_TReg32_Y; break;
16711 : case AMDGPU::T50_Z: OpKind = MCK_R600_TReg32_Z; break;
16712 : case AMDGPU::T50_W: OpKind = MCK_R600_TReg32_W; break;
16713 : case AMDGPU::T51_X: OpKind = MCK_R600_TReg32_X; break;
16714 : case AMDGPU::T51_Y: OpKind = MCK_R600_TReg32_Y; break;
16715 : case AMDGPU::T51_Z: OpKind = MCK_R600_TReg32_Z; break;
16716 : case AMDGPU::T51_W: OpKind = MCK_R600_TReg32_W; break;
16717 : case AMDGPU::T52_X: OpKind = MCK_R600_TReg32_X; break;
16718 : case AMDGPU::T52_Y: OpKind = MCK_R600_TReg32_Y; break;
16719 : case AMDGPU::T52_Z: OpKind = MCK_R600_TReg32_Z; break;
16720 : case AMDGPU::T52_W: OpKind = MCK_R600_TReg32_W; break;
16721 : case AMDGPU::T53_X: OpKind = MCK_R600_TReg32_X; break;
16722 : case AMDGPU::T53_Y: OpKind = MCK_R600_TReg32_Y; break;
16723 : case AMDGPU::T53_Z: OpKind = MCK_R600_TReg32_Z; break;
16724 : case AMDGPU::T53_W: OpKind = MCK_R600_TReg32_W; break;
16725 : case AMDGPU::T54_X: OpKind = MCK_R600_TReg32_X; break;
16726 : case AMDGPU::T54_Y: OpKind = MCK_R600_TReg32_Y; break;
16727 : case AMDGPU::T54_Z: OpKind = MCK_R600_TReg32_Z; break;
16728 : case AMDGPU::T54_W: OpKind = MCK_R600_TReg32_W; break;
16729 : case AMDGPU::T55_X: OpKind = MCK_R600_TReg32_X; break;
16730 : case AMDGPU::T55_Y: OpKind = MCK_R600_TReg32_Y; break;
16731 : case AMDGPU::T55_Z: OpKind = MCK_R600_TReg32_Z; break;
16732 : case AMDGPU::T55_W: OpKind = MCK_R600_TReg32_W; break;
16733 : case AMDGPU::T56_X: OpKind = MCK_R600_TReg32_X; break;
16734 : case AMDGPU::T56_Y: OpKind = MCK_R600_TReg32_Y; break;
16735 : case AMDGPU::T56_Z: OpKind = MCK_R600_TReg32_Z; break;
16736 : case AMDGPU::T56_W: OpKind = MCK_R600_TReg32_W; break;
16737 : case AMDGPU::T57_X: OpKind = MCK_R600_TReg32_X; break;
16738 : case AMDGPU::T57_Y: OpKind = MCK_R600_TReg32_Y; break;
16739 : case AMDGPU::T57_Z: OpKind = MCK_R600_TReg32_Z; break;
16740 : case AMDGPU::T57_W: OpKind = MCK_R600_TReg32_W; break;
16741 : case AMDGPU::T58_X: OpKind = MCK_R600_TReg32_X; break;
16742 : case AMDGPU::T58_Y: OpKind = MCK_R600_TReg32_Y; break;
16743 : case AMDGPU::T58_Z: OpKind = MCK_R600_TReg32_Z; break;
16744 : case AMDGPU::T58_W: OpKind = MCK_R600_TReg32_W; break;
16745 : case AMDGPU::T59_X: OpKind = MCK_R600_TReg32_X; break;
16746 : case AMDGPU::T59_Y: OpKind = MCK_R600_TReg32_Y; break;
16747 : case AMDGPU::T59_Z: OpKind = MCK_R600_TReg32_Z; break;
16748 : case AMDGPU::T59_W: OpKind = MCK_R600_TReg32_W; break;
16749 : case AMDGPU::T60_X: OpKind = MCK_R600_TReg32_X; break;
16750 : case AMDGPU::T60_Y: OpKind = MCK_R600_TReg32_Y; break;
16751 : case AMDGPU::T60_Z: OpKind = MCK_R600_TReg32_Z; break;
16752 : case AMDGPU::T60_W: OpKind = MCK_R600_TReg32_W; break;
16753 : case AMDGPU::T61_X: OpKind = MCK_R600_TReg32_X; break;
16754 : case AMDGPU::T61_Y: OpKind = MCK_R600_TReg32_Y; break;
16755 : case AMDGPU::T61_Z: OpKind = MCK_R600_TReg32_Z; break;
16756 : case AMDGPU::T61_W: OpKind = MCK_R600_TReg32_W; break;
16757 : case AMDGPU::T62_X: OpKind = MCK_R600_TReg32_X; break;
16758 : case AMDGPU::T62_Y: OpKind = MCK_R600_TReg32_Y; break;
16759 : case AMDGPU::T62_Z: OpKind = MCK_R600_TReg32_Z; break;
16760 : case AMDGPU::T62_W: OpKind = MCK_R600_TReg32_W; break;
16761 : case AMDGPU::T63_X: OpKind = MCK_R600_TReg32_X; break;
16762 : case AMDGPU::T63_Y: OpKind = MCK_R600_TReg32_Y; break;
16763 : case AMDGPU::T63_Z: OpKind = MCK_R600_TReg32_Z; break;
16764 : case AMDGPU::T63_W: OpKind = MCK_R600_TReg32_W; break;
16765 : case AMDGPU::T64_X: OpKind = MCK_R600_TReg32_X; break;
16766 : case AMDGPU::T64_Y: OpKind = MCK_R600_TReg32_Y; break;
16767 : case AMDGPU::T64_Z: OpKind = MCK_R600_TReg32_Z; break;
16768 : case AMDGPU::T64_W: OpKind = MCK_R600_TReg32_W; break;
16769 : case AMDGPU::T65_X: OpKind = MCK_R600_TReg32_X; break;
16770 : case AMDGPU::T65_Y: OpKind = MCK_R600_TReg32_Y; break;
16771 : case AMDGPU::T65_Z: OpKind = MCK_R600_TReg32_Z; break;
16772 : case AMDGPU::T65_W: OpKind = MCK_R600_TReg32_W; break;
16773 : case AMDGPU::T66_X: OpKind = MCK_R600_TReg32_X; break;
16774 : case AMDGPU::T66_Y: OpKind = MCK_R600_TReg32_Y; break;
16775 : case AMDGPU::T66_Z: OpKind = MCK_R600_TReg32_Z; break;
16776 : case AMDGPU::T66_W: OpKind = MCK_R600_TReg32_W; break;
16777 : case AMDGPU::T67_X: OpKind = MCK_R600_TReg32_X; break;
16778 : case AMDGPU::T67_Y: OpKind = MCK_R600_TReg32_Y; break;
16779 : case AMDGPU::T67_Z: OpKind = MCK_R600_TReg32_Z; break;
16780 : case AMDGPU::T67_W: OpKind = MCK_R600_TReg32_W; break;
16781 : case AMDGPU::T68_X: OpKind = MCK_R600_TReg32_X; break;
16782 : case AMDGPU::T68_Y: OpKind = MCK_R600_TReg32_Y; break;
16783 : case AMDGPU::T68_Z: OpKind = MCK_R600_TReg32_Z; break;
16784 : case AMDGPU::T68_W: OpKind = MCK_R600_TReg32_W; break;
16785 : case AMDGPU::T69_X: OpKind = MCK_R600_TReg32_X; break;
16786 : case AMDGPU::T69_Y: OpKind = MCK_R600_TReg32_Y; break;
16787 : case AMDGPU::T69_Z: OpKind = MCK_R600_TReg32_Z; break;
16788 : case AMDGPU::T69_W: OpKind = MCK_R600_TReg32_W; break;
16789 : case AMDGPU::T70_X: OpKind = MCK_R600_TReg32_X; break;
16790 : case AMDGPU::T70_Y: OpKind = MCK_R600_TReg32_Y; break;
16791 : case AMDGPU::T70_Z: OpKind = MCK_R600_TReg32_Z; break;
16792 : case AMDGPU::T70_W: OpKind = MCK_R600_TReg32_W; break;
16793 : case AMDGPU::T71_X: OpKind = MCK_R600_TReg32_X; break;
16794 : case AMDGPU::T71_Y: OpKind = MCK_R600_TReg32_Y; break;
16795 : case AMDGPU::T71_Z: OpKind = MCK_R600_TReg32_Z; break;
16796 : case AMDGPU::T71_W: OpKind = MCK_R600_TReg32_W; break;
16797 : case AMDGPU::T72_X: OpKind = MCK_R600_TReg32_X; break;
16798 : case AMDGPU::T72_Y: OpKind = MCK_R600_TReg32_Y; break;
16799 : case AMDGPU::T72_Z: OpKind = MCK_R600_TReg32_Z; break;
16800 : case AMDGPU::T72_W: OpKind = MCK_R600_TReg32_W; break;
16801 : case AMDGPU::T73_X: OpKind = MCK_R600_TReg32_X; break;
16802 : case AMDGPU::T73_Y: OpKind = MCK_R600_TReg32_Y; break;
16803 : case AMDGPU::T73_Z: OpKind = MCK_R600_TReg32_Z; break;
16804 : case AMDGPU::T73_W: OpKind = MCK_R600_TReg32_W; break;
16805 : case AMDGPU::T74_X: OpKind = MCK_R600_TReg32_X; break;
16806 : case AMDGPU::T74_Y: OpKind = MCK_R600_TReg32_Y; break;
16807 : case AMDGPU::T74_Z: OpKind = MCK_R600_TReg32_Z; break;
16808 : case AMDGPU::T74_W: OpKind = MCK_R600_TReg32_W; break;
16809 : case AMDGPU::T75_X: OpKind = MCK_R600_TReg32_X; break;
16810 : case AMDGPU::T75_Y: OpKind = MCK_R600_TReg32_Y; break;
16811 : case AMDGPU::T75_Z: OpKind = MCK_R600_TReg32_Z; break;
16812 : case AMDGPU::T75_W: OpKind = MCK_R600_TReg32_W; break;
16813 : case AMDGPU::T76_X: OpKind = MCK_R600_TReg32_X; break;
16814 : case AMDGPU::T76_Y: OpKind = MCK_R600_TReg32_Y; break;
16815 : case AMDGPU::T76_Z: OpKind = MCK_R600_TReg32_Z; break;
16816 : case AMDGPU::T76_W: OpKind = MCK_R600_TReg32_W; break;
16817 : case AMDGPU::T77_X: OpKind = MCK_R600_TReg32_X; break;
16818 : case AMDGPU::T77_Y: OpKind = MCK_R600_TReg32_Y; break;
16819 : case AMDGPU::T77_Z: OpKind = MCK_R600_TReg32_Z; break;
16820 : case AMDGPU::T77_W: OpKind = MCK_R600_TReg32_W; break;
16821 : case AMDGPU::T78_X: OpKind = MCK_R600_TReg32_X; break;
16822 : case AMDGPU::T78_Y: OpKind = MCK_R600_TReg32_Y; break;
16823 : case AMDGPU::T78_Z: OpKind = MCK_R600_TReg32_Z; break;
16824 : case AMDGPU::T78_W: OpKind = MCK_R600_TReg32_W; break;
16825 : case AMDGPU::T79_X: OpKind = MCK_R600_TReg32_X; break;
16826 : case AMDGPU::T79_Y: OpKind = MCK_R600_TReg32_Y; break;
16827 : case AMDGPU::T79_Z: OpKind = MCK_R600_TReg32_Z; break;
16828 : case AMDGPU::T79_W: OpKind = MCK_R600_TReg32_W; break;
16829 : case AMDGPU::T80_X: OpKind = MCK_R600_TReg32_X; break;
16830 : case AMDGPU::T80_Y: OpKind = MCK_R600_TReg32_Y; break;
16831 : case AMDGPU::T80_Z: OpKind = MCK_R600_TReg32_Z; break;
16832 : case AMDGPU::T80_W: OpKind = MCK_R600_TReg32_W; break;
16833 : case AMDGPU::T81_X: OpKind = MCK_R600_TReg32_X; break;
16834 : case AMDGPU::T81_Y: OpKind = MCK_R600_TReg32_Y; break;
16835 : case AMDGPU::T81_Z: OpKind = MCK_R600_TReg32_Z; break;
16836 : case AMDGPU::T81_W: OpKind = MCK_R600_TReg32_W; break;
16837 : case AMDGPU::T82_X: OpKind = MCK_R600_TReg32_X; break;
16838 : case AMDGPU::T82_Y: OpKind = MCK_R600_TReg32_Y; break;
16839 : case AMDGPU::T82_Z: OpKind = MCK_R600_TReg32_Z; break;
16840 : case AMDGPU::T82_W: OpKind = MCK_R600_TReg32_W; break;
16841 : case AMDGPU::T83_X: OpKind = MCK_R600_TReg32_X; break;
16842 : case AMDGPU::T83_Y: OpKind = MCK_R600_TReg32_Y; break;
16843 : case AMDGPU::T83_Z: OpKind = MCK_R600_TReg32_Z; break;
16844 : case AMDGPU::T83_W: OpKind = MCK_R600_TReg32_W; break;
16845 : case AMDGPU::T84_X: OpKind = MCK_R600_TReg32_X; break;
16846 : case AMDGPU::T84_Y: OpKind = MCK_R600_TReg32_Y; break;
16847 : case AMDGPU::T84_Z: OpKind = MCK_R600_TReg32_Z; break;
16848 : case AMDGPU::T84_W: OpKind = MCK_R600_TReg32_W; break;
16849 : case AMDGPU::T85_X: OpKind = MCK_R600_TReg32_X; break;
16850 : case AMDGPU::T85_Y: OpKind = MCK_R600_TReg32_Y; break;
16851 : case AMDGPU::T85_Z: OpKind = MCK_R600_TReg32_Z; break;
16852 : case AMDGPU::T85_W: OpKind = MCK_R600_TReg32_W; break;
16853 : case AMDGPU::T86_X: OpKind = MCK_R600_TReg32_X; break;
16854 : case AMDGPU::T86_Y: OpKind = MCK_R600_TReg32_Y; break;
16855 : case AMDGPU::T86_Z: OpKind = MCK_R600_TReg32_Z; break;
16856 : case AMDGPU::T86_W: OpKind = MCK_R600_TReg32_W; break;
16857 : case AMDGPU::T87_X: OpKind = MCK_R600_TReg32_X; break;
16858 : case AMDGPU::T87_Y: OpKind = MCK_R600_TReg32_Y; break;
16859 : case AMDGPU::T87_Z: OpKind = MCK_R600_TReg32_Z; break;
16860 : case AMDGPU::T87_W: OpKind = MCK_R600_TReg32_W; break;
16861 : case AMDGPU::T88_X: OpKind = MCK_R600_TReg32_X; break;
16862 : case AMDGPU::T88_Y: OpKind = MCK_R600_TReg32_Y; break;
16863 : case AMDGPU::T88_Z: OpKind = MCK_R600_TReg32_Z; break;
16864 : case AMDGPU::T88_W: OpKind = MCK_R600_TReg32_W; break;
16865 : case AMDGPU::T89_X: OpKind = MCK_R600_TReg32_X; break;
16866 : case AMDGPU::T89_Y: OpKind = MCK_R600_TReg32_Y; break;
16867 : case AMDGPU::T89_Z: OpKind = MCK_R600_TReg32_Z; break;
16868 : case AMDGPU::T89_W: OpKind = MCK_R600_TReg32_W; break;
16869 : case AMDGPU::T90_X: OpKind = MCK_R600_TReg32_X; break;
16870 : case AMDGPU::T90_Y: OpKind = MCK_R600_TReg32_Y; break;
16871 : case AMDGPU::T90_Z: OpKind = MCK_R600_TReg32_Z; break;
16872 : case AMDGPU::T90_W: OpKind = MCK_R600_TReg32_W; break;
16873 : case AMDGPU::T91_X: OpKind = MCK_R600_TReg32_X; break;
16874 : case AMDGPU::T91_Y: OpKind = MCK_R600_TReg32_Y; break;
16875 : case AMDGPU::T91_Z: OpKind = MCK_R600_TReg32_Z; break;
16876 : case AMDGPU::T91_W: OpKind = MCK_R600_TReg32_W; break;
16877 : case AMDGPU::T92_X: OpKind = MCK_R600_TReg32_X; break;
16878 : case AMDGPU::T92_Y: OpKind = MCK_R600_TReg32_Y; break;
16879 : case AMDGPU::T92_Z: OpKind = MCK_R600_TReg32_Z; break;
16880 : case AMDGPU::T92_W: OpKind = MCK_R600_TReg32_W; break;
16881 : case AMDGPU::T93_X: OpKind = MCK_R600_TReg32_X; break;
16882 : case AMDGPU::T93_Y: OpKind = MCK_R600_TReg32_Y; break;
16883 : case AMDGPU::T93_Z: OpKind = MCK_R600_TReg32_Z; break;
16884 : case AMDGPU::T93_W: OpKind = MCK_R600_TReg32_W; break;
16885 : case AMDGPU::T94_X: OpKind = MCK_R600_TReg32_X; break;
16886 : case AMDGPU::T94_Y: OpKind = MCK_R600_TReg32_Y; break;
16887 : case AMDGPU::T94_Z: OpKind = MCK_R600_TReg32_Z; break;
16888 : case AMDGPU::T94_W: OpKind = MCK_R600_TReg32_W; break;
16889 : case AMDGPU::T95_X: OpKind = MCK_R600_TReg32_X; break;
16890 : case AMDGPU::T95_Y: OpKind = MCK_R600_TReg32_Y; break;
16891 : case AMDGPU::T95_Z: OpKind = MCK_R600_TReg32_Z; break;
16892 : case AMDGPU::T95_W: OpKind = MCK_R600_TReg32_W; break;
16893 : case AMDGPU::T96_X: OpKind = MCK_R600_TReg32_X; break;
16894 : case AMDGPU::T96_Y: OpKind = MCK_R600_TReg32_Y; break;
16895 : case AMDGPU::T96_Z: OpKind = MCK_R600_TReg32_Z; break;
16896 : case AMDGPU::T96_W: OpKind = MCK_R600_TReg32_W; break;
16897 : case AMDGPU::T97_X: OpKind = MCK_R600_TReg32_X; break;
16898 : case AMDGPU::T97_Y: OpKind = MCK_R600_TReg32_Y; break;
16899 : case AMDGPU::T97_Z: OpKind = MCK_R600_TReg32_Z; break;
16900 : case AMDGPU::T97_W: OpKind = MCK_R600_TReg32_W; break;
16901 : case AMDGPU::T98_X: OpKind = MCK_R600_TReg32_X; break;
16902 : case AMDGPU::T98_Y: OpKind = MCK_R600_TReg32_Y; break;
16903 : case AMDGPU::T98_Z: OpKind = MCK_R600_TReg32_Z; break;
16904 : case AMDGPU::T98_W: OpKind = MCK_R600_TReg32_W; break;
16905 : case AMDGPU::T99_X: OpKind = MCK_R600_TReg32_X; break;
16906 : case AMDGPU::T99_Y: OpKind = MCK_R600_TReg32_Y; break;
16907 : case AMDGPU::T99_Z: OpKind = MCK_R600_TReg32_Z; break;
16908 : case AMDGPU::T99_W: OpKind = MCK_R600_TReg32_W; break;
16909 : case AMDGPU::T100_X: OpKind = MCK_R600_TReg32_X; break;
16910 : case AMDGPU::T100_Y: OpKind = MCK_R600_TReg32_Y; break;
16911 : case AMDGPU::T100_Z: OpKind = MCK_R600_TReg32_Z; break;
16912 : case AMDGPU::T100_W: OpKind = MCK_R600_TReg32_W; break;
16913 : case AMDGPU::T101_X: OpKind = MCK_R600_TReg32_X; break;
16914 : case AMDGPU::T101_Y: OpKind = MCK_R600_TReg32_Y; break;
16915 : case AMDGPU::T101_Z: OpKind = MCK_R600_TReg32_Z; break;
16916 : case AMDGPU::T101_W: OpKind = MCK_R600_TReg32_W; break;
16917 : case AMDGPU::T102_X: OpKind = MCK_R600_TReg32_X; break;
16918 : case AMDGPU::T102_Y: OpKind = MCK_R600_TReg32_Y; break;
16919 : case AMDGPU::T102_Z: OpKind = MCK_R600_TReg32_Z; break;
16920 : case AMDGPU::T102_W: OpKind = MCK_R600_TReg32_W; break;
16921 : case AMDGPU::T103_X: OpKind = MCK_R600_TReg32_X; break;
16922 : case AMDGPU::T103_Y: OpKind = MCK_R600_TReg32_Y; break;
16923 : case AMDGPU::T103_Z: OpKind = MCK_R600_TReg32_Z; break;
16924 : case AMDGPU::T103_W: OpKind = MCK_R600_TReg32_W; break;
16925 : case AMDGPU::T104_X: OpKind = MCK_R600_TReg32_X; break;
16926 : case AMDGPU::T104_Y: OpKind = MCK_R600_TReg32_Y; break;
16927 : case AMDGPU::T104_Z: OpKind = MCK_R600_TReg32_Z; break;
16928 : case AMDGPU::T104_W: OpKind = MCK_R600_TReg32_W; break;
16929 : case AMDGPU::T105_X: OpKind = MCK_R600_TReg32_X; break;
16930 : case AMDGPU::T105_Y: OpKind = MCK_R600_TReg32_Y; break;
16931 : case AMDGPU::T105_Z: OpKind = MCK_R600_TReg32_Z; break;
16932 : case AMDGPU::T105_W: OpKind = MCK_R600_TReg32_W; break;
16933 : case AMDGPU::T106_X: OpKind = MCK_R600_TReg32_X; break;
16934 : case AMDGPU::T106_Y: OpKind = MCK_R600_TReg32_Y; break;
16935 : case AMDGPU::T106_Z: OpKind = MCK_R600_TReg32_Z; break;
16936 : case AMDGPU::T106_W: OpKind = MCK_R600_TReg32_W; break;
16937 : case AMDGPU::T107_X: OpKind = MCK_R600_TReg32_X; break;
16938 : case AMDGPU::T107_Y: OpKind = MCK_R600_TReg32_Y; break;
16939 : case AMDGPU::T107_Z: OpKind = MCK_R600_TReg32_Z; break;
16940 : case AMDGPU::T107_W: OpKind = MCK_R600_TReg32_W; break;
16941 : case AMDGPU::T108_X: OpKind = MCK_R600_TReg32_X; break;
16942 : case AMDGPU::T108_Y: OpKind = MCK_R600_TReg32_Y; break;
16943 : case AMDGPU::T108_Z: OpKind = MCK_R600_TReg32_Z; break;
16944 : case AMDGPU::T108_W: OpKind = MCK_R600_TReg32_W; break;
16945 : case AMDGPU::T109_X: OpKind = MCK_R600_TReg32_X; break;
16946 : case AMDGPU::T109_Y: OpKind = MCK_R600_TReg32_Y; break;
16947 : case AMDGPU::T109_Z: OpKind = MCK_R600_TReg32_Z; break;
16948 : case AMDGPU::T109_W: OpKind = MCK_R600_TReg32_W; break;
16949 : case AMDGPU::T110_X: OpKind = MCK_R600_TReg32_X; break;
16950 : case AMDGPU::T110_Y: OpKind = MCK_R600_TReg32_Y; break;
16951 : case AMDGPU::T110_Z: OpKind = MCK_R600_TReg32_Z; break;
16952 : case AMDGPU::T110_W: OpKind = MCK_R600_TReg32_W; break;
16953 : case AMDGPU::T111_X: OpKind = MCK_R600_TReg32_X; break;
16954 : case AMDGPU::T111_Y: OpKind = MCK_R600_TReg32_Y; break;
16955 : case AMDGPU::T111_Z: OpKind = MCK_R600_TReg32_Z; break;
16956 : case AMDGPU::T111_W: OpKind = MCK_R600_TReg32_W; break;
16957 : case AMDGPU::T112_X: OpKind = MCK_R600_TReg32_X; break;
16958 : case AMDGPU::T112_Y: OpKind = MCK_R600_TReg32_Y; break;
16959 : case AMDGPU::T112_Z: OpKind = MCK_R600_TReg32_Z; break;
16960 : case AMDGPU::T112_W: OpKind = MCK_R600_TReg32_W; break;
16961 : case AMDGPU::T113_X: OpKind = MCK_R600_TReg32_X; break;
16962 : case AMDGPU::T113_Y: OpKind = MCK_R600_TReg32_Y; break;
16963 : case AMDGPU::T113_Z: OpKind = MCK_R600_TReg32_Z; break;
16964 : case AMDGPU::T113_W: OpKind = MCK_R600_TReg32_W; break;
16965 : case AMDGPU::T114_X: OpKind = MCK_R600_TReg32_X; break;
16966 : case AMDGPU::T114_Y: OpKind = MCK_R600_TReg32_Y; break;
16967 : case AMDGPU::T114_Z: OpKind = MCK_R600_TReg32_Z; break;
16968 : case AMDGPU::T114_W: OpKind = MCK_R600_TReg32_W; break;
16969 : case AMDGPU::T115_X: OpKind = MCK_R600_TReg32_X; break;
16970 : case AMDGPU::T115_Y: OpKind = MCK_R600_TReg32_Y; break;
16971 : case AMDGPU::T115_Z: OpKind = MCK_R600_TReg32_Z; break;
16972 : case AMDGPU::T115_W: OpKind = MCK_R600_TReg32_W; break;
16973 : case AMDGPU::T116_X: OpKind = MCK_R600_TReg32_X; break;
16974 : case AMDGPU::T116_Y: OpKind = MCK_R600_TReg32_Y; break;
16975 : case AMDGPU::T116_Z: OpKind = MCK_R600_TReg32_Z; break;
16976 : case AMDGPU::T116_W: OpKind = MCK_R600_TReg32_W; break;
16977 : case AMDGPU::T117_X: OpKind = MCK_R600_TReg32_X; break;
16978 : case AMDGPU::T117_Y: OpKind = MCK_R600_TReg32_Y; break;
16979 : case AMDGPU::T117_Z: OpKind = MCK_R600_TReg32_Z; break;
16980 : case AMDGPU::T117_W: OpKind = MCK_R600_TReg32_W; break;
16981 : case AMDGPU::T118_X: OpKind = MCK_R600_TReg32_X; break;
16982 : case AMDGPU::T118_Y: OpKind = MCK_R600_TReg32_Y; break;
16983 : case AMDGPU::T118_Z: OpKind = MCK_R600_TReg32_Z; break;
16984 : case AMDGPU::T118_W: OpKind = MCK_R600_TReg32_W; break;
16985 : case AMDGPU::T119_X: OpKind = MCK_R600_TReg32_X; break;
16986 : case AMDGPU::T119_Y: OpKind = MCK_R600_TReg32_Y; break;
16987 : case AMDGPU::T119_Z: OpKind = MCK_R600_TReg32_Z; break;
16988 : case AMDGPU::T119_W: OpKind = MCK_R600_TReg32_W; break;
16989 : case AMDGPU::T120_X: OpKind = MCK_R600_TReg32_X; break;
16990 : case AMDGPU::T120_Y: OpKind = MCK_R600_TReg32_Y; break;
16991 : case AMDGPU::T120_Z: OpKind = MCK_R600_TReg32_Z; break;
16992 : case AMDGPU::T120_W: OpKind = MCK_R600_TReg32_W; break;
16993 : case AMDGPU::T121_X: OpKind = MCK_R600_TReg32_X; break;
16994 : case AMDGPU::T121_Y: OpKind = MCK_R600_TReg32_Y; break;
16995 : case AMDGPU::T121_Z: OpKind = MCK_R600_TReg32_Z; break;
16996 : case AMDGPU::T121_W: OpKind = MCK_R600_TReg32_W; break;
16997 : case AMDGPU::T122_X: OpKind = MCK_R600_TReg32_X; break;
16998 : case AMDGPU::T122_Y: OpKind = MCK_R600_TReg32_Y; break;
16999 : case AMDGPU::T122_Z: OpKind = MCK_R600_TReg32_Z; break;
17000 : case AMDGPU::T122_W: OpKind = MCK_R600_TReg32_W; break;
17001 : case AMDGPU::T123_X: OpKind = MCK_R600_TReg32_X; break;
17002 : case AMDGPU::T123_Y: OpKind = MCK_R600_TReg32_Y; break;
17003 : case AMDGPU::T123_Z: OpKind = MCK_R600_TReg32_Z; break;
17004 : case AMDGPU::T123_W: OpKind = MCK_R600_TReg32_W; break;
17005 : case AMDGPU::T124_X: OpKind = MCK_R600_TReg32_X; break;
17006 : case AMDGPU::T124_Y: OpKind = MCK_R600_TReg32_Y; break;
17007 : case AMDGPU::T124_Z: OpKind = MCK_R600_TReg32_Z; break;
17008 : case AMDGPU::T124_W: OpKind = MCK_R600_TReg32_W; break;
17009 : case AMDGPU::T125_X: OpKind = MCK_R600_TReg32_X; break;
17010 : case AMDGPU::T125_Y: OpKind = MCK_R600_TReg32_Y; break;
17011 : case AMDGPU::T125_Z: OpKind = MCK_R600_TReg32_Z; break;
17012 : case AMDGPU::T125_W: OpKind = MCK_R600_TReg32_W; break;
17013 : case AMDGPU::T126_X: OpKind = MCK_R600_TReg32_X; break;
17014 : case AMDGPU::T126_Y: OpKind = MCK_R600_TReg32_Y; break;
17015 : case AMDGPU::T126_Z: OpKind = MCK_R600_TReg32_Z; break;
17016 : case AMDGPU::T126_W: OpKind = MCK_R600_TReg32_W; break;
17017 : case AMDGPU::T127_X: OpKind = MCK_R600_TReg32_X; break;
17018 : case AMDGPU::T127_Y: OpKind = MCK_R600_TReg32_Y; break;
17019 : case AMDGPU::T127_Z: OpKind = MCK_R600_TReg32_Z; break;
17020 : case AMDGPU::T127_W: OpKind = MCK_R600_TReg32_W; break;
17021 : case AMDGPU::Addr0_X: OpKind = MCK_R600_Addr; break;
17022 : case AMDGPU::Addr0_Y: OpKind = MCK_R600_Addr_Y; break;
17023 : case AMDGPU::Addr0_Z: OpKind = MCK_R600_Addr_Z; break;
17024 : case AMDGPU::Addr0_W: OpKind = MCK_R600_Addr_W; break;
17025 : case AMDGPU::Addr1_X: OpKind = MCK_R600_Addr; break;
17026 : case AMDGPU::Addr2_X: OpKind = MCK_R600_Addr; break;
17027 : case AMDGPU::Addr3_X: OpKind = MCK_R600_Addr; break;
17028 : case AMDGPU::Addr4_X: OpKind = MCK_R600_Addr; break;
17029 : case AMDGPU::Addr5_X: OpKind = MCK_R600_Addr; break;
17030 : case AMDGPU::Addr6_X: OpKind = MCK_R600_Addr; break;
17031 : case AMDGPU::Addr7_X: OpKind = MCK_R600_Addr; break;
17032 : case AMDGPU::Addr8_X: OpKind = MCK_R600_Addr; break;
17033 : case AMDGPU::Addr9_X: OpKind = MCK_R600_Addr; break;
17034 : case AMDGPU::Addr10_X: OpKind = MCK_R600_Addr; break;
17035 : case AMDGPU::Addr11_X: OpKind = MCK_R600_Addr; break;
17036 : case AMDGPU::Addr12_X: OpKind = MCK_R600_Addr; break;
17037 : case AMDGPU::Addr13_X: OpKind = MCK_R600_Addr; break;
17038 : case AMDGPU::Addr14_X: OpKind = MCK_R600_Addr; break;
17039 : case AMDGPU::Addr15_X: OpKind = MCK_R600_Addr; break;
17040 : case AMDGPU::Addr16_X: OpKind = MCK_R600_Addr; break;
17041 : case AMDGPU::Addr17_X: OpKind = MCK_R600_Addr; break;
17042 : case AMDGPU::Addr18_X: OpKind = MCK_R600_Addr; break;
17043 : case AMDGPU::Addr19_X: OpKind = MCK_R600_Addr; break;
17044 : case AMDGPU::Addr20_X: OpKind = MCK_R600_Addr; break;
17045 : case AMDGPU::Addr21_X: OpKind = MCK_R600_Addr; break;
17046 : case AMDGPU::Addr22_X: OpKind = MCK_R600_Addr; break;
17047 : case AMDGPU::Addr23_X: OpKind = MCK_R600_Addr; break;
17048 : case AMDGPU::Addr24_X: OpKind = MCK_R600_Addr; break;
17049 : case AMDGPU::Addr25_X: OpKind = MCK_R600_Addr; break;
17050 : case AMDGPU::Addr26_X: OpKind = MCK_R600_Addr; break;
17051 : case AMDGPU::Addr27_X: OpKind = MCK_R600_Addr; break;
17052 : case AMDGPU::Addr28_X: OpKind = MCK_R600_Addr; break;
17053 : case AMDGPU::Addr29_X: OpKind = MCK_R600_Addr; break;
17054 : case AMDGPU::Addr30_X: OpKind = MCK_R600_Addr; break;
17055 : case AMDGPU::Addr31_X: OpKind = MCK_R600_Addr; break;
17056 : case AMDGPU::Addr32_X: OpKind = MCK_R600_Addr; break;
17057 : case AMDGPU::Addr33_X: OpKind = MCK_R600_Addr; break;
17058 : case AMDGPU::Addr34_X: OpKind = MCK_R600_Addr; break;
17059 : case AMDGPU::Addr35_X: OpKind = MCK_R600_Addr; break;
17060 : case AMDGPU::Addr36_X: OpKind = MCK_R600_Addr; break;
17061 : case AMDGPU::Addr37_X: OpKind = MCK_R600_Addr; break;
17062 : case AMDGPU::Addr38_X: OpKind = MCK_R600_Addr; break;
17063 : case AMDGPU::Addr39_X: OpKind = MCK_R600_Addr; break;
17064 : case AMDGPU::Addr40_X: OpKind = MCK_R600_Addr; break;
17065 : case AMDGPU::Addr41_X: OpKind = MCK_R600_Addr; break;
17066 : case AMDGPU::Addr42_X: OpKind = MCK_R600_Addr; break;
17067 : case AMDGPU::Addr43_X: OpKind = MCK_R600_Addr; break;
17068 : case AMDGPU::Addr44_X: OpKind = MCK_R600_Addr; break;
17069 : case AMDGPU::Addr45_X: OpKind = MCK_R600_Addr; break;
17070 : case AMDGPU::Addr46_X: OpKind = MCK_R600_Addr; break;
17071 : case AMDGPU::Addr47_X: OpKind = MCK_R600_Addr; break;
17072 : case AMDGPU::Addr48_X: OpKind = MCK_R600_Addr; break;
17073 : case AMDGPU::Addr49_X: OpKind = MCK_R600_Addr; break;
17074 : case AMDGPU::Addr50_X: OpKind = MCK_R600_Addr; break;
17075 : case AMDGPU::Addr51_X: OpKind = MCK_R600_Addr; break;
17076 : case AMDGPU::Addr52_X: OpKind = MCK_R600_Addr; break;
17077 : case AMDGPU::Addr53_X: OpKind = MCK_R600_Addr; break;
17078 : case AMDGPU::Addr54_X: OpKind = MCK_R600_Addr; break;
17079 : case AMDGPU::Addr55_X: OpKind = MCK_R600_Addr; break;
17080 : case AMDGPU::Addr56_X: OpKind = MCK_R600_Addr; break;
17081 : case AMDGPU::Addr57_X: OpKind = MCK_R600_Addr; break;
17082 : case AMDGPU::Addr58_X: OpKind = MCK_R600_Addr; break;
17083 : case AMDGPU::Addr59_X: OpKind = MCK_R600_Addr; break;
17084 : case AMDGPU::Addr60_X: OpKind = MCK_R600_Addr; break;
17085 : case AMDGPU::Addr61_X: OpKind = MCK_R600_Addr; break;
17086 : case AMDGPU::Addr62_X: OpKind = MCK_R600_Addr; break;
17087 : case AMDGPU::Addr63_X: OpKind = MCK_R600_Addr; break;
17088 : case AMDGPU::Addr64_X: OpKind = MCK_R600_Addr; break;
17089 : case AMDGPU::Addr65_X: OpKind = MCK_R600_Addr; break;
17090 : case AMDGPU::Addr66_X: OpKind = MCK_R600_Addr; break;
17091 : case AMDGPU::Addr67_X: OpKind = MCK_R600_Addr; break;
17092 : case AMDGPU::Addr68_X: OpKind = MCK_R600_Addr; break;
17093 : case AMDGPU::Addr69_X: OpKind = MCK_R600_Addr; break;
17094 : case AMDGPU::Addr70_X: OpKind = MCK_R600_Addr; break;
17095 : case AMDGPU::Addr71_X: OpKind = MCK_R600_Addr; break;
17096 : case AMDGPU::Addr72_X: OpKind = MCK_R600_Addr; break;
17097 : case AMDGPU::Addr73_X: OpKind = MCK_R600_Addr; break;
17098 : case AMDGPU::Addr74_X: OpKind = MCK_R600_Addr; break;
17099 : case AMDGPU::Addr75_X: OpKind = MCK_R600_Addr; break;
17100 : case AMDGPU::Addr76_X: OpKind = MCK_R600_Addr; break;
17101 : case AMDGPU::Addr77_X: OpKind = MCK_R600_Addr; break;
17102 : case AMDGPU::Addr78_X: OpKind = MCK_R600_Addr; break;
17103 : case AMDGPU::Addr79_X: OpKind = MCK_R600_Addr; break;
17104 : case AMDGPU::Addr80_X: OpKind = MCK_R600_Addr; break;
17105 : case AMDGPU::Addr81_X: OpKind = MCK_R600_Addr; break;
17106 : case AMDGPU::Addr82_X: OpKind = MCK_R600_Addr; break;
17107 : case AMDGPU::Addr83_X: OpKind = MCK_R600_Addr; break;
17108 : case AMDGPU::Addr84_X: OpKind = MCK_R600_Addr; break;
17109 : case AMDGPU::Addr85_X: OpKind = MCK_R600_Addr; break;
17110 : case AMDGPU::Addr86_X: OpKind = MCK_R600_Addr; break;
17111 : case AMDGPU::Addr87_X: OpKind = MCK_R600_Addr; break;
17112 : case AMDGPU::Addr88_X: OpKind = MCK_R600_Addr; break;
17113 : case AMDGPU::Addr89_X: OpKind = MCK_R600_Addr; break;
17114 : case AMDGPU::Addr90_X: OpKind = MCK_R600_Addr; break;
17115 : case AMDGPU::Addr91_X: OpKind = MCK_R600_Addr; break;
17116 : case AMDGPU::Addr92_X: OpKind = MCK_R600_Addr; break;
17117 : case AMDGPU::Addr93_X: OpKind = MCK_R600_Addr; break;
17118 : case AMDGPU::Addr94_X: OpKind = MCK_R600_Addr; break;
17119 : case AMDGPU::Addr95_X: OpKind = MCK_R600_Addr; break;
17120 : case AMDGPU::Addr96_X: OpKind = MCK_R600_Addr; break;
17121 : case AMDGPU::Addr97_X: OpKind = MCK_R600_Addr; break;
17122 : case AMDGPU::Addr98_X: OpKind = MCK_R600_Addr; break;
17123 : case AMDGPU::Addr99_X: OpKind = MCK_R600_Addr; break;
17124 : case AMDGPU::Addr100_X: OpKind = MCK_R600_Addr; break;
17125 : case AMDGPU::Addr101_X: OpKind = MCK_R600_Addr; break;
17126 : case AMDGPU::Addr102_X: OpKind = MCK_R600_Addr; break;
17127 : case AMDGPU::Addr103_X: OpKind = MCK_R600_Addr; break;
17128 : case AMDGPU::Addr104_X: OpKind = MCK_R600_Addr; break;
17129 : case AMDGPU::Addr105_X: OpKind = MCK_R600_Addr; break;
17130 : case AMDGPU::Addr106_X: OpKind = MCK_R600_Addr; break;
17131 : case AMDGPU::Addr107_X: OpKind = MCK_R600_Addr; break;
17132 : case AMDGPU::Addr108_X: OpKind = MCK_R600_Addr; break;
17133 : case AMDGPU::Addr109_X: OpKind = MCK_R600_Addr; break;
17134 : case AMDGPU::Addr110_X: OpKind = MCK_R600_Addr; break;
17135 : case AMDGPU::Addr111_X: OpKind = MCK_R600_Addr; break;
17136 : case AMDGPU::Addr112_X: OpKind = MCK_R600_Addr; break;
17137 : case AMDGPU::Addr113_X: OpKind = MCK_R600_Addr; break;
17138 : case AMDGPU::Addr114_X: OpKind = MCK_R600_Addr; break;
17139 : case AMDGPU::Addr115_X: OpKind = MCK_R600_Addr; break;
17140 : case AMDGPU::Addr116_X: OpKind = MCK_R600_Addr; break;
17141 : case AMDGPU::Addr117_X: OpKind = MCK_R600_Addr; break;
17142 : case AMDGPU::Addr118_X: OpKind = MCK_R600_Addr; break;
17143 : case AMDGPU::Addr119_X: OpKind = MCK_R600_Addr; break;
17144 : case AMDGPU::Addr120_X: OpKind = MCK_R600_Addr; break;
17145 : case AMDGPU::Addr121_X: OpKind = MCK_R600_Addr; break;
17146 : case AMDGPU::Addr122_X: OpKind = MCK_R600_Addr; break;
17147 : case AMDGPU::Addr123_X: OpKind = MCK_R600_Addr; break;
17148 : case AMDGPU::Addr124_X: OpKind = MCK_R600_Addr; break;
17149 : case AMDGPU::Addr125_X: OpKind = MCK_R600_Addr; break;
17150 : case AMDGPU::Addr126_X: OpKind = MCK_R600_Addr; break;
17151 : case AMDGPU::Addr127_X: OpKind = MCK_R600_Addr; break;
17152 : case AMDGPU::T0_XYZW: OpKind = MCK_R600_Reg128; break;
17153 : case AMDGPU::T1_XYZW: OpKind = MCK_R600_Reg128; break;
17154 : case AMDGPU::T2_XYZW: OpKind = MCK_R600_Reg128; break;
17155 : case AMDGPU::T3_XYZW: OpKind = MCK_R600_Reg128; break;
17156 : case AMDGPU::T4_XYZW: OpKind = MCK_R600_Reg128; break;
17157 : case AMDGPU::T5_XYZW: OpKind = MCK_R600_Reg128; break;
17158 : case AMDGPU::T6_XYZW: OpKind = MCK_R600_Reg128; break;
17159 : case AMDGPU::T7_XYZW: OpKind = MCK_R600_Reg128; break;
17160 : case AMDGPU::T8_XYZW: OpKind = MCK_R600_Reg128; break;
17161 : case AMDGPU::T9_XYZW: OpKind = MCK_R600_Reg128; break;
17162 : case AMDGPU::T10_XYZW: OpKind = MCK_R600_Reg128; break;
17163 : case AMDGPU::T11_XYZW: OpKind = MCK_R600_Reg128; break;
17164 : case AMDGPU::T12_XYZW: OpKind = MCK_R600_Reg128; break;
17165 : case AMDGPU::T13_XYZW: OpKind = MCK_R600_Reg128; break;
17166 : case AMDGPU::T14_XYZW: OpKind = MCK_R600_Reg128; break;
17167 : case AMDGPU::T15_XYZW: OpKind = MCK_R600_Reg128; break;
17168 : case AMDGPU::T16_XYZW: OpKind = MCK_R600_Reg128; break;
17169 : case AMDGPU::T17_XYZW: OpKind = MCK_R600_Reg128; break;
17170 : case AMDGPU::T18_XYZW: OpKind = MCK_R600_Reg128; break;
17171 : case AMDGPU::T19_XYZW: OpKind = MCK_R600_Reg128; break;
17172 : case AMDGPU::T20_XYZW: OpKind = MCK_R600_Reg128; break;
17173 : case AMDGPU::T21_XYZW: OpKind = MCK_R600_Reg128; break;
17174 : case AMDGPU::T22_XYZW: OpKind = MCK_R600_Reg128; break;
17175 : case AMDGPU::T23_XYZW: OpKind = MCK_R600_Reg128; break;
17176 : case AMDGPU::T24_XYZW: OpKind = MCK_R600_Reg128; break;
17177 : case AMDGPU::T25_XYZW: OpKind = MCK_R600_Reg128; break;
17178 : case AMDGPU::T26_XYZW: OpKind = MCK_R600_Reg128; break;
17179 : case AMDGPU::T27_XYZW: OpKind = MCK_R600_Reg128; break;
17180 : case AMDGPU::T28_XYZW: OpKind = MCK_R600_Reg128; break;
17181 : case AMDGPU::T29_XYZW: OpKind = MCK_R600_Reg128; break;
17182 : case AMDGPU::T30_XYZW: OpKind = MCK_R600_Reg128; break;
17183 : case AMDGPU::T31_XYZW: OpKind = MCK_R600_Reg128; break;
17184 : case AMDGPU::T32_XYZW: OpKind = MCK_R600_Reg128; break;
17185 : case AMDGPU::T33_XYZW: OpKind = MCK_R600_Reg128; break;
17186 : case AMDGPU::T34_XYZW: OpKind = MCK_R600_Reg128; break;
17187 : case AMDGPU::T35_XYZW: OpKind = MCK_R600_Reg128; break;
17188 : case AMDGPU::T36_XYZW: OpKind = MCK_R600_Reg128; break;
17189 : case AMDGPU::T37_XYZW: OpKind = MCK_R600_Reg128; break;
17190 : case AMDGPU::T38_XYZW: OpKind = MCK_R600_Reg128; break;
17191 : case AMDGPU::T39_XYZW: OpKind = MCK_R600_Reg128; break;
17192 : case AMDGPU::T40_XYZW: OpKind = MCK_R600_Reg128; break;
17193 : case AMDGPU::T41_XYZW: OpKind = MCK_R600_Reg128; break;
17194 : case AMDGPU::T42_XYZW: OpKind = MCK_R600_Reg128; break;
17195 : case AMDGPU::T43_XYZW: OpKind = MCK_R600_Reg128; break;
17196 : case AMDGPU::T44_XYZW: OpKind = MCK_R600_Reg128; break;
17197 : case AMDGPU::T45_XYZW: OpKind = MCK_R600_Reg128; break;
17198 : case AMDGPU::T46_XYZW: OpKind = MCK_R600_Reg128; break;
17199 : case AMDGPU::T47_XYZW: OpKind = MCK_R600_Reg128; break;
17200 : case AMDGPU::T48_XYZW: OpKind = MCK_R600_Reg128; break;
17201 : case AMDGPU::T49_XYZW: OpKind = MCK_R600_Reg128; break;
17202 : case AMDGPU::T50_XYZW: OpKind = MCK_R600_Reg128; break;
17203 : case AMDGPU::T51_XYZW: OpKind = MCK_R600_Reg128; break;
17204 : case AMDGPU::T52_XYZW: OpKind = MCK_R600_Reg128; break;
17205 : case AMDGPU::T53_XYZW: OpKind = MCK_R600_Reg128; break;
17206 : case AMDGPU::T54_XYZW: OpKind = MCK_R600_Reg128; break;
17207 : case AMDGPU::T55_XYZW: OpKind = MCK_R600_Reg128; break;
17208 : case AMDGPU::T56_XYZW: OpKind = MCK_R600_Reg128; break;
17209 : case AMDGPU::T57_XYZW: OpKind = MCK_R600_Reg128; break;
17210 : case AMDGPU::T58_XYZW: OpKind = MCK_R600_Reg128; break;
17211 : case AMDGPU::T59_XYZW: OpKind = MCK_R600_Reg128; break;
17212 : case AMDGPU::T60_XYZW: OpKind = MCK_R600_Reg128; break;
17213 : case AMDGPU::T61_XYZW: OpKind = MCK_R600_Reg128; break;
17214 : case AMDGPU::T62_XYZW: OpKind = MCK_R600_Reg128; break;
17215 : case AMDGPU::T63_XYZW: OpKind = MCK_R600_Reg128; break;
17216 : case AMDGPU::T64_XYZW: OpKind = MCK_R600_Reg128; break;
17217 : case AMDGPU::T65_XYZW: OpKind = MCK_R600_Reg128; break;
17218 : case AMDGPU::T66_XYZW: OpKind = MCK_R600_Reg128; break;
17219 : case AMDGPU::T67_XYZW: OpKind = MCK_R600_Reg128; break;
17220 : case AMDGPU::T68_XYZW: OpKind = MCK_R600_Reg128; break;
17221 : case AMDGPU::T69_XYZW: OpKind = MCK_R600_Reg128; break;
17222 : case AMDGPU::T70_XYZW: OpKind = MCK_R600_Reg128; break;
17223 : case AMDGPU::T71_XYZW: OpKind = MCK_R600_Reg128; break;
17224 : case AMDGPU::T72_XYZW: OpKind = MCK_R600_Reg128; break;
17225 : case AMDGPU::T73_XYZW: OpKind = MCK_R600_Reg128; break;
17226 : case AMDGPU::T74_XYZW: OpKind = MCK_R600_Reg128; break;
17227 : case AMDGPU::T75_XYZW: OpKind = MCK_R600_Reg128; break;
17228 : case AMDGPU::T76_XYZW: OpKind = MCK_R600_Reg128; break;
17229 : case AMDGPU::T77_XYZW: OpKind = MCK_R600_Reg128; break;
17230 : case AMDGPU::T78_XYZW: OpKind = MCK_R600_Reg128; break;
17231 : case AMDGPU::T79_XYZW: OpKind = MCK_R600_Reg128; break;
17232 : case AMDGPU::T80_XYZW: OpKind = MCK_R600_Reg128; break;
17233 : case AMDGPU::T81_XYZW: OpKind = MCK_R600_Reg128; break;
17234 : case AMDGPU::T82_XYZW: OpKind = MCK_R600_Reg128; break;
17235 : case AMDGPU::T83_XYZW: OpKind = MCK_R600_Reg128; break;
17236 : case AMDGPU::T84_XYZW: OpKind = MCK_R600_Reg128; break;
17237 : case AMDGPU::T85_XYZW: OpKind = MCK_R600_Reg128; break;
17238 : case AMDGPU::T86_XYZW: OpKind = MCK_R600_Reg128; break;
17239 : case AMDGPU::T87_XYZW: OpKind = MCK_R600_Reg128; break;
17240 : case AMDGPU::T88_XYZW: OpKind = MCK_R600_Reg128; break;
17241 : case AMDGPU::T89_XYZW: OpKind = MCK_R600_Reg128; break;
17242 : case AMDGPU::T90_XYZW: OpKind = MCK_R600_Reg128; break;
17243 : case AMDGPU::T91_XYZW: OpKind = MCK_R600_Reg128; break;
17244 : case AMDGPU::T92_XYZW: OpKind = MCK_R600_Reg128; break;
17245 : case AMDGPU::T93_XYZW: OpKind = MCK_R600_Reg128; break;
17246 : case AMDGPU::T94_XYZW: OpKind = MCK_R600_Reg128; break;
17247 : case AMDGPU::T95_XYZW: OpKind = MCK_R600_Reg128; break;
17248 : case AMDGPU::T96_XYZW: OpKind = MCK_R600_Reg128; break;
17249 : case AMDGPU::T97_XYZW: OpKind = MCK_R600_Reg128; break;
17250 : case AMDGPU::T98_XYZW: OpKind = MCK_R600_Reg128; break;
17251 : case AMDGPU::T99_XYZW: OpKind = MCK_R600_Reg128; break;
17252 : case AMDGPU::T100_XYZW: OpKind = MCK_R600_Reg128; break;
17253 : case AMDGPU::T101_XYZW: OpKind = MCK_R600_Reg128; break;
17254 : case AMDGPU::T102_XYZW: OpKind = MCK_R600_Reg128; break;
17255 : case AMDGPU::T103_XYZW: OpKind = MCK_R600_Reg128; break;
17256 : case AMDGPU::T104_XYZW: OpKind = MCK_R600_Reg128; break;
17257 : case AMDGPU::T105_XYZW: OpKind = MCK_R600_Reg128; break;
17258 : case AMDGPU::T106_XYZW: OpKind = MCK_R600_Reg128; break;
17259 : case AMDGPU::T107_XYZW: OpKind = MCK_R600_Reg128; break;
17260 : case AMDGPU::T108_XYZW: OpKind = MCK_R600_Reg128; break;
17261 : case AMDGPU::T109_XYZW: OpKind = MCK_R600_Reg128; break;
17262 : case AMDGPU::T110_XYZW: OpKind = MCK_R600_Reg128; break;
17263 : case AMDGPU::T111_XYZW: OpKind = MCK_R600_Reg128; break;
17264 : case AMDGPU::T112_XYZW: OpKind = MCK_R600_Reg128; break;
17265 : case AMDGPU::T113_XYZW: OpKind = MCK_R600_Reg128; break;
17266 : case AMDGPU::T114_XYZW: OpKind = MCK_R600_Reg128; break;
17267 : case AMDGPU::T115_XYZW: OpKind = MCK_R600_Reg128; break;
17268 : case AMDGPU::T116_XYZW: OpKind = MCK_R600_Reg128; break;
17269 : case AMDGPU::T117_XYZW: OpKind = MCK_R600_Reg128; break;
17270 : case AMDGPU::T118_XYZW: OpKind = MCK_R600_Reg128; break;
17271 : case AMDGPU::T119_XYZW: OpKind = MCK_R600_Reg128; break;
17272 : case AMDGPU::T120_XYZW: OpKind = MCK_R600_Reg128; break;
17273 : case AMDGPU::T121_XYZW: OpKind = MCK_R600_Reg128; break;
17274 : case AMDGPU::T122_XYZW: OpKind = MCK_R600_Reg128; break;
17275 : case AMDGPU::T123_XYZW: OpKind = MCK_R600_Reg128; break;
17276 : case AMDGPU::T124_XYZW: OpKind = MCK_R600_Reg128; break;
17277 : case AMDGPU::T125_XYZW: OpKind = MCK_R600_Reg128; break;
17278 : case AMDGPU::T126_XYZW: OpKind = MCK_R600_Reg128; break;
17279 : case AMDGPU::T127_XYZW: OpKind = MCK_R600_Reg128; break;
17280 : case AMDGPU::T0_XY: OpKind = MCK_R600_Reg64; break;
17281 : case AMDGPU::T1_XY: OpKind = MCK_R600_Reg64; break;
17282 : case AMDGPU::T2_XY: OpKind = MCK_R600_Reg64; break;
17283 : case AMDGPU::T3_XY: OpKind = MCK_R600_Reg64; break;
17284 : case AMDGPU::T4_XY: OpKind = MCK_R600_Reg64; break;
17285 : case AMDGPU::T5_XY: OpKind = MCK_R600_Reg64; break;
17286 : case AMDGPU::T6_XY: OpKind = MCK_R600_Reg64; break;
17287 : case AMDGPU::T7_XY: OpKind = MCK_R600_Reg64; break;
17288 : case AMDGPU::T8_XY: OpKind = MCK_R600_Reg64; break;
17289 : case AMDGPU::T9_XY: OpKind = MCK_R600_Reg64; break;
17290 : case AMDGPU::T10_XY: OpKind = MCK_R600_Reg64; break;
17291 : case AMDGPU::T11_XY: OpKind = MCK_R600_Reg64; break;
17292 : case AMDGPU::T12_XY: OpKind = MCK_R600_Reg64; break;
17293 : case AMDGPU::T13_XY: OpKind = MCK_R600_Reg64; break;
17294 : case AMDGPU::T14_XY: OpKind = MCK_R600_Reg64; break;
17295 : case AMDGPU::T15_XY: OpKind = MCK_R600_Reg64; break;
17296 : case AMDGPU::T16_XY: OpKind = MCK_R600_Reg64; break;
17297 : case AMDGPU::T17_XY: OpKind = MCK_R600_Reg64; break;
17298 : case AMDGPU::T18_XY: OpKind = MCK_R600_Reg64; break;
17299 : case AMDGPU::T19_XY: OpKind = MCK_R600_Reg64; break;
17300 : case AMDGPU::T20_XY: OpKind = MCK_R600_Reg64; break;
17301 : case AMDGPU::T21_XY: OpKind = MCK_R600_Reg64; break;
17302 : case AMDGPU::T22_XY: OpKind = MCK_R600_Reg64; break;
17303 : case AMDGPU::T23_XY: OpKind = MCK_R600_Reg64; break;
17304 : case AMDGPU::T24_XY: OpKind = MCK_R600_Reg64; break;
17305 : case AMDGPU::T25_XY: OpKind = MCK_R600_Reg64; break;
17306 : case AMDGPU::T26_XY: OpKind = MCK_R600_Reg64; break;
17307 : case AMDGPU::T27_XY: OpKind = MCK_R600_Reg64; break;
17308 : case AMDGPU::T28_XY: OpKind = MCK_R600_Reg64; break;
17309 : case AMDGPU::T29_XY: OpKind = MCK_R600_Reg64; break;
17310 : case AMDGPU::T30_XY: OpKind = MCK_R600_Reg64; break;
17311 : case AMDGPU::T31_XY: OpKind = MCK_R600_Reg64; break;
17312 : case AMDGPU::T32_XY: OpKind = MCK_R600_Reg64; break;
17313 : case AMDGPU::T33_XY: OpKind = MCK_R600_Reg64; break;
17314 : case AMDGPU::T34_XY: OpKind = MCK_R600_Reg64; break;
17315 : case AMDGPU::T35_XY: OpKind = MCK_R600_Reg64; break;
17316 : case AMDGPU::T36_XY: OpKind = MCK_R600_Reg64; break;
17317 : case AMDGPU::T37_XY: OpKind = MCK_R600_Reg64; break;
17318 : case AMDGPU::T38_XY: OpKind = MCK_R600_Reg64; break;
17319 : case AMDGPU::T39_XY: OpKind = MCK_R600_Reg64; break;
17320 : case AMDGPU::T40_XY: OpKind = MCK_R600_Reg64; break;
17321 : case AMDGPU::T41_XY: OpKind = MCK_R600_Reg64; break;
17322 : case AMDGPU::T42_XY: OpKind = MCK_R600_Reg64; break;
17323 : case AMDGPU::T43_XY: OpKind = MCK_R600_Reg64; break;
17324 : case AMDGPU::T44_XY: OpKind = MCK_R600_Reg64; break;
17325 : case AMDGPU::T45_XY: OpKind = MCK_R600_Reg64; break;
17326 : case AMDGPU::T46_XY: OpKind = MCK_R600_Reg64; break;
17327 : case AMDGPU::T47_XY: OpKind = MCK_R600_Reg64; break;
17328 : case AMDGPU::T48_XY: OpKind = MCK_R600_Reg64; break;
17329 : case AMDGPU::T49_XY: OpKind = MCK_R600_Reg64; break;
17330 : case AMDGPU::T50_XY: OpKind = MCK_R600_Reg64; break;
17331 : case AMDGPU::T51_XY: OpKind = MCK_R600_Reg64; break;
17332 : case AMDGPU::T52_XY: OpKind = MCK_R600_Reg64; break;
17333 : case AMDGPU::T53_XY: OpKind = MCK_R600_Reg64; break;
17334 : case AMDGPU::T54_XY: OpKind = MCK_R600_Reg64; break;
17335 : case AMDGPU::T55_XY: OpKind = MCK_R600_Reg64; break;
17336 : case AMDGPU::T56_XY: OpKind = MCK_R600_Reg64; break;
17337 : case AMDGPU::T57_XY: OpKind = MCK_R600_Reg64; break;
17338 : case AMDGPU::T58_XY: OpKind = MCK_R600_Reg64; break;
17339 : case AMDGPU::T59_XY: OpKind = MCK_R600_Reg64; break;
17340 : case AMDGPU::T60_XY: OpKind = MCK_R600_Reg64; break;
17341 : case AMDGPU::T61_XY: OpKind = MCK_R600_Reg64; break;
17342 : case AMDGPU::T62_XY: OpKind = MCK_R600_Reg64; break;
17343 : case AMDGPU::T63_XY: OpKind = MCK_R600_Reg64; break;
17344 : case AMDGPU::V0123_X: OpKind = MCK_Reg12; break;
17345 : case AMDGPU::V0123_Y: OpKind = MCK_Reg14; break;
17346 : case AMDGPU::V0123_Z: OpKind = MCK_Reg15; break;
17347 : case AMDGPU::V0123_W: OpKind = MCK_Reg16; break;
17348 : case AMDGPU::V01_X: OpKind = MCK_Reg18; break;
17349 : case AMDGPU::V01_Y: OpKind = MCK_Reg19; break;
17350 : case AMDGPU::V01_Z: OpKind = MCK_Reg20; break;
17351 : case AMDGPU::V01_W: OpKind = MCK_Reg21; break;
17352 : case AMDGPU::V23_X: OpKind = MCK_Reg18; break;
17353 : case AMDGPU::V23_Y: OpKind = MCK_Reg19; break;
17354 : case AMDGPU::V23_Z: OpKind = MCK_Reg20; break;
17355 : case AMDGPU::V23_W: OpKind = MCK_Reg21; break;
17356 : case AMDGPU::KC0_159_X: OpKind = MCK_R600_KC0_X; break;
17357 : case AMDGPU::KC0_159_Y: OpKind = MCK_R600_KC0_Y; break;
17358 : case AMDGPU::KC0_159_Z: OpKind = MCK_R600_KC0_Z; break;
17359 : case AMDGPU::KC0_159_W: OpKind = MCK_R600_KC0_W; break;
17360 : case AMDGPU::KC0_158_X: OpKind = MCK_R600_KC0_X; break;
17361 : case AMDGPU::KC0_158_Y: OpKind = MCK_R600_KC0_Y; break;
17362 : case AMDGPU::KC0_158_Z: OpKind = MCK_R600_KC0_Z; break;
17363 : case AMDGPU::KC0_158_W: OpKind = MCK_R600_KC0_W; break;
17364 : case AMDGPU::KC0_157_X: OpKind = MCK_R600_KC0_X; break;
17365 : case AMDGPU::KC0_157_Y: OpKind = MCK_R600_KC0_Y; break;
17366 : case AMDGPU::KC0_157_Z: OpKind = MCK_R600_KC0_Z; break;
17367 : case AMDGPU::KC0_157_W: OpKind = MCK_R600_KC0_W; break;
17368 : case AMDGPU::KC0_156_X: OpKind = MCK_R600_KC0_X; break;
17369 : case AMDGPU::KC0_156_Y: OpKind = MCK_R600_KC0_Y; break;
17370 : case AMDGPU::KC0_156_Z: OpKind = MCK_R600_KC0_Z; break;
17371 : case AMDGPU::KC0_156_W: OpKind = MCK_R600_KC0_W; break;
17372 : case AMDGPU::KC0_155_X: OpKind = MCK_R600_KC0_X; break;
17373 : case AMDGPU::KC0_155_Y: OpKind = MCK_R600_KC0_Y; break;
17374 : case AMDGPU::KC0_155_Z: OpKind = MCK_R600_KC0_Z; break;
17375 : case AMDGPU::KC0_155_W: OpKind = MCK_R600_KC0_W; break;
17376 : case AMDGPU::KC0_154_X: OpKind = MCK_R600_KC0_X; break;
17377 : case AMDGPU::KC0_154_Y: OpKind = MCK_R600_KC0_Y; break;
17378 : case AMDGPU::KC0_154_Z: OpKind = MCK_R600_KC0_Z; break;
17379 : case AMDGPU::KC0_154_W: OpKind = MCK_R600_KC0_W; break;
17380 : case AMDGPU::KC0_153_X: OpKind = MCK_R600_KC0_X; break;
17381 : case AMDGPU::KC0_153_Y: OpKind = MCK_R600_KC0_Y; break;
17382 : case AMDGPU::KC0_153_Z: OpKind = MCK_R600_KC0_Z; break;
17383 : case AMDGPU::KC0_153_W: OpKind = MCK_R600_KC0_W; break;
17384 : case AMDGPU::KC0_152_X: OpKind = MCK_R600_KC0_X; break;
17385 : case AMDGPU::KC0_152_Y: OpKind = MCK_R600_KC0_Y; break;
17386 : case AMDGPU::KC0_152_Z: OpKind = MCK_R600_KC0_Z; break;
17387 : case AMDGPU::KC0_152_W: OpKind = MCK_R600_KC0_W; break;
17388 : case AMDGPU::KC0_151_X: OpKind = MCK_R600_KC0_X; break;
17389 : case AMDGPU::KC0_151_Y: OpKind = MCK_R600_KC0_Y; break;
17390 : case AMDGPU::KC0_151_Z: OpKind = MCK_R600_KC0_Z; break;
17391 : case AMDGPU::KC0_151_W: OpKind = MCK_R600_KC0_W; break;
17392 : case AMDGPU::KC0_150_X: OpKind = MCK_R600_KC0_X; break;
17393 : case AMDGPU::KC0_150_Y: OpKind = MCK_R600_KC0_Y; break;
17394 : case AMDGPU::KC0_150_Z: OpKind = MCK_R600_KC0_Z; break;
17395 : case AMDGPU::KC0_150_W: OpKind = MCK_R600_KC0_W; break;
17396 : case AMDGPU::KC0_149_X: OpKind = MCK_R600_KC0_X; break;
17397 : case AMDGPU::KC0_149_Y: OpKind = MCK_R600_KC0_Y; break;
17398 : case AMDGPU::KC0_149_Z: OpKind = MCK_R600_KC0_Z; break;
17399 : case AMDGPU::KC0_149_W: OpKind = MCK_R600_KC0_W; break;
17400 : case AMDGPU::KC0_148_X: OpKind = MCK_R600_KC0_X; break;
17401 : case AMDGPU::KC0_148_Y: OpKind = MCK_R600_KC0_Y; break;
17402 : case AMDGPU::KC0_148_Z: OpKind = MCK_R600_KC0_Z; break;
17403 : case AMDGPU::KC0_148_W: OpKind = MCK_R600_KC0_W; break;
17404 : case AMDGPU::KC0_147_X: OpKind = MCK_R600_KC0_X; break;
17405 : case AMDGPU::KC0_147_Y: OpKind = MCK_R600_KC0_Y; break;
17406 : case AMDGPU::KC0_147_Z: OpKind = MCK_R600_KC0_Z; break;
17407 : case AMDGPU::KC0_147_W: OpKind = MCK_R600_KC0_W; break;
17408 : case AMDGPU::KC0_146_X: OpKind = MCK_R600_KC0_X; break;
17409 : case AMDGPU::KC0_146_Y: OpKind = MCK_R600_KC0_Y; break;
17410 : case AMDGPU::KC0_146_Z: OpKind = MCK_R600_KC0_Z; break;
17411 : case AMDGPU::KC0_146_W: OpKind = MCK_R600_KC0_W; break;
17412 : case AMDGPU::KC0_145_X: OpKind = MCK_R600_KC0_X; break;
17413 : case AMDGPU::KC0_145_Y: OpKind = MCK_R600_KC0_Y; break;
17414 : case AMDGPU::KC0_145_Z: OpKind = MCK_R600_KC0_Z; break;
17415 : case AMDGPU::KC0_145_W: OpKind = MCK_R600_KC0_W; break;
17416 : case AMDGPU::KC0_144_X: OpKind = MCK_R600_KC0_X; break;
17417 : case AMDGPU::KC0_144_Y: OpKind = MCK_R600_KC0_Y; break;
17418 : case AMDGPU::KC0_144_Z: OpKind = MCK_R600_KC0_Z; break;
17419 : case AMDGPU::KC0_144_W: OpKind = MCK_R600_KC0_W; break;
17420 : case AMDGPU::KC0_143_X: OpKind = MCK_R600_KC0_X; break;
17421 : case AMDGPU::KC0_143_Y: OpKind = MCK_R600_KC0_Y; break;
17422 : case AMDGPU::KC0_143_Z: OpKind = MCK_R600_KC0_Z; break;
17423 : case AMDGPU::KC0_143_W: OpKind = MCK_R600_KC0_W; break;
17424 : case AMDGPU::KC0_142_X: OpKind = MCK_R600_KC0_X; break;
17425 : case AMDGPU::KC0_142_Y: OpKind = MCK_R600_KC0_Y; break;
17426 : case AMDGPU::KC0_142_Z: OpKind = MCK_R600_KC0_Z; break;
17427 : case AMDGPU::KC0_142_W: OpKind = MCK_R600_KC0_W; break;
17428 : case AMDGPU::KC0_141_X: OpKind = MCK_R600_KC0_X; break;
17429 : case AMDGPU::KC0_141_Y: OpKind = MCK_R600_KC0_Y; break;
17430 : case AMDGPU::KC0_141_Z: OpKind = MCK_R600_KC0_Z; break;
17431 : case AMDGPU::KC0_141_W: OpKind = MCK_R600_KC0_W; break;
17432 : case AMDGPU::KC0_140_X: OpKind = MCK_R600_KC0_X; break;
17433 : case AMDGPU::KC0_140_Y: OpKind = MCK_R600_KC0_Y; break;
17434 : case AMDGPU::KC0_140_Z: OpKind = MCK_R600_KC0_Z; break;
17435 : case AMDGPU::KC0_140_W: OpKind = MCK_R600_KC0_W; break;
17436 : case AMDGPU::KC0_139_X: OpKind = MCK_R600_KC0_X; break;
17437 : case AMDGPU::KC0_139_Y: OpKind = MCK_R600_KC0_Y; break;
17438 : case AMDGPU::KC0_139_Z: OpKind = MCK_R600_KC0_Z; break;
17439 : case AMDGPU::KC0_139_W: OpKind = MCK_R600_KC0_W; break;
17440 : case AMDGPU::KC0_138_X: OpKind = MCK_R600_KC0_X; break;
17441 : case AMDGPU::KC0_138_Y: OpKind = MCK_R600_KC0_Y; break;
17442 : case AMDGPU::KC0_138_Z: OpKind = MCK_R600_KC0_Z; break;
17443 : case AMDGPU::KC0_138_W: OpKind = MCK_R600_KC0_W; break;
17444 : case AMDGPU::KC0_137_X: OpKind = MCK_R600_KC0_X; break;
17445 : case AMDGPU::KC0_137_Y: OpKind = MCK_R600_KC0_Y; break;
17446 : case AMDGPU::KC0_137_Z: OpKind = MCK_R600_KC0_Z; break;
17447 : case AMDGPU::KC0_137_W: OpKind = MCK_R600_KC0_W; break;
17448 : case AMDGPU::KC0_136_X: OpKind = MCK_R600_KC0_X; break;
17449 : case AMDGPU::KC0_136_Y: OpKind = MCK_R600_KC0_Y; break;
17450 : case AMDGPU::KC0_136_Z: OpKind = MCK_R600_KC0_Z; break;
17451 : case AMDGPU::KC0_136_W: OpKind = MCK_R600_KC0_W; break;
17452 : case AMDGPU::KC0_135_X: OpKind = MCK_R600_KC0_X; break;
17453 : case AMDGPU::KC0_135_Y: OpKind = MCK_R600_KC0_Y; break;
17454 : case AMDGPU::KC0_135_Z: OpKind = MCK_R600_KC0_Z; break;
17455 : case AMDGPU::KC0_135_W: OpKind = MCK_R600_KC0_W; break;
17456 : case AMDGPU::KC0_134_X: OpKind = MCK_R600_KC0_X; break;
17457 : case AMDGPU::KC0_134_Y: OpKind = MCK_R600_KC0_Y; break;
17458 : case AMDGPU::KC0_134_Z: OpKind = MCK_R600_KC0_Z; break;
17459 : case AMDGPU::KC0_134_W: OpKind = MCK_R600_KC0_W; break;
17460 : case AMDGPU::KC0_133_X: OpKind = MCK_R600_KC0_X; break;
17461 : case AMDGPU::KC0_133_Y: OpKind = MCK_R600_KC0_Y; break;
17462 : case AMDGPU::KC0_133_Z: OpKind = MCK_R600_KC0_Z; break;
17463 : case AMDGPU::KC0_133_W: OpKind = MCK_R600_KC0_W; break;
17464 : case AMDGPU::KC0_132_X: OpKind = MCK_R600_KC0_X; break;
17465 : case AMDGPU::KC0_132_Y: OpKind = MCK_R600_KC0_Y; break;
17466 : case AMDGPU::KC0_132_Z: OpKind = MCK_R600_KC0_Z; break;
17467 : case AMDGPU::KC0_132_W: OpKind = MCK_R600_KC0_W; break;
17468 : case AMDGPU::KC0_131_X: OpKind = MCK_R600_KC0_X; break;
17469 : case AMDGPU::KC0_131_Y: OpKind = MCK_R600_KC0_Y; break;
17470 : case AMDGPU::KC0_131_Z: OpKind = MCK_R600_KC0_Z; break;
17471 : case AMDGPU::KC0_131_W: OpKind = MCK_R600_KC0_W; break;
17472 : case AMDGPU::KC0_130_X: OpKind = MCK_R600_KC0_X; break;
17473 : case AMDGPU::KC0_130_Y: OpKind = MCK_R600_KC0_Y; break;
17474 : case AMDGPU::KC0_130_Z: OpKind = MCK_R600_KC0_Z; break;
17475 : case AMDGPU::KC0_130_W: OpKind = MCK_R600_KC0_W; break;
17476 : case AMDGPU::KC0_129_X: OpKind = MCK_R600_KC0_X; break;
17477 : case AMDGPU::KC0_129_Y: OpKind = MCK_R600_KC0_Y; break;
17478 : case AMDGPU::KC0_129_Z: OpKind = MCK_R600_KC0_Z; break;
17479 : case AMDGPU::KC0_129_W: OpKind = MCK_R600_KC0_W; break;
17480 : case AMDGPU::KC0_128_X: OpKind = MCK_R600_KC0_X; break;
17481 : case AMDGPU::KC0_128_Y: OpKind = MCK_R600_KC0_Y; break;
17482 : case AMDGPU::KC0_128_Z: OpKind = MCK_R600_KC0_Z; break;
17483 : case AMDGPU::KC0_128_W: OpKind = MCK_R600_KC0_W; break;
17484 : case AMDGPU::KC1_191_X: OpKind = MCK_R600_KC1_X; break;
17485 : case AMDGPU::KC1_191_Y: OpKind = MCK_R600_KC1_Y; break;
17486 : case AMDGPU::KC1_191_Z: OpKind = MCK_R600_KC1_Z; break;
17487 : case AMDGPU::KC1_191_W: OpKind = MCK_R600_KC1_W; break;
17488 : case AMDGPU::KC1_190_X: OpKind = MCK_R600_KC1_X; break;
17489 : case AMDGPU::KC1_190_Y: OpKind = MCK_R600_KC1_Y; break;
17490 : case AMDGPU::KC1_190_Z: OpKind = MCK_R600_KC1_Z; break;
17491 : case AMDGPU::KC1_190_W: OpKind = MCK_R600_KC1_W; break;
17492 : case AMDGPU::KC1_189_X: OpKind = MCK_R600_KC1_X; break;
17493 : case AMDGPU::KC1_189_Y: OpKind = MCK_R600_KC1_Y; break;
17494 : case AMDGPU::KC1_189_Z: OpKind = MCK_R600_KC1_Z; break;
17495 : case AMDGPU::KC1_189_W: OpKind = MCK_R600_KC1_W; break;
17496 : case AMDGPU::KC1_188_X: OpKind = MCK_R600_KC1_X; break;
17497 : case AMDGPU::KC1_188_Y: OpKind = MCK_R600_KC1_Y; break;
17498 : case AMDGPU::KC1_188_Z: OpKind = MCK_R600_KC1_Z; break;
17499 : case AMDGPU::KC1_188_W: OpKind = MCK_R600_KC1_W; break;
17500 : case AMDGPU::KC1_187_X: OpKind = MCK_R600_KC1_X; break;
17501 : case AMDGPU::KC1_187_Y: OpKind = MCK_R600_KC1_Y; break;
17502 : case AMDGPU::KC1_187_Z: OpKind = MCK_R600_KC1_Z; break;
17503 : case AMDGPU::KC1_187_W: OpKind = MCK_R600_KC1_W; break;
17504 : case AMDGPU::KC1_186_X: OpKind = MCK_R600_KC1_X; break;
17505 : case AMDGPU::KC1_186_Y: OpKind = MCK_R600_KC1_Y; break;
17506 : case AMDGPU::KC1_186_Z: OpKind = MCK_R600_KC1_Z; break;
17507 : case AMDGPU::KC1_186_W: OpKind = MCK_R600_KC1_W; break;
17508 : case AMDGPU::KC1_185_X: OpKind = MCK_R600_KC1_X; break;
17509 : case AMDGPU::KC1_185_Y: OpKind = MCK_R600_KC1_Y; break;
17510 : case AMDGPU::KC1_185_Z: OpKind = MCK_R600_KC1_Z; break;
17511 : case AMDGPU::KC1_185_W: OpKind = MCK_R600_KC1_W; break;
17512 : case AMDGPU::KC1_184_X: OpKind = MCK_R600_KC1_X; break;
17513 : case AMDGPU::KC1_184_Y: OpKind = MCK_R600_KC1_Y; break;
17514 : case AMDGPU::KC1_184_Z: OpKind = MCK_R600_KC1_Z; break;
17515 : case AMDGPU::KC1_184_W: OpKind = MCK_R600_KC1_W; break;
17516 : case AMDGPU::KC1_183_X: OpKind = MCK_R600_KC1_X; break;
17517 : case AMDGPU::KC1_183_Y: OpKind = MCK_R600_KC1_Y; break;
17518 : case AMDGPU::KC1_183_Z: OpKind = MCK_R600_KC1_Z; break;
17519 : case AMDGPU::KC1_183_W: OpKind = MCK_R600_KC1_W; break;
17520 : case AMDGPU::KC1_182_X: OpKind = MCK_R600_KC1_X; break;
17521 : case AMDGPU::KC1_182_Y: OpKind = MCK_R600_KC1_Y; break;
17522 : case AMDGPU::KC1_182_Z: OpKind = MCK_R600_KC1_Z; break;
17523 : case AMDGPU::KC1_182_W: OpKind = MCK_R600_KC1_W; break;
17524 : case AMDGPU::KC1_181_X: OpKind = MCK_R600_KC1_X; break;
17525 : case AMDGPU::KC1_181_Y: OpKind = MCK_R600_KC1_Y; break;
17526 : case AMDGPU::KC1_181_Z: OpKind = MCK_R600_KC1_Z; break;
17527 : case AMDGPU::KC1_181_W: OpKind = MCK_R600_KC1_W; break;
17528 : case AMDGPU::KC1_180_X: OpKind = MCK_R600_KC1_X; break;
17529 : case AMDGPU::KC1_180_Y: OpKind = MCK_R600_KC1_Y; break;
17530 : case AMDGPU::KC1_180_Z: OpKind = MCK_R600_KC1_Z; break;
17531 : case AMDGPU::KC1_180_W: OpKind = MCK_R600_KC1_W; break;
17532 : case AMDGPU::KC1_179_X: OpKind = MCK_R600_KC1_X; break;
17533 : case AMDGPU::KC1_179_Y: OpKind = MCK_R600_KC1_Y; break;
17534 : case AMDGPU::KC1_179_Z: OpKind = MCK_R600_KC1_Z; break;
17535 : case AMDGPU::KC1_179_W: OpKind = MCK_R600_KC1_W; break;
17536 : case AMDGPU::KC1_178_X: OpKind = MCK_R600_KC1_X; break;
17537 : case AMDGPU::KC1_178_Y: OpKind = MCK_R600_KC1_Y; break;
17538 : case AMDGPU::KC1_178_Z: OpKind = MCK_R600_KC1_Z; break;
17539 : case AMDGPU::KC1_178_W: OpKind = MCK_R600_KC1_W; break;
17540 : case AMDGPU::KC1_177_X: OpKind = MCK_R600_KC1_X; break;
17541 : case AMDGPU::KC1_177_Y: OpKind = MCK_R600_KC1_Y; break;
17542 : case AMDGPU::KC1_177_Z: OpKind = MCK_R600_KC1_Z; break;
17543 : case AMDGPU::KC1_177_W: OpKind = MCK_R600_KC1_W; break;
17544 : case AMDGPU::KC1_176_X: OpKind = MCK_R600_KC1_X; break;
17545 : case AMDGPU::KC1_176_Y: OpKind = MCK_R600_KC1_Y; break;
17546 : case AMDGPU::KC1_176_Z: OpKind = MCK_R600_KC1_Z; break;
17547 : case AMDGPU::KC1_176_W: OpKind = MCK_R600_KC1_W; break;
17548 : case AMDGPU::KC1_175_X: OpKind = MCK_R600_KC1_X; break;
17549 : case AMDGPU::KC1_175_Y: OpKind = MCK_R600_KC1_Y; break;
17550 : case AMDGPU::KC1_175_Z: OpKind = MCK_R600_KC1_Z; break;
17551 : case AMDGPU::KC1_175_W: OpKind = MCK_R600_KC1_W; break;
17552 : case AMDGPU::KC1_174_X: OpKind = MCK_R600_KC1_X; break;
17553 : case AMDGPU::KC1_174_Y: OpKind = MCK_R600_KC1_Y; break;
17554 : case AMDGPU::KC1_174_Z: OpKind = MCK_R600_KC1_Z; break;
17555 : case AMDGPU::KC1_174_W: OpKind = MCK_R600_KC1_W; break;
17556 : case AMDGPU::KC1_173_X: OpKind = MCK_R600_KC1_X; break;
17557 : case AMDGPU::KC1_173_Y: OpKind = MCK_R600_KC1_Y; break;
17558 : case AMDGPU::KC1_173_Z: OpKind = MCK_R600_KC1_Z; break;
17559 : case AMDGPU::KC1_173_W: OpKind = MCK_R600_KC1_W; break;
17560 : case AMDGPU::KC1_172_X: OpKind = MCK_R600_KC1_X; break;
17561 : case AMDGPU::KC1_172_Y: OpKind = MCK_R600_KC1_Y; break;
17562 : case AMDGPU::KC1_172_Z: OpKind = MCK_R600_KC1_Z; break;
17563 : case AMDGPU::KC1_172_W: OpKind = MCK_R600_KC1_W; break;
17564 : case AMDGPU::KC1_171_X: OpKind = MCK_R600_KC1_X; break;
17565 : case AMDGPU::KC1_171_Y: OpKind = MCK_R600_KC1_Y; break;
17566 : case AMDGPU::KC1_171_Z: OpKind = MCK_R600_KC1_Z; break;
17567 : case AMDGPU::KC1_171_W: OpKind = MCK_R600_KC1_W; break;
17568 : case AMDGPU::KC1_170_X: OpKind = MCK_R600_KC1_X; break;
17569 : case AMDGPU::KC1_170_Y: OpKind = MCK_R600_KC1_Y; break;
17570 : case AMDGPU::KC1_170_Z: OpKind = MCK_R600_KC1_Z; break;
17571 : case AMDGPU::KC1_170_W: OpKind = MCK_R600_KC1_W; break;
17572 : case AMDGPU::KC1_169_X: OpKind = MCK_R600_KC1_X; break;
17573 : case AMDGPU::KC1_169_Y: OpKind = MCK_R600_KC1_Y; break;
17574 : case AMDGPU::KC1_169_Z: OpKind = MCK_R600_KC1_Z; break;
17575 : case AMDGPU::KC1_169_W: OpKind = MCK_R600_KC1_W; break;
17576 : case AMDGPU::KC1_168_X: OpKind = MCK_R600_KC1_X; break;
17577 : case AMDGPU::KC1_168_Y: OpKind = MCK_R600_KC1_Y; break;
17578 : case AMDGPU::KC1_168_Z: OpKind = MCK_R600_KC1_Z; break;
17579 : case AMDGPU::KC1_168_W: OpKind = MCK_R600_KC1_W; break;
17580 : case AMDGPU::KC1_167_X: OpKind = MCK_R600_KC1_X; break;
17581 : case AMDGPU::KC1_167_Y: OpKind = MCK_R600_KC1_Y; break;
17582 : case AMDGPU::KC1_167_Z: OpKind = MCK_R600_KC1_Z; break;
17583 : case AMDGPU::KC1_167_W: OpKind = MCK_R600_KC1_W; break;
17584 : case AMDGPU::KC1_166_X: OpKind = MCK_R600_KC1_X; break;
17585 : case AMDGPU::KC1_166_Y: OpKind = MCK_R600_KC1_Y; break;
17586 : case AMDGPU::KC1_166_Z: OpKind = MCK_R600_KC1_Z; break;
17587 : case AMDGPU::KC1_166_W: OpKind = MCK_R600_KC1_W; break;
17588 : case AMDGPU::KC1_165_X: OpKind = MCK_R600_KC1_X; break;
17589 : case AMDGPU::KC1_165_Y: OpKind = MCK_R600_KC1_Y; break;
17590 : case AMDGPU::KC1_165_Z: OpKind = MCK_R600_KC1_Z; break;
17591 : case AMDGPU::KC1_165_W: OpKind = MCK_R600_KC1_W; break;
17592 : case AMDGPU::KC1_164_X: OpKind = MCK_R600_KC1_X; break;
17593 : case AMDGPU::KC1_164_Y: OpKind = MCK_R600_KC1_Y; break;
17594 : case AMDGPU::KC1_164_Z: OpKind = MCK_R600_KC1_Z; break;
17595 : case AMDGPU::KC1_164_W: OpKind = MCK_R600_KC1_W; break;
17596 : case AMDGPU::KC1_163_X: OpKind = MCK_R600_KC1_X; break;
17597 : case AMDGPU::KC1_163_Y: OpKind = MCK_R600_KC1_Y; break;
17598 : case AMDGPU::KC1_163_Z: OpKind = MCK_R600_KC1_Z; break;
17599 : case AMDGPU::KC1_163_W: OpKind = MCK_R600_KC1_W; break;
17600 : case AMDGPU::KC1_162_X: OpKind = MCK_R600_KC1_X; break;
17601 : case AMDGPU::KC1_162_Y: OpKind = MCK_R600_KC1_Y; break;
17602 : case AMDGPU::KC1_162_Z: OpKind = MCK_R600_KC1_Z; break;
17603 : case AMDGPU::KC1_162_W: OpKind = MCK_R600_KC1_W; break;
17604 : case AMDGPU::KC1_161_X: OpKind = MCK_R600_KC1_X; break;
17605 : case AMDGPU::KC1_161_Y: OpKind = MCK_R600_KC1_Y; break;
17606 : case AMDGPU::KC1_161_Z: OpKind = MCK_R600_KC1_Z; break;
17607 : case AMDGPU::KC1_161_W: OpKind = MCK_R600_KC1_W; break;
17608 : case AMDGPU::KC1_160_X: OpKind = MCK_R600_KC1_X; break;
17609 : case AMDGPU::KC1_160_Y: OpKind = MCK_R600_KC1_Y; break;
17610 : case AMDGPU::KC1_160_Z: OpKind = MCK_R600_KC1_Z; break;
17611 : case AMDGPU::KC1_160_W: OpKind = MCK_R600_KC1_W; break;
17612 : case AMDGPU::ArrayBase448: OpKind = MCK_R600_ArrayBase; break;
17613 : case AMDGPU::ArrayBase449: OpKind = MCK_R600_ArrayBase; break;
17614 : case AMDGPU::ArrayBase450: OpKind = MCK_R600_ArrayBase; break;
17615 : case AMDGPU::ArrayBase451: OpKind = MCK_R600_ArrayBase; break;
17616 : case AMDGPU::ArrayBase452: OpKind = MCK_R600_ArrayBase; break;
17617 : case AMDGPU::ArrayBase453: OpKind = MCK_R600_ArrayBase; break;
17618 : case AMDGPU::ArrayBase454: OpKind = MCK_R600_ArrayBase; break;
17619 : case AMDGPU::ArrayBase455: OpKind = MCK_R600_ArrayBase; break;
17620 : case AMDGPU::ArrayBase456: OpKind = MCK_R600_ArrayBase; break;
17621 : case AMDGPU::ArrayBase457: OpKind = MCK_R600_ArrayBase; break;
17622 : case AMDGPU::ArrayBase458: OpKind = MCK_R600_ArrayBase; break;
17623 : case AMDGPU::ArrayBase459: OpKind = MCK_R600_ArrayBase; break;
17624 : case AMDGPU::ArrayBase460: OpKind = MCK_R600_ArrayBase; break;
17625 : case AMDGPU::ArrayBase461: OpKind = MCK_R600_ArrayBase; break;
17626 : case AMDGPU::ArrayBase462: OpKind = MCK_R600_ArrayBase; break;
17627 : case AMDGPU::ArrayBase463: OpKind = MCK_R600_ArrayBase; break;
17628 : case AMDGPU::ArrayBase464: OpKind = MCK_R600_ArrayBase; break;
17629 : case AMDGPU::ArrayBase465: OpKind = MCK_R600_ArrayBase; break;
17630 : case AMDGPU::ArrayBase466: OpKind = MCK_R600_ArrayBase; break;
17631 : case AMDGPU::ArrayBase467: OpKind = MCK_R600_ArrayBase; break;
17632 : case AMDGPU::ArrayBase468: OpKind = MCK_R600_ArrayBase; break;
17633 : case AMDGPU::ArrayBase469: OpKind = MCK_R600_ArrayBase; break;
17634 : case AMDGPU::ArrayBase470: OpKind = MCK_R600_ArrayBase; break;
17635 : case AMDGPU::ArrayBase471: OpKind = MCK_R600_ArrayBase; break;
17636 : case AMDGPU::ArrayBase472: OpKind = MCK_R600_ArrayBase; break;
17637 : case AMDGPU::ArrayBase473: OpKind = MCK_R600_ArrayBase; break;
17638 : case AMDGPU::ArrayBase474: OpKind = MCK_R600_ArrayBase; break;
17639 : case AMDGPU::ArrayBase475: OpKind = MCK_R600_ArrayBase; break;
17640 : case AMDGPU::ArrayBase476: OpKind = MCK_R600_ArrayBase; break;
17641 : case AMDGPU::ArrayBase477: OpKind = MCK_R600_ArrayBase; break;
17642 : case AMDGPU::ArrayBase478: OpKind = MCK_R600_ArrayBase; break;
17643 : case AMDGPU::ArrayBase479: OpKind = MCK_R600_ArrayBase; break;
17644 : case AMDGPU::ArrayBase480: OpKind = MCK_R600_ArrayBase; break;
17645 : case AMDGPU::OQA: OpKind = MCK_R600_LDS_SRC_REG; break;
17646 : case AMDGPU::OQB: OpKind = MCK_R600_LDS_SRC_REG; break;
17647 : case AMDGPU::OQAP: OpKind = MCK_Reg34; break;
17648 : case AMDGPU::OQBP: OpKind = MCK_R600_LDS_SRC_REG; break;
17649 : case AMDGPU::LDS_DIRECT_A: OpKind = MCK_R600_LDS_SRC_REG; break;
17650 : case AMDGPU::LDS_DIRECT_B: OpKind = MCK_R600_LDS_SRC_REG; break;
17651 : case AMDGPU::ZERO: OpKind = MCK_R600_Reg32; break;
17652 : case AMDGPU::ONE: OpKind = MCK_R600_Reg32; break;
17653 : case AMDGPU::NEG_ONE: OpKind = MCK_R600_Reg32; break;
17654 : case AMDGPU::ONE_INT: OpKind = MCK_R600_Reg32; break;
17655 : case AMDGPU::HALF: OpKind = MCK_R600_Reg32; break;
17656 : case AMDGPU::NEG_HALF: OpKind = MCK_R600_Reg32; break;
17657 : case AMDGPU::ALU_LITERAL_X: OpKind = MCK_R600_Reg32; break;
17658 : case AMDGPU::PV_X: OpKind = MCK_R600_Reg32; break;
17659 : case AMDGPU::PREDICATE_BIT: OpKind = MCK_R600_Predicate_Bit; break;
17660 : case AMDGPU::PRED_SEL_OFF: OpKind = MCK_R600_Predicate; break;
17661 : case AMDGPU::PRED_SEL_ZERO: OpKind = MCK_R600_Predicate; break;
17662 : case AMDGPU::PRED_SEL_ONE: OpKind = MCK_R600_Predicate; break;
17663 : case AMDGPU::AR_X: OpKind = MCK_R600_TReg32_X; break;
17664 : case AMDGPU::ALU_CONST: OpKind = MCK_R600_Reg32; break;
17665 : case AMDGPU::ALU_PARAM: OpKind = MCK_R600_Reg32; break;
17666 : case AMDGPU::VCC_LO: OpKind = MCK_SReg_32; break;
17667 : case AMDGPU::VCC_HI: OpKind = MCK_SReg_32; break;
17668 : case AMDGPU::VCC: OpKind = MCK_VCCReg; break;
17669 : case AMDGPU::EXEC_LO: OpKind = MCK_SReg_32; break;
17670 : case AMDGPU::EXEC_HI: OpKind = MCK_SReg_32; break;
17671 : case AMDGPU::EXEC: OpKind = MCK_EXECReg; break;
17672 : case AMDGPU::SCC: OpKind = MCK_SCCReg; break;
17673 : case AMDGPU::M0: OpKind = MCK_M0; break;
17674 : case AMDGPU::FLAT_SCR_LO: OpKind = MCK_SReg_32; break;
17675 : case AMDGPU::FLAT_SCR_HI: OpKind = MCK_SReg_32; break;
17676 : case AMDGPU::FLAT_SCR: OpKind = MCK_SReg_64; break;
17677 : case AMDGPU::SGPR0: OpKind = MCK_SGPR_32; break;
17678 : case AMDGPU::SGPR1: OpKind = MCK_SGPR_32; break;
17679 : case AMDGPU::SGPR2: OpKind = MCK_SGPR_32; break;
17680 : case AMDGPU::SGPR3: OpKind = MCK_SGPR_32; break;
17681 : case AMDGPU::SGPR4: OpKind = MCK_SGPR_32; break;
17682 : case AMDGPU::SGPR5: OpKind = MCK_SGPR_32; break;
17683 : case AMDGPU::SGPR6: OpKind = MCK_SGPR_32; break;
17684 : case AMDGPU::SGPR7: OpKind = MCK_SGPR_32; break;
17685 : case AMDGPU::SGPR8: OpKind = MCK_SGPR_32; break;
17686 : case AMDGPU::SGPR9: OpKind = MCK_SGPR_32; break;
17687 : case AMDGPU::SGPR10: OpKind = MCK_SGPR_32; break;
17688 : case AMDGPU::SGPR11: OpKind = MCK_SGPR_32; break;
17689 : case AMDGPU::SGPR12: OpKind = MCK_SGPR_32; break;
17690 : case AMDGPU::SGPR13: OpKind = MCK_SGPR_32; break;
17691 : case AMDGPU::SGPR14: OpKind = MCK_SGPR_32; break;
17692 : case AMDGPU::SGPR15: OpKind = MCK_SGPR_32; break;
17693 : case AMDGPU::SGPR16: OpKind = MCK_SGPR_32; break;
17694 : case AMDGPU::SGPR17: OpKind = MCK_SGPR_32; break;
17695 : case AMDGPU::SGPR18: OpKind = MCK_SGPR_32; break;
17696 : case AMDGPU::SGPR19: OpKind = MCK_SGPR_32; break;
17697 : case AMDGPU::SGPR20: OpKind = MCK_SGPR_32; break;
17698 : case AMDGPU::SGPR21: OpKind = MCK_SGPR_32; break;
17699 : case AMDGPU::SGPR22: OpKind = MCK_SGPR_32; break;
17700 : case AMDGPU::SGPR23: OpKind = MCK_SGPR_32; break;
17701 : case AMDGPU::SGPR24: OpKind = MCK_SGPR_32; break;
17702 : case AMDGPU::SGPR25: OpKind = MCK_SGPR_32; break;
17703 : case AMDGPU::SGPR26: OpKind = MCK_SGPR_32; break;
17704 : case AMDGPU::SGPR27: OpKind = MCK_SGPR_32; break;
17705 : case AMDGPU::SGPR28: OpKind = MCK_SGPR_32; break;
17706 : case AMDGPU::SGPR29: OpKind = MCK_SGPR_32; break;
17707 : case AMDGPU::SGPR30: OpKind = MCK_SGPR_32; break;
17708 : case AMDGPU::SGPR31: OpKind = MCK_SGPR_32; break;
17709 : case AMDGPU::SGPR32: OpKind = MCK_SGPR_32; break;
17710 : case AMDGPU::SGPR33: OpKind = MCK_SGPR_32; break;
17711 : case AMDGPU::SGPR34: OpKind = MCK_SGPR_32; break;
17712 : case AMDGPU::SGPR35: OpKind = MCK_SGPR_32; break;
17713 : case AMDGPU::SGPR36: OpKind = MCK_SGPR_32; break;
17714 : case AMDGPU::SGPR37: OpKind = MCK_SGPR_32; break;
17715 : case AMDGPU::SGPR38: OpKind = MCK_SGPR_32; break;
17716 : case AMDGPU::SGPR39: OpKind = MCK_SGPR_32; break;
17717 : case AMDGPU::SGPR40: OpKind = MCK_SGPR_32; break;
17718 : case AMDGPU::SGPR41: OpKind = MCK_SGPR_32; break;
17719 : case AMDGPU::SGPR42: OpKind = MCK_SGPR_32; break;
17720 : case AMDGPU::SGPR43: OpKind = MCK_SGPR_32; break;
17721 : case AMDGPU::SGPR44: OpKind = MCK_SGPR_32; break;
17722 : case AMDGPU::SGPR45: OpKind = MCK_SGPR_32; break;
17723 : case AMDGPU::SGPR46: OpKind = MCK_SGPR_32; break;
17724 : case AMDGPU::SGPR47: OpKind = MCK_SGPR_32; break;
17725 : case AMDGPU::SGPR48: OpKind = MCK_SGPR_32; break;
17726 : case AMDGPU::SGPR49: OpKind = MCK_SGPR_32; break;
17727 : case AMDGPU::SGPR50: OpKind = MCK_SGPR_32; break;
17728 : case AMDGPU::SGPR51: OpKind = MCK_SGPR_32; break;
17729 : case AMDGPU::SGPR52: OpKind = MCK_SGPR_32; break;
17730 : case AMDGPU::SGPR53: OpKind = MCK_SGPR_32; break;
17731 : case AMDGPU::SGPR54: OpKind = MCK_SGPR_32; break;
17732 : case AMDGPU::SGPR55: OpKind = MCK_SGPR_32; break;
17733 : case AMDGPU::SGPR56: OpKind = MCK_SGPR_32; break;
17734 : case AMDGPU::SGPR57: OpKind = MCK_SGPR_32; break;
17735 : case AMDGPU::SGPR58: OpKind = MCK_SGPR_32; break;
17736 : case AMDGPU::SGPR59: OpKind = MCK_SGPR_32; break;
17737 : case AMDGPU::SGPR60: OpKind = MCK_SGPR_32; break;
17738 : case AMDGPU::SGPR61: OpKind = MCK_SGPR_32; break;
17739 : case AMDGPU::SGPR62: OpKind = MCK_SGPR_32; break;
17740 : case AMDGPU::SGPR63: OpKind = MCK_SGPR_32; break;
17741 : case AMDGPU::SGPR64: OpKind = MCK_SGPR_32; break;
17742 : case AMDGPU::SGPR65: OpKind = MCK_SGPR_32; break;
17743 : case AMDGPU::SGPR66: OpKind = MCK_SGPR_32; break;
17744 : case AMDGPU::SGPR67: OpKind = MCK_SGPR_32; break;
17745 : case AMDGPU::SGPR68: OpKind = MCK_SGPR_32; break;
17746 : case AMDGPU::SGPR69: OpKind = MCK_SGPR_32; break;
17747 : case AMDGPU::SGPR70: OpKind = MCK_SGPR_32; break;
17748 : case AMDGPU::SGPR71: OpKind = MCK_SGPR_32; break;
17749 : case AMDGPU::SGPR72: OpKind = MCK_SGPR_32; break;
17750 : case AMDGPU::SGPR73: OpKind = MCK_SGPR_32; break;
17751 : case AMDGPU::SGPR74: OpKind = MCK_SGPR_32; break;
17752 : case AMDGPU::SGPR75: OpKind = MCK_SGPR_32; break;
17753 : case AMDGPU::SGPR76: OpKind = MCK_SGPR_32; break;
17754 : case AMDGPU::SGPR77: OpKind = MCK_SGPR_32; break;
17755 : case AMDGPU::SGPR78: OpKind = MCK_SGPR_32; break;
17756 : case AMDGPU::SGPR79: OpKind = MCK_SGPR_32; break;
17757 : case AMDGPU::SGPR80: OpKind = MCK_SGPR_32; break;
17758 : case AMDGPU::SGPR81: OpKind = MCK_SGPR_32; break;
17759 : case AMDGPU::SGPR82: OpKind = MCK_SGPR_32; break;
17760 : case AMDGPU::SGPR83: OpKind = MCK_SGPR_32; break;
17761 : case AMDGPU::SGPR84: OpKind = MCK_SGPR_32; break;
17762 : case AMDGPU::SGPR85: OpKind = MCK_SGPR_32; break;
17763 : case AMDGPU::SGPR86: OpKind = MCK_SGPR_32; break;
17764 : case AMDGPU::SGPR87: OpKind = MCK_SGPR_32; break;
17765 : case AMDGPU::SGPR88: OpKind = MCK_SGPR_32; break;
17766 : case AMDGPU::SGPR89: OpKind = MCK_SGPR_32; break;
17767 : case AMDGPU::SGPR90: OpKind = MCK_SGPR_32; break;
17768 : case AMDGPU::SGPR91: OpKind = MCK_SGPR_32; break;
17769 : case AMDGPU::SGPR92: OpKind = MCK_SGPR_32; break;
17770 : case AMDGPU::SGPR93: OpKind = MCK_SGPR_32; break;
17771 : case AMDGPU::SGPR94: OpKind = MCK_SGPR_32; break;
17772 : case AMDGPU::SGPR95: OpKind = MCK_SGPR_32; break;
17773 : case AMDGPU::SGPR96: OpKind = MCK_SGPR_32; break;
17774 : case AMDGPU::SGPR97: OpKind = MCK_SGPR_32; break;
17775 : case AMDGPU::SGPR98: OpKind = MCK_SGPR_32; break;
17776 : case AMDGPU::SGPR99: OpKind = MCK_SGPR_32; break;
17777 : case AMDGPU::SGPR100: OpKind = MCK_SGPR_32; break;
17778 : case AMDGPU::SGPR101: OpKind = MCK_SGPR_32; break;
17779 : case AMDGPU::VGPR0: OpKind = MCK_VGPR_32; break;
17780 : case AMDGPU::VGPR1: OpKind = MCK_VGPR_32; break;
17781 : case AMDGPU::VGPR2: OpKind = MCK_VGPR_32; break;
17782 : case AMDGPU::VGPR3: OpKind = MCK_VGPR_32; break;
17783 : case AMDGPU::VGPR4: OpKind = MCK_VGPR_32; break;
17784 : case AMDGPU::VGPR5: OpKind = MCK_VGPR_32; break;
17785 : case AMDGPU::VGPR6: OpKind = MCK_VGPR_32; break;
17786 : case AMDGPU::VGPR7: OpKind = MCK_VGPR_32; break;
17787 : case AMDGPU::VGPR8: OpKind = MCK_VGPR_32; break;
17788 : case AMDGPU::VGPR9: OpKind = MCK_VGPR_32; break;
17789 : case AMDGPU::VGPR10: OpKind = MCK_VGPR_32; break;
17790 : case AMDGPU::VGPR11: OpKind = MCK_VGPR_32; break;
17791 : case AMDGPU::VGPR12: OpKind = MCK_VGPR_32; break;
17792 : case AMDGPU::VGPR13: OpKind = MCK_VGPR_32; break;
17793 : case AMDGPU::VGPR14: OpKind = MCK_VGPR_32; break;
17794 : case AMDGPU::VGPR15: OpKind = MCK_VGPR_32; break;
17795 : case AMDGPU::VGPR16: OpKind = MCK_VGPR_32; break;
17796 : case AMDGPU::VGPR17: OpKind = MCK_VGPR_32; break;
17797 : case AMDGPU::VGPR18: OpKind = MCK_VGPR_32; break;
17798 : case AMDGPU::VGPR19: OpKind = MCK_VGPR_32; break;
17799 : case AMDGPU::VGPR20: OpKind = MCK_VGPR_32; break;
17800 : case AMDGPU::VGPR21: OpKind = MCK_VGPR_32; break;
17801 : case AMDGPU::VGPR22: OpKind = MCK_VGPR_32; break;
17802 : case AMDGPU::VGPR23: OpKind = MCK_VGPR_32; break;
17803 : case AMDGPU::VGPR24: OpKind = MCK_VGPR_32; break;
17804 : case AMDGPU::VGPR25: OpKind = MCK_VGPR_32; break;
17805 : case AMDGPU::VGPR26: OpKind = MCK_VGPR_32; break;
17806 : case AMDGPU::VGPR27: OpKind = MCK_VGPR_32; break;
17807 : case AMDGPU::VGPR28: OpKind = MCK_VGPR_32; break;
17808 : case AMDGPU::VGPR29: OpKind = MCK_VGPR_32; break;
17809 : case AMDGPU::VGPR30: OpKind = MCK_VGPR_32; break;
17810 : case AMDGPU::VGPR31: OpKind = MCK_VGPR_32; break;
17811 : case AMDGPU::VGPR32: OpKind = MCK_VGPR_32; break;
17812 : case AMDGPU::VGPR33: OpKind = MCK_VGPR_32; break;
17813 : case AMDGPU::VGPR34: OpKind = MCK_VGPR_32; break;
17814 : case AMDGPU::VGPR35: OpKind = MCK_VGPR_32; break;
17815 : case AMDGPU::VGPR36: OpKind = MCK_VGPR_32; break;
17816 : case AMDGPU::VGPR37: OpKind = MCK_VGPR_32; break;
17817 : case AMDGPU::VGPR38: OpKind = MCK_VGPR_32; break;
17818 : case AMDGPU::VGPR39: OpKind = MCK_VGPR_32; break;
17819 : case AMDGPU::VGPR40: OpKind = MCK_VGPR_32; break;
17820 : case AMDGPU::VGPR41: OpKind = MCK_VGPR_32; break;
17821 : case AMDGPU::VGPR42: OpKind = MCK_VGPR_32; break;
17822 : case AMDGPU::VGPR43: OpKind = MCK_VGPR_32; break;
17823 : case AMDGPU::VGPR44: OpKind = MCK_VGPR_32; break;
17824 : case AMDGPU::VGPR45: OpKind = MCK_VGPR_32; break;
17825 : case AMDGPU::VGPR46: OpKind = MCK_VGPR_32; break;
17826 : case AMDGPU::VGPR47: OpKind = MCK_VGPR_32; break;
17827 : case AMDGPU::VGPR48: OpKind = MCK_VGPR_32; break;
17828 : case AMDGPU::VGPR49: OpKind = MCK_VGPR_32; break;
17829 : case AMDGPU::VGPR50: OpKind = MCK_VGPR_32; break;
17830 : case AMDGPU::VGPR51: OpKind = MCK_VGPR_32; break;
17831 : case AMDGPU::VGPR52: OpKind = MCK_VGPR_32; break;
17832 : case AMDGPU::VGPR53: OpKind = MCK_VGPR_32; break;
17833 : case AMDGPU::VGPR54: OpKind = MCK_VGPR_32; break;
17834 : case AMDGPU::VGPR55: OpKind = MCK_VGPR_32; break;
17835 : case AMDGPU::VGPR56: OpKind = MCK_VGPR_32; break;
17836 : case AMDGPU::VGPR57: OpKind = MCK_VGPR_32; break;
17837 : case AMDGPU::VGPR58: OpKind = MCK_VGPR_32; break;
17838 : case AMDGPU::VGPR59: OpKind = MCK_VGPR_32; break;
17839 : case AMDGPU::VGPR60: OpKind = MCK_VGPR_32; break;
17840 : case AMDGPU::VGPR61: OpKind = MCK_VGPR_32; break;
17841 : case AMDGPU::VGPR62: OpKind = MCK_VGPR_32; break;
17842 : case AMDGPU::VGPR63: OpKind = MCK_VGPR_32; break;
17843 : case AMDGPU::VGPR64: OpKind = MCK_VGPR_32; break;
17844 : case AMDGPU::VGPR65: OpKind = MCK_VGPR_32; break;
17845 : case AMDGPU::VGPR66: OpKind = MCK_VGPR_32; break;
17846 : case AMDGPU::VGPR67: OpKind = MCK_VGPR_32; break;
17847 : case AMDGPU::VGPR68: OpKind = MCK_VGPR_32; break;
17848 : case AMDGPU::VGPR69: OpKind = MCK_VGPR_32; break;
17849 : case AMDGPU::VGPR70: OpKind = MCK_VGPR_32; break;
17850 : case AMDGPU::VGPR71: OpKind = MCK_VGPR_32; break;
17851 : case AMDGPU::VGPR72: OpKind = MCK_VGPR_32; break;
17852 : case AMDGPU::VGPR73: OpKind = MCK_VGPR_32; break;
17853 : case AMDGPU::VGPR74: OpKind = MCK_VGPR_32; break;
17854 : case AMDGPU::VGPR75: OpKind = MCK_VGPR_32; break;
17855 : case AMDGPU::VGPR76: OpKind = MCK_VGPR_32; break;
17856 : case AMDGPU::VGPR77: OpKind = MCK_VGPR_32; break;
17857 : case AMDGPU::VGPR78: OpKind = MCK_VGPR_32; break;
17858 : case AMDGPU::VGPR79: OpKind = MCK_VGPR_32; break;
17859 : case AMDGPU::VGPR80: OpKind = MCK_VGPR_32; break;
17860 : case AMDGPU::VGPR81: OpKind = MCK_VGPR_32; break;
17861 : case AMDGPU::VGPR82: OpKind = MCK_VGPR_32; break;
17862 : case AMDGPU::VGPR83: OpKind = MCK_VGPR_32; break;
17863 : case AMDGPU::VGPR84: OpKind = MCK_VGPR_32; break;
17864 : case AMDGPU::VGPR85: OpKind = MCK_VGPR_32; break;
17865 : case AMDGPU::VGPR86: OpKind = MCK_VGPR_32; break;
17866 : case AMDGPU::VGPR87: OpKind = MCK_VGPR_32; break;
17867 : case AMDGPU::VGPR88: OpKind = MCK_VGPR_32; break;
17868 : case AMDGPU::VGPR89: OpKind = MCK_VGPR_32; break;
17869 : case AMDGPU::VGPR90: OpKind = MCK_VGPR_32; break;
17870 : case AMDGPU::VGPR91: OpKind = MCK_VGPR_32; break;
17871 : case AMDGPU::VGPR92: OpKind = MCK_VGPR_32; break;
17872 : case AMDGPU::VGPR93: OpKind = MCK_VGPR_32; break;
17873 : case AMDGPU::VGPR94: OpKind = MCK_VGPR_32; break;
17874 : case AMDGPU::VGPR95: OpKind = MCK_VGPR_32; break;
17875 : case AMDGPU::VGPR96: OpKind = MCK_VGPR_32; break;
17876 : case AMDGPU::VGPR97: OpKind = MCK_VGPR_32; break;
17877 : case AMDGPU::VGPR98: OpKind = MCK_VGPR_32; break;
17878 : case AMDGPU::VGPR99: OpKind = MCK_VGPR_32; break;
17879 : case AMDGPU::VGPR100: OpKind = MCK_VGPR_32; break;
17880 : case AMDGPU::VGPR101: OpKind = MCK_VGPR_32; break;
17881 : case AMDGPU::VGPR102: OpKind = MCK_VGPR_32; break;
17882 : case AMDGPU::VGPR103: OpKind = MCK_VGPR_32; break;
17883 : case AMDGPU::VGPR104: OpKind = MCK_VGPR_32; break;
17884 : case AMDGPU::VGPR105: OpKind = MCK_VGPR_32; break;
17885 : case AMDGPU::VGPR106: OpKind = MCK_VGPR_32; break;
17886 : case AMDGPU::VGPR107: OpKind = MCK_VGPR_32; break;
17887 : case AMDGPU::VGPR108: OpKind = MCK_VGPR_32; break;
17888 : case AMDGPU::VGPR109: OpKind = MCK_VGPR_32; break;
17889 : case AMDGPU::VGPR110: OpKind = MCK_VGPR_32; break;
17890 : case AMDGPU::VGPR111: OpKind = MCK_VGPR_32; break;
17891 : case AMDGPU::VGPR112: OpKind = MCK_VGPR_32; break;
17892 : case AMDGPU::VGPR113: OpKind = MCK_VGPR_32; break;
17893 : case AMDGPU::VGPR114: OpKind = MCK_VGPR_32; break;
17894 : case AMDGPU::VGPR115: OpKind = MCK_VGPR_32; break;
17895 : case AMDGPU::VGPR116: OpKind = MCK_VGPR_32; break;
17896 : case AMDGPU::VGPR117: OpKind = MCK_VGPR_32; break;
17897 : case AMDGPU::VGPR118: OpKind = MCK_VGPR_32; break;
17898 : case AMDGPU::VGPR119: OpKind = MCK_VGPR_32; break;
17899 : case AMDGPU::VGPR120: OpKind = MCK_VGPR_32; break;
17900 : case AMDGPU::VGPR121: OpKind = MCK_VGPR_32; break;
17901 : case AMDGPU::VGPR122: OpKind = MCK_VGPR_32; break;
17902 : case AMDGPU::VGPR123: OpKind = MCK_VGPR_32; break;
17903 : case AMDGPU::VGPR124: OpKind = MCK_VGPR_32; break;
17904 : case AMDGPU::VGPR125: OpKind = MCK_VGPR_32; break;
17905 : case AMDGPU::VGPR126: OpKind = MCK_VGPR_32; break;
17906 : case AMDGPU::VGPR127: OpKind = MCK_VGPR_32; break;
17907 : case AMDGPU::VGPR128: OpKind = MCK_VGPR_32; break;
17908 : case AMDGPU::VGPR129: OpKind = MCK_VGPR_32; break;
17909 : case AMDGPU::VGPR130: OpKind = MCK_VGPR_32; break;
17910 : case AMDGPU::VGPR131: OpKind = MCK_VGPR_32; break;
17911 : case AMDGPU::VGPR132: OpKind = MCK_VGPR_32; break;
17912 : case AMDGPU::VGPR133: OpKind = MCK_VGPR_32; break;
17913 : case AMDGPU::VGPR134: OpKind = MCK_VGPR_32; break;
17914 : case AMDGPU::VGPR135: OpKind = MCK_VGPR_32; break;
17915 : case AMDGPU::VGPR136: OpKind = MCK_VGPR_32; break;
17916 : case AMDGPU::VGPR137: OpKind = MCK_VGPR_32; break;
17917 : case AMDGPU::VGPR138: OpKind = MCK_VGPR_32; break;
17918 : case AMDGPU::VGPR139: OpKind = MCK_VGPR_32; break;
17919 : case AMDGPU::VGPR140: OpKind = MCK_VGPR_32; break;
17920 : case AMDGPU::VGPR141: OpKind = MCK_VGPR_32; break;
17921 : case AMDGPU::VGPR142: OpKind = MCK_VGPR_32; break;
17922 : case AMDGPU::VGPR143: OpKind = MCK_VGPR_32; break;
17923 : case AMDGPU::VGPR144: OpKind = MCK_VGPR_32; break;
17924 : case AMDGPU::VGPR145: OpKind = MCK_VGPR_32; break;
17925 : case AMDGPU::VGPR146: OpKind = MCK_VGPR_32; break;
17926 : case AMDGPU::VGPR147: OpKind = MCK_VGPR_32; break;
17927 : case AMDGPU::VGPR148: OpKind = MCK_VGPR_32; break;
17928 : case AMDGPU::VGPR149: OpKind = MCK_VGPR_32; break;
17929 : case AMDGPU::VGPR150: OpKind = MCK_VGPR_32; break;
17930 : case AMDGPU::VGPR151: OpKind = MCK_VGPR_32; break;
17931 : case AMDGPU::VGPR152: OpKind = MCK_VGPR_32; break;
17932 : case AMDGPU::VGPR153: OpKind = MCK_VGPR_32; break;
17933 : case AMDGPU::VGPR154: OpKind = MCK_VGPR_32; break;
17934 : case AMDGPU::VGPR155: OpKind = MCK_VGPR_32; break;
17935 : case AMDGPU::VGPR156: OpKind = MCK_VGPR_32; break;
17936 : case AMDGPU::VGPR157: OpKind = MCK_VGPR_32; break;
17937 : case AMDGPU::VGPR158: OpKind = MCK_VGPR_32; break;
17938 : case AMDGPU::VGPR159: OpKind = MCK_VGPR_32; break;
17939 : case AMDGPU::VGPR160: OpKind = MCK_VGPR_32; break;
17940 : case AMDGPU::VGPR161: OpKind = MCK_VGPR_32; break;
17941 : case AMDGPU::VGPR162: OpKind = MCK_VGPR_32; break;
17942 : case AMDGPU::VGPR163: OpKind = MCK_VGPR_32; break;
17943 : case AMDGPU::VGPR164: OpKind = MCK_VGPR_32; break;
17944 : case AMDGPU::VGPR165: OpKind = MCK_VGPR_32; break;
17945 : case AMDGPU::VGPR166: OpKind = MCK_VGPR_32; break;
17946 : case AMDGPU::VGPR167: OpKind = MCK_VGPR_32; break;
17947 : case AMDGPU::VGPR168: OpKind = MCK_VGPR_32; break;
17948 : case AMDGPU::VGPR169: OpKind = MCK_VGPR_32; break;
17949 : case AMDGPU::VGPR170: OpKind = MCK_VGPR_32; break;
17950 : case AMDGPU::VGPR171: OpKind = MCK_VGPR_32; break;
17951 : case AMDGPU::VGPR172: OpKind = MCK_VGPR_32; break;
17952 : case AMDGPU::VGPR173: OpKind = MCK_VGPR_32; break;
17953 : case AMDGPU::VGPR174: OpKind = MCK_VGPR_32; break;
17954 : case AMDGPU::VGPR175: OpKind = MCK_VGPR_32; break;
17955 : case AMDGPU::VGPR176: OpKind = MCK_VGPR_32; break;
17956 : case AMDGPU::VGPR177: OpKind = MCK_VGPR_32; break;
17957 : case AMDGPU::VGPR178: OpKind = MCK_VGPR_32; break;
17958 : case AMDGPU::VGPR179: OpKind = MCK_VGPR_32; break;
17959 : case AMDGPU::VGPR180: OpKind = MCK_VGPR_32; break;
17960 : case AMDGPU::VGPR181: OpKind = MCK_VGPR_32; break;
17961 : case AMDGPU::VGPR182: OpKind = MCK_VGPR_32; break;
17962 : case AMDGPU::VGPR183: OpKind = MCK_VGPR_32; break;
17963 : case AMDGPU::VGPR184: OpKind = MCK_VGPR_32; break;
17964 : case AMDGPU::VGPR185: OpKind = MCK_VGPR_32; break;
17965 : case AMDGPU::VGPR186: OpKind = MCK_VGPR_32; break;
17966 : case AMDGPU::VGPR187: OpKind = MCK_VGPR_32; break;
17967 : case AMDGPU::VGPR188: OpKind = MCK_VGPR_32; break;
17968 : case AMDGPU::VGPR189: OpKind = MCK_VGPR_32; break;
17969 : case AMDGPU::VGPR190: OpKind = MCK_VGPR_32; break;
17970 : case AMDGPU::VGPR191: OpKind = MCK_VGPR_32; break;
17971 : case AMDGPU::VGPR192: OpKind = MCK_VGPR_32; break;
17972 : case AMDGPU::VGPR193: OpKind = MCK_VGPR_32; break;
17973 : case AMDGPU::VGPR194: OpKind = MCK_VGPR_32; break;
17974 : case AMDGPU::VGPR195: OpKind = MCK_VGPR_32; break;
17975 : case AMDGPU::VGPR196: OpKind = MCK_VGPR_32; break;
17976 : case AMDGPU::VGPR197: OpKind = MCK_VGPR_32; break;
17977 : case AMDGPU::VGPR198: OpKind = MCK_VGPR_32; break;
17978 : case AMDGPU::VGPR199: OpKind = MCK_VGPR_32; break;
17979 : case AMDGPU::VGPR200: OpKind = MCK_VGPR_32; break;
17980 : case AMDGPU::VGPR201: OpKind = MCK_VGPR_32; break;
17981 : case AMDGPU::VGPR202: OpKind = MCK_VGPR_32; break;
17982 : case AMDGPU::VGPR203: OpKind = MCK_VGPR_32; break;
17983 : case AMDGPU::VGPR204: OpKind = MCK_VGPR_32; break;
17984 : case AMDGPU::VGPR205: OpKind = MCK_VGPR_32; break;
17985 : case AMDGPU::VGPR206: OpKind = MCK_VGPR_32; break;
17986 : case AMDGPU::VGPR207: OpKind = MCK_VGPR_32; break;
17987 : case AMDGPU::VGPR208: OpKind = MCK_VGPR_32; break;
17988 : case AMDGPU::VGPR209: OpKind = MCK_VGPR_32; break;
17989 : case AMDGPU::VGPR210: OpKind = MCK_VGPR_32; break;
17990 : case AMDGPU::VGPR211: OpKind = MCK_VGPR_32; break;
17991 : case AMDGPU::VGPR212: OpKind = MCK_VGPR_32; break;
17992 : case AMDGPU::VGPR213: OpKind = MCK_VGPR_32; break;
17993 : case AMDGPU::VGPR214: OpKind = MCK_VGPR_32; break;
17994 : case AMDGPU::VGPR215: OpKind = MCK_VGPR_32; break;
17995 : case AMDGPU::VGPR216: OpKind = MCK_VGPR_32; break;
17996 : case AMDGPU::VGPR217: OpKind = MCK_VGPR_32; break;
17997 : case AMDGPU::VGPR218: OpKind = MCK_VGPR_32; break;
17998 : case AMDGPU::VGPR219: OpKind = MCK_VGPR_32; break;
17999 : case AMDGPU::VGPR220: OpKind = MCK_VGPR_32; break;
18000 : case AMDGPU::VGPR221: OpKind = MCK_VGPR_32; break;
18001 : case AMDGPU::VGPR222: OpKind = MCK_VGPR_32; break;
18002 : case AMDGPU::VGPR223: OpKind = MCK_VGPR_32; break;
18003 : case AMDGPU::VGPR224: OpKind = MCK_VGPR_32; break;
18004 : case AMDGPU::VGPR225: OpKind = MCK_VGPR_32; break;
18005 : case AMDGPU::VGPR226: OpKind = MCK_VGPR_32; break;
18006 : case AMDGPU::VGPR227: OpKind = MCK_VGPR_32; break;
18007 : case AMDGPU::VGPR228: OpKind = MCK_VGPR_32; break;
18008 : case AMDGPU::VGPR229: OpKind = MCK_VGPR_32; break;
18009 : case AMDGPU::VGPR230: OpKind = MCK_VGPR_32; break;
18010 : case AMDGPU::VGPR231: OpKind = MCK_VGPR_32; break;
18011 : case AMDGPU::VGPR232: OpKind = MCK_VGPR_32; break;
18012 : case AMDGPU::VGPR233: OpKind = MCK_VGPR_32; break;
18013 : case AMDGPU::VGPR234: OpKind = MCK_VGPR_32; break;
18014 : case AMDGPU::VGPR235: OpKind = MCK_VGPR_32; break;
18015 : case AMDGPU::VGPR236: OpKind = MCK_VGPR_32; break;
18016 : case AMDGPU::VGPR237: OpKind = MCK_VGPR_32; break;
18017 : case AMDGPU::VGPR238: OpKind = MCK_VGPR_32; break;
18018 : case AMDGPU::VGPR239: OpKind = MCK_VGPR_32; break;
18019 : case AMDGPU::VGPR240: OpKind = MCK_VGPR_32; break;
18020 : case AMDGPU::VGPR241: OpKind = MCK_VGPR_32; break;
18021 : case AMDGPU::VGPR242: OpKind = MCK_VGPR_32; break;
18022 : case AMDGPU::VGPR243: OpKind = MCK_VGPR_32; break;
18023 : case AMDGPU::VGPR244: OpKind = MCK_VGPR_32; break;
18024 : case AMDGPU::VGPR245: OpKind = MCK_VGPR_32; break;
18025 : case AMDGPU::VGPR246: OpKind = MCK_VGPR_32; break;
18026 : case AMDGPU::VGPR247: OpKind = MCK_VGPR_32; break;
18027 : case AMDGPU::VGPR248: OpKind = MCK_VGPR_32; break;
18028 : case AMDGPU::VGPR249: OpKind = MCK_VGPR_32; break;
18029 : case AMDGPU::VGPR250: OpKind = MCK_VGPR_32; break;
18030 : case AMDGPU::VGPR251: OpKind = MCK_VGPR_32; break;
18031 : case AMDGPU::VGPR252: OpKind = MCK_VGPR_32; break;
18032 : case AMDGPU::VGPR253: OpKind = MCK_VGPR_32; break;
18033 : case AMDGPU::VGPR254: OpKind = MCK_VGPR_32; break;
18034 : case AMDGPU::VGPR255: OpKind = MCK_VGPR_32; break;
18035 : case AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3: OpKind = MCK_SReg_128; break;
18036 : case AMDGPU::SGPR4_SGPR5_SGPR6_SGPR7: OpKind = MCK_SReg_128; break;
18037 : case AMDGPU::SGPR8_SGPR9_SGPR10_SGPR11: OpKind = MCK_SReg_128; break;
18038 : case AMDGPU::SGPR12_SGPR13_SGPR14_SGPR15: OpKind = MCK_SReg_128; break;
18039 : case AMDGPU::SGPR16_SGPR17_SGPR18_SGPR19: OpKind = MCK_SReg_128; break;
18040 : case AMDGPU::SGPR20_SGPR21_SGPR22_SGPR23: OpKind = MCK_SReg_128; break;
18041 : case AMDGPU::SGPR24_SGPR25_SGPR26_SGPR27: OpKind = MCK_SReg_128; break;
18042 : case AMDGPU::SGPR28_SGPR29_SGPR30_SGPR31: OpKind = MCK_SReg_128; break;
18043 : case AMDGPU::SGPR32_SGPR33_SGPR34_SGPR35: OpKind = MCK_SReg_128; break;
18044 : case AMDGPU::SGPR36_SGPR37_SGPR38_SGPR39: OpKind = MCK_SReg_128; break;
18045 : case AMDGPU::SGPR40_SGPR41_SGPR42_SGPR43: OpKind = MCK_SReg_128; break;
18046 : case AMDGPU::SGPR44_SGPR45_SGPR46_SGPR47: OpKind = MCK_SReg_128; break;
18047 : case AMDGPU::SGPR48_SGPR49_SGPR50_SGPR51: OpKind = MCK_SReg_128; break;
18048 : case AMDGPU::SGPR52_SGPR53_SGPR54_SGPR55: OpKind = MCK_SReg_128; break;
18049 : case AMDGPU::SGPR56_SGPR57_SGPR58_SGPR59: OpKind = MCK_SReg_128; break;
18050 : case AMDGPU::SGPR60_SGPR61_SGPR62_SGPR63: OpKind = MCK_SReg_128; break;
18051 : case AMDGPU::SGPR64_SGPR65_SGPR66_SGPR67: OpKind = MCK_SReg_128; break;
18052 : case AMDGPU::SGPR68_SGPR69_SGPR70_SGPR71: OpKind = MCK_SReg_128; break;
18053 : case AMDGPU::SGPR72_SGPR73_SGPR74_SGPR75: OpKind = MCK_SReg_128; break;
18054 : case AMDGPU::SGPR76_SGPR77_SGPR78_SGPR79: OpKind = MCK_SReg_128; break;
18055 : case AMDGPU::SGPR80_SGPR81_SGPR82_SGPR83: OpKind = MCK_SReg_128; break;
18056 : case AMDGPU::SGPR84_SGPR85_SGPR86_SGPR87: OpKind = MCK_SReg_128; break;
18057 : case AMDGPU::SGPR88_SGPR89_SGPR90_SGPR91: OpKind = MCK_SReg_128; break;
18058 : case AMDGPU::SGPR92_SGPR93_SGPR94_SGPR95: OpKind = MCK_SReg_128; break;
18059 : case AMDGPU::SGPR96_SGPR97_SGPR98_SGPR99: OpKind = MCK_SReg_128; break;
18060 : case AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3_SGPR4_SGPR5_SGPR6_SGPR7: OpKind = MCK_SReg_256; break;
18061 : case AMDGPU::SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11: OpKind = MCK_SReg_256; break;
18062 : case AMDGPU::SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15: OpKind = MCK_SReg_256; break;
18063 : case AMDGPU::SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19: OpKind = MCK_SReg_256; break;
18064 : case AMDGPU::SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23: OpKind = MCK_SReg_256; break;
18065 : case AMDGPU::SGPR20_SGPR21_SGPR22_SGPR23_SGPR24_SGPR25_SGPR26_SGPR27: OpKind = MCK_SReg_256; break;
18066 : case AMDGPU::SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31: OpKind = MCK_SReg_256; break;
18067 : case AMDGPU::SGPR28_SGPR29_SGPR30_SGPR31_SGPR32_SGPR33_SGPR34_SGPR35: OpKind = MCK_SReg_256; break;
18068 : case AMDGPU::SGPR32_SGPR33_SGPR34_SGPR35_SGPR36_SGPR37_SGPR38_SGPR39: OpKind = MCK_SReg_256; break;
18069 : case AMDGPU::SGPR36_SGPR37_SGPR38_SGPR39_SGPR40_SGPR41_SGPR42_SGPR43: OpKind = MCK_SReg_256; break;
18070 : case AMDGPU::SGPR40_SGPR41_SGPR42_SGPR43_SGPR44_SGPR45_SGPR46_SGPR47: OpKind = MCK_SReg_256; break;
18071 : case AMDGPU::SGPR44_SGPR45_SGPR46_SGPR47_SGPR48_SGPR49_SGPR50_SGPR51: OpKind = MCK_SReg_256; break;
18072 : case AMDGPU::SGPR48_SGPR49_SGPR50_SGPR51_SGPR52_SGPR53_SGPR54_SGPR55: OpKind = MCK_SReg_256; break;
18073 : case AMDGPU::SGPR52_SGPR53_SGPR54_SGPR55_SGPR56_SGPR57_SGPR58_SGPR59: OpKind = MCK_SReg_256; break;
18074 : case AMDGPU::SGPR56_SGPR57_SGPR58_SGPR59_SGPR60_SGPR61_SGPR62_SGPR63: OpKind = MCK_SReg_256; break;
18075 : case AMDGPU::SGPR60_SGPR61_SGPR62_SGPR63_SGPR64_SGPR65_SGPR66_SGPR67: OpKind = MCK_SReg_256; break;
18076 : case AMDGPU::SGPR64_SGPR65_SGPR66_SGPR67_SGPR68_SGPR69_SGPR70_SGPR71: OpKind = MCK_SReg_256; break;
18077 : case AMDGPU::SGPR68_SGPR69_SGPR70_SGPR71_SGPR72_SGPR73_SGPR74_SGPR75: OpKind = MCK_SReg_256; break;
18078 : case AMDGPU::SGPR72_SGPR73_SGPR74_SGPR75_SGPR76_SGPR77_SGPR78_SGPR79: OpKind = MCK_SReg_256; break;
18079 : case AMDGPU::SGPR76_SGPR77_SGPR78_SGPR79_SGPR80_SGPR81_SGPR82_SGPR83: OpKind = MCK_SReg_256; break;
18080 : case AMDGPU::SGPR80_SGPR81_SGPR82_SGPR83_SGPR84_SGPR85_SGPR86_SGPR87: OpKind = MCK_SReg_256; break;
18081 : case AMDGPU::SGPR84_SGPR85_SGPR86_SGPR87_SGPR88_SGPR89_SGPR90_SGPR91: OpKind = MCK_SReg_256; break;
18082 : case AMDGPU::SGPR88_SGPR89_SGPR90_SGPR91_SGPR92_SGPR93_SGPR94_SGPR95: OpKind = MCK_SReg_256; break;
18083 : case AMDGPU::SGPR92_SGPR93_SGPR94_SGPR95_SGPR96_SGPR97_SGPR98_SGPR99: OpKind = MCK_SReg_256; break;
18084 : case AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3_SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15: OpKind = MCK_SReg_512; break;
18085 : case AMDGPU::SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19: OpKind = MCK_SReg_512; break;
18086 : case AMDGPU::SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23: OpKind = MCK_SReg_512; break;
18087 : case AMDGPU::SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23_SGPR24_SGPR25_SGPR26_SGPR27: OpKind = MCK_SReg_512; break;
18088 : case AMDGPU::SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23_SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31: OpKind = MCK_SReg_512; break;
18089 : case AMDGPU::SGPR20_SGPR21_SGPR22_SGPR23_SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31_SGPR32_SGPR33_SGPR34_SGPR35: OpKind = MCK_SReg_512; break;
18090 : case AMDGPU::SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31_SGPR32_SGPR33_SGPR34_SGPR35_SGPR36_SGPR37_SGPR38_SGPR39: OpKind = MCK_SReg_512; break;
18091 : case AMDGPU::SGPR28_SGPR29_SGPR30_SGPR31_SGPR32_SGPR33_SGPR34_SGPR35_SGPR36_SGPR37_SGPR38_SGPR39_SGPR40_SGPR41_SGPR42_SGPR43: OpKind = MCK_SReg_512; break;
18092 : case AMDGPU::SGPR32_SGPR33_SGPR34_SGPR35_SGPR36_SGPR37_SGPR38_SGPR39_SGPR40_SGPR41_SGPR42_SGPR43_SGPR44_SGPR45_SGPR46_SGPR47: OpKind = MCK_SReg_512; break;
18093 : case AMDGPU::SGPR36_SGPR37_SGPR38_SGPR39_SGPR40_SGPR41_SGPR42_SGPR43_SGPR44_SGPR45_SGPR46_SGPR47_SGPR48_SGPR49_SGPR50_SGPR51: OpKind = MCK_SReg_512; break;
18094 : case AMDGPU::SGPR40_SGPR41_SGPR42_SGPR43_SGPR44_SGPR45_SGPR46_SGPR47_SGPR48_SGPR49_SGPR50_SGPR51_SGPR52_SGPR53_SGPR54_SGPR55: OpKind = MCK_SReg_512; break;
18095 : case AMDGPU::SGPR44_SGPR45_SGPR46_SGPR47_SGPR48_SGPR49_SGPR50_SGPR51_SGPR52_SGPR53_SGPR54_SGPR55_SGPR56_SGPR57_SGPR58_SGPR59: OpKind = MCK_SReg_512; break;
18096 : case AMDGPU::SGPR48_SGPR49_SGPR50_SGPR51_SGPR52_SGPR53_SGPR54_SGPR55_SGPR56_SGPR57_SGPR58_SGPR59_SGPR60_SGPR61_SGPR62_SGPR63: OpKind = MCK_SReg_512; break;
18097 : case AMDGPU::SGPR52_SGPR53_SGPR54_SGPR55_SGPR56_SGPR57_SGPR58_SGPR59_SGPR60_SGPR61_SGPR62_SGPR63_SGPR64_SGPR65_SGPR66_SGPR67: OpKind = MCK_SReg_512; break;
18098 : case AMDGPU::SGPR56_SGPR57_SGPR58_SGPR59_SGPR60_SGPR61_SGPR62_SGPR63_SGPR64_SGPR65_SGPR66_SGPR67_SGPR68_SGPR69_SGPR70_SGPR71: OpKind = MCK_SReg_512; break;
18099 : case AMDGPU::SGPR60_SGPR61_SGPR62_SGPR63_SGPR64_SGPR65_SGPR66_SGPR67_SGPR68_SGPR69_SGPR70_SGPR71_SGPR72_SGPR73_SGPR74_SGPR75: OpKind = MCK_SReg_512; break;
18100 : case AMDGPU::SGPR64_SGPR65_SGPR66_SGPR67_SGPR68_SGPR69_SGPR70_SGPR71_SGPR72_SGPR73_SGPR74_SGPR75_SGPR76_SGPR77_SGPR78_SGPR79: OpKind = MCK_SReg_512; break;
18101 : case AMDGPU::SGPR68_SGPR69_SGPR70_SGPR71_SGPR72_SGPR73_SGPR74_SGPR75_SGPR76_SGPR77_SGPR78_SGPR79_SGPR80_SGPR81_SGPR82_SGPR83: OpKind = MCK_SReg_512; break;
18102 : case AMDGPU::SGPR72_SGPR73_SGPR74_SGPR75_SGPR76_SGPR77_SGPR78_SGPR79_SGPR80_SGPR81_SGPR82_SGPR83_SGPR84_SGPR85_SGPR86_SGPR87: OpKind = MCK_SReg_512; break;
18103 : case AMDGPU::SGPR76_SGPR77_SGPR78_SGPR79_SGPR80_SGPR81_SGPR82_SGPR83_SGPR84_SGPR85_SGPR86_SGPR87_SGPR88_SGPR89_SGPR90_SGPR91: OpKind = MCK_SReg_512; break;
18104 : case AMDGPU::SGPR80_SGPR81_SGPR82_SGPR83_SGPR84_SGPR85_SGPR86_SGPR87_SGPR88_SGPR89_SGPR90_SGPR91_SGPR92_SGPR93_SGPR94_SGPR95: OpKind = MCK_SReg_512; break;
18105 : case AMDGPU::SGPR84_SGPR85_SGPR86_SGPR87_SGPR88_SGPR89_SGPR90_SGPR91_SGPR92_SGPR93_SGPR94_SGPR95_SGPR96_SGPR97_SGPR98_SGPR99: OpKind = MCK_SReg_512; break;
18106 : case AMDGPU::SGPR0_SGPR1: OpKind = MCK_SGPR_64; break;
18107 : case AMDGPU::SGPR2_SGPR3: OpKind = MCK_SGPR_64; break;
18108 : case AMDGPU::SGPR4_SGPR5: OpKind = MCK_SGPR_64; break;
18109 : case AMDGPU::SGPR6_SGPR7: OpKind = MCK_SGPR_64; break;
18110 : case AMDGPU::SGPR8_SGPR9: OpKind = MCK_SGPR_64; break;
18111 : case AMDGPU::SGPR10_SGPR11: OpKind = MCK_SGPR_64; break;
18112 : case AMDGPU::SGPR12_SGPR13: OpKind = MCK_SGPR_64; break;
18113 : case AMDGPU::SGPR14_SGPR15: OpKind = MCK_SGPR_64; break;
18114 : case AMDGPU::SGPR16_SGPR17: OpKind = MCK_SGPR_64; break;
18115 : case AMDGPU::SGPR18_SGPR19: OpKind = MCK_SGPR_64; break;
18116 : case AMDGPU::SGPR20_SGPR21: OpKind = MCK_SGPR_64; break;
18117 : case AMDGPU::SGPR22_SGPR23: OpKind = MCK_SGPR_64; break;
18118 : case AMDGPU::SGPR24_SGPR25: OpKind = MCK_SGPR_64; break;
18119 : case AMDGPU::SGPR26_SGPR27: OpKind = MCK_SGPR_64; break;
18120 : case AMDGPU::SGPR28_SGPR29: OpKind = MCK_SGPR_64; break;
18121 : case AMDGPU::SGPR30_SGPR31: OpKind = MCK_SGPR_64; break;
18122 : case AMDGPU::SGPR32_SGPR33: OpKind = MCK_SGPR_64; break;
18123 : case AMDGPU::SGPR34_SGPR35: OpKind = MCK_SGPR_64; break;
18124 : case AMDGPU::SGPR36_SGPR37: OpKind = MCK_SGPR_64; break;
18125 : case AMDGPU::SGPR38_SGPR39: OpKind = MCK_SGPR_64; break;
18126 : case AMDGPU::SGPR40_SGPR41: OpKind = MCK_SGPR_64; break;
18127 : case AMDGPU::SGPR42_SGPR43: OpKind = MCK_SGPR_64; break;
18128 : case AMDGPU::SGPR44_SGPR45: OpKind = MCK_SGPR_64; break;
18129 : case AMDGPU::SGPR46_SGPR47: OpKind = MCK_SGPR_64; break;
18130 : case AMDGPU::SGPR48_SGPR49: OpKind = MCK_SGPR_64; break;
18131 : case AMDGPU::SGPR50_SGPR51: OpKind = MCK_SGPR_64; break;
18132 : case AMDGPU::SGPR52_SGPR53: OpKind = MCK_SGPR_64; break;
18133 : case AMDGPU::SGPR54_SGPR55: OpKind = MCK_SGPR_64; break;
18134 : case AMDGPU::SGPR56_SGPR57: OpKind = MCK_SGPR_64; break;
18135 : case AMDGPU::SGPR58_SGPR59: OpKind = MCK_SGPR_64; break;
18136 : case AMDGPU::SGPR60_SGPR61: OpKind = MCK_SGPR_64; break;
18137 : case AMDGPU::SGPR62_SGPR63: OpKind = MCK_SGPR_64; break;
18138 : case AMDGPU::SGPR64_SGPR65: OpKind = MCK_SGPR_64; break;
18139 : case AMDGPU::SGPR66_SGPR67: OpKind = MCK_SGPR_64; break;
18140 : case AMDGPU::SGPR68_SGPR69: OpKind = MCK_SGPR_64; break;
18141 : case AMDGPU::SGPR70_SGPR71: OpKind = MCK_SGPR_64; break;
18142 : case AMDGPU::SGPR72_SGPR73: OpKind = MCK_SGPR_64; break;
18143 : case AMDGPU::SGPR74_SGPR75: OpKind = MCK_SGPR_64; break;
18144 : case AMDGPU::SGPR76_SGPR77: OpKind = MCK_SGPR_64; break;
18145 : case AMDGPU::SGPR78_SGPR79: OpKind = MCK_SGPR_64; break;
18146 : case AMDGPU::SGPR80_SGPR81: OpKind = MCK_SGPR_64; break;
18147 : case AMDGPU::SGPR82_SGPR83: OpKind = MCK_SGPR_64; break;
18148 : case AMDGPU::SGPR84_SGPR85: OpKind = MCK_SGPR_64; break;
18149 : case AMDGPU::SGPR86_SGPR87: OpKind = MCK_SGPR_64; break;
18150 : case AMDGPU::SGPR88_SGPR89: OpKind = MCK_SGPR_64; break;
18151 : case AMDGPU::SGPR90_SGPR91: OpKind = MCK_SGPR_64; break;
18152 : case AMDGPU::SGPR92_SGPR93: OpKind = MCK_SGPR_64; break;
18153 : case AMDGPU::SGPR94_SGPR95: OpKind = MCK_SGPR_64; break;
18154 : case AMDGPU::SGPR96_SGPR97: OpKind = MCK_SGPR_64; break;
18155 : case AMDGPU::SGPR98_SGPR99: OpKind = MCK_SGPR_64; break;
18156 : case AMDGPU::SGPR100_SGPR101: OpKind = MCK_SGPR_64; break;
18157 : case AMDGPU::VGPR0_VGPR1_VGPR2_VGPR3: OpKind = MCK_VReg_128; break;
18158 : case AMDGPU::VGPR1_VGPR2_VGPR3_VGPR4: OpKind = MCK_VReg_128; break;
18159 : case AMDGPU::VGPR2_VGPR3_VGPR4_VGPR5: OpKind = MCK_VReg_128; break;
18160 : case AMDGPU::VGPR3_VGPR4_VGPR5_VGPR6: OpKind = MCK_VReg_128; break;
18161 : case AMDGPU::VGPR4_VGPR5_VGPR6_VGPR7: OpKind = MCK_VReg_128; break;
18162 : case AMDGPU::VGPR5_VGPR6_VGPR7_VGPR8: OpKind = MCK_VReg_128; break;
18163 : case AMDGPU::VGPR6_VGPR7_VGPR8_VGPR9: OpKind = MCK_VReg_128; break;
18164 : case AMDGPU::VGPR7_VGPR8_VGPR9_VGPR10: OpKind = MCK_VReg_128; break;
18165 : case AMDGPU::VGPR8_VGPR9_VGPR10_VGPR11: OpKind = MCK_VReg_128; break;
18166 : case AMDGPU::VGPR9_VGPR10_VGPR11_VGPR12: OpKind = MCK_VReg_128; break;
18167 : case AMDGPU::VGPR10_VGPR11_VGPR12_VGPR13: OpKind = MCK_VReg_128; break;
18168 : case AMDGPU::VGPR11_VGPR12_VGPR13_VGPR14: OpKind = MCK_VReg_128; break;
18169 : case AMDGPU::VGPR12_VGPR13_VGPR14_VGPR15: OpKind = MCK_VReg_128; break;
18170 : case AMDGPU::VGPR13_VGPR14_VGPR15_VGPR16: OpKind = MCK_VReg_128; break;
18171 : case AMDGPU::VGPR14_VGPR15_VGPR16_VGPR17: OpKind = MCK_VReg_128; break;
18172 : case AMDGPU::VGPR15_VGPR16_VGPR17_VGPR18: OpKind = MCK_VReg_128; break;
18173 : case AMDGPU::VGPR16_VGPR17_VGPR18_VGPR19: OpKind = MCK_VReg_128; break;
18174 : case AMDGPU::VGPR17_VGPR18_VGPR19_VGPR20: OpKind = MCK_VReg_128; break;
18175 : case AMDGPU::VGPR18_VGPR19_VGPR20_VGPR21: OpKind = MCK_VReg_128; break;
18176 : case AMDGPU::VGPR19_VGPR20_VGPR21_VGPR22: OpKind = MCK_VReg_128; break;
18177 : case AMDGPU::VGPR20_VGPR21_VGPR22_VGPR23: OpKind = MCK_VReg_128; break;
18178 : case AMDGPU::VGPR21_VGPR22_VGPR23_VGPR24: OpKind = MCK_VReg_128; break;
18179 : case AMDGPU::VGPR22_VGPR23_VGPR24_VGPR25: OpKind = MCK_VReg_128; break;
18180 : case AMDGPU::VGPR23_VGPR24_VGPR25_VGPR26: OpKind = MCK_VReg_128; break;
18181 : case AMDGPU::VGPR24_VGPR25_VGPR26_VGPR27: OpKind = MCK_VReg_128; break;
18182 : case AMDGPU::VGPR25_VGPR26_VGPR27_VGPR28: OpKind = MCK_VReg_128; break;
18183 : case AMDGPU::VGPR26_VGPR27_VGPR28_VGPR29: OpKind = MCK_VReg_128; break;
18184 : case AMDGPU::VGPR27_VGPR28_VGPR29_VGPR30: OpKind = MCK_VReg_128; break;
18185 : case AMDGPU::VGPR28_VGPR29_VGPR30_VGPR31: OpKind = MCK_VReg_128; break;
18186 : case AMDGPU::VGPR29_VGPR30_VGPR31_VGPR32: OpKind = MCK_VReg_128; break;
18187 : case AMDGPU::VGPR30_VGPR31_VGPR32_VGPR33: OpKind = MCK_VReg_128; break;
18188 : case AMDGPU::VGPR31_VGPR32_VGPR33_VGPR34: OpKind = MCK_VReg_128; break;
18189 : case AMDGPU::VGPR32_VGPR33_VGPR34_VGPR35: OpKind = MCK_VReg_128; break;
18190 : case AMDGPU::VGPR33_VGPR34_VGPR35_VGPR36: OpKind = MCK_VReg_128; break;
18191 : case AMDGPU::VGPR34_VGPR35_VGPR36_VGPR37: OpKind = MCK_VReg_128; break;
18192 : case AMDGPU::VGPR35_VGPR36_VGPR37_VGPR38: OpKind = MCK_VReg_128; break;
18193 : case AMDGPU::VGPR36_VGPR37_VGPR38_VGPR39: OpKind = MCK_VReg_128; break;
18194 : case AMDGPU::VGPR37_VGPR38_VGPR39_VGPR40: OpKind = MCK_VReg_128; break;
18195 : case AMDGPU::VGPR38_VGPR39_VGPR40_VGPR41: OpKind = MCK_VReg_128; break;
18196 : case AMDGPU::VGPR39_VGPR40_VGPR41_VGPR42: OpKind = MCK_VReg_128; break;
18197 : case AMDGPU::VGPR40_VGPR41_VGPR42_VGPR43: OpKind = MCK_VReg_128; break;
18198 : case AMDGPU::VGPR41_VGPR42_VGPR43_VGPR44: OpKind = MCK_VReg_128; break;
18199 : case AMDGPU::VGPR42_VGPR43_VGPR44_VGPR45: OpKind = MCK_VReg_128; break;
18200 : case AMDGPU::VGPR43_VGPR44_VGPR45_VGPR46: OpKind = MCK_VReg_128; break;
18201 : case AMDGPU::VGPR44_VGPR45_VGPR46_VGPR47: OpKind = MCK_VReg_128; break;
18202 : case AMDGPU::VGPR45_VGPR46_VGPR47_VGPR48: OpKind = MCK_VReg_128; break;
18203 : case AMDGPU::VGPR46_VGPR47_VGPR48_VGPR49: OpKind = MCK_VReg_128; break;
18204 : case AMDGPU::VGPR47_VGPR48_VGPR49_VGPR50: OpKind = MCK_VReg_128; break;
18205 : case AMDGPU::VGPR48_VGPR49_VGPR50_VGPR51: OpKind = MCK_VReg_128; break;
18206 : case AMDGPU::VGPR49_VGPR50_VGPR51_VGPR52: OpKind = MCK_VReg_128; break;
18207 : case AMDGPU::VGPR50_VGPR51_VGPR52_VGPR53: OpKind = MCK_VReg_128; break;
18208 : case AMDGPU::VGPR51_VGPR52_VGPR53_VGPR54: OpKind = MCK_VReg_128; break;
18209 : case AMDGPU::VGPR52_VGPR53_VGPR54_VGPR55: OpKind = MCK_VReg_128; break;
18210 : case AMDGPU::VGPR53_VGPR54_VGPR55_VGPR56: OpKind = MCK_VReg_128; break;
18211 : case AMDGPU::VGPR54_VGPR55_VGPR56_VGPR57: OpKind = MCK_VReg_128; break;
18212 : case AMDGPU::VGPR55_VGPR56_VGPR57_VGPR58: OpKind = MCK_VReg_128; break;
18213 : case AMDGPU::VGPR56_VGPR57_VGPR58_VGPR59: OpKind = MCK_VReg_128; break;
18214 : case AMDGPU::VGPR57_VGPR58_VGPR59_VGPR60: OpKind = MCK_VReg_128; break;
18215 : case AMDGPU::VGPR58_VGPR59_VGPR60_VGPR61: OpKind = MCK_VReg_128; break;
18216 : case AMDGPU::VGPR59_VGPR60_VGPR61_VGPR62: OpKind = MCK_VReg_128; break;
18217 : case AMDGPU::VGPR60_VGPR61_VGPR62_VGPR63: OpKind = MCK_VReg_128; break;
18218 : case AMDGPU::VGPR61_VGPR62_VGPR63_VGPR64: OpKind = MCK_VReg_128; break;
18219 : case AMDGPU::VGPR62_VGPR63_VGPR64_VGPR65: OpKind = MCK_VReg_128; break;
18220 : case AMDGPU::VGPR63_VGPR64_VGPR65_VGPR66: OpKind = MCK_VReg_128; break;
18221 : case AMDGPU::VGPR64_VGPR65_VGPR66_VGPR67: OpKind = MCK_VReg_128; break;
18222 : case AMDGPU::VGPR65_VGPR66_VGPR67_VGPR68: OpKind = MCK_VReg_128; break;
18223 : case AMDGPU::VGPR66_VGPR67_VGPR68_VGPR69: OpKind = MCK_VReg_128; break;
18224 : case AMDGPU::VGPR67_VGPR68_VGPR69_VGPR70: OpKind = MCK_VReg_128; break;
18225 : case AMDGPU::VGPR68_VGPR69_VGPR70_VGPR71: OpKind = MCK_VReg_128; break;
18226 : case AMDGPU::VGPR69_VGPR70_VGPR71_VGPR72: OpKind = MCK_VReg_128; break;
18227 : case AMDGPU::VGPR70_VGPR71_VGPR72_VGPR73: OpKind = MCK_VReg_128; break;
18228 : case AMDGPU::VGPR71_VGPR72_VGPR73_VGPR74: OpKind = MCK_VReg_128; break;
18229 : case AMDGPU::VGPR72_VGPR73_VGPR74_VGPR75: OpKind = MCK_VReg_128; break;
18230 : case AMDGPU::VGPR73_VGPR74_VGPR75_VGPR76: OpKind = MCK_VReg_128; break;
18231 : case AMDGPU::VGPR74_VGPR75_VGPR76_VGPR77: OpKind = MCK_VReg_128; break;
18232 : case AMDGPU::VGPR75_VGPR76_VGPR77_VGPR78: OpKind = MCK_VReg_128; break;
18233 : case AMDGPU::VGPR76_VGPR77_VGPR78_VGPR79: OpKind = MCK_VReg_128; break;
18234 : case AMDGPU::VGPR77_VGPR78_VGPR79_VGPR80: OpKind = MCK_VReg_128; break;
18235 : case AMDGPU::VGPR78_VGPR79_VGPR80_VGPR81: OpKind = MCK_VReg_128; break;
18236 : case AMDGPU::VGPR79_VGPR80_VGPR81_VGPR82: OpKind = MCK_VReg_128; break;
18237 : case AMDGPU::VGPR80_VGPR81_VGPR82_VGPR83: OpKind = MCK_VReg_128; break;
18238 : case AMDGPU::VGPR81_VGPR82_VGPR83_VGPR84: OpKind = MCK_VReg_128; break;
18239 : case AMDGPU::VGPR82_VGPR83_VGPR84_VGPR85: OpKind = MCK_VReg_128; break;
18240 : case AMDGPU::VGPR83_VGPR84_VGPR85_VGPR86: OpKind = MCK_VReg_128; break;
18241 : case AMDGPU::VGPR84_VGPR85_VGPR86_VGPR87: OpKind = MCK_VReg_128; break;
18242 : case AMDGPU::VGPR85_VGPR86_VGPR87_VGPR88: OpKind = MCK_VReg_128; break;
18243 : case AMDGPU::VGPR86_VGPR87_VGPR88_VGPR89: OpKind = MCK_VReg_128; break;
18244 : case AMDGPU::VGPR87_VGPR88_VGPR89_VGPR90: OpKind = MCK_VReg_128; break;
18245 : case AMDGPU::VGPR88_VGPR89_VGPR90_VGPR91: OpKind = MCK_VReg_128; break;
18246 : case AMDGPU::VGPR89_VGPR90_VGPR91_VGPR92: OpKind = MCK_VReg_128; break;
18247 : case AMDGPU::VGPR90_VGPR91_VGPR92_VGPR93: OpKind = MCK_VReg_128; break;
18248 : case AMDGPU::VGPR91_VGPR92_VGPR93_VGPR94: OpKind = MCK_VReg_128; break;
18249 : case AMDGPU::VGPR92_VGPR93_VGPR94_VGPR95: OpKind = MCK_VReg_128; break;
18250 : case AMDGPU::VGPR93_VGPR94_VGPR95_VGPR96: OpKind = MCK_VReg_128; break;
18251 : case AMDGPU::VGPR94_VGPR95_VGPR96_VGPR97: OpKind = MCK_VReg_128; break;
18252 : case AMDGPU::VGPR95_VGPR96_VGPR97_VGPR98: OpKind = MCK_VReg_128; break;
18253 : case AMDGPU::VGPR96_VGPR97_VGPR98_VGPR99: OpKind = MCK_VReg_128; break;
18254 : case AMDGPU::VGPR97_VGPR98_VGPR99_VGPR100: OpKind = MCK_VReg_128; break;
18255 : case AMDGPU::VGPR98_VGPR99_VGPR100_VGPR101: OpKind = MCK_VReg_128; break;
18256 : case AMDGPU::VGPR99_VGPR100_VGPR101_VGPR102: OpKind = MCK_VReg_128; break;
18257 : case AMDGPU::VGPR100_VGPR101_VGPR102_VGPR103: OpKind = MCK_VReg_128; break;
18258 : case AMDGPU::VGPR101_VGPR102_VGPR103_VGPR104: OpKind = MCK_VReg_128; break;
18259 : case AMDGPU::VGPR102_VGPR103_VGPR104_VGPR105: OpKind = MCK_VReg_128; break;
18260 : case AMDGPU::VGPR103_VGPR104_VGPR105_VGPR106: OpKind = MCK_VReg_128; break;
18261 : case AMDGPU::VGPR104_VGPR105_VGPR106_VGPR107: OpKind = MCK_VReg_128; break;
18262 : case AMDGPU::VGPR105_VGPR106_VGPR107_VGPR108: OpKind = MCK_VReg_128; break;
18263 : case AMDGPU::VGPR106_VGPR107_VGPR108_VGPR109: OpKind = MCK_VReg_128; break;
18264 : case AMDGPU::VGPR107_VGPR108_VGPR109_VGPR110: OpKind = MCK_VReg_128; break;
18265 : case AMDGPU::VGPR108_VGPR109_VGPR110_VGPR111: OpKind = MCK_VReg_128; break;
18266 : case AMDGPU::VGPR109_VGPR110_VGPR111_VGPR112: OpKind = MCK_VReg_128; break;
18267 : case AMDGPU::VGPR110_VGPR111_VGPR112_VGPR113: OpKind = MCK_VReg_128; break;
18268 : case AMDGPU::VGPR111_VGPR112_VGPR113_VGPR114: OpKind = MCK_VReg_128; break;
18269 : case AMDGPU::VGPR112_VGPR113_VGPR114_VGPR115: OpKind = MCK_VReg_128; break;
18270 : case AMDGPU::VGPR113_VGPR114_VGPR115_VGPR116: OpKind = MCK_VReg_128; break;
18271 : case AMDGPU::VGPR114_VGPR115_VGPR116_VGPR117: OpKind = MCK_VReg_128; break;
18272 : case AMDGPU::VGPR115_VGPR116_VGPR117_VGPR118: OpKind = MCK_VReg_128; break;
18273 : case AMDGPU::VGPR116_VGPR117_VGPR118_VGPR119: OpKind = MCK_VReg_128; break;
18274 : case AMDGPU::VGPR117_VGPR118_VGPR119_VGPR120: OpKind = MCK_VReg_128; break;
18275 : case AMDGPU::VGPR118_VGPR119_VGPR120_VGPR121: OpKind = MCK_VReg_128; break;
18276 : case AMDGPU::VGPR119_VGPR120_VGPR121_VGPR122: OpKind = MCK_VReg_128; break;
18277 : case AMDGPU::VGPR120_VGPR121_VGPR122_VGPR123: OpKind = MCK_VReg_128; break;
18278 : case AMDGPU::VGPR121_VGPR122_VGPR123_VGPR124: OpKind = MCK_VReg_128; break;
18279 : case AMDGPU::VGPR122_VGPR123_VGPR124_VGPR125: OpKind = MCK_VReg_128; break;
18280 : case AMDGPU::VGPR123_VGPR124_VGPR125_VGPR126: OpKind = MCK_VReg_128; break;
18281 : case AMDGPU::VGPR124_VGPR125_VGPR126_VGPR127: OpKind = MCK_VReg_128; break;
18282 : case AMDGPU::VGPR125_VGPR126_VGPR127_VGPR128: OpKind = MCK_VReg_128; break;
18283 : case AMDGPU::VGPR126_VGPR127_VGPR128_VGPR129: OpKind = MCK_VReg_128; break;
18284 : case AMDGPU::VGPR127_VGPR128_VGPR129_VGPR130: OpKind = MCK_VReg_128; break;
18285 : case AMDGPU::VGPR128_VGPR129_VGPR130_VGPR131: OpKind = MCK_VReg_128; break;
18286 : case AMDGPU::VGPR129_VGPR130_VGPR131_VGPR132: OpKind = MCK_VReg_128; break;
18287 : case AMDGPU::VGPR130_VGPR131_VGPR132_VGPR133: OpKind = MCK_VReg_128; break;
18288 : case AMDGPU::VGPR131_VGPR132_VGPR133_VGPR134: OpKind = MCK_VReg_128; break;
18289 : case AMDGPU::VGPR132_VGPR133_VGPR134_VGPR135: OpKind = MCK_VReg_128; break;
18290 : case AMDGPU::VGPR133_VGPR134_VGPR135_VGPR136: OpKind = MCK_VReg_128; break;
18291 : case AMDGPU::VGPR134_VGPR135_VGPR136_VGPR137: OpKind = MCK_VReg_128; break;
18292 : case AMDGPU::VGPR135_VGPR136_VGPR137_VGPR138: OpKind = MCK_VReg_128; break;
18293 : case AMDGPU::VGPR136_VGPR137_VGPR138_VGPR139: OpKind = MCK_VReg_128; break;
18294 : case AMDGPU::VGPR137_VGPR138_VGPR139_VGPR140: OpKind = MCK_VReg_128; break;
18295 : case AMDGPU::VGPR138_VGPR139_VGPR140_VGPR141: OpKind = MCK_VReg_128; break;
18296 : case AMDGPU::VGPR139_VGPR140_VGPR141_VGPR142: OpKind = MCK_VReg_128; break;
18297 : case AMDGPU::VGPR140_VGPR141_VGPR142_VGPR143: OpKind = MCK_VReg_128; break;
18298 : case AMDGPU::VGPR141_VGPR142_VGPR143_VGPR144: OpKind = MCK_VReg_128; break;
18299 : case AMDGPU::VGPR142_VGPR143_VGPR144_VGPR145: OpKind = MCK_VReg_128; break;
18300 : case AMDGPU::VGPR143_VGPR144_VGPR145_VGPR146: OpKind = MCK_VReg_128; break;
18301 : case AMDGPU::VGPR144_VGPR145_VGPR146_VGPR147: OpKind = MCK_VReg_128; break;
18302 : case AMDGPU::VGPR145_VGPR146_VGPR147_VGPR148: OpKind = MCK_VReg_128; break;
18303 : case AMDGPU::VGPR146_VGPR147_VGPR148_VGPR149: OpKind = MCK_VReg_128; break;
18304 : case AMDGPU::VGPR147_VGPR148_VGPR149_VGPR150: OpKind = MCK_VReg_128; break;
18305 : case AMDGPU::VGPR148_VGPR149_VGPR150_VGPR151: OpKind = MCK_VReg_128; break;
18306 : case AMDGPU::VGPR149_VGPR150_VGPR151_VGPR152: OpKind = MCK_VReg_128; break;
18307 : case AMDGPU::VGPR150_VGPR151_VGPR152_VGPR153: OpKind = MCK_VReg_128; break;
18308 : case AMDGPU::VGPR151_VGPR152_VGPR153_VGPR154: OpKind = MCK_VReg_128; break;
18309 : case AMDGPU::VGPR152_VGPR153_VGPR154_VGPR155: OpKind = MCK_VReg_128; break;
18310 : case AMDGPU::VGPR153_VGPR154_VGPR155_VGPR156: OpKind = MCK_VReg_128; break;
18311 : case AMDGPU::VGPR154_VGPR155_VGPR156_VGPR157: OpKind = MCK_VReg_128; break;
18312 : case AMDGPU::VGPR155_VGPR156_VGPR157_VGPR158: OpKind = MCK_VReg_128; break;
18313 : case AMDGPU::VGPR156_VGPR157_VGPR158_VGPR159: OpKind = MCK_VReg_128; break;
18314 : case AMDGPU::VGPR157_VGPR158_VGPR159_VGPR160: OpKind = MCK_VReg_128; break;
18315 : case AMDGPU::VGPR158_VGPR159_VGPR160_VGPR161: OpKind = MCK_VReg_128; break;
18316 : case AMDGPU::VGPR159_VGPR160_VGPR161_VGPR162: OpKind = MCK_VReg_128; break;
18317 : case AMDGPU::VGPR160_VGPR161_VGPR162_VGPR163: OpKind = MCK_VReg_128; break;
18318 : case AMDGPU::VGPR161_VGPR162_VGPR163_VGPR164: OpKind = MCK_VReg_128; break;
18319 : case AMDGPU::VGPR162_VGPR163_VGPR164_VGPR165: OpKind = MCK_VReg_128; break;
18320 : case AMDGPU::VGPR163_VGPR164_VGPR165_VGPR166: OpKind = MCK_VReg_128; break;
18321 : case AMDGPU::VGPR164_VGPR165_VGPR166_VGPR167: OpKind = MCK_VReg_128; break;
18322 : case AMDGPU::VGPR165_VGPR166_VGPR167_VGPR168: OpKind = MCK_VReg_128; break;
18323 : case AMDGPU::VGPR166_VGPR167_VGPR168_VGPR169: OpKind = MCK_VReg_128; break;
18324 : case AMDGPU::VGPR167_VGPR168_VGPR169_VGPR170: OpKind = MCK_VReg_128; break;
18325 : case AMDGPU::VGPR168_VGPR169_VGPR170_VGPR171: OpKind = MCK_VReg_128; break;
18326 : case AMDGPU::VGPR169_VGPR170_VGPR171_VGPR172: OpKind = MCK_VReg_128; break;
18327 : case AMDGPU::VGPR170_VGPR171_VGPR172_VGPR173: OpKind = MCK_VReg_128; break;
18328 : case AMDGPU::VGPR171_VGPR172_VGPR173_VGPR174: OpKind = MCK_VReg_128; break;
18329 : case AMDGPU::VGPR172_VGPR173_VGPR174_VGPR175: OpKind = MCK_VReg_128; break;
18330 : case AMDGPU::VGPR173_VGPR174_VGPR175_VGPR176: OpKind = MCK_VReg_128; break;
18331 : case AMDGPU::VGPR174_VGPR175_VGPR176_VGPR177: OpKind = MCK_VReg_128; break;
18332 : case AMDGPU::VGPR175_VGPR176_VGPR177_VGPR178: OpKind = MCK_VReg_128; break;
18333 : case AMDGPU::VGPR176_VGPR177_VGPR178_VGPR179: OpKind = MCK_VReg_128; break;
18334 : case AMDGPU::VGPR177_VGPR178_VGPR179_VGPR180: OpKind = MCK_VReg_128; break;
18335 : case AMDGPU::VGPR178_VGPR179_VGPR180_VGPR181: OpKind = MCK_VReg_128; break;
18336 : case AMDGPU::VGPR179_VGPR180_VGPR181_VGPR182: OpKind = MCK_VReg_128; break;
18337 : case AMDGPU::VGPR180_VGPR181_VGPR182_VGPR183: OpKind = MCK_VReg_128; break;
18338 : case AMDGPU::VGPR181_VGPR182_VGPR183_VGPR184: OpKind = MCK_VReg_128; break;
18339 : case AMDGPU::VGPR182_VGPR183_VGPR184_VGPR185: OpKind = MCK_VReg_128; break;
18340 : case AMDGPU::VGPR183_VGPR184_VGPR185_VGPR186: OpKind = MCK_VReg_128; break;
18341 : case AMDGPU::VGPR184_VGPR185_VGPR186_VGPR187: OpKind = MCK_VReg_128; break;
18342 : case AMDGPU::VGPR185_VGPR186_VGPR187_VGPR188: OpKind = MCK_VReg_128; break;
18343 : case AMDGPU::VGPR186_VGPR187_VGPR188_VGPR189: OpKind = MCK_VReg_128; break;
18344 : case AMDGPU::VGPR187_VGPR188_VGPR189_VGPR190: OpKind = MCK_VReg_128; break;
18345 : case AMDGPU::VGPR188_VGPR189_VGPR190_VGPR191: OpKind = MCK_VReg_128; break;
18346 : case AMDGPU::VGPR189_VGPR190_VGPR191_VGPR192: OpKind = MCK_VReg_128; break;
18347 : case AMDGPU::VGPR190_VGPR191_VGPR192_VGPR193: OpKind = MCK_VReg_128; break;
18348 : case AMDGPU::VGPR191_VGPR192_VGPR193_VGPR194: OpKind = MCK_VReg_128; break;
18349 : case AMDGPU::VGPR192_VGPR193_VGPR194_VGPR195: OpKind = MCK_VReg_128; break;
18350 : case AMDGPU::VGPR193_VGPR194_VGPR195_VGPR196: OpKind = MCK_VReg_128; break;
18351 : case AMDGPU::VGPR194_VGPR195_VGPR196_VGPR197: OpKind = MCK_VReg_128; break;
18352 : case AMDGPU::VGPR195_VGPR196_VGPR197_VGPR198: OpKind = MCK_VReg_128; break;
18353 : case AMDGPU::VGPR196_VGPR197_VGPR198_VGPR199: OpKind = MCK_VReg_128; break;
18354 : case AMDGPU::VGPR197_VGPR198_VGPR199_VGPR200: OpKind = MCK_VReg_128; break;
18355 : case AMDGPU::VGPR198_VGPR199_VGPR200_VGPR201: OpKind = MCK_VReg_128; break;
18356 : case AMDGPU::VGPR199_VGPR200_VGPR201_VGPR202: OpKind = MCK_VReg_128; break;
18357 : case AMDGPU::VGPR200_VGPR201_VGPR202_VGPR203: OpKind = MCK_VReg_128; break;
18358 : case AMDGPU::VGPR201_VGPR202_VGPR203_VGPR204: OpKind = MCK_VReg_128; break;
18359 : case AMDGPU::VGPR202_VGPR203_VGPR204_VGPR205: OpKind = MCK_VReg_128; break;
18360 : case AMDGPU::VGPR203_VGPR204_VGPR205_VGPR206: OpKind = MCK_VReg_128; break;
18361 : case AMDGPU::VGPR204_VGPR205_VGPR206_VGPR207: OpKind = MCK_VReg_128; break;
18362 : case AMDGPU::VGPR205_VGPR206_VGPR207_VGPR208: OpKind = MCK_VReg_128; break;
18363 : case AMDGPU::VGPR206_VGPR207_VGPR208_VGPR209: OpKind = MCK_VReg_128; break;
18364 : case AMDGPU::VGPR207_VGPR208_VGPR209_VGPR210: OpKind = MCK_VReg_128; break;
18365 : case AMDGPU::VGPR208_VGPR209_VGPR210_VGPR211: OpKind = MCK_VReg_128; break;
18366 : case AMDGPU::VGPR209_VGPR210_VGPR211_VGPR212: OpKind = MCK_VReg_128; break;
18367 : case AMDGPU::VGPR210_VGPR211_VGPR212_VGPR213: OpKind = MCK_VReg_128; break;
18368 : case AMDGPU::VGPR211_VGPR212_VGPR213_VGPR214: OpKind = MCK_VReg_128; break;
18369 : case AMDGPU::VGPR212_VGPR213_VGPR214_VGPR215: OpKind = MCK_VReg_128; break;
18370 : case AMDGPU::VGPR213_VGPR214_VGPR215_VGPR216: OpKind = MCK_VReg_128; break;
18371 : case AMDGPU::VGPR214_VGPR215_VGPR216_VGPR217: OpKind = MCK_VReg_128; break;
18372 : case AMDGPU::VGPR215_VGPR216_VGPR217_VGPR218: OpKind = MCK_VReg_128; break;
18373 : case AMDGPU::VGPR216_VGPR217_VGPR218_VGPR219: OpKind = MCK_VReg_128; break;
18374 : case AMDGPU::VGPR217_VGPR218_VGPR219_VGPR220: OpKind = MCK_VReg_128; break;
18375 : case AMDGPU::VGPR218_VGPR219_VGPR220_VGPR221: OpKind = MCK_VReg_128; break;
18376 : case AMDGPU::VGPR219_VGPR220_VGPR221_VGPR222: OpKind = MCK_VReg_128; break;
18377 : case AMDGPU::VGPR220_VGPR221_VGPR222_VGPR223: OpKind = MCK_VReg_128; break;
18378 : case AMDGPU::VGPR221_VGPR222_VGPR223_VGPR224: OpKind = MCK_VReg_128; break;
18379 : case AMDGPU::VGPR222_VGPR223_VGPR224_VGPR225: OpKind = MCK_VReg_128; break;
18380 : case AMDGPU::VGPR223_VGPR224_VGPR225_VGPR226: OpKind = MCK_VReg_128; break;
18381 : case AMDGPU::VGPR224_VGPR225_VGPR226_VGPR227: OpKind = MCK_VReg_128; break;
18382 : case AMDGPU::VGPR225_VGPR226_VGPR227_VGPR228: OpKind = MCK_VReg_128; break;
18383 : case AMDGPU::VGPR226_VGPR227_VGPR228_VGPR229: OpKind = MCK_VReg_128; break;
18384 : case AMDGPU::VGPR227_VGPR228_VGPR229_VGPR230: OpKind = MCK_VReg_128; break;
18385 : case AMDGPU::VGPR228_VGPR229_VGPR230_VGPR231: OpKind = MCK_VReg_128; break;
18386 : case AMDGPU::VGPR229_VGPR230_VGPR231_VGPR232: OpKind = MCK_VReg_128; break;
18387 : case AMDGPU::VGPR230_VGPR231_VGPR232_VGPR233: OpKind = MCK_VReg_128; break;
18388 : case AMDGPU::VGPR231_VGPR232_VGPR233_VGPR234: OpKind = MCK_VReg_128; break;
18389 : case AMDGPU::VGPR232_VGPR233_VGPR234_VGPR235: OpKind = MCK_VReg_128; break;
18390 : case AMDGPU::VGPR233_VGPR234_VGPR235_VGPR236: OpKind = MCK_VReg_128; break;
18391 : case AMDGPU::VGPR234_VGPR235_VGPR236_VGPR237: OpKind = MCK_VReg_128; break;
18392 : case AMDGPU::VGPR235_VGPR236_VGPR237_VGPR238: OpKind = MCK_VReg_128; break;
18393 : case AMDGPU::VGPR236_VGPR237_VGPR238_VGPR239: OpKind = MCK_VReg_128; break;
18394 : case AMDGPU::VGPR237_VGPR238_VGPR239_VGPR240: OpKind = MCK_VReg_128; break;
18395 : case AMDGPU::VGPR238_VGPR239_VGPR240_VGPR241: OpKind = MCK_VReg_128; break;
18396 : case AMDGPU::VGPR239_VGPR240_VGPR241_VGPR242: OpKind = MCK_VReg_128; break;
18397 : case AMDGPU::VGPR240_VGPR241_VGPR242_VGPR243: OpKind = MCK_VReg_128; break;
18398 : case AMDGPU::VGPR241_VGPR242_VGPR243_VGPR244: OpKind = MCK_VReg_128; break;
18399 : case AMDGPU::VGPR242_VGPR243_VGPR244_VGPR245: OpKind = MCK_VReg_128; break;
18400 : case AMDGPU::VGPR243_VGPR244_VGPR245_VGPR246: OpKind = MCK_VReg_128; break;
18401 : case AMDGPU::VGPR244_VGPR245_VGPR246_VGPR247: OpKind = MCK_VReg_128; break;
18402 : case AMDGPU::VGPR245_VGPR246_VGPR247_VGPR248: OpKind = MCK_VReg_128; break;
18403 : case AMDGPU::VGPR246_VGPR247_VGPR248_VGPR249: OpKind = MCK_VReg_128; break;
18404 : case AMDGPU::VGPR247_VGPR248_VGPR249_VGPR250: OpKind = MCK_VReg_128; break;
18405 : case AMDGPU::VGPR248_VGPR249_VGPR250_VGPR251: OpKind = MCK_VReg_128; break;
18406 : case AMDGPU::VGPR249_VGPR250_VGPR251_VGPR252: OpKind = MCK_VReg_128; break;
18407 : case AMDGPU::VGPR250_VGPR251_VGPR252_VGPR253: OpKind = MCK_VReg_128; break;
18408 : case AMDGPU::VGPR251_VGPR252_VGPR253_VGPR254: OpKind = MCK_VReg_128; break;
18409 : case AMDGPU::VGPR252_VGPR253_VGPR254_VGPR255: OpKind = MCK_VReg_128; break;
18410 : case AMDGPU::VGPR0_VGPR1_VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7: OpKind = MCK_VReg_256; break;
18411 : case AMDGPU::VGPR1_VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7_VGPR8: OpKind = MCK_VReg_256; break;
18412 : case AMDGPU::VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9: OpKind = MCK_VReg_256; break;
18413 : case AMDGPU::VGPR3_VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10: OpKind = MCK_VReg_256; break;
18414 : case AMDGPU::VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11: OpKind = MCK_VReg_256; break;
18415 : case AMDGPU::VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12: OpKind = MCK_VReg_256; break;
18416 : case AMDGPU::VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13: OpKind = MCK_VReg_256; break;
18417 : case AMDGPU::VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14: OpKind = MCK_VReg_256; break;
18418 : case AMDGPU::VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15: OpKind = MCK_VReg_256; break;
18419 : case AMDGPU::VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16: OpKind = MCK_VReg_256; break;
18420 : case AMDGPU::VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17: OpKind = MCK_VReg_256; break;
18421 : case AMDGPU::VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18: OpKind = MCK_VReg_256; break;
18422 : case AMDGPU::VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19: OpKind = MCK_VReg_256; break;
18423 : case AMDGPU::VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20: OpKind = MCK_VReg_256; break;
18424 : case AMDGPU::VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21: OpKind = MCK_VReg_256; break;
18425 : case AMDGPU::VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22: OpKind = MCK_VReg_256; break;
18426 : case AMDGPU::VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23: OpKind = MCK_VReg_256; break;
18427 : case AMDGPU::VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24: OpKind = MCK_VReg_256; break;
18428 : case AMDGPU::VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25: OpKind = MCK_VReg_256; break;
18429 : case AMDGPU::VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26: OpKind = MCK_VReg_256; break;
18430 : case AMDGPU::VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27: OpKind = MCK_VReg_256; break;
18431 : case AMDGPU::VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28: OpKind = MCK_VReg_256; break;
18432 : case AMDGPU::VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29: OpKind = MCK_VReg_256; break;
18433 : case AMDGPU::VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30: OpKind = MCK_VReg_256; break;
18434 : case AMDGPU::VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31: OpKind = MCK_VReg_256; break;
18435 : case AMDGPU::VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32: OpKind = MCK_VReg_256; break;
18436 : case AMDGPU::VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33: OpKind = MCK_VReg_256; break;
18437 : case AMDGPU::VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34: OpKind = MCK_VReg_256; break;
18438 : case AMDGPU::VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35: OpKind = MCK_VReg_256; break;
18439 : case AMDGPU::VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36: OpKind = MCK_VReg_256; break;
18440 : case AMDGPU::VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37: OpKind = MCK_VReg_256; break;
18441 : case AMDGPU::VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38: OpKind = MCK_VReg_256; break;
18442 : case AMDGPU::VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39: OpKind = MCK_VReg_256; break;
18443 : case AMDGPU::VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40: OpKind = MCK_VReg_256; break;
18444 : case AMDGPU::VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41: OpKind = MCK_VReg_256; break;
18445 : case AMDGPU::VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42: OpKind = MCK_VReg_256; break;
18446 : case AMDGPU::VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43: OpKind = MCK_VReg_256; break;
18447 : case AMDGPU::VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44: OpKind = MCK_VReg_256; break;
18448 : case AMDGPU::VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45: OpKind = MCK_VReg_256; break;
18449 : case AMDGPU::VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46: OpKind = MCK_VReg_256; break;
18450 : case AMDGPU::VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47: OpKind = MCK_VReg_256; break;
18451 : case AMDGPU::VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48: OpKind = MCK_VReg_256; break;
18452 : case AMDGPU::VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49: OpKind = MCK_VReg_256; break;
18453 : case AMDGPU::VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50: OpKind = MCK_VReg_256; break;
18454 : case AMDGPU::VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51: OpKind = MCK_VReg_256; break;
18455 : case AMDGPU::VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52: OpKind = MCK_VReg_256; break;
18456 : case AMDGPU::VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53: OpKind = MCK_VReg_256; break;
18457 : case AMDGPU::VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54: OpKind = MCK_VReg_256; break;
18458 : case AMDGPU::VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55: OpKind = MCK_VReg_256; break;
18459 : case AMDGPU::VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56: OpKind = MCK_VReg_256; break;
18460 : case AMDGPU::VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57: OpKind = MCK_VReg_256; break;
18461 : case AMDGPU::VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58: OpKind = MCK_VReg_256; break;
18462 : case AMDGPU::VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59: OpKind = MCK_VReg_256; break;
18463 : case AMDGPU::VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60: OpKind = MCK_VReg_256; break;
18464 : case AMDGPU::VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61: OpKind = MCK_VReg_256; break;
18465 : case AMDGPU::VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62: OpKind = MCK_VReg_256; break;
18466 : case AMDGPU::VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63: OpKind = MCK_VReg_256; break;
18467 : case AMDGPU::VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64: OpKind = MCK_VReg_256; break;
18468 : case AMDGPU::VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65: OpKind = MCK_VReg_256; break;
18469 : case AMDGPU::VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66: OpKind = MCK_VReg_256; break;
18470 : case AMDGPU::VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67: OpKind = MCK_VReg_256; break;
18471 : case AMDGPU::VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68: OpKind = MCK_VReg_256; break;
18472 : case AMDGPU::VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69: OpKind = MCK_VReg_256; break;
18473 : case AMDGPU::VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70: OpKind = MCK_VReg_256; break;
18474 : case AMDGPU::VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71: OpKind = MCK_VReg_256; break;
18475 : case AMDGPU::VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72: OpKind = MCK_VReg_256; break;
18476 : case AMDGPU::VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73: OpKind = MCK_VReg_256; break;
18477 : case AMDGPU::VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74: OpKind = MCK_VReg_256; break;
18478 : case AMDGPU::VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75: OpKind = MCK_VReg_256; break;
18479 : case AMDGPU::VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76: OpKind = MCK_VReg_256; break;
18480 : case AMDGPU::VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77: OpKind = MCK_VReg_256; break;
18481 : case AMDGPU::VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78: OpKind = MCK_VReg_256; break;
18482 : case AMDGPU::VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79: OpKind = MCK_VReg_256; break;
18483 : case AMDGPU::VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80: OpKind = MCK_VReg_256; break;
18484 : case AMDGPU::VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81: OpKind = MCK_VReg_256; break;
18485 : case AMDGPU::VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82: OpKind = MCK_VReg_256; break;
18486 : case AMDGPU::VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83: OpKind = MCK_VReg_256; break;
18487 : case AMDGPU::VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84: OpKind = MCK_VReg_256; break;
18488 : case AMDGPU::VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85: OpKind = MCK_VReg_256; break;
18489 : case AMDGPU::VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86: OpKind = MCK_VReg_256; break;
18490 : case AMDGPU::VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87: OpKind = MCK_VReg_256; break;
18491 : case AMDGPU::VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88: OpKind = MCK_VReg_256; break;
18492 : case AMDGPU::VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89: OpKind = MCK_VReg_256; break;
18493 : case AMDGPU::VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90: OpKind = MCK_VReg_256; break;
18494 : case AMDGPU::VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91: OpKind = MCK_VReg_256; break;
18495 : case AMDGPU::VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92: OpKind = MCK_VReg_256; break;
18496 : case AMDGPU::VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93: OpKind = MCK_VReg_256; break;
18497 : case AMDGPU::VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94: OpKind = MCK_VReg_256; break;
18498 : case AMDGPU::VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95: OpKind = MCK_VReg_256; break;
18499 : case AMDGPU::VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96: OpKind = MCK_VReg_256; break;
18500 : case AMDGPU::VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97: OpKind = MCK_VReg_256; break;
18501 : case AMDGPU::VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98: OpKind = MCK_VReg_256; break;
18502 : case AMDGPU::VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99: OpKind = MCK_VReg_256; break;
18503 : case AMDGPU::VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100: OpKind = MCK_VReg_256; break;
18504 : case AMDGPU::VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101: OpKind = MCK_VReg_256; break;
18505 : case AMDGPU::VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102: OpKind = MCK_VReg_256; break;
18506 : case AMDGPU::VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103: OpKind = MCK_VReg_256; break;
18507 : case AMDGPU::VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104: OpKind = MCK_VReg_256; break;
18508 : case AMDGPU::VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105: OpKind = MCK_VReg_256; break;
18509 : case AMDGPU::VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106: OpKind = MCK_VReg_256; break;
18510 : case AMDGPU::VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107: OpKind = MCK_VReg_256; break;
18511 : case AMDGPU::VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108: OpKind = MCK_VReg_256; break;
18512 : case AMDGPU::VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109: OpKind = MCK_VReg_256; break;
18513 : case AMDGPU::VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110: OpKind = MCK_VReg_256; break;
18514 : case AMDGPU::VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111: OpKind = MCK_VReg_256; break;
18515 : case AMDGPU::VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112: OpKind = MCK_VReg_256; break;
18516 : case AMDGPU::VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113: OpKind = MCK_VReg_256; break;
18517 : case AMDGPU::VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114: OpKind = MCK_VReg_256; break;
18518 : case AMDGPU::VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115: OpKind = MCK_VReg_256; break;
18519 : case AMDGPU::VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116: OpKind = MCK_VReg_256; break;
18520 : case AMDGPU::VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117: OpKind = MCK_VReg_256; break;
18521 : case AMDGPU::VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118: OpKind = MCK_VReg_256; break;
18522 : case AMDGPU::VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119: OpKind = MCK_VReg_256; break;
18523 : case AMDGPU::VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120: OpKind = MCK_VReg_256; break;
18524 : case AMDGPU::VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121: OpKind = MCK_VReg_256; break;
18525 : case AMDGPU::VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122: OpKind = MCK_VReg_256; break;
18526 : case AMDGPU::VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123: OpKind = MCK_VReg_256; break;
18527 : case AMDGPU::VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124: OpKind = MCK_VReg_256; break;
18528 : case AMDGPU::VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125: OpKind = MCK_VReg_256; break;
18529 : case AMDGPU::VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126: OpKind = MCK_VReg_256; break;
18530 : case AMDGPU::VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127: OpKind = MCK_VReg_256; break;
18531 : case AMDGPU::VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128: OpKind = MCK_VReg_256; break;
18532 : case AMDGPU::VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129: OpKind = MCK_VReg_256; break;
18533 : case AMDGPU::VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130: OpKind = MCK_VReg_256; break;
18534 : case AMDGPU::VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131: OpKind = MCK_VReg_256; break;
18535 : case AMDGPU::VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132: OpKind = MCK_VReg_256; break;
18536 : case AMDGPU::VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133: OpKind = MCK_VReg_256; break;
18537 : case AMDGPU::VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134: OpKind = MCK_VReg_256; break;
18538 : case AMDGPU::VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135: OpKind = MCK_VReg_256; break;
18539 : case AMDGPU::VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136: OpKind = MCK_VReg_256; break;
18540 : case AMDGPU::VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137: OpKind = MCK_VReg_256; break;
18541 : case AMDGPU::VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138: OpKind = MCK_VReg_256; break;
18542 : case AMDGPU::VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139: OpKind = MCK_VReg_256; break;
18543 : case AMDGPU::VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140: OpKind = MCK_VReg_256; break;
18544 : case AMDGPU::VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141: OpKind = MCK_VReg_256; break;
18545 : case AMDGPU::VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142: OpKind = MCK_VReg_256; break;
18546 : case AMDGPU::VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143: OpKind = MCK_VReg_256; break;
18547 : case AMDGPU::VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144: OpKind = MCK_VReg_256; break;
18548 : case AMDGPU::VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145: OpKind = MCK_VReg_256; break;
18549 : case AMDGPU::VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146: OpKind = MCK_VReg_256; break;
18550 : case AMDGPU::VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147: OpKind = MCK_VReg_256; break;
18551 : case AMDGPU::VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148: OpKind = MCK_VReg_256; break;
18552 : case AMDGPU::VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149: OpKind = MCK_VReg_256; break;
18553 : case AMDGPU::VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150: OpKind = MCK_VReg_256; break;
18554 : case AMDGPU::VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151: OpKind = MCK_VReg_256; break;
18555 : case AMDGPU::VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152: OpKind = MCK_VReg_256; break;
18556 : case AMDGPU::VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153: OpKind = MCK_VReg_256; break;
18557 : case AMDGPU::VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154: OpKind = MCK_VReg_256; break;
18558 : case AMDGPU::VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155: OpKind = MCK_VReg_256; break;
18559 : case AMDGPU::VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156: OpKind = MCK_VReg_256; break;
18560 : case AMDGPU::VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157: OpKind = MCK_VReg_256; break;
18561 : case AMDGPU::VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158: OpKind = MCK_VReg_256; break;
18562 : case AMDGPU::VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159: OpKind = MCK_VReg_256; break;
18563 : case AMDGPU::VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160: OpKind = MCK_VReg_256; break;
18564 : case AMDGPU::VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161: OpKind = MCK_VReg_256; break;
18565 : case AMDGPU::VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162: OpKind = MCK_VReg_256; break;
18566 : case AMDGPU::VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163: OpKind = MCK_VReg_256; break;
18567 : case AMDGPU::VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164: OpKind = MCK_VReg_256; break;
18568 : case AMDGPU::VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165: OpKind = MCK_VReg_256; break;
18569 : case AMDGPU::VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166: OpKind = MCK_VReg_256; break;
18570 : case AMDGPU::VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167: OpKind = MCK_VReg_256; break;
18571 : case AMDGPU::VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168: OpKind = MCK_VReg_256; break;
18572 : case AMDGPU::VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169: OpKind = MCK_VReg_256; break;
18573 : case AMDGPU::VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170: OpKind = MCK_VReg_256; break;
18574 : case AMDGPU::VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171: OpKind = MCK_VReg_256; break;
18575 : case AMDGPU::VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172: OpKind = MCK_VReg_256; break;
18576 : case AMDGPU::VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173: OpKind = MCK_VReg_256; break;
18577 : case AMDGPU::VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174: OpKind = MCK_VReg_256; break;
18578 : case AMDGPU::VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175: OpKind = MCK_VReg_256; break;
18579 : case AMDGPU::VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176: OpKind = MCK_VReg_256; break;
18580 : case AMDGPU::VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177: OpKind = MCK_VReg_256; break;
18581 : case AMDGPU::VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178: OpKind = MCK_VReg_256; break;
18582 : case AMDGPU::VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179: OpKind = MCK_VReg_256; break;
18583 : case AMDGPU::VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180: OpKind = MCK_VReg_256; break;
18584 : case AMDGPU::VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181: OpKind = MCK_VReg_256; break;
18585 : case AMDGPU::VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182: OpKind = MCK_VReg_256; break;
18586 : case AMDGPU::VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183: OpKind = MCK_VReg_256; break;
18587 : case AMDGPU::VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184: OpKind = MCK_VReg_256; break;
18588 : case AMDGPU::VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185: OpKind = MCK_VReg_256; break;
18589 : case AMDGPU::VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186: OpKind = MCK_VReg_256; break;
18590 : case AMDGPU::VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187: OpKind = MCK_VReg_256; break;
18591 : case AMDGPU::VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188: OpKind = MCK_VReg_256; break;
18592 : case AMDGPU::VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189: OpKind = MCK_VReg_256; break;
18593 : case AMDGPU::VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190: OpKind = MCK_VReg_256; break;
18594 : case AMDGPU::VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191: OpKind = MCK_VReg_256; break;
18595 : case AMDGPU::VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192: OpKind = MCK_VReg_256; break;
18596 : case AMDGPU::VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193: OpKind = MCK_VReg_256; break;
18597 : case AMDGPU::VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194: OpKind = MCK_VReg_256; break;
18598 : case AMDGPU::VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195: OpKind = MCK_VReg_256; break;
18599 : case AMDGPU::VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196: OpKind = MCK_VReg_256; break;
18600 : case AMDGPU::VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197: OpKind = MCK_VReg_256; break;
18601 : case AMDGPU::VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198: OpKind = MCK_VReg_256; break;
18602 : case AMDGPU::VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199: OpKind = MCK_VReg_256; break;
18603 : case AMDGPU::VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200: OpKind = MCK_VReg_256; break;
18604 : case AMDGPU::VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201: OpKind = MCK_VReg_256; break;
18605 : case AMDGPU::VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202: OpKind = MCK_VReg_256; break;
18606 : case AMDGPU::VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203: OpKind = MCK_VReg_256; break;
18607 : case AMDGPU::VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204: OpKind = MCK_VReg_256; break;
18608 : case AMDGPU::VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205: OpKind = MCK_VReg_256; break;
18609 : case AMDGPU::VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206: OpKind = MCK_VReg_256; break;
18610 : case AMDGPU::VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207: OpKind = MCK_VReg_256; break;
18611 : case AMDGPU::VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208: OpKind = MCK_VReg_256; break;
18612 : case AMDGPU::VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209: OpKind = MCK_VReg_256; break;
18613 : case AMDGPU::VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210: OpKind = MCK_VReg_256; break;
18614 : case AMDGPU::VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211: OpKind = MCK_VReg_256; break;
18615 : case AMDGPU::VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212: OpKind = MCK_VReg_256; break;
18616 : case AMDGPU::VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213: OpKind = MCK_VReg_256; break;
18617 : case AMDGPU::VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214: OpKind = MCK_VReg_256; break;
18618 : case AMDGPU::VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215: OpKind = MCK_VReg_256; break;
18619 : case AMDGPU::VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216: OpKind = MCK_VReg_256; break;
18620 : case AMDGPU::VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217: OpKind = MCK_VReg_256; break;
18621 : case AMDGPU::VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218: OpKind = MCK_VReg_256; break;
18622 : case AMDGPU::VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219: OpKind = MCK_VReg_256; break;
18623 : case AMDGPU::VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220: OpKind = MCK_VReg_256; break;
18624 : case AMDGPU::VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221: OpKind = MCK_VReg_256; break;
18625 : case AMDGPU::VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222: OpKind = MCK_VReg_256; break;
18626 : case AMDGPU::VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223: OpKind = MCK_VReg_256; break;
18627 : case AMDGPU::VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224: OpKind = MCK_VReg_256; break;
18628 : case AMDGPU::VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225: OpKind = MCK_VReg_256; break;
18629 : case AMDGPU::VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226: OpKind = MCK_VReg_256; break;
18630 : case AMDGPU::VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227: OpKind = MCK_VReg_256; break;
18631 : case AMDGPU::VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228: OpKind = MCK_VReg_256; break;
18632 : case AMDGPU::VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229: OpKind = MCK_VReg_256; break;
18633 : case AMDGPU::VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230: OpKind = MCK_VReg_256; break;
18634 : case AMDGPU::VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231: OpKind = MCK_VReg_256; break;
18635 : case AMDGPU::VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232: OpKind = MCK_VReg_256; break;
18636 : case AMDGPU::VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233: OpKind = MCK_VReg_256; break;
18637 : case AMDGPU::VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234: OpKind = MCK_VReg_256; break;
18638 : case AMDGPU::VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235: OpKind = MCK_VReg_256; break;
18639 : case AMDGPU::VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236: OpKind = MCK_VReg_256; break;
18640 : case AMDGPU::VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237: OpKind = MCK_VReg_256; break;
18641 : case AMDGPU::VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238: OpKind = MCK_VReg_256; break;
18642 : case AMDGPU::VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239: OpKind = MCK_VReg_256; break;
18643 : case AMDGPU::VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240: OpKind = MCK_VReg_256; break;
18644 : case AMDGPU::VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241: OpKind = MCK_VReg_256; break;
18645 : case AMDGPU::VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242: OpKind = MCK_VReg_256; break;
18646 : case AMDGPU::VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243: OpKind = MCK_VReg_256; break;
18647 : case AMDGPU::VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244: OpKind = MCK_VReg_256; break;
18648 : case AMDGPU::VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245: OpKind = MCK_VReg_256; break;
18649 : case AMDGPU::VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246: OpKind = MCK_VReg_256; break;
18650 : case AMDGPU::VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247: OpKind = MCK_VReg_256; break;
18651 : case AMDGPU::VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248: OpKind = MCK_VReg_256; break;
18652 : case AMDGPU::VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249: OpKind = MCK_VReg_256; break;
18653 : case AMDGPU::VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250: OpKind = MCK_VReg_256; break;
18654 : case AMDGPU::VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251: OpKind = MCK_VReg_256; break;
18655 : case AMDGPU::VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251_VGPR252: OpKind = MCK_VReg_256; break;
18656 : case AMDGPU::VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251_VGPR252_VGPR253: OpKind = MCK_VReg_256; break;
18657 : case AMDGPU::VGPR247_VGPR248_VGPR249_VGPR250_VGPR251_VGPR252_VGPR253_VGPR254: OpKind = MCK_VReg_256; break;
18658 : case AMDGPU::VGPR248_VGPR249_VGPR250_VGPR251_VGPR252_VGPR253_VGPR254_VGPR255: OpKind = MCK_VReg_256; break;
18659 : case AMDGPU::VGPR0_VGPR1_VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15: OpKind = MCK_VReg_512; break;
18660 : case AMDGPU::VGPR1_VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16: OpKind = MCK_VReg_512; break;
18661 : case AMDGPU::VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17: OpKind = MCK_VReg_512; break;
18662 : case AMDGPU::VGPR3_VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18: OpKind = MCK_VReg_512; break;
18663 : case AMDGPU::VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19: OpKind = MCK_VReg_512; break;
18664 : case AMDGPU::VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20: OpKind = MCK_VReg_512; break;
18665 : case AMDGPU::VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21: OpKind = MCK_VReg_512; break;
18666 : case AMDGPU::VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22: OpKind = MCK_VReg_512; break;
18667 : case AMDGPU::VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23: OpKind = MCK_VReg_512; break;
18668 : case AMDGPU::VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24: OpKind = MCK_VReg_512; break;
18669 : case AMDGPU::VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25: OpKind = MCK_VReg_512; break;
18670 : case AMDGPU::VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26: OpKind = MCK_VReg_512; break;
18671 : case AMDGPU::VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27: OpKind = MCK_VReg_512; break;
18672 : case AMDGPU::VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28: OpKind = MCK_VReg_512; break;
18673 : case AMDGPU::VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29: OpKind = MCK_VReg_512; break;
18674 : case AMDGPU::VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30: OpKind = MCK_VReg_512; break;
18675 : case AMDGPU::VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31: OpKind = MCK_VReg_512; break;
18676 : case AMDGPU::VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32: OpKind = MCK_VReg_512; break;
18677 : case AMDGPU::VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33: OpKind = MCK_VReg_512; break;
18678 : case AMDGPU::VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34: OpKind = MCK_VReg_512; break;
18679 : case AMDGPU::VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35: OpKind = MCK_VReg_512; break;
18680 : case AMDGPU::VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36: OpKind = MCK_VReg_512; break;
18681 : case AMDGPU::VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37: OpKind = MCK_VReg_512; break;
18682 : case AMDGPU::VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38: OpKind = MCK_VReg_512; break;
18683 : case AMDGPU::VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39: OpKind = MCK_VReg_512; break;
18684 : case AMDGPU::VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40: OpKind = MCK_VReg_512; break;
18685 : case AMDGPU::VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41: OpKind = MCK_VReg_512; break;
18686 : case AMDGPU::VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42: OpKind = MCK_VReg_512; break;
18687 : case AMDGPU::VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43: OpKind = MCK_VReg_512; break;
18688 : case AMDGPU::VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44: OpKind = MCK_VReg_512; break;
18689 : case AMDGPU::VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45: OpKind = MCK_VReg_512; break;
18690 : case AMDGPU::VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46: OpKind = MCK_VReg_512; break;
18691 : case AMDGPU::VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47: OpKind = MCK_VReg_512; break;
18692 : case AMDGPU::VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48: OpKind = MCK_VReg_512; break;
18693 : case AMDGPU::VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49: OpKind = MCK_VReg_512; break;
18694 : case AMDGPU::VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50: OpKind = MCK_VReg_512; break;
18695 : case AMDGPU::VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51: OpKind = MCK_VReg_512; break;
18696 : case AMDGPU::VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52: OpKind = MCK_VReg_512; break;
18697 : case AMDGPU::VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53: OpKind = MCK_VReg_512; break;
18698 : case AMDGPU::VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54: OpKind = MCK_VReg_512; break;
18699 : case AMDGPU::VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55: OpKind = MCK_VReg_512; break;
18700 : case AMDGPU::VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56: OpKind = MCK_VReg_512; break;
18701 : case AMDGPU::VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57: OpKind = MCK_VReg_512; break;
18702 : case AMDGPU::VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58: OpKind = MCK_VReg_512; break;
18703 : case AMDGPU::VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59: OpKind = MCK_VReg_512; break;
18704 : case AMDGPU::VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60: OpKind = MCK_VReg_512; break;
18705 : case AMDGPU::VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61: OpKind = MCK_VReg_512; break;
18706 : case AMDGPU::VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62: OpKind = MCK_VReg_512; break;
18707 : case AMDGPU::VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63: OpKind = MCK_VReg_512; break;
18708 : case AMDGPU::VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64: OpKind = MCK_VReg_512; break;
18709 : case AMDGPU::VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65: OpKind = MCK_VReg_512; break;
18710 : case AMDGPU::VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66: OpKind = MCK_VReg_512; break;
18711 : case AMDGPU::VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67: OpKind = MCK_VReg_512; break;
18712 : case AMDGPU::VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68: OpKind = MCK_VReg_512; break;
18713 : case AMDGPU::VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69: OpKind = MCK_VReg_512; break;
18714 : case AMDGPU::VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70: OpKind = MCK_VReg_512; break;
18715 : case AMDGPU::VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71: OpKind = MCK_VReg_512; break;
18716 : case AMDGPU::VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72: OpKind = MCK_VReg_512; break;
18717 : case AMDGPU::VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73: OpKind = MCK_VReg_512; break;
18718 : case AMDGPU::VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74: OpKind = MCK_VReg_512; break;
18719 : case AMDGPU::VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75: OpKind = MCK_VReg_512; break;
18720 : case AMDGPU::VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76: OpKind = MCK_VReg_512; break;
18721 : case AMDGPU::VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77: OpKind = MCK_VReg_512; break;
18722 : case AMDGPU::VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78: OpKind = MCK_VReg_512; break;
18723 : case AMDGPU::VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79: OpKind = MCK_VReg_512; break;
18724 : case AMDGPU::VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80: OpKind = MCK_VReg_512; break;
18725 : case AMDGPU::VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81: OpKind = MCK_VReg_512; break;
18726 : case AMDGPU::VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82: OpKind = MCK_VReg_512; break;
18727 : case AMDGPU::VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83: OpKind = MCK_VReg_512; break;
18728 : case AMDGPU::VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84: OpKind = MCK_VReg_512; break;
18729 : case AMDGPU::VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85: OpKind = MCK_VReg_512; break;
18730 : case AMDGPU::VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86: OpKind = MCK_VReg_512; break;
18731 : case AMDGPU::VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87: OpKind = MCK_VReg_512; break;
18732 : case AMDGPU::VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88: OpKind = MCK_VReg_512; break;
18733 : case AMDGPU::VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89: OpKind = MCK_VReg_512; break;
18734 : case AMDGPU::VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90: OpKind = MCK_VReg_512; break;
18735 : case AMDGPU::VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91: OpKind = MCK_VReg_512; break;
18736 : case AMDGPU::VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92: OpKind = MCK_VReg_512; break;
18737 : case AMDGPU::VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93: OpKind = MCK_VReg_512; break;
18738 : case AMDGPU::VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94: OpKind = MCK_VReg_512; break;
18739 : case AMDGPU::VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95: OpKind = MCK_VReg_512; break;
18740 : case AMDGPU::VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96: OpKind = MCK_VReg_512; break;
18741 : case AMDGPU::VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97: OpKind = MCK_VReg_512; break;
18742 : case AMDGPU::VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98: OpKind = MCK_VReg_512; break;
18743 : case AMDGPU::VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99: OpKind = MCK_VReg_512; break;
18744 : case AMDGPU::VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100: OpKind = MCK_VReg_512; break;
18745 : case AMDGPU::VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101: OpKind = MCK_VReg_512; break;
18746 : case AMDGPU::VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102: OpKind = MCK_VReg_512; break;
18747 : case AMDGPU::VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103: OpKind = MCK_VReg_512; break;
18748 : case AMDGPU::VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104: OpKind = MCK_VReg_512; break;
18749 : case AMDGPU::VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105: OpKind = MCK_VReg_512; break;
18750 : case AMDGPU::VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106: OpKind = MCK_VReg_512; break;
18751 : case AMDGPU::VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107: OpKind = MCK_VReg_512; break;
18752 : case AMDGPU::VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108: OpKind = MCK_VReg_512; break;
18753 : case AMDGPU::VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109: OpKind = MCK_VReg_512; break;
18754 : case AMDGPU::VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110: OpKind = MCK_VReg_512; break;
18755 : case AMDGPU::VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111: OpKind = MCK_VReg_512; break;
18756 : case AMDGPU::VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112: OpKind = MCK_VReg_512; break;
18757 : case AMDGPU::VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113: OpKind = MCK_VReg_512; break;
18758 : case AMDGPU::VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114: OpKind = MCK_VReg_512; break;
18759 : case AMDGPU::VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115: OpKind = MCK_VReg_512; break;
18760 : case AMDGPU::VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116: OpKind = MCK_VReg_512; break;
18761 : case AMDGPU::VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117: OpKind = MCK_VReg_512; break;
18762 : case AMDGPU::VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118: OpKind = MCK_VReg_512; break;
18763 : case AMDGPU::VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119: OpKind = MCK_VReg_512; break;
18764 : case AMDGPU::VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120: OpKind = MCK_VReg_512; break;
18765 : case AMDGPU::VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121: OpKind = MCK_VReg_512; break;
18766 : case AMDGPU::VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122: OpKind = MCK_VReg_512; break;
18767 : case AMDGPU::VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123: OpKind = MCK_VReg_512; break;
18768 : case AMDGPU::VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124: OpKind = MCK_VReg_512; break;
18769 : case AMDGPU::VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125: OpKind = MCK_VReg_512; break;
18770 : case AMDGPU::VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126: OpKind = MCK_VReg_512; break;
18771 : case AMDGPU::VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127: OpKind = MCK_VReg_512; break;
18772 : case AMDGPU::VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128: OpKind = MCK_VReg_512; break;
18773 : case AMDGPU::VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129: OpKind = MCK_VReg_512; break;
18774 : case AMDGPU::VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130: OpKind = MCK_VReg_512; break;
18775 : case AMDGPU::VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131: OpKind = MCK_VReg_512; break;
18776 : case AMDGPU::VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132: OpKind = MCK_VReg_512; break;
18777 : case AMDGPU::VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133: OpKind = MCK_VReg_512; break;
18778 : case AMDGPU::VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134: OpKind = MCK_VReg_512; break;
18779 : case AMDGPU::VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135: OpKind = MCK_VReg_512; break;
18780 : case AMDGPU::VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136: OpKind = MCK_VReg_512; break;
18781 : case AMDGPU::VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137: OpKind = MCK_VReg_512; break;
18782 : case AMDGPU::VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138: OpKind = MCK_VReg_512; break;
18783 : case AMDGPU::VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139: OpKind = MCK_VReg_512; break;
18784 : case AMDGPU::VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140: OpKind = MCK_VReg_512; break;
18785 : case AMDGPU::VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141: OpKind = MCK_VReg_512; break;
18786 : case AMDGPU::VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142: OpKind = MCK_VReg_512; break;
18787 : case AMDGPU::VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143: OpKind = MCK_VReg_512; break;
18788 : case AMDGPU::VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144: OpKind = MCK_VReg_512; break;
18789 : case AMDGPU::VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145: OpKind = MCK_VReg_512; break;
18790 : case AMDGPU::VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146: OpKind = MCK_VReg_512; break;
18791 : case AMDGPU::VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147: OpKind = MCK_VReg_512; break;
18792 : case AMDGPU::VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148: OpKind = MCK_VReg_512; break;
18793 : case AMDGPU::VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149: OpKind = MCK_VReg_512; break;
18794 : case AMDGPU::VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150: OpKind = MCK_VReg_512; break;
18795 : case AMDGPU::VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151: OpKind = MCK_VReg_512; break;
18796 : case AMDGPU::VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152: OpKind = MCK_VReg_512; break;
18797 : case AMDGPU::VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153: OpKind = MCK_VReg_512; break;
18798 : case AMDGPU::VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154: OpKind = MCK_VReg_512; break;
18799 : case AMDGPU::VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155: OpKind = MCK_VReg_512; break;
18800 : case AMDGPU::VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156: OpKind = MCK_VReg_512; break;
18801 : case AMDGPU::VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157: OpKind = MCK_VReg_512; break;
18802 : case AMDGPU::VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158: OpKind = MCK_VReg_512; break;
18803 : case AMDGPU::VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159: OpKind = MCK_VReg_512; break;
18804 : case AMDGPU::VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160: OpKind = MCK_VReg_512; break;
18805 : case AMDGPU::VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161: OpKind = MCK_VReg_512; break;
18806 : case AMDGPU::VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162: OpKind = MCK_VReg_512; break;
18807 : case AMDGPU::VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163: OpKind = MCK_VReg_512; break;
18808 : case AMDGPU::VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164: OpKind = MCK_VReg_512; break;
18809 : case AMDGPU::VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165: OpKind = MCK_VReg_512; break;
18810 : case AMDGPU::VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166: OpKind = MCK_VReg_512; break;
18811 : case AMDGPU::VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167: OpKind = MCK_VReg_512; break;
18812 : case AMDGPU::VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168: OpKind = MCK_VReg_512; break;
18813 : case AMDGPU::VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169: OpKind = MCK_VReg_512; break;
18814 : case AMDGPU::VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170: OpKind = MCK_VReg_512; break;
18815 : case AMDGPU::VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171: OpKind = MCK_VReg_512; break;
18816 : case AMDGPU::VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172: OpKind = MCK_VReg_512; break;
18817 : case AMDGPU::VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173: OpKind = MCK_VReg_512; break;
18818 : case AMDGPU::VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174: OpKind = MCK_VReg_512; break;
18819 : case AMDGPU::VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175: OpKind = MCK_VReg_512; break;
18820 : case AMDGPU::VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176: OpKind = MCK_VReg_512; break;
18821 : case AMDGPU::VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177: OpKind = MCK_VReg_512; break;
18822 : case AMDGPU::VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178: OpKind = MCK_VReg_512; break;
18823 : case AMDGPU::VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179: OpKind = MCK_VReg_512; break;
18824 : case AMDGPU::VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180: OpKind = MCK_VReg_512; break;
18825 : case AMDGPU::VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181: OpKind = MCK_VReg_512; break;
18826 : case AMDGPU::VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182: OpKind = MCK_VReg_512; break;
18827 : case AMDGPU::VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183: OpKind = MCK_VReg_512; break;
18828 : case AMDGPU::VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184: OpKind = MCK_VReg_512; break;
18829 : case AMDGPU::VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185: OpKind = MCK_VReg_512; break;
18830 : case AMDGPU::VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186: OpKind = MCK_VReg_512; break;
18831 : case AMDGPU::VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187: OpKind = MCK_VReg_512; break;
18832 : case AMDGPU::VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188: OpKind = MCK_VReg_512; break;
18833 : case AMDGPU::VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189: OpKind = MCK_VReg_512; break;
18834 : case AMDGPU::VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190: OpKind = MCK_VReg_512; break;
18835 : case AMDGPU::VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191: OpKind = MCK_VReg_512; break;
18836 : case AMDGPU::VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192: OpKind = MCK_VReg_512; break;
18837 : case AMDGPU::VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193: OpKind = MCK_VReg_512; break;
18838 : case AMDGPU::VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194: OpKind = MCK_VReg_512; break;
18839 : case AMDGPU::VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195: OpKind = MCK_VReg_512; break;
18840 : case AMDGPU::VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196: OpKind = MCK_VReg_512; break;
18841 : case AMDGPU::VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197: OpKind = MCK_VReg_512; break;
18842 : case AMDGPU::VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198: OpKind = MCK_VReg_512; break;
18843 : case AMDGPU::VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199: OpKind = MCK_VReg_512; break;
18844 : case AMDGPU::VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200: OpKind = MCK_VReg_512; break;
18845 : case AMDGPU::VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201: OpKind = MCK_VReg_512; break;
18846 : case AMDGPU::VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202: OpKind = MCK_VReg_512; break;
18847 : case AMDGPU::VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203: OpKind = MCK_VReg_512; break;
18848 : case AMDGPU::VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204: OpKind = MCK_VReg_512; break;
18849 : case AMDGPU::VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205: OpKind = MCK_VReg_512; break;
18850 : case AMDGPU::VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206: OpKind = MCK_VReg_512; break;
18851 : case AMDGPU::VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207: OpKind = MCK_VReg_512; break;
18852 : case AMDGPU::VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208: OpKind = MCK_VReg_512; break;
18853 : case AMDGPU::VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209: OpKind = MCK_VReg_512; break;
18854 : case AMDGPU::VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210: OpKind = MCK_VReg_512; break;
18855 : case AMDGPU::VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211: OpKind = MCK_VReg_512; break;
18856 : case AMDGPU::VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212: OpKind = MCK_VReg_512; break;
18857 : case AMDGPU::VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213: OpKind = MCK_VReg_512; break;
18858 : case AMDGPU::VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214: OpKind = MCK_VReg_512; break;
18859 : case AMDGPU::VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215: OpKind = MCK_VReg_512; break;
18860 : case AMDGPU::VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216: OpKind = MCK_VReg_512; break;
18861 : case AMDGPU::VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217: OpKind = MCK_VReg_512; break;
18862 : case AMDGPU::VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218: OpKind = MCK_VReg_512; break;
18863 : case AMDGPU::VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219: OpKind = MCK_VReg_512; break;
18864 : case AMDGPU::VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220: OpKind = MCK_VReg_512; break;
18865 : case AMDGPU::VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221: OpKind = MCK_VReg_512; break;
18866 : case AMDGPU::VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222: OpKind = MCK_VReg_512; break;
18867 : case AMDGPU::VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223: OpKind = MCK_VReg_512; break;
18868 : case AMDGPU::VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224: OpKind = MCK_VReg_512; break;
18869 : case AMDGPU::VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225: OpKind = MCK_VReg_512; break;
18870 : case AMDGPU::VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226: OpKind = MCK_VReg_512; break;
18871 : case AMDGPU::VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227: OpKind = MCK_VReg_512; break;
18872 : case AMDGPU::VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228: OpKind = MCK_VReg_512; break;
18873 : case AMDGPU::VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229: OpKind = MCK_VReg_512; break;
18874 : case AMDGPU::VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230: OpKind = MCK_VReg_512; break;
18875 : case AMDGPU::VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231: OpKind = MCK_VReg_512; break;
18876 : case AMDGPU::VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232: OpKind = MCK_VReg_512; break;
18877 : case AMDGPU::VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233: OpKind = MCK_VReg_512; break;
18878 : case AMDGPU::VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234: OpKind = MCK_VReg_512; break;
18879 : case AMDGPU::VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235: OpKind = MCK_VReg_512; break;
18880 : case AMDGPU::VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236: OpKind = MCK_VReg_512; break;
18881 : case AMDGPU::VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237: OpKind = MCK_VReg_512; break;
18882 : case AMDGPU::VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238: OpKind = MCK_VReg_512; break;
18883 : case AMDGPU::VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239: OpKind = MCK_VReg_512; break;
18884 : case AMDGPU::VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240: OpKind = MCK_VReg_512; break;
18885 : case AMDGPU::VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241: OpKind = MCK_VReg_512; break;
18886 : case AMDGPU::VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242: OpKind = MCK_VReg_512; break;
18887 : case AMDGPU::VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243: OpKind = MCK_VReg_512; break;
18888 : case AMDGPU::VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244: OpKind = MCK_VReg_512; break;
18889 : case AMDGPU::VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245: OpKind = MCK_VReg_512; break;
18890 : case AMDGPU::VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246: OpKind = MCK_VReg_512; break;
18891 : case AMDGPU::VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247: OpKind = MCK_VReg_512; break;
18892 : case AMDGPU::VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248: OpKind = MCK_VReg_512; break;
18893 : case AMDGPU::VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249: OpKind = MCK_VReg_512; break;
18894 : case AMDGPU::VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250: OpKind = MCK_VReg_512; break;
18895 : case AMDGPU::VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251: OpKind = MCK_VReg_512; break;
18896 : case AMDGPU::VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251_VGPR252: OpKind = MCK_VReg_512; break;
18897 : case AMDGPU::VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251_VGPR252_VGPR253: OpKind = MCK_VReg_512; break;
18898 : case AMDGPU::VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251_VGPR252_VGPR253_VGPR254: OpKind = MCK_VReg_512; break;
18899 : case AMDGPU::VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251_VGPR252_VGPR253_VGPR254_VGPR255: OpKind = MCK_VReg_512; break;
18900 : case AMDGPU::VGPR0_VGPR1: OpKind = MCK_VReg_64; break;
18901 : case AMDGPU::VGPR1_VGPR2: OpKind = MCK_VReg_64; break;
18902 : case AMDGPU::VGPR2_VGPR3: OpKind = MCK_VReg_64; break;
18903 : case AMDGPU::VGPR3_VGPR4: OpKind = MCK_VReg_64; break;
18904 : case AMDGPU::VGPR4_VGPR5: OpKind = MCK_VReg_64; break;
18905 : case AMDGPU::VGPR5_VGPR6: OpKind = MCK_VReg_64; break;
18906 : case AMDGPU::VGPR6_VGPR7: OpKind = MCK_VReg_64; break;
18907 : case AMDGPU::VGPR7_VGPR8: OpKind = MCK_VReg_64; break;
18908 : case AMDGPU::VGPR8_VGPR9: OpKind = MCK_VReg_64; break;
18909 : case AMDGPU::VGPR9_VGPR10: OpKind = MCK_VReg_64; break;
18910 : case AMDGPU::VGPR10_VGPR11: OpKind = MCK_VReg_64; break;
18911 : case AMDGPU::VGPR11_VGPR12: OpKind = MCK_VReg_64; break;
18912 : case AMDGPU::VGPR12_VGPR13: OpKind = MCK_VReg_64; break;
18913 : case AMDGPU::VGPR13_VGPR14: OpKind = MCK_VReg_64; break;
18914 : case AMDGPU::VGPR14_VGPR15: OpKind = MCK_VReg_64; break;
18915 : case AMDGPU::VGPR15_VGPR16: OpKind = MCK_VReg_64; break;
18916 : case AMDGPU::VGPR16_VGPR17: OpKind = MCK_VReg_64; break;
18917 : case AMDGPU::VGPR17_VGPR18: OpKind = MCK_VReg_64; break;
18918 : case AMDGPU::VGPR18_VGPR19: OpKind = MCK_VReg_64; break;
18919 : case AMDGPU::VGPR19_VGPR20: OpKind = MCK_VReg_64; break;
18920 : case AMDGPU::VGPR20_VGPR21: OpKind = MCK_VReg_64; break;
18921 : case AMDGPU::VGPR21_VGPR22: OpKind = MCK_VReg_64; break;
18922 : case AMDGPU::VGPR22_VGPR23: OpKind = MCK_VReg_64; break;
18923 : case AMDGPU::VGPR23_VGPR24: OpKind = MCK_VReg_64; break;
18924 : case AMDGPU::VGPR24_VGPR25: OpKind = MCK_VReg_64; break;
18925 : case AMDGPU::VGPR25_VGPR26: OpKind = MCK_VReg_64; break;
18926 : case AMDGPU::VGPR26_VGPR27: OpKind = MCK_VReg_64; break;
18927 : case AMDGPU::VGPR27_VGPR28: OpKind = MCK_VReg_64; break;
18928 : case AMDGPU::VGPR28_VGPR29: OpKind = MCK_VReg_64; break;
18929 : case AMDGPU::VGPR29_VGPR30: OpKind = MCK_VReg_64; break;
18930 : case AMDGPU::VGPR30_VGPR31: OpKind = MCK_VReg_64; break;
18931 : case AMDGPU::VGPR31_VGPR32: OpKind = MCK_VReg_64; break;
18932 : case AMDGPU::VGPR32_VGPR33: OpKind = MCK_VReg_64; break;
18933 : case AMDGPU::VGPR33_VGPR34: OpKind = MCK_VReg_64; break;
18934 : case AMDGPU::VGPR34_VGPR35: OpKind = MCK_VReg_64; break;
18935 : case AMDGPU::VGPR35_VGPR36: OpKind = MCK_VReg_64; break;
18936 : case AMDGPU::VGPR36_VGPR37: OpKind = MCK_VReg_64; break;
18937 : case AMDGPU::VGPR37_VGPR38: OpKind = MCK_VReg_64; break;
18938 : case AMDGPU::VGPR38_VGPR39: OpKind = MCK_VReg_64; break;
18939 : case AMDGPU::VGPR39_VGPR40: OpKind = MCK_VReg_64; break;
18940 : case AMDGPU::VGPR40_VGPR41: OpKind = MCK_VReg_64; break;
18941 : case AMDGPU::VGPR41_VGPR42: OpKind = MCK_VReg_64; break;
18942 : case AMDGPU::VGPR42_VGPR43: OpKind = MCK_VReg_64; break;
18943 : case AMDGPU::VGPR43_VGPR44: OpKind = MCK_VReg_64; break;
18944 : case AMDGPU::VGPR44_VGPR45: OpKind = MCK_VReg_64; break;
18945 : case AMDGPU::VGPR45_VGPR46: OpKind = MCK_VReg_64; break;
18946 : case AMDGPU::VGPR46_VGPR47: OpKind = MCK_VReg_64; break;
18947 : case AMDGPU::VGPR47_VGPR48: OpKind = MCK_VReg_64; break;
18948 : case AMDGPU::VGPR48_VGPR49: OpKind = MCK_VReg_64; break;
18949 : case AMDGPU::VGPR49_VGPR50: OpKind = MCK_VReg_64; break;
18950 : case AMDGPU::VGPR50_VGPR51: OpKind = MCK_VReg_64; break;
18951 : case AMDGPU::VGPR51_VGPR52: OpKind = MCK_VReg_64; break;
18952 : case AMDGPU::VGPR52_VGPR53: OpKind = MCK_VReg_64; break;
18953 : case AMDGPU::VGPR53_VGPR54: OpKind = MCK_VReg_64; break;
18954 : case AMDGPU::VGPR54_VGPR55: OpKind = MCK_VReg_64; break;
18955 : case AMDGPU::VGPR55_VGPR56: OpKind = MCK_VReg_64; break;
18956 : case AMDGPU::VGPR56_VGPR57: OpKind = MCK_VReg_64; break;
18957 : case AMDGPU::VGPR57_VGPR58: OpKind = MCK_VReg_64; break;
18958 : case AMDGPU::VGPR58_VGPR59: OpKind = MCK_VReg_64; break;
18959 : case AMDGPU::VGPR59_VGPR60: OpKind = MCK_VReg_64; break;
18960 : case AMDGPU::VGPR60_VGPR61: OpKind = MCK_VReg_64; break;
18961 : case AMDGPU::VGPR61_VGPR62: OpKind = MCK_VReg_64; break;
18962 : case AMDGPU::VGPR62_VGPR63: OpKind = MCK_VReg_64; break;
18963 : case AMDGPU::VGPR63_VGPR64: OpKind = MCK_VReg_64; break;
18964 : case AMDGPU::VGPR64_VGPR65: OpKind = MCK_VReg_64; break;
18965 : case AMDGPU::VGPR65_VGPR66: OpKind = MCK_VReg_64; break;
18966 : case AMDGPU::VGPR66_VGPR67: OpKind = MCK_VReg_64; break;
18967 : case AMDGPU::VGPR67_VGPR68: OpKind = MCK_VReg_64; break;
18968 : case AMDGPU::VGPR68_VGPR69: OpKind = MCK_VReg_64; break;
18969 : case AMDGPU::VGPR69_VGPR70: OpKind = MCK_VReg_64; break;
18970 : case AMDGPU::VGPR70_VGPR71: OpKind = MCK_VReg_64; break;
18971 : case AMDGPU::VGPR71_VGPR72: OpKind = MCK_VReg_64; break;
18972 : case AMDGPU::VGPR72_VGPR73: OpKind = MCK_VReg_64; break;
18973 : case AMDGPU::VGPR73_VGPR74: OpKind = MCK_VReg_64; break;
18974 : case AMDGPU::VGPR74_VGPR75: OpKind = MCK_VReg_64; break;
18975 : case AMDGPU::VGPR75_VGPR76: OpKind = MCK_VReg_64; break;
18976 : case AMDGPU::VGPR76_VGPR77: OpKind = MCK_VReg_64; break;
18977 : case AMDGPU::VGPR77_VGPR78: OpKind = MCK_VReg_64; break;
18978 : case AMDGPU::VGPR78_VGPR79: OpKind = MCK_VReg_64; break;
18979 : case AMDGPU::VGPR79_VGPR80: OpKind = MCK_VReg_64; break;
18980 : case AMDGPU::VGPR80_VGPR81: OpKind = MCK_VReg_64; break;
18981 : case AMDGPU::VGPR81_VGPR82: OpKind = MCK_VReg_64; break;
18982 : case AMDGPU::VGPR82_VGPR83: OpKind = MCK_VReg_64; break;
18983 : case AMDGPU::VGPR83_VGPR84: OpKind = MCK_VReg_64; break;
18984 : case AMDGPU::VGPR84_VGPR85: OpKind = MCK_VReg_64; break;
18985 : case AMDGPU::VGPR85_VGPR86: OpKind = MCK_VReg_64; break;
18986 : case AMDGPU::VGPR86_VGPR87: OpKind = MCK_VReg_64; break;
18987 : case AMDGPU::VGPR87_VGPR88: OpKind = MCK_VReg_64; break;
18988 : case AMDGPU::VGPR88_VGPR89: OpKind = MCK_VReg_64; break;
18989 : case AMDGPU::VGPR89_VGPR90: OpKind = MCK_VReg_64; break;
18990 : case AMDGPU::VGPR90_VGPR91: OpKind = MCK_VReg_64; break;
18991 : case AMDGPU::VGPR91_VGPR92: OpKind = MCK_VReg_64; break;
18992 : case AMDGPU::VGPR92_VGPR93: OpKind = MCK_VReg_64; break;
18993 : case AMDGPU::VGPR93_VGPR94: OpKind = MCK_VReg_64; break;
18994 : case AMDGPU::VGPR94_VGPR95: OpKind = MCK_VReg_64; break;
18995 : case AMDGPU::VGPR95_VGPR96: OpKind = MCK_VReg_64; break;
18996 : case AMDGPU::VGPR96_VGPR97: OpKind = MCK_VReg_64; break;
18997 : case AMDGPU::VGPR97_VGPR98: OpKind = MCK_VReg_64; break;
18998 : case AMDGPU::VGPR98_VGPR99: OpKind = MCK_VReg_64; break;
18999 : case AMDGPU::VGPR99_VGPR100: OpKind = MCK_VReg_64; break;
19000 : case AMDGPU::VGPR100_VGPR101: OpKind = MCK_VReg_64; break;
19001 : case AMDGPU::VGPR101_VGPR102: OpKind = MCK_VReg_64; break;
19002 : case AMDGPU::VGPR102_VGPR103: OpKind = MCK_VReg_64; break;
19003 : case AMDGPU::VGPR103_VGPR104: OpKind = MCK_VReg_64; break;
19004 : case AMDGPU::VGPR104_VGPR105: OpKind = MCK_VReg_64; break;
19005 : case AMDGPU::VGPR105_VGPR106: OpKind = MCK_VReg_64; break;
19006 : case AMDGPU::VGPR106_VGPR107: OpKind = MCK_VReg_64; break;
19007 : case AMDGPU::VGPR107_VGPR108: OpKind = MCK_VReg_64; break;
19008 : case AMDGPU::VGPR108_VGPR109: OpKind = MCK_VReg_64; break;
19009 : case AMDGPU::VGPR109_VGPR110: OpKind = MCK_VReg_64; break;
19010 : case AMDGPU::VGPR110_VGPR111: OpKind = MCK_VReg_64; break;
19011 : case AMDGPU::VGPR111_VGPR112: OpKind = MCK_VReg_64; break;
19012 : case AMDGPU::VGPR112_VGPR113: OpKind = MCK_VReg_64; break;
19013 : case AMDGPU::VGPR113_VGPR114: OpKind = MCK_VReg_64; break;
19014 : case AMDGPU::VGPR114_VGPR115: OpKind = MCK_VReg_64; break;
19015 : case AMDGPU::VGPR115_VGPR116: OpKind = MCK_VReg_64; break;
19016 : case AMDGPU::VGPR116_VGPR117: OpKind = MCK_VReg_64; break;
19017 : case AMDGPU::VGPR117_VGPR118: OpKind = MCK_VReg_64; break;
19018 : case AMDGPU::VGPR118_VGPR119: OpKind = MCK_VReg_64; break;
19019 : case AMDGPU::VGPR119_VGPR120: OpKind = MCK_VReg_64; break;
19020 : case AMDGPU::VGPR120_VGPR121: OpKind = MCK_VReg_64; break;
19021 : case AMDGPU::VGPR121_VGPR122: OpKind = MCK_VReg_64; break;
19022 : case AMDGPU::VGPR122_VGPR123: OpKind = MCK_VReg_64; break;
19023 : case AMDGPU::VGPR123_VGPR124: OpKind = MCK_VReg_64; break;
19024 : case AMDGPU::VGPR124_VGPR125: OpKind = MCK_VReg_64; break;
19025 : case AMDGPU::VGPR125_VGPR126: OpKind = MCK_VReg_64; break;
19026 : case AMDGPU::VGPR126_VGPR127: OpKind = MCK_VReg_64; break;
19027 : case AMDGPU::VGPR127_VGPR128: OpKind = MCK_VReg_64; break;
19028 : case AMDGPU::VGPR128_VGPR129: OpKind = MCK_VReg_64; break;
19029 : case AMDGPU::VGPR129_VGPR130: OpKind = MCK_VReg_64; break;
19030 : case AMDGPU::VGPR130_VGPR131: OpKind = MCK_VReg_64; break;
19031 : case AMDGPU::VGPR131_VGPR132: OpKind = MCK_VReg_64; break;
19032 : case AMDGPU::VGPR132_VGPR133: OpKind = MCK_VReg_64; break;
19033 : case AMDGPU::VGPR133_VGPR134: OpKind = MCK_VReg_64; break;
19034 : case AMDGPU::VGPR134_VGPR135: OpKind = MCK_VReg_64; break;
19035 : case AMDGPU::VGPR135_VGPR136: OpKind = MCK_VReg_64; break;
19036 : case AMDGPU::VGPR136_VGPR137: OpKind = MCK_VReg_64; break;
19037 : case AMDGPU::VGPR137_VGPR138: OpKind = MCK_VReg_64; break;
19038 : case AMDGPU::VGPR138_VGPR139: OpKind = MCK_VReg_64; break;
19039 : case AMDGPU::VGPR139_VGPR140: OpKind = MCK_VReg_64; break;
19040 : case AMDGPU::VGPR140_VGPR141: OpKind = MCK_VReg_64; break;
19041 : case AMDGPU::VGPR141_VGPR142: OpKind = MCK_VReg_64; break;
19042 : case AMDGPU::VGPR142_VGPR143: OpKind = MCK_VReg_64; break;
19043 : case AMDGPU::VGPR143_VGPR144: OpKind = MCK_VReg_64; break;
19044 : case AMDGPU::VGPR144_VGPR145: OpKind = MCK_VReg_64; break;
19045 : case AMDGPU::VGPR145_VGPR146: OpKind = MCK_VReg_64; break;
19046 : case AMDGPU::VGPR146_VGPR147: OpKind = MCK_VReg_64; break;
19047 : case AMDGPU::VGPR147_VGPR148: OpKind = MCK_VReg_64; break;
19048 : case AMDGPU::VGPR148_VGPR149: OpKind = MCK_VReg_64; break;
19049 : case AMDGPU::VGPR149_VGPR150: OpKind = MCK_VReg_64; break;
19050 : case AMDGPU::VGPR150_VGPR151: OpKind = MCK_VReg_64; break;
19051 : case AMDGPU::VGPR151_VGPR152: OpKind = MCK_VReg_64; break;
19052 : case AMDGPU::VGPR152_VGPR153: OpKind = MCK_VReg_64; break;
19053 : case AMDGPU::VGPR153_VGPR154: OpKind = MCK_VReg_64; break;
19054 : case AMDGPU::VGPR154_VGPR155: OpKind = MCK_VReg_64; break;
19055 : case AMDGPU::VGPR155_VGPR156: OpKind = MCK_VReg_64; break;
19056 : case AMDGPU::VGPR156_VGPR157: OpKind = MCK_VReg_64; break;
19057 : case AMDGPU::VGPR157_VGPR158: OpKind = MCK_VReg_64; break;
19058 : case AMDGPU::VGPR158_VGPR159: OpKind = MCK_VReg_64; break;
19059 : case AMDGPU::VGPR159_VGPR160: OpKind = MCK_VReg_64; break;
19060 : case AMDGPU::VGPR160_VGPR161: OpKind = MCK_VReg_64; break;
19061 : case AMDGPU::VGPR161_VGPR162: OpKind = MCK_VReg_64; break;
19062 : case AMDGPU::VGPR162_VGPR163: OpKind = MCK_VReg_64; break;
19063 : case AMDGPU::VGPR163_VGPR164: OpKind = MCK_VReg_64; break;
19064 : case AMDGPU::VGPR164_VGPR165: OpKind = MCK_VReg_64; break;
19065 : case AMDGPU::VGPR165_VGPR166: OpKind = MCK_VReg_64; break;
19066 : case AMDGPU::VGPR166_VGPR167: OpKind = MCK_VReg_64; break;
19067 : case AMDGPU::VGPR167_VGPR168: OpKind = MCK_VReg_64; break;
19068 : case AMDGPU::VGPR168_VGPR169: OpKind = MCK_VReg_64; break;
19069 : case AMDGPU::VGPR169_VGPR170: OpKind = MCK_VReg_64; break;
19070 : case AMDGPU::VGPR170_VGPR171: OpKind = MCK_VReg_64; break;
19071 : case AMDGPU::VGPR171_VGPR172: OpKind = MCK_VReg_64; break;
19072 : case AMDGPU::VGPR172_VGPR173: OpKind = MCK_VReg_64; break;
19073 : case AMDGPU::VGPR173_VGPR174: OpKind = MCK_VReg_64; break;
19074 : case AMDGPU::VGPR174_VGPR175: OpKind = MCK_VReg_64; break;
19075 : case AMDGPU::VGPR175_VGPR176: OpKind = MCK_VReg_64; break;
19076 : case AMDGPU::VGPR176_VGPR177: OpKind = MCK_VReg_64; break;
19077 : case AMDGPU::VGPR177_VGPR178: OpKind = MCK_VReg_64; break;
19078 : case AMDGPU::VGPR178_VGPR179: OpKind = MCK_VReg_64; break;
19079 : case AMDGPU::VGPR179_VGPR180: OpKind = MCK_VReg_64; break;
19080 : case AMDGPU::VGPR180_VGPR181: OpKind = MCK_VReg_64; break;
19081 : case AMDGPU::VGPR181_VGPR182: OpKind = MCK_VReg_64; break;
19082 : case AMDGPU::VGPR182_VGPR183: OpKind = MCK_VReg_64; break;
19083 : case AMDGPU::VGPR183_VGPR184: OpKind = MCK_VReg_64; break;
19084 : case AMDGPU::VGPR184_VGPR185: OpKind = MCK_VReg_64; break;
19085 : case AMDGPU::VGPR185_VGPR186: OpKind = MCK_VReg_64; break;
19086 : case AMDGPU::VGPR186_VGPR187: OpKind = MCK_VReg_64; break;
19087 : case AMDGPU::VGPR187_VGPR188: OpKind = MCK_VReg_64; break;
19088 : case AMDGPU::VGPR188_VGPR189: OpKind = MCK_VReg_64; break;
19089 : case AMDGPU::VGPR189_VGPR190: OpKind = MCK_VReg_64; break;
19090 : case AMDGPU::VGPR190_VGPR191: OpKind = MCK_VReg_64; break;
19091 : case AMDGPU::VGPR191_VGPR192: OpKind = MCK_VReg_64; break;
19092 : case AMDGPU::VGPR192_VGPR193: OpKind = MCK_VReg_64; break;
19093 : case AMDGPU::VGPR193_VGPR194: OpKind = MCK_VReg_64; break;
19094 : case AMDGPU::VGPR194_VGPR195: OpKind = MCK_VReg_64; break;
19095 : case AMDGPU::VGPR195_VGPR196: OpKind = MCK_VReg_64; break;
19096 : case AMDGPU::VGPR196_VGPR197: OpKind = MCK_VReg_64; break;
19097 : case AMDGPU::VGPR197_VGPR198: OpKind = MCK_VReg_64; break;
19098 : case AMDGPU::VGPR198_VGPR199: OpKind = MCK_VReg_64; break;
19099 : case AMDGPU::VGPR199_VGPR200: OpKind = MCK_VReg_64; break;
19100 : case AMDGPU::VGPR200_VGPR201: OpKind = MCK_VReg_64; break;
19101 : case AMDGPU::VGPR201_VGPR202: OpKind = MCK_VReg_64; break;
19102 : case AMDGPU::VGPR202_VGPR203: OpKind = MCK_VReg_64; break;
19103 : case AMDGPU::VGPR203_VGPR204: OpKind = MCK_VReg_64; break;
19104 : case AMDGPU::VGPR204_VGPR205: OpKind = MCK_VReg_64; break;
19105 : case AMDGPU::VGPR205_VGPR206: OpKind = MCK_VReg_64; break;
19106 : case AMDGPU::VGPR206_VGPR207: OpKind = MCK_VReg_64; break;
19107 : case AMDGPU::VGPR207_VGPR208: OpKind = MCK_VReg_64; break;
19108 : case AMDGPU::VGPR208_VGPR209: OpKind = MCK_VReg_64; break;
19109 : case AMDGPU::VGPR209_VGPR210: OpKind = MCK_VReg_64; break;
19110 : case AMDGPU::VGPR210_VGPR211: OpKind = MCK_VReg_64; break;
19111 : case AMDGPU::VGPR211_VGPR212: OpKind = MCK_VReg_64; break;
19112 : case AMDGPU::VGPR212_VGPR213: OpKind = MCK_VReg_64; break;
19113 : case AMDGPU::VGPR213_VGPR214: OpKind = MCK_VReg_64; break;
19114 : case AMDGPU::VGPR214_VGPR215: OpKind = MCK_VReg_64; break;
19115 : case AMDGPU::VGPR215_VGPR216: OpKind = MCK_VReg_64; break;
19116 : case AMDGPU::VGPR216_VGPR217: OpKind = MCK_VReg_64; break;
19117 : case AMDGPU::VGPR217_VGPR218: OpKind = MCK_VReg_64; break;
19118 : case AMDGPU::VGPR218_VGPR219: OpKind = MCK_VReg_64; break;
19119 : case AMDGPU::VGPR219_VGPR220: OpKind = MCK_VReg_64; break;
19120 : case AMDGPU::VGPR220_VGPR221: OpKind = MCK_VReg_64; break;
19121 : case AMDGPU::VGPR221_VGPR222: OpKind = MCK_VReg_64; break;
19122 : case AMDGPU::VGPR222_VGPR223: OpKind = MCK_VReg_64; break;
19123 : case AMDGPU::VGPR223_VGPR224: OpKind = MCK_VReg_64; break;
19124 : case AMDGPU::VGPR224_VGPR225: OpKind = MCK_VReg_64; break;
19125 : case AMDGPU::VGPR225_VGPR226: OpKind = MCK_VReg_64; break;
19126 : case AMDGPU::VGPR226_VGPR227: OpKind = MCK_VReg_64; break;
19127 : case AMDGPU::VGPR227_VGPR228: OpKind = MCK_VReg_64; break;
19128 : case AMDGPU::VGPR228_VGPR229: OpKind = MCK_VReg_64; break;
19129 : case AMDGPU::VGPR229_VGPR230: OpKind = MCK_VReg_64; break;
19130 : case AMDGPU::VGPR230_VGPR231: OpKind = MCK_VReg_64; break;
19131 : case AMDGPU::VGPR231_VGPR232: OpKind = MCK_VReg_64; break;
19132 : case AMDGPU::VGPR232_VGPR233: OpKind = MCK_VReg_64; break;
19133 : case AMDGPU::VGPR233_VGPR234: OpKind = MCK_VReg_64; break;
19134 : case AMDGPU::VGPR234_VGPR235: OpKind = MCK_VReg_64; break;
19135 : case AMDGPU::VGPR235_VGPR236: OpKind = MCK_VReg_64; break;
19136 : case AMDGPU::VGPR236_VGPR237: OpKind = MCK_VReg_64; break;
19137 : case AMDGPU::VGPR237_VGPR238: OpKind = MCK_VReg_64; break;
19138 : case AMDGPU::VGPR238_VGPR239: OpKind = MCK_VReg_64; break;
19139 : case AMDGPU::VGPR239_VGPR240: OpKind = MCK_VReg_64; break;
19140 : case AMDGPU::VGPR240_VGPR241: OpKind = MCK_VReg_64; break;
19141 : case AMDGPU::VGPR241_VGPR242: OpKind = MCK_VReg_64; break;
19142 : case AMDGPU::VGPR242_VGPR243: OpKind = MCK_VReg_64; break;
19143 : case AMDGPU::VGPR243_VGPR244: OpKind = MCK_VReg_64; break;
19144 : case AMDGPU::VGPR244_VGPR245: OpKind = MCK_VReg_64; break;
19145 : case AMDGPU::VGPR245_VGPR246: OpKind = MCK_VReg_64; break;
19146 : case AMDGPU::VGPR246_VGPR247: OpKind = MCK_VReg_64; break;
19147 : case AMDGPU::VGPR247_VGPR248: OpKind = MCK_VReg_64; break;
19148 : case AMDGPU::VGPR248_VGPR249: OpKind = MCK_VReg_64; break;
19149 : case AMDGPU::VGPR249_VGPR250: OpKind = MCK_VReg_64; break;
19150 : case AMDGPU::VGPR250_VGPR251: OpKind = MCK_VReg_64; break;
19151 : case AMDGPU::VGPR251_VGPR252: OpKind = MCK_VReg_64; break;
19152 : case AMDGPU::VGPR252_VGPR253: OpKind = MCK_VReg_64; break;
19153 : case AMDGPU::VGPR253_VGPR254: OpKind = MCK_VReg_64; break;
19154 : case AMDGPU::VGPR254_VGPR255: OpKind = MCK_VReg_64; break;
19155 : case AMDGPU::VGPR0_VGPR1_VGPR2: OpKind = MCK_VReg_96; break;
19156 : case AMDGPU::VGPR1_VGPR2_VGPR3: OpKind = MCK_VReg_96; break;
19157 : case AMDGPU::VGPR2_VGPR3_VGPR4: OpKind = MCK_VReg_96; break;
19158 : case AMDGPU::VGPR3_VGPR4_VGPR5: OpKind = MCK_VReg_96; break;
19159 : case AMDGPU::VGPR4_VGPR5_VGPR6: OpKind = MCK_VReg_96; break;
19160 : case AMDGPU::VGPR5_VGPR6_VGPR7: OpKind = MCK_VReg_96; break;
19161 : case AMDGPU::VGPR6_VGPR7_VGPR8: OpKind = MCK_VReg_96; break;
19162 : case AMDGPU::VGPR7_VGPR8_VGPR9: OpKind = MCK_VReg_96; break;
19163 : case AMDGPU::VGPR8_VGPR9_VGPR10: OpKind = MCK_VReg_96; break;
19164 : case AMDGPU::VGPR9_VGPR10_VGPR11: OpKind = MCK_VReg_96; break;
19165 : case AMDGPU::VGPR10_VGPR11_VGPR12: OpKind = MCK_VReg_96; break;
19166 : case AMDGPU::VGPR11_VGPR12_VGPR13: OpKind = MCK_VReg_96; break;
19167 : case AMDGPU::VGPR12_VGPR13_VGPR14: OpKind = MCK_VReg_96; break;
19168 : case AMDGPU::VGPR13_VGPR14_VGPR15: OpKind = MCK_VReg_96; break;
19169 : case AMDGPU::VGPR14_VGPR15_VGPR16: OpKind = MCK_VReg_96; break;
19170 : case AMDGPU::VGPR15_VGPR16_VGPR17: OpKind = MCK_VReg_96; break;
19171 : case AMDGPU::VGPR16_VGPR17_VGPR18: OpKind = MCK_VReg_96; break;
19172 : case AMDGPU::VGPR17_VGPR18_VGPR19: OpKind = MCK_VReg_96; break;
19173 : case AMDGPU::VGPR18_VGPR19_VGPR20: OpKind = MCK_VReg_96; break;
19174 : case AMDGPU::VGPR19_VGPR20_VGPR21: OpKind = MCK_VReg_96; break;
19175 : case AMDGPU::VGPR20_VGPR21_VGPR22: OpKind = MCK_VReg_96; break;
19176 : case AMDGPU::VGPR21_VGPR22_VGPR23: OpKind = MCK_VReg_96; break;
19177 : case AMDGPU::VGPR22_VGPR23_VGPR24: OpKind = MCK_VReg_96; break;
19178 : case AMDGPU::VGPR23_VGPR24_VGPR25: OpKind = MCK_VReg_96; break;
19179 : case AMDGPU::VGPR24_VGPR25_VGPR26: OpKind = MCK_VReg_96; break;
19180 : case AMDGPU::VGPR25_VGPR26_VGPR27: OpKind = MCK_VReg_96; break;
19181 : case AMDGPU::VGPR26_VGPR27_VGPR28: OpKind = MCK_VReg_96; break;
19182 : case AMDGPU::VGPR27_VGPR28_VGPR29: OpKind = MCK_VReg_96; break;
19183 : case AMDGPU::VGPR28_VGPR29_VGPR30: OpKind = MCK_VReg_96; break;
19184 : case AMDGPU::VGPR29_VGPR30_VGPR31: OpKind = MCK_VReg_96; break;
19185 : case AMDGPU::VGPR30_VGPR31_VGPR32: OpKind = MCK_VReg_96; break;
19186 : case AMDGPU::VGPR31_VGPR32_VGPR33: OpKind = MCK_VReg_96; break;
19187 : case AMDGPU::VGPR32_VGPR33_VGPR34: OpKind = MCK_VReg_96; break;
19188 : case AMDGPU::VGPR33_VGPR34_VGPR35: OpKind = MCK_VReg_96; break;
19189 : case AMDGPU::VGPR34_VGPR35_VGPR36: OpKind = MCK_VReg_96; break;
19190 : case AMDGPU::VGPR35_VGPR36_VGPR37: OpKind = MCK_VReg_96; break;
19191 : case AMDGPU::VGPR36_VGPR37_VGPR38: OpKind = MCK_VReg_96; break;
19192 : case AMDGPU::VGPR37_VGPR38_VGPR39: OpKind = MCK_VReg_96; break;
19193 : case AMDGPU::VGPR38_VGPR39_VGPR40: OpKind = MCK_VReg_96; break;
19194 : case AMDGPU::VGPR39_VGPR40_VGPR41: OpKind = MCK_VReg_96; break;
19195 : case AMDGPU::VGPR40_VGPR41_VGPR42: OpKind = MCK_VReg_96; break;
19196 : case AMDGPU::VGPR41_VGPR42_VGPR43: OpKind = MCK_VReg_96; break;
19197 : case AMDGPU::VGPR42_VGPR43_VGPR44: OpKind = MCK_VReg_96; break;
19198 : case AMDGPU::VGPR43_VGPR44_VGPR45: OpKind = MCK_VReg_96; break;
19199 : case AMDGPU::VGPR44_VGPR45_VGPR46: OpKind = MCK_VReg_96; break;
19200 : case AMDGPU::VGPR45_VGPR46_VGPR47: OpKind = MCK_VReg_96; break;
19201 : case AMDGPU::VGPR46_VGPR47_VGPR48: OpKind = MCK_VReg_96; break;
19202 : case AMDGPU::VGPR47_VGPR48_VGPR49: OpKind = MCK_VReg_96; break;
19203 : case AMDGPU::VGPR48_VGPR49_VGPR50: OpKind = MCK_VReg_96; break;
19204 : case AMDGPU::VGPR49_VGPR50_VGPR51: OpKind = MCK_VReg_96; break;
19205 : case AMDGPU::VGPR50_VGPR51_VGPR52: OpKind = MCK_VReg_96; break;
19206 : case AMDGPU::VGPR51_VGPR52_VGPR53: OpKind = MCK_VReg_96; break;
19207 : case AMDGPU::VGPR52_VGPR53_VGPR54: OpKind = MCK_VReg_96; break;
19208 : case AMDGPU::VGPR53_VGPR54_VGPR55: OpKind = MCK_VReg_96; break;
19209 : case AMDGPU::VGPR54_VGPR55_VGPR56: OpKind = MCK_VReg_96; break;
19210 : case AMDGPU::VGPR55_VGPR56_VGPR57: OpKind = MCK_VReg_96; break;
19211 : case AMDGPU::VGPR56_VGPR57_VGPR58: OpKind = MCK_VReg_96; break;
19212 : case AMDGPU::VGPR57_VGPR58_VGPR59: OpKind = MCK_VReg_96; break;
19213 : case AMDGPU::VGPR58_VGPR59_VGPR60: OpKind = MCK_VReg_96; break;
19214 : case AMDGPU::VGPR59_VGPR60_VGPR61: OpKind = MCK_VReg_96; break;
19215 : case AMDGPU::VGPR60_VGPR61_VGPR62: OpKind = MCK_VReg_96; break;
19216 : case AMDGPU::VGPR61_VGPR62_VGPR63: OpKind = MCK_VReg_96; break;
19217 : case AMDGPU::VGPR62_VGPR63_VGPR64: OpKind = MCK_VReg_96; break;
19218 : case AMDGPU::VGPR63_VGPR64_VGPR65: OpKind = MCK_VReg_96; break;
19219 : case AMDGPU::VGPR64_VGPR65_VGPR66: OpKind = MCK_VReg_96; break;
19220 : case AMDGPU::VGPR65_VGPR66_VGPR67: OpKind = MCK_VReg_96; break;
19221 : case AMDGPU::VGPR66_VGPR67_VGPR68: OpKind = MCK_VReg_96; break;
19222 : case AMDGPU::VGPR67_VGPR68_VGPR69: OpKind = MCK_VReg_96; break;
19223 : case AMDGPU::VGPR68_VGPR69_VGPR70: OpKind = MCK_VReg_96; break;
19224 : case AMDGPU::VGPR69_VGPR70_VGPR71: OpKind = MCK_VReg_96; break;
19225 : case AMDGPU::VGPR70_VGPR71_VGPR72: OpKind = MCK_VReg_96; break;
19226 : case AMDGPU::VGPR71_VGPR72_VGPR73: OpKind = MCK_VReg_96; break;
19227 : case AMDGPU::VGPR72_VGPR73_VGPR74: OpKind = MCK_VReg_96; break;
19228 : case AMDGPU::VGPR73_VGPR74_VGPR75: OpKind = MCK_VReg_96; break;
19229 : case AMDGPU::VGPR74_VGPR75_VGPR76: OpKind = MCK_VReg_96; break;
19230 : case AMDGPU::VGPR75_VGPR76_VGPR77: OpKind = MCK_VReg_96; break;
19231 : case AMDGPU::VGPR76_VGPR77_VGPR78: OpKind = MCK_VReg_96; break;
19232 : case AMDGPU::VGPR77_VGPR78_VGPR79: OpKind = MCK_VReg_96; break;
19233 : case AMDGPU::VGPR78_VGPR79_VGPR80: OpKind = MCK_VReg_96; break;
19234 : case AMDGPU::VGPR79_VGPR80_VGPR81: OpKind = MCK_VReg_96; break;
19235 : case AMDGPU::VGPR80_VGPR81_VGPR82: OpKind = MCK_VReg_96; break;
19236 : case AMDGPU::VGPR81_VGPR82_VGPR83: OpKind = MCK_VReg_96; break;
19237 : case AMDGPU::VGPR82_VGPR83_VGPR84: OpKind = MCK_VReg_96; break;
19238 : case AMDGPU::VGPR83_VGPR84_VGPR85: OpKind = MCK_VReg_96; break;
19239 : case AMDGPU::VGPR84_VGPR85_VGPR86: OpKind = MCK_VReg_96; break;
19240 : case AMDGPU::VGPR85_VGPR86_VGPR87: OpKind = MCK_VReg_96; break;
19241 : case AMDGPU::VGPR86_VGPR87_VGPR88: OpKind = MCK_VReg_96; break;
19242 : case AMDGPU::VGPR87_VGPR88_VGPR89: OpKind = MCK_VReg_96; break;
19243 : case AMDGPU::VGPR88_VGPR89_VGPR90: OpKind = MCK_VReg_96; break;
19244 : case AMDGPU::VGPR89_VGPR90_VGPR91: OpKind = MCK_VReg_96; break;
19245 : case AMDGPU::VGPR90_VGPR91_VGPR92: OpKind = MCK_VReg_96; break;
19246 : case AMDGPU::VGPR91_VGPR92_VGPR93: OpKind = MCK_VReg_96; break;
19247 : case AMDGPU::VGPR92_VGPR93_VGPR94: OpKind = MCK_VReg_96; break;
19248 : case AMDGPU::VGPR93_VGPR94_VGPR95: OpKind = MCK_VReg_96; break;
19249 : case AMDGPU::VGPR94_VGPR95_VGPR96: OpKind = MCK_VReg_96; break;
19250 : case AMDGPU::VGPR95_VGPR96_VGPR97: OpKind = MCK_VReg_96; break;
19251 : case AMDGPU::VGPR96_VGPR97_VGPR98: OpKind = MCK_VReg_96; break;
19252 : case AMDGPU::VGPR97_VGPR98_VGPR99: OpKind = MCK_VReg_96; break;
19253 : case AMDGPU::VGPR98_VGPR99_VGPR100: OpKind = MCK_VReg_96; break;
19254 : case AMDGPU::VGPR99_VGPR100_VGPR101: OpKind = MCK_VReg_96; break;
19255 : case AMDGPU::VGPR100_VGPR101_VGPR102: OpKind = MCK_VReg_96; break;
19256 : case AMDGPU::VGPR101_VGPR102_VGPR103: OpKind = MCK_VReg_96; break;
19257 : case AMDGPU::VGPR102_VGPR103_VGPR104: OpKind = MCK_VReg_96; break;
19258 : case AMDGPU::VGPR103_VGPR104_VGPR105: OpKind = MCK_VReg_96; break;
19259 : case AMDGPU::VGPR104_VGPR105_VGPR106: OpKind = MCK_VReg_96; break;
19260 : case AMDGPU::VGPR105_VGPR106_VGPR107: OpKind = MCK_VReg_96; break;
19261 : case AMDGPU::VGPR106_VGPR107_VGPR108: OpKind = MCK_VReg_96; break;
19262 : case AMDGPU::VGPR107_VGPR108_VGPR109: OpKind = MCK_VReg_96; break;
19263 : case AMDGPU::VGPR108_VGPR109_VGPR110: OpKind = MCK_VReg_96; break;
19264 : case AMDGPU::VGPR109_VGPR110_VGPR111: OpKind = MCK_VReg_96; break;
19265 : case AMDGPU::VGPR110_VGPR111_VGPR112: OpKind = MCK_VReg_96; break;
19266 : case AMDGPU::VGPR111_VGPR112_VGPR113: OpKind = MCK_VReg_96; break;
19267 : case AMDGPU::VGPR112_VGPR113_VGPR114: OpKind = MCK_VReg_96; break;
19268 : case AMDGPU::VGPR113_VGPR114_VGPR115: OpKind = MCK_VReg_96; break;
19269 : case AMDGPU::VGPR114_VGPR115_VGPR116: OpKind = MCK_VReg_96; break;
19270 : case AMDGPU::VGPR115_VGPR116_VGPR117: OpKind = MCK_VReg_96; break;
19271 : case AMDGPU::VGPR116_VGPR117_VGPR118: OpKind = MCK_VReg_96; break;
19272 : case AMDGPU::VGPR117_VGPR118_VGPR119: OpKind = MCK_VReg_96; break;
19273 : case AMDGPU::VGPR118_VGPR119_VGPR120: OpKind = MCK_VReg_96; break;
19274 : case AMDGPU::VGPR119_VGPR120_VGPR121: OpKind = MCK_VReg_96; break;
19275 : case AMDGPU::VGPR120_VGPR121_VGPR122: OpKind = MCK_VReg_96; break;
19276 : case AMDGPU::VGPR121_VGPR122_VGPR123: OpKind = MCK_VReg_96; break;
19277 : case AMDGPU::VGPR122_VGPR123_VGPR124: OpKind = MCK_VReg_96; break;
19278 : case AMDGPU::VGPR123_VGPR124_VGPR125: OpKind = MCK_VReg_96; break;
19279 : case AMDGPU::VGPR124_VGPR125_VGPR126: OpKind = MCK_VReg_96; break;
19280 : case AMDGPU::VGPR125_VGPR126_VGPR127: OpKind = MCK_VReg_96; break;
19281 : case AMDGPU::VGPR126_VGPR127_VGPR128: OpKind = MCK_VReg_96; break;
19282 : case AMDGPU::VGPR127_VGPR128_VGPR129: OpKind = MCK_VReg_96; break;
19283 : case AMDGPU::VGPR128_VGPR129_VGPR130: OpKind = MCK_VReg_96; break;
19284 : case AMDGPU::VGPR129_VGPR130_VGPR131: OpKind = MCK_VReg_96; break;
19285 : case AMDGPU::VGPR130_VGPR131_VGPR132: OpKind = MCK_VReg_96; break;
19286 : case AMDGPU::VGPR131_VGPR132_VGPR133: OpKind = MCK_VReg_96; break;
19287 : case AMDGPU::VGPR132_VGPR133_VGPR134: OpKind = MCK_VReg_96; break;
19288 : case AMDGPU::VGPR133_VGPR134_VGPR135: OpKind = MCK_VReg_96; break;
19289 : case AMDGPU::VGPR134_VGPR135_VGPR136: OpKind = MCK_VReg_96; break;
19290 : case AMDGPU::VGPR135_VGPR136_VGPR137: OpKind = MCK_VReg_96; break;
19291 : case AMDGPU::VGPR136_VGPR137_VGPR138: OpKind = MCK_VReg_96; break;
19292 : case AMDGPU::VGPR137_VGPR138_VGPR139: OpKind = MCK_VReg_96; break;
19293 : case AMDGPU::VGPR138_VGPR139_VGPR140: OpKind = MCK_VReg_96; break;
19294 : case AMDGPU::VGPR139_VGPR140_VGPR141: OpKind = MCK_VReg_96; break;
19295 : case AMDGPU::VGPR140_VGPR141_VGPR142: OpKind = MCK_VReg_96; break;
19296 : case AMDGPU::VGPR141_VGPR142_VGPR143: OpKind = MCK_VReg_96; break;
19297 : case AMDGPU::VGPR142_VGPR143_VGPR144: OpKind = MCK_VReg_96; break;
19298 : case AMDGPU::VGPR143_VGPR144_VGPR145: OpKind = MCK_VReg_96; break;
19299 : case AMDGPU::VGPR144_VGPR145_VGPR146: OpKind = MCK_VReg_96; break;
19300 : case AMDGPU::VGPR145_VGPR146_VGPR147: OpKind = MCK_VReg_96; break;
19301 : case AMDGPU::VGPR146_VGPR147_VGPR148: OpKind = MCK_VReg_96; break;
19302 : case AMDGPU::VGPR147_VGPR148_VGPR149: OpKind = MCK_VReg_96; break;
19303 : case AMDGPU::VGPR148_VGPR149_VGPR150: OpKind = MCK_VReg_96; break;
19304 : case AMDGPU::VGPR149_VGPR150_VGPR151: OpKind = MCK_VReg_96; break;
19305 : case AMDGPU::VGPR150_VGPR151_VGPR152: OpKind = MCK_VReg_96; break;
19306 : case AMDGPU::VGPR151_VGPR152_VGPR153: OpKind = MCK_VReg_96; break;
19307 : case AMDGPU::VGPR152_VGPR153_VGPR154: OpKind = MCK_VReg_96; break;
19308 : case AMDGPU::VGPR153_VGPR154_VGPR155: OpKind = MCK_VReg_96; break;
19309 : case AMDGPU::VGPR154_VGPR155_VGPR156: OpKind = MCK_VReg_96; break;
19310 : case AMDGPU::VGPR155_VGPR156_VGPR157: OpKind = MCK_VReg_96; break;
19311 : case AMDGPU::VGPR156_VGPR157_VGPR158: OpKind = MCK_VReg_96; break;
19312 : case AMDGPU::VGPR157_VGPR158_VGPR159: OpKind = MCK_VReg_96; break;
19313 : case AMDGPU::VGPR158_VGPR159_VGPR160: OpKind = MCK_VReg_96; break;
19314 : case AMDGPU::VGPR159_VGPR160_VGPR161: OpKind = MCK_VReg_96; break;
19315 : case AMDGPU::VGPR160_VGPR161_VGPR162: OpKind = MCK_VReg_96; break;
19316 : case AMDGPU::VGPR161_VGPR162_VGPR163: OpKind = MCK_VReg_96; break;
19317 : case AMDGPU::VGPR162_VGPR163_VGPR164: OpKind = MCK_VReg_96; break;
19318 : case AMDGPU::VGPR163_VGPR164_VGPR165: OpKind = MCK_VReg_96; break;
19319 : case AMDGPU::VGPR164_VGPR165_VGPR166: OpKind = MCK_VReg_96; break;
19320 : case AMDGPU::VGPR165_VGPR166_VGPR167: OpKind = MCK_VReg_96; break;
19321 : case AMDGPU::VGPR166_VGPR167_VGPR168: OpKind = MCK_VReg_96; break;
19322 : case AMDGPU::VGPR167_VGPR168_VGPR169: OpKind = MCK_VReg_96; break;
19323 : case AMDGPU::VGPR168_VGPR169_VGPR170: OpKind = MCK_VReg_96; break;
19324 : case AMDGPU::VGPR169_VGPR170_VGPR171: OpKind = MCK_VReg_96; break;
19325 : case AMDGPU::VGPR170_VGPR171_VGPR172: OpKind = MCK_VReg_96; break;
19326 : case AMDGPU::VGPR171_VGPR172_VGPR173: OpKind = MCK_VReg_96; break;
19327 : case AMDGPU::VGPR172_VGPR173_VGPR174: OpKind = MCK_VReg_96; break;
19328 : case AMDGPU::VGPR173_VGPR174_VGPR175: OpKind = MCK_VReg_96; break;
19329 : case AMDGPU::VGPR174_VGPR175_VGPR176: OpKind = MCK_VReg_96; break;
19330 : case AMDGPU::VGPR175_VGPR176_VGPR177: OpKind = MCK_VReg_96; break;
19331 : case AMDGPU::VGPR176_VGPR177_VGPR178: OpKind = MCK_VReg_96; break;
19332 : case AMDGPU::VGPR177_VGPR178_VGPR179: OpKind = MCK_VReg_96; break;
19333 : case AMDGPU::VGPR178_VGPR179_VGPR180: OpKind = MCK_VReg_96; break;
19334 : case AMDGPU::VGPR179_VGPR180_VGPR181: OpKind = MCK_VReg_96; break;
19335 : case AMDGPU::VGPR180_VGPR181_VGPR182: OpKind = MCK_VReg_96; break;
19336 : case AMDGPU::VGPR181_VGPR182_VGPR183: OpKind = MCK_VReg_96; break;
19337 : case AMDGPU::VGPR182_VGPR183_VGPR184: OpKind = MCK_VReg_96; break;
19338 : case AMDGPU::VGPR183_VGPR184_VGPR185: OpKind = MCK_VReg_96; break;
19339 : case AMDGPU::VGPR184_VGPR185_VGPR186: OpKind = MCK_VReg_96; break;
19340 : case AMDGPU::VGPR185_VGPR186_VGPR187: OpKind = MCK_VReg_96; break;
19341 : case AMDGPU::VGPR186_VGPR187_VGPR188: OpKind = MCK_VReg_96; break;
19342 : case AMDGPU::VGPR187_VGPR188_VGPR189: OpKind = MCK_VReg_96; break;
19343 : case AMDGPU::VGPR188_VGPR189_VGPR190: OpKind = MCK_VReg_96; break;
19344 : case AMDGPU::VGPR189_VGPR190_VGPR191: OpKind = MCK_VReg_96; break;
19345 : case AMDGPU::VGPR190_VGPR191_VGPR192: OpKind = MCK_VReg_96; break;
19346 : case AMDGPU::VGPR191_VGPR192_VGPR193: OpKind = MCK_VReg_96; break;
19347 : case AMDGPU::VGPR192_VGPR193_VGPR194: OpKind = MCK_VReg_96; break;
19348 : case AMDGPU::VGPR193_VGPR194_VGPR195: OpKind = MCK_VReg_96; break;
19349 : case AMDGPU::VGPR194_VGPR195_VGPR196: OpKind = MCK_VReg_96; break;
19350 : case AMDGPU::VGPR195_VGPR196_VGPR197: OpKind = MCK_VReg_96; break;
19351 : case AMDGPU::VGPR196_VGPR197_VGPR198: OpKind = MCK_VReg_96; break;
19352 : case AMDGPU::VGPR197_VGPR198_VGPR199: OpKind = MCK_VReg_96; break;
19353 : case AMDGPU::VGPR198_VGPR199_VGPR200: OpKind = MCK_VReg_96; break;
19354 : case AMDGPU::VGPR199_VGPR200_VGPR201: OpKind = MCK_VReg_96; break;
19355 : case AMDGPU::VGPR200_VGPR201_VGPR202: OpKind = MCK_VReg_96; break;
19356 : case AMDGPU::VGPR201_VGPR202_VGPR203: OpKind = MCK_VReg_96; break;
19357 : case AMDGPU::VGPR202_VGPR203_VGPR204: OpKind = MCK_VReg_96; break;
19358 : case AMDGPU::VGPR203_VGPR204_VGPR205: OpKind = MCK_VReg_96; break;
19359 : case AMDGPU::VGPR204_VGPR205_VGPR206: OpKind = MCK_VReg_96; break;
19360 : case AMDGPU::VGPR205_VGPR206_VGPR207: OpKind = MCK_VReg_96; break;
19361 : case AMDGPU::VGPR206_VGPR207_VGPR208: OpKind = MCK_VReg_96; break;
19362 : case AMDGPU::VGPR207_VGPR208_VGPR209: OpKind = MCK_VReg_96; break;
19363 : case AMDGPU::VGPR208_VGPR209_VGPR210: OpKind = MCK_VReg_96; break;
19364 : case AMDGPU::VGPR209_VGPR210_VGPR211: OpKind = MCK_VReg_96; break;
19365 : case AMDGPU::VGPR210_VGPR211_VGPR212: OpKind = MCK_VReg_96; break;
19366 : case AMDGPU::VGPR211_VGPR212_VGPR213: OpKind = MCK_VReg_96; break;
19367 : case AMDGPU::VGPR212_VGPR213_VGPR214: OpKind = MCK_VReg_96; break;
19368 : case AMDGPU::VGPR213_VGPR214_VGPR215: OpKind = MCK_VReg_96; break;
19369 : case AMDGPU::VGPR214_VGPR215_VGPR216: OpKind = MCK_VReg_96; break;
19370 : case AMDGPU::VGPR215_VGPR216_VGPR217: OpKind = MCK_VReg_96; break;
19371 : case AMDGPU::VGPR216_VGPR217_VGPR218: OpKind = MCK_VReg_96; break;
19372 : case AMDGPU::VGPR217_VGPR218_VGPR219: OpKind = MCK_VReg_96; break;
19373 : case AMDGPU::VGPR218_VGPR219_VGPR220: OpKind = MCK_VReg_96; break;
19374 : case AMDGPU::VGPR219_VGPR220_VGPR221: OpKind = MCK_VReg_96; break;
19375 : case AMDGPU::VGPR220_VGPR221_VGPR222: OpKind = MCK_VReg_96; break;
19376 : case AMDGPU::VGPR221_VGPR222_VGPR223: OpKind = MCK_VReg_96; break;
19377 : case AMDGPU::VGPR222_VGPR223_VGPR224: OpKind = MCK_VReg_96; break;
19378 : case AMDGPU::VGPR223_VGPR224_VGPR225: OpKind = MCK_VReg_96; break;
19379 : case AMDGPU::VGPR224_VGPR225_VGPR226: OpKind = MCK_VReg_96; break;
19380 : case AMDGPU::VGPR225_VGPR226_VGPR227: OpKind = MCK_VReg_96; break;
19381 : case AMDGPU::VGPR226_VGPR227_VGPR228: OpKind = MCK_VReg_96; break;
19382 : case AMDGPU::VGPR227_VGPR228_VGPR229: OpKind = MCK_VReg_96; break;
19383 : case AMDGPU::VGPR228_VGPR229_VGPR230: OpKind = MCK_VReg_96; break;
19384 : case AMDGPU::VGPR229_VGPR230_VGPR231: OpKind = MCK_VReg_96; break;
19385 : case AMDGPU::VGPR230_VGPR231_VGPR232: OpKind = MCK_VReg_96; break;
19386 : case AMDGPU::VGPR231_VGPR232_VGPR233: OpKind = MCK_VReg_96; break;
19387 : case AMDGPU::VGPR232_VGPR233_VGPR234: OpKind = MCK_VReg_96; break;
19388 : case AMDGPU::VGPR233_VGPR234_VGPR235: OpKind = MCK_VReg_96; break;
19389 : case AMDGPU::VGPR234_VGPR235_VGPR236: OpKind = MCK_VReg_96; break;
19390 : case AMDGPU::VGPR235_VGPR236_VGPR237: OpKind = MCK_VReg_96; break;
19391 : case AMDGPU::VGPR236_VGPR237_VGPR238: OpKind = MCK_VReg_96; break;
19392 : case AMDGPU::VGPR237_VGPR238_VGPR239: OpKind = MCK_VReg_96; break;
19393 : case AMDGPU::VGPR238_VGPR239_VGPR240: OpKind = MCK_VReg_96; break;
19394 : case AMDGPU::VGPR239_VGPR240_VGPR241: OpKind = MCK_VReg_96; break;
19395 : case AMDGPU::VGPR240_VGPR241_VGPR242: OpKind = MCK_VReg_96; break;
19396 : case AMDGPU::VGPR241_VGPR242_VGPR243: OpKind = MCK_VReg_96; break;
19397 : case AMDGPU::VGPR242_VGPR243_VGPR244: OpKind = MCK_VReg_96; break;
19398 : case AMDGPU::VGPR243_VGPR244_VGPR245: OpKind = MCK_VReg_96; break;
19399 : case AMDGPU::VGPR244_VGPR245_VGPR246: OpKind = MCK_VReg_96; break;
19400 : case AMDGPU::VGPR245_VGPR246_VGPR247: OpKind = MCK_VReg_96; break;
19401 : case AMDGPU::VGPR246_VGPR247_VGPR248: OpKind = MCK_VReg_96; break;
19402 : case AMDGPU::VGPR247_VGPR248_VGPR249: OpKind = MCK_VReg_96; break;
19403 : case AMDGPU::VGPR248_VGPR249_VGPR250: OpKind = MCK_VReg_96; break;
19404 : case AMDGPU::VGPR249_VGPR250_VGPR251: OpKind = MCK_VReg_96; break;
19405 : case AMDGPU::VGPR250_VGPR251_VGPR252: OpKind = MCK_VReg_96; break;
19406 : case AMDGPU::VGPR251_VGPR252_VGPR253: OpKind = MCK_VReg_96; break;
19407 : case AMDGPU::VGPR252_VGPR253_VGPR254: OpKind = MCK_VReg_96; break;
19408 : case AMDGPU::VGPR253_VGPR254_VGPR255: OpKind = MCK_VReg_96; break;
19409 : }
19410 7154 : return isSubclass(OpKind, Kind) ? MCTargetAsmParser::Match_Success :
19411 7154 : MCTargetAsmParser::Match_InvalidOperand;
19412 : }
19413 :
19414 : return MCTargetAsmParser::Match_InvalidOperand;
19415 : }
19416 :
19417 44 : uint64_t AMDGPUAsmParser::
19418 : ComputeAvailableFeatures(const FeatureBitset& FB) const {
19419 44 : uint64_t Features = 0;
19420 88 : if ((FB[AMDGPU::FeatureGCN1Encoding]))
19421 40 : Features |= Feature_isSICI;
19422 88 : if ((FB[AMDGPU::FeatureGCN3Encoding]))
19423 4 : Features |= Feature_isVI;
19424 88 : if ((FB[AMDGPU::FeatureDisable]))
19425 0 : Features |= Feature_DisableInst;
19426 88 : if ((FB[AMDGPU::FeatureGCN]))
19427 44 : Features |= Feature_isGCN;
19428 88 : if ((FB[AMDGPU::FeatureCIInsts]))
19429 8 : Features |= Feature_isCIVI;
19430 44 : return Features;
19431 : }
19432 :
19433 : static const char *const MnemonicTable =
19434 : "\007CALL_FS\006CF_END\010CONTINUE\004ELSE\010END_LOOP\013INTERP_LOAD\016"
19435 : "INTERP_PAIR_XY\016INTERP_PAIR_ZW\004JUMP\nLOOP_BREAK\017LOOP_START_DX10"
19436 : "\nMASK_WRITE\003PAD\003POP\004PUSH\tPUSH_ELSE\003TEX\003VTX\021buffer_a"
19437 : "tomic_add\021buffer_atomic_and\020buffer_atomic_or\022buffer_atomic_sma"
19438 : "x\022buffer_atomic_smin\021buffer_atomic_sub\022buffer_atomic_swap\022b"
19439 : "uffer_atomic_umax\022buffer_atomic_umin\021buffer_atomic_xor\021buffer_"
19440 : "load_dword\023buffer_load_dwordx2\023buffer_load_dwordx4\024buffer_load"
19441 : "_format_x\025buffer_load_format_xy\026buffer_load_format_xyz\027buffer_"
19442 : "load_format_xyzw\021buffer_load_sbyte\022buffer_load_sshort\021buffer_l"
19443 : "oad_ubyte\022buffer_load_ushort\021buffer_store_byte\022buffer_store_dw"
19444 : "ord\024buffer_store_dwordx2\024buffer_store_dwordx4\025buffer_store_for"
19445 : "mat_x\026buffer_store_format_xy\027buffer_store_format_xyz\030buffer_st"
19446 : "ore_format_xyzw\022buffer_store_short\016ds_add_rtn_u32\016ds_add_rtn_u"
19447 : "64\017ds_add_src2_u32\017ds_add_src2_u64\nds_add_u32\nds_add_u64\nds_an"
19448 : "d_b32\nds_and_b64\016ds_and_rtn_b32\016ds_and_rtn_b64\017ds_and_src2_b6"
19449 : "4\016ds_and_src_b32\tds_append\014ds_cmpst_b32\014ds_cmpst_b64\014ds_cm"
19450 : "pst_f32\014ds_cmpst_f64\020ds_cmpst_rtn_b32\020ds_cmpst_rtn_b64\020ds_c"
19451 : "mpst_rtn_f32\020ds_cmpst_rtn_f64\nds_consume\016ds_dec_rtn_u32\016ds_de"
19452 : "c_rtn_u64\017ds_dec_src2_u32\017ds_dec_src2_u64\nds_dec_u32\nds_dec_u64"
19453 : "\016ds_gws_barrier\013ds_gws_init\016ds_gws_sema_br\015ds_gws_sema_p\015"
19454 : "ds_gws_sema_v\016ds_inc_rtn_u32\016ds_inc_rtn_u64\017ds_inc_src2_u32\017"
19455 : "ds_inc_src2_u64\nds_inc_u32\nds_inc_u64\nds_max_f32\nds_max_f64\nds_max"
19456 : "_i32\nds_max_i64\016ds_max_rtn_f32\016ds_max_rtn_f64\016ds_max_rtn_i32\016"
19457 : "ds_max_rtn_i64\016ds_max_rtn_u32\016ds_max_rtn_u64\017ds_max_src2_f32\017"
19458 : "ds_max_src2_f64\017ds_max_src2_i32\017ds_max_src2_i64\017ds_max_src2_u3"
19459 : "2\017ds_max_src2_u64\nds_max_u32\nds_max_u64\nds_min_f32\nds_min_f64\nd"
19460 : "s_min_i32\nds_min_i64\016ds_min_rtn_f32\016ds_min_rtn_f64\016ds_min_rtn"
19461 : "_i32\016ds_min_rtn_i64\016ds_min_rtn_u32\016ds_min_rtn_u64\017ds_min_sr"
19462 : "c2_f32\017ds_min_src2_f64\017ds_min_src2_i32\017ds_min_src2_i64\017ds_m"
19463 : "in_src2_u32\017ds_min_src2_u64\nds_min_u32\nds_min_u64\014ds_mskor_b32\014"
19464 : "ds_mskor_b64\020ds_mskor_rtn_b32\020ds_mskor_rtn_b64\tds_or_b32\tds_or_"
19465 : "b64\015ds_or_rtn_b32\015ds_or_rtn_b64\016ds_or_src2_b32\016ds_or_src2_b"
19466 : "64\020ds_ordered_count\014ds_read2_b32\014ds_read2_b64\020ds_read2st64_"
19467 : "b32\020ds_read2st64_b64\013ds_read_b32\013ds_read_b64\013ds_read_i16\nd"
19468 : "s_read_i8\013ds_read_u16\nds_read_u8\017ds_rsub_rtn_u32\017ds_rsub_rtn_"
19469 : "u64\020ds_rsub_src2_u32\020ds_rsub_src2_u64\013ds_rsub_u32\013ds_rsub_u"
19470 : "64\016ds_sub_rtn_u32\016ds_sub_rtn_u64\017ds_sub_src2_u32\017ds_sub_src"
19471 : "2_u64\nds_sub_u32\nds_sub_u64\016ds_swizzle_b32\017ds_wrap_rtn_f32\015d"
19472 : "s_write2_b32\015ds_write2_b64\021ds_write2st64_b32\021ds_write2st64_b64"
19473 : "\014ds_write_b16\014ds_write_b32\014ds_write_b64\013ds_write_b8\021ds_w"
19474 : "rite_src2_b32\021ds_write_src2_b64\022ds_wrxchg2_rtn_b32\022ds_wrxchg2_"
19475 : "rtn_b64\026ds_wrxchg2st64_rtn_b32\026ds_wrxchg2st64_rtn_b64\021ds_wrxch"
19476 : "g_rtn_b32\021ds_wrxchg_rtn_b64\nds_xor_b32\nds_xor_b64\016ds_xor_rtn_b3"
19477 : "2\016ds_xor_rtn_b64\017ds_xor_src2_b32\017ds_xor_src2_b64\003exp\017fla"
19478 : "t_load_dword\021flat_load_dwordx2\021flat_load_dwordx3\021flat_load_dwo"
19479 : "rdx4\017flat_load_sbyte\020flat_load_sshort\017flat_load_ubyte\020flat_"
19480 : "load_ushort\017flat_store_byte\020flat_store_dword\022flat_store_dwordx"
19481 : "2\022flat_store_dwordx3\022flat_store_dwordx4\020flat_store_short\015im"
19482 : "age_gather4\017image_gather4_b\022image_gather4_b_cl\024image_gather4_b"
19483 : "_cl_o\021image_gather4_b_o\017image_gather4_c\021image_gather4_c_b\024i"
19484 : "mage_gather4_c_b_cl\026image_gather4_c_b_cl_o\023image_gather4_c_b_o\022"
19485 : "image_gather4_c_cl\024image_gather4_c_cl_o\021image_gather4_c_l\023imag"
19486 : "e_gather4_c_l_o\022image_gather4_c_lz\024image_gather4_c_lz_o\021image_"
19487 : "gather4_c_o\020image_gather4_cl\022image_gather4_cl_o\017image_gather4_"
19488 : "l\021image_gather4_l_o\020image_gather4_lz\022image_gather4_lz_o\017ima"
19489 : "ge_gather4_o\015image_get_lod\021image_get_resinfo\nimage_load\016image"
19490 : "_load_mip\014image_sample\016image_sample_b\021image_sample_b_cl\023ima"
19491 : "ge_sample_b_cl_o\020image_sample_b_o\016image_sample_c\020image_sample_"
19492 : "c_b\023image_sample_c_b_cl\025image_sample_c_b_cl_o\022image_sample_c_b"
19493 : "_o\021image_sample_c_cd\024image_sample_c_cd_cl\026image_sample_c_cd_cl"
19494 : "_o\023image_sample_c_cd_o\021image_sample_c_cl\023image_sample_c_cl_o\020"
19495 : "image_sample_c_d\023image_sample_c_d_cl\025image_sample_c_d_cl_o\022ima"
19496 : "ge_sample_c_d_o\020image_sample_c_l\022image_sample_c_l_o\021image_samp"
19497 : "le_c_lz\023image_sample_c_lz_o\020image_sample_c_o\017image_sample_cd\022"
19498 : "image_sample_cd_cl\024image_sample_cd_cl_o\021image_sample_cd_o\017imag"
19499 : "e_sample_cl\021image_sample_cl_o\016image_sample_d\021image_sample_d_cl"
19500 : "\023image_sample_d_cl_o\020image_sample_d_o\016image_sample_l\020image_"
19501 : "sample_l_o\017image_sample_lz\021image_sample_lz_o\016image_sample_o\ts"
19502 : "_abs_i32\015s_absdiff_i32\ts_add_i32\ts_add_u32\ns_addc_u32\ns_addk_i32"
19503 : "\ts_and_b32\ts_and_b64\022s_and_saveexec_b64\013s_andn2_b32\013s_andn2_"
19504 : "b64\024s_andn2_saveexec_b64\ns_ashr_i32\ns_ashr_i64\ts_barrier\017s_bcn"
19505 : "t0_i32_b32\017s_bcnt0_i32_b64\017s_bcnt1_i32_b32\017s_bcnt1_i32_b64\ts_"
19506 : "bfe_i32\ts_bfe_i64\ts_bfe_u32\ts_bfe_u64\ts_bfm_b32\ts_bfm_b64\015s_bit"
19507 : "set0_b32\015s_bitset0_b64\015s_bitset1_b32\015s_bitset1_b64\010s_branch"
19508 : "\ns_brev_b32\ns_brev_b64\023s_buffer_load_dword\026s_buffer_load_dwordx"
19509 : "16\025s_buffer_load_dwordx2\025s_buffer_load_dwordx4\025s_buffer_load_d"
19510 : "wordx8\020s_cbranch_execnz\017s_cbranch_execz\020s_cbranch_g_fork\020s_"
19511 : "cbranch_i_fork\016s_cbranch_join\016s_cbranch_scc0\016s_cbranch_scc1\017"
19512 : "s_cbranch_vccnz\016s_cbranch_vccz\ns_cmov_b32\ns_cmov_b64\013s_cmovk_i3"
19513 : "2\014s_cmp_eq_i32\014s_cmp_eq_u32\014s_cmp_ge_i32\014s_cmp_ge_u32\014s_"
19514 : "cmp_gt_i32\014s_cmp_gt_u32\014s_cmp_le_i32\014s_cmp_le_u32\014s_cmp_lg_"
19515 : "i32\014s_cmp_lg_u32\014s_cmp_lt_i32\014s_cmp_lt_u32\015s_cmpk_eq_i32\015"
19516 : "s_cmpk_eq_u32\015s_cmpk_ge_i32\015s_cmpk_ge_u32\015s_cmpk_gt_i32\015s_c"
19517 : "mpk_gt_u32\015s_cmpk_le_i32\015s_cmpk_le_u32\015s_cmpk_lg_i32\015s_cmpk"
19518 : "_lg_u32\015s_cmpk_lt_i32\015s_cmpk_lt_u32\015s_cselect_b32\015s_cselect"
19519 : "_b64\016s_decperflevel\010s_endpgm\015s_ff0_i32_b32\015s_ff0_i32_b64\015"
19520 : "s_ff1_i32_b32\015s_ff1_i32_b64\013s_flbit_i32\017s_flbit_i32_b32\017s_f"
19521 : "lbit_i32_b64\017s_flbit_i32_i64\013s_getpc_b64\014s_getreg_b32\014s_ica"
19522 : "che_inv\016s_incperflevel\014s_load_dword\017s_load_dwordx16\016s_load_"
19523 : "dwordx2\016s_load_dwordx4\016s_load_dwordx8\ns_lshl_b32\ns_lshl_b64\ns_"
19524 : "lshr_b32\ns_lshr_b64\ts_max_i32\ts_max_u32\ts_min_i32\ts_min_u32\ts_mov"
19525 : "_b32\ts_mov_b64\015s_mov_fed_b32\017s_mov_regrd_b32\ns_movk_i32\015s_mo"
19526 : "vreld_b32\015s_movreld_b64\015s_movrels_b32\015s_movrels_b64\ts_mul_i32"
19527 : "\ns_mulk_i32\ns_nand_b32\ns_nand_b64\023s_nand_saveexec_b64\005s_nop\ts"
19528 : "_nor_b32\ts_nor_b64\022s_nor_saveexec_b64\ts_not_b32\ts_not_b64\010s_or"
19529 : "_b32\010s_or_b64\021s_or_saveexec_b64\ns_orn2_b32\ns_orn2_b64\023s_orn2"
19530 : "_saveexec_b64\016s_quadmask_b32\016s_quadmask_b64\ts_rfe_b64\ts_sendmsg"
19531 : "\015s_sendmsghalt\ts_sethalt\013s_setpc_b64\ts_setprio\014s_setreg_b32\022"
19532 : "s_setreg_imm32_b32\016s_sext_i32_i16\015s_sext_i32_i8\007s_sleep\ts_sub"
19533 : "_i32\ts_sub_u32\ns_subb_u32\014s_swappc_b64\006s_trap\014s_ttracedata\t"
19534 : "s_waitcnt\ts_wqm_b32\ts_wqm_b64\ns_xnor_b32\ns_xnor_b64\023s_xnor_savee"
19535 : "xec_b64\ts_xor_b32\ts_xor_b64\022s_xor_saveexec_b64\030tbuffer_load_for"
19536 : "mat_xyzw\026tbuffer_store_format_x\027tbuffer_store_format_xy\030tbuffe"
19537 : "r_store_format_xyz\031tbuffer_store_format_xyzw\tv_add_f16\tv_add_f32\t"
19538 : "v_add_f64\tv_add_i32\tv_add_u16\nv_addc_u32\016v_alignbit_b32\017v_alig"
19539 : "nbyte_b32\tv_and_b32\nv_ashr_i32\nv_ashr_i64\015v_ashrrev_b16\015v_ashr"
19540 : "rev_i32\015v_ashrrev_i64\016v_bcnt_u32_b32\tv_bfe_i32\tv_bfe_u32\tv_bfi"
19541 : "_b32\tv_bfm_b32\013v_bfrev_b32\nv_ceil_f16\nv_ceil_f32\nv_ceil_f64\tv_c"
19542 : "lrexcp\017v_cmp_class_f32\017v_cmp_class_f64\014v_cmp_eq_f32\014v_cmp_e"
19543 : "q_f64\014v_cmp_eq_i32\014v_cmp_eq_i64\014v_cmp_eq_u32\014v_cmp_eq_u64\013"
19544 : "v_cmp_f_f32\013v_cmp_f_f64\013v_cmp_f_i32\013v_cmp_f_i64\013v_cmp_f_u32"
19545 : "\013v_cmp_f_u64\014v_cmp_ge_f32\014v_cmp_ge_f64\014v_cmp_ge_i32\014v_cm"
19546 : "p_ge_i64\014v_cmp_ge_u32\014v_cmp_ge_u64\014v_cmp_gt_f32\014v_cmp_gt_f6"
19547 : "4\014v_cmp_gt_i32\014v_cmp_gt_i64\014v_cmp_gt_u32\014v_cmp_gt_u64\014v_"
19548 : "cmp_le_f32\014v_cmp_le_f64\014v_cmp_le_i32\014v_cmp_le_i64\014v_cmp_le_"
19549 : "u32\014v_cmp_le_u64\014v_cmp_lg_f32\014v_cmp_lg_f64\014v_cmp_lt_f32\014"
19550 : "v_cmp_lt_f64\014v_cmp_lt_i32\014v_cmp_lt_i64\014v_cmp_lt_u32\014v_cmp_l"
19551 : "t_u64\014v_cmp_ne_i32\014v_cmp_ne_i64\014v_cmp_ne_u32\014v_cmp_ne_u64\015"
19552 : "v_cmp_neq_f32\015v_cmp_neq_f64\015v_cmp_nge_f32\015v_cmp_nge_f64\015v_c"
19553 : "mp_ngt_f32\015v_cmp_ngt_f64\015v_cmp_nle_f32\015v_cmp_nle_f64\015v_cmp_"
19554 : "nlg_f32\015v_cmp_nlg_f64\015v_cmp_nlt_f32\015v_cmp_nlt_f64\013v_cmp_o_f"
19555 : "32\013v_cmp_o_f64\013v_cmp_t_i32\013v_cmp_t_i64\013v_cmp_t_u32\013v_cmp"
19556 : "_t_u64\015v_cmp_tru_f32\015v_cmp_tru_f64\013v_cmp_u_f32\013v_cmp_u_f64\015"
19557 : "v_cmps_eq_f32\015v_cmps_eq_f64\014v_cmps_f_f32\014v_cmps_f_f64\015v_cmp"
19558 : "s_ge_f32\015v_cmps_ge_f64\015v_cmps_gt_f32\015v_cmps_gt_f64\015v_cmps_l"
19559 : "e_f32\015v_cmps_le_f64\015v_cmps_lg_f32\015v_cmps_lg_f64\015v_cmps_lt_f"
19560 : "32\015v_cmps_lt_f64\016v_cmps_neq_f32\016v_cmps_neq_f64\016v_cmps_nge_f"
19561 : "32\016v_cmps_nge_f64\016v_cmps_ngt_f32\016v_cmps_ngt_f64\016v_cmps_nle_"
19562 : "f32\016v_cmps_nle_f64\016v_cmps_nlg_f32\016v_cmps_nlg_f64\016v_cmps_nlt"
19563 : "_f32\016v_cmps_nlt_f64\014v_cmps_o_f32\014v_cmps_o_f64\016v_cmps_tru_f3"
19564 : "2\016v_cmps_tru_f64\014v_cmps_u_f32\014v_cmps_u_f64\016v_cmpsx_eq_f32\016"
19565 : "v_cmpsx_eq_f64\015v_cmpsx_f_f32\015v_cmpsx_f_f64\016v_cmpsx_ge_f32\016v"
19566 : "_cmpsx_ge_f64\016v_cmpsx_gt_f32\016v_cmpsx_gt_f64\016v_cmpsx_le_f32\016"
19567 : "v_cmpsx_le_f64\016v_cmpsx_lg_f32\016v_cmpsx_lg_f64\016v_cmpsx_lt_f32\016"
19568 : "v_cmpsx_lt_f64\017v_cmpsx_neq_f32\017v_cmpsx_neq_f64\017v_cmpsx_nge_f32"
19569 : "\017v_cmpsx_nge_f64\017v_cmpsx_ngt_f32\017v_cmpsx_ngt_f64\017v_cmpsx_nl"
19570 : "e_f32\017v_cmpsx_nle_f64\017v_cmpsx_nlg_f32\017v_cmpsx_nlg_f64\017v_cmp"
19571 : "sx_nlt_f32\017v_cmpsx_nlt_f64\015v_cmpsx_o_f32\015v_cmpsx_o_f64\017v_cm"
19572 : "psx_tru_f32\017v_cmpsx_tru_f64\015v_cmpsx_u_f32\015v_cmpsx_u_f64\020v_c"
19573 : "mpx_class_f32\020v_cmpx_class_f64\015v_cmpx_eq_f32\015v_cmpx_eq_f64\015"
19574 : "v_cmpx_eq_i32\015v_cmpx_eq_i64\015v_cmpx_eq_u32\015v_cmpx_eq_u64\014v_c"
19575 : "mpx_f_f32\014v_cmpx_f_f64\014v_cmpx_f_i32\014v_cmpx_f_i64\014v_cmpx_f_u"
19576 : "32\014v_cmpx_f_u64\015v_cmpx_ge_f32\015v_cmpx_ge_f64\015v_cmpx_ge_i32\015"
19577 : "v_cmpx_ge_i64\015v_cmpx_ge_u32\015v_cmpx_ge_u64\015v_cmpx_gt_f32\015v_c"
19578 : "mpx_gt_f64\015v_cmpx_gt_i32\015v_cmpx_gt_i64\015v_cmpx_gt_u32\015v_cmpx"
19579 : "_gt_u64\015v_cmpx_le_f32\015v_cmpx_le_f64\015v_cmpx_le_i32\015v_cmpx_le"
19580 : "_i64\015v_cmpx_le_u32\015v_cmpx_le_u64\015v_cmpx_lg_f32\015v_cmpx_lg_f6"
19581 : "4\015v_cmpx_lt_f32\015v_cmpx_lt_f64\015v_cmpx_lt_i32\015v_cmpx_lt_i64\015"
19582 : "v_cmpx_lt_u32\015v_cmpx_lt_u64\015v_cmpx_ne_i32\015v_cmpx_ne_i64\015v_c"
19583 : "mpx_ne_u32\015v_cmpx_ne_u64\016v_cmpx_neq_f32\016v_cmpx_neq_f64\016v_cm"
19584 : "px_nge_f32\016v_cmpx_nge_f64\016v_cmpx_ngt_f32\016v_cmpx_ngt_f64\016v_c"
19585 : "mpx_nle_f32\016v_cmpx_nle_f64\016v_cmpx_nlg_f32\016v_cmpx_nlg_f64\016v_"
19586 : "cmpx_nlt_f32\016v_cmpx_nlt_f64\014v_cmpx_o_f32\014v_cmpx_o_f64\014v_cmp"
19587 : "x_t_i32\014v_cmpx_t_i64\014v_cmpx_t_u32\014v_cmpx_t_u64\016v_cmpx_tru_f"
19588 : "32\016v_cmpx_tru_f64\014v_cmpx_u_f32\014v_cmpx_u_f64\015v_cndmask_b32\t"
19589 : "v_cos_f16\tv_cos_f32\014v_cubeid_f32\014v_cubema_f32\014v_cubesc_f32\014"
19590 : "v_cubetc_f32\015v_cvt_f16_f32\015v_cvt_f16_i16\015v_cvt_f16_u16\015v_cv"
19591 : "t_f32_f16\015v_cvt_f32_f64\015v_cvt_f32_i32\015v_cvt_f32_u32\020v_cvt_f"
19592 : "32_ubyte0\020v_cvt_f32_ubyte1\020v_cvt_f32_ubyte2\020v_cvt_f32_ubyte3\015"
19593 : "v_cvt_f64_f32\015v_cvt_f64_i32\015v_cvt_f64_u32\021v_cvt_flr_i32_f32\015"
19594 : "v_cvt_i16_f16\015v_cvt_i32_f32\015v_cvt_i32_f64\020v_cvt_off_f32_i4\020"
19595 : "v_cvt_pk_i16_i32\020v_cvt_pk_u16_u32\024v_cvt_pkaccum_u8_f32\024v_cvt_p"
19596 : "knorm_i16_f32\024v_cvt_pknorm_u16_f32\023v_cvt_pkrtz_f16_f32\021v_cvt_r"
19597 : "pi_i32_f32\015v_cvt_u16_f16\015v_cvt_u32_f32\015v_cvt_u32_f64\017v_div_"
19598 : "fixup_f32\017v_div_fixup_f64\016v_div_fmas_f32\016v_div_fmas_f64\017v_d"
19599 : "iv_scale_f32\017v_div_scale_f64\tv_exp_f16\tv_exp_f32\020v_exp_legacy_f"
19600 : "32\nv_ffbh_i32\nv_ffbh_u32\nv_ffbl_b32\013v_floor_f16\013v_floor_f32\013"
19601 : "v_floor_f64\tv_fma_f32\tv_fma_f64\013v_fract_f16\013v_fract_f32\013v_fr"
19602 : "act_f64\023v_frexp_exp_i16_f16\023v_frexp_exp_i32_f32\023v_frexp_exp_i3"
19603 : "2_f64\020v_frexp_mant_f16\020v_frexp_mant_f32\020v_frexp_mant_f64\020v_"
19604 : "interp_mov_f32\017v_interp_p1_f32\017v_interp_p2_f32\013v_ldexp_f16\013"
19605 : "v_ldexp_f32\013v_ldexp_f64\017v_log_clamp_f32\tv_log_f16\tv_log_f32\020"
19606 : "v_log_legacy_f32\nv_lshl_b32\nv_lshl_b64\015v_lshlrev_b16\015v_lshlrev_"
19607 : "b32\015v_lshlrev_b64\nv_lshr_b32\nv_lshr_b64\015v_lshrrev_b16\015v_lshr"
19608 : "rev_b32\015v_lshrrev_b64\tv_mac_f16\tv_mac_f32\020v_mac_legacy_f32\tv_m"
19609 : "ad_f32\015v_mad_i32_i24\015v_mad_i64_i32\020v_mad_legacy_f32\015v_mad_u"
19610 : "32_u24\015v_mad_u64_u32\013v_madak_f16\013v_madak_f32\013v_madmk_f16\013"
19611 : "v_madmk_f32\nv_max3_f32\nv_max3_i32\nv_max3_u32\tv_max_f16\tv_max_f32\t"
19612 : "v_max_f64\tv_max_i16\tv_max_i32\020v_max_legacy_f32\tv_max_u16\tv_max_u"
19613 : "32\022v_mbcnt_hi_u32_b32\022v_mbcnt_lo_u32_b32\nv_med3_f32\nv_med3_i32\n"
19614 : "v_med3_u32\nv_min3_f32\nv_min3_i32\nv_min3_u32\tv_min_f16\tv_min_f32\tv"
19615 : "_min_f64\tv_min_i16\tv_min_i32\020v_min_legacy_f32\tv_min_u16\tv_min_u3"
19616 : "2\tv_mov_b32\015v_mov_fed_b32\015v_movreld_b32\015v_movrels_b32\016v_mo"
19617 : "vrelsd_b32\016v_mqsad_u16_u8\016v_mqsad_u32_u8\tv_mul_f16\tv_mul_f32\tv"
19618 : "_mul_f64\014v_mul_hi_i32\020v_mul_hi_i32_i24\014v_mul_hi_u32\020v_mul_h"
19619 : "i_u32_u24\015v_mul_i32_i24\020v_mul_legacy_f32\014v_mul_lo_i32\014v_mul"
19620 : "_lo_u16\014v_mul_lo_u32\015v_mul_u32_u24\014v_mullit_f32\005v_nop\tv_no"
19621 : "t_b32\010v_or_b32\020v_qsad_pk_u16_u8\017v_rcp_clamp_f32\017v_rcp_clamp"
19622 : "_f64\tv_rcp_f16\tv_rcp_f32\tv_rcp_f64\017v_rcp_iflag_f32\020v_rcp_legac"
19623 : "y_f32\023v_readfirstlane_b32\016v_readlane_b32\013v_rndne_f16\013v_rndn"
19624 : "e_f32\013v_rndne_f64\017v_rsq_clamp_f32\017v_rsq_clamp_f64\tv_rsq_f16\t"
19625 : "v_rsq_f32\tv_rsq_f64\020v_rsq_legacy_f32\tv_sad_u32\tv_sin_f16\tv_sin_f"
19626 : "32\nv_sqrt_f16\nv_sqrt_f32\nv_sqrt_f64\tv_sub_f16\tv_sub_f32\tv_sub_i32"
19627 : "\tv_sub_u16\nv_subb_u32\015v_subbrev_u32\014v_subrev_f16\014v_subrev_f3"
19628 : "2\014v_subrev_i32\014v_subrev_u16\020v_trig_preop_f64\013v_trunc_f16\013"
19629 : "v_trunc_f32\013v_trunc_f64\017v_writelane_b32\tv_xor_b32";
19630 :
19631 : namespace {
19632 : struct MatchEntry {
19633 : uint16_t Mnemonic;
19634 : uint16_t Opcode;
19635 : uint16_t ConvertFn;
19636 : uint8_t RequiredFeatures;
19637 : uint8_t Classes[13];
19638 : StringRef getMnemonic() const {
19639 43604 : return StringRef(MnemonicTable + Mnemonic + 1,
19640 87208 : MnemonicTable[Mnemonic]);
19641 : }
19642 : };
19643 :
19644 : // Predicate for searching for an opcode.
19645 : struct LessOpcode {
19646 26948 : bool operator()(const MatchEntry &LHS, StringRef RHS) {
19647 53896 : return LHS.getMnemonic() < RHS;
19648 : }
19649 16656 : bool operator()(StringRef LHS, const MatchEntry &RHS) {
19650 33312 : return LHS < RHS.getMnemonic();
19651 : }
19652 : bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
19653 : return LHS.getMnemonic() < RHS.getMnemonic();
19654 : }
19655 : };
19656 : } // end anonymous namespace.
19657 :
19658 : static const MatchEntry MatchTable0[] = {
19659 : { 0 /* CALL_FS */, AMDGPU::CF_CALL_FS_EG, Convert_NoOperands, 0, { }, },
19660 : { 0 /* CALL_FS */, AMDGPU::CF_CALL_FS_R600, Convert_NoOperands, 0, { }, },
19661 : { 8 /* CF_END */, AMDGPU::CF_END_CM, Convert_NoOperands, 0, { }, },
19662 : { 8 /* CF_END */, AMDGPU::CF_END_EG, Convert_NoOperands, 0, { }, },
19663 : { 8 /* CF_END */, AMDGPU::CF_END_R600, Convert_NoOperands, 0, { }, },
19664 : { 15 /* CONTINUE */, AMDGPU::CF_CONTINUE_EG, Convert__Imm1_1, 0, { MCK__64_, MCK_Imm }, },
19665 : { 15 /* CONTINUE */, AMDGPU::CF_CONTINUE_R600, Convert__Imm1_1, 0, { MCK__64_, MCK_Imm }, },
19666 : { 24 /* ELSE */, AMDGPU::CF_ELSE_EG, Convert__Imm1_1__Imm1_3, 0, { MCK__64_, MCK_Imm, MCK_POP_COLON_, MCK_Imm }, },
19667 : { 24 /* ELSE */, AMDGPU::CF_ELSE_R600, Convert__Imm1_1__Imm1_3, 0, { MCK__64_, MCK_Imm, MCK_POP_COLON_, MCK_Imm }, },
19668 : { 29 /* END_LOOP */, AMDGPU::END_LOOP_EG, Convert__Imm1_1, 0, { MCK__64_, MCK_Imm }, },
19669 : { 29 /* END_LOOP */, AMDGPU::END_LOOP_R600, Convert__Imm1_1, 0, { MCK__64_, MCK_Imm }, },
19670 : { 38 /* INTERP_LOAD */, AMDGPU::INTERP_VEC_LOAD, Convert__Reg1_2__Imm1_0, 0, { MCK_Imm, MCK__COLON_, MCK_R600_Reg128 }, },
19671 : { 50 /* INTERP_PAIR_XY */, AMDGPU::INTERP_PAIR_XY, Convert__Reg1_4__imm_95_0__Imm1_0__Reg1_1__Reg1_2, 0, { MCK_Imm, MCK_R600_TReg32_Y, MCK_R600_TReg32_X, MCK__COLON_, MCK_R600_TReg32_X, MCK_dst1 }, },
19672 : { 65 /* INTERP_PAIR_ZW */, AMDGPU::INTERP_PAIR_ZW, Convert__Reg1_4__imm_95_0__Imm1_0__Reg1_1__Reg1_2, 0, { MCK_Imm, MCK_R600_TReg32_Y, MCK_R600_TReg32_X, MCK__COLON_, MCK_R600_TReg32_Z, MCK_dst1 }, },
19673 : { 80 /* JUMP */, AMDGPU::CF_JUMP_EG, Convert__Imm1_1__Imm1_3, 0, { MCK__64_, MCK_Imm, MCK_POP_COLON_, MCK_Imm }, },
19674 : { 80 /* JUMP */, AMDGPU::CF_JUMP_R600, Convert__Imm1_1__Imm1_3, 0, { MCK__64_, MCK_Imm, MCK_POP_COLON_, MCK_Imm }, },
19675 : { 85 /* LOOP_BREAK */, AMDGPU::LOOP_BREAK_EG, Convert__Imm1_1, 0, { MCK__64_, MCK_Imm }, },
19676 : { 85 /* LOOP_BREAK */, AMDGPU::LOOP_BREAK_R600, Convert__Imm1_1, 0, { MCK__64_, MCK_Imm }, },
19677 : { 96 /* LOOP_START_DX10 */, AMDGPU::WHILE_LOOP_EG, Convert__Imm1_1, 0, { MCK__64_, MCK_Imm }, },
19678 : { 96 /* LOOP_START_DX10 */, AMDGPU::WHILE_LOOP_R600, Convert__Imm1_1, 0, { MCK__64_, MCK_Imm }, },
19679 : { 112 /* MASK_WRITE */, AMDGPU::MASK_WRITE, Convert__Reg1_0, 0, { MCK_R600_Reg32 }, },
19680 : { 123 /* PAD */, AMDGPU::PAD, Convert_NoOperands, 0, { }, },
19681 : { 127 /* POP */, AMDGPU::POP_EG, Convert__Imm1_1__Imm1_3, 0, { MCK__64_, MCK_Imm, MCK_POP_COLON_, MCK_Imm }, },
19682 : { 127 /* POP */, AMDGPU::POP_R600, Convert__Imm1_1__Imm1_3, 0, { MCK__64_, MCK_Imm, MCK_POP_COLON_, MCK_Imm }, },
19683 : { 131 /* PUSH */, AMDGPU::CF_PUSH_EG, Convert__Imm1_1__Imm1_3, 0, { MCK__64_, MCK_Imm, MCK_POP_COLON_, MCK_Imm }, },
19684 : { 136 /* PUSH_ELSE */, AMDGPU::CF_PUSH_ELSE_R600, Convert__Imm1_1, 0, { MCK__64_, MCK_Imm }, },
19685 : { 146 /* TEX */, AMDGPU::CF_TC_EG, Convert__Imm1_2__Imm1_0, 0, { MCK_Imm, MCK__64_, MCK_Imm }, },
19686 : { 146 /* TEX */, AMDGPU::CF_TC_R600, Convert__Imm1_2__Imm1_0, 0, { MCK_Imm, MCK__64_, MCK_Imm }, },
19687 : { 150 /* VTX */, AMDGPU::CF_VC_EG, Convert__Imm1_2__Imm1_0, 0, { MCK_Imm, MCK__64_, MCK_Imm }, },
19688 : { 150 /* VTX */, AMDGPU::CF_VC_R600, Convert__Imm1_2__Imm1_0, 0, { MCK_Imm, MCK__64_, MCK_Imm }, },
19689 : { 154 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_SLC }, },
19690 : { 154 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_SLC }, },
19691 : { 154 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_RTN_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_glc, MCK_SLC }, },
19692 : { 154 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_RTN_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_glc, MCK_SLC }, },
19693 : { 154 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_SLC }, },
19694 : { 154 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_RTN_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_glc, MCK_SLC }, },
19695 : { 172 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_SLC }, },
19696 : { 172 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_SLC }, },
19697 : { 172 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_RTN_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_glc, MCK_SLC }, },
19698 : { 172 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_RTN_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_glc, MCK_SLC }, },
19699 : { 172 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_SLC }, },
19700 : { 172 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_RTN_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_glc, MCK_SLC }, },
19701 : { 190 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_SLC }, },
19702 : { 190 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_SLC }, },
19703 : { 190 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_RTN_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_glc, MCK_SLC }, },
19704 : { 190 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_RTN_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_glc, MCK_SLC }, },
19705 : { 190 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_SLC }, },
19706 : { 190 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_RTN_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_glc, MCK_SLC }, },
19707 : { 207 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_SLC }, },
19708 : { 207 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_SLC }, },
19709 : { 207 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_RTN_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_glc, MCK_SLC }, },
19710 : { 207 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_RTN_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_glc, MCK_SLC }, },
19711 : { 207 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_SLC }, },
19712 : { 207 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_RTN_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_glc, MCK_SLC }, },
19713 : { 226 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_SLC }, },
19714 : { 226 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_SLC }, },
19715 : { 226 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_RTN_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_glc, MCK_SLC }, },
19716 : { 226 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_RTN_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_glc, MCK_SLC }, },
19717 : { 226 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_SLC }, },
19718 : { 226 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_RTN_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_glc, MCK_SLC }, },
19719 : { 245 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_SLC }, },
19720 : { 245 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_SLC }, },
19721 : { 245 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_RTN_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_glc, MCK_SLC }, },
19722 : { 245 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_RTN_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_glc, MCK_SLC }, },
19723 : { 245 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_SLC }, },
19724 : { 245 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_RTN_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_glc, MCK_SLC }, },
19725 : { 263 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_SLC }, },
19726 : { 263 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_SLC }, },
19727 : { 263 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_RTN_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_glc, MCK_SLC }, },
19728 : { 263 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_RTN_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_glc, MCK_SLC }, },
19729 : { 263 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_SLC }, },
19730 : { 263 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_RTN_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_glc, MCK_SLC }, },
19731 : { 282 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_SLC }, },
19732 : { 282 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_SLC }, },
19733 : { 282 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_RTN_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_glc, MCK_SLC }, },
19734 : { 282 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_RTN_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_glc, MCK_SLC }, },
19735 : { 282 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_SLC }, },
19736 : { 282 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_RTN_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_glc, MCK_SLC }, },
19737 : { 301 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_SLC }, },
19738 : { 301 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_SLC }, },
19739 : { 301 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_RTN_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_glc, MCK_SLC }, },
19740 : { 301 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_RTN_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_glc, MCK_SLC }, },
19741 : { 301 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_SLC }, },
19742 : { 301 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_RTN_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_glc, MCK_SLC }, },
19743 : { 320 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_SLC }, },
19744 : { 320 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_SLC }, },
19745 : { 320 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_RTN_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_glc, MCK_SLC }, },
19746 : { 320 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_RTN_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_glc, MCK_SLC }, },
19747 : { 320 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_SLC }, },
19748 : { 320 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_RTN_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_glc, MCK_SLC }, },
19749 : { 338 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19750 : { 338 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19751 : { 338 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19752 : { 338 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19753 : { 338 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19754 : { 338 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19755 : { 338 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19756 : { 338 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19757 : { 338 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19758 : { 356 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19759 : { 356 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19760 : { 356 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19761 : { 356 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19762 : { 356 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19763 : { 356 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19764 : { 356 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19765 : { 356 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19766 : { 356 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19767 : { 376 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19768 : { 376 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19769 : { 376 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19770 : { 376 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19771 : { 376 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19772 : { 376 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19773 : { 376 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19774 : { 376 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19775 : { 376 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19776 : { 396 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19777 : { 396 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19778 : { 396 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19779 : { 396 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19780 : { 396 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19781 : { 396 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19782 : { 396 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19783 : { 396 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19784 : { 396 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19785 : { 417 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19786 : { 417 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19787 : { 417 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19788 : { 417 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19789 : { 417 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19790 : { 417 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19791 : { 417 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19792 : { 417 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19793 : { 417 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19794 : { 439 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_96, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19795 : { 439 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_96, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19796 : { 439 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19797 : { 439 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19798 : { 439 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19799 : { 439 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19800 : { 439 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19801 : { 439 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19802 : { 439 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19803 : { 462 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19804 : { 462 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19805 : { 462 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19806 : { 462 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19807 : { 462 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19808 : { 462 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19809 : { 462 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19810 : { 462 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19811 : { 462 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19812 : { 486 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19813 : { 486 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19814 : { 486 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19815 : { 486 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19816 : { 486 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19817 : { 486 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19818 : { 486 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19819 : { 486 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19820 : { 486 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19821 : { 504 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19822 : { 504 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19823 : { 504 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19824 : { 504 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19825 : { 504 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19826 : { 504 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19827 : { 504 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19828 : { 504 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19829 : { 504 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19830 : { 523 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19831 : { 523 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19832 : { 523 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19833 : { 523 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19834 : { 523 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19835 : { 523 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19836 : { 523 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19837 : { 523 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19838 : { 523 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19839 : { 541 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19840 : { 541 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19841 : { 541 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19842 : { 541 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19843 : { 541 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19844 : { 541 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19845 : { 541 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19846 : { 541 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19847 : { 541 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19848 : { 560 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19849 : { 560 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19850 : { 560 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19851 : { 560 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19852 : { 560 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19853 : { 560 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19854 : { 560 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19855 : { 560 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTEanonymous_768_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_Imm, MCK_Imm, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19856 : { 560 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTEanonymous_768_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_Imm, MCK_Imm, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19857 : { 560 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19858 : { 560 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19859 : { 578 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19860 : { 578 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19861 : { 578 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19862 : { 578 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19863 : { 578 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19864 : { 578 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19865 : { 578 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19866 : { 578 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORDanonymous_768_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_Imm, MCK_Imm, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19867 : { 578 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORDanonymous_768_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_Imm, MCK_Imm, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19868 : { 578 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19869 : { 578 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19870 : { 597 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19871 : { 597 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19872 : { 597 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19873 : { 597 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19874 : { 597 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19875 : { 597 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19876 : { 597 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19877 : { 597 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2anonymous_768_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_Imm, MCK_Imm, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19878 : { 597 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2anonymous_768_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_Imm, MCK_Imm, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19879 : { 597 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19880 : { 597 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19881 : { 618 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19882 : { 618 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19883 : { 618 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19884 : { 618 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19885 : { 618 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19886 : { 618 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19887 : { 618 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19888 : { 618 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4anonymous_768_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_Imm, MCK_Imm, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19889 : { 618 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4anonymous_768_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_Imm, MCK_Imm, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19890 : { 618 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19891 : { 618 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19892 : { 639 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19893 : { 639 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19894 : { 639 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19895 : { 639 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19896 : { 639 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19897 : { 639 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19898 : { 639 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19899 : { 639 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_Xanonymous_768_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_Imm, MCK_Imm, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19900 : { 639 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_Xanonymous_768_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_Imm, MCK_Imm, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19901 : { 639 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19902 : { 639 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19903 : { 661 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19904 : { 661 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19905 : { 661 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19906 : { 661 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19907 : { 661 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19908 : { 661 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19909 : { 661 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19910 : { 661 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XYanonymous_768_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_Imm, MCK_Imm, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19911 : { 661 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XYanonymous_768_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_Imm, MCK_Imm, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19912 : { 661 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19913 : { 661 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19914 : { 684 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_96, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19915 : { 684 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_96, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19916 : { 684 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19917 : { 684 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19918 : { 684 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19919 : { 684 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19920 : { 684 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19921 : { 684 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZanonymous_768_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_Imm, MCK_Imm, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19922 : { 684 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZanonymous_768_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_Imm, MCK_Imm, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19923 : { 684 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19924 : { 684 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19925 : { 708 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19926 : { 708 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19927 : { 708 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19928 : { 708 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19929 : { 708 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19930 : { 708 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19931 : { 708 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19932 : { 708 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZWanonymous_768_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_Imm, MCK_Imm, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19933 : { 708 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZWanonymous_768_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_Imm, MCK_Imm, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19934 : { 708 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19935 : { 708 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19936 : { 733 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19937 : { 733 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19938 : { 733 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19939 : { 733 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19940 : { 733 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19941 : { 733 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19942 : { 733 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_addr64, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19943 : { 733 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORTanonymous_768_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_Imm, MCK_Imm, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19944 : { 733 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORTanonymous_768_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrc32, MCK_Imm, MCK_Imm, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19945 : { 733 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19946 : { 733 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrc32, MCK_idxen, MCK_offen, MCK_MubufOffset, MCK_GLC, MCK_SLC, MCK_TFE }, },
19947 : { 752 /* ds_add_rtn_u32 */, AMDGPU::DS_ADD_RTN_U32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19948 : { 752 /* ds_add_rtn_u32 */, AMDGPU::DS_ADD_RTN_U32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19949 : { 767 /* ds_add_rtn_u64 */, AMDGPU::DS_ADD_RTN_U64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19950 : { 767 /* ds_add_rtn_u64 */, AMDGPU::DS_ADD_RTN_U64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19951 : { 782 /* ds_add_src2_u32 */, AMDGPU::DS_ADD_SRC2_U32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19952 : { 782 /* ds_add_src2_u32 */, AMDGPU::DS_ADD_SRC2_U32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19953 : { 798 /* ds_add_src2_u64 */, AMDGPU::DS_ADD_SRC2_U64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19954 : { 798 /* ds_add_src2_u64 */, AMDGPU::DS_ADD_SRC2_U64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19955 : { 814 /* ds_add_u32 */, AMDGPU::DS_ADD_U32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19956 : { 814 /* ds_add_u32 */, AMDGPU::DS_ADD_U32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19957 : { 825 /* ds_add_u64 */, AMDGPU::DS_ADD_U64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19958 : { 825 /* ds_add_u64 */, AMDGPU::DS_ADD_U64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19959 : { 836 /* ds_and_b32 */, AMDGPU::DS_AND_B32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19960 : { 836 /* ds_and_b32 */, AMDGPU::DS_AND_B32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19961 : { 847 /* ds_and_b64 */, AMDGPU::DS_AND_B64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19962 : { 847 /* ds_and_b64 */, AMDGPU::DS_AND_B64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19963 : { 858 /* ds_and_rtn_b32 */, AMDGPU::DS_AND_RTN_B32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19964 : { 858 /* ds_and_rtn_b32 */, AMDGPU::DS_AND_RTN_B32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19965 : { 873 /* ds_and_rtn_b64 */, AMDGPU::DS_AND_RTN_B64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19966 : { 873 /* ds_and_rtn_b64 */, AMDGPU::DS_AND_RTN_B64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19967 : { 888 /* ds_and_src2_b64 */, AMDGPU::DS_AND_SRC2_B64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19968 : { 888 /* ds_and_src2_b64 */, AMDGPU::DS_AND_SRC2_B64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19969 : { 904 /* ds_and_src_b32 */, AMDGPU::DS_AND_SRC2_B32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19970 : { 904 /* ds_and_src_b32 */, AMDGPU::DS_AND_SRC2_B32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19971 : { 919 /* ds_append */, AMDGPU::DS_APPEND_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19972 : { 919 /* ds_append */, AMDGPU::DS_APPEND_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19973 : { 929 /* ds_cmpst_b32 */, AMDGPU::DS_CMPST_B32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19974 : { 929 /* ds_cmpst_b32 */, AMDGPU::DS_CMPST_B32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19975 : { 942 /* ds_cmpst_b64 */, AMDGPU::DS_CMPST_B64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19976 : { 942 /* ds_cmpst_b64 */, AMDGPU::DS_CMPST_B64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19977 : { 955 /* ds_cmpst_f32 */, AMDGPU::DS_CMPST_F32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19978 : { 955 /* ds_cmpst_f32 */, AMDGPU::DS_CMPST_F32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19979 : { 968 /* ds_cmpst_f64 */, AMDGPU::DS_CMPST_F64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19980 : { 968 /* ds_cmpst_f64 */, AMDGPU::DS_CMPST_F64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19981 : { 981 /* ds_cmpst_rtn_b32 */, AMDGPU::DS_CMPST_RTN_B32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19982 : { 981 /* ds_cmpst_rtn_b32 */, AMDGPU::DS_CMPST_RTN_B32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19983 : { 998 /* ds_cmpst_rtn_b64 */, AMDGPU::DS_CMPST_RTN_B64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19984 : { 998 /* ds_cmpst_rtn_b64 */, AMDGPU::DS_CMPST_RTN_B64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19985 : { 1015 /* ds_cmpst_rtn_f32 */, AMDGPU::DS_CMPST_RTN_F32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19986 : { 1015 /* ds_cmpst_rtn_f32 */, AMDGPU::DS_CMPST_RTN_F32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19987 : { 1032 /* ds_cmpst_rtn_f64 */, AMDGPU::DS_CMPST_RTN_F64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19988 : { 1032 /* ds_cmpst_rtn_f64 */, AMDGPU::DS_CMPST_RTN_F64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19989 : { 1049 /* ds_consume */, AMDGPU::DS_CONSUME_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19990 : { 1049 /* ds_consume */, AMDGPU::DS_CONSUME_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19991 : { 1060 /* ds_dec_rtn_u32 */, AMDGPU::DS_DEC_RTN_U32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19992 : { 1060 /* ds_dec_rtn_u32 */, AMDGPU::DS_DEC_RTN_U32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19993 : { 1075 /* ds_dec_rtn_u64 */, AMDGPU::DS_DEC_RTN_U64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19994 : { 1075 /* ds_dec_rtn_u64 */, AMDGPU::DS_DEC_RTN_U64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19995 : { 1090 /* ds_dec_src2_u32 */, AMDGPU::DS_DEC_SRC2_U32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19996 : { 1090 /* ds_dec_src2_u32 */, AMDGPU::DS_DEC_SRC2_U32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19997 : { 1106 /* ds_dec_src2_u64 */, AMDGPU::DS_DEC_SRC2_U64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19998 : { 1106 /* ds_dec_src2_u64 */, AMDGPU::DS_DEC_SRC2_U64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
19999 : { 1122 /* ds_dec_u32 */, AMDGPU::DS_DEC_U32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20000 : { 1122 /* ds_dec_u32 */, AMDGPU::DS_DEC_U32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20001 : { 1133 /* ds_dec_u64 */, AMDGPU::DS_DEC_U64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20002 : { 1133 /* ds_dec_u64 */, AMDGPU::DS_DEC_U64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20003 : { 1144 /* ds_gws_barrier */, AMDGPU::DS_GWS_BARRIER_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_gds }, },
20004 : { 1144 /* ds_gws_barrier */, AMDGPU::DS_GWS_BARRIER_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_gds }, },
20005 : { 1159 /* ds_gws_init */, AMDGPU::DS_GWS_INIT_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_gds }, },
20006 : { 1159 /* ds_gws_init */, AMDGPU::DS_GWS_INIT_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_gds }, },
20007 : { 1171 /* ds_gws_sema_br */, AMDGPU::DS_GWS_SEMA_BR_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_gds }, },
20008 : { 1171 /* ds_gws_sema_br */, AMDGPU::DS_GWS_SEMA_BR_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_gds }, },
20009 : { 1186 /* ds_gws_sema_p */, AMDGPU::DS_GWS_SEMA_P_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_gds }, },
20010 : { 1186 /* ds_gws_sema_p */, AMDGPU::DS_GWS_SEMA_P_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_gds }, },
20011 : { 1200 /* ds_gws_sema_v */, AMDGPU::DS_GWS_SEMA_V_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_gds }, },
20012 : { 1200 /* ds_gws_sema_v */, AMDGPU::DS_GWS_SEMA_V_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_gds }, },
20013 : { 1214 /* ds_inc_rtn_u32 */, AMDGPU::DS_INC_RTN_U32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20014 : { 1214 /* ds_inc_rtn_u32 */, AMDGPU::DS_INC_RTN_U32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20015 : { 1229 /* ds_inc_rtn_u64 */, AMDGPU::DS_INC_RTN_U64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20016 : { 1229 /* ds_inc_rtn_u64 */, AMDGPU::DS_INC_RTN_U64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20017 : { 1244 /* ds_inc_src2_u32 */, AMDGPU::DS_INC_SRC2_U32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20018 : { 1244 /* ds_inc_src2_u32 */, AMDGPU::DS_INC_SRC2_U32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20019 : { 1260 /* ds_inc_src2_u64 */, AMDGPU::DS_INC_SRC2_U64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20020 : { 1260 /* ds_inc_src2_u64 */, AMDGPU::DS_INC_SRC2_U64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20021 : { 1276 /* ds_inc_u32 */, AMDGPU::DS_INC_U32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20022 : { 1276 /* ds_inc_u32 */, AMDGPU::DS_INC_U32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20023 : { 1287 /* ds_inc_u64 */, AMDGPU::DS_INC_U64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20024 : { 1287 /* ds_inc_u64 */, AMDGPU::DS_INC_U64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20025 : { 1298 /* ds_max_f32 */, AMDGPU::DS_MAX_F32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20026 : { 1298 /* ds_max_f32 */, AMDGPU::DS_MAX_F32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20027 : { 1309 /* ds_max_f64 */, AMDGPU::DS_MAX_F64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20028 : { 1309 /* ds_max_f64 */, AMDGPU::DS_MAX_F64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20029 : { 1320 /* ds_max_i32 */, AMDGPU::DS_MAX_I32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20030 : { 1320 /* ds_max_i32 */, AMDGPU::DS_MAX_I32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20031 : { 1331 /* ds_max_i64 */, AMDGPU::DS_MAX_I64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20032 : { 1331 /* ds_max_i64 */, AMDGPU::DS_MAX_I64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20033 : { 1342 /* ds_max_rtn_f32 */, AMDGPU::DS_MAX_RTN_F32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20034 : { 1342 /* ds_max_rtn_f32 */, AMDGPU::DS_MAX_RTN_F32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20035 : { 1357 /* ds_max_rtn_f64 */, AMDGPU::DS_MAX_RTN_F64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20036 : { 1357 /* ds_max_rtn_f64 */, AMDGPU::DS_MAX_RTN_F64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20037 : { 1372 /* ds_max_rtn_i32 */, AMDGPU::DS_MAX_RTN_I32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20038 : { 1372 /* ds_max_rtn_i32 */, AMDGPU::DS_MAX_RTN_I32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20039 : { 1387 /* ds_max_rtn_i64 */, AMDGPU::DS_MAX_RTN_I64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20040 : { 1387 /* ds_max_rtn_i64 */, AMDGPU::DS_MAX_RTN_I64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20041 : { 1402 /* ds_max_rtn_u32 */, AMDGPU::DS_MAX_RTN_U32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20042 : { 1402 /* ds_max_rtn_u32 */, AMDGPU::DS_MAX_RTN_U32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20043 : { 1417 /* ds_max_rtn_u64 */, AMDGPU::DS_MAX_RTN_U64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20044 : { 1417 /* ds_max_rtn_u64 */, AMDGPU::DS_MAX_RTN_U64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20045 : { 1432 /* ds_max_src2_f32 */, AMDGPU::DS_MAX_SRC2_F32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20046 : { 1432 /* ds_max_src2_f32 */, AMDGPU::DS_MAX_SRC2_F32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20047 : { 1448 /* ds_max_src2_f64 */, AMDGPU::DS_MAX_SRC2_F64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20048 : { 1448 /* ds_max_src2_f64 */, AMDGPU::DS_MAX_SRC2_F64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20049 : { 1464 /* ds_max_src2_i32 */, AMDGPU::DS_MAX_SRC2_I32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20050 : { 1464 /* ds_max_src2_i32 */, AMDGPU::DS_MAX_SRC2_I32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20051 : { 1480 /* ds_max_src2_i64 */, AMDGPU::DS_MAX_SRC2_I64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20052 : { 1480 /* ds_max_src2_i64 */, AMDGPU::DS_MAX_SRC2_I64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20053 : { 1496 /* ds_max_src2_u32 */, AMDGPU::DS_MAX_SRC2_U32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20054 : { 1496 /* ds_max_src2_u32 */, AMDGPU::DS_MAX_SRC2_U32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20055 : { 1512 /* ds_max_src2_u64 */, AMDGPU::DS_MAX_SRC2_U64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20056 : { 1512 /* ds_max_src2_u64 */, AMDGPU::DS_MAX_SRC2_U64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20057 : { 1528 /* ds_max_u32 */, AMDGPU::DS_MAX_U32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20058 : { 1528 /* ds_max_u32 */, AMDGPU::DS_MAX_U32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20059 : { 1539 /* ds_max_u64 */, AMDGPU::DS_MAX_U64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20060 : { 1539 /* ds_max_u64 */, AMDGPU::DS_MAX_U64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20061 : { 1550 /* ds_min_f32 */, AMDGPU::DS_MIN_F32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20062 : { 1550 /* ds_min_f32 */, AMDGPU::DS_MIN_F32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20063 : { 1561 /* ds_min_f64 */, AMDGPU::DS_MIN_F64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20064 : { 1561 /* ds_min_f64 */, AMDGPU::DS_MIN_F64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20065 : { 1572 /* ds_min_i32 */, AMDGPU::DS_MIN_I32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20066 : { 1572 /* ds_min_i32 */, AMDGPU::DS_MIN_I32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20067 : { 1583 /* ds_min_i64 */, AMDGPU::DS_MIN_I64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20068 : { 1583 /* ds_min_i64 */, AMDGPU::DS_MIN_I64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20069 : { 1594 /* ds_min_rtn_f32 */, AMDGPU::DS_MIN_RTN_F32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20070 : { 1594 /* ds_min_rtn_f32 */, AMDGPU::DS_MIN_RTN_F32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20071 : { 1609 /* ds_min_rtn_f64 */, AMDGPU::DS_MIN_RTN_F64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20072 : { 1609 /* ds_min_rtn_f64 */, AMDGPU::DS_MIN_RTN_F64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20073 : { 1624 /* ds_min_rtn_i32 */, AMDGPU::DS_MIN_RTN_I32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20074 : { 1624 /* ds_min_rtn_i32 */, AMDGPU::DS_MIN_RTN_I32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20075 : { 1639 /* ds_min_rtn_i64 */, AMDGPU::DS_MIN_RTN_I64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20076 : { 1639 /* ds_min_rtn_i64 */, AMDGPU::DS_MIN_RTN_I64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20077 : { 1654 /* ds_min_rtn_u32 */, AMDGPU::DS_MIN_RTN_U32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20078 : { 1654 /* ds_min_rtn_u32 */, AMDGPU::DS_MIN_RTN_U32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20079 : { 1669 /* ds_min_rtn_u64 */, AMDGPU::DS_MIN_RTN_U64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20080 : { 1669 /* ds_min_rtn_u64 */, AMDGPU::DS_MIN_RTN_U64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20081 : { 1684 /* ds_min_src2_f32 */, AMDGPU::DS_MIN_SRC2_F32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20082 : { 1684 /* ds_min_src2_f32 */, AMDGPU::DS_MIN_SRC2_F32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20083 : { 1700 /* ds_min_src2_f64 */, AMDGPU::DS_MIN_SRC2_F64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20084 : { 1700 /* ds_min_src2_f64 */, AMDGPU::DS_MIN_SRC2_F64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20085 : { 1716 /* ds_min_src2_i32 */, AMDGPU::DS_MIN_SRC2_I32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20086 : { 1716 /* ds_min_src2_i32 */, AMDGPU::DS_MIN_SRC2_I32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20087 : { 1732 /* ds_min_src2_i64 */, AMDGPU::DS_MIN_SRC2_I64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20088 : { 1732 /* ds_min_src2_i64 */, AMDGPU::DS_MIN_SRC2_I64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20089 : { 1748 /* ds_min_src2_u32 */, AMDGPU::DS_MIN_SRC2_U32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20090 : { 1748 /* ds_min_src2_u32 */, AMDGPU::DS_MIN_SRC2_U32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20091 : { 1764 /* ds_min_src2_u64 */, AMDGPU::DS_MIN_SRC2_U64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20092 : { 1764 /* ds_min_src2_u64 */, AMDGPU::DS_MIN_SRC2_U64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20093 : { 1780 /* ds_min_u32 */, AMDGPU::DS_MIN_U32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20094 : { 1780 /* ds_min_u32 */, AMDGPU::DS_MIN_U32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20095 : { 1791 /* ds_min_u64 */, AMDGPU::DS_MIN_U64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20096 : { 1791 /* ds_min_u64 */, AMDGPU::DS_MIN_U64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20097 : { 1802 /* ds_mskor_b32 */, AMDGPU::DS_MSKOR_B32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20098 : { 1802 /* ds_mskor_b32 */, AMDGPU::DS_MSKOR_B32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20099 : { 1815 /* ds_mskor_b64 */, AMDGPU::DS_MSKOR_B64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20100 : { 1815 /* ds_mskor_b64 */, AMDGPU::DS_MSKOR_B64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20101 : { 1828 /* ds_mskor_rtn_b32 */, AMDGPU::DS_MSKOR_RTN_B32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20102 : { 1828 /* ds_mskor_rtn_b32 */, AMDGPU::DS_MSKOR_RTN_B32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20103 : { 1845 /* ds_mskor_rtn_b64 */, AMDGPU::DS_MSKOR_RTN_B64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20104 : { 1845 /* ds_mskor_rtn_b64 */, AMDGPU::DS_MSKOR_RTN_B64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20105 : { 1862 /* ds_or_b32 */, AMDGPU::DS_OR_B32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20106 : { 1862 /* ds_or_b32 */, AMDGPU::DS_OR_B32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20107 : { 1872 /* ds_or_b64 */, AMDGPU::DS_OR_B64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20108 : { 1872 /* ds_or_b64 */, AMDGPU::DS_OR_B64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20109 : { 1882 /* ds_or_rtn_b32 */, AMDGPU::DS_OR_RTN_B32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20110 : { 1882 /* ds_or_rtn_b32 */, AMDGPU::DS_OR_RTN_B32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20111 : { 1896 /* ds_or_rtn_b64 */, AMDGPU::DS_OR_RTN_B64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20112 : { 1896 /* ds_or_rtn_b64 */, AMDGPU::DS_OR_RTN_B64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20113 : { 1910 /* ds_or_src2_b32 */, AMDGPU::DS_OR_SRC2_B32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20114 : { 1910 /* ds_or_src2_b32 */, AMDGPU::DS_OR_SRC2_B32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20115 : { 1925 /* ds_or_src2_b64 */, AMDGPU::DS_OR_SRC2_B64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20116 : { 1925 /* ds_or_src2_b64 */, AMDGPU::DS_OR_SRC2_B64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20117 : { 1940 /* ds_ordered_count */, AMDGPU::DS_ORDERED_COUNT_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOffsetOptional, MCK_gds }, },
20118 : { 1940 /* ds_ordered_count */, AMDGPU::DS_ORDERED_COUNT_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOffsetOptional, MCK_gds }, },
20119 : { 1957 /* ds_read2_b32 */, AMDGPU::DS_READ2_B32_si, ConvertCustom_cvtDSOffset01, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_DSOffset1, MCK_DSOffset1, MCK_GDSparseDSOff01OptionalOps }, },
20120 : { 1957 /* ds_read2_b32 */, AMDGPU::DS_READ2_B32_vi, ConvertCustom_cvtDSOffset01, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_DSOffset1, MCK_DSOffset1, MCK_GDSparseDSOff01OptionalOps }, },
20121 : { 1970 /* ds_read2_b64 */, AMDGPU::DS_READ2_B64_si, ConvertCustom_cvtDSOffset01, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_DSOffset1, MCK_DSOffset1, MCK_GDSparseDSOff01OptionalOps }, },
20122 : { 1970 /* ds_read2_b64 */, AMDGPU::DS_READ2_B64_vi, ConvertCustom_cvtDSOffset01, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_DSOffset1, MCK_DSOffset1, MCK_GDSparseDSOff01OptionalOps }, },
20123 : { 1983 /* ds_read2st64_b32 */, AMDGPU::DS_READ2ST64_B32_si, ConvertCustom_cvtDSOffset01, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_DSOffset1, MCK_DSOffset1, MCK_GDSparseDSOff01OptionalOps }, },
20124 : { 1983 /* ds_read2st64_b32 */, AMDGPU::DS_READ2ST64_B32_vi, ConvertCustom_cvtDSOffset01, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_DSOffset1, MCK_DSOffset1, MCK_GDSparseDSOff01OptionalOps }, },
20125 : { 2000 /* ds_read2st64_b64 */, AMDGPU::DS_READ2ST64_B64_si, ConvertCustom_cvtDSOffset01, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_DSOffset1, MCK_DSOffset1, MCK_GDSparseDSOff01OptionalOps }, },
20126 : { 2000 /* ds_read2st64_b64 */, AMDGPU::DS_READ2ST64_B64_vi, ConvertCustom_cvtDSOffset01, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_DSOffset1, MCK_DSOffset1, MCK_GDSparseDSOff01OptionalOps }, },
20127 : { 2017 /* ds_read_b32 */, AMDGPU::DS_READ_B32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20128 : { 2017 /* ds_read_b32 */, AMDGPU::DS_READ_B32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20129 : { 2029 /* ds_read_b64 */, AMDGPU::DS_READ_B64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20130 : { 2029 /* ds_read_b64 */, AMDGPU::DS_READ_B64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20131 : { 2041 /* ds_read_i16 */, AMDGPU::DS_READ_I16_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20132 : { 2041 /* ds_read_i16 */, AMDGPU::DS_READ_I16_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20133 : { 2053 /* ds_read_i8 */, AMDGPU::DS_READ_I8_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20134 : { 2053 /* ds_read_i8 */, AMDGPU::DS_READ_I8_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20135 : { 2064 /* ds_read_u16 */, AMDGPU::DS_READ_U16_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20136 : { 2064 /* ds_read_u16 */, AMDGPU::DS_READ_U16_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20137 : { 2076 /* ds_read_u8 */, AMDGPU::DS_READ_U8_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20138 : { 2076 /* ds_read_u8 */, AMDGPU::DS_READ_U8_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20139 : { 2087 /* ds_rsub_rtn_u32 */, AMDGPU::DS_RSUB_RTN_U32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20140 : { 2087 /* ds_rsub_rtn_u32 */, AMDGPU::DS_RSUB_RTN_U32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20141 : { 2103 /* ds_rsub_rtn_u64 */, AMDGPU::DS_RSUB_RTN_U64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20142 : { 2103 /* ds_rsub_rtn_u64 */, AMDGPU::DS_RSUB_RTN_U64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20143 : { 2119 /* ds_rsub_src2_u32 */, AMDGPU::DS_RSUB_SRC2_U32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20144 : { 2119 /* ds_rsub_src2_u32 */, AMDGPU::DS_RSUB_SRC2_U32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20145 : { 2136 /* ds_rsub_src2_u64 */, AMDGPU::DS_RSUB_SRC2_U64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20146 : { 2136 /* ds_rsub_src2_u64 */, AMDGPU::DS_RSUB_SRC2_U64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20147 : { 2153 /* ds_rsub_u32 */, AMDGPU::DS_RSUB_U32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20148 : { 2153 /* ds_rsub_u32 */, AMDGPU::DS_RSUB_U32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20149 : { 2165 /* ds_rsub_u64 */, AMDGPU::DS_RSUB_U64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20150 : { 2165 /* ds_rsub_u64 */, AMDGPU::DS_RSUB_U64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20151 : { 2177 /* ds_sub_rtn_u32 */, AMDGPU::DS_SUB_RTN_U32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20152 : { 2177 /* ds_sub_rtn_u32 */, AMDGPU::DS_SUB_RTN_U32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20153 : { 2192 /* ds_sub_rtn_u64 */, AMDGPU::DS_SUB_RTN_U64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20154 : { 2192 /* ds_sub_rtn_u64 */, AMDGPU::DS_SUB_RTN_U64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20155 : { 2207 /* ds_sub_src2_u32 */, AMDGPU::DS_SUB_SRC2_U32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20156 : { 2207 /* ds_sub_src2_u32 */, AMDGPU::DS_SUB_SRC2_U32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20157 : { 2223 /* ds_sub_src2_u64 */, AMDGPU::DS_SUB_SRC2_U64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20158 : { 2223 /* ds_sub_src2_u64 */, AMDGPU::DS_SUB_SRC2_U64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20159 : { 2239 /* ds_sub_u32 */, AMDGPU::DS_SUB_U32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20160 : { 2239 /* ds_sub_u32 */, AMDGPU::DS_SUB_U32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20161 : { 2250 /* ds_sub_u64 */, AMDGPU::DS_SUB_U64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20162 : { 2250 /* ds_sub_u64 */, AMDGPU::DS_SUB_U64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20163 : { 2261 /* ds_swizzle_b32 */, AMDGPU::DS_SWIZZLE_B32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20164 : { 2261 /* ds_swizzle_b32 */, AMDGPU::DS_SWIZZLE_B32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20165 : { 2276 /* ds_wrap_rtn_f32 */, AMDGPU::DS_WRAP_RTN_F32_si, ConvertCustom_cvtDS, 0, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20166 : { 2276 /* ds_wrap_rtn_f32 */, AMDGPU::DS_WRAP_RTN_F32_vi, ConvertCustom_cvtDS, 0, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20167 : { 2292 /* ds_write2_b32 */, AMDGPU::DS_WRITE2_B32_si, ConvertCustom_cvtDSOffset01, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffset1, MCK_DSOffset1, MCK_GDSparseDSOff01OptionalOps }, },
20168 : { 2292 /* ds_write2_b32 */, AMDGPU::DS_WRITE2_B32_vi, ConvertCustom_cvtDSOffset01, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffset1, MCK_DSOffset1, MCK_GDSparseDSOff01OptionalOps }, },
20169 : { 2306 /* ds_write2_b64 */, AMDGPU::DS_WRITE2_B64_si, ConvertCustom_cvtDSOffset01, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_DSOffset1, MCK_DSOffset1, MCK_GDSparseDSOff01OptionalOps }, },
20170 : { 2306 /* ds_write2_b64 */, AMDGPU::DS_WRITE2_B64_vi, ConvertCustom_cvtDSOffset01, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_DSOffset1, MCK_DSOffset1, MCK_GDSparseDSOff01OptionalOps }, },
20171 : { 2320 /* ds_write2st64_b32 */, AMDGPU::DS_WRITE2ST64_B32_si, ConvertCustom_cvtDSOffset01, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffset1, MCK_DSOffset1, MCK_GDSparseDSOff01OptionalOps }, },
20172 : { 2320 /* ds_write2st64_b32 */, AMDGPU::DS_WRITE2ST64_B32_vi, ConvertCustom_cvtDSOffset01, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffset1, MCK_DSOffset1, MCK_GDSparseDSOff01OptionalOps }, },
20173 : { 2338 /* ds_write2st64_b64 */, AMDGPU::DS_WRITE2ST64_B64_si, ConvertCustom_cvtDSOffset01, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_DSOffset1, MCK_DSOffset1, MCK_GDSparseDSOff01OptionalOps }, },
20174 : { 2338 /* ds_write2st64_b64 */, AMDGPU::DS_WRITE2ST64_B64_vi, ConvertCustom_cvtDSOffset01, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_DSOffset1, MCK_DSOffset1, MCK_GDSparseDSOff01OptionalOps }, },
20175 : { 2356 /* ds_write_b16 */, AMDGPU::DS_WRITE_B16_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20176 : { 2356 /* ds_write_b16 */, AMDGPU::DS_WRITE_B16_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20177 : { 2369 /* ds_write_b32 */, AMDGPU::DS_WRITE_B32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20178 : { 2369 /* ds_write_b32 */, AMDGPU::DS_WRITE_B32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20179 : { 2382 /* ds_write_b64 */, AMDGPU::DS_WRITE_B64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20180 : { 2382 /* ds_write_b64 */, AMDGPU::DS_WRITE_B64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20181 : { 2395 /* ds_write_b8 */, AMDGPU::DS_WRITE_B8_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20182 : { 2395 /* ds_write_b8 */, AMDGPU::DS_WRITE_B8_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20183 : { 2407 /* ds_write_src2_b32 */, AMDGPU::DS_WRITE_SRC2_B32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20184 : { 2407 /* ds_write_src2_b32 */, AMDGPU::DS_WRITE_SRC2_B32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20185 : { 2425 /* ds_write_src2_b64 */, AMDGPU::DS_WRITE_SRC2_B64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20186 : { 2425 /* ds_write_src2_b64 */, AMDGPU::DS_WRITE_SRC2_B64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20187 : { 2443 /* ds_wrxchg2_rtn_b32 */, AMDGPU::DS_WRXCHG2_RTN_B32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20188 : { 2443 /* ds_wrxchg2_rtn_b32 */, AMDGPU::DS_WRXCHG2_RTN_B32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20189 : { 2462 /* ds_wrxchg2_rtn_b64 */, AMDGPU::DS_WRXCHG2_RTN_B64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20190 : { 2462 /* ds_wrxchg2_rtn_b64 */, AMDGPU::DS_WRXCHG2_RTN_B64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20191 : { 2481 /* ds_wrxchg2st64_rtn_b32 */, AMDGPU::DS_WRXCHG2ST64_RTN_B32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20192 : { 2481 /* ds_wrxchg2st64_rtn_b32 */, AMDGPU::DS_WRXCHG2ST64_RTN_B32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20193 : { 2504 /* ds_wrxchg2st64_rtn_b64 */, AMDGPU::DS_WRXCHG2ST64_RTN_B64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20194 : { 2504 /* ds_wrxchg2st64_rtn_b64 */, AMDGPU::DS_WRXCHG2ST64_RTN_B64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20195 : { 2527 /* ds_wrxchg_rtn_b32 */, AMDGPU::DS_WRXCHG_RTN_B32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20196 : { 2527 /* ds_wrxchg_rtn_b32 */, AMDGPU::DS_WRXCHG_RTN_B32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20197 : { 2545 /* ds_wrxchg_rtn_b64 */, AMDGPU::DS_WRXCHG_RTN_B64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20198 : { 2545 /* ds_wrxchg_rtn_b64 */, AMDGPU::DS_WRXCHG_RTN_B64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20199 : { 2563 /* ds_xor_b32 */, AMDGPU::DS_XOR_B32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20200 : { 2563 /* ds_xor_b32 */, AMDGPU::DS_XOR_B32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20201 : { 2574 /* ds_xor_b64 */, AMDGPU::DS_XOR_B64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20202 : { 2574 /* ds_xor_b64 */, AMDGPU::DS_XOR_B64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20203 : { 2585 /* ds_xor_rtn_b32 */, AMDGPU::DS_XOR_RTN_B32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20204 : { 2585 /* ds_xor_rtn_b32 */, AMDGPU::DS_XOR_RTN_B32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20205 : { 2600 /* ds_xor_rtn_b64 */, AMDGPU::DS_XOR_RTN_B64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20206 : { 2600 /* ds_xor_rtn_b64 */, AMDGPU::DS_XOR_RTN_B64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20207 : { 2615 /* ds_xor_src2_b32 */, AMDGPU::DS_XOR_SRC2_B32_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20208 : { 2615 /* ds_xor_src2_b32 */, AMDGPU::DS_XOR_SRC2_B32_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20209 : { 2631 /* ds_xor_src2_b64 */, AMDGPU::DS_XOR_SRC2_B64_si, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20210 : { 2631 /* ds_xor_src2_b64 */, AMDGPU::DS_XOR_SRC2_B64_vi, ConvertCustom_cvtDS, Feature_isGCN, { MCK_VGPR_32, MCK_DSOffsetparseDSOptionalOps, MCK_GDSparseDSOptionalOps }, },
20211 : { 2647 /* exp */, AMDGPU::EXP_si, Convert__Imm1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Reg1_5__Reg1_6__Reg1_7__Reg1_8, Feature_isGCN, { MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32 }, },
20212 : { 2647 /* exp */, AMDGPU::EXP_vi, Convert__Imm1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Reg1_5__Reg1_6__Reg1_7__Reg1_8, Feature_isGCN, { MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32 }, },
20213 : { 2651 /* flat_load_dword */, AMDGPU::FLAT_LOAD_DWORD, Convert__Reg1_0__Reg1_1, 0, { MCK_VGPR_32, MCK_VReg_64, MCK__91_, MCK_M0, MCK_FLAT_95_SCRATCH, MCK__93_ }, },
20214 : { 2667 /* flat_load_dwordx2 */, AMDGPU::FLAT_LOAD_DWORDX2, Convert__Reg1_0__Reg1_1, 0, { MCK_VReg_64, MCK_VReg_64, MCK__91_, MCK_M0, MCK_FLAT_95_SCRATCH, MCK__93_ }, },
20215 : { 2685 /* flat_load_dwordx3 */, AMDGPU::FLAT_LOAD_DWORDX3, Convert__Reg1_0__Reg1_1, 0, { MCK_VReg_96, MCK_VReg_64, MCK__91_, MCK_M0, MCK_FLAT_95_SCRATCH, MCK__93_ }, },
20216 : { 2703 /* flat_load_dwordx4 */, AMDGPU::FLAT_LOAD_DWORDX4, Convert__Reg1_0__Reg1_1, 0, { MCK_VReg_128, MCK_VReg_64, MCK__91_, MCK_M0, MCK_FLAT_95_SCRATCH, MCK__93_ }, },
20217 : { 2721 /* flat_load_sbyte */, AMDGPU::FLAT_LOAD_SBYTE, Convert__Reg1_0__Reg1_1, 0, { MCK_VGPR_32, MCK_VReg_64, MCK__91_, MCK_M0, MCK_FLAT_95_SCRATCH, MCK__93_ }, },
20218 : { 2737 /* flat_load_sshort */, AMDGPU::FLAT_LOAD_SSHORT, Convert__Reg1_0__Reg1_1, 0, { MCK_VGPR_32, MCK_VReg_64, MCK__91_, MCK_M0, MCK_FLAT_95_SCRATCH, MCK__93_ }, },
20219 : { 2754 /* flat_load_ubyte */, AMDGPU::FLAT_LOAD_UBYTE, Convert__Reg1_0__Reg1_1, 0, { MCK_VGPR_32, MCK_VReg_64, MCK__91_, MCK_M0, MCK_FLAT_95_SCRATCH, MCK__93_ }, },
20220 : { 2770 /* flat_load_ushort */, AMDGPU::FLAT_LOAD_USHORT, Convert__Reg1_0__Reg1_1, 0, { MCK_VGPR_32, MCK_VReg_64, MCK__91_, MCK_M0, MCK_FLAT_95_SCRATCH, MCK__93_ }, },
20221 : { 2787 /* flat_store_byte */, AMDGPU::FLAT_STORE_BYTE, Convert__Reg1_0__Reg1_1, 0, { MCK_VGPR_32, MCK_VReg_64, MCK__91_, MCK_M0, MCK_FLAT_95_SCRATCH, MCK__93_ }, },
20222 : { 2803 /* flat_store_dword */, AMDGPU::FLAT_STORE_DWORD, Convert__Reg1_0__Reg1_1, 0, { MCK_VGPR_32, MCK_VReg_64, MCK__91_, MCK_M0, MCK_FLAT_95_SCRATCH, MCK__93_ }, },
20223 : { 2820 /* flat_store_dwordx2 */, AMDGPU::FLAT_STORE_DWORDX2, Convert__Reg1_0__Reg1_1, 0, { MCK_VReg_64, MCK_VReg_64, MCK__91_, MCK_M0, MCK_FLAT_95_SCRATCH, MCK__93_ }, },
20224 : { 2839 /* flat_store_dwordx3 */, AMDGPU::FLAT_STORE_DWORDX3, Convert__Reg1_0__Reg1_1, 0, { MCK_VReg_96, MCK_VReg_64, MCK__91_, MCK_M0, MCK_FLAT_95_SCRATCH, MCK__93_ }, },
20225 : { 2858 /* flat_store_dwordx4 */, AMDGPU::FLAT_STORE_DWORDX4, Convert__Reg1_0__Reg1_1, 0, { MCK_VReg_128, MCK_VReg_64, MCK__91_, MCK_M0, MCK_FLAT_95_SCRATCH, MCK__93_ }, },
20226 : { 2877 /* flat_store_short */, AMDGPU::FLAT_STORE_SHORT, Convert__Reg1_0__Reg1_1, 0, { MCK_VGPR_32, MCK_VReg_64, MCK__91_, MCK_M0, MCK_FLAT_95_SCRATCH, MCK__93_ }, },
20227 : { 2894 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20228 : { 2894 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20229 : { 2894 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20230 : { 2894 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20231 : { 2894 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20232 : { 2894 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20233 : { 2894 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20234 : { 2894 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20235 : { 2894 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20236 : { 2894 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20237 : { 2894 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20238 : { 2894 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20239 : { 2894 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20240 : { 2894 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20241 : { 2894 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20242 : { 2894 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20243 : { 2894 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20244 : { 2894 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20245 : { 2894 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20246 : { 2894 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20247 : { 2908 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20248 : { 2908 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20249 : { 2908 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20250 : { 2908 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20251 : { 2908 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20252 : { 2908 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20253 : { 2908 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20254 : { 2908 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20255 : { 2908 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20256 : { 2908 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20257 : { 2908 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20258 : { 2908 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20259 : { 2908 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20260 : { 2908 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20261 : { 2908 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20262 : { 2908 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20263 : { 2908 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20264 : { 2908 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20265 : { 2908 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20266 : { 2908 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20267 : { 2924 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20268 : { 2924 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20269 : { 2924 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20270 : { 2924 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20271 : { 2924 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20272 : { 2924 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20273 : { 2924 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20274 : { 2924 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20275 : { 2924 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20276 : { 2924 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20277 : { 2924 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20278 : { 2924 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20279 : { 2924 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20280 : { 2924 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20281 : { 2924 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20282 : { 2924 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20283 : { 2924 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20284 : { 2924 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20285 : { 2924 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20286 : { 2924 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20287 : { 2943 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20288 : { 2943 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20289 : { 2943 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20290 : { 2943 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20291 : { 2943 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20292 : { 2943 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20293 : { 2943 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20294 : { 2943 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20295 : { 2943 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20296 : { 2943 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20297 : { 2943 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20298 : { 2943 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20299 : { 2943 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20300 : { 2943 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20301 : { 2943 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20302 : { 2943 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20303 : { 2943 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20304 : { 2943 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20305 : { 2943 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20306 : { 2943 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20307 : { 2964 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20308 : { 2964 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20309 : { 2964 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20310 : { 2964 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20311 : { 2964 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20312 : { 2964 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20313 : { 2964 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20314 : { 2964 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20315 : { 2964 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20316 : { 2964 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20317 : { 2964 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20318 : { 2964 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20319 : { 2964 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20320 : { 2964 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20321 : { 2964 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20322 : { 2964 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20323 : { 2964 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20324 : { 2964 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20325 : { 2964 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20326 : { 2964 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20327 : { 2982 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20328 : { 2982 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20329 : { 2982 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20330 : { 2982 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20331 : { 2982 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20332 : { 2982 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20333 : { 2982 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20334 : { 2982 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20335 : { 2982 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20336 : { 2982 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20337 : { 2982 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20338 : { 2982 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20339 : { 2982 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20340 : { 2982 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20341 : { 2982 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20342 : { 2982 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20343 : { 2982 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20344 : { 2982 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20345 : { 2982 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20346 : { 2982 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20347 : { 2998 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20348 : { 2998 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20349 : { 2998 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20350 : { 2998 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20351 : { 2998 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20352 : { 2998 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20353 : { 2998 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20354 : { 2998 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20355 : { 2998 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20356 : { 2998 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20357 : { 2998 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20358 : { 2998 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20359 : { 2998 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20360 : { 2998 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20361 : { 2998 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20362 : { 2998 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20363 : { 2998 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20364 : { 2998 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20365 : { 2998 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20366 : { 2998 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20367 : { 3016 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20368 : { 3016 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20369 : { 3016 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20370 : { 3016 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20371 : { 3016 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20372 : { 3016 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20373 : { 3016 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20374 : { 3016 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20375 : { 3016 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20376 : { 3016 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20377 : { 3016 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20378 : { 3016 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20379 : { 3016 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20380 : { 3016 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20381 : { 3016 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20382 : { 3016 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20383 : { 3016 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20384 : { 3016 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20385 : { 3016 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20386 : { 3016 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20387 : { 3037 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20388 : { 3037 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20389 : { 3037 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20390 : { 3037 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20391 : { 3037 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20392 : { 3037 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20393 : { 3037 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20394 : { 3037 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20395 : { 3037 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20396 : { 3037 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20397 : { 3037 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20398 : { 3037 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20399 : { 3037 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20400 : { 3037 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20401 : { 3037 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20402 : { 3037 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20403 : { 3037 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20404 : { 3037 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20405 : { 3037 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20406 : { 3037 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20407 : { 3060 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20408 : { 3060 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20409 : { 3060 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20410 : { 3060 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20411 : { 3060 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20412 : { 3060 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20413 : { 3060 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20414 : { 3060 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20415 : { 3060 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20416 : { 3060 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20417 : { 3060 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20418 : { 3060 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20419 : { 3060 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20420 : { 3060 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20421 : { 3060 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20422 : { 3060 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20423 : { 3060 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20424 : { 3060 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20425 : { 3060 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20426 : { 3060 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20427 : { 3080 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20428 : { 3080 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20429 : { 3080 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20430 : { 3080 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20431 : { 3080 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20432 : { 3080 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20433 : { 3080 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20434 : { 3080 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20435 : { 3080 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20436 : { 3080 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20437 : { 3080 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20438 : { 3080 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20439 : { 3080 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20440 : { 3080 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20441 : { 3080 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20442 : { 3080 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20443 : { 3080 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20444 : { 3080 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20445 : { 3080 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20446 : { 3080 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20447 : { 3099 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20448 : { 3099 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20449 : { 3099 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20450 : { 3099 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20451 : { 3099 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20452 : { 3099 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20453 : { 3099 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20454 : { 3099 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20455 : { 3099 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20456 : { 3099 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20457 : { 3099 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20458 : { 3099 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20459 : { 3099 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20460 : { 3099 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20461 : { 3099 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20462 : { 3099 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20463 : { 3099 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20464 : { 3099 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20465 : { 3099 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20466 : { 3099 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20467 : { 3120 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20468 : { 3120 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20469 : { 3120 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20470 : { 3120 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20471 : { 3120 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20472 : { 3120 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20473 : { 3120 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20474 : { 3120 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20475 : { 3120 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20476 : { 3120 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20477 : { 3120 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20478 : { 3120 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20479 : { 3120 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20480 : { 3120 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20481 : { 3120 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20482 : { 3120 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20483 : { 3120 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20484 : { 3120 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20485 : { 3120 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20486 : { 3120 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20487 : { 3138 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20488 : { 3138 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20489 : { 3138 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20490 : { 3138 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20491 : { 3138 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20492 : { 3138 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20493 : { 3138 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20494 : { 3138 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20495 : { 3138 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20496 : { 3138 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20497 : { 3138 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20498 : { 3138 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20499 : { 3138 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20500 : { 3138 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20501 : { 3138 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20502 : { 3138 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20503 : { 3138 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20504 : { 3138 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20505 : { 3138 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20506 : { 3138 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20507 : { 3158 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20508 : { 3158 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20509 : { 3158 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20510 : { 3158 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20511 : { 3158 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20512 : { 3158 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20513 : { 3158 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20514 : { 3158 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20515 : { 3158 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20516 : { 3158 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20517 : { 3158 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20518 : { 3158 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20519 : { 3158 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20520 : { 3158 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20521 : { 3158 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20522 : { 3158 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20523 : { 3158 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20524 : { 3158 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20525 : { 3158 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20526 : { 3158 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20527 : { 3177 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20528 : { 3177 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20529 : { 3177 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20530 : { 3177 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20531 : { 3177 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20532 : { 3177 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20533 : { 3177 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20534 : { 3177 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20535 : { 3177 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20536 : { 3177 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20537 : { 3177 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20538 : { 3177 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20539 : { 3177 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20540 : { 3177 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20541 : { 3177 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20542 : { 3177 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20543 : { 3177 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20544 : { 3177 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20545 : { 3177 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20546 : { 3177 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20547 : { 3198 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20548 : { 3198 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20549 : { 3198 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20550 : { 3198 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20551 : { 3198 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20552 : { 3198 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20553 : { 3198 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20554 : { 3198 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20555 : { 3198 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20556 : { 3198 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20557 : { 3198 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20558 : { 3198 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20559 : { 3198 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20560 : { 3198 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20561 : { 3198 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20562 : { 3198 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20563 : { 3198 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20564 : { 3198 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20565 : { 3198 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20566 : { 3198 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20567 : { 3216 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20568 : { 3216 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20569 : { 3216 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20570 : { 3216 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20571 : { 3216 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20572 : { 3216 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20573 : { 3216 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20574 : { 3216 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20575 : { 3216 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20576 : { 3216 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20577 : { 3216 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20578 : { 3216 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20579 : { 3216 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20580 : { 3216 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20581 : { 3216 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20582 : { 3216 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20583 : { 3216 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20584 : { 3216 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20585 : { 3216 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20586 : { 3216 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20587 : { 3233 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20588 : { 3233 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20589 : { 3233 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20590 : { 3233 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20591 : { 3233 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20592 : { 3233 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20593 : { 3233 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20594 : { 3233 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20595 : { 3233 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20596 : { 3233 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20597 : { 3233 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20598 : { 3233 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20599 : { 3233 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20600 : { 3233 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20601 : { 3233 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20602 : { 3233 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20603 : { 3233 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20604 : { 3233 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20605 : { 3233 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20606 : { 3233 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20607 : { 3252 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20608 : { 3252 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20609 : { 3252 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20610 : { 3252 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20611 : { 3252 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20612 : { 3252 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20613 : { 3252 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20614 : { 3252 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20615 : { 3252 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20616 : { 3252 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20617 : { 3252 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20618 : { 3252 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20619 : { 3252 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20620 : { 3252 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20621 : { 3252 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20622 : { 3252 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20623 : { 3252 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20624 : { 3252 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20625 : { 3252 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20626 : { 3252 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20627 : { 3268 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20628 : { 3268 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20629 : { 3268 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20630 : { 3268 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20631 : { 3268 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20632 : { 3268 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20633 : { 3268 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20634 : { 3268 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20635 : { 3268 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20636 : { 3268 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20637 : { 3268 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20638 : { 3268 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20639 : { 3268 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20640 : { 3268 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20641 : { 3268 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20642 : { 3268 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20643 : { 3268 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20644 : { 3268 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20645 : { 3268 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20646 : { 3268 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20647 : { 3286 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20648 : { 3286 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20649 : { 3286 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20650 : { 3286 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20651 : { 3286 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20652 : { 3286 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20653 : { 3286 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20654 : { 3286 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20655 : { 3286 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20656 : { 3286 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20657 : { 3286 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20658 : { 3286 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20659 : { 3286 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20660 : { 3286 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20661 : { 3286 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20662 : { 3286 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20663 : { 3286 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20664 : { 3286 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20665 : { 3286 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20666 : { 3286 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20667 : { 3303 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20668 : { 3303 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20669 : { 3303 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20670 : { 3303 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20671 : { 3303 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20672 : { 3303 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20673 : { 3303 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20674 : { 3303 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20675 : { 3303 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20676 : { 3303 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20677 : { 3303 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20678 : { 3303 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20679 : { 3303 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20680 : { 3303 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20681 : { 3303 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20682 : { 3303 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20683 : { 3303 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20684 : { 3303 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20685 : { 3303 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20686 : { 3303 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20687 : { 3322 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20688 : { 3322 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20689 : { 3322 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20690 : { 3322 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20691 : { 3322 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20692 : { 3322 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20693 : { 3322 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20694 : { 3322 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20695 : { 3322 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20696 : { 3322 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20697 : { 3322 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20698 : { 3322 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20699 : { 3322 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20700 : { 3322 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20701 : { 3322 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20702 : { 3322 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20703 : { 3322 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20704 : { 3322 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20705 : { 3322 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20706 : { 3322 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20707 : { 3338 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20708 : { 3338 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20709 : { 3338 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20710 : { 3338 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20711 : { 3338 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20712 : { 3338 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20713 : { 3338 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20714 : { 3338 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20715 : { 3338 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20716 : { 3338 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20717 : { 3338 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20718 : { 3338 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20719 : { 3338 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20720 : { 3338 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20721 : { 3338 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20722 : { 3338 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20723 : { 3338 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20724 : { 3338 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20725 : { 3338 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20726 : { 3338 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20727 : { 3352 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256 }, },
20728 : { 3352 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256 }, },
20729 : { 3352 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256 }, },
20730 : { 3352 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256 }, },
20731 : { 3352 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256 }, },
20732 : { 3352 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256 }, },
20733 : { 3352 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256 }, },
20734 : { 3352 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256 }, },
20735 : { 3352 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256 }, },
20736 : { 3352 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256 }, },
20737 : { 3352 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256 }, },
20738 : { 3352 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256 }, },
20739 : { 3370 /* image_load */, AMDGPU::IMAGE_LOAD_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256 }, },
20740 : { 3370 /* image_load */, AMDGPU::IMAGE_LOAD_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256 }, },
20741 : { 3370 /* image_load */, AMDGPU::IMAGE_LOAD_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256 }, },
20742 : { 3370 /* image_load */, AMDGPU::IMAGE_LOAD_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256 }, },
20743 : { 3370 /* image_load */, AMDGPU::IMAGE_LOAD_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256 }, },
20744 : { 3370 /* image_load */, AMDGPU::IMAGE_LOAD_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256 }, },
20745 : { 3370 /* image_load */, AMDGPU::IMAGE_LOAD_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256 }, },
20746 : { 3370 /* image_load */, AMDGPU::IMAGE_LOAD_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256 }, },
20747 : { 3370 /* image_load */, AMDGPU::IMAGE_LOAD_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256 }, },
20748 : { 3370 /* image_load */, AMDGPU::IMAGE_LOAD_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256 }, },
20749 : { 3370 /* image_load */, AMDGPU::IMAGE_LOAD_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256 }, },
20750 : { 3370 /* image_load */, AMDGPU::IMAGE_LOAD_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256 }, },
20751 : { 3381 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256 }, },
20752 : { 3381 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256 }, },
20753 : { 3381 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256 }, },
20754 : { 3381 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256 }, },
20755 : { 3381 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256 }, },
20756 : { 3381 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256 }, },
20757 : { 3381 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256 }, },
20758 : { 3381 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256 }, },
20759 : { 3381 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256 }, },
20760 : { 3381 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256 }, },
20761 : { 3381 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256 }, },
20762 : { 3381 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256 }, },
20763 : { 3396 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20764 : { 3396 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20765 : { 3396 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20766 : { 3396 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20767 : { 3396 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20768 : { 3396 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20769 : { 3396 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20770 : { 3396 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20771 : { 3396 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20772 : { 3396 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20773 : { 3396 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20774 : { 3396 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20775 : { 3396 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20776 : { 3396 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20777 : { 3396 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20778 : { 3396 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20779 : { 3396 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20780 : { 3396 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20781 : { 3396 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20782 : { 3396 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20783 : { 3409 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20784 : { 3409 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20785 : { 3409 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20786 : { 3409 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20787 : { 3409 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20788 : { 3409 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20789 : { 3409 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20790 : { 3409 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20791 : { 3409 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20792 : { 3409 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20793 : { 3409 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20794 : { 3409 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20795 : { 3409 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20796 : { 3409 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20797 : { 3409 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20798 : { 3409 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20799 : { 3409 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20800 : { 3409 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20801 : { 3409 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20802 : { 3409 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20803 : { 3424 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20804 : { 3424 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20805 : { 3424 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20806 : { 3424 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20807 : { 3424 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20808 : { 3424 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20809 : { 3424 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20810 : { 3424 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20811 : { 3424 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20812 : { 3424 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20813 : { 3424 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20814 : { 3424 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20815 : { 3424 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20816 : { 3424 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20817 : { 3424 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20818 : { 3424 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20819 : { 3424 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20820 : { 3424 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20821 : { 3424 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20822 : { 3424 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20823 : { 3442 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20824 : { 3442 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20825 : { 3442 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20826 : { 3442 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20827 : { 3442 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20828 : { 3442 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20829 : { 3442 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20830 : { 3442 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20831 : { 3442 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20832 : { 3442 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20833 : { 3442 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20834 : { 3442 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20835 : { 3442 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20836 : { 3442 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20837 : { 3442 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20838 : { 3442 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20839 : { 3442 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20840 : { 3442 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20841 : { 3442 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20842 : { 3442 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20843 : { 3462 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20844 : { 3462 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20845 : { 3462 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20846 : { 3462 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20847 : { 3462 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20848 : { 3462 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20849 : { 3462 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20850 : { 3462 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20851 : { 3462 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20852 : { 3462 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20853 : { 3462 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20854 : { 3462 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20855 : { 3462 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20856 : { 3462 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20857 : { 3462 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20858 : { 3462 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20859 : { 3462 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20860 : { 3462 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20861 : { 3462 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20862 : { 3462 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20863 : { 3479 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20864 : { 3479 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20865 : { 3479 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20866 : { 3479 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20867 : { 3479 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20868 : { 3479 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20869 : { 3479 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20870 : { 3479 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20871 : { 3479 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20872 : { 3479 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20873 : { 3479 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20874 : { 3479 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20875 : { 3479 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20876 : { 3479 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20877 : { 3479 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20878 : { 3479 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20879 : { 3479 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20880 : { 3479 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20881 : { 3479 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20882 : { 3479 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20883 : { 3494 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20884 : { 3494 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20885 : { 3494 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20886 : { 3494 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20887 : { 3494 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20888 : { 3494 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20889 : { 3494 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20890 : { 3494 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20891 : { 3494 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20892 : { 3494 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20893 : { 3494 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20894 : { 3494 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20895 : { 3494 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20896 : { 3494 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20897 : { 3494 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20898 : { 3494 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20899 : { 3494 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20900 : { 3494 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20901 : { 3494 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20902 : { 3494 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20903 : { 3511 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20904 : { 3511 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20905 : { 3511 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20906 : { 3511 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20907 : { 3511 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20908 : { 3511 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20909 : { 3511 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20910 : { 3511 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20911 : { 3511 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20912 : { 3511 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20913 : { 3511 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20914 : { 3511 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20915 : { 3511 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20916 : { 3511 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20917 : { 3511 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20918 : { 3511 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20919 : { 3511 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20920 : { 3511 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20921 : { 3511 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20922 : { 3511 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20923 : { 3531 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20924 : { 3531 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20925 : { 3531 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20926 : { 3531 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20927 : { 3531 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20928 : { 3531 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20929 : { 3531 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20930 : { 3531 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20931 : { 3531 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20932 : { 3531 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20933 : { 3531 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20934 : { 3531 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20935 : { 3531 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20936 : { 3531 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20937 : { 3531 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20938 : { 3531 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20939 : { 3531 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20940 : { 3531 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20941 : { 3531 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20942 : { 3531 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20943 : { 3553 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20944 : { 3553 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20945 : { 3553 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20946 : { 3553 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20947 : { 3553 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20948 : { 3553 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20949 : { 3553 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20950 : { 3553 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20951 : { 3553 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20952 : { 3553 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20953 : { 3553 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20954 : { 3553 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20955 : { 3553 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20956 : { 3553 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20957 : { 3553 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20958 : { 3553 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20959 : { 3553 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20960 : { 3553 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20961 : { 3553 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20962 : { 3553 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20963 : { 3572 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20964 : { 3572 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20965 : { 3572 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20966 : { 3572 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20967 : { 3572 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20968 : { 3572 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20969 : { 3572 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20970 : { 3572 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20971 : { 3572 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20972 : { 3572 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20973 : { 3572 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20974 : { 3572 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20975 : { 3572 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20976 : { 3572 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20977 : { 3572 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20978 : { 3572 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20979 : { 3572 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20980 : { 3572 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20981 : { 3572 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20982 : { 3572 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20983 : { 3590 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20984 : { 3590 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20985 : { 3590 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20986 : { 3590 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20987 : { 3590 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20988 : { 3590 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20989 : { 3590 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20990 : { 3590 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20991 : { 3590 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20992 : { 3590 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20993 : { 3590 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20994 : { 3590 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
20995 : { 3590 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
20996 : { 3590 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
20997 : { 3590 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
20998 : { 3590 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
20999 : { 3590 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21000 : { 3590 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21001 : { 3590 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21002 : { 3590 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21003 : { 3611 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21004 : { 3611 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21005 : { 3611 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21006 : { 3611 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21007 : { 3611 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21008 : { 3611 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21009 : { 3611 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21010 : { 3611 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21011 : { 3611 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21012 : { 3611 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21013 : { 3611 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21014 : { 3611 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21015 : { 3611 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21016 : { 3611 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21017 : { 3611 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21018 : { 3611 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21019 : { 3611 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21020 : { 3611 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21021 : { 3611 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21022 : { 3611 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21023 : { 3634 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21024 : { 3634 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21025 : { 3634 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21026 : { 3634 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21027 : { 3634 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21028 : { 3634 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21029 : { 3634 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21030 : { 3634 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21031 : { 3634 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21032 : { 3634 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21033 : { 3634 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21034 : { 3634 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21035 : { 3634 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21036 : { 3634 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21037 : { 3634 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21038 : { 3634 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21039 : { 3634 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21040 : { 3634 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21041 : { 3634 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21042 : { 3634 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21043 : { 3654 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21044 : { 3654 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21045 : { 3654 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21046 : { 3654 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21047 : { 3654 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21048 : { 3654 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21049 : { 3654 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21050 : { 3654 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21051 : { 3654 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21052 : { 3654 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21053 : { 3654 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21054 : { 3654 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21055 : { 3654 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21056 : { 3654 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21057 : { 3654 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21058 : { 3654 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21059 : { 3654 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21060 : { 3654 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21061 : { 3654 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21062 : { 3654 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21063 : { 3672 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21064 : { 3672 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21065 : { 3672 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21066 : { 3672 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21067 : { 3672 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21068 : { 3672 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21069 : { 3672 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21070 : { 3672 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21071 : { 3672 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21072 : { 3672 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21073 : { 3672 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21074 : { 3672 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21075 : { 3672 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21076 : { 3672 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21077 : { 3672 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21078 : { 3672 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21079 : { 3672 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21080 : { 3672 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21081 : { 3672 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21082 : { 3672 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21083 : { 3692 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21084 : { 3692 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21085 : { 3692 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21086 : { 3692 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21087 : { 3692 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21088 : { 3692 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21089 : { 3692 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21090 : { 3692 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21091 : { 3692 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21092 : { 3692 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21093 : { 3692 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21094 : { 3692 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21095 : { 3692 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21096 : { 3692 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21097 : { 3692 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21098 : { 3692 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21099 : { 3692 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21100 : { 3692 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21101 : { 3692 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21102 : { 3692 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21103 : { 3709 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21104 : { 3709 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21105 : { 3709 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21106 : { 3709 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21107 : { 3709 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21108 : { 3709 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21109 : { 3709 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21110 : { 3709 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21111 : { 3709 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21112 : { 3709 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21113 : { 3709 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21114 : { 3709 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21115 : { 3709 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21116 : { 3709 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21117 : { 3709 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21118 : { 3709 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21119 : { 3709 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21120 : { 3709 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21121 : { 3709 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21122 : { 3709 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21123 : { 3729 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21124 : { 3729 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21125 : { 3729 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21126 : { 3729 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21127 : { 3729 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21128 : { 3729 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21129 : { 3729 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21130 : { 3729 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21131 : { 3729 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21132 : { 3729 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21133 : { 3729 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21134 : { 3729 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21135 : { 3729 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21136 : { 3729 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21137 : { 3729 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21138 : { 3729 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21139 : { 3729 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21140 : { 3729 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21141 : { 3729 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21142 : { 3729 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21143 : { 3751 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21144 : { 3751 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21145 : { 3751 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21146 : { 3751 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21147 : { 3751 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21148 : { 3751 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21149 : { 3751 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21150 : { 3751 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21151 : { 3751 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21152 : { 3751 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21153 : { 3751 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21154 : { 3751 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21155 : { 3751 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21156 : { 3751 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21157 : { 3751 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21158 : { 3751 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21159 : { 3751 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21160 : { 3751 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21161 : { 3751 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21162 : { 3751 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21163 : { 3770 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21164 : { 3770 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21165 : { 3770 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21166 : { 3770 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21167 : { 3770 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21168 : { 3770 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21169 : { 3770 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21170 : { 3770 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21171 : { 3770 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21172 : { 3770 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21173 : { 3770 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21174 : { 3770 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21175 : { 3770 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21176 : { 3770 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21177 : { 3770 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21178 : { 3770 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21179 : { 3770 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21180 : { 3770 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21181 : { 3770 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21182 : { 3770 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21183 : { 3787 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21184 : { 3787 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21185 : { 3787 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21186 : { 3787 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21187 : { 3787 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21188 : { 3787 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21189 : { 3787 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21190 : { 3787 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21191 : { 3787 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21192 : { 3787 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21193 : { 3787 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21194 : { 3787 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21195 : { 3787 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21196 : { 3787 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21197 : { 3787 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21198 : { 3787 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21199 : { 3787 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21200 : { 3787 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21201 : { 3787 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21202 : { 3787 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21203 : { 3806 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21204 : { 3806 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21205 : { 3806 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21206 : { 3806 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21207 : { 3806 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21208 : { 3806 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21209 : { 3806 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21210 : { 3806 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21211 : { 3806 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21212 : { 3806 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21213 : { 3806 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21214 : { 3806 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21215 : { 3806 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21216 : { 3806 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21217 : { 3806 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21218 : { 3806 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21219 : { 3806 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21220 : { 3806 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21221 : { 3806 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21222 : { 3806 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21223 : { 3824 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21224 : { 3824 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21225 : { 3824 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21226 : { 3824 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21227 : { 3824 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21228 : { 3824 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21229 : { 3824 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21230 : { 3824 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21231 : { 3824 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21232 : { 3824 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21233 : { 3824 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21234 : { 3824 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21235 : { 3824 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21236 : { 3824 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21237 : { 3824 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21238 : { 3824 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21239 : { 3824 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21240 : { 3824 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21241 : { 3824 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21242 : { 3824 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21243 : { 3844 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21244 : { 3844 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21245 : { 3844 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21246 : { 3844 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21247 : { 3844 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21248 : { 3844 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21249 : { 3844 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21250 : { 3844 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21251 : { 3844 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21252 : { 3844 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21253 : { 3844 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21254 : { 3844 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21255 : { 3844 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21256 : { 3844 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21257 : { 3844 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21258 : { 3844 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21259 : { 3844 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21260 : { 3844 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21261 : { 3844 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21262 : { 3844 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21263 : { 3861 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21264 : { 3861 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21265 : { 3861 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21266 : { 3861 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21267 : { 3861 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21268 : { 3861 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21269 : { 3861 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21270 : { 3861 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21271 : { 3861 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21272 : { 3861 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21273 : { 3861 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21274 : { 3861 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21275 : { 3861 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21276 : { 3861 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21277 : { 3861 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21278 : { 3861 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21279 : { 3861 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21280 : { 3861 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21281 : { 3861 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21282 : { 3861 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21283 : { 3877 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21284 : { 3877 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21285 : { 3877 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21286 : { 3877 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21287 : { 3877 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21288 : { 3877 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21289 : { 3877 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21290 : { 3877 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21291 : { 3877 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21292 : { 3877 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21293 : { 3877 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21294 : { 3877 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21295 : { 3877 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21296 : { 3877 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21297 : { 3877 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21298 : { 3877 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21299 : { 3877 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21300 : { 3877 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21301 : { 3877 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21302 : { 3877 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21303 : { 3896 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21304 : { 3896 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21305 : { 3896 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21306 : { 3896 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21307 : { 3896 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21308 : { 3896 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21309 : { 3896 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21310 : { 3896 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21311 : { 3896 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21312 : { 3896 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21313 : { 3896 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21314 : { 3896 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21315 : { 3896 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21316 : { 3896 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21317 : { 3896 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21318 : { 3896 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21319 : { 3896 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21320 : { 3896 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21321 : { 3896 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21322 : { 3896 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21323 : { 3917 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21324 : { 3917 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21325 : { 3917 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21326 : { 3917 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21327 : { 3917 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21328 : { 3917 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21329 : { 3917 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21330 : { 3917 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21331 : { 3917 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21332 : { 3917 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21333 : { 3917 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21334 : { 3917 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21335 : { 3917 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21336 : { 3917 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21337 : { 3917 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21338 : { 3917 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21339 : { 3917 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21340 : { 3917 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21341 : { 3917 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21342 : { 3917 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21343 : { 3935 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21344 : { 3935 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21345 : { 3935 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21346 : { 3935 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21347 : { 3935 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21348 : { 3935 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21349 : { 3935 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21350 : { 3935 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21351 : { 3935 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21352 : { 3935 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21353 : { 3935 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21354 : { 3935 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21355 : { 3935 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21356 : { 3935 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21357 : { 3935 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21358 : { 3935 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21359 : { 3935 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21360 : { 3935 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21361 : { 3935 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21362 : { 3935 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21363 : { 3951 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21364 : { 3951 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21365 : { 3951 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21366 : { 3951 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21367 : { 3951 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21368 : { 3951 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21369 : { 3951 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21370 : { 3951 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21371 : { 3951 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21372 : { 3951 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21373 : { 3951 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21374 : { 3951 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21375 : { 3951 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21376 : { 3951 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21377 : { 3951 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21378 : { 3951 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21379 : { 3951 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21380 : { 3951 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21381 : { 3951 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21382 : { 3951 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21383 : { 3969 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21384 : { 3969 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21385 : { 3969 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21386 : { 3969 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21387 : { 3969 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21388 : { 3969 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21389 : { 3969 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21390 : { 3969 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21391 : { 3969 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21392 : { 3969 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21393 : { 3969 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21394 : { 3969 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21395 : { 3969 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21396 : { 3969 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21397 : { 3969 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21398 : { 3969 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21399 : { 3969 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21400 : { 3969 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21401 : { 3969 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21402 : { 3969 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21403 : { 3984 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21404 : { 3984 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21405 : { 3984 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21406 : { 3984 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21407 : { 3984 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21408 : { 3984 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21409 : { 3984 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21410 : { 3984 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21411 : { 3984 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21412 : { 3984 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21413 : { 3984 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21414 : { 3984 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21415 : { 3984 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21416 : { 3984 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21417 : { 3984 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21418 : { 3984 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21419 : { 3984 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21420 : { 3984 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21421 : { 3984 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21422 : { 3984 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21423 : { 4002 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21424 : { 4002 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21425 : { 4002 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21426 : { 4002 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21427 : { 4002 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21428 : { 4002 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21429 : { 4002 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21430 : { 4002 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21431 : { 4002 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21432 : { 4002 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21433 : { 4002 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21434 : { 4002 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21435 : { 4002 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21436 : { 4002 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21437 : { 4002 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21438 : { 4002 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21439 : { 4002 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21440 : { 4002 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21441 : { 4002 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21442 : { 4002 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21443 : { 4022 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21444 : { 4022 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21445 : { 4022 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21446 : { 4022 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21447 : { 4022 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21448 : { 4022 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21449 : { 4022 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21450 : { 4022 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21451 : { 4022 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21452 : { 4022 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21453 : { 4022 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21454 : { 4022 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21455 : { 4022 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21456 : { 4022 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21457 : { 4022 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21458 : { 4022 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21459 : { 4022 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21460 : { 4022 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21461 : { 4022 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21462 : { 4022 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21463 : { 4039 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21464 : { 4039 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21465 : { 4039 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21466 : { 4039 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21467 : { 4039 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21468 : { 4039 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21469 : { 4039 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21470 : { 4039 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21471 : { 4039 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21472 : { 4039 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21473 : { 4039 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21474 : { 4039 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21475 : { 4039 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21476 : { 4039 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21477 : { 4039 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21478 : { 4039 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21479 : { 4039 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21480 : { 4039 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21481 : { 4039 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21482 : { 4039 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21483 : { 4054 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21484 : { 4054 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21485 : { 4054 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21486 : { 4054 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21487 : { 4054 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21488 : { 4054 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21489 : { 4054 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21490 : { 4054 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21491 : { 4054 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21492 : { 4054 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21493 : { 4054 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21494 : { 4054 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21495 : { 4054 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21496 : { 4054 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21497 : { 4054 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21498 : { 4054 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21499 : { 4054 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21500 : { 4054 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21501 : { 4054 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21502 : { 4054 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21503 : { 4071 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21504 : { 4071 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21505 : { 4071 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21506 : { 4071 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21507 : { 4071 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21508 : { 4071 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21509 : { 4071 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21510 : { 4071 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21511 : { 4071 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21512 : { 4071 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21513 : { 4071 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21514 : { 4071 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21515 : { 4071 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21516 : { 4071 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21517 : { 4071 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21518 : { 4071 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21519 : { 4071 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21520 : { 4071 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21521 : { 4071 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21522 : { 4071 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21523 : { 4087 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21524 : { 4087 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21525 : { 4087 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21526 : { 4087 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21527 : { 4087 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21528 : { 4087 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21529 : { 4087 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21530 : { 4087 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21531 : { 4087 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21532 : { 4087 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21533 : { 4087 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21534 : { 4087 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21535 : { 4087 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21536 : { 4087 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21537 : { 4087 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21538 : { 4087 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21539 : { 4087 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21540 : { 4087 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21541 : { 4087 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21542 : { 4087 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21543 : { 4105 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V1_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21544 : { 4105 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V1_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21545 : { 4105 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V1_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21546 : { 4105 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V1_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21547 : { 4105 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V1_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21548 : { 4105 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V4_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21549 : { 4105 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V4_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21550 : { 4105 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V4_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21551 : { 4105 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V4_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21552 : { 4105 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V4_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21553 : { 4105 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V2_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21554 : { 4105 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V2_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21555 : { 4105 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V2_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21556 : { 4105 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V2_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21557 : { 4105 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V2_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21558 : { 4105 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V3_V1, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128 }, },
21559 : { 4105 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V3_V4, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128 }, },
21560 : { 4105 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V3_V8, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128 }, },
21561 : { 4105 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V3_V16, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128 }, },
21562 : { 4105 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V3_V2, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Imm1_8__Reg1_9__Reg1_10__Reg1_11, Feature_isGCN, { MCK_VReg_96, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128 }, },
21563 : { 4120 /* s_abs_i32 */, AMDGPU::S_ABS_I32_si, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32 }, },
21564 : { 4120 /* s_abs_i32 */, AMDGPU::S_ABS_I32_vi, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32 }, },
21565 : { 4130 /* s_absdiff_i32 */, AMDGPU::S_ABSDIFF_I32_si, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21566 : { 4130 /* s_absdiff_i32 */, AMDGPU::S_ABSDIFF_I32_vi, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21567 : { 4144 /* s_add_i32 */, AMDGPU::S_ADD_I32_si, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21568 : { 4144 /* s_add_i32 */, AMDGPU::S_ADD_I32_vi, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21569 : { 4154 /* s_add_u32 */, AMDGPU::S_ADD_U32_si, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21570 : { 4154 /* s_add_u32 */, AMDGPU::S_ADD_U32_vi, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21571 : { 4164 /* s_addc_u32 */, AMDGPU::S_ADDC_U32_si, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21572 : { 4164 /* s_addc_u32 */, AMDGPU::S_ADDC_U32_vi, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21573 : { 4175 /* s_addk_i32 */, AMDGPU::S_ADDK_I32_si, Convert__Reg1_0__Tie0__Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_Imm }, },
21574 : { 4175 /* s_addk_i32 */, AMDGPU::S_ADDK_I32_vi, Convert__Reg1_0__Tie0__Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_Imm }, },
21575 : { 4186 /* s_and_b32 */, AMDGPU::S_AND_B32_si, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21576 : { 4186 /* s_and_b32 */, AMDGPU::S_AND_B32_vi, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21577 : { 4196 /* s_and_b64 */, AMDGPU::S_AND_B64_si, Convert__Reg1_0__SSrc641_1__SSrc641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64, MCK_SSrc64 }, },
21578 : { 4196 /* s_and_b64 */, AMDGPU::S_AND_B64_vi, Convert__Reg1_0__SSrc641_1__SSrc641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64, MCK_SSrc64 }, },
21579 : { 4206 /* s_and_saveexec_b64 */, AMDGPU::S_AND_SAVEEXEC_B64_si, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64 }, },
21580 : { 4206 /* s_and_saveexec_b64 */, AMDGPU::S_AND_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64 }, },
21581 : { 4225 /* s_andn2_b32 */, AMDGPU::S_ANDN2_B32_si, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21582 : { 4225 /* s_andn2_b32 */, AMDGPU::S_ANDN2_B32_vi, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21583 : { 4237 /* s_andn2_b64 */, AMDGPU::S_ANDN2_B64_si, Convert__Reg1_0__SSrc641_1__SSrc641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64, MCK_SSrc64 }, },
21584 : { 4237 /* s_andn2_b64 */, AMDGPU::S_ANDN2_B64_vi, Convert__Reg1_0__SSrc641_1__SSrc641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64, MCK_SSrc64 }, },
21585 : { 4249 /* s_andn2_saveexec_b64 */, AMDGPU::S_ANDN2_SAVEEXEC_B64_si, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64 }, },
21586 : { 4249 /* s_andn2_saveexec_b64 */, AMDGPU::S_ANDN2_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64 }, },
21587 : { 4270 /* s_ashr_i32 */, AMDGPU::S_ASHR_I32_si, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21588 : { 4270 /* s_ashr_i32 */, AMDGPU::S_ASHR_I32_vi, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21589 : { 4281 /* s_ashr_i64 */, AMDGPU::S_ASHR_I64_si, Convert__Reg1_0__SSrc641_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64, MCK_SSrc32 }, },
21590 : { 4281 /* s_ashr_i64 */, AMDGPU::S_ASHR_I64_vi, Convert__Reg1_0__SSrc641_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64, MCK_SSrc32 }, },
21591 : { 4292 /* s_barrier */, AMDGPU::S_BARRIER, Convert_NoOperands, Feature_isGCN, { }, },
21592 : { 4302 /* s_bcnt0_i32_b32 */, AMDGPU::S_BCNT0_I32_B32_si, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32 }, },
21593 : { 4302 /* s_bcnt0_i32_b32 */, AMDGPU::S_BCNT0_I32_B32_vi, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32 }, },
21594 : { 4318 /* s_bcnt0_i32_b64 */, AMDGPU::S_BCNT0_I32_B64_si, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc64 }, },
21595 : { 4318 /* s_bcnt0_i32_b64 */, AMDGPU::S_BCNT0_I32_B64_vi, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc64 }, },
21596 : { 4334 /* s_bcnt1_i32_b32 */, AMDGPU::S_BCNT1_I32_B32_si, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32 }, },
21597 : { 4334 /* s_bcnt1_i32_b32 */, AMDGPU::S_BCNT1_I32_B32_vi, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32 }, },
21598 : { 4350 /* s_bcnt1_i32_b64 */, AMDGPU::S_BCNT1_I32_B64_si, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc64 }, },
21599 : { 4350 /* s_bcnt1_i32_b64 */, AMDGPU::S_BCNT1_I32_B64_vi, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc64 }, },
21600 : { 4366 /* s_bfe_i32 */, AMDGPU::S_BFE_I32_si, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21601 : { 4366 /* s_bfe_i32 */, AMDGPU::S_BFE_I32_vi, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21602 : { 4376 /* s_bfe_i64 */, AMDGPU::S_BFE_I64_si, Convert__Reg1_0__SSrc641_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64, MCK_SSrc32 }, },
21603 : { 4376 /* s_bfe_i64 */, AMDGPU::S_BFE_I64_vi, Convert__Reg1_0__SSrc641_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64, MCK_SSrc32 }, },
21604 : { 4386 /* s_bfe_u32 */, AMDGPU::S_BFE_U32_si, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21605 : { 4386 /* s_bfe_u32 */, AMDGPU::S_BFE_U32_vi, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21606 : { 4396 /* s_bfe_u64 */, AMDGPU::S_BFE_U64_si, Convert__Reg1_0__SSrc641_1__SSrc641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64, MCK_SSrc64 }, },
21607 : { 4396 /* s_bfe_u64 */, AMDGPU::S_BFE_U64_vi, Convert__Reg1_0__SSrc641_1__SSrc641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64, MCK_SSrc64 }, },
21608 : { 4406 /* s_bfm_b32 */, AMDGPU::S_BFM_B32_si, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21609 : { 4406 /* s_bfm_b32 */, AMDGPU::S_BFM_B32_vi, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21610 : { 4416 /* s_bfm_b64 */, AMDGPU::S_BFM_B64_si, Convert__Reg1_0__SSrc641_1__SSrc641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64, MCK_SSrc64 }, },
21611 : { 4416 /* s_bfm_b64 */, AMDGPU::S_BFM_B64_vi, Convert__Reg1_0__SSrc641_1__SSrc641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64, MCK_SSrc64 }, },
21612 : { 4426 /* s_bitset0_b32 */, AMDGPU::S_BITSET0_B32_si, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32 }, },
21613 : { 4426 /* s_bitset0_b32 */, AMDGPU::S_BITSET0_B32_vi, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32 }, },
21614 : { 4440 /* s_bitset0_b64 */, AMDGPU::S_BITSET0_B64_si, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64 }, },
21615 : { 4440 /* s_bitset0_b64 */, AMDGPU::S_BITSET0_B64_vi, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64 }, },
21616 : { 4454 /* s_bitset1_b32 */, AMDGPU::S_BITSET1_B32_si, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32 }, },
21617 : { 4454 /* s_bitset1_b32 */, AMDGPU::S_BITSET1_B32_vi, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32 }, },
21618 : { 4468 /* s_bitset1_b64 */, AMDGPU::S_BITSET1_B64_si, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64 }, },
21619 : { 4468 /* s_bitset1_b64 */, AMDGPU::S_BITSET1_B64_vi, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64 }, },
21620 : { 4482 /* s_branch */, AMDGPU::S_BRANCH, Convert__SoppBrTarget1_0, Feature_isGCN, { MCK_SoppBrTarget }, },
21621 : { 4491 /* s_brev_b32 */, AMDGPU::S_BREV_B32_si, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32 }, },
21622 : { 4491 /* s_brev_b32 */, AMDGPU::S_BREV_B32_vi, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32 }, },
21623 : { 4502 /* s_brev_b64 */, AMDGPU::S_BREV_B64_si, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64 }, },
21624 : { 4502 /* s_brev_b64 */, AMDGPU::S_BREV_B64_vi, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64 }, },
21625 : { 4513 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_SGPR_32, MCK_SReg_128, MCK_SReg_32 }, },
21626 : { 4513 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_SGPR_32, MCK_SReg_128, MCK_SReg_32 }, },
21627 : { 4513 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_IMM_si, Convert__Reg1_0__Reg1_1__Imm1_2, Feature_isGCN|Feature_isSICI, { MCK_SGPR_32, MCK_SReg_128, MCK_Imm }, },
21628 : { 4513 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_IMM_vi, Convert__Reg1_0__Reg1_1__Imm1_2, Feature_isGCN|Feature_isVI, { MCK_SGPR_32, MCK_SReg_128, MCK_Imm }, },
21629 : { 4533 /* s_buffer_load_dwordx16 */, AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_512, MCK_SReg_128, MCK_SReg_32 }, },
21630 : { 4533 /* s_buffer_load_dwordx16 */, AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_SReg_512, MCK_SReg_128, MCK_SReg_32 }, },
21631 : { 4533 /* s_buffer_load_dwordx16 */, AMDGPU::S_BUFFER_LOAD_DWORDX16_IMM_si, Convert__Reg1_0__Reg1_1__Imm1_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_512, MCK_SReg_128, MCK_Imm }, },
21632 : { 4533 /* s_buffer_load_dwordx16 */, AMDGPU::S_BUFFER_LOAD_DWORDX16_IMM_vi, Convert__Reg1_0__Reg1_1__Imm1_2, Feature_isGCN|Feature_isVI, { MCK_SReg_512, MCK_SReg_128, MCK_Imm }, },
21633 : { 4556 /* s_buffer_load_dwordx2 */, AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SReg_128, MCK_SReg_32 }, },
21634 : { 4556 /* s_buffer_load_dwordx2 */, AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SReg_128, MCK_SReg_32 }, },
21635 : { 4556 /* s_buffer_load_dwordx2 */, AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM_si, Convert__Reg1_0__Reg1_1__Imm1_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SReg_128, MCK_Imm }, },
21636 : { 4556 /* s_buffer_load_dwordx2 */, AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM_vi, Convert__Reg1_0__Reg1_1__Imm1_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SReg_128, MCK_Imm }, },
21637 : { 4578 /* s_buffer_load_dwordx4 */, AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32 }, },
21638 : { 4578 /* s_buffer_load_dwordx4 */, AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32 }, },
21639 : { 4578 /* s_buffer_load_dwordx4 */, AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM_si, Convert__Reg1_0__Reg1_1__Imm1_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_128, MCK_SReg_128, MCK_Imm }, },
21640 : { 4578 /* s_buffer_load_dwordx4 */, AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM_vi, Convert__Reg1_0__Reg1_1__Imm1_2, Feature_isGCN|Feature_isVI, { MCK_SReg_128, MCK_SReg_128, MCK_Imm }, },
21641 : { 4600 /* s_buffer_load_dwordx8 */, AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_256, MCK_SReg_128, MCK_SReg_32 }, },
21642 : { 4600 /* s_buffer_load_dwordx8 */, AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_SReg_256, MCK_SReg_128, MCK_SReg_32 }, },
21643 : { 4600 /* s_buffer_load_dwordx8 */, AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM_si, Convert__Reg1_0__Reg1_1__Imm1_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_256, MCK_SReg_128, MCK_Imm }, },
21644 : { 4600 /* s_buffer_load_dwordx8 */, AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM_vi, Convert__Reg1_0__Reg1_1__Imm1_2, Feature_isGCN|Feature_isVI, { MCK_SReg_256, MCK_SReg_128, MCK_Imm }, },
21645 : { 4622 /* s_cbranch_execnz */, AMDGPU::S_CBRANCH_EXECNZ, Convert__SoppBrTarget1_0__imm_95_0, Feature_isGCN, { MCK_SoppBrTarget }, },
21646 : { 4639 /* s_cbranch_execz */, AMDGPU::S_CBRANCH_EXECZ, Convert__SoppBrTarget1_0__imm_95_0, Feature_isGCN, { MCK_SoppBrTarget }, },
21647 : { 4655 /* s_cbranch_g_fork */, AMDGPU::S_CBRANCH_G_FORK_si, Convert__Reg1_0__Reg1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SReg_64 }, },
21648 : { 4655 /* s_cbranch_g_fork */, AMDGPU::S_CBRANCH_G_FORK_vi, Convert__Reg1_0__Reg1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SReg_64 }, },
21649 : { 4672 /* s_cbranch_i_fork */, AMDGPU::S_CBRANCH_I_FORK_si, Convert__Reg1_0__Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_Imm }, },
21650 : { 4672 /* s_cbranch_i_fork */, AMDGPU::S_CBRANCH_I_FORK_vi, Convert__Reg1_0__Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_Imm }, },
21651 : { 4689 /* s_cbranch_join */, AMDGPU::S_CBRANCH_JOIN_si, Convert__Reg1_0, Feature_isGCN|Feature_isSICI, { MCK_SReg_64 }, },
21652 : { 4689 /* s_cbranch_join */, AMDGPU::S_CBRANCH_JOIN_vi, Convert__Reg1_0, Feature_isGCN|Feature_isVI, { MCK_SReg_64 }, },
21653 : { 4704 /* s_cbranch_scc0 */, AMDGPU::S_CBRANCH_SCC0, Convert__SoppBrTarget1_0__imm_95_0, Feature_isGCN, { MCK_SoppBrTarget }, },
21654 : { 4719 /* s_cbranch_scc1 */, AMDGPU::S_CBRANCH_SCC1, Convert__SoppBrTarget1_0__imm_95_0, Feature_isGCN, { MCK_SoppBrTarget }, },
21655 : { 4734 /* s_cbranch_vccnz */, AMDGPU::S_CBRANCH_VCCNZ, Convert__SoppBrTarget1_0__imm_95_0, Feature_isGCN, { MCK_SoppBrTarget }, },
21656 : { 4750 /* s_cbranch_vccz */, AMDGPU::S_CBRANCH_VCCZ, Convert__SoppBrTarget1_0__imm_95_0, Feature_isGCN, { MCK_SoppBrTarget }, },
21657 : { 4765 /* s_cmov_b32 */, AMDGPU::S_CMOV_B32_si, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32 }, },
21658 : { 4765 /* s_cmov_b32 */, AMDGPU::S_CMOV_B32_vi, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32 }, },
21659 : { 4776 /* s_cmov_b64 */, AMDGPU::S_CMOV_B64_si, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64 }, },
21660 : { 4776 /* s_cmov_b64 */, AMDGPU::S_CMOV_B64_vi, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64 }, },
21661 : { 4787 /* s_cmovk_i32 */, AMDGPU::S_CMOVK_I32_si, Convert__Reg1_0__Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_Imm }, },
21662 : { 4787 /* s_cmovk_i32 */, AMDGPU::S_CMOVK_I32_vi, Convert__Reg1_0__Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_Imm }, },
21663 : { 4799 /* s_cmp_eq_i32 */, AMDGPU::S_CMP_EQ_I32, Convert__imm_95_0__SSrc321_0__SSrc321_1, Feature_isGCN, { MCK_SSrc32, MCK_SSrc32 }, },
21664 : { 4812 /* s_cmp_eq_u32 */, AMDGPU::S_CMP_EQ_U32, Convert__imm_95_0__SSrc321_0__SSrc321_1, Feature_isGCN, { MCK_SSrc32, MCK_SSrc32 }, },
21665 : { 4825 /* s_cmp_ge_i32 */, AMDGPU::S_CMP_GE_I32, Convert__imm_95_0__SSrc321_0__SSrc321_1, Feature_isGCN, { MCK_SSrc32, MCK_SSrc32 }, },
21666 : { 4838 /* s_cmp_ge_u32 */, AMDGPU::S_CMP_GE_U32, Convert__imm_95_0__SSrc321_0__SSrc321_1, Feature_isGCN, { MCK_SSrc32, MCK_SSrc32 }, },
21667 : { 4851 /* s_cmp_gt_i32 */, AMDGPU::S_CMP_GT_I32, Convert__imm_95_0__SSrc321_0__SSrc321_1, Feature_isGCN, { MCK_SSrc32, MCK_SSrc32 }, },
21668 : { 4864 /* s_cmp_gt_u32 */, AMDGPU::S_CMP_GT_U32, Convert__imm_95_0__SSrc321_0__SSrc321_1, Feature_isGCN, { MCK_SSrc32, MCK_SSrc32 }, },
21669 : { 4877 /* s_cmp_le_i32 */, AMDGPU::S_CMP_LE_I32, Convert__imm_95_0__SSrc321_0__SSrc321_1, Feature_isGCN, { MCK_SSrc32, MCK_SSrc32 }, },
21670 : { 4890 /* s_cmp_le_u32 */, AMDGPU::S_CMP_LE_U32, Convert__imm_95_0__SSrc321_0__SSrc321_1, Feature_isGCN, { MCK_SSrc32, MCK_SSrc32 }, },
21671 : { 4903 /* s_cmp_lg_i32 */, AMDGPU::S_CMP_LG_I32, Convert__imm_95_0__SSrc321_0__SSrc321_1, Feature_isGCN, { MCK_SSrc32, MCK_SSrc32 }, },
21672 : { 4916 /* s_cmp_lg_u32 */, AMDGPU::S_CMP_LG_U32, Convert__imm_95_0__SSrc321_0__SSrc321_1, Feature_isGCN, { MCK_SSrc32, MCK_SSrc32 }, },
21673 : { 4929 /* s_cmp_lt_i32 */, AMDGPU::S_CMP_LT_I32, Convert__imm_95_0__SSrc321_0__SSrc321_1, Feature_isGCN, { MCK_SSrc32, MCK_SSrc32 }, },
21674 : { 4942 /* s_cmp_lt_u32 */, AMDGPU::S_CMP_LT_U32, Convert__imm_95_0__SSrc321_0__SSrc321_1, Feature_isGCN, { MCK_SSrc32, MCK_SSrc32 }, },
21675 : { 4955 /* s_cmpk_eq_i32 */, AMDGPU::S_CMPK_EQ_I32_si, Convert__imm_95_0__Reg1_0__Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_Imm }, },
21676 : { 4955 /* s_cmpk_eq_i32 */, AMDGPU::S_CMPK_EQ_I32_vi, Convert__imm_95_0__Reg1_0__Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_Imm }, },
21677 : { 4969 /* s_cmpk_eq_u32 */, AMDGPU::S_CMPK_EQ_U32_si, Convert__imm_95_0__Reg1_0__Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_Imm }, },
21678 : { 4969 /* s_cmpk_eq_u32 */, AMDGPU::S_CMPK_EQ_U32_vi, Convert__imm_95_0__Reg1_0__Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_Imm }, },
21679 : { 4983 /* s_cmpk_ge_i32 */, AMDGPU::S_CMPK_GE_I32_si, Convert__imm_95_0__Reg1_0__Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_Imm }, },
21680 : { 4983 /* s_cmpk_ge_i32 */, AMDGPU::S_CMPK_GE_I32_vi, Convert__imm_95_0__Reg1_0__Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_Imm }, },
21681 : { 4997 /* s_cmpk_ge_u32 */, AMDGPU::S_CMPK_GE_U32_si, Convert__imm_95_0__Reg1_0__Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_Imm }, },
21682 : { 4997 /* s_cmpk_ge_u32 */, AMDGPU::S_CMPK_GE_U32_vi, Convert__imm_95_0__Reg1_0__Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_Imm }, },
21683 : { 5011 /* s_cmpk_gt_i32 */, AMDGPU::S_CMPK_GT_I32_si, Convert__imm_95_0__Reg1_0__Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_Imm }, },
21684 : { 5011 /* s_cmpk_gt_i32 */, AMDGPU::S_CMPK_GT_I32_vi, Convert__imm_95_0__Reg1_0__Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_Imm }, },
21685 : { 5025 /* s_cmpk_gt_u32 */, AMDGPU::S_CMPK_GT_U32_si, Convert__imm_95_0__Reg1_0__Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_Imm }, },
21686 : { 5025 /* s_cmpk_gt_u32 */, AMDGPU::S_CMPK_GT_U32_vi, Convert__imm_95_0__Reg1_0__Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_Imm }, },
21687 : { 5039 /* s_cmpk_le_i32 */, AMDGPU::S_CMPK_LE_I32_si, Convert__imm_95_0__Reg1_0__Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_Imm }, },
21688 : { 5039 /* s_cmpk_le_i32 */, AMDGPU::S_CMPK_LE_I32_vi, Convert__imm_95_0__Reg1_0__Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_Imm }, },
21689 : { 5053 /* s_cmpk_le_u32 */, AMDGPU::S_CMPK_LE_U32_si, Convert__imm_95_0__Reg1_0__Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_Imm }, },
21690 : { 5053 /* s_cmpk_le_u32 */, AMDGPU::S_CMPK_LE_U32_vi, Convert__imm_95_0__Reg1_0__Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_Imm }, },
21691 : { 5067 /* s_cmpk_lg_i32 */, AMDGPU::S_CMPK_LG_I32_si, Convert__imm_95_0__Reg1_0__Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_Imm }, },
21692 : { 5067 /* s_cmpk_lg_i32 */, AMDGPU::S_CMPK_LG_I32_vi, Convert__imm_95_0__Reg1_0__Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_Imm }, },
21693 : { 5081 /* s_cmpk_lg_u32 */, AMDGPU::S_CMPK_LG_U32_si, Convert__imm_95_0__Reg1_0__Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_Imm }, },
21694 : { 5081 /* s_cmpk_lg_u32 */, AMDGPU::S_CMPK_LG_U32_vi, Convert__imm_95_0__Reg1_0__Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_Imm }, },
21695 : { 5095 /* s_cmpk_lt_i32 */, AMDGPU::S_CMPK_LT_I32_si, Convert__imm_95_0__Reg1_0__Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_Imm }, },
21696 : { 5095 /* s_cmpk_lt_i32 */, AMDGPU::S_CMPK_LT_I32_vi, Convert__imm_95_0__Reg1_0__Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_Imm }, },
21697 : { 5109 /* s_cmpk_lt_u32 */, AMDGPU::S_CMPK_LT_U32_si, Convert__imm_95_0__Reg1_0__Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_Imm }, },
21698 : { 5109 /* s_cmpk_lt_u32 */, AMDGPU::S_CMPK_LT_U32_vi, Convert__imm_95_0__Reg1_0__Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_Imm }, },
21699 : { 5123 /* s_cselect_b32 */, AMDGPU::S_CSELECT_B32_si, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21700 : { 5123 /* s_cselect_b32 */, AMDGPU::S_CSELECT_B32_vi, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21701 : { 5137 /* s_cselect_b64 */, AMDGPU::S_CSELECT_B64_si, Convert__Reg1_0__SSrc641_1__SSrc641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64, MCK_SSrc64 }, },
21702 : { 5137 /* s_cselect_b64 */, AMDGPU::S_CSELECT_B64_vi, Convert__Reg1_0__SSrc641_1__SSrc641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64, MCK_SSrc64 }, },
21703 : { 5151 /* s_decperflevel */, AMDGPU::S_DECPERFLEVEL, Convert__Imm1_0, Feature_isGCN, { MCK_Imm }, },
21704 : { 5166 /* s_endpgm */, AMDGPU::S_ENDPGM, Convert_NoOperands, Feature_isGCN, { }, },
21705 : { 5175 /* s_ff0_i32_b32 */, AMDGPU::S_FF0_I32_B32_si, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32 }, },
21706 : { 5175 /* s_ff0_i32_b32 */, AMDGPU::S_FF0_I32_B32_vi, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32 }, },
21707 : { 5189 /* s_ff0_i32_b64 */, AMDGPU::S_FF0_I32_B64_si, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc64 }, },
21708 : { 5189 /* s_ff0_i32_b64 */, AMDGPU::S_FF0_I32_B64_vi, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc64 }, },
21709 : { 5203 /* s_ff1_i32_b32 */, AMDGPU::S_FF1_I32_B32_si, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32 }, },
21710 : { 5203 /* s_ff1_i32_b32 */, AMDGPU::S_FF1_I32_B32_vi, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32 }, },
21711 : { 5217 /* s_ff1_i32_b64 */, AMDGPU::S_FF1_I32_B64_si, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc64 }, },
21712 : { 5217 /* s_ff1_i32_b64 */, AMDGPU::S_FF1_I32_B64_vi, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc64 }, },
21713 : { 5231 /* s_flbit_i32 */, AMDGPU::S_FLBIT_I32_si, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32 }, },
21714 : { 5231 /* s_flbit_i32 */, AMDGPU::S_FLBIT_I32_vi, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32 }, },
21715 : { 5243 /* s_flbit_i32_b32 */, AMDGPU::S_FLBIT_I32_B32_si, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32 }, },
21716 : { 5243 /* s_flbit_i32_b32 */, AMDGPU::S_FLBIT_I32_B32_vi, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32 }, },
21717 : { 5259 /* s_flbit_i32_b64 */, AMDGPU::S_FLBIT_I32_B64_si, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc64 }, },
21718 : { 5259 /* s_flbit_i32_b64 */, AMDGPU::S_FLBIT_I32_B64_vi, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc64 }, },
21719 : { 5275 /* s_flbit_i32_i64 */, AMDGPU::S_FLBIT_I32_I64_si, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc64 }, },
21720 : { 5275 /* s_flbit_i32_i64 */, AMDGPU::S_FLBIT_I32_I64_vi, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc64 }, },
21721 : { 5291 /* s_getpc_b64 */, AMDGPU::S_GETPC_B64_si, Convert__Reg1_0, Feature_isGCN|Feature_isSICI, { MCK_SReg_64 }, },
21722 : { 5291 /* s_getpc_b64 */, AMDGPU::S_GETPC_B64_vi, Convert__Reg1_0, Feature_isGCN|Feature_isVI, { MCK_SReg_64 }, },
21723 : { 5303 /* s_getreg_b32 */, AMDGPU::S_GETREG_B32_si, Convert__Reg1_0__Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_Imm }, },
21724 : { 5303 /* s_getreg_b32 */, AMDGPU::S_GETREG_B32_vi, Convert__Reg1_0__Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_Imm }, },
21725 : { 5316 /* s_icache_inv */, AMDGPU::S_ICACHE_INV, Convert_NoOperands, Feature_isGCN, { }, },
21726 : { 5329 /* s_incperflevel */, AMDGPU::S_INCPERFLEVEL, Convert__Imm1_0, Feature_isGCN, { MCK_Imm }, },
21727 : { 5344 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_SGPR_32, MCK_SReg_64, MCK_SReg_32 }, },
21728 : { 5344 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_SGPR_32, MCK_SReg_64, MCK_SReg_32 }, },
21729 : { 5344 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_IMM_si, Convert__Reg1_0__Reg1_1__Imm1_2, Feature_isGCN|Feature_isSICI, { MCK_SGPR_32, MCK_SReg_64, MCK_Imm }, },
21730 : { 5344 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_IMM_vi, Convert__Reg1_0__Reg1_1__Imm1_2, Feature_isGCN|Feature_isVI, { MCK_SGPR_32, MCK_SReg_64, MCK_Imm }, },
21731 : { 5357 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_512, MCK_SReg_64, MCK_SReg_32 }, },
21732 : { 5357 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_SReg_512, MCK_SReg_64, MCK_SReg_32 }, },
21733 : { 5357 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_IMM_si, Convert__Reg1_0__Reg1_1__Imm1_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_512, MCK_SReg_64, MCK_Imm }, },
21734 : { 5357 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_IMM_vi, Convert__Reg1_0__Reg1_1__Imm1_2, Feature_isGCN|Feature_isVI, { MCK_SReg_512, MCK_SReg_64, MCK_Imm }, },
21735 : { 5373 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SReg_64, MCK_SReg_32 }, },
21736 : { 5373 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SReg_64, MCK_SReg_32 }, },
21737 : { 5373 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_IMM_si, Convert__Reg1_0__Reg1_1__Imm1_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SReg_64, MCK_Imm }, },
21738 : { 5373 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_IMM_vi, Convert__Reg1_0__Reg1_1__Imm1_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SReg_64, MCK_Imm }, },
21739 : { 5388 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32 }, },
21740 : { 5388 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32 }, },
21741 : { 5388 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_IMM_si, Convert__Reg1_0__Reg1_1__Imm1_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_128, MCK_SReg_64, MCK_Imm }, },
21742 : { 5388 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_IMM_vi, Convert__Reg1_0__Reg1_1__Imm1_2, Feature_isGCN|Feature_isVI, { MCK_SReg_128, MCK_SReg_64, MCK_Imm }, },
21743 : { 5403 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_256, MCK_SReg_64, MCK_SReg_32 }, },
21744 : { 5403 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_SReg_256, MCK_SReg_64, MCK_SReg_32 }, },
21745 : { 5403 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_IMM_si, Convert__Reg1_0__Reg1_1__Imm1_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_256, MCK_SReg_64, MCK_Imm }, },
21746 : { 5403 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_IMM_vi, Convert__Reg1_0__Reg1_1__Imm1_2, Feature_isGCN|Feature_isVI, { MCK_SReg_256, MCK_SReg_64, MCK_Imm }, },
21747 : { 5418 /* s_lshl_b32 */, AMDGPU::S_LSHL_B32_si, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21748 : { 5418 /* s_lshl_b32 */, AMDGPU::S_LSHL_B32_vi, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21749 : { 5429 /* s_lshl_b64 */, AMDGPU::S_LSHL_B64_si, Convert__Reg1_0__SSrc641_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64, MCK_SSrc32 }, },
21750 : { 5429 /* s_lshl_b64 */, AMDGPU::S_LSHL_B64_vi, Convert__Reg1_0__SSrc641_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64, MCK_SSrc32 }, },
21751 : { 5440 /* s_lshr_b32 */, AMDGPU::S_LSHR_B32_si, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21752 : { 5440 /* s_lshr_b32 */, AMDGPU::S_LSHR_B32_vi, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21753 : { 5451 /* s_lshr_b64 */, AMDGPU::S_LSHR_B64_si, Convert__Reg1_0__SSrc641_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64, MCK_SSrc32 }, },
21754 : { 5451 /* s_lshr_b64 */, AMDGPU::S_LSHR_B64_vi, Convert__Reg1_0__SSrc641_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64, MCK_SSrc32 }, },
21755 : { 5462 /* s_max_i32 */, AMDGPU::S_MAX_I32_si, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21756 : { 5462 /* s_max_i32 */, AMDGPU::S_MAX_I32_vi, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21757 : { 5472 /* s_max_u32 */, AMDGPU::S_MAX_U32_si, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21758 : { 5472 /* s_max_u32 */, AMDGPU::S_MAX_U32_vi, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21759 : { 5482 /* s_min_i32 */, AMDGPU::S_MIN_I32_si, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21760 : { 5482 /* s_min_i32 */, AMDGPU::S_MIN_I32_vi, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21761 : { 5492 /* s_min_u32 */, AMDGPU::S_MIN_U32_si, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21762 : { 5492 /* s_min_u32 */, AMDGPU::S_MIN_U32_vi, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21763 : { 5502 /* s_mov_b32 */, AMDGPU::S_MOV_B32_si, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32 }, },
21764 : { 5502 /* s_mov_b32 */, AMDGPU::S_MOV_B32_vi, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32 }, },
21765 : { 5512 /* s_mov_b64 */, AMDGPU::S_MOV_B64_si, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64 }, },
21766 : { 5512 /* s_mov_b64 */, AMDGPU::S_MOV_B64_vi, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64 }, },
21767 : { 5522 /* s_mov_fed_b32 */, AMDGPU::S_MOV_FED_B32_si, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32 }, },
21768 : { 5522 /* s_mov_fed_b32 */, AMDGPU::S_MOV_FED_B32_vi, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32 }, },
21769 : { 5536 /* s_mov_regrd_b32 */, AMDGPU::S_MOV_REGRD_B32_si, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32 }, },
21770 : { 5536 /* s_mov_regrd_b32 */, AMDGPU::S_MOV_REGRD_B32_vi, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32 }, },
21771 : { 5552 /* s_movk_i32 */, AMDGPU::S_MOVK_I32_si, Convert__Reg1_0__Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_Imm }, },
21772 : { 5552 /* s_movk_i32 */, AMDGPU::S_MOVK_I32_vi, Convert__Reg1_0__Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_Imm }, },
21773 : { 5563 /* s_movreld_b32 */, AMDGPU::S_MOVRELD_B32_si, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32 }, },
21774 : { 5563 /* s_movreld_b32 */, AMDGPU::S_MOVRELD_B32_vi, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32 }, },
21775 : { 5577 /* s_movreld_b64 */, AMDGPU::S_MOVRELD_B64_si, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64 }, },
21776 : { 5577 /* s_movreld_b64 */, AMDGPU::S_MOVRELD_B64_vi, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64 }, },
21777 : { 5591 /* s_movrels_b32 */, AMDGPU::S_MOVRELS_B32_si, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32 }, },
21778 : { 5591 /* s_movrels_b32 */, AMDGPU::S_MOVRELS_B32_vi, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32 }, },
21779 : { 5605 /* s_movrels_b64 */, AMDGPU::S_MOVRELS_B64_si, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64 }, },
21780 : { 5605 /* s_movrels_b64 */, AMDGPU::S_MOVRELS_B64_vi, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64 }, },
21781 : { 5619 /* s_mul_i32 */, AMDGPU::S_MUL_I32_si, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21782 : { 5619 /* s_mul_i32 */, AMDGPU::S_MUL_I32_vi, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21783 : { 5629 /* s_mulk_i32 */, AMDGPU::S_MULK_I32_si, Convert__Reg1_0__Tie0__Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_Imm }, },
21784 : { 5629 /* s_mulk_i32 */, AMDGPU::S_MULK_I32_vi, Convert__Reg1_0__Tie0__Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_Imm }, },
21785 : { 5640 /* s_nand_b32 */, AMDGPU::S_NAND_B32_si, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21786 : { 5640 /* s_nand_b32 */, AMDGPU::S_NAND_B32_vi, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21787 : { 5651 /* s_nand_b64 */, AMDGPU::S_NAND_B64_si, Convert__Reg1_0__SSrc641_1__SSrc641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64, MCK_SSrc64 }, },
21788 : { 5651 /* s_nand_b64 */, AMDGPU::S_NAND_B64_vi, Convert__Reg1_0__SSrc641_1__SSrc641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64, MCK_SSrc64 }, },
21789 : { 5662 /* s_nand_saveexec_b64 */, AMDGPU::S_NAND_SAVEEXEC_B64_si, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64 }, },
21790 : { 5662 /* s_nand_saveexec_b64 */, AMDGPU::S_NAND_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64 }, },
21791 : { 5682 /* s_nop */, AMDGPU::S_NOP, Convert__Imm1_0, Feature_isGCN, { MCK_Imm }, },
21792 : { 5688 /* s_nor_b32 */, AMDGPU::S_NOR_B32_si, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21793 : { 5688 /* s_nor_b32 */, AMDGPU::S_NOR_B32_vi, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21794 : { 5698 /* s_nor_b64 */, AMDGPU::S_NOR_B64_si, Convert__Reg1_0__SSrc641_1__SSrc641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64, MCK_SSrc64 }, },
21795 : { 5698 /* s_nor_b64 */, AMDGPU::S_NOR_B64_vi, Convert__Reg1_0__SSrc641_1__SSrc641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64, MCK_SSrc64 }, },
21796 : { 5708 /* s_nor_saveexec_b64 */, AMDGPU::S_NOR_SAVEEXEC_B64_si, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64 }, },
21797 : { 5708 /* s_nor_saveexec_b64 */, AMDGPU::S_NOR_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64 }, },
21798 : { 5727 /* s_not_b32 */, AMDGPU::S_NOT_B32_si, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32 }, },
21799 : { 5727 /* s_not_b32 */, AMDGPU::S_NOT_B32_vi, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32 }, },
21800 : { 5737 /* s_not_b64 */, AMDGPU::S_NOT_B64_si, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64 }, },
21801 : { 5737 /* s_not_b64 */, AMDGPU::S_NOT_B64_vi, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64 }, },
21802 : { 5747 /* s_or_b32 */, AMDGPU::S_OR_B32_si, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21803 : { 5747 /* s_or_b32 */, AMDGPU::S_OR_B32_vi, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21804 : { 5756 /* s_or_b64 */, AMDGPU::S_OR_B64_si, Convert__Reg1_0__SSrc641_1__SSrc641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64, MCK_SSrc64 }, },
21805 : { 5756 /* s_or_b64 */, AMDGPU::S_OR_B64_vi, Convert__Reg1_0__SSrc641_1__SSrc641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64, MCK_SSrc64 }, },
21806 : { 5765 /* s_or_saveexec_b64 */, AMDGPU::S_OR_SAVEEXEC_B64_si, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64 }, },
21807 : { 5765 /* s_or_saveexec_b64 */, AMDGPU::S_OR_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64 }, },
21808 : { 5783 /* s_orn2_b32 */, AMDGPU::S_ORN2_B32_si, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21809 : { 5783 /* s_orn2_b32 */, AMDGPU::S_ORN2_B32_vi, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21810 : { 5794 /* s_orn2_b64 */, AMDGPU::S_ORN2_B64_si, Convert__Reg1_0__SSrc641_1__SSrc641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64, MCK_SSrc64 }, },
21811 : { 5794 /* s_orn2_b64 */, AMDGPU::S_ORN2_B64_vi, Convert__Reg1_0__SSrc641_1__SSrc641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64, MCK_SSrc64 }, },
21812 : { 5805 /* s_orn2_saveexec_b64 */, AMDGPU::S_ORN2_SAVEEXEC_B64_si, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64 }, },
21813 : { 5805 /* s_orn2_saveexec_b64 */, AMDGPU::S_ORN2_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64 }, },
21814 : { 5825 /* s_quadmask_b32 */, AMDGPU::S_QUADMASK_B32_si, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32 }, },
21815 : { 5825 /* s_quadmask_b32 */, AMDGPU::S_QUADMASK_B32_vi, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32 }, },
21816 : { 5840 /* s_quadmask_b64 */, AMDGPU::S_QUADMASK_B64_si, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64 }, },
21817 : { 5840 /* s_quadmask_b64 */, AMDGPU::S_QUADMASK_B64_vi, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64 }, },
21818 : { 5855 /* s_rfe_b64 */, AMDGPU::S_RFE_B64_si, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64 }, },
21819 : { 5855 /* s_rfe_b64 */, AMDGPU::S_RFE_B64_vi, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64 }, },
21820 : { 5865 /* s_sendmsg */, AMDGPU::S_SENDMSG, Convert__Imm1_0, Feature_isGCN, { MCK_Imm }, },
21821 : { 5875 /* s_sendmsghalt */, AMDGPU::S_SENDMSGHALT, Convert__Imm1_0, Feature_isGCN, { MCK_Imm }, },
21822 : { 5889 /* s_sethalt */, AMDGPU::S_SETHALT, Convert__Imm1_0, Feature_isGCN, { MCK_Imm }, },
21823 : { 5899 /* s_setpc_b64 */, AMDGPU::S_SETPC_B64_si, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64 }, },
21824 : { 5899 /* s_setpc_b64 */, AMDGPU::S_SETPC_B64_vi, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64 }, },
21825 : { 5911 /* s_setprio */, AMDGPU::S_SETPRIO, Convert__Imm1_0, Feature_isGCN, { MCK_Imm }, },
21826 : { 5921 /* s_setreg_b32 */, AMDGPU::S_SETREG_B32_si, Convert__Reg1_0__Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_Imm }, },
21827 : { 5921 /* s_setreg_b32 */, AMDGPU::S_SETREG_B32_vi, Convert__Reg1_0__Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_Imm }, },
21828 : { 5934 /* s_setreg_imm32_b32 */, AMDGPU::S_SETREG_IMM32_B32_si, Convert__Imm1_0__Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_Imm, MCK_Imm }, },
21829 : { 5934 /* s_setreg_imm32_b32 */, AMDGPU::S_SETREG_IMM32_B32_vi, Convert__Imm1_0__Imm1_1, Feature_isGCN|Feature_isVI, { MCK_Imm, MCK_Imm }, },
21830 : { 5953 /* s_sext_i32_i16 */, AMDGPU::S_SEXT_I32_I16_si, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32 }, },
21831 : { 5953 /* s_sext_i32_i16 */, AMDGPU::S_SEXT_I32_I16_vi, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32 }, },
21832 : { 5968 /* s_sext_i32_i8 */, AMDGPU::S_SEXT_I32_I8_si, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32 }, },
21833 : { 5968 /* s_sext_i32_i8 */, AMDGPU::S_SEXT_I32_I8_vi, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32 }, },
21834 : { 5982 /* s_sleep */, AMDGPU::S_SLEEP, Convert__Imm1_0, Feature_isGCN, { MCK_Imm }, },
21835 : { 5990 /* s_sub_i32 */, AMDGPU::S_SUB_I32_si, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21836 : { 5990 /* s_sub_i32 */, AMDGPU::S_SUB_I32_vi, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21837 : { 6000 /* s_sub_u32 */, AMDGPU::S_SUB_U32_si, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21838 : { 6000 /* s_sub_u32 */, AMDGPU::S_SUB_U32_vi, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21839 : { 6010 /* s_subb_u32 */, AMDGPU::S_SUBB_U32_si, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21840 : { 6010 /* s_subb_u32 */, AMDGPU::S_SUBB_U32_vi, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21841 : { 6021 /* s_swappc_b64 */, AMDGPU::S_SWAPPC_B64_si, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64 }, },
21842 : { 6021 /* s_swappc_b64 */, AMDGPU::S_SWAPPC_B64_vi, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64 }, },
21843 : { 6034 /* s_trap */, AMDGPU::S_TRAP, Convert__Imm1_0, Feature_isGCN, { MCK_Imm }, },
21844 : { 6041 /* s_ttracedata */, AMDGPU::S_TTRACEDATA, Convert_NoOperands, Feature_isGCN, { }, },
21845 : { 6054 /* s_waitcnt */, AMDGPU::S_WAITCNT, Convert__SWaitCnt1_0, Feature_isGCN, { MCK_SWaitCnt }, },
21846 : { 6064 /* s_wqm_b32 */, AMDGPU::S_WQM_B32_si, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32 }, },
21847 : { 6064 /* s_wqm_b32 */, AMDGPU::S_WQM_B32_vi, Convert__Reg1_0__SSrc321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32 }, },
21848 : { 6074 /* s_wqm_b64 */, AMDGPU::S_WQM_B64_si, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64 }, },
21849 : { 6074 /* s_wqm_b64 */, AMDGPU::S_WQM_B64_vi, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64 }, },
21850 : { 6084 /* s_xnor_b32 */, AMDGPU::S_XNOR_B32_si, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21851 : { 6084 /* s_xnor_b32 */, AMDGPU::S_XNOR_B32_vi, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21852 : { 6095 /* s_xnor_b64 */, AMDGPU::S_XNOR_B64_si, Convert__Reg1_0__SSrc641_1__SSrc641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64, MCK_SSrc64 }, },
21853 : { 6095 /* s_xnor_b64 */, AMDGPU::S_XNOR_B64_vi, Convert__Reg1_0__SSrc641_1__SSrc641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64, MCK_SSrc64 }, },
21854 : { 6106 /* s_xnor_saveexec_b64 */, AMDGPU::S_XNOR_SAVEEXEC_B64_si, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64 }, },
21855 : { 6106 /* s_xnor_saveexec_b64 */, AMDGPU::S_XNOR_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64 }, },
21856 : { 6126 /* s_xor_b32 */, AMDGPU::S_XOR_B32_si, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21857 : { 6126 /* s_xor_b32 */, AMDGPU::S_XOR_B32_vi, Convert__Reg1_0__SSrc321_1__SSrc321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrc32, MCK_SSrc32 }, },
21858 : { 6136 /* s_xor_b64 */, AMDGPU::S_XOR_B64_si, Convert__Reg1_0__SSrc641_1__SSrc641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64, MCK_SSrc64 }, },
21859 : { 6136 /* s_xor_b64 */, AMDGPU::S_XOR_B64_vi, Convert__Reg1_0__SSrc641_1__SSrc641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64, MCK_SSrc64 }, },
21860 : { 6146 /* s_xor_saveexec_b64 */, AMDGPU::S_XOR_SAVEEXEC_B64_si, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrc64 }, },
21861 : { 6146 /* s_xor_saveexec_b64 */, AMDGPU::S_XOR_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrc641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrc64 }, },
21862 : { 6165 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_si, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Reg1_8__Reg1_9__Imm1_10__Imm1_11__SCSrc321_12, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_128, MCK_Imm, MCK_Imm, MCK_SCSrc32 }, },
21863 : { 6165 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_vi, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Reg1_8__Reg1_9__Imm1_10__Imm1_11__SCSrc321_12, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_128, MCK_Imm, MCK_Imm, MCK_SCSrc32 }, },
21864 : { 6190 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_si, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Reg1_8__Reg1_9__Imm1_10__Imm1_11__SCSrc321_12, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_128, MCK_Imm, MCK_Imm, MCK_SCSrc32 }, },
21865 : { 6190 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_vi, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Reg1_8__Reg1_9__Imm1_10__Imm1_11__SCSrc321_12, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_128, MCK_Imm, MCK_Imm, MCK_SCSrc32 }, },
21866 : { 6213 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_si, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Reg1_8__Reg1_9__Imm1_10__Imm1_11__SCSrc321_12, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_128, MCK_Imm, MCK_Imm, MCK_SCSrc32 }, },
21867 : { 6213 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_vi, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Reg1_8__Reg1_9__Imm1_10__Imm1_11__SCSrc321_12, Feature_isGCN, { MCK_VReg_64, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_128, MCK_Imm, MCK_Imm, MCK_SCSrc32 }, },
21868 : { 6237 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_si, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Reg1_8__Reg1_9__Imm1_10__Imm1_11__SCSrc321_12, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_128, MCK_Imm, MCK_Imm, MCK_SCSrc32 }, },
21869 : { 6237 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_vi, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Reg1_8__Reg1_9__Imm1_10__Imm1_11__SCSrc321_12, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_128, MCK_Imm, MCK_Imm, MCK_SCSrc32 }, },
21870 : { 6262 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_si, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Reg1_8__Reg1_9__Imm1_10__Imm1_11__SCSrc321_12, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_128, MCK_Imm, MCK_Imm, MCK_SCSrc32 }, },
21871 : { 6262 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_vi, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3__Imm1_4__Imm1_5__Imm1_6__Imm1_7__Reg1_8__Reg1_9__Imm1_10__Imm1_11__SCSrc321_12, Feature_isGCN, { MCK_VReg_128, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_Imm, MCK_VGPR_32, MCK_SReg_128, MCK_Imm, MCK_Imm, MCK_SCSrc32 }, },
21872 : { 6288 /* v_add_f16 */, AMDGPU::V_ADD_F16_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
21873 : { 6288 /* v_add_f16 */, AMDGPU::V_ADD_F16_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
21874 : { 6288 /* v_add_f16 */, AMDGPU::V_ADD_F16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
21875 : { 6288 /* v_add_f16 */, AMDGPU::V_ADD_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
21876 : { 6298 /* v_add_f32 */, AMDGPU::V_ADD_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
21877 : { 6298 /* v_add_f32 */, AMDGPU::V_ADD_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
21878 : { 6298 /* v_add_f32 */, AMDGPU::V_ADD_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
21879 : { 6298 /* v_add_f32 */, AMDGPU::V_ADD_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
21880 : { 6308 /* v_add_f64 */, AMDGPU::V_ADD_F64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
21881 : { 6308 /* v_add_f64 */, AMDGPU::V_ADD_F64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
21882 : { 6318 /* v_add_i32 */, AMDGPU::V_ADD_I32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
21883 : { 6318 /* v_add_i32 */, AMDGPU::V_ADD_I32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
21884 : { 6318 /* v_add_i32 */, AMDGPU::V_ADD_I32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
21885 : { 6318 /* v_add_i32 */, AMDGPU::V_ADD_I32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
21886 : { 6328 /* v_add_u16 */, AMDGPU::V_ADD_U16_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
21887 : { 6328 /* v_add_u16 */, AMDGPU::V_ADD_U16_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
21888 : { 6328 /* v_add_u16 */, AMDGPU::V_ADD_U16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
21889 : { 6328 /* v_add_u16 */, AMDGPU::V_ADD_U16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
21890 : { 6338 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_e32_si, Convert__Reg1_0__VCSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VGPR_32 }, },
21891 : { 6338 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_e32_vi, Convert__Reg1_0__VCSrc321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VGPR_32 }, },
21892 : { 6338 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
21893 : { 6338 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
21894 : { 6349 /* v_alignbit_b32 */, AMDGPU::V_ALIGNBIT_B32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc32 }, },
21895 : { 6349 /* v_alignbit_b32 */, AMDGPU::V_ALIGNBIT_B32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc32 }, },
21896 : { 6364 /* v_alignbyte_b32 */, AMDGPU::V_ALIGNBYTE_B32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc32 }, },
21897 : { 6364 /* v_alignbyte_b32 */, AMDGPU::V_ALIGNBYTE_B32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc32 }, },
21898 : { 6380 /* v_and_b32 */, AMDGPU::V_AND_B32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
21899 : { 6380 /* v_and_b32 */, AMDGPU::V_AND_B32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
21900 : { 6380 /* v_and_b32 */, AMDGPU::V_AND_B32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
21901 : { 6380 /* v_and_b32 */, AMDGPU::V_AND_B32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
21902 : { 6390 /* v_ashr_i32 */, AMDGPU::V_ASHR_I32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
21903 : { 6390 /* v_ashr_i32 */, AMDGPU::V_ASHR_I32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
21904 : { 6401 /* v_ashr_i64 */, AMDGPU::V_ASHR_I64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_VReg_64, MCK_VCSrc64, MCK_VCSrc32 }, },
21905 : { 6401 /* v_ashr_i64 */, AMDGPU::V_ASHR_I64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_VReg_64, MCK_VCSrc64, MCK_VCSrc32 }, },
21906 : { 6412 /* v_ashrrev_b16 */, AMDGPU::V_ASHRREV_B16_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
21907 : { 6412 /* v_ashrrev_b16 */, AMDGPU::V_ASHRREV_B16_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
21908 : { 6412 /* v_ashrrev_b16 */, AMDGPU::V_ASHRREV_B16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
21909 : { 6412 /* v_ashrrev_b16 */, AMDGPU::V_ASHRREV_B16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
21910 : { 6426 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
21911 : { 6426 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
21912 : { 6426 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
21913 : { 6426 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
21914 : { 6440 /* v_ashrrev_i64 */, AMDGPU::V_ASHRREV_I64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VReg_64, MCK_VCSrc32, MCK_VCSrc64 }, },
21915 : { 6440 /* v_ashrrev_i64 */, AMDGPU::V_ASHRREV_I64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VReg_64, MCK_VCSrc32, MCK_VCSrc64 }, },
21916 : { 6454 /* v_bcnt_u32_b32 */, AMDGPU::V_BCNT_U32_B32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
21917 : { 6454 /* v_bcnt_u32_b32 */, AMDGPU::V_BCNT_U32_B32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
21918 : { 6454 /* v_bcnt_u32_b32 */, AMDGPU::V_BCNT_U32_B32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
21919 : { 6469 /* v_bfe_i32 */, AMDGPU::V_BFE_I32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc32 }, },
21920 : { 6469 /* v_bfe_i32 */, AMDGPU::V_BFE_I32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc32 }, },
21921 : { 6479 /* v_bfe_u32 */, AMDGPU::V_BFE_U32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc32 }, },
21922 : { 6479 /* v_bfe_u32 */, AMDGPU::V_BFE_U32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc32 }, },
21923 : { 6489 /* v_bfi_b32 */, AMDGPU::V_BFI_B32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc32 }, },
21924 : { 6489 /* v_bfi_b32 */, AMDGPU::V_BFI_B32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc32 }, },
21925 : { 6499 /* v_bfm_b32 */, AMDGPU::V_BFM_B32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
21926 : { 6499 /* v_bfm_b32 */, AMDGPU::V_BFM_B32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
21927 : { 6499 /* v_bfm_b32 */, AMDGPU::V_BFM_B32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
21928 : { 6509 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
21929 : { 6509 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
21930 : { 6509 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32 }, },
21931 : { 6509 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32 }, },
21932 : { 6521 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_DisableInst, { MCK_VGPR_32, MCK_VSrc32 }, },
21933 : { 6521 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
21934 : { 6521 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
21935 : { 6521 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
21936 : { 6532 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
21937 : { 6532 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
21938 : { 6532 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
21939 : { 6532 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
21940 : { 6543 /* v_ceil_f64 */, AMDGPU::V_CEIL_F64_e32_si, Convert__Reg1_0__VSrc641_1, Feature_isCIVI|Feature_isSICI, { MCK_VReg_64, MCK_VSrc64 }, },
21941 : { 6543 /* v_ceil_f64 */, AMDGPU::V_CEIL_F64_e32_vi, Convert__Reg1_0__VSrc641_1, Feature_isCIVI|Feature_isVI, { MCK_VReg_64, MCK_VSrc64 }, },
21942 : { 6543 /* v_ceil_f64 */, AMDGPU::V_CEIL_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isSICI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
21943 : { 6543 /* v_ceil_f64 */, AMDGPU::V_CEIL_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isVI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
21944 : { 6554 /* v_clrexcp */, AMDGPU::V_CLREXCP_si, Convert_NoOperands, Feature_isGCN|Feature_isSICI, { }, },
21945 : { 6554 /* v_clrexcp */, AMDGPU::V_CLREXCP_vi, Convert_NoOperands, Feature_isGCN|Feature_isVI, { }, },
21946 : { 6564 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
21947 : { 6564 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
21948 : { 6564 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_VCSrc32 }, },
21949 : { 6564 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_VCSrc32 }, },
21950 : { 6580 /* v_cmp_class_f64 */, AMDGPU::V_CMP_CLASS_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VGPR_32 }, },
21951 : { 6580 /* v_cmp_class_f64 */, AMDGPU::V_CMP_CLASS_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VGPR_32 }, },
21952 : { 6580 /* v_cmp_class_f64 */, AMDGPU::V_CMP_CLASS_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_VCSrc32 }, },
21953 : { 6580 /* v_cmp_class_f64 */, AMDGPU::V_CMP_CLASS_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_VCSrc32 }, },
21954 : { 6596 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
21955 : { 6596 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
21956 : { 6596 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
21957 : { 6596 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
21958 : { 6609 /* v_cmp_eq_f64 */, AMDGPU::V_CMP_EQ_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
21959 : { 6609 /* v_cmp_eq_f64 */, AMDGPU::V_CMP_EQ_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
21960 : { 6609 /* v_cmp_eq_f64 */, AMDGPU::V_CMP_EQ_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
21961 : { 6609 /* v_cmp_eq_f64 */, AMDGPU::V_CMP_EQ_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
21962 : { 6622 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
21963 : { 6622 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
21964 : { 6622 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
21965 : { 6622 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
21966 : { 6635 /* v_cmp_eq_i64 */, AMDGPU::V_CMP_EQ_I64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
21967 : { 6635 /* v_cmp_eq_i64 */, AMDGPU::V_CMP_EQ_I64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
21968 : { 6635 /* v_cmp_eq_i64 */, AMDGPU::V_CMP_EQ_I64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
21969 : { 6635 /* v_cmp_eq_i64 */, AMDGPU::V_CMP_EQ_I64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
21970 : { 6648 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
21971 : { 6648 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
21972 : { 6648 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
21973 : { 6648 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
21974 : { 6661 /* v_cmp_eq_u64 */, AMDGPU::V_CMP_EQ_U64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
21975 : { 6661 /* v_cmp_eq_u64 */, AMDGPU::V_CMP_EQ_U64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
21976 : { 6661 /* v_cmp_eq_u64 */, AMDGPU::V_CMP_EQ_U64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
21977 : { 6661 /* v_cmp_eq_u64 */, AMDGPU::V_CMP_EQ_U64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
21978 : { 6674 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
21979 : { 6674 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
21980 : { 6674 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
21981 : { 6674 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
21982 : { 6686 /* v_cmp_f_f64 */, AMDGPU::V_CMP_F_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
21983 : { 6686 /* v_cmp_f_f64 */, AMDGPU::V_CMP_F_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
21984 : { 6686 /* v_cmp_f_f64 */, AMDGPU::V_CMP_F_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
21985 : { 6686 /* v_cmp_f_f64 */, AMDGPU::V_CMP_F_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
21986 : { 6698 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
21987 : { 6698 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
21988 : { 6698 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
21989 : { 6698 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
21990 : { 6710 /* v_cmp_f_i64 */, AMDGPU::V_CMP_F_I64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
21991 : { 6710 /* v_cmp_f_i64 */, AMDGPU::V_CMP_F_I64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
21992 : { 6710 /* v_cmp_f_i64 */, AMDGPU::V_CMP_F_I64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
21993 : { 6710 /* v_cmp_f_i64 */, AMDGPU::V_CMP_F_I64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
21994 : { 6722 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
21995 : { 6722 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
21996 : { 6722 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
21997 : { 6722 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
21998 : { 6734 /* v_cmp_f_u64 */, AMDGPU::V_CMP_F_U64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
21999 : { 6734 /* v_cmp_f_u64 */, AMDGPU::V_CMP_F_U64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22000 : { 6734 /* v_cmp_f_u64 */, AMDGPU::V_CMP_F_U64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22001 : { 6734 /* v_cmp_f_u64 */, AMDGPU::V_CMP_F_U64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22002 : { 6746 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22003 : { 6746 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22004 : { 6746 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22005 : { 6746 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22006 : { 6759 /* v_cmp_ge_f64 */, AMDGPU::V_CMP_GE_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22007 : { 6759 /* v_cmp_ge_f64 */, AMDGPU::V_CMP_GE_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22008 : { 6759 /* v_cmp_ge_f64 */, AMDGPU::V_CMP_GE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22009 : { 6759 /* v_cmp_ge_f64 */, AMDGPU::V_CMP_GE_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22010 : { 6772 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22011 : { 6772 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22012 : { 6772 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22013 : { 6772 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22014 : { 6785 /* v_cmp_ge_i64 */, AMDGPU::V_CMP_GE_I64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22015 : { 6785 /* v_cmp_ge_i64 */, AMDGPU::V_CMP_GE_I64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22016 : { 6785 /* v_cmp_ge_i64 */, AMDGPU::V_CMP_GE_I64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22017 : { 6785 /* v_cmp_ge_i64 */, AMDGPU::V_CMP_GE_I64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22018 : { 6798 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22019 : { 6798 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22020 : { 6798 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22021 : { 6798 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22022 : { 6811 /* v_cmp_ge_u64 */, AMDGPU::V_CMP_GE_U64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22023 : { 6811 /* v_cmp_ge_u64 */, AMDGPU::V_CMP_GE_U64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22024 : { 6811 /* v_cmp_ge_u64 */, AMDGPU::V_CMP_GE_U64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22025 : { 6811 /* v_cmp_ge_u64 */, AMDGPU::V_CMP_GE_U64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22026 : { 6824 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22027 : { 6824 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22028 : { 6824 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22029 : { 6824 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22030 : { 6837 /* v_cmp_gt_f64 */, AMDGPU::V_CMP_GT_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22031 : { 6837 /* v_cmp_gt_f64 */, AMDGPU::V_CMP_GT_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22032 : { 6837 /* v_cmp_gt_f64 */, AMDGPU::V_CMP_GT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22033 : { 6837 /* v_cmp_gt_f64 */, AMDGPU::V_CMP_GT_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22034 : { 6850 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22035 : { 6850 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22036 : { 6850 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22037 : { 6850 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22038 : { 6863 /* v_cmp_gt_i64 */, AMDGPU::V_CMP_GT_I64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22039 : { 6863 /* v_cmp_gt_i64 */, AMDGPU::V_CMP_GT_I64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22040 : { 6863 /* v_cmp_gt_i64 */, AMDGPU::V_CMP_GT_I64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22041 : { 6863 /* v_cmp_gt_i64 */, AMDGPU::V_CMP_GT_I64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22042 : { 6876 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22043 : { 6876 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22044 : { 6876 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22045 : { 6876 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22046 : { 6889 /* v_cmp_gt_u64 */, AMDGPU::V_CMP_GT_U64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22047 : { 6889 /* v_cmp_gt_u64 */, AMDGPU::V_CMP_GT_U64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22048 : { 6889 /* v_cmp_gt_u64 */, AMDGPU::V_CMP_GT_U64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22049 : { 6889 /* v_cmp_gt_u64 */, AMDGPU::V_CMP_GT_U64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22050 : { 6902 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22051 : { 6902 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22052 : { 6902 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22053 : { 6902 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22054 : { 6915 /* v_cmp_le_f64 */, AMDGPU::V_CMP_LE_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22055 : { 6915 /* v_cmp_le_f64 */, AMDGPU::V_CMP_LE_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22056 : { 6915 /* v_cmp_le_f64 */, AMDGPU::V_CMP_LE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22057 : { 6915 /* v_cmp_le_f64 */, AMDGPU::V_CMP_LE_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22058 : { 6928 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22059 : { 6928 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22060 : { 6928 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22061 : { 6928 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22062 : { 6941 /* v_cmp_le_i64 */, AMDGPU::V_CMP_LE_I64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22063 : { 6941 /* v_cmp_le_i64 */, AMDGPU::V_CMP_LE_I64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22064 : { 6941 /* v_cmp_le_i64 */, AMDGPU::V_CMP_LE_I64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22065 : { 6941 /* v_cmp_le_i64 */, AMDGPU::V_CMP_LE_I64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22066 : { 6954 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22067 : { 6954 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22068 : { 6954 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22069 : { 6954 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22070 : { 6967 /* v_cmp_le_u64 */, AMDGPU::V_CMP_LE_U64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22071 : { 6967 /* v_cmp_le_u64 */, AMDGPU::V_CMP_LE_U64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22072 : { 6967 /* v_cmp_le_u64 */, AMDGPU::V_CMP_LE_U64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22073 : { 6967 /* v_cmp_le_u64 */, AMDGPU::V_CMP_LE_U64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22074 : { 6980 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22075 : { 6980 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22076 : { 6980 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22077 : { 6980 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22078 : { 6993 /* v_cmp_lg_f64 */, AMDGPU::V_CMP_LG_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22079 : { 6993 /* v_cmp_lg_f64 */, AMDGPU::V_CMP_LG_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22080 : { 6993 /* v_cmp_lg_f64 */, AMDGPU::V_CMP_LG_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22081 : { 6993 /* v_cmp_lg_f64 */, AMDGPU::V_CMP_LG_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22082 : { 7006 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22083 : { 7006 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22084 : { 7006 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22085 : { 7006 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22086 : { 7019 /* v_cmp_lt_f64 */, AMDGPU::V_CMP_LT_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22087 : { 7019 /* v_cmp_lt_f64 */, AMDGPU::V_CMP_LT_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22088 : { 7019 /* v_cmp_lt_f64 */, AMDGPU::V_CMP_LT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22089 : { 7019 /* v_cmp_lt_f64 */, AMDGPU::V_CMP_LT_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22090 : { 7032 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22091 : { 7032 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22092 : { 7032 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22093 : { 7032 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22094 : { 7045 /* v_cmp_lt_i64 */, AMDGPU::V_CMP_LT_I64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22095 : { 7045 /* v_cmp_lt_i64 */, AMDGPU::V_CMP_LT_I64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22096 : { 7045 /* v_cmp_lt_i64 */, AMDGPU::V_CMP_LT_I64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22097 : { 7045 /* v_cmp_lt_i64 */, AMDGPU::V_CMP_LT_I64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22098 : { 7058 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22099 : { 7058 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22100 : { 7058 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22101 : { 7058 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22102 : { 7071 /* v_cmp_lt_u64 */, AMDGPU::V_CMP_LT_U64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22103 : { 7071 /* v_cmp_lt_u64 */, AMDGPU::V_CMP_LT_U64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22104 : { 7071 /* v_cmp_lt_u64 */, AMDGPU::V_CMP_LT_U64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22105 : { 7071 /* v_cmp_lt_u64 */, AMDGPU::V_CMP_LT_U64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22106 : { 7084 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22107 : { 7084 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22108 : { 7084 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22109 : { 7084 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22110 : { 7097 /* v_cmp_ne_i64 */, AMDGPU::V_CMP_NE_I64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22111 : { 7097 /* v_cmp_ne_i64 */, AMDGPU::V_CMP_NE_I64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22112 : { 7097 /* v_cmp_ne_i64 */, AMDGPU::V_CMP_NE_I64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22113 : { 7097 /* v_cmp_ne_i64 */, AMDGPU::V_CMP_NE_I64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22114 : { 7110 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22115 : { 7110 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22116 : { 7110 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22117 : { 7110 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22118 : { 7123 /* v_cmp_ne_u64 */, AMDGPU::V_CMP_NE_U64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22119 : { 7123 /* v_cmp_ne_u64 */, AMDGPU::V_CMP_NE_U64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22120 : { 7123 /* v_cmp_ne_u64 */, AMDGPU::V_CMP_NE_U64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22121 : { 7123 /* v_cmp_ne_u64 */, AMDGPU::V_CMP_NE_U64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22122 : { 7136 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22123 : { 7136 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22124 : { 7136 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22125 : { 7136 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22126 : { 7150 /* v_cmp_neq_f64 */, AMDGPU::V_CMP_NEQ_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22127 : { 7150 /* v_cmp_neq_f64 */, AMDGPU::V_CMP_NEQ_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22128 : { 7150 /* v_cmp_neq_f64 */, AMDGPU::V_CMP_NEQ_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22129 : { 7150 /* v_cmp_neq_f64 */, AMDGPU::V_CMP_NEQ_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22130 : { 7164 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22131 : { 7164 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22132 : { 7164 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22133 : { 7164 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22134 : { 7178 /* v_cmp_nge_f64 */, AMDGPU::V_CMP_NGE_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22135 : { 7178 /* v_cmp_nge_f64 */, AMDGPU::V_CMP_NGE_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22136 : { 7178 /* v_cmp_nge_f64 */, AMDGPU::V_CMP_NGE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22137 : { 7178 /* v_cmp_nge_f64 */, AMDGPU::V_CMP_NGE_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22138 : { 7192 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22139 : { 7192 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22140 : { 7192 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22141 : { 7192 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22142 : { 7206 /* v_cmp_ngt_f64 */, AMDGPU::V_CMP_NGT_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22143 : { 7206 /* v_cmp_ngt_f64 */, AMDGPU::V_CMP_NGT_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22144 : { 7206 /* v_cmp_ngt_f64 */, AMDGPU::V_CMP_NGT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22145 : { 7206 /* v_cmp_ngt_f64 */, AMDGPU::V_CMP_NGT_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22146 : { 7220 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22147 : { 7220 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22148 : { 7220 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22149 : { 7220 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22150 : { 7234 /* v_cmp_nle_f64 */, AMDGPU::V_CMP_NLE_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22151 : { 7234 /* v_cmp_nle_f64 */, AMDGPU::V_CMP_NLE_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22152 : { 7234 /* v_cmp_nle_f64 */, AMDGPU::V_CMP_NLE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22153 : { 7234 /* v_cmp_nle_f64 */, AMDGPU::V_CMP_NLE_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22154 : { 7248 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22155 : { 7248 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22156 : { 7248 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22157 : { 7248 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22158 : { 7262 /* v_cmp_nlg_f64 */, AMDGPU::V_CMP_NLG_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22159 : { 7262 /* v_cmp_nlg_f64 */, AMDGPU::V_CMP_NLG_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22160 : { 7262 /* v_cmp_nlg_f64 */, AMDGPU::V_CMP_NLG_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22161 : { 7262 /* v_cmp_nlg_f64 */, AMDGPU::V_CMP_NLG_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22162 : { 7276 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22163 : { 7276 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22164 : { 7276 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22165 : { 7276 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22166 : { 7290 /* v_cmp_nlt_f64 */, AMDGPU::V_CMP_NLT_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22167 : { 7290 /* v_cmp_nlt_f64 */, AMDGPU::V_CMP_NLT_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22168 : { 7290 /* v_cmp_nlt_f64 */, AMDGPU::V_CMP_NLT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22169 : { 7290 /* v_cmp_nlt_f64 */, AMDGPU::V_CMP_NLT_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22170 : { 7304 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22171 : { 7304 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22172 : { 7304 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22173 : { 7304 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22174 : { 7316 /* v_cmp_o_f64 */, AMDGPU::V_CMP_O_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22175 : { 7316 /* v_cmp_o_f64 */, AMDGPU::V_CMP_O_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22176 : { 7316 /* v_cmp_o_f64 */, AMDGPU::V_CMP_O_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22177 : { 7316 /* v_cmp_o_f64 */, AMDGPU::V_CMP_O_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22178 : { 7328 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22179 : { 7328 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22180 : { 7328 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22181 : { 7328 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22182 : { 7340 /* v_cmp_t_i64 */, AMDGPU::V_CMP_T_I64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22183 : { 7340 /* v_cmp_t_i64 */, AMDGPU::V_CMP_T_I64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22184 : { 7340 /* v_cmp_t_i64 */, AMDGPU::V_CMP_T_I64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22185 : { 7340 /* v_cmp_t_i64 */, AMDGPU::V_CMP_T_I64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22186 : { 7352 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22187 : { 7352 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22188 : { 7352 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22189 : { 7352 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22190 : { 7364 /* v_cmp_t_u64 */, AMDGPU::V_CMP_T_U64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22191 : { 7364 /* v_cmp_t_u64 */, AMDGPU::V_CMP_T_U64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22192 : { 7364 /* v_cmp_t_u64 */, AMDGPU::V_CMP_T_U64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22193 : { 7364 /* v_cmp_t_u64 */, AMDGPU::V_CMP_T_U64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22194 : { 7376 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22195 : { 7376 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22196 : { 7376 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22197 : { 7376 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22198 : { 7390 /* v_cmp_tru_f64 */, AMDGPU::V_CMP_TRU_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22199 : { 7390 /* v_cmp_tru_f64 */, AMDGPU::V_CMP_TRU_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22200 : { 7390 /* v_cmp_tru_f64 */, AMDGPU::V_CMP_TRU_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22201 : { 7390 /* v_cmp_tru_f64 */, AMDGPU::V_CMP_TRU_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22202 : { 7404 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22203 : { 7404 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22204 : { 7404 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22205 : { 7404 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22206 : { 7416 /* v_cmp_u_f64 */, AMDGPU::V_CMP_U_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22207 : { 7416 /* v_cmp_u_f64 */, AMDGPU::V_CMP_U_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22208 : { 7416 /* v_cmp_u_f64 */, AMDGPU::V_CMP_U_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22209 : { 7416 /* v_cmp_u_f64 */, AMDGPU::V_CMP_U_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22210 : { 7428 /* v_cmps_eq_f32 */, AMDGPU::V_CMPS_EQ_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22211 : { 7428 /* v_cmps_eq_f32 */, AMDGPU::V_CMPS_EQ_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22212 : { 7428 /* v_cmps_eq_f32 */, AMDGPU::V_CMPS_EQ_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22213 : { 7428 /* v_cmps_eq_f32 */, AMDGPU::V_CMPS_EQ_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22214 : { 7442 /* v_cmps_eq_f64 */, AMDGPU::V_CMPS_EQ_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22215 : { 7442 /* v_cmps_eq_f64 */, AMDGPU::V_CMPS_EQ_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22216 : { 7442 /* v_cmps_eq_f64 */, AMDGPU::V_CMPS_EQ_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22217 : { 7442 /* v_cmps_eq_f64 */, AMDGPU::V_CMPS_EQ_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22218 : { 7456 /* v_cmps_f_f32 */, AMDGPU::V_CMPS_F_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22219 : { 7456 /* v_cmps_f_f32 */, AMDGPU::V_CMPS_F_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22220 : { 7456 /* v_cmps_f_f32 */, AMDGPU::V_CMPS_F_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22221 : { 7456 /* v_cmps_f_f32 */, AMDGPU::V_CMPS_F_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22222 : { 7469 /* v_cmps_f_f64 */, AMDGPU::V_CMPS_F_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22223 : { 7469 /* v_cmps_f_f64 */, AMDGPU::V_CMPS_F_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22224 : { 7469 /* v_cmps_f_f64 */, AMDGPU::V_CMPS_F_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22225 : { 7469 /* v_cmps_f_f64 */, AMDGPU::V_CMPS_F_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22226 : { 7482 /* v_cmps_ge_f32 */, AMDGPU::V_CMPS_GE_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22227 : { 7482 /* v_cmps_ge_f32 */, AMDGPU::V_CMPS_GE_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22228 : { 7482 /* v_cmps_ge_f32 */, AMDGPU::V_CMPS_GE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22229 : { 7482 /* v_cmps_ge_f32 */, AMDGPU::V_CMPS_GE_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22230 : { 7496 /* v_cmps_ge_f64 */, AMDGPU::V_CMPS_GE_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22231 : { 7496 /* v_cmps_ge_f64 */, AMDGPU::V_CMPS_GE_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22232 : { 7496 /* v_cmps_ge_f64 */, AMDGPU::V_CMPS_GE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22233 : { 7496 /* v_cmps_ge_f64 */, AMDGPU::V_CMPS_GE_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22234 : { 7510 /* v_cmps_gt_f32 */, AMDGPU::V_CMPS_GT_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22235 : { 7510 /* v_cmps_gt_f32 */, AMDGPU::V_CMPS_GT_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22236 : { 7510 /* v_cmps_gt_f32 */, AMDGPU::V_CMPS_GT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22237 : { 7510 /* v_cmps_gt_f32 */, AMDGPU::V_CMPS_GT_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22238 : { 7524 /* v_cmps_gt_f64 */, AMDGPU::V_CMPS_GT_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22239 : { 7524 /* v_cmps_gt_f64 */, AMDGPU::V_CMPS_GT_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22240 : { 7524 /* v_cmps_gt_f64 */, AMDGPU::V_CMPS_GT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22241 : { 7524 /* v_cmps_gt_f64 */, AMDGPU::V_CMPS_GT_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22242 : { 7538 /* v_cmps_le_f32 */, AMDGPU::V_CMPS_LE_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22243 : { 7538 /* v_cmps_le_f32 */, AMDGPU::V_CMPS_LE_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22244 : { 7538 /* v_cmps_le_f32 */, AMDGPU::V_CMPS_LE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22245 : { 7538 /* v_cmps_le_f32 */, AMDGPU::V_CMPS_LE_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22246 : { 7552 /* v_cmps_le_f64 */, AMDGPU::V_CMPS_LE_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22247 : { 7552 /* v_cmps_le_f64 */, AMDGPU::V_CMPS_LE_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22248 : { 7552 /* v_cmps_le_f64 */, AMDGPU::V_CMPS_LE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22249 : { 7552 /* v_cmps_le_f64 */, AMDGPU::V_CMPS_LE_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22250 : { 7566 /* v_cmps_lg_f32 */, AMDGPU::V_CMPS_LG_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22251 : { 7566 /* v_cmps_lg_f32 */, AMDGPU::V_CMPS_LG_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22252 : { 7566 /* v_cmps_lg_f32 */, AMDGPU::V_CMPS_LG_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22253 : { 7566 /* v_cmps_lg_f32 */, AMDGPU::V_CMPS_LG_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22254 : { 7580 /* v_cmps_lg_f64 */, AMDGPU::V_CMPS_LG_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22255 : { 7580 /* v_cmps_lg_f64 */, AMDGPU::V_CMPS_LG_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22256 : { 7580 /* v_cmps_lg_f64 */, AMDGPU::V_CMPS_LG_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22257 : { 7580 /* v_cmps_lg_f64 */, AMDGPU::V_CMPS_LG_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22258 : { 7594 /* v_cmps_lt_f32 */, AMDGPU::V_CMPS_LT_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22259 : { 7594 /* v_cmps_lt_f32 */, AMDGPU::V_CMPS_LT_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22260 : { 7594 /* v_cmps_lt_f32 */, AMDGPU::V_CMPS_LT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22261 : { 7594 /* v_cmps_lt_f32 */, AMDGPU::V_CMPS_LT_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22262 : { 7608 /* v_cmps_lt_f64 */, AMDGPU::V_CMPS_LT_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22263 : { 7608 /* v_cmps_lt_f64 */, AMDGPU::V_CMPS_LT_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22264 : { 7608 /* v_cmps_lt_f64 */, AMDGPU::V_CMPS_LT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22265 : { 7608 /* v_cmps_lt_f64 */, AMDGPU::V_CMPS_LT_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22266 : { 7622 /* v_cmps_neq_f32 */, AMDGPU::V_CMPS_NEQ_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22267 : { 7622 /* v_cmps_neq_f32 */, AMDGPU::V_CMPS_NEQ_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22268 : { 7622 /* v_cmps_neq_f32 */, AMDGPU::V_CMPS_NEQ_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22269 : { 7622 /* v_cmps_neq_f32 */, AMDGPU::V_CMPS_NEQ_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22270 : { 7637 /* v_cmps_neq_f64 */, AMDGPU::V_CMPS_NEQ_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22271 : { 7637 /* v_cmps_neq_f64 */, AMDGPU::V_CMPS_NEQ_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22272 : { 7637 /* v_cmps_neq_f64 */, AMDGPU::V_CMPS_NEQ_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22273 : { 7637 /* v_cmps_neq_f64 */, AMDGPU::V_CMPS_NEQ_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22274 : { 7652 /* v_cmps_nge_f32 */, AMDGPU::V_CMPS_NGE_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22275 : { 7652 /* v_cmps_nge_f32 */, AMDGPU::V_CMPS_NGE_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22276 : { 7652 /* v_cmps_nge_f32 */, AMDGPU::V_CMPS_NGE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22277 : { 7652 /* v_cmps_nge_f32 */, AMDGPU::V_CMPS_NGE_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22278 : { 7667 /* v_cmps_nge_f64 */, AMDGPU::V_CMPS_NGE_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22279 : { 7667 /* v_cmps_nge_f64 */, AMDGPU::V_CMPS_NGE_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22280 : { 7667 /* v_cmps_nge_f64 */, AMDGPU::V_CMPS_NGE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22281 : { 7667 /* v_cmps_nge_f64 */, AMDGPU::V_CMPS_NGE_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22282 : { 7682 /* v_cmps_ngt_f32 */, AMDGPU::V_CMPS_NGT_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22283 : { 7682 /* v_cmps_ngt_f32 */, AMDGPU::V_CMPS_NGT_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22284 : { 7682 /* v_cmps_ngt_f32 */, AMDGPU::V_CMPS_NGT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22285 : { 7682 /* v_cmps_ngt_f32 */, AMDGPU::V_CMPS_NGT_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22286 : { 7697 /* v_cmps_ngt_f64 */, AMDGPU::V_CMPS_NGT_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22287 : { 7697 /* v_cmps_ngt_f64 */, AMDGPU::V_CMPS_NGT_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22288 : { 7697 /* v_cmps_ngt_f64 */, AMDGPU::V_CMPS_NGT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22289 : { 7697 /* v_cmps_ngt_f64 */, AMDGPU::V_CMPS_NGT_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22290 : { 7712 /* v_cmps_nle_f32 */, AMDGPU::V_CMPS_NLE_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22291 : { 7712 /* v_cmps_nle_f32 */, AMDGPU::V_CMPS_NLE_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22292 : { 7712 /* v_cmps_nle_f32 */, AMDGPU::V_CMPS_NLE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22293 : { 7712 /* v_cmps_nle_f32 */, AMDGPU::V_CMPS_NLE_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22294 : { 7727 /* v_cmps_nle_f64 */, AMDGPU::V_CMPS_NLE_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22295 : { 7727 /* v_cmps_nle_f64 */, AMDGPU::V_CMPS_NLE_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22296 : { 7727 /* v_cmps_nle_f64 */, AMDGPU::V_CMPS_NLE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22297 : { 7727 /* v_cmps_nle_f64 */, AMDGPU::V_CMPS_NLE_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22298 : { 7742 /* v_cmps_nlg_f32 */, AMDGPU::V_CMPS_NLG_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22299 : { 7742 /* v_cmps_nlg_f32 */, AMDGPU::V_CMPS_NLG_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22300 : { 7742 /* v_cmps_nlg_f32 */, AMDGPU::V_CMPS_NLG_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22301 : { 7742 /* v_cmps_nlg_f32 */, AMDGPU::V_CMPS_NLG_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22302 : { 7757 /* v_cmps_nlg_f64 */, AMDGPU::V_CMPS_NLG_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22303 : { 7757 /* v_cmps_nlg_f64 */, AMDGPU::V_CMPS_NLG_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22304 : { 7757 /* v_cmps_nlg_f64 */, AMDGPU::V_CMPS_NLG_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22305 : { 7757 /* v_cmps_nlg_f64 */, AMDGPU::V_CMPS_NLG_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22306 : { 7772 /* v_cmps_nlt_f32 */, AMDGPU::V_CMPS_NLT_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22307 : { 7772 /* v_cmps_nlt_f32 */, AMDGPU::V_CMPS_NLT_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22308 : { 7772 /* v_cmps_nlt_f32 */, AMDGPU::V_CMPS_NLT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22309 : { 7772 /* v_cmps_nlt_f32 */, AMDGPU::V_CMPS_NLT_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22310 : { 7787 /* v_cmps_nlt_f64 */, AMDGPU::V_CMPS_NLT_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22311 : { 7787 /* v_cmps_nlt_f64 */, AMDGPU::V_CMPS_NLT_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22312 : { 7787 /* v_cmps_nlt_f64 */, AMDGPU::V_CMPS_NLT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22313 : { 7787 /* v_cmps_nlt_f64 */, AMDGPU::V_CMPS_NLT_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22314 : { 7802 /* v_cmps_o_f32 */, AMDGPU::V_CMPS_O_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22315 : { 7802 /* v_cmps_o_f32 */, AMDGPU::V_CMPS_O_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22316 : { 7802 /* v_cmps_o_f32 */, AMDGPU::V_CMPS_O_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22317 : { 7802 /* v_cmps_o_f32 */, AMDGPU::V_CMPS_O_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22318 : { 7815 /* v_cmps_o_f64 */, AMDGPU::V_CMPS_O_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22319 : { 7815 /* v_cmps_o_f64 */, AMDGPU::V_CMPS_O_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22320 : { 7815 /* v_cmps_o_f64 */, AMDGPU::V_CMPS_O_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22321 : { 7815 /* v_cmps_o_f64 */, AMDGPU::V_CMPS_O_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22322 : { 7828 /* v_cmps_tru_f32 */, AMDGPU::V_CMPS_TRU_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22323 : { 7828 /* v_cmps_tru_f32 */, AMDGPU::V_CMPS_TRU_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22324 : { 7828 /* v_cmps_tru_f32 */, AMDGPU::V_CMPS_TRU_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22325 : { 7828 /* v_cmps_tru_f32 */, AMDGPU::V_CMPS_TRU_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22326 : { 7843 /* v_cmps_tru_f64 */, AMDGPU::V_CMPS_TRU_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22327 : { 7843 /* v_cmps_tru_f64 */, AMDGPU::V_CMPS_TRU_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22328 : { 7843 /* v_cmps_tru_f64 */, AMDGPU::V_CMPS_TRU_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22329 : { 7843 /* v_cmps_tru_f64 */, AMDGPU::V_CMPS_TRU_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22330 : { 7858 /* v_cmps_u_f32 */, AMDGPU::V_CMPS_U_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22331 : { 7858 /* v_cmps_u_f32 */, AMDGPU::V_CMPS_U_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22332 : { 7858 /* v_cmps_u_f32 */, AMDGPU::V_CMPS_U_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22333 : { 7858 /* v_cmps_u_f32 */, AMDGPU::V_CMPS_U_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22334 : { 7871 /* v_cmps_u_f64 */, AMDGPU::V_CMPS_U_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22335 : { 7871 /* v_cmps_u_f64 */, AMDGPU::V_CMPS_U_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22336 : { 7871 /* v_cmps_u_f64 */, AMDGPU::V_CMPS_U_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22337 : { 7871 /* v_cmps_u_f64 */, AMDGPU::V_CMPS_U_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22338 : { 7884 /* v_cmpsx_eq_f32 */, AMDGPU::V_CMPSX_EQ_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22339 : { 7884 /* v_cmpsx_eq_f32 */, AMDGPU::V_CMPSX_EQ_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22340 : { 7884 /* v_cmpsx_eq_f32 */, AMDGPU::V_CMPSX_EQ_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22341 : { 7884 /* v_cmpsx_eq_f32 */, AMDGPU::V_CMPSX_EQ_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22342 : { 7899 /* v_cmpsx_eq_f64 */, AMDGPU::V_CMPSX_EQ_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22343 : { 7899 /* v_cmpsx_eq_f64 */, AMDGPU::V_CMPSX_EQ_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22344 : { 7899 /* v_cmpsx_eq_f64 */, AMDGPU::V_CMPSX_EQ_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22345 : { 7899 /* v_cmpsx_eq_f64 */, AMDGPU::V_CMPSX_EQ_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22346 : { 7914 /* v_cmpsx_f_f32 */, AMDGPU::V_CMPSX_F_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22347 : { 7914 /* v_cmpsx_f_f32 */, AMDGPU::V_CMPSX_F_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22348 : { 7914 /* v_cmpsx_f_f32 */, AMDGPU::V_CMPSX_F_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22349 : { 7914 /* v_cmpsx_f_f32 */, AMDGPU::V_CMPSX_F_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22350 : { 7928 /* v_cmpsx_f_f64 */, AMDGPU::V_CMPSX_F_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22351 : { 7928 /* v_cmpsx_f_f64 */, AMDGPU::V_CMPSX_F_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22352 : { 7928 /* v_cmpsx_f_f64 */, AMDGPU::V_CMPSX_F_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22353 : { 7928 /* v_cmpsx_f_f64 */, AMDGPU::V_CMPSX_F_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22354 : { 7942 /* v_cmpsx_ge_f32 */, AMDGPU::V_CMPSX_GE_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22355 : { 7942 /* v_cmpsx_ge_f32 */, AMDGPU::V_CMPSX_GE_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22356 : { 7942 /* v_cmpsx_ge_f32 */, AMDGPU::V_CMPSX_GE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22357 : { 7942 /* v_cmpsx_ge_f32 */, AMDGPU::V_CMPSX_GE_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22358 : { 7957 /* v_cmpsx_ge_f64 */, AMDGPU::V_CMPSX_GE_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22359 : { 7957 /* v_cmpsx_ge_f64 */, AMDGPU::V_CMPSX_GE_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22360 : { 7957 /* v_cmpsx_ge_f64 */, AMDGPU::V_CMPSX_GE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22361 : { 7957 /* v_cmpsx_ge_f64 */, AMDGPU::V_CMPSX_GE_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22362 : { 7972 /* v_cmpsx_gt_f32 */, AMDGPU::V_CMPSX_GT_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22363 : { 7972 /* v_cmpsx_gt_f32 */, AMDGPU::V_CMPSX_GT_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22364 : { 7972 /* v_cmpsx_gt_f32 */, AMDGPU::V_CMPSX_GT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22365 : { 7972 /* v_cmpsx_gt_f32 */, AMDGPU::V_CMPSX_GT_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22366 : { 7987 /* v_cmpsx_gt_f64 */, AMDGPU::V_CMPSX_GT_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22367 : { 7987 /* v_cmpsx_gt_f64 */, AMDGPU::V_CMPSX_GT_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22368 : { 7987 /* v_cmpsx_gt_f64 */, AMDGPU::V_CMPSX_GT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22369 : { 7987 /* v_cmpsx_gt_f64 */, AMDGPU::V_CMPSX_GT_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22370 : { 8002 /* v_cmpsx_le_f32 */, AMDGPU::V_CMPSX_LE_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22371 : { 8002 /* v_cmpsx_le_f32 */, AMDGPU::V_CMPSX_LE_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22372 : { 8002 /* v_cmpsx_le_f32 */, AMDGPU::V_CMPSX_LE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22373 : { 8002 /* v_cmpsx_le_f32 */, AMDGPU::V_CMPSX_LE_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22374 : { 8017 /* v_cmpsx_le_f64 */, AMDGPU::V_CMPSX_LE_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22375 : { 8017 /* v_cmpsx_le_f64 */, AMDGPU::V_CMPSX_LE_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22376 : { 8017 /* v_cmpsx_le_f64 */, AMDGPU::V_CMPSX_LE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22377 : { 8017 /* v_cmpsx_le_f64 */, AMDGPU::V_CMPSX_LE_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22378 : { 8032 /* v_cmpsx_lg_f32 */, AMDGPU::V_CMPSX_LG_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22379 : { 8032 /* v_cmpsx_lg_f32 */, AMDGPU::V_CMPSX_LG_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22380 : { 8032 /* v_cmpsx_lg_f32 */, AMDGPU::V_CMPSX_LG_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22381 : { 8032 /* v_cmpsx_lg_f32 */, AMDGPU::V_CMPSX_LG_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22382 : { 8047 /* v_cmpsx_lg_f64 */, AMDGPU::V_CMPSX_LG_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22383 : { 8047 /* v_cmpsx_lg_f64 */, AMDGPU::V_CMPSX_LG_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22384 : { 8047 /* v_cmpsx_lg_f64 */, AMDGPU::V_CMPSX_LG_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22385 : { 8047 /* v_cmpsx_lg_f64 */, AMDGPU::V_CMPSX_LG_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22386 : { 8062 /* v_cmpsx_lt_f32 */, AMDGPU::V_CMPSX_LT_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22387 : { 8062 /* v_cmpsx_lt_f32 */, AMDGPU::V_CMPSX_LT_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22388 : { 8062 /* v_cmpsx_lt_f32 */, AMDGPU::V_CMPSX_LT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22389 : { 8062 /* v_cmpsx_lt_f32 */, AMDGPU::V_CMPSX_LT_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22390 : { 8077 /* v_cmpsx_lt_f64 */, AMDGPU::V_CMPSX_LT_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22391 : { 8077 /* v_cmpsx_lt_f64 */, AMDGPU::V_CMPSX_LT_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22392 : { 8077 /* v_cmpsx_lt_f64 */, AMDGPU::V_CMPSX_LT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22393 : { 8077 /* v_cmpsx_lt_f64 */, AMDGPU::V_CMPSX_LT_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22394 : { 8092 /* v_cmpsx_neq_f32 */, AMDGPU::V_CMPSX_NEQ_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22395 : { 8092 /* v_cmpsx_neq_f32 */, AMDGPU::V_CMPSX_NEQ_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22396 : { 8092 /* v_cmpsx_neq_f32 */, AMDGPU::V_CMPSX_NEQ_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22397 : { 8092 /* v_cmpsx_neq_f32 */, AMDGPU::V_CMPSX_NEQ_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22398 : { 8108 /* v_cmpsx_neq_f64 */, AMDGPU::V_CMPSX_NEQ_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22399 : { 8108 /* v_cmpsx_neq_f64 */, AMDGPU::V_CMPSX_NEQ_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22400 : { 8108 /* v_cmpsx_neq_f64 */, AMDGPU::V_CMPSX_NEQ_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22401 : { 8108 /* v_cmpsx_neq_f64 */, AMDGPU::V_CMPSX_NEQ_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22402 : { 8124 /* v_cmpsx_nge_f32 */, AMDGPU::V_CMPSX_NGE_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22403 : { 8124 /* v_cmpsx_nge_f32 */, AMDGPU::V_CMPSX_NGE_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22404 : { 8124 /* v_cmpsx_nge_f32 */, AMDGPU::V_CMPSX_NGE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22405 : { 8124 /* v_cmpsx_nge_f32 */, AMDGPU::V_CMPSX_NGE_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22406 : { 8140 /* v_cmpsx_nge_f64 */, AMDGPU::V_CMPSX_NGE_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22407 : { 8140 /* v_cmpsx_nge_f64 */, AMDGPU::V_CMPSX_NGE_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22408 : { 8140 /* v_cmpsx_nge_f64 */, AMDGPU::V_CMPSX_NGE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22409 : { 8140 /* v_cmpsx_nge_f64 */, AMDGPU::V_CMPSX_NGE_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22410 : { 8156 /* v_cmpsx_ngt_f32 */, AMDGPU::V_CMPSX_NGT_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22411 : { 8156 /* v_cmpsx_ngt_f32 */, AMDGPU::V_CMPSX_NGT_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22412 : { 8156 /* v_cmpsx_ngt_f32 */, AMDGPU::V_CMPSX_NGT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22413 : { 8156 /* v_cmpsx_ngt_f32 */, AMDGPU::V_CMPSX_NGT_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22414 : { 8172 /* v_cmpsx_ngt_f64 */, AMDGPU::V_CMPSX_NGT_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22415 : { 8172 /* v_cmpsx_ngt_f64 */, AMDGPU::V_CMPSX_NGT_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22416 : { 8172 /* v_cmpsx_ngt_f64 */, AMDGPU::V_CMPSX_NGT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22417 : { 8172 /* v_cmpsx_ngt_f64 */, AMDGPU::V_CMPSX_NGT_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22418 : { 8188 /* v_cmpsx_nle_f32 */, AMDGPU::V_CMPSX_NLE_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22419 : { 8188 /* v_cmpsx_nle_f32 */, AMDGPU::V_CMPSX_NLE_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22420 : { 8188 /* v_cmpsx_nle_f32 */, AMDGPU::V_CMPSX_NLE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22421 : { 8188 /* v_cmpsx_nle_f32 */, AMDGPU::V_CMPSX_NLE_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22422 : { 8204 /* v_cmpsx_nle_f64 */, AMDGPU::V_CMPSX_NLE_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22423 : { 8204 /* v_cmpsx_nle_f64 */, AMDGPU::V_CMPSX_NLE_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22424 : { 8204 /* v_cmpsx_nle_f64 */, AMDGPU::V_CMPSX_NLE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22425 : { 8204 /* v_cmpsx_nle_f64 */, AMDGPU::V_CMPSX_NLE_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22426 : { 8220 /* v_cmpsx_nlg_f32 */, AMDGPU::V_CMPSX_NLG_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22427 : { 8220 /* v_cmpsx_nlg_f32 */, AMDGPU::V_CMPSX_NLG_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22428 : { 8220 /* v_cmpsx_nlg_f32 */, AMDGPU::V_CMPSX_NLG_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22429 : { 8220 /* v_cmpsx_nlg_f32 */, AMDGPU::V_CMPSX_NLG_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22430 : { 8236 /* v_cmpsx_nlg_f64 */, AMDGPU::V_CMPSX_NLG_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22431 : { 8236 /* v_cmpsx_nlg_f64 */, AMDGPU::V_CMPSX_NLG_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22432 : { 8236 /* v_cmpsx_nlg_f64 */, AMDGPU::V_CMPSX_NLG_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22433 : { 8236 /* v_cmpsx_nlg_f64 */, AMDGPU::V_CMPSX_NLG_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22434 : { 8252 /* v_cmpsx_nlt_f32 */, AMDGPU::V_CMPSX_NLT_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22435 : { 8252 /* v_cmpsx_nlt_f32 */, AMDGPU::V_CMPSX_NLT_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22436 : { 8252 /* v_cmpsx_nlt_f32 */, AMDGPU::V_CMPSX_NLT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22437 : { 8252 /* v_cmpsx_nlt_f32 */, AMDGPU::V_CMPSX_NLT_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22438 : { 8268 /* v_cmpsx_nlt_f64 */, AMDGPU::V_CMPSX_NLT_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22439 : { 8268 /* v_cmpsx_nlt_f64 */, AMDGPU::V_CMPSX_NLT_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22440 : { 8268 /* v_cmpsx_nlt_f64 */, AMDGPU::V_CMPSX_NLT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22441 : { 8268 /* v_cmpsx_nlt_f64 */, AMDGPU::V_CMPSX_NLT_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22442 : { 8284 /* v_cmpsx_o_f32 */, AMDGPU::V_CMPSX_O_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22443 : { 8284 /* v_cmpsx_o_f32 */, AMDGPU::V_CMPSX_O_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22444 : { 8284 /* v_cmpsx_o_f32 */, AMDGPU::V_CMPSX_O_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22445 : { 8284 /* v_cmpsx_o_f32 */, AMDGPU::V_CMPSX_O_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22446 : { 8298 /* v_cmpsx_o_f64 */, AMDGPU::V_CMPSX_O_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22447 : { 8298 /* v_cmpsx_o_f64 */, AMDGPU::V_CMPSX_O_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22448 : { 8298 /* v_cmpsx_o_f64 */, AMDGPU::V_CMPSX_O_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22449 : { 8298 /* v_cmpsx_o_f64 */, AMDGPU::V_CMPSX_O_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22450 : { 8312 /* v_cmpsx_tru_f32 */, AMDGPU::V_CMPSX_TRU_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22451 : { 8312 /* v_cmpsx_tru_f32 */, AMDGPU::V_CMPSX_TRU_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22452 : { 8312 /* v_cmpsx_tru_f32 */, AMDGPU::V_CMPSX_TRU_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22453 : { 8312 /* v_cmpsx_tru_f32 */, AMDGPU::V_CMPSX_TRU_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22454 : { 8328 /* v_cmpsx_tru_f64 */, AMDGPU::V_CMPSX_TRU_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22455 : { 8328 /* v_cmpsx_tru_f64 */, AMDGPU::V_CMPSX_TRU_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22456 : { 8328 /* v_cmpsx_tru_f64 */, AMDGPU::V_CMPSX_TRU_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22457 : { 8328 /* v_cmpsx_tru_f64 */, AMDGPU::V_CMPSX_TRU_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22458 : { 8344 /* v_cmpsx_u_f32 */, AMDGPU::V_CMPSX_U_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22459 : { 8344 /* v_cmpsx_u_f32 */, AMDGPU::V_CMPSX_U_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22460 : { 8344 /* v_cmpsx_u_f32 */, AMDGPU::V_CMPSX_U_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22461 : { 8344 /* v_cmpsx_u_f32 */, AMDGPU::V_CMPSX_U_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22462 : { 8358 /* v_cmpsx_u_f64 */, AMDGPU::V_CMPSX_U_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22463 : { 8358 /* v_cmpsx_u_f64 */, AMDGPU::V_CMPSX_U_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isSICI, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22464 : { 8358 /* v_cmpsx_u_f64 */, AMDGPU::V_CMPSX_U_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22465 : { 8358 /* v_cmpsx_u_f64 */, AMDGPU::V_CMPSX_U_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22466 : { 8372 /* v_cmpx_class_f32 */, AMDGPU::V_CMPX_CLASS_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22467 : { 8372 /* v_cmpx_class_f32 */, AMDGPU::V_CMPX_CLASS_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22468 : { 8372 /* v_cmpx_class_f32 */, AMDGPU::V_CMPX_CLASS_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_VCSrc32 }, },
22469 : { 8372 /* v_cmpx_class_f32 */, AMDGPU::V_CMPX_CLASS_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_VCSrc32 }, },
22470 : { 8389 /* v_cmpx_class_f64 */, AMDGPU::V_CMPX_CLASS_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VGPR_32 }, },
22471 : { 8389 /* v_cmpx_class_f64 */, AMDGPU::V_CMPX_CLASS_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VGPR_32 }, },
22472 : { 8389 /* v_cmpx_class_f64 */, AMDGPU::V_CMPX_CLASS_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_VCSrc32 }, },
22473 : { 8389 /* v_cmpx_class_f64 */, AMDGPU::V_CMPX_CLASS_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_VCSrc32 }, },
22474 : { 8406 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22475 : { 8406 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22476 : { 8406 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22477 : { 8406 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22478 : { 8420 /* v_cmpx_eq_f64 */, AMDGPU::V_CMPX_EQ_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22479 : { 8420 /* v_cmpx_eq_f64 */, AMDGPU::V_CMPX_EQ_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22480 : { 8420 /* v_cmpx_eq_f64 */, AMDGPU::V_CMPX_EQ_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22481 : { 8420 /* v_cmpx_eq_f64 */, AMDGPU::V_CMPX_EQ_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22482 : { 8434 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22483 : { 8434 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22484 : { 8434 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22485 : { 8434 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22486 : { 8448 /* v_cmpx_eq_i64 */, AMDGPU::V_CMPX_EQ_I64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22487 : { 8448 /* v_cmpx_eq_i64 */, AMDGPU::V_CMPX_EQ_I64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22488 : { 8448 /* v_cmpx_eq_i64 */, AMDGPU::V_CMPX_EQ_I64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22489 : { 8448 /* v_cmpx_eq_i64 */, AMDGPU::V_CMPX_EQ_I64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22490 : { 8462 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22491 : { 8462 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22492 : { 8462 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22493 : { 8462 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22494 : { 8476 /* v_cmpx_eq_u64 */, AMDGPU::V_CMPX_EQ_U64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22495 : { 8476 /* v_cmpx_eq_u64 */, AMDGPU::V_CMPX_EQ_U64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22496 : { 8476 /* v_cmpx_eq_u64 */, AMDGPU::V_CMPX_EQ_U64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22497 : { 8476 /* v_cmpx_eq_u64 */, AMDGPU::V_CMPX_EQ_U64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22498 : { 8490 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22499 : { 8490 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22500 : { 8490 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22501 : { 8490 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22502 : { 8503 /* v_cmpx_f_f64 */, AMDGPU::V_CMPX_F_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22503 : { 8503 /* v_cmpx_f_f64 */, AMDGPU::V_CMPX_F_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22504 : { 8503 /* v_cmpx_f_f64 */, AMDGPU::V_CMPX_F_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22505 : { 8503 /* v_cmpx_f_f64 */, AMDGPU::V_CMPX_F_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22506 : { 8516 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22507 : { 8516 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22508 : { 8516 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22509 : { 8516 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22510 : { 8529 /* v_cmpx_f_i64 */, AMDGPU::V_CMPX_F_I64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22511 : { 8529 /* v_cmpx_f_i64 */, AMDGPU::V_CMPX_F_I64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22512 : { 8529 /* v_cmpx_f_i64 */, AMDGPU::V_CMPX_F_I64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22513 : { 8529 /* v_cmpx_f_i64 */, AMDGPU::V_CMPX_F_I64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22514 : { 8542 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22515 : { 8542 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22516 : { 8542 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22517 : { 8542 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22518 : { 8555 /* v_cmpx_f_u64 */, AMDGPU::V_CMPX_F_U64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22519 : { 8555 /* v_cmpx_f_u64 */, AMDGPU::V_CMPX_F_U64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22520 : { 8555 /* v_cmpx_f_u64 */, AMDGPU::V_CMPX_F_U64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22521 : { 8555 /* v_cmpx_f_u64 */, AMDGPU::V_CMPX_F_U64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22522 : { 8568 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22523 : { 8568 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22524 : { 8568 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22525 : { 8568 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22526 : { 8582 /* v_cmpx_ge_f64 */, AMDGPU::V_CMPX_GE_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22527 : { 8582 /* v_cmpx_ge_f64 */, AMDGPU::V_CMPX_GE_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22528 : { 8582 /* v_cmpx_ge_f64 */, AMDGPU::V_CMPX_GE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22529 : { 8582 /* v_cmpx_ge_f64 */, AMDGPU::V_CMPX_GE_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22530 : { 8596 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22531 : { 8596 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22532 : { 8596 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22533 : { 8596 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22534 : { 8610 /* v_cmpx_ge_i64 */, AMDGPU::V_CMPX_GE_I64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22535 : { 8610 /* v_cmpx_ge_i64 */, AMDGPU::V_CMPX_GE_I64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22536 : { 8610 /* v_cmpx_ge_i64 */, AMDGPU::V_CMPX_GE_I64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22537 : { 8610 /* v_cmpx_ge_i64 */, AMDGPU::V_CMPX_GE_I64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22538 : { 8624 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22539 : { 8624 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22540 : { 8624 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22541 : { 8624 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22542 : { 8638 /* v_cmpx_ge_u64 */, AMDGPU::V_CMPX_GE_U64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22543 : { 8638 /* v_cmpx_ge_u64 */, AMDGPU::V_CMPX_GE_U64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22544 : { 8638 /* v_cmpx_ge_u64 */, AMDGPU::V_CMPX_GE_U64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22545 : { 8638 /* v_cmpx_ge_u64 */, AMDGPU::V_CMPX_GE_U64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22546 : { 8652 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22547 : { 8652 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22548 : { 8652 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22549 : { 8652 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22550 : { 8666 /* v_cmpx_gt_f64 */, AMDGPU::V_CMPX_GT_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22551 : { 8666 /* v_cmpx_gt_f64 */, AMDGPU::V_CMPX_GT_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22552 : { 8666 /* v_cmpx_gt_f64 */, AMDGPU::V_CMPX_GT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22553 : { 8666 /* v_cmpx_gt_f64 */, AMDGPU::V_CMPX_GT_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22554 : { 8680 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22555 : { 8680 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22556 : { 8680 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22557 : { 8680 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22558 : { 8694 /* v_cmpx_gt_i64 */, AMDGPU::V_CMPX_GT_I64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22559 : { 8694 /* v_cmpx_gt_i64 */, AMDGPU::V_CMPX_GT_I64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22560 : { 8694 /* v_cmpx_gt_i64 */, AMDGPU::V_CMPX_GT_I64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22561 : { 8694 /* v_cmpx_gt_i64 */, AMDGPU::V_CMPX_GT_I64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22562 : { 8708 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22563 : { 8708 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22564 : { 8708 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22565 : { 8708 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22566 : { 8722 /* v_cmpx_gt_u64 */, AMDGPU::V_CMPX_GT_U64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22567 : { 8722 /* v_cmpx_gt_u64 */, AMDGPU::V_CMPX_GT_U64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22568 : { 8722 /* v_cmpx_gt_u64 */, AMDGPU::V_CMPX_GT_U64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22569 : { 8722 /* v_cmpx_gt_u64 */, AMDGPU::V_CMPX_GT_U64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22570 : { 8736 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22571 : { 8736 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22572 : { 8736 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22573 : { 8736 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22574 : { 8750 /* v_cmpx_le_f64 */, AMDGPU::V_CMPX_LE_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22575 : { 8750 /* v_cmpx_le_f64 */, AMDGPU::V_CMPX_LE_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22576 : { 8750 /* v_cmpx_le_f64 */, AMDGPU::V_CMPX_LE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22577 : { 8750 /* v_cmpx_le_f64 */, AMDGPU::V_CMPX_LE_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22578 : { 8764 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22579 : { 8764 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22580 : { 8764 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22581 : { 8764 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22582 : { 8778 /* v_cmpx_le_i64 */, AMDGPU::V_CMPX_LE_I64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22583 : { 8778 /* v_cmpx_le_i64 */, AMDGPU::V_CMPX_LE_I64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22584 : { 8778 /* v_cmpx_le_i64 */, AMDGPU::V_CMPX_LE_I64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22585 : { 8778 /* v_cmpx_le_i64 */, AMDGPU::V_CMPX_LE_I64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22586 : { 8792 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22587 : { 8792 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22588 : { 8792 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22589 : { 8792 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22590 : { 8806 /* v_cmpx_le_u64 */, AMDGPU::V_CMPX_LE_U64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22591 : { 8806 /* v_cmpx_le_u64 */, AMDGPU::V_CMPX_LE_U64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22592 : { 8806 /* v_cmpx_le_u64 */, AMDGPU::V_CMPX_LE_U64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22593 : { 8806 /* v_cmpx_le_u64 */, AMDGPU::V_CMPX_LE_U64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22594 : { 8820 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22595 : { 8820 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22596 : { 8820 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22597 : { 8820 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22598 : { 8834 /* v_cmpx_lg_f64 */, AMDGPU::V_CMPX_LG_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22599 : { 8834 /* v_cmpx_lg_f64 */, AMDGPU::V_CMPX_LG_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22600 : { 8834 /* v_cmpx_lg_f64 */, AMDGPU::V_CMPX_LG_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22601 : { 8834 /* v_cmpx_lg_f64 */, AMDGPU::V_CMPX_LG_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22602 : { 8848 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22603 : { 8848 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22604 : { 8848 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22605 : { 8848 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22606 : { 8862 /* v_cmpx_lt_f64 */, AMDGPU::V_CMPX_LT_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22607 : { 8862 /* v_cmpx_lt_f64 */, AMDGPU::V_CMPX_LT_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22608 : { 8862 /* v_cmpx_lt_f64 */, AMDGPU::V_CMPX_LT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22609 : { 8862 /* v_cmpx_lt_f64 */, AMDGPU::V_CMPX_LT_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22610 : { 8876 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22611 : { 8876 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22612 : { 8876 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22613 : { 8876 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22614 : { 8890 /* v_cmpx_lt_i64 */, AMDGPU::V_CMPX_LT_I64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22615 : { 8890 /* v_cmpx_lt_i64 */, AMDGPU::V_CMPX_LT_I64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22616 : { 8890 /* v_cmpx_lt_i64 */, AMDGPU::V_CMPX_LT_I64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22617 : { 8890 /* v_cmpx_lt_i64 */, AMDGPU::V_CMPX_LT_I64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22618 : { 8904 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22619 : { 8904 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22620 : { 8904 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22621 : { 8904 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22622 : { 8918 /* v_cmpx_lt_u64 */, AMDGPU::V_CMPX_LT_U64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22623 : { 8918 /* v_cmpx_lt_u64 */, AMDGPU::V_CMPX_LT_U64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22624 : { 8918 /* v_cmpx_lt_u64 */, AMDGPU::V_CMPX_LT_U64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22625 : { 8918 /* v_cmpx_lt_u64 */, AMDGPU::V_CMPX_LT_U64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22626 : { 8932 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22627 : { 8932 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22628 : { 8932 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22629 : { 8932 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22630 : { 8946 /* v_cmpx_ne_i64 */, AMDGPU::V_CMPX_NE_I64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22631 : { 8946 /* v_cmpx_ne_i64 */, AMDGPU::V_CMPX_NE_I64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22632 : { 8946 /* v_cmpx_ne_i64 */, AMDGPU::V_CMPX_NE_I64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22633 : { 8946 /* v_cmpx_ne_i64 */, AMDGPU::V_CMPX_NE_I64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22634 : { 8960 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22635 : { 8960 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22636 : { 8960 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22637 : { 8960 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22638 : { 8974 /* v_cmpx_ne_u64 */, AMDGPU::V_CMPX_NE_U64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22639 : { 8974 /* v_cmpx_ne_u64 */, AMDGPU::V_CMPX_NE_U64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22640 : { 8974 /* v_cmpx_ne_u64 */, AMDGPU::V_CMPX_NE_U64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22641 : { 8974 /* v_cmpx_ne_u64 */, AMDGPU::V_CMPX_NE_U64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22642 : { 8988 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22643 : { 8988 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22644 : { 8988 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22645 : { 8988 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22646 : { 9003 /* v_cmpx_neq_f64 */, AMDGPU::V_CMPX_NEQ_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22647 : { 9003 /* v_cmpx_neq_f64 */, AMDGPU::V_CMPX_NEQ_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22648 : { 9003 /* v_cmpx_neq_f64 */, AMDGPU::V_CMPX_NEQ_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22649 : { 9003 /* v_cmpx_neq_f64 */, AMDGPU::V_CMPX_NEQ_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22650 : { 9018 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22651 : { 9018 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22652 : { 9018 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22653 : { 9018 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22654 : { 9033 /* v_cmpx_nge_f64 */, AMDGPU::V_CMPX_NGE_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22655 : { 9033 /* v_cmpx_nge_f64 */, AMDGPU::V_CMPX_NGE_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22656 : { 9033 /* v_cmpx_nge_f64 */, AMDGPU::V_CMPX_NGE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22657 : { 9033 /* v_cmpx_nge_f64 */, AMDGPU::V_CMPX_NGE_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22658 : { 9048 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22659 : { 9048 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22660 : { 9048 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22661 : { 9048 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22662 : { 9063 /* v_cmpx_ngt_f64 */, AMDGPU::V_CMPX_NGT_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22663 : { 9063 /* v_cmpx_ngt_f64 */, AMDGPU::V_CMPX_NGT_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22664 : { 9063 /* v_cmpx_ngt_f64 */, AMDGPU::V_CMPX_NGT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22665 : { 9063 /* v_cmpx_ngt_f64 */, AMDGPU::V_CMPX_NGT_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22666 : { 9078 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22667 : { 9078 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22668 : { 9078 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22669 : { 9078 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22670 : { 9093 /* v_cmpx_nle_f64 */, AMDGPU::V_CMPX_NLE_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22671 : { 9093 /* v_cmpx_nle_f64 */, AMDGPU::V_CMPX_NLE_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22672 : { 9093 /* v_cmpx_nle_f64 */, AMDGPU::V_CMPX_NLE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22673 : { 9093 /* v_cmpx_nle_f64 */, AMDGPU::V_CMPX_NLE_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22674 : { 9108 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22675 : { 9108 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22676 : { 9108 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22677 : { 9108 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22678 : { 9123 /* v_cmpx_nlg_f64 */, AMDGPU::V_CMPX_NLG_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22679 : { 9123 /* v_cmpx_nlg_f64 */, AMDGPU::V_CMPX_NLG_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22680 : { 9123 /* v_cmpx_nlg_f64 */, AMDGPU::V_CMPX_NLG_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22681 : { 9123 /* v_cmpx_nlg_f64 */, AMDGPU::V_CMPX_NLG_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22682 : { 9138 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22683 : { 9138 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22684 : { 9138 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22685 : { 9138 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22686 : { 9153 /* v_cmpx_nlt_f64 */, AMDGPU::V_CMPX_NLT_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22687 : { 9153 /* v_cmpx_nlt_f64 */, AMDGPU::V_CMPX_NLT_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22688 : { 9153 /* v_cmpx_nlt_f64 */, AMDGPU::V_CMPX_NLT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22689 : { 9153 /* v_cmpx_nlt_f64 */, AMDGPU::V_CMPX_NLT_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22690 : { 9168 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22691 : { 9168 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22692 : { 9168 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22693 : { 9168 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22694 : { 9181 /* v_cmpx_o_f64 */, AMDGPU::V_CMPX_O_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22695 : { 9181 /* v_cmpx_o_f64 */, AMDGPU::V_CMPX_O_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22696 : { 9181 /* v_cmpx_o_f64 */, AMDGPU::V_CMPX_O_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22697 : { 9181 /* v_cmpx_o_f64 */, AMDGPU::V_CMPX_O_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22698 : { 9194 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22699 : { 9194 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22700 : { 9194 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22701 : { 9194 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22702 : { 9207 /* v_cmpx_t_i64 */, AMDGPU::V_CMPX_T_I64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22703 : { 9207 /* v_cmpx_t_i64 */, AMDGPU::V_CMPX_T_I64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22704 : { 9207 /* v_cmpx_t_i64 */, AMDGPU::V_CMPX_T_I64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22705 : { 9207 /* v_cmpx_t_i64 */, AMDGPU::V_CMPX_T_I64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22706 : { 9220 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22707 : { 9220 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22708 : { 9220 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22709 : { 9220 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc32, MCK_VCSrc32 }, },
22710 : { 9233 /* v_cmpx_t_u64 */, AMDGPU::V_CMPX_T_U64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22711 : { 9233 /* v_cmpx_t_u64 */, AMDGPU::V_CMPX_T_U64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22712 : { 9233 /* v_cmpx_t_u64 */, AMDGPU::V_CMPX_T_U64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22713 : { 9233 /* v_cmpx_t_u64 */, AMDGPU::V_CMPX_T_U64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrc64, MCK_VCSrc64 }, },
22714 : { 9246 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22715 : { 9246 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22716 : { 9246 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22717 : { 9246 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22718 : { 9261 /* v_cmpx_tru_f64 */, AMDGPU::V_CMPX_TRU_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22719 : { 9261 /* v_cmpx_tru_f64 */, AMDGPU::V_CMPX_TRU_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22720 : { 9261 /* v_cmpx_tru_f64 */, AMDGPU::V_CMPX_TRU_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22721 : { 9261 /* v_cmpx_tru_f64 */, AMDGPU::V_CMPX_TRU_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22722 : { 9276 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22723 : { 9276 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc32, MCK_VGPR_32 }, },
22724 : { 9276 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22725 : { 9276 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22726 : { 9289 /* v_cmpx_u_f64 */, AMDGPU::V_CMPX_U_F64_e32_si, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22727 : { 9289 /* v_cmpx_u_f64 */, AMDGPU::V_CMPX_U_F64_e32_vi, Convert__Reg1_0__VSrc641_1__Reg1_2, Feature_isGCN, { MCK_VCCReg, MCK_VSrc64, MCK_VReg_64 }, },
22728 : { 9289 /* v_cmpx_u_f64 */, AMDGPU::V_CMPX_U_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22729 : { 9289 /* v_cmpx_u_f64 */, AMDGPU::V_CMPX_U_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22730 : { 9302 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2__imm_95_0, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
22731 : { 9302 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2__imm_95_0, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
22732 : { 9302 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32, MCK_SSrc64 }, },
22733 : { 9302 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32, MCK_SSrc64 }, },
22734 : { 9316 /* v_cos_f16 */, AMDGPU::V_COS_F16_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_DisableInst, { MCK_VGPR_32, MCK_VSrc32 }, },
22735 : { 9316 /* v_cos_f16 */, AMDGPU::V_COS_F16_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22736 : { 9316 /* v_cos_f16 */, AMDGPU::V_COS_F16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22737 : { 9316 /* v_cos_f16 */, AMDGPU::V_COS_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22738 : { 9326 /* v_cos_f32 */, AMDGPU::V_COS_F32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
22739 : { 9326 /* v_cos_f32 */, AMDGPU::V_COS_F32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22740 : { 9326 /* v_cos_f32 */, AMDGPU::V_COS_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22741 : { 9326 /* v_cos_f32 */, AMDGPU::V_COS_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22742 : { 9336 /* v_cubeid_f32 */, AMDGPU::V_CUBEID_F32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22743 : { 9336 /* v_cubeid_f32 */, AMDGPU::V_CUBEID_F32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22744 : { 9349 /* v_cubema_f32 */, AMDGPU::V_CUBEMA_F32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22745 : { 9349 /* v_cubema_f32 */, AMDGPU::V_CUBEMA_F32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22746 : { 9362 /* v_cubesc_f32 */, AMDGPU::V_CUBESC_F32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22747 : { 9362 /* v_cubesc_f32 */, AMDGPU::V_CUBESC_F32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22748 : { 9375 /* v_cubetc_f32 */, AMDGPU::V_CUBETC_F32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22749 : { 9375 /* v_cubetc_f32 */, AMDGPU::V_CUBETC_F32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22750 : { 9388 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
22751 : { 9388 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22752 : { 9388 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22753 : { 9388 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22754 : { 9402 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_DisableInst, { MCK_VGPR_32, MCK_VSrc32 }, },
22755 : { 9402 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22756 : { 9402 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32 }, },
22757 : { 9402 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32 }, },
22758 : { 9416 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_DisableInst, { MCK_VGPR_32, MCK_VSrc32 }, },
22759 : { 9416 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22760 : { 9416 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32 }, },
22761 : { 9416 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32 }, },
22762 : { 9430 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
22763 : { 9430 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22764 : { 9430 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32 }, },
22765 : { 9430 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32 }, },
22766 : { 9444 /* v_cvt_f32_f64 */, AMDGPU::V_CVT_F32_F64_e32_si, Convert__Reg1_0__VSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc64 }, },
22767 : { 9444 /* v_cvt_f32_f64 */, AMDGPU::V_CVT_F32_F64_e32_vi, Convert__Reg1_0__VSrc641_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc64 }, },
22768 : { 9444 /* v_cvt_f32_f64 */, AMDGPU::V_CVT_F32_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22769 : { 9444 /* v_cvt_f32_f64 */, AMDGPU::V_CVT_F32_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22770 : { 9458 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
22771 : { 9458 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22772 : { 9458 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32 }, },
22773 : { 9458 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32 }, },
22774 : { 9472 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
22775 : { 9472 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22776 : { 9472 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32 }, },
22777 : { 9472 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32 }, },
22778 : { 9486 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
22779 : { 9486 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22780 : { 9486 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32 }, },
22781 : { 9486 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32 }, },
22782 : { 9503 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
22783 : { 9503 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22784 : { 9503 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32 }, },
22785 : { 9503 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32 }, },
22786 : { 9520 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
22787 : { 9520 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22788 : { 9520 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32 }, },
22789 : { 9520 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32 }, },
22790 : { 9537 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
22791 : { 9537 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22792 : { 9537 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32 }, },
22793 : { 9537 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32 }, },
22794 : { 9554 /* v_cvt_f64_f32 */, AMDGPU::V_CVT_F64_F32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VSrc32 }, },
22795 : { 9554 /* v_cvt_f64_f32 */, AMDGPU::V_CVT_F64_F32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VSrc32 }, },
22796 : { 9554 /* v_cvt_f64_f32 */, AMDGPU::V_CVT_F64_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22797 : { 9554 /* v_cvt_f64_f32 */, AMDGPU::V_CVT_F64_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22798 : { 9568 /* v_cvt_f64_i32 */, AMDGPU::V_CVT_F64_I32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VSrc32 }, },
22799 : { 9568 /* v_cvt_f64_i32 */, AMDGPU::V_CVT_F64_I32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VSrc32 }, },
22800 : { 9568 /* v_cvt_f64_i32 */, AMDGPU::V_CVT_F64_I32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VCSrc32 }, },
22801 : { 9568 /* v_cvt_f64_i32 */, AMDGPU::V_CVT_F64_I32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VCSrc32 }, },
22802 : { 9582 /* v_cvt_f64_u32 */, AMDGPU::V_CVT_F64_U32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VSrc32 }, },
22803 : { 9582 /* v_cvt_f64_u32 */, AMDGPU::V_CVT_F64_U32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VSrc32 }, },
22804 : { 9582 /* v_cvt_f64_u32 */, AMDGPU::V_CVT_F64_U32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VCSrc32 }, },
22805 : { 9582 /* v_cvt_f64_u32 */, AMDGPU::V_CVT_F64_U32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VCSrc32 }, },
22806 : { 9596 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
22807 : { 9596 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22808 : { 9596 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22809 : { 9596 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22810 : { 9614 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_DisableInst, { MCK_VGPR_32, MCK_VSrc32 }, },
22811 : { 9614 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22812 : { 9614 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22813 : { 9614 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22814 : { 9628 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
22815 : { 9628 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22816 : { 9628 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22817 : { 9628 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22818 : { 9642 /* v_cvt_i32_f64 */, AMDGPU::V_CVT_I32_F64_e32_si, Convert__Reg1_0__VSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc64 }, },
22819 : { 9642 /* v_cvt_i32_f64 */, AMDGPU::V_CVT_I32_F64_e32_vi, Convert__Reg1_0__VSrc641_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc64 }, },
22820 : { 9642 /* v_cvt_i32_f64 */, AMDGPU::V_CVT_I32_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22821 : { 9642 /* v_cvt_i32_f64 */, AMDGPU::V_CVT_I32_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22822 : { 9656 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
22823 : { 9656 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22824 : { 9656 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32 }, },
22825 : { 9656 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32 }, },
22826 : { 9673 /* v_cvt_pk_i16_i32 */, AMDGPU::V_CVT_PK_I16_I32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
22827 : { 9673 /* v_cvt_pk_i16_i32 */, AMDGPU::V_CVT_PK_I16_I32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
22828 : { 9673 /* v_cvt_pk_i16_i32 */, AMDGPU::V_CVT_PK_I16_I32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
22829 : { 9690 /* v_cvt_pk_u16_u32 */, AMDGPU::V_CVT_PK_U16_U32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
22830 : { 9690 /* v_cvt_pk_u16_u32 */, AMDGPU::V_CVT_PK_U16_U32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
22831 : { 9690 /* v_cvt_pk_u16_u32 */, AMDGPU::V_CVT_PK_U16_U32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
22832 : { 9707 /* v_cvt_pkaccum_u8_f32 */, AMDGPU::V_CVT_PKACCUM_U8_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
22833 : { 9707 /* v_cvt_pkaccum_u8_f32 */, AMDGPU::V_CVT_PKACCUM_U8_F32_e64_vi, Convert__Reg1_0__imm_95_0__VCSrc321_1__imm_95_0__VCSrc321_2__imm_95_0__imm_95_0, Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
22834 : { 9707 /* v_cvt_pkaccum_u8_f32 */, AMDGPU::V_CVT_PKACCUM_U8_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22835 : { 9707 /* v_cvt_pkaccum_u8_f32 */, AMDGPU::V_CVT_PKACCUM_U8_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22836 : { 9728 /* v_cvt_pknorm_i16_f32 */, AMDGPU::V_CVT_PKNORM_I16_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
22837 : { 9728 /* v_cvt_pknorm_i16_f32 */, AMDGPU::V_CVT_PKNORM_I16_F32_e64_vi, Convert__Reg1_0__imm_95_0__VCSrc321_1__imm_95_0__VCSrc321_2__imm_95_0__imm_95_0, Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
22838 : { 9728 /* v_cvt_pknorm_i16_f32 */, AMDGPU::V_CVT_PKNORM_I16_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22839 : { 9728 /* v_cvt_pknorm_i16_f32 */, AMDGPU::V_CVT_PKNORM_I16_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22840 : { 9749 /* v_cvt_pknorm_u16_f32 */, AMDGPU::V_CVT_PKNORM_U16_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
22841 : { 9749 /* v_cvt_pknorm_u16_f32 */, AMDGPU::V_CVT_PKNORM_U16_F32_e64_vi, Convert__Reg1_0__imm_95_0__VCSrc321_1__imm_95_0__VCSrc321_2__imm_95_0__imm_95_0, Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
22842 : { 9749 /* v_cvt_pknorm_u16_f32 */, AMDGPU::V_CVT_PKNORM_U16_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22843 : { 9749 /* v_cvt_pknorm_u16_f32 */, AMDGPU::V_CVT_PKNORM_U16_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22844 : { 9770 /* v_cvt_pkrtz_f16_f32 */, AMDGPU::V_CVT_PKRTZ_F16_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
22845 : { 9770 /* v_cvt_pkrtz_f16_f32 */, AMDGPU::V_CVT_PKRTZ_F16_F32_e64_vi, Convert__Reg1_0__imm_95_0__VCSrc321_1__imm_95_0__VCSrc321_2__imm_95_0__imm_95_0, Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
22846 : { 9770 /* v_cvt_pkrtz_f16_f32 */, AMDGPU::V_CVT_PKRTZ_F16_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22847 : { 9770 /* v_cvt_pkrtz_f16_f32 */, AMDGPU::V_CVT_PKRTZ_F16_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22848 : { 9790 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
22849 : { 9790 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22850 : { 9790 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22851 : { 9790 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22852 : { 9808 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_DisableInst, { MCK_VGPR_32, MCK_VSrc32 }, },
22853 : { 9808 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22854 : { 9808 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22855 : { 9808 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22856 : { 9822 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
22857 : { 9822 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22858 : { 9822 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22859 : { 9822 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22860 : { 9836 /* v_cvt_u32_f64 */, AMDGPU::V_CVT_U32_F64_e32_si, Convert__Reg1_0__VSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc64 }, },
22861 : { 9836 /* v_cvt_u32_f64 */, AMDGPU::V_CVT_U32_F64_e32_vi, Convert__Reg1_0__VSrc641_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc64 }, },
22862 : { 9836 /* v_cvt_u32_f64 */, AMDGPU::V_CVT_U32_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22863 : { 9836 /* v_cvt_u32_f64 */, AMDGPU::V_CVT_U32_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22864 : { 9850 /* v_div_fixup_f32 */, AMDGPU::V_DIV_FIXUP_F32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22865 : { 9850 /* v_div_fixup_f32 */, AMDGPU::V_DIV_FIXUP_F32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22866 : { 9866 /* v_div_fixup_f64 */, AMDGPU::V_DIV_FIXUP_F64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22867 : { 9866 /* v_div_fixup_f64 */, AMDGPU::V_DIV_FIXUP_F64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22868 : { 9882 /* v_div_fmas_f32 */, AMDGPU::V_DIV_FMAS_F32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22869 : { 9882 /* v_div_fmas_f32 */, AMDGPU::V_DIV_FMAS_F32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22870 : { 9897 /* v_div_fmas_f64 */, AMDGPU::V_DIV_FMAS_F64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22871 : { 9897 /* v_div_fmas_f64 */, AMDGPU::V_DIV_FMAS_F64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22872 : { 9912 /* v_div_scale_f32 */, AMDGPU::V_DIV_SCALE_F32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22873 : { 9912 /* v_div_scale_f32 */, AMDGPU::V_DIV_SCALE_F32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22874 : { 9928 /* v_div_scale_f64 */, AMDGPU::V_DIV_SCALE_F64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22875 : { 9928 /* v_div_scale_f64 */, AMDGPU::V_DIV_SCALE_F64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_SReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22876 : { 9944 /* v_exp_f16 */, AMDGPU::V_EXP_F16_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_DisableInst, { MCK_VGPR_32, MCK_VSrc32 }, },
22877 : { 9944 /* v_exp_f16 */, AMDGPU::V_EXP_F16_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22878 : { 9944 /* v_exp_f16 */, AMDGPU::V_EXP_F16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22879 : { 9944 /* v_exp_f16 */, AMDGPU::V_EXP_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22880 : { 9954 /* v_exp_f32 */, AMDGPU::V_EXP_F32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
22881 : { 9954 /* v_exp_f32 */, AMDGPU::V_EXP_F32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22882 : { 9954 /* v_exp_f32 */, AMDGPU::V_EXP_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22883 : { 9954 /* v_exp_f32 */, AMDGPU::V_EXP_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22884 : { 9964 /* v_exp_legacy_f32 */, AMDGPU::V_EXP_LEGACY_F32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isCIVI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
22885 : { 9964 /* v_exp_legacy_f32 */, AMDGPU::V_EXP_LEGACY_F32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isCIVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22886 : { 9964 /* v_exp_legacy_f32 */, AMDGPU::V_EXP_LEGACY_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22887 : { 9964 /* v_exp_legacy_f32 */, AMDGPU::V_EXP_LEGACY_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22888 : { 9981 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
22889 : { 9981 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22890 : { 9981 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32 }, },
22891 : { 9981 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32 }, },
22892 : { 9992 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
22893 : { 9992 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22894 : { 9992 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32 }, },
22895 : { 9992 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32 }, },
22896 : { 10003 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
22897 : { 10003 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22898 : { 10003 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32 }, },
22899 : { 10003 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32 }, },
22900 : { 10014 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_DisableInst, { MCK_VGPR_32, MCK_VSrc32 }, },
22901 : { 10014 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22902 : { 10014 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22903 : { 10014 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22904 : { 10026 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
22905 : { 10026 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22906 : { 10026 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22907 : { 10026 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22908 : { 10038 /* v_floor_f64 */, AMDGPU::V_FLOOR_F64_e32_si, Convert__Reg1_0__VSrc641_1, Feature_isCIVI|Feature_isSICI, { MCK_VReg_64, MCK_VSrc64 }, },
22909 : { 10038 /* v_floor_f64 */, AMDGPU::V_FLOOR_F64_e32_vi, Convert__Reg1_0__VSrc641_1, Feature_isCIVI|Feature_isVI, { MCK_VReg_64, MCK_VSrc64 }, },
22910 : { 10038 /* v_floor_f64 */, AMDGPU::V_FLOOR_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isSICI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22911 : { 10038 /* v_floor_f64 */, AMDGPU::V_FLOOR_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isVI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22912 : { 10050 /* v_fma_f32 */, AMDGPU::V_FMA_F32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22913 : { 10050 /* v_fma_f32 */, AMDGPU::V_FMA_F32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22914 : { 10060 /* v_fma_f64 */, AMDGPU::V_FMA_F64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22915 : { 10060 /* v_fma_f64 */, AMDGPU::V_FMA_F64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22916 : { 10070 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_DisableInst, { MCK_VGPR_32, MCK_VSrc32 }, },
22917 : { 10070 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22918 : { 10070 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22919 : { 10070 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22920 : { 10082 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
22921 : { 10082 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22922 : { 10082 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22923 : { 10082 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22924 : { 10094 /* v_fract_f64 */, AMDGPU::V_FRACT_F64_e32_si, Convert__Reg1_0__VSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VSrc64 }, },
22925 : { 10094 /* v_fract_f64 */, AMDGPU::V_FRACT_F64_e32_vi, Convert__Reg1_0__VSrc641_1, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VSrc64 }, },
22926 : { 10094 /* v_fract_f64 */, AMDGPU::V_FRACT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22927 : { 10094 /* v_fract_f64 */, AMDGPU::V_FRACT_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22928 : { 10106 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_DisableInst, { MCK_VGPR_32, MCK_VSrc32 }, },
22929 : { 10106 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22930 : { 10106 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22931 : { 10106 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22932 : { 10126 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
22933 : { 10126 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22934 : { 10126 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22935 : { 10126 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22936 : { 10146 /* v_frexp_exp_i32_f64 */, AMDGPU::V_FREXP_EXP_I32_F64_e32_si, Convert__Reg1_0__VSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc64 }, },
22937 : { 10146 /* v_frexp_exp_i32_f64 */, AMDGPU::V_FREXP_EXP_I32_F64_e32_vi, Convert__Reg1_0__VSrc641_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc64 }, },
22938 : { 10146 /* v_frexp_exp_i32_f64 */, AMDGPU::V_FREXP_EXP_I32_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22939 : { 10146 /* v_frexp_exp_i32_f64 */, AMDGPU::V_FREXP_EXP_I32_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22940 : { 10166 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_DisableInst, { MCK_VGPR_32, MCK_VSrc32 }, },
22941 : { 10166 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22942 : { 10166 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22943 : { 10166 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22944 : { 10183 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
22945 : { 10183 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22946 : { 10183 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22947 : { 10183 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22948 : { 10200 /* v_frexp_mant_f64 */, AMDGPU::V_FREXP_MANT_F64_e32_si, Convert__Reg1_0__VSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VSrc64 }, },
22949 : { 10200 /* v_frexp_mant_f64 */, AMDGPU::V_FREXP_MANT_F64_e32_vi, Convert__Reg1_0__VSrc641_1, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VSrc64 }, },
22950 : { 10200 /* v_frexp_mant_f64 */, AMDGPU::V_FREXP_MANT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22951 : { 10200 /* v_frexp_mant_f64 */, AMDGPU::V_FREXP_MANT_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22952 : { 10217 /* v_interp_mov_f32 */, AMDGPU::V_INTERP_MOV_F32_si, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK__91_, MCK_M0, MCK__93_ }, },
22953 : { 10217 /* v_interp_mov_f32 */, AMDGPU::V_INTERP_MOV_F32_vi, Convert__Reg1_0__Imm1_1__Imm1_2__Imm1_3, Feature_isGCN, { MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK_Imm, MCK__91_, MCK_M0, MCK__93_ }, },
22954 : { 10234 /* v_interp_p1_f32 */, AMDGPU::V_INTERP_P1_F32_16bank_si, Convert__Reg1_0__Reg1_1__Imm1_2__Imm1_3, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK__91_, MCK_M0, MCK__93_ }, },
22955 : { 10234 /* v_interp_p1_f32 */, AMDGPU::V_INTERP_P1_F32_16bank_vi, Convert__Reg1_0__Reg1_1__Imm1_2__Imm1_3, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK__91_, MCK_M0, MCK__93_ }, },
22956 : { 10234 /* v_interp_p1_f32 */, AMDGPU::V_INTERP_P1_F32_si, Convert__Reg1_0__Reg1_1__Imm1_2__Imm1_3, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK__91_, MCK_M0, MCK__93_ }, },
22957 : { 10234 /* v_interp_p1_f32 */, AMDGPU::V_INTERP_P1_F32_vi, Convert__Reg1_0__Reg1_1__Imm1_2__Imm1_3, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK__91_, MCK_M0, MCK__93_ }, },
22958 : { 10250 /* v_interp_p2_f32 */, AMDGPU::V_INTERP_P2_F32_si, Convert__Reg1_0__Tie0__Reg1_4__Imm1_5__Imm1_6, Feature_isGCN, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK__93_, MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK__91_, MCK_M0, MCK__93_ }, },
22959 : { 10250 /* v_interp_p2_f32 */, AMDGPU::V_INTERP_P2_F32_vi, Convert__Reg1_0__Tie0__Reg1_4__Imm1_5__Imm1_6, Feature_isGCN, { MCK_VGPR_32, MCK__91_, MCK_VGPR_32, MCK__93_, MCK_VGPR_32, MCK_Imm, MCK_Imm, MCK__91_, MCK_M0, MCK__93_ }, },
22960 : { 10266 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
22961 : { 10266 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
22962 : { 10266 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22963 : { 10266 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22964 : { 10278 /* v_ldexp_f32 */, AMDGPU::V_LDEXP_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
22965 : { 10278 /* v_ldexp_f32 */, AMDGPU::V_LDEXP_F32_e64_vi, Convert__Reg1_0__imm_95_0__VCSrc321_1__imm_95_0__VCSrc321_2__imm_95_0__imm_95_0, Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
22966 : { 10278 /* v_ldexp_f32 */, AMDGPU::V_LDEXP_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22967 : { 10278 /* v_ldexp_f32 */, AMDGPU::V_LDEXP_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22968 : { 10290 /* v_ldexp_f64 */, AMDGPU::V_LDEXP_F64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22969 : { 10290 /* v_ldexp_f64 */, AMDGPU::V_LDEXP_F64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22970 : { 10302 /* v_log_clamp_f32 */, AMDGPU::V_LOG_CLAMP_F32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
22971 : { 10302 /* v_log_clamp_f32 */, AMDGPU::V_LOG_CLAMP_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22972 : { 10318 /* v_log_f16 */, AMDGPU::V_LOG_F16_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_DisableInst, { MCK_VGPR_32, MCK_VSrc32 }, },
22973 : { 10318 /* v_log_f16 */, AMDGPU::V_LOG_F16_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22974 : { 10318 /* v_log_f16 */, AMDGPU::V_LOG_F16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22975 : { 10318 /* v_log_f16 */, AMDGPU::V_LOG_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22976 : { 10328 /* v_log_f32 */, AMDGPU::V_LOG_F32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
22977 : { 10328 /* v_log_f32 */, AMDGPU::V_LOG_F32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22978 : { 10328 /* v_log_f32 */, AMDGPU::V_LOG_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22979 : { 10328 /* v_log_f32 */, AMDGPU::V_LOG_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22980 : { 10338 /* v_log_legacy_f32 */, AMDGPU::V_LOG_LEGACY_F32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isCIVI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
22981 : { 10338 /* v_log_legacy_f32 */, AMDGPU::V_LOG_LEGACY_F32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isCIVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
22982 : { 10338 /* v_log_legacy_f32 */, AMDGPU::V_LOG_LEGACY_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22983 : { 10338 /* v_log_legacy_f32 */, AMDGPU::V_LOG_LEGACY_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
22984 : { 10355 /* v_lshl_b32 */, AMDGPU::V_LSHL_B32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
22985 : { 10355 /* v_lshl_b32 */, AMDGPU::V_LSHL_B32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
22986 : { 10366 /* v_lshl_b64 */, AMDGPU::V_LSHL_B64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_VReg_64, MCK_VCSrc64, MCK_VCSrc32 }, },
22987 : { 10366 /* v_lshl_b64 */, AMDGPU::V_LSHL_B64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_VReg_64, MCK_VCSrc64, MCK_VCSrc32 }, },
22988 : { 10377 /* v_lshlrev_b16 */, AMDGPU::V_LSHLREV_B16_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
22989 : { 10377 /* v_lshlrev_b16 */, AMDGPU::V_LSHLREV_B16_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
22990 : { 10377 /* v_lshlrev_b16 */, AMDGPU::V_LSHLREV_B16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
22991 : { 10377 /* v_lshlrev_b16 */, AMDGPU::V_LSHLREV_B16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
22992 : { 10391 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
22993 : { 10391 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
22994 : { 10391 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
22995 : { 10391 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
22996 : { 10405 /* v_lshlrev_b64 */, AMDGPU::V_LSHLREV_B64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VReg_64, MCK_VCSrc32, MCK_VCSrc64 }, },
22997 : { 10405 /* v_lshlrev_b64 */, AMDGPU::V_LSHLREV_B64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VReg_64, MCK_VCSrc32, MCK_VCSrc64 }, },
22998 : { 10419 /* v_lshr_b32 */, AMDGPU::V_LSHR_B32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
22999 : { 10419 /* v_lshr_b32 */, AMDGPU::V_LSHR_B32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23000 : { 10430 /* v_lshr_b64 */, AMDGPU::V_LSHR_B64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_VReg_64, MCK_VCSrc64, MCK_VCSrc32 }, },
23001 : { 10430 /* v_lshr_b64 */, AMDGPU::V_LSHR_B64_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_VReg_64, MCK_VCSrc64, MCK_VCSrc32 }, },
23002 : { 10441 /* v_lshrrev_b16 */, AMDGPU::V_LSHRREV_B16_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23003 : { 10441 /* v_lshrrev_b16 */, AMDGPU::V_LSHRREV_B16_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23004 : { 10441 /* v_lshrrev_b16 */, AMDGPU::V_LSHRREV_B16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23005 : { 10441 /* v_lshrrev_b16 */, AMDGPU::V_LSHRREV_B16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23006 : { 10455 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23007 : { 10455 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23008 : { 10455 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23009 : { 10455 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23010 : { 10469 /* v_lshrrev_b64 */, AMDGPU::V_LSHRREV_B64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VReg_64, MCK_VCSrc32, MCK_VCSrc64 }, },
23011 : { 10469 /* v_lshrrev_b64 */, AMDGPU::V_LSHRREV_B64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VReg_64, MCK_VCSrc32, MCK_VCSrc64 }, },
23012 : { 10483 /* v_mac_f16 */, AMDGPU::V_MAC_F16_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23013 : { 10483 /* v_mac_f16 */, AMDGPU::V_MAC_F16_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23014 : { 10483 /* v_mac_f16 */, AMDGPU::V_MAC_F16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23015 : { 10483 /* v_mac_f16 */, AMDGPU::V_MAC_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23016 : { 10493 /* v_mac_f32 */, AMDGPU::V_MAC_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23017 : { 10493 /* v_mac_f32 */, AMDGPU::V_MAC_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23018 : { 10493 /* v_mac_f32 */, AMDGPU::V_MAC_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23019 : { 10493 /* v_mac_f32 */, AMDGPU::V_MAC_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23020 : { 10503 /* v_mac_legacy_f32 */, AMDGPU::V_MAC_LEGACY_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23021 : { 10503 /* v_mac_legacy_f32 */, AMDGPU::V_MAC_LEGACY_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23022 : { 10503 /* v_mac_legacy_f32 */, AMDGPU::V_MAC_LEGACY_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23023 : { 10520 /* v_mad_f32 */, AMDGPU::V_MAD_F32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23024 : { 10520 /* v_mad_f32 */, AMDGPU::V_MAD_F32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23025 : { 10530 /* v_mad_i32_i24 */, AMDGPU::V_MAD_I32_I24_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc32 }, },
23026 : { 10530 /* v_mad_i32_i24 */, AMDGPU::V_MAD_I32_I24_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc32 }, },
23027 : { 10544 /* v_mad_i64_i32 */, AMDGPU::V_MAD_I64_I32_si, ConvertCustom_cvtVOP3, Feature_isGCN, { MCK_VReg_64, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc64 }, },
23028 : { 10544 /* v_mad_i64_i32 */, AMDGPU::V_MAD_I64_I32_vi, ConvertCustom_cvtVOP3, Feature_isGCN, { MCK_VReg_64, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc64 }, },
23029 : { 10558 /* v_mad_legacy_f32 */, AMDGPU::V_MAD_LEGACY_F32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23030 : { 10558 /* v_mad_legacy_f32 */, AMDGPU::V_MAD_LEGACY_F32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23031 : { 10575 /* v_mad_u32_u24 */, AMDGPU::V_MAD_U32_U24_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc32 }, },
23032 : { 10575 /* v_mad_u32_u24 */, AMDGPU::V_MAD_U32_U24_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc32 }, },
23033 : { 10589 /* v_mad_u64_u32 */, AMDGPU::V_MAD_U64_U32_si, ConvertCustom_cvtVOP3, Feature_isGCN, { MCK_VReg_64, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc64 }, },
23034 : { 10589 /* v_mad_u64_u32 */, AMDGPU::V_MAD_U64_U32_vi, ConvertCustom_cvtVOP3, Feature_isGCN, { MCK_VReg_64, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc64 }, },
23035 : { 10603 /* v_madak_f16 */, AMDGPU::V_MADAK_F16_si, Convert__Reg1_0__VCSrc321_1__Reg1_2__Imm1_3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VGPR_32, MCK_Imm }, },
23036 : { 10603 /* v_madak_f16 */, AMDGPU::V_MADAK_F16_vi, Convert__Reg1_0__VCSrc321_1__Reg1_2__Imm1_3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VGPR_32, MCK_Imm }, },
23037 : { 10615 /* v_madak_f32 */, AMDGPU::V_MADAK_F32_si, Convert__Reg1_0__VCSrc321_1__Reg1_2__Imm1_3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VGPR_32, MCK_Imm }, },
23038 : { 10615 /* v_madak_f32 */, AMDGPU::V_MADAK_F32_vi, Convert__Reg1_0__VCSrc321_1__Reg1_2__Imm1_3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VGPR_32, MCK_Imm }, },
23039 : { 10627 /* v_madmk_f16 */, AMDGPU::V_MADMK_F16_si, Convert__Reg1_0__VCSrc321_1__Reg1_2__Imm1_3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VGPR_32, MCK_Imm }, },
23040 : { 10627 /* v_madmk_f16 */, AMDGPU::V_MADMK_F16_vi, Convert__Reg1_0__VCSrc321_1__Reg1_2__Imm1_3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VGPR_32, MCK_Imm }, },
23041 : { 10639 /* v_madmk_f32 */, AMDGPU::V_MADMK_F32_si, Convert__Reg1_0__VCSrc321_1__Reg1_2__Imm1_3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VGPR_32, MCK_Imm }, },
23042 : { 10639 /* v_madmk_f32 */, AMDGPU::V_MADMK_F32_vi, Convert__Reg1_0__VCSrc321_1__Reg1_2__Imm1_3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VGPR_32, MCK_Imm }, },
23043 : { 10651 /* v_max3_f32 */, AMDGPU::V_MAX3_F32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23044 : { 10651 /* v_max3_f32 */, AMDGPU::V_MAX3_F32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23045 : { 10662 /* v_max3_i32 */, AMDGPU::V_MAX3_I32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc32 }, },
23046 : { 10662 /* v_max3_i32 */, AMDGPU::V_MAX3_I32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc32 }, },
23047 : { 10673 /* v_max3_u32 */, AMDGPU::V_MAX3_U32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc32 }, },
23048 : { 10673 /* v_max3_u32 */, AMDGPU::V_MAX3_U32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc32 }, },
23049 : { 10684 /* v_max_f16 */, AMDGPU::V_MAX_F16_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23050 : { 10684 /* v_max_f16 */, AMDGPU::V_MAX_F16_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23051 : { 10684 /* v_max_f16 */, AMDGPU::V_MAX_F16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23052 : { 10684 /* v_max_f16 */, AMDGPU::V_MAX_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23053 : { 10694 /* v_max_f32 */, AMDGPU::V_MAX_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23054 : { 10694 /* v_max_f32 */, AMDGPU::V_MAX_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23055 : { 10694 /* v_max_f32 */, AMDGPU::V_MAX_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23056 : { 10694 /* v_max_f32 */, AMDGPU::V_MAX_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23057 : { 10704 /* v_max_f64 */, AMDGPU::V_MAX_F64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23058 : { 10704 /* v_max_f64 */, AMDGPU::V_MAX_F64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23059 : { 10714 /* v_max_i16 */, AMDGPU::V_MAX_I16_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23060 : { 10714 /* v_max_i16 */, AMDGPU::V_MAX_I16_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23061 : { 10714 /* v_max_i16 */, AMDGPU::V_MAX_I16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23062 : { 10714 /* v_max_i16 */, AMDGPU::V_MAX_I16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23063 : { 10724 /* v_max_i32 */, AMDGPU::V_MAX_I32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23064 : { 10724 /* v_max_i32 */, AMDGPU::V_MAX_I32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23065 : { 10724 /* v_max_i32 */, AMDGPU::V_MAX_I32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23066 : { 10724 /* v_max_i32 */, AMDGPU::V_MAX_I32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23067 : { 10734 /* v_max_legacy_f32 */, AMDGPU::V_MAX_LEGACY_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23068 : { 10734 /* v_max_legacy_f32 */, AMDGPU::V_MAX_LEGACY_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23069 : { 10751 /* v_max_u16 */, AMDGPU::V_MAX_U16_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23070 : { 10751 /* v_max_u16 */, AMDGPU::V_MAX_U16_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23071 : { 10751 /* v_max_u16 */, AMDGPU::V_MAX_U16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23072 : { 10751 /* v_max_u16 */, AMDGPU::V_MAX_U16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23073 : { 10761 /* v_max_u32 */, AMDGPU::V_MAX_U32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23074 : { 10761 /* v_max_u32 */, AMDGPU::V_MAX_U32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23075 : { 10761 /* v_max_u32 */, AMDGPU::V_MAX_U32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23076 : { 10761 /* v_max_u32 */, AMDGPU::V_MAX_U32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23077 : { 10771 /* v_mbcnt_hi_u32_b32 */, AMDGPU::V_MBCNT_HI_U32_B32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23078 : { 10771 /* v_mbcnt_hi_u32_b32 */, AMDGPU::V_MBCNT_HI_U32_B32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23079 : { 10771 /* v_mbcnt_hi_u32_b32 */, AMDGPU::V_MBCNT_HI_U32_B32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23080 : { 10790 /* v_mbcnt_lo_u32_b32 */, AMDGPU::V_MBCNT_LO_U32_B32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23081 : { 10790 /* v_mbcnt_lo_u32_b32 */, AMDGPU::V_MBCNT_LO_U32_B32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23082 : { 10790 /* v_mbcnt_lo_u32_b32 */, AMDGPU::V_MBCNT_LO_U32_B32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23083 : { 10809 /* v_med3_f32 */, AMDGPU::V_MED3_F32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23084 : { 10809 /* v_med3_f32 */, AMDGPU::V_MED3_F32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23085 : { 10820 /* v_med3_i32 */, AMDGPU::V_MED3_I32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc32 }, },
23086 : { 10820 /* v_med3_i32 */, AMDGPU::V_MED3_I32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc32 }, },
23087 : { 10831 /* v_med3_u32 */, AMDGPU::V_MED3_U32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc32 }, },
23088 : { 10831 /* v_med3_u32 */, AMDGPU::V_MED3_U32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc32 }, },
23089 : { 10842 /* v_min3_f32 */, AMDGPU::V_MIN3_F32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23090 : { 10842 /* v_min3_f32 */, AMDGPU::V_MIN3_F32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23091 : { 10853 /* v_min3_i32 */, AMDGPU::V_MIN3_I32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc32 }, },
23092 : { 10853 /* v_min3_i32 */, AMDGPU::V_MIN3_I32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc32 }, },
23093 : { 10864 /* v_min3_u32 */, AMDGPU::V_MIN3_U32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc32 }, },
23094 : { 10864 /* v_min3_u32 */, AMDGPU::V_MIN3_U32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc32 }, },
23095 : { 10875 /* v_min_f16 */, AMDGPU::V_MIN_F16_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23096 : { 10875 /* v_min_f16 */, AMDGPU::V_MIN_F16_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23097 : { 10875 /* v_min_f16 */, AMDGPU::V_MIN_F16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23098 : { 10875 /* v_min_f16 */, AMDGPU::V_MIN_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23099 : { 10885 /* v_min_f32 */, AMDGPU::V_MIN_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23100 : { 10885 /* v_min_f32 */, AMDGPU::V_MIN_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23101 : { 10885 /* v_min_f32 */, AMDGPU::V_MIN_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23102 : { 10885 /* v_min_f32 */, AMDGPU::V_MIN_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23103 : { 10895 /* v_min_f64 */, AMDGPU::V_MIN_F64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23104 : { 10895 /* v_min_f64 */, AMDGPU::V_MIN_F64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23105 : { 10905 /* v_min_i16 */, AMDGPU::V_MIN_I16_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23106 : { 10905 /* v_min_i16 */, AMDGPU::V_MIN_I16_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23107 : { 10905 /* v_min_i16 */, AMDGPU::V_MIN_I16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23108 : { 10905 /* v_min_i16 */, AMDGPU::V_MIN_I16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23109 : { 10915 /* v_min_i32 */, AMDGPU::V_MIN_I32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23110 : { 10915 /* v_min_i32 */, AMDGPU::V_MIN_I32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23111 : { 10915 /* v_min_i32 */, AMDGPU::V_MIN_I32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23112 : { 10915 /* v_min_i32 */, AMDGPU::V_MIN_I32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23113 : { 10925 /* v_min_legacy_f32 */, AMDGPU::V_MIN_LEGACY_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23114 : { 10925 /* v_min_legacy_f32 */, AMDGPU::V_MIN_LEGACY_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23115 : { 10942 /* v_min_u16 */, AMDGPU::V_MIN_U16_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23116 : { 10942 /* v_min_u16 */, AMDGPU::V_MIN_U16_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23117 : { 10942 /* v_min_u16 */, AMDGPU::V_MIN_U16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23118 : { 10942 /* v_min_u16 */, AMDGPU::V_MIN_U16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23119 : { 10952 /* v_min_u32 */, AMDGPU::V_MIN_U32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23120 : { 10952 /* v_min_u32 */, AMDGPU::V_MIN_U32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23121 : { 10952 /* v_min_u32 */, AMDGPU::V_MIN_U32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23122 : { 10952 /* v_min_u32 */, AMDGPU::V_MIN_U32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23123 : { 10962 /* v_mov_b32 */, AMDGPU::V_MOV_B32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
23124 : { 10962 /* v_mov_b32 */, AMDGPU::V_MOV_B32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
23125 : { 10962 /* v_mov_b32 */, AMDGPU::V_MOV_B32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32 }, },
23126 : { 10962 /* v_mov_b32 */, AMDGPU::V_MOV_B32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32 }, },
23127 : { 10972 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
23128 : { 10972 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32 }, },
23129 : { 10986 /* v_movreld_b32 */, AMDGPU::V_MOVRELD_B32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
23130 : { 10986 /* v_movreld_b32 */, AMDGPU::V_MOVRELD_B32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
23131 : { 10986 /* v_movreld_b32 */, AMDGPU::V_MOVRELD_B32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32 }, },
23132 : { 10986 /* v_movreld_b32 */, AMDGPU::V_MOVRELD_B32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32 }, },
23133 : { 11000 /* v_movrels_b32 */, AMDGPU::V_MOVRELS_B32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
23134 : { 11000 /* v_movrels_b32 */, AMDGPU::V_MOVRELS_B32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
23135 : { 11000 /* v_movrels_b32 */, AMDGPU::V_MOVRELS_B32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32 }, },
23136 : { 11000 /* v_movrels_b32 */, AMDGPU::V_MOVRELS_B32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32 }, },
23137 : { 11014 /* v_movrelsd_b32 */, AMDGPU::V_MOVRELSD_B32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
23138 : { 11014 /* v_movrelsd_b32 */, AMDGPU::V_MOVRELSD_B32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
23139 : { 11014 /* v_movrelsd_b32 */, AMDGPU::V_MOVRELSD_B32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32 }, },
23140 : { 11014 /* v_movrelsd_b32 */, AMDGPU::V_MOVRELSD_B32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32 }, },
23141 : { 11029 /* v_mqsad_u16_u8 */, AMDGPU::V_MQSAD_U16_U8_si, ConvertCustom_cvtVOP3, Feature_isGCN, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23142 : { 11029 /* v_mqsad_u16_u8 */, AMDGPU::V_MQSAD_U16_U8_vi, ConvertCustom_cvtVOP3, Feature_isGCN, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23143 : { 11044 /* v_mqsad_u32_u8 */, AMDGPU::V_MQSAD_U32_U8_si, ConvertCustom_cvtVOP3, Feature_isGCN, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23144 : { 11044 /* v_mqsad_u32_u8 */, AMDGPU::V_MQSAD_U32_U8_vi, ConvertCustom_cvtVOP3, Feature_isGCN, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23145 : { 11059 /* v_mul_f16 */, AMDGPU::V_MUL_F16_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23146 : { 11059 /* v_mul_f16 */, AMDGPU::V_MUL_F16_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23147 : { 11059 /* v_mul_f16 */, AMDGPU::V_MUL_F16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23148 : { 11059 /* v_mul_f16 */, AMDGPU::V_MUL_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23149 : { 11069 /* v_mul_f32 */, AMDGPU::V_MUL_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23150 : { 11069 /* v_mul_f32 */, AMDGPU::V_MUL_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23151 : { 11069 /* v_mul_f32 */, AMDGPU::V_MUL_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23152 : { 11069 /* v_mul_f32 */, AMDGPU::V_MUL_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23153 : { 11079 /* v_mul_f64 */, AMDGPU::V_MUL_F64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23154 : { 11079 /* v_mul_f64 */, AMDGPU::V_MUL_F64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23155 : { 11089 /* v_mul_hi_i32 */, AMDGPU::V_MUL_HI_I32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23156 : { 11089 /* v_mul_hi_i32 */, AMDGPU::V_MUL_HI_I32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23157 : { 11102 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23158 : { 11102 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23159 : { 11102 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23160 : { 11102 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23161 : { 11119 /* v_mul_hi_u32 */, AMDGPU::V_MUL_HI_U32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23162 : { 11119 /* v_mul_hi_u32 */, AMDGPU::V_MUL_HI_U32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23163 : { 11132 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23164 : { 11132 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23165 : { 11132 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23166 : { 11132 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23167 : { 11149 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23168 : { 11149 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23169 : { 11149 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23170 : { 11149 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23171 : { 11163 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23172 : { 11163 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23173 : { 11163 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23174 : { 11163 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23175 : { 11180 /* v_mul_lo_i32 */, AMDGPU::V_MUL_LO_I32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23176 : { 11180 /* v_mul_lo_i32 */, AMDGPU::V_MUL_LO_I32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23177 : { 11193 /* v_mul_lo_u16 */, AMDGPU::V_MUL_LO_U16_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23178 : { 11193 /* v_mul_lo_u16 */, AMDGPU::V_MUL_LO_U16_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23179 : { 11193 /* v_mul_lo_u16 */, AMDGPU::V_MUL_LO_U16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23180 : { 11193 /* v_mul_lo_u16 */, AMDGPU::V_MUL_LO_U16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23181 : { 11206 /* v_mul_lo_u32 */, AMDGPU::V_MUL_LO_U32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23182 : { 11206 /* v_mul_lo_u32 */, AMDGPU::V_MUL_LO_U32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23183 : { 11219 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23184 : { 11219 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23185 : { 11219 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23186 : { 11219 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23187 : { 11233 /* v_mullit_f32 */, AMDGPU::V_MULLIT_F32_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23188 : { 11233 /* v_mullit_f32 */, AMDGPU::V_MULLIT_F32_vi, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23189 : { 11246 /* v_nop */, AMDGPU::V_NOP_si, Convert_NoOperands, Feature_isGCN|Feature_isSICI, { }, },
23190 : { 11246 /* v_nop */, AMDGPU::V_NOP_vi, Convert_NoOperands, Feature_isGCN|Feature_isVI, { }, },
23191 : { 11252 /* v_not_b32 */, AMDGPU::V_NOT_B32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
23192 : { 11252 /* v_not_b32 */, AMDGPU::V_NOT_B32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
23193 : { 11252 /* v_not_b32 */, AMDGPU::V_NOT_B32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32 }, },
23194 : { 11252 /* v_not_b32 */, AMDGPU::V_NOT_B32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32 }, },
23195 : { 11262 /* v_or_b32 */, AMDGPU::V_OR_B32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23196 : { 11262 /* v_or_b32 */, AMDGPU::V_OR_B32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23197 : { 11262 /* v_or_b32 */, AMDGPU::V_OR_B32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23198 : { 11262 /* v_or_b32 */, AMDGPU::V_OR_B32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23199 : { 11271 /* v_qsad_pk_u16_u8 */, AMDGPU::V_QSAD_PK_U16_U8_si, ConvertCustom_cvtVOP3, Feature_isGCN, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23200 : { 11271 /* v_qsad_pk_u16_u8 */, AMDGPU::V_QSAD_PK_U16_U8_vi, ConvertCustom_cvtVOP3, Feature_isGCN, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23201 : { 11288 /* v_rcp_clamp_f32 */, AMDGPU::V_RCP_CLAMP_F32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
23202 : { 11288 /* v_rcp_clamp_f32 */, AMDGPU::V_RCP_CLAMP_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23203 : { 11304 /* v_rcp_clamp_f64 */, AMDGPU::V_RCP_CLAMP_F64_e32_si, Convert__Reg1_0__VSrc641_1, Feature_isSICI|Feature_isSICI, { MCK_VReg_64, MCK_VSrc64 }, },
23204 : { 11304 /* v_rcp_clamp_f64 */, AMDGPU::V_RCP_CLAMP_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23205 : { 11320 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_DisableInst, { MCK_VGPR_32, MCK_VSrc32 }, },
23206 : { 11320 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
23207 : { 11320 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23208 : { 11320 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23209 : { 11330 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
23210 : { 11330 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
23211 : { 11330 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23212 : { 11330 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23213 : { 11340 /* v_rcp_f64 */, AMDGPU::V_RCP_F64_e32_si, Convert__Reg1_0__VSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VSrc64 }, },
23214 : { 11340 /* v_rcp_f64 */, AMDGPU::V_RCP_F64_e32_vi, Convert__Reg1_0__VSrc641_1, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VSrc64 }, },
23215 : { 11340 /* v_rcp_f64 */, AMDGPU::V_RCP_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23216 : { 11340 /* v_rcp_f64 */, AMDGPU::V_RCP_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23217 : { 11350 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
23218 : { 11350 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
23219 : { 11350 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23220 : { 11350 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23221 : { 11366 /* v_rcp_legacy_f32 */, AMDGPU::V_RCP_LEGACY_F32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
23222 : { 11366 /* v_rcp_legacy_f32 */, AMDGPU::V_RCP_LEGACY_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23223 : { 11383 /* v_readfirstlane_b32 */, AMDGPU::V_READFIRSTLANE_B32, Convert__Reg1_0__Reg1_1, Feature_isGCN, { MCK_SReg_32, MCK_VGPR_32 }, },
23224 : { 11403 /* v_readlane_b32 */, AMDGPU::V_READLANE_B32_si, Convert__Reg1_0__Reg1_1__SCSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_VGPR_32, MCK_SCSrc32 }, },
23225 : { 11403 /* v_readlane_b32 */, AMDGPU::V_READLANE_B32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_VGPR_32, MCK_SCSrc32 }, },
23226 : { 11418 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_DisableInst, { MCK_VGPR_32, MCK_VSrc32 }, },
23227 : { 11418 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
23228 : { 11418 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23229 : { 11418 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23230 : { 11430 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
23231 : { 11430 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
23232 : { 11430 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23233 : { 11430 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23234 : { 11442 /* v_rndne_f64 */, AMDGPU::V_RNDNE_F64_e32_si, Convert__Reg1_0__VSrc641_1, Feature_isCIVI|Feature_isSICI, { MCK_VReg_64, MCK_VSrc64 }, },
23235 : { 11442 /* v_rndne_f64 */, AMDGPU::V_RNDNE_F64_e32_vi, Convert__Reg1_0__VSrc641_1, Feature_isCIVI|Feature_isVI, { MCK_VReg_64, MCK_VSrc64 }, },
23236 : { 11442 /* v_rndne_f64 */, AMDGPU::V_RNDNE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isSICI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23237 : { 11442 /* v_rndne_f64 */, AMDGPU::V_RNDNE_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isVI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23238 : { 11454 /* v_rsq_clamp_f32 */, AMDGPU::V_RSQ_CLAMP_F32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
23239 : { 11454 /* v_rsq_clamp_f32 */, AMDGPU::V_RSQ_CLAMP_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23240 : { 11470 /* v_rsq_clamp_f64 */, AMDGPU::V_RSQ_CLAMP_F64_e32_si, Convert__Reg1_0__VSrc641_1, Feature_isSICI|Feature_isSICI, { MCK_VReg_64, MCK_VSrc64 }, },
23241 : { 11470 /* v_rsq_clamp_f64 */, AMDGPU::V_RSQ_CLAMP_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23242 : { 11486 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_DisableInst, { MCK_VGPR_32, MCK_VSrc32 }, },
23243 : { 11486 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
23244 : { 11486 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23245 : { 11486 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23246 : { 11496 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
23247 : { 11496 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
23248 : { 11496 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23249 : { 11496 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23250 : { 11506 /* v_rsq_f64 */, AMDGPU::V_RSQ_F64_e32_si, Convert__Reg1_0__VSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VSrc64 }, },
23251 : { 11506 /* v_rsq_f64 */, AMDGPU::V_RSQ_F64_e32_vi, Convert__Reg1_0__VSrc641_1, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VSrc64 }, },
23252 : { 11506 /* v_rsq_f64 */, AMDGPU::V_RSQ_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23253 : { 11506 /* v_rsq_f64 */, AMDGPU::V_RSQ_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23254 : { 11516 /* v_rsq_legacy_f32 */, AMDGPU::V_RSQ_LEGACY_F32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
23255 : { 11516 /* v_rsq_legacy_f32 */, AMDGPU::V_RSQ_LEGACY_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23256 : { 11533 /* v_sad_u32 */, AMDGPU::V_SAD_U32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc32 }, },
23257 : { 11533 /* v_sad_u32 */, AMDGPU::V_SAD_U32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32, MCK_VCSrc32 }, },
23258 : { 11543 /* v_sin_f16 */, AMDGPU::V_SIN_F16_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_DisableInst, { MCK_VGPR_32, MCK_VSrc32 }, },
23259 : { 11543 /* v_sin_f16 */, AMDGPU::V_SIN_F16_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
23260 : { 11543 /* v_sin_f16 */, AMDGPU::V_SIN_F16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23261 : { 11543 /* v_sin_f16 */, AMDGPU::V_SIN_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23262 : { 11553 /* v_sin_f32 */, AMDGPU::V_SIN_F32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
23263 : { 11553 /* v_sin_f32 */, AMDGPU::V_SIN_F32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
23264 : { 11553 /* v_sin_f32 */, AMDGPU::V_SIN_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23265 : { 11553 /* v_sin_f32 */, AMDGPU::V_SIN_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23266 : { 11563 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_DisableInst, { MCK_VGPR_32, MCK_VSrc32 }, },
23267 : { 11563 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
23268 : { 11563 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23269 : { 11563 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23270 : { 11574 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
23271 : { 11574 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
23272 : { 11574 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23273 : { 11574 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23274 : { 11585 /* v_sqrt_f64 */, AMDGPU::V_SQRT_F64_e32_si, Convert__Reg1_0__VSrc641_1, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VSrc64 }, },
23275 : { 11585 /* v_sqrt_f64 */, AMDGPU::V_SQRT_F64_e32_vi, Convert__Reg1_0__VSrc641_1, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VSrc64 }, },
23276 : { 11585 /* v_sqrt_f64 */, AMDGPU::V_SQRT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23277 : { 11585 /* v_sqrt_f64 */, AMDGPU::V_SQRT_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23278 : { 11596 /* v_sub_f16 */, AMDGPU::V_SUB_F16_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23279 : { 11596 /* v_sub_f16 */, AMDGPU::V_SUB_F16_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23280 : { 11596 /* v_sub_f16 */, AMDGPU::V_SUB_F16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23281 : { 11596 /* v_sub_f16 */, AMDGPU::V_SUB_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23282 : { 11606 /* v_sub_f32 */, AMDGPU::V_SUB_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23283 : { 11606 /* v_sub_f32 */, AMDGPU::V_SUB_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23284 : { 11606 /* v_sub_f32 */, AMDGPU::V_SUB_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23285 : { 11606 /* v_sub_f32 */, AMDGPU::V_SUB_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23286 : { 11616 /* v_sub_i32 */, AMDGPU::V_SUB_I32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23287 : { 11616 /* v_sub_i32 */, AMDGPU::V_SUB_I32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23288 : { 11616 /* v_sub_i32 */, AMDGPU::V_SUB_I32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23289 : { 11616 /* v_sub_i32 */, AMDGPU::V_SUB_I32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23290 : { 11626 /* v_sub_u16 */, AMDGPU::V_SUB_U16_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23291 : { 11626 /* v_sub_u16 */, AMDGPU::V_SUB_U16_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23292 : { 11626 /* v_sub_u16 */, AMDGPU::V_SUB_U16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23293 : { 11626 /* v_sub_u16 */, AMDGPU::V_SUB_U16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23294 : { 11636 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_e32_si, Convert__Reg1_0__VCSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VGPR_32 }, },
23295 : { 11636 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_e32_vi, Convert__Reg1_0__VCSrc321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VGPR_32 }, },
23296 : { 11636 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23297 : { 11636 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23298 : { 11647 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_e32_si, Convert__Reg1_0__VCSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VGPR_32 }, },
23299 : { 11647 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_e32_vi, Convert__Reg1_0__VCSrc321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VGPR_32 }, },
23300 : { 11647 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23301 : { 11647 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23302 : { 11661 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23303 : { 11661 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23304 : { 11661 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23305 : { 11661 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23306 : { 11674 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23307 : { 11674 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23308 : { 11674 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23309 : { 11674 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23310 : { 11687 /* v_subrev_i32 */, AMDGPU::V_SUBREV_I32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23311 : { 11687 /* v_subrev_i32 */, AMDGPU::V_SUBREV_I32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23312 : { 11687 /* v_subrev_i32 */, AMDGPU::V_SUBREV_I32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23313 : { 11687 /* v_subrev_i32 */, AMDGPU::V_SUBREV_I32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23314 : { 11700 /* v_subrev_u16 */, AMDGPU::V_SUBREV_U16_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23315 : { 11700 /* v_subrev_u16 */, AMDGPU::V_SUBREV_U16_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23316 : { 11700 /* v_subrev_u16 */, AMDGPU::V_SUBREV_U16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23317 : { 11700 /* v_subrev_u16 */, AMDGPU::V_SUBREV_U16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23318 : { 11713 /* v_trig_preop_f64 */, AMDGPU::V_TRIG_PREOP_F64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23319 : { 11713 /* v_trig_preop_f64 */, AMDGPU::V_TRIG_PREOP_F64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23320 : { 11730 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_DisableInst, { MCK_VGPR_32, MCK_VSrc32 }, },
23321 : { 11730 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
23322 : { 11730 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_e64_si, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23323 : { 11730 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23324 : { 11742 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_e32_si, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32 }, },
23325 : { 11742 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_e32_vi, Convert__Reg1_0__VSrc321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32 }, },
23326 : { 11742 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23327 : { 11742 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23328 : { 11754 /* v_trunc_f64 */, AMDGPU::V_TRUNC_F64_e32_si, Convert__Reg1_0__VSrc641_1, Feature_isCIVI|Feature_isSICI, { MCK_VReg_64, MCK_VSrc64 }, },
23329 : { 11754 /* v_trunc_f64 */, AMDGPU::V_TRUNC_F64_e32_vi, Convert__Reg1_0__VSrc641_1, Feature_isCIVI|Feature_isVI, { MCK_VReg_64, MCK_VSrc64 }, },
23330 : { 11754 /* v_trunc_f64 */, AMDGPU::V_TRUNC_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isSICI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23331 : { 11754 /* v_trunc_f64 */, AMDGPU::V_TRUNC_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isVI, { MCK_VReg_64, MCK_RegWithInputMods, MCK_Clamp, MCK_OMod }, },
23332 : { 11766 /* v_writelane_b32 */, AMDGPU::V_WRITELANE_B32_si, Convert__Reg1_0__Reg1_1__SCSrc321_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_SReg_32, MCK_SCSrc32 }, },
23333 : { 11766 /* v_writelane_b32 */, AMDGPU::V_WRITELANE_B32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_SReg_32, MCK_SCSrc32 }, },
23334 : { 11782 /* v_xor_b32 */, AMDGPU::V_XOR_B32_e32_si, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23335 : { 11782 /* v_xor_b32 */, AMDGPU::V_XOR_B32_e32_vi, Convert__Reg1_0__VSrc321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrc32, MCK_VGPR_32 }, },
23336 : { 11782 /* v_xor_b32 */, AMDGPU::V_XOR_B32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23337 : { 11782 /* v_xor_b32 */, AMDGPU::V_XOR_B32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrc32, MCK_VCSrc32 }, },
23338 : };
23339 :
23340 0 : bool AMDGPUAsmParser::
23341 : mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) {
23342 : // Find the appropriate table for this asm variant.
23343 : const MatchEntry *Start, *End;
23344 0 : switch (VariantID) {
23345 0 : default: llvm_unreachable("invalid variant!");
23346 0 : case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
23347 : }
23348 : // Search the table.
23349 : std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =
23350 0 : std::equal_range(Start, End, Mnemonic, LessOpcode());
23351 0 : return MnemonicRange.first != MnemonicRange.second;
23352 : }
23353 :
23354 2266 : unsigned AMDGPUAsmParser::
23355 : MatchInstructionImpl(const OperandVector &Operands,
23356 : MCInst &Inst, uint64_t &ErrorInfo,
23357 : bool matchingInlineAsm, unsigned VariantID) {
23358 : // Eliminate obvious mismatches.
23359 4532 : if (Operands.size() > 14) {
23360 0 : ErrorInfo = 14;
23361 0 : return Match_InvalidOperand;
23362 : }
23363 :
23364 : // Get the current feature set.
23365 2266 : uint64_t AvailableFeatures = getAvailableFeatures();
23366 :
23367 : // Get the instruction mnemonic, which is the first token.
23368 6798 : StringRef Mnemonic = ((AMDGPUOperand&)*Operands[0]).getToken();
23369 :
23370 : // Process all MnemonicAliases to remap the mnemonic.
23371 2266 : applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);
23372 :
23373 : // Some state to try to produce better error messages.
23374 2266 : bool HadMatchOtherThanFeatures = false;
23375 2266 : bool HadMatchOtherThanPredicate = false;
23376 2266 : unsigned RetCode = Match_InvalidOperand;
23377 2266 : uint64_t MissingFeatures = ~0ULL;
23378 : // Set ErrorInfo to the operand that mismatches if it is
23379 : // wrong for all instances of the instruction.
23380 2266 : ErrorInfo = ~0ULL;
23381 : // Find the appropriate table for this asm variant.
23382 : const MatchEntry *Start, *End;
23383 2266 : switch (VariantID) {
23384 0 : default: llvm_unreachable("invalid variant!");
23385 2266 : case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
23386 : }
23387 : // Search the table.
23388 : std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =
23389 2266 : std::equal_range(Start, End, Mnemonic, LessOpcode());
23390 :
23391 : // Return a more specific error code if no mnemonics match.
23392 2266 : if (MnemonicRange.first == MnemonicRange.second)
23393 : return Match_MnemonicFail;
23394 :
23395 2418 : for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
23396 : it != ie; ++it) {
23397 : // equal_range guarantees that instruction mnemonic matches.
23398 : assert(Mnemonic == it->getMnemonic());
23399 : bool OperandsValid = true;
23400 11086 : for (unsigned i = 0; i != 13; ++i) {
23401 30884 : if (i + 1 >= Operands.size()) {
23402 3024 : OperandsValid = (it->Classes[i] == InvalidMatchClass);
23403 3024 : if (!OperandsValid) ErrorInfo = i + 1;
23404 : break;
23405 : }
23406 24836 : unsigned Diag = validateOperandClass(*Operands[i+1],
23407 24836 : (MatchClassKind)it->Classes[i]);
23408 12418 : if (Diag == Match_Success)
23409 : continue;
23410 : // If the generic handler indicates an invalid operand
23411 : // failure, check for a special case.
23412 1332 : if (Diag == Match_InvalidOperand) {
23413 2664 : Diag = validateTargetOperandClass(*Operands[i+1],
23414 2664 : (MatchClassKind)it->Classes[i]);
23415 1332 : if (Diag == Match_Success)
23416 : continue;
23417 : }
23418 : // If this operand is broken for all of the instances of this
23419 : // mnemonic, keep track of it so we can report loc info.
23420 : // If we already had a match that only failed due to a
23421 : // target predicate, that diagnostic is preferred.
23422 1332 : if (!HadMatchOtherThanPredicate &&
23423 1042 : (it == MnemonicRange.first || ErrorInfo <= i+1)) {
23424 938 : ErrorInfo = i+1;
23425 : // InvalidOperand is the default. Prefer specificity.
23426 938 : if (Diag != Match_InvalidOperand)
23427 0 : RetCode = Diag;
23428 : }
23429 : // Otherwise, just reject this instance of the mnemonic.
23430 : OperandsValid = false;
23431 : break;
23432 : }
23433 :
23434 4356 : if (!OperandsValid) continue;
23435 3008 : if ((AvailableFeatures & it->RequiredFeatures) != it->RequiredFeatures) {
23436 1056 : HadMatchOtherThanFeatures = true;
23437 1056 : uint64_t NewMissingFeatures = it->RequiredFeatures & ~AvailableFeatures;
23438 2112 : if (countPopulation(NewMissingFeatures) <=
23439 : countPopulation(MissingFeatures))
23440 1032 : MissingFeatures = NewMissingFeatures;
23441 : continue;
23442 : }
23443 :
23444 : Inst.clear();
23445 :
23446 1952 : if (matchingInlineAsm) {
23447 0 : Inst.setOpcode(it->Opcode);
23448 0 : convertToMapAndConstraints(it->ConvertFn, Operands);
23449 0 : return Match_Success;
23450 : }
23451 :
23452 : // We have selected a definite instruction, convert the parsed
23453 : // operands into the appropriate MCInst.
23454 1952 : convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);
23455 :
23456 : // We have a potential match. Check the target predicate to
23457 : // handle any context sensitive constraints.
23458 : unsigned MatchResult;
23459 1952 : if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
23460 : Inst.clear();
23461 14 : RetCode = MatchResult;
23462 14 : HadMatchOtherThanPredicate = true;
23463 14 : continue;
23464 : }
23465 :
23466 : return Match_Success;
23467 : }
23468 :
23469 : // Okay, we had no match. Try to return a useful error code.
23470 328 : if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)
23471 42 : return RetCode;
23472 :
23473 : // Missing feature matches return which features were missing
23474 286 : ErrorInfo = MissingFeatures;
23475 286 : return Match_MissingFeature;
23476 : }
23477 :
23478 : namespace {
23479 : struct OperandMatchEntry {
23480 : uint8_t RequiredFeatures;
23481 : uint16_t Mnemonic;
23482 : uint8_t Class;
23483 : uint16_t OperandMask;
23484 :
23485 : StringRef getMnemonic() const {
23486 173514 : return StringRef(MnemonicTable + Mnemonic + 1,
23487 347028 : MnemonicTable[Mnemonic]);
23488 : }
23489 : };
23490 :
23491 : // Predicate for searching for an opcode.
23492 : struct LessOpcodeOperand {
23493 109068 : bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
23494 218136 : return LHS.getMnemonic() < RHS;
23495 : }
23496 64446 : bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
23497 128892 : return LHS < RHS.getMnemonic();
23498 : }
23499 : bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
23500 : return LHS.getMnemonic() < RHS.getMnemonic();
23501 : }
23502 : };
23503 : } // end anonymous namespace.
23504 :
23505 : static const OperandMatchEntry OperandMatchTable[2348] = {
23506 : /* Operand List Mask, Mnemonic, Operand Class, Features */
23507 : { Feature_isGCN, 154 /* buffer_atomic_add */, MCK_MubufOffset, 8 /* 3 */ },
23508 : { Feature_isGCN, 154 /* buffer_atomic_add */, MCK_SLC, 16 /* 4 */ },
23509 : { Feature_isGCN, 154 /* buffer_atomic_add */, MCK_MubufOffset, 8 /* 3 */ },
23510 : { Feature_isGCN, 154 /* buffer_atomic_add */, MCK_SLC, 16 /* 4 */ },
23511 : { Feature_isGCN, 154 /* buffer_atomic_add */, MCK_MubufOffset, 8 /* 3 */ },
23512 : { Feature_isGCN, 154 /* buffer_atomic_add */, MCK_SLC, 32 /* 5 */ },
23513 : { Feature_isGCN, 154 /* buffer_atomic_add */, MCK_MubufOffset, 8 /* 3 */ },
23514 : { Feature_isGCN, 154 /* buffer_atomic_add */, MCK_SLC, 32 /* 5 */ },
23515 : { Feature_isGCN, 154 /* buffer_atomic_add */, MCK_MubufOffset, 32 /* 5 */ },
23516 : { Feature_isGCN, 154 /* buffer_atomic_add */, MCK_SLC, 64 /* 6 */ },
23517 : { Feature_isGCN, 154 /* buffer_atomic_add */, MCK_MubufOffset, 32 /* 5 */ },
23518 : { Feature_isGCN, 154 /* buffer_atomic_add */, MCK_SLC, 128 /* 7 */ },
23519 : { Feature_isGCN, 172 /* buffer_atomic_and */, MCK_MubufOffset, 8 /* 3 */ },
23520 : { Feature_isGCN, 172 /* buffer_atomic_and */, MCK_SLC, 16 /* 4 */ },
23521 : { Feature_isGCN, 172 /* buffer_atomic_and */, MCK_MubufOffset, 8 /* 3 */ },
23522 : { Feature_isGCN, 172 /* buffer_atomic_and */, MCK_SLC, 16 /* 4 */ },
23523 : { Feature_isGCN, 172 /* buffer_atomic_and */, MCK_MubufOffset, 8 /* 3 */ },
23524 : { Feature_isGCN, 172 /* buffer_atomic_and */, MCK_SLC, 32 /* 5 */ },
23525 : { Feature_isGCN, 172 /* buffer_atomic_and */, MCK_MubufOffset, 8 /* 3 */ },
23526 : { Feature_isGCN, 172 /* buffer_atomic_and */, MCK_SLC, 32 /* 5 */ },
23527 : { Feature_isGCN, 172 /* buffer_atomic_and */, MCK_MubufOffset, 32 /* 5 */ },
23528 : { Feature_isGCN, 172 /* buffer_atomic_and */, MCK_SLC, 64 /* 6 */ },
23529 : { Feature_isGCN, 172 /* buffer_atomic_and */, MCK_MubufOffset, 32 /* 5 */ },
23530 : { Feature_isGCN, 172 /* buffer_atomic_and */, MCK_SLC, 128 /* 7 */ },
23531 : { Feature_isGCN, 190 /* buffer_atomic_or */, MCK_MubufOffset, 8 /* 3 */ },
23532 : { Feature_isGCN, 190 /* buffer_atomic_or */, MCK_SLC, 16 /* 4 */ },
23533 : { Feature_isGCN, 190 /* buffer_atomic_or */, MCK_MubufOffset, 8 /* 3 */ },
23534 : { Feature_isGCN, 190 /* buffer_atomic_or */, MCK_SLC, 16 /* 4 */ },
23535 : { Feature_isGCN, 190 /* buffer_atomic_or */, MCK_MubufOffset, 8 /* 3 */ },
23536 : { Feature_isGCN, 190 /* buffer_atomic_or */, MCK_SLC, 32 /* 5 */ },
23537 : { Feature_isGCN, 190 /* buffer_atomic_or */, MCK_MubufOffset, 8 /* 3 */ },
23538 : { Feature_isGCN, 190 /* buffer_atomic_or */, MCK_SLC, 32 /* 5 */ },
23539 : { Feature_isGCN, 190 /* buffer_atomic_or */, MCK_MubufOffset, 32 /* 5 */ },
23540 : { Feature_isGCN, 190 /* buffer_atomic_or */, MCK_SLC, 64 /* 6 */ },
23541 : { Feature_isGCN, 190 /* buffer_atomic_or */, MCK_MubufOffset, 32 /* 5 */ },
23542 : { Feature_isGCN, 190 /* buffer_atomic_or */, MCK_SLC, 128 /* 7 */ },
23543 : { Feature_isGCN, 207 /* buffer_atomic_smax */, MCK_MubufOffset, 8 /* 3 */ },
23544 : { Feature_isGCN, 207 /* buffer_atomic_smax */, MCK_SLC, 16 /* 4 */ },
23545 : { Feature_isGCN, 207 /* buffer_atomic_smax */, MCK_MubufOffset, 8 /* 3 */ },
23546 : { Feature_isGCN, 207 /* buffer_atomic_smax */, MCK_SLC, 16 /* 4 */ },
23547 : { Feature_isGCN, 207 /* buffer_atomic_smax */, MCK_MubufOffset, 8 /* 3 */ },
23548 : { Feature_isGCN, 207 /* buffer_atomic_smax */, MCK_SLC, 32 /* 5 */ },
23549 : { Feature_isGCN, 207 /* buffer_atomic_smax */, MCK_MubufOffset, 8 /* 3 */ },
23550 : { Feature_isGCN, 207 /* buffer_atomic_smax */, MCK_SLC, 32 /* 5 */ },
23551 : { Feature_isGCN, 207 /* buffer_atomic_smax */, MCK_MubufOffset, 32 /* 5 */ },
23552 : { Feature_isGCN, 207 /* buffer_atomic_smax */, MCK_SLC, 64 /* 6 */ },
23553 : { Feature_isGCN, 207 /* buffer_atomic_smax */, MCK_MubufOffset, 32 /* 5 */ },
23554 : { Feature_isGCN, 207 /* buffer_atomic_smax */, MCK_SLC, 128 /* 7 */ },
23555 : { Feature_isGCN, 226 /* buffer_atomic_smin */, MCK_MubufOffset, 8 /* 3 */ },
23556 : { Feature_isGCN, 226 /* buffer_atomic_smin */, MCK_SLC, 16 /* 4 */ },
23557 : { Feature_isGCN, 226 /* buffer_atomic_smin */, MCK_MubufOffset, 8 /* 3 */ },
23558 : { Feature_isGCN, 226 /* buffer_atomic_smin */, MCK_SLC, 16 /* 4 */ },
23559 : { Feature_isGCN, 226 /* buffer_atomic_smin */, MCK_MubufOffset, 8 /* 3 */ },
23560 : { Feature_isGCN, 226 /* buffer_atomic_smin */, MCK_SLC, 32 /* 5 */ },
23561 : { Feature_isGCN, 226 /* buffer_atomic_smin */, MCK_MubufOffset, 8 /* 3 */ },
23562 : { Feature_isGCN, 226 /* buffer_atomic_smin */, MCK_SLC, 32 /* 5 */ },
23563 : { Feature_isGCN, 226 /* buffer_atomic_smin */, MCK_MubufOffset, 32 /* 5 */ },
23564 : { Feature_isGCN, 226 /* buffer_atomic_smin */, MCK_SLC, 64 /* 6 */ },
23565 : { Feature_isGCN, 226 /* buffer_atomic_smin */, MCK_MubufOffset, 32 /* 5 */ },
23566 : { Feature_isGCN, 226 /* buffer_atomic_smin */, MCK_SLC, 128 /* 7 */ },
23567 : { Feature_isGCN, 245 /* buffer_atomic_sub */, MCK_MubufOffset, 8 /* 3 */ },
23568 : { Feature_isGCN, 245 /* buffer_atomic_sub */, MCK_SLC, 16 /* 4 */ },
23569 : { Feature_isGCN, 245 /* buffer_atomic_sub */, MCK_MubufOffset, 8 /* 3 */ },
23570 : { Feature_isGCN, 245 /* buffer_atomic_sub */, MCK_SLC, 16 /* 4 */ },
23571 : { Feature_isGCN, 245 /* buffer_atomic_sub */, MCK_MubufOffset, 8 /* 3 */ },
23572 : { Feature_isGCN, 245 /* buffer_atomic_sub */, MCK_SLC, 32 /* 5 */ },
23573 : { Feature_isGCN, 245 /* buffer_atomic_sub */, MCK_MubufOffset, 8 /* 3 */ },
23574 : { Feature_isGCN, 245 /* buffer_atomic_sub */, MCK_SLC, 32 /* 5 */ },
23575 : { Feature_isGCN, 245 /* buffer_atomic_sub */, MCK_MubufOffset, 32 /* 5 */ },
23576 : { Feature_isGCN, 245 /* buffer_atomic_sub */, MCK_SLC, 64 /* 6 */ },
23577 : { Feature_isGCN, 245 /* buffer_atomic_sub */, MCK_MubufOffset, 32 /* 5 */ },
23578 : { Feature_isGCN, 245 /* buffer_atomic_sub */, MCK_SLC, 128 /* 7 */ },
23579 : { Feature_isGCN, 263 /* buffer_atomic_swap */, MCK_MubufOffset, 8 /* 3 */ },
23580 : { Feature_isGCN, 263 /* buffer_atomic_swap */, MCK_SLC, 16 /* 4 */ },
23581 : { Feature_isGCN, 263 /* buffer_atomic_swap */, MCK_MubufOffset, 8 /* 3 */ },
23582 : { Feature_isGCN, 263 /* buffer_atomic_swap */, MCK_SLC, 16 /* 4 */ },
23583 : { Feature_isGCN, 263 /* buffer_atomic_swap */, MCK_MubufOffset, 8 /* 3 */ },
23584 : { Feature_isGCN, 263 /* buffer_atomic_swap */, MCK_SLC, 32 /* 5 */ },
23585 : { Feature_isGCN, 263 /* buffer_atomic_swap */, MCK_MubufOffset, 8 /* 3 */ },
23586 : { Feature_isGCN, 263 /* buffer_atomic_swap */, MCK_SLC, 32 /* 5 */ },
23587 : { Feature_isGCN, 263 /* buffer_atomic_swap */, MCK_MubufOffset, 32 /* 5 */ },
23588 : { Feature_isGCN, 263 /* buffer_atomic_swap */, MCK_SLC, 64 /* 6 */ },
23589 : { Feature_isGCN, 263 /* buffer_atomic_swap */, MCK_MubufOffset, 32 /* 5 */ },
23590 : { Feature_isGCN, 263 /* buffer_atomic_swap */, MCK_SLC, 128 /* 7 */ },
23591 : { Feature_isGCN, 282 /* buffer_atomic_umax */, MCK_MubufOffset, 8 /* 3 */ },
23592 : { Feature_isGCN, 282 /* buffer_atomic_umax */, MCK_SLC, 16 /* 4 */ },
23593 : { Feature_isGCN, 282 /* buffer_atomic_umax */, MCK_MubufOffset, 8 /* 3 */ },
23594 : { Feature_isGCN, 282 /* buffer_atomic_umax */, MCK_SLC, 16 /* 4 */ },
23595 : { Feature_isGCN, 282 /* buffer_atomic_umax */, MCK_MubufOffset, 8 /* 3 */ },
23596 : { Feature_isGCN, 282 /* buffer_atomic_umax */, MCK_SLC, 32 /* 5 */ },
23597 : { Feature_isGCN, 282 /* buffer_atomic_umax */, MCK_MubufOffset, 8 /* 3 */ },
23598 : { Feature_isGCN, 282 /* buffer_atomic_umax */, MCK_SLC, 32 /* 5 */ },
23599 : { Feature_isGCN, 282 /* buffer_atomic_umax */, MCK_MubufOffset, 32 /* 5 */ },
23600 : { Feature_isGCN, 282 /* buffer_atomic_umax */, MCK_SLC, 64 /* 6 */ },
23601 : { Feature_isGCN, 282 /* buffer_atomic_umax */, MCK_MubufOffset, 32 /* 5 */ },
23602 : { Feature_isGCN, 282 /* buffer_atomic_umax */, MCK_SLC, 128 /* 7 */ },
23603 : { Feature_isGCN, 301 /* buffer_atomic_umin */, MCK_MubufOffset, 8 /* 3 */ },
23604 : { Feature_isGCN, 301 /* buffer_atomic_umin */, MCK_SLC, 16 /* 4 */ },
23605 : { Feature_isGCN, 301 /* buffer_atomic_umin */, MCK_MubufOffset, 8 /* 3 */ },
23606 : { Feature_isGCN, 301 /* buffer_atomic_umin */, MCK_SLC, 16 /* 4 */ },
23607 : { Feature_isGCN, 301 /* buffer_atomic_umin */, MCK_MubufOffset, 8 /* 3 */ },
23608 : { Feature_isGCN, 301 /* buffer_atomic_umin */, MCK_SLC, 32 /* 5 */ },
23609 : { Feature_isGCN, 301 /* buffer_atomic_umin */, MCK_MubufOffset, 8 /* 3 */ },
23610 : { Feature_isGCN, 301 /* buffer_atomic_umin */, MCK_SLC, 32 /* 5 */ },
23611 : { Feature_isGCN, 301 /* buffer_atomic_umin */, MCK_MubufOffset, 32 /* 5 */ },
23612 : { Feature_isGCN, 301 /* buffer_atomic_umin */, MCK_SLC, 64 /* 6 */ },
23613 : { Feature_isGCN, 301 /* buffer_atomic_umin */, MCK_MubufOffset, 32 /* 5 */ },
23614 : { Feature_isGCN, 301 /* buffer_atomic_umin */, MCK_SLC, 128 /* 7 */ },
23615 : { Feature_isGCN, 320 /* buffer_atomic_xor */, MCK_MubufOffset, 8 /* 3 */ },
23616 : { Feature_isGCN, 320 /* buffer_atomic_xor */, MCK_SLC, 16 /* 4 */ },
23617 : { Feature_isGCN, 320 /* buffer_atomic_xor */, MCK_MubufOffset, 8 /* 3 */ },
23618 : { Feature_isGCN, 320 /* buffer_atomic_xor */, MCK_SLC, 16 /* 4 */ },
23619 : { Feature_isGCN, 320 /* buffer_atomic_xor */, MCK_MubufOffset, 8 /* 3 */ },
23620 : { Feature_isGCN, 320 /* buffer_atomic_xor */, MCK_SLC, 32 /* 5 */ },
23621 : { Feature_isGCN, 320 /* buffer_atomic_xor */, MCK_MubufOffset, 8 /* 3 */ },
23622 : { Feature_isGCN, 320 /* buffer_atomic_xor */, MCK_SLC, 32 /* 5 */ },
23623 : { Feature_isGCN, 320 /* buffer_atomic_xor */, MCK_MubufOffset, 32 /* 5 */ },
23624 : { Feature_isGCN, 320 /* buffer_atomic_xor */, MCK_SLC, 64 /* 6 */ },
23625 : { Feature_isGCN, 320 /* buffer_atomic_xor */, MCK_MubufOffset, 32 /* 5 */ },
23626 : { Feature_isGCN, 320 /* buffer_atomic_xor */, MCK_SLC, 128 /* 7 */ },
23627 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_GLC, 16 /* 4 */ },
23628 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_MubufOffset, 8 /* 3 */ },
23629 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_SLC, 32 /* 5 */ },
23630 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_TFE, 64 /* 6 */ },
23631 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_GLC, 16 /* 4 */ },
23632 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_MubufOffset, 8 /* 3 */ },
23633 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_SLC, 32 /* 5 */ },
23634 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_TFE, 64 /* 6 */ },
23635 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_GLC, 64 /* 6 */ },
23636 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_MubufOffset, 32 /* 5 */ },
23637 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_SLC, 128 /* 7 */ },
23638 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_TFE, 256 /* 8 */ },
23639 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_GLC, 64 /* 6 */ },
23640 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_MubufOffset, 32 /* 5 */ },
23641 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_SLC, 128 /* 7 */ },
23642 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_TFE, 256 /* 8 */ },
23643 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_GLC, 64 /* 6 */ },
23644 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_MubufOffset, 32 /* 5 */ },
23645 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_SLC, 128 /* 7 */ },
23646 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_TFE, 256 /* 8 */ },
23647 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_GLC, 64 /* 6 */ },
23648 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_MubufOffset, 32 /* 5 */ },
23649 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_SLC, 128 /* 7 */ },
23650 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_TFE, 256 /* 8 */ },
23651 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_GLC, 64 /* 6 */ },
23652 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_MubufOffset, 32 /* 5 */ },
23653 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_SLC, 128 /* 7 */ },
23654 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_TFE, 256 /* 8 */ },
23655 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_GLC, 128 /* 7 */ },
23656 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_MubufOffset, 64 /* 6 */ },
23657 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_SLC, 256 /* 8 */ },
23658 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_TFE, 512 /* 9 */ },
23659 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_GLC, 128 /* 7 */ },
23660 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_MubufOffset, 64 /* 6 */ },
23661 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_SLC, 256 /* 8 */ },
23662 : { Feature_isGCN, 338 /* buffer_load_dword */, MCK_TFE, 512 /* 9 */ },
23663 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_GLC, 16 /* 4 */ },
23664 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_MubufOffset, 8 /* 3 */ },
23665 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_SLC, 32 /* 5 */ },
23666 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_TFE, 64 /* 6 */ },
23667 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_GLC, 16 /* 4 */ },
23668 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_MubufOffset, 8 /* 3 */ },
23669 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_SLC, 32 /* 5 */ },
23670 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_TFE, 64 /* 6 */ },
23671 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_GLC, 64 /* 6 */ },
23672 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_MubufOffset, 32 /* 5 */ },
23673 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_SLC, 128 /* 7 */ },
23674 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_TFE, 256 /* 8 */ },
23675 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_GLC, 64 /* 6 */ },
23676 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_MubufOffset, 32 /* 5 */ },
23677 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_SLC, 128 /* 7 */ },
23678 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_TFE, 256 /* 8 */ },
23679 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_GLC, 64 /* 6 */ },
23680 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_MubufOffset, 32 /* 5 */ },
23681 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_SLC, 128 /* 7 */ },
23682 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_TFE, 256 /* 8 */ },
23683 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_GLC, 64 /* 6 */ },
23684 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_MubufOffset, 32 /* 5 */ },
23685 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_SLC, 128 /* 7 */ },
23686 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_TFE, 256 /* 8 */ },
23687 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_GLC, 64 /* 6 */ },
23688 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_MubufOffset, 32 /* 5 */ },
23689 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_SLC, 128 /* 7 */ },
23690 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_TFE, 256 /* 8 */ },
23691 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_GLC, 128 /* 7 */ },
23692 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_MubufOffset, 64 /* 6 */ },
23693 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_SLC, 256 /* 8 */ },
23694 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_TFE, 512 /* 9 */ },
23695 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_GLC, 128 /* 7 */ },
23696 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_MubufOffset, 64 /* 6 */ },
23697 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_SLC, 256 /* 8 */ },
23698 : { Feature_isGCN, 356 /* buffer_load_dwordx2 */, MCK_TFE, 512 /* 9 */ },
23699 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_GLC, 16 /* 4 */ },
23700 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_MubufOffset, 8 /* 3 */ },
23701 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_SLC, 32 /* 5 */ },
23702 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_TFE, 64 /* 6 */ },
23703 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_GLC, 16 /* 4 */ },
23704 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_MubufOffset, 8 /* 3 */ },
23705 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_SLC, 32 /* 5 */ },
23706 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_TFE, 64 /* 6 */ },
23707 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_GLC, 64 /* 6 */ },
23708 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_MubufOffset, 32 /* 5 */ },
23709 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_SLC, 128 /* 7 */ },
23710 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_TFE, 256 /* 8 */ },
23711 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_GLC, 64 /* 6 */ },
23712 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_MubufOffset, 32 /* 5 */ },
23713 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_SLC, 128 /* 7 */ },
23714 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_TFE, 256 /* 8 */ },
23715 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_GLC, 64 /* 6 */ },
23716 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_MubufOffset, 32 /* 5 */ },
23717 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_SLC, 128 /* 7 */ },
23718 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_TFE, 256 /* 8 */ },
23719 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_GLC, 64 /* 6 */ },
23720 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_MubufOffset, 32 /* 5 */ },
23721 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_SLC, 128 /* 7 */ },
23722 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_TFE, 256 /* 8 */ },
23723 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_GLC, 64 /* 6 */ },
23724 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_MubufOffset, 32 /* 5 */ },
23725 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_SLC, 128 /* 7 */ },
23726 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_TFE, 256 /* 8 */ },
23727 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_GLC, 128 /* 7 */ },
23728 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_MubufOffset, 64 /* 6 */ },
23729 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_SLC, 256 /* 8 */ },
23730 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_TFE, 512 /* 9 */ },
23731 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_GLC, 128 /* 7 */ },
23732 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_MubufOffset, 64 /* 6 */ },
23733 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_SLC, 256 /* 8 */ },
23734 : { Feature_isGCN, 376 /* buffer_load_dwordx4 */, MCK_TFE, 512 /* 9 */ },
23735 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_GLC, 16 /* 4 */ },
23736 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_MubufOffset, 8 /* 3 */ },
23737 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_SLC, 32 /* 5 */ },
23738 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_TFE, 64 /* 6 */ },
23739 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_GLC, 16 /* 4 */ },
23740 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_MubufOffset, 8 /* 3 */ },
23741 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_SLC, 32 /* 5 */ },
23742 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_TFE, 64 /* 6 */ },
23743 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_GLC, 64 /* 6 */ },
23744 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_MubufOffset, 32 /* 5 */ },
23745 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_SLC, 128 /* 7 */ },
23746 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_TFE, 256 /* 8 */ },
23747 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_GLC, 64 /* 6 */ },
23748 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_MubufOffset, 32 /* 5 */ },
23749 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_SLC, 128 /* 7 */ },
23750 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_TFE, 256 /* 8 */ },
23751 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_GLC, 64 /* 6 */ },
23752 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_MubufOffset, 32 /* 5 */ },
23753 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_SLC, 128 /* 7 */ },
23754 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_TFE, 256 /* 8 */ },
23755 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_GLC, 64 /* 6 */ },
23756 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_MubufOffset, 32 /* 5 */ },
23757 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_SLC, 128 /* 7 */ },
23758 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_TFE, 256 /* 8 */ },
23759 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_GLC, 64 /* 6 */ },
23760 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_MubufOffset, 32 /* 5 */ },
23761 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_SLC, 128 /* 7 */ },
23762 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_TFE, 256 /* 8 */ },
23763 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_GLC, 128 /* 7 */ },
23764 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_MubufOffset, 64 /* 6 */ },
23765 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_SLC, 256 /* 8 */ },
23766 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_TFE, 512 /* 9 */ },
23767 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_GLC, 128 /* 7 */ },
23768 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_MubufOffset, 64 /* 6 */ },
23769 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_SLC, 256 /* 8 */ },
23770 : { Feature_isGCN, 396 /* buffer_load_format_x */, MCK_TFE, 512 /* 9 */ },
23771 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_GLC, 16 /* 4 */ },
23772 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_MubufOffset, 8 /* 3 */ },
23773 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_SLC, 32 /* 5 */ },
23774 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_TFE, 64 /* 6 */ },
23775 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_GLC, 16 /* 4 */ },
23776 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_MubufOffset, 8 /* 3 */ },
23777 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_SLC, 32 /* 5 */ },
23778 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_TFE, 64 /* 6 */ },
23779 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_GLC, 64 /* 6 */ },
23780 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_MubufOffset, 32 /* 5 */ },
23781 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_SLC, 128 /* 7 */ },
23782 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_TFE, 256 /* 8 */ },
23783 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_GLC, 64 /* 6 */ },
23784 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_MubufOffset, 32 /* 5 */ },
23785 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_SLC, 128 /* 7 */ },
23786 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_TFE, 256 /* 8 */ },
23787 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_GLC, 64 /* 6 */ },
23788 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_MubufOffset, 32 /* 5 */ },
23789 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_SLC, 128 /* 7 */ },
23790 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_TFE, 256 /* 8 */ },
23791 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_GLC, 64 /* 6 */ },
23792 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_MubufOffset, 32 /* 5 */ },
23793 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_SLC, 128 /* 7 */ },
23794 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_TFE, 256 /* 8 */ },
23795 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_GLC, 64 /* 6 */ },
23796 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_MubufOffset, 32 /* 5 */ },
23797 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_SLC, 128 /* 7 */ },
23798 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_TFE, 256 /* 8 */ },
23799 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_GLC, 128 /* 7 */ },
23800 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_MubufOffset, 64 /* 6 */ },
23801 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_SLC, 256 /* 8 */ },
23802 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_TFE, 512 /* 9 */ },
23803 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_GLC, 128 /* 7 */ },
23804 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_MubufOffset, 64 /* 6 */ },
23805 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_SLC, 256 /* 8 */ },
23806 : { Feature_isGCN, 417 /* buffer_load_format_xy */, MCK_TFE, 512 /* 9 */ },
23807 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_GLC, 16 /* 4 */ },
23808 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_MubufOffset, 8 /* 3 */ },
23809 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_SLC, 32 /* 5 */ },
23810 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_TFE, 64 /* 6 */ },
23811 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_GLC, 16 /* 4 */ },
23812 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_MubufOffset, 8 /* 3 */ },
23813 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_SLC, 32 /* 5 */ },
23814 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_TFE, 64 /* 6 */ },
23815 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_GLC, 64 /* 6 */ },
23816 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_MubufOffset, 32 /* 5 */ },
23817 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_SLC, 128 /* 7 */ },
23818 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_TFE, 256 /* 8 */ },
23819 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_GLC, 64 /* 6 */ },
23820 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_MubufOffset, 32 /* 5 */ },
23821 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_SLC, 128 /* 7 */ },
23822 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_TFE, 256 /* 8 */ },
23823 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_GLC, 64 /* 6 */ },
23824 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_MubufOffset, 32 /* 5 */ },
23825 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_SLC, 128 /* 7 */ },
23826 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_TFE, 256 /* 8 */ },
23827 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_GLC, 64 /* 6 */ },
23828 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_MubufOffset, 32 /* 5 */ },
23829 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_SLC, 128 /* 7 */ },
23830 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_TFE, 256 /* 8 */ },
23831 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_GLC, 64 /* 6 */ },
23832 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_MubufOffset, 32 /* 5 */ },
23833 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_SLC, 128 /* 7 */ },
23834 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_TFE, 256 /* 8 */ },
23835 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_GLC, 128 /* 7 */ },
23836 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_MubufOffset, 64 /* 6 */ },
23837 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_SLC, 256 /* 8 */ },
23838 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_TFE, 512 /* 9 */ },
23839 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_GLC, 128 /* 7 */ },
23840 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_MubufOffset, 64 /* 6 */ },
23841 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_SLC, 256 /* 8 */ },
23842 : { Feature_isGCN, 439 /* buffer_load_format_xyz */, MCK_TFE, 512 /* 9 */ },
23843 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_GLC, 16 /* 4 */ },
23844 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_MubufOffset, 8 /* 3 */ },
23845 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_SLC, 32 /* 5 */ },
23846 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_TFE, 64 /* 6 */ },
23847 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_GLC, 16 /* 4 */ },
23848 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_MubufOffset, 8 /* 3 */ },
23849 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_SLC, 32 /* 5 */ },
23850 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_TFE, 64 /* 6 */ },
23851 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_GLC, 64 /* 6 */ },
23852 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_MubufOffset, 32 /* 5 */ },
23853 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_SLC, 128 /* 7 */ },
23854 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_TFE, 256 /* 8 */ },
23855 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_GLC, 64 /* 6 */ },
23856 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_MubufOffset, 32 /* 5 */ },
23857 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_SLC, 128 /* 7 */ },
23858 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_TFE, 256 /* 8 */ },
23859 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_GLC, 64 /* 6 */ },
23860 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_MubufOffset, 32 /* 5 */ },
23861 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_SLC, 128 /* 7 */ },
23862 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_TFE, 256 /* 8 */ },
23863 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_GLC, 64 /* 6 */ },
23864 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_MubufOffset, 32 /* 5 */ },
23865 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_SLC, 128 /* 7 */ },
23866 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_TFE, 256 /* 8 */ },
23867 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_GLC, 64 /* 6 */ },
23868 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_MubufOffset, 32 /* 5 */ },
23869 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_SLC, 128 /* 7 */ },
23870 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_TFE, 256 /* 8 */ },
23871 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_GLC, 128 /* 7 */ },
23872 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_MubufOffset, 64 /* 6 */ },
23873 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_SLC, 256 /* 8 */ },
23874 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_TFE, 512 /* 9 */ },
23875 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_GLC, 128 /* 7 */ },
23876 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_MubufOffset, 64 /* 6 */ },
23877 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_SLC, 256 /* 8 */ },
23878 : { Feature_isGCN, 462 /* buffer_load_format_xyzw */, MCK_TFE, 512 /* 9 */ },
23879 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_GLC, 16 /* 4 */ },
23880 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_MubufOffset, 8 /* 3 */ },
23881 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_SLC, 32 /* 5 */ },
23882 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_TFE, 64 /* 6 */ },
23883 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_GLC, 16 /* 4 */ },
23884 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_MubufOffset, 8 /* 3 */ },
23885 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_SLC, 32 /* 5 */ },
23886 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_TFE, 64 /* 6 */ },
23887 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_GLC, 64 /* 6 */ },
23888 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_MubufOffset, 32 /* 5 */ },
23889 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_SLC, 128 /* 7 */ },
23890 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_TFE, 256 /* 8 */ },
23891 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_GLC, 64 /* 6 */ },
23892 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_MubufOffset, 32 /* 5 */ },
23893 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_SLC, 128 /* 7 */ },
23894 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_TFE, 256 /* 8 */ },
23895 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_GLC, 64 /* 6 */ },
23896 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_MubufOffset, 32 /* 5 */ },
23897 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_SLC, 128 /* 7 */ },
23898 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_TFE, 256 /* 8 */ },
23899 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_GLC, 64 /* 6 */ },
23900 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_MubufOffset, 32 /* 5 */ },
23901 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_SLC, 128 /* 7 */ },
23902 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_TFE, 256 /* 8 */ },
23903 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_GLC, 64 /* 6 */ },
23904 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_MubufOffset, 32 /* 5 */ },
23905 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_SLC, 128 /* 7 */ },
23906 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_TFE, 256 /* 8 */ },
23907 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_GLC, 128 /* 7 */ },
23908 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_MubufOffset, 64 /* 6 */ },
23909 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_SLC, 256 /* 8 */ },
23910 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_TFE, 512 /* 9 */ },
23911 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_GLC, 128 /* 7 */ },
23912 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_MubufOffset, 64 /* 6 */ },
23913 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_SLC, 256 /* 8 */ },
23914 : { Feature_isGCN, 486 /* buffer_load_sbyte */, MCK_TFE, 512 /* 9 */ },
23915 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_GLC, 16 /* 4 */ },
23916 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_MubufOffset, 8 /* 3 */ },
23917 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_SLC, 32 /* 5 */ },
23918 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_TFE, 64 /* 6 */ },
23919 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_GLC, 16 /* 4 */ },
23920 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_MubufOffset, 8 /* 3 */ },
23921 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_SLC, 32 /* 5 */ },
23922 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_TFE, 64 /* 6 */ },
23923 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_GLC, 64 /* 6 */ },
23924 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_MubufOffset, 32 /* 5 */ },
23925 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_SLC, 128 /* 7 */ },
23926 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_TFE, 256 /* 8 */ },
23927 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_GLC, 64 /* 6 */ },
23928 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_MubufOffset, 32 /* 5 */ },
23929 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_SLC, 128 /* 7 */ },
23930 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_TFE, 256 /* 8 */ },
23931 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_GLC, 64 /* 6 */ },
23932 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_MubufOffset, 32 /* 5 */ },
23933 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_SLC, 128 /* 7 */ },
23934 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_TFE, 256 /* 8 */ },
23935 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_GLC, 64 /* 6 */ },
23936 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_MubufOffset, 32 /* 5 */ },
23937 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_SLC, 128 /* 7 */ },
23938 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_TFE, 256 /* 8 */ },
23939 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_GLC, 64 /* 6 */ },
23940 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_MubufOffset, 32 /* 5 */ },
23941 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_SLC, 128 /* 7 */ },
23942 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_TFE, 256 /* 8 */ },
23943 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_GLC, 128 /* 7 */ },
23944 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_MubufOffset, 64 /* 6 */ },
23945 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_SLC, 256 /* 8 */ },
23946 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_TFE, 512 /* 9 */ },
23947 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_GLC, 128 /* 7 */ },
23948 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_MubufOffset, 64 /* 6 */ },
23949 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_SLC, 256 /* 8 */ },
23950 : { Feature_isGCN, 504 /* buffer_load_sshort */, MCK_TFE, 512 /* 9 */ },
23951 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_GLC, 16 /* 4 */ },
23952 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_MubufOffset, 8 /* 3 */ },
23953 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_SLC, 32 /* 5 */ },
23954 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_TFE, 64 /* 6 */ },
23955 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_GLC, 16 /* 4 */ },
23956 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_MubufOffset, 8 /* 3 */ },
23957 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_SLC, 32 /* 5 */ },
23958 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_TFE, 64 /* 6 */ },
23959 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_GLC, 64 /* 6 */ },
23960 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_MubufOffset, 32 /* 5 */ },
23961 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_SLC, 128 /* 7 */ },
23962 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_TFE, 256 /* 8 */ },
23963 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_GLC, 64 /* 6 */ },
23964 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_MubufOffset, 32 /* 5 */ },
23965 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_SLC, 128 /* 7 */ },
23966 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_TFE, 256 /* 8 */ },
23967 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_GLC, 64 /* 6 */ },
23968 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_MubufOffset, 32 /* 5 */ },
23969 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_SLC, 128 /* 7 */ },
23970 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_TFE, 256 /* 8 */ },
23971 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_GLC, 64 /* 6 */ },
23972 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_MubufOffset, 32 /* 5 */ },
23973 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_SLC, 128 /* 7 */ },
23974 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_TFE, 256 /* 8 */ },
23975 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_GLC, 64 /* 6 */ },
23976 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_MubufOffset, 32 /* 5 */ },
23977 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_SLC, 128 /* 7 */ },
23978 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_TFE, 256 /* 8 */ },
23979 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_GLC, 128 /* 7 */ },
23980 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_MubufOffset, 64 /* 6 */ },
23981 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_SLC, 256 /* 8 */ },
23982 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_TFE, 512 /* 9 */ },
23983 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_GLC, 128 /* 7 */ },
23984 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_MubufOffset, 64 /* 6 */ },
23985 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_SLC, 256 /* 8 */ },
23986 : { Feature_isGCN, 523 /* buffer_load_ubyte */, MCK_TFE, 512 /* 9 */ },
23987 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_GLC, 16 /* 4 */ },
23988 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_MubufOffset, 8 /* 3 */ },
23989 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_SLC, 32 /* 5 */ },
23990 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_TFE, 64 /* 6 */ },
23991 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_GLC, 16 /* 4 */ },
23992 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_MubufOffset, 8 /* 3 */ },
23993 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_SLC, 32 /* 5 */ },
23994 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_TFE, 64 /* 6 */ },
23995 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_GLC, 64 /* 6 */ },
23996 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_MubufOffset, 32 /* 5 */ },
23997 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_SLC, 128 /* 7 */ },
23998 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_TFE, 256 /* 8 */ },
23999 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_GLC, 64 /* 6 */ },
24000 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_MubufOffset, 32 /* 5 */ },
24001 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_SLC, 128 /* 7 */ },
24002 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_TFE, 256 /* 8 */ },
24003 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_GLC, 64 /* 6 */ },
24004 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_MubufOffset, 32 /* 5 */ },
24005 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_SLC, 128 /* 7 */ },
24006 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_TFE, 256 /* 8 */ },
24007 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_GLC, 64 /* 6 */ },
24008 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_MubufOffset, 32 /* 5 */ },
24009 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_SLC, 128 /* 7 */ },
24010 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_TFE, 256 /* 8 */ },
24011 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_GLC, 64 /* 6 */ },
24012 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_MubufOffset, 32 /* 5 */ },
24013 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_SLC, 128 /* 7 */ },
24014 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_TFE, 256 /* 8 */ },
24015 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_GLC, 128 /* 7 */ },
24016 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_MubufOffset, 64 /* 6 */ },
24017 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_SLC, 256 /* 8 */ },
24018 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_TFE, 512 /* 9 */ },
24019 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_GLC, 128 /* 7 */ },
24020 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_MubufOffset, 64 /* 6 */ },
24021 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_SLC, 256 /* 8 */ },
24022 : { Feature_isGCN, 541 /* buffer_load_ushort */, MCK_TFE, 512 /* 9 */ },
24023 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_GLC, 16 /* 4 */ },
24024 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_MubufOffset, 8 /* 3 */ },
24025 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_SLC, 32 /* 5 */ },
24026 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_TFE, 64 /* 6 */ },
24027 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_GLC, 16 /* 4 */ },
24028 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_MubufOffset, 8 /* 3 */ },
24029 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_SLC, 32 /* 5 */ },
24030 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_TFE, 64 /* 6 */ },
24031 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_GLC, 64 /* 6 */ },
24032 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_MubufOffset, 32 /* 5 */ },
24033 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_SLC, 128 /* 7 */ },
24034 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_TFE, 256 /* 8 */ },
24035 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_GLC, 64 /* 6 */ },
24036 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_MubufOffset, 32 /* 5 */ },
24037 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_SLC, 128 /* 7 */ },
24038 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_TFE, 256 /* 8 */ },
24039 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_GLC, 64 /* 6 */ },
24040 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_MubufOffset, 32 /* 5 */ },
24041 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_SLC, 128 /* 7 */ },
24042 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_TFE, 256 /* 8 */ },
24043 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_GLC, 64 /* 6 */ },
24044 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_MubufOffset, 32 /* 5 */ },
24045 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_SLC, 128 /* 7 */ },
24046 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_TFE, 256 /* 8 */ },
24047 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_GLC, 64 /* 6 */ },
24048 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_MubufOffset, 32 /* 5 */ },
24049 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_SLC, 128 /* 7 */ },
24050 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_TFE, 256 /* 8 */ },
24051 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_GLC, 128 /* 7 */ },
24052 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_MubufOffset, 64 /* 6 */ },
24053 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_SLC, 256 /* 8 */ },
24054 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_TFE, 512 /* 9 */ },
24055 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_GLC, 128 /* 7 */ },
24056 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_MubufOffset, 64 /* 6 */ },
24057 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_SLC, 256 /* 8 */ },
24058 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_TFE, 512 /* 9 */ },
24059 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_GLC, 128 /* 7 */ },
24060 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_MubufOffset, 64 /* 6 */ },
24061 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_SLC, 256 /* 8 */ },
24062 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_TFE, 512 /* 9 */ },
24063 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_GLC, 128 /* 7 */ },
24064 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_MubufOffset, 64 /* 6 */ },
24065 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_SLC, 256 /* 8 */ },
24066 : { Feature_isGCN, 560 /* buffer_store_byte */, MCK_TFE, 512 /* 9 */ },
24067 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_GLC, 16 /* 4 */ },
24068 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_MubufOffset, 8 /* 3 */ },
24069 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_SLC, 32 /* 5 */ },
24070 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_TFE, 64 /* 6 */ },
24071 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_GLC, 16 /* 4 */ },
24072 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_MubufOffset, 8 /* 3 */ },
24073 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_SLC, 32 /* 5 */ },
24074 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_TFE, 64 /* 6 */ },
24075 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_GLC, 64 /* 6 */ },
24076 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_MubufOffset, 32 /* 5 */ },
24077 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_SLC, 128 /* 7 */ },
24078 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_TFE, 256 /* 8 */ },
24079 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_GLC, 64 /* 6 */ },
24080 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_MubufOffset, 32 /* 5 */ },
24081 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_SLC, 128 /* 7 */ },
24082 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_TFE, 256 /* 8 */ },
24083 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_GLC, 64 /* 6 */ },
24084 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_MubufOffset, 32 /* 5 */ },
24085 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_SLC, 128 /* 7 */ },
24086 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_TFE, 256 /* 8 */ },
24087 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_GLC, 64 /* 6 */ },
24088 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_MubufOffset, 32 /* 5 */ },
24089 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_SLC, 128 /* 7 */ },
24090 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_TFE, 256 /* 8 */ },
24091 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_GLC, 64 /* 6 */ },
24092 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_MubufOffset, 32 /* 5 */ },
24093 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_SLC, 128 /* 7 */ },
24094 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_TFE, 256 /* 8 */ },
24095 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_GLC, 128 /* 7 */ },
24096 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_MubufOffset, 64 /* 6 */ },
24097 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_SLC, 256 /* 8 */ },
24098 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_TFE, 512 /* 9 */ },
24099 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_GLC, 128 /* 7 */ },
24100 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_MubufOffset, 64 /* 6 */ },
24101 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_SLC, 256 /* 8 */ },
24102 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_TFE, 512 /* 9 */ },
24103 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_GLC, 128 /* 7 */ },
24104 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_MubufOffset, 64 /* 6 */ },
24105 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_SLC, 256 /* 8 */ },
24106 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_TFE, 512 /* 9 */ },
24107 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_GLC, 128 /* 7 */ },
24108 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_MubufOffset, 64 /* 6 */ },
24109 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_SLC, 256 /* 8 */ },
24110 : { Feature_isGCN, 578 /* buffer_store_dword */, MCK_TFE, 512 /* 9 */ },
24111 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_GLC, 16 /* 4 */ },
24112 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_MubufOffset, 8 /* 3 */ },
24113 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_SLC, 32 /* 5 */ },
24114 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_TFE, 64 /* 6 */ },
24115 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_GLC, 16 /* 4 */ },
24116 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_MubufOffset, 8 /* 3 */ },
24117 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_SLC, 32 /* 5 */ },
24118 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_TFE, 64 /* 6 */ },
24119 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_GLC, 64 /* 6 */ },
24120 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_MubufOffset, 32 /* 5 */ },
24121 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_SLC, 128 /* 7 */ },
24122 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_TFE, 256 /* 8 */ },
24123 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_GLC, 64 /* 6 */ },
24124 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_MubufOffset, 32 /* 5 */ },
24125 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_SLC, 128 /* 7 */ },
24126 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_TFE, 256 /* 8 */ },
24127 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_GLC, 64 /* 6 */ },
24128 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_MubufOffset, 32 /* 5 */ },
24129 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_SLC, 128 /* 7 */ },
24130 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_TFE, 256 /* 8 */ },
24131 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_GLC, 64 /* 6 */ },
24132 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_MubufOffset, 32 /* 5 */ },
24133 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_SLC, 128 /* 7 */ },
24134 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_TFE, 256 /* 8 */ },
24135 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_GLC, 64 /* 6 */ },
24136 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_MubufOffset, 32 /* 5 */ },
24137 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_SLC, 128 /* 7 */ },
24138 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_TFE, 256 /* 8 */ },
24139 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_GLC, 128 /* 7 */ },
24140 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_MubufOffset, 64 /* 6 */ },
24141 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_SLC, 256 /* 8 */ },
24142 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_TFE, 512 /* 9 */ },
24143 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_GLC, 128 /* 7 */ },
24144 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_MubufOffset, 64 /* 6 */ },
24145 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_SLC, 256 /* 8 */ },
24146 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_TFE, 512 /* 9 */ },
24147 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_GLC, 128 /* 7 */ },
24148 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_MubufOffset, 64 /* 6 */ },
24149 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_SLC, 256 /* 8 */ },
24150 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_TFE, 512 /* 9 */ },
24151 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_GLC, 128 /* 7 */ },
24152 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_MubufOffset, 64 /* 6 */ },
24153 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_SLC, 256 /* 8 */ },
24154 : { Feature_isGCN, 597 /* buffer_store_dwordx2 */, MCK_TFE, 512 /* 9 */ },
24155 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_GLC, 16 /* 4 */ },
24156 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_MubufOffset, 8 /* 3 */ },
24157 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_SLC, 32 /* 5 */ },
24158 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_TFE, 64 /* 6 */ },
24159 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_GLC, 16 /* 4 */ },
24160 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_MubufOffset, 8 /* 3 */ },
24161 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_SLC, 32 /* 5 */ },
24162 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_TFE, 64 /* 6 */ },
24163 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_GLC, 64 /* 6 */ },
24164 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_MubufOffset, 32 /* 5 */ },
24165 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_SLC, 128 /* 7 */ },
24166 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_TFE, 256 /* 8 */ },
24167 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_GLC, 64 /* 6 */ },
24168 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_MubufOffset, 32 /* 5 */ },
24169 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_SLC, 128 /* 7 */ },
24170 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_TFE, 256 /* 8 */ },
24171 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_GLC, 64 /* 6 */ },
24172 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_MubufOffset, 32 /* 5 */ },
24173 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_SLC, 128 /* 7 */ },
24174 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_TFE, 256 /* 8 */ },
24175 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_GLC, 64 /* 6 */ },
24176 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_MubufOffset, 32 /* 5 */ },
24177 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_SLC, 128 /* 7 */ },
24178 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_TFE, 256 /* 8 */ },
24179 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_GLC, 64 /* 6 */ },
24180 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_MubufOffset, 32 /* 5 */ },
24181 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_SLC, 128 /* 7 */ },
24182 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_TFE, 256 /* 8 */ },
24183 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_GLC, 128 /* 7 */ },
24184 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_MubufOffset, 64 /* 6 */ },
24185 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_SLC, 256 /* 8 */ },
24186 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_TFE, 512 /* 9 */ },
24187 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_GLC, 128 /* 7 */ },
24188 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_MubufOffset, 64 /* 6 */ },
24189 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_SLC, 256 /* 8 */ },
24190 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_TFE, 512 /* 9 */ },
24191 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_GLC, 128 /* 7 */ },
24192 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_MubufOffset, 64 /* 6 */ },
24193 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_SLC, 256 /* 8 */ },
24194 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_TFE, 512 /* 9 */ },
24195 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_GLC, 128 /* 7 */ },
24196 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_MubufOffset, 64 /* 6 */ },
24197 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_SLC, 256 /* 8 */ },
24198 : { Feature_isGCN, 618 /* buffer_store_dwordx4 */, MCK_TFE, 512 /* 9 */ },
24199 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_GLC, 16 /* 4 */ },
24200 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_MubufOffset, 8 /* 3 */ },
24201 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_SLC, 32 /* 5 */ },
24202 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_TFE, 64 /* 6 */ },
24203 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_GLC, 16 /* 4 */ },
24204 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_MubufOffset, 8 /* 3 */ },
24205 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_SLC, 32 /* 5 */ },
24206 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_TFE, 64 /* 6 */ },
24207 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_GLC, 64 /* 6 */ },
24208 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_MubufOffset, 32 /* 5 */ },
24209 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_SLC, 128 /* 7 */ },
24210 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_TFE, 256 /* 8 */ },
24211 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_GLC, 64 /* 6 */ },
24212 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_MubufOffset, 32 /* 5 */ },
24213 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_SLC, 128 /* 7 */ },
24214 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_TFE, 256 /* 8 */ },
24215 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_GLC, 64 /* 6 */ },
24216 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_MubufOffset, 32 /* 5 */ },
24217 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_SLC, 128 /* 7 */ },
24218 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_TFE, 256 /* 8 */ },
24219 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_GLC, 64 /* 6 */ },
24220 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_MubufOffset, 32 /* 5 */ },
24221 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_SLC, 128 /* 7 */ },
24222 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_TFE, 256 /* 8 */ },
24223 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_GLC, 64 /* 6 */ },
24224 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_MubufOffset, 32 /* 5 */ },
24225 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_SLC, 128 /* 7 */ },
24226 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_TFE, 256 /* 8 */ },
24227 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_GLC, 128 /* 7 */ },
24228 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_MubufOffset, 64 /* 6 */ },
24229 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_SLC, 256 /* 8 */ },
24230 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_TFE, 512 /* 9 */ },
24231 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_GLC, 128 /* 7 */ },
24232 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_MubufOffset, 64 /* 6 */ },
24233 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_SLC, 256 /* 8 */ },
24234 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_TFE, 512 /* 9 */ },
24235 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_GLC, 128 /* 7 */ },
24236 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_MubufOffset, 64 /* 6 */ },
24237 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_SLC, 256 /* 8 */ },
24238 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_TFE, 512 /* 9 */ },
24239 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_GLC, 128 /* 7 */ },
24240 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_MubufOffset, 64 /* 6 */ },
24241 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_SLC, 256 /* 8 */ },
24242 : { Feature_isGCN, 639 /* buffer_store_format_x */, MCK_TFE, 512 /* 9 */ },
24243 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_GLC, 16 /* 4 */ },
24244 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_MubufOffset, 8 /* 3 */ },
24245 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_SLC, 32 /* 5 */ },
24246 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_TFE, 64 /* 6 */ },
24247 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_GLC, 16 /* 4 */ },
24248 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_MubufOffset, 8 /* 3 */ },
24249 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_SLC, 32 /* 5 */ },
24250 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_TFE, 64 /* 6 */ },
24251 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_GLC, 64 /* 6 */ },
24252 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_MubufOffset, 32 /* 5 */ },
24253 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_SLC, 128 /* 7 */ },
24254 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_TFE, 256 /* 8 */ },
24255 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_GLC, 64 /* 6 */ },
24256 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_MubufOffset, 32 /* 5 */ },
24257 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_SLC, 128 /* 7 */ },
24258 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_TFE, 256 /* 8 */ },
24259 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_GLC, 64 /* 6 */ },
24260 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_MubufOffset, 32 /* 5 */ },
24261 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_SLC, 128 /* 7 */ },
24262 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_TFE, 256 /* 8 */ },
24263 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_GLC, 64 /* 6 */ },
24264 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_MubufOffset, 32 /* 5 */ },
24265 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_SLC, 128 /* 7 */ },
24266 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_TFE, 256 /* 8 */ },
24267 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_GLC, 64 /* 6 */ },
24268 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_MubufOffset, 32 /* 5 */ },
24269 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_SLC, 128 /* 7 */ },
24270 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_TFE, 256 /* 8 */ },
24271 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_GLC, 128 /* 7 */ },
24272 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_MubufOffset, 64 /* 6 */ },
24273 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_SLC, 256 /* 8 */ },
24274 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_TFE, 512 /* 9 */ },
24275 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_GLC, 128 /* 7 */ },
24276 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_MubufOffset, 64 /* 6 */ },
24277 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_SLC, 256 /* 8 */ },
24278 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_TFE, 512 /* 9 */ },
24279 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_GLC, 128 /* 7 */ },
24280 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_MubufOffset, 64 /* 6 */ },
24281 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_SLC, 256 /* 8 */ },
24282 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_TFE, 512 /* 9 */ },
24283 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_GLC, 128 /* 7 */ },
24284 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_MubufOffset, 64 /* 6 */ },
24285 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_SLC, 256 /* 8 */ },
24286 : { Feature_isGCN, 661 /* buffer_store_format_xy */, MCK_TFE, 512 /* 9 */ },
24287 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_GLC, 16 /* 4 */ },
24288 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_MubufOffset, 8 /* 3 */ },
24289 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_SLC, 32 /* 5 */ },
24290 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_TFE, 64 /* 6 */ },
24291 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_GLC, 16 /* 4 */ },
24292 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_MubufOffset, 8 /* 3 */ },
24293 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_SLC, 32 /* 5 */ },
24294 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_TFE, 64 /* 6 */ },
24295 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_GLC, 64 /* 6 */ },
24296 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_MubufOffset, 32 /* 5 */ },
24297 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_SLC, 128 /* 7 */ },
24298 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_TFE, 256 /* 8 */ },
24299 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_GLC, 64 /* 6 */ },
24300 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_MubufOffset, 32 /* 5 */ },
24301 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_SLC, 128 /* 7 */ },
24302 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_TFE, 256 /* 8 */ },
24303 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_GLC, 64 /* 6 */ },
24304 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_MubufOffset, 32 /* 5 */ },
24305 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_SLC, 128 /* 7 */ },
24306 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_TFE, 256 /* 8 */ },
24307 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_GLC, 64 /* 6 */ },
24308 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_MubufOffset, 32 /* 5 */ },
24309 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_SLC, 128 /* 7 */ },
24310 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_TFE, 256 /* 8 */ },
24311 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_GLC, 64 /* 6 */ },
24312 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_MubufOffset, 32 /* 5 */ },
24313 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_SLC, 128 /* 7 */ },
24314 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_TFE, 256 /* 8 */ },
24315 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_GLC, 128 /* 7 */ },
24316 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_MubufOffset, 64 /* 6 */ },
24317 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_SLC, 256 /* 8 */ },
24318 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_TFE, 512 /* 9 */ },
24319 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_GLC, 128 /* 7 */ },
24320 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_MubufOffset, 64 /* 6 */ },
24321 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_SLC, 256 /* 8 */ },
24322 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_TFE, 512 /* 9 */ },
24323 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_GLC, 128 /* 7 */ },
24324 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_MubufOffset, 64 /* 6 */ },
24325 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_SLC, 256 /* 8 */ },
24326 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_TFE, 512 /* 9 */ },
24327 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_GLC, 128 /* 7 */ },
24328 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_MubufOffset, 64 /* 6 */ },
24329 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_SLC, 256 /* 8 */ },
24330 : { Feature_isGCN, 684 /* buffer_store_format_xyz */, MCK_TFE, 512 /* 9 */ },
24331 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_GLC, 16 /* 4 */ },
24332 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_MubufOffset, 8 /* 3 */ },
24333 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_SLC, 32 /* 5 */ },
24334 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_TFE, 64 /* 6 */ },
24335 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_GLC, 16 /* 4 */ },
24336 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_MubufOffset, 8 /* 3 */ },
24337 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_SLC, 32 /* 5 */ },
24338 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_TFE, 64 /* 6 */ },
24339 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_GLC, 64 /* 6 */ },
24340 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_MubufOffset, 32 /* 5 */ },
24341 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_SLC, 128 /* 7 */ },
24342 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_TFE, 256 /* 8 */ },
24343 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_GLC, 64 /* 6 */ },
24344 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_MubufOffset, 32 /* 5 */ },
24345 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_SLC, 128 /* 7 */ },
24346 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_TFE, 256 /* 8 */ },
24347 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_GLC, 64 /* 6 */ },
24348 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_MubufOffset, 32 /* 5 */ },
24349 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_SLC, 128 /* 7 */ },
24350 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_TFE, 256 /* 8 */ },
24351 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_GLC, 64 /* 6 */ },
24352 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_MubufOffset, 32 /* 5 */ },
24353 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_SLC, 128 /* 7 */ },
24354 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_TFE, 256 /* 8 */ },
24355 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_GLC, 64 /* 6 */ },
24356 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_MubufOffset, 32 /* 5 */ },
24357 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_SLC, 128 /* 7 */ },
24358 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_TFE, 256 /* 8 */ },
24359 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_GLC, 128 /* 7 */ },
24360 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_MubufOffset, 64 /* 6 */ },
24361 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_SLC, 256 /* 8 */ },
24362 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_TFE, 512 /* 9 */ },
24363 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_GLC, 128 /* 7 */ },
24364 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_MubufOffset, 64 /* 6 */ },
24365 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_SLC, 256 /* 8 */ },
24366 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_TFE, 512 /* 9 */ },
24367 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_GLC, 128 /* 7 */ },
24368 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_MubufOffset, 64 /* 6 */ },
24369 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_SLC, 256 /* 8 */ },
24370 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_TFE, 512 /* 9 */ },
24371 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_GLC, 128 /* 7 */ },
24372 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_MubufOffset, 64 /* 6 */ },
24373 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_SLC, 256 /* 8 */ },
24374 : { Feature_isGCN, 708 /* buffer_store_format_xyzw */, MCK_TFE, 512 /* 9 */ },
24375 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_GLC, 16 /* 4 */ },
24376 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_MubufOffset, 8 /* 3 */ },
24377 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_SLC, 32 /* 5 */ },
24378 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_TFE, 64 /* 6 */ },
24379 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_GLC, 16 /* 4 */ },
24380 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_MubufOffset, 8 /* 3 */ },
24381 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_SLC, 32 /* 5 */ },
24382 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_TFE, 64 /* 6 */ },
24383 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_GLC, 64 /* 6 */ },
24384 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_MubufOffset, 32 /* 5 */ },
24385 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_SLC, 128 /* 7 */ },
24386 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_TFE, 256 /* 8 */ },
24387 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_GLC, 64 /* 6 */ },
24388 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_MubufOffset, 32 /* 5 */ },
24389 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_SLC, 128 /* 7 */ },
24390 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_TFE, 256 /* 8 */ },
24391 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_GLC, 64 /* 6 */ },
24392 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_MubufOffset, 32 /* 5 */ },
24393 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_SLC, 128 /* 7 */ },
24394 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_TFE, 256 /* 8 */ },
24395 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_GLC, 64 /* 6 */ },
24396 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_MubufOffset, 32 /* 5 */ },
24397 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_SLC, 128 /* 7 */ },
24398 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_TFE, 256 /* 8 */ },
24399 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_GLC, 64 /* 6 */ },
24400 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_MubufOffset, 32 /* 5 */ },
24401 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_SLC, 128 /* 7 */ },
24402 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_TFE, 256 /* 8 */ },
24403 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_GLC, 128 /* 7 */ },
24404 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_MubufOffset, 64 /* 6 */ },
24405 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_SLC, 256 /* 8 */ },
24406 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_TFE, 512 /* 9 */ },
24407 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_GLC, 128 /* 7 */ },
24408 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_MubufOffset, 64 /* 6 */ },
24409 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_SLC, 256 /* 8 */ },
24410 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_TFE, 512 /* 9 */ },
24411 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_GLC, 128 /* 7 */ },
24412 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_MubufOffset, 64 /* 6 */ },
24413 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_SLC, 256 /* 8 */ },
24414 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_TFE, 512 /* 9 */ },
24415 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_GLC, 128 /* 7 */ },
24416 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_MubufOffset, 64 /* 6 */ },
24417 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_SLC, 256 /* 8 */ },
24418 : { Feature_isGCN, 733 /* buffer_store_short */, MCK_TFE, 512 /* 9 */ },
24419 : { Feature_isGCN, 752 /* ds_add_rtn_u32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24420 : { Feature_isGCN, 752 /* ds_add_rtn_u32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24421 : { Feature_isGCN, 752 /* ds_add_rtn_u32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24422 : { Feature_isGCN, 752 /* ds_add_rtn_u32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24423 : { Feature_isGCN, 767 /* ds_add_rtn_u64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24424 : { Feature_isGCN, 767 /* ds_add_rtn_u64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24425 : { Feature_isGCN, 767 /* ds_add_rtn_u64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24426 : { Feature_isGCN, 767 /* ds_add_rtn_u64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24427 : { Feature_isGCN, 782 /* ds_add_src2_u32 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24428 : { Feature_isGCN, 782 /* ds_add_src2_u32 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24429 : { Feature_isGCN, 782 /* ds_add_src2_u32 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24430 : { Feature_isGCN, 782 /* ds_add_src2_u32 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24431 : { Feature_isGCN, 798 /* ds_add_src2_u64 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24432 : { Feature_isGCN, 798 /* ds_add_src2_u64 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24433 : { Feature_isGCN, 798 /* ds_add_src2_u64 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24434 : { Feature_isGCN, 798 /* ds_add_src2_u64 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24435 : { Feature_isGCN, 814 /* ds_add_u32 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24436 : { Feature_isGCN, 814 /* ds_add_u32 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24437 : { Feature_isGCN, 814 /* ds_add_u32 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24438 : { Feature_isGCN, 814 /* ds_add_u32 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24439 : { Feature_isGCN, 825 /* ds_add_u64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24440 : { Feature_isGCN, 825 /* ds_add_u64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24441 : { Feature_isGCN, 825 /* ds_add_u64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24442 : { Feature_isGCN, 825 /* ds_add_u64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24443 : { Feature_isGCN, 836 /* ds_and_b32 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24444 : { Feature_isGCN, 836 /* ds_and_b32 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24445 : { Feature_isGCN, 836 /* ds_and_b32 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24446 : { Feature_isGCN, 836 /* ds_and_b32 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24447 : { Feature_isGCN, 847 /* ds_and_b64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24448 : { Feature_isGCN, 847 /* ds_and_b64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24449 : { Feature_isGCN, 847 /* ds_and_b64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24450 : { Feature_isGCN, 847 /* ds_and_b64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24451 : { Feature_isGCN, 858 /* ds_and_rtn_b32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24452 : { Feature_isGCN, 858 /* ds_and_rtn_b32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24453 : { Feature_isGCN, 858 /* ds_and_rtn_b32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24454 : { Feature_isGCN, 858 /* ds_and_rtn_b32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24455 : { Feature_isGCN, 873 /* ds_and_rtn_b64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24456 : { Feature_isGCN, 873 /* ds_and_rtn_b64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24457 : { Feature_isGCN, 873 /* ds_and_rtn_b64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24458 : { Feature_isGCN, 873 /* ds_and_rtn_b64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24459 : { Feature_isGCN, 888 /* ds_and_src2_b64 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24460 : { Feature_isGCN, 888 /* ds_and_src2_b64 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24461 : { Feature_isGCN, 888 /* ds_and_src2_b64 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24462 : { Feature_isGCN, 888 /* ds_and_src2_b64 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24463 : { Feature_isGCN, 904 /* ds_and_src_b32 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24464 : { Feature_isGCN, 904 /* ds_and_src_b32 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24465 : { Feature_isGCN, 904 /* ds_and_src_b32 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24466 : { Feature_isGCN, 904 /* ds_and_src_b32 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24467 : { Feature_isGCN, 919 /* ds_append */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24468 : { Feature_isGCN, 919 /* ds_append */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24469 : { Feature_isGCN, 919 /* ds_append */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24470 : { Feature_isGCN, 919 /* ds_append */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24471 : { Feature_isGCN, 929 /* ds_cmpst_b32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24472 : { Feature_isGCN, 929 /* ds_cmpst_b32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24473 : { Feature_isGCN, 929 /* ds_cmpst_b32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24474 : { Feature_isGCN, 929 /* ds_cmpst_b32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24475 : { Feature_isGCN, 942 /* ds_cmpst_b64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24476 : { Feature_isGCN, 942 /* ds_cmpst_b64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24477 : { Feature_isGCN, 942 /* ds_cmpst_b64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24478 : { Feature_isGCN, 942 /* ds_cmpst_b64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24479 : { Feature_isGCN, 955 /* ds_cmpst_f32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24480 : { Feature_isGCN, 955 /* ds_cmpst_f32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24481 : { Feature_isGCN, 955 /* ds_cmpst_f32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24482 : { Feature_isGCN, 955 /* ds_cmpst_f32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24483 : { Feature_isGCN, 968 /* ds_cmpst_f64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24484 : { Feature_isGCN, 968 /* ds_cmpst_f64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24485 : { Feature_isGCN, 968 /* ds_cmpst_f64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24486 : { Feature_isGCN, 968 /* ds_cmpst_f64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24487 : { Feature_isGCN, 981 /* ds_cmpst_rtn_b32 */, MCK_DSOffsetparseDSOptionalOps, 16 /* 4 */ },
24488 : { Feature_isGCN, 981 /* ds_cmpst_rtn_b32 */, MCK_GDSparseDSOptionalOps, 32 /* 5 */ },
24489 : { Feature_isGCN, 981 /* ds_cmpst_rtn_b32 */, MCK_DSOffsetparseDSOptionalOps, 16 /* 4 */ },
24490 : { Feature_isGCN, 981 /* ds_cmpst_rtn_b32 */, MCK_GDSparseDSOptionalOps, 32 /* 5 */ },
24491 : { Feature_isGCN, 998 /* ds_cmpst_rtn_b64 */, MCK_DSOffsetparseDSOptionalOps, 16 /* 4 */ },
24492 : { Feature_isGCN, 998 /* ds_cmpst_rtn_b64 */, MCK_GDSparseDSOptionalOps, 32 /* 5 */ },
24493 : { Feature_isGCN, 998 /* ds_cmpst_rtn_b64 */, MCK_DSOffsetparseDSOptionalOps, 16 /* 4 */ },
24494 : { Feature_isGCN, 998 /* ds_cmpst_rtn_b64 */, MCK_GDSparseDSOptionalOps, 32 /* 5 */ },
24495 : { Feature_isGCN, 1015 /* ds_cmpst_rtn_f32 */, MCK_DSOffsetparseDSOptionalOps, 16 /* 4 */ },
24496 : { Feature_isGCN, 1015 /* ds_cmpst_rtn_f32 */, MCK_GDSparseDSOptionalOps, 32 /* 5 */ },
24497 : { Feature_isGCN, 1015 /* ds_cmpst_rtn_f32 */, MCK_DSOffsetparseDSOptionalOps, 16 /* 4 */ },
24498 : { Feature_isGCN, 1015 /* ds_cmpst_rtn_f32 */, MCK_GDSparseDSOptionalOps, 32 /* 5 */ },
24499 : { Feature_isGCN, 1032 /* ds_cmpst_rtn_f64 */, MCK_DSOffsetparseDSOptionalOps, 16 /* 4 */ },
24500 : { Feature_isGCN, 1032 /* ds_cmpst_rtn_f64 */, MCK_GDSparseDSOptionalOps, 32 /* 5 */ },
24501 : { Feature_isGCN, 1032 /* ds_cmpst_rtn_f64 */, MCK_DSOffsetparseDSOptionalOps, 16 /* 4 */ },
24502 : { Feature_isGCN, 1032 /* ds_cmpst_rtn_f64 */, MCK_GDSparseDSOptionalOps, 32 /* 5 */ },
24503 : { Feature_isGCN, 1049 /* ds_consume */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24504 : { Feature_isGCN, 1049 /* ds_consume */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24505 : { Feature_isGCN, 1049 /* ds_consume */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24506 : { Feature_isGCN, 1049 /* ds_consume */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24507 : { Feature_isGCN, 1060 /* ds_dec_rtn_u32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24508 : { Feature_isGCN, 1060 /* ds_dec_rtn_u32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24509 : { Feature_isGCN, 1060 /* ds_dec_rtn_u32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24510 : { Feature_isGCN, 1060 /* ds_dec_rtn_u32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24511 : { Feature_isGCN, 1075 /* ds_dec_rtn_u64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24512 : { Feature_isGCN, 1075 /* ds_dec_rtn_u64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24513 : { Feature_isGCN, 1075 /* ds_dec_rtn_u64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24514 : { Feature_isGCN, 1075 /* ds_dec_rtn_u64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24515 : { Feature_isGCN, 1090 /* ds_dec_src2_u32 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24516 : { Feature_isGCN, 1090 /* ds_dec_src2_u32 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24517 : { Feature_isGCN, 1090 /* ds_dec_src2_u32 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24518 : { Feature_isGCN, 1090 /* ds_dec_src2_u32 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24519 : { Feature_isGCN, 1106 /* ds_dec_src2_u64 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24520 : { Feature_isGCN, 1106 /* ds_dec_src2_u64 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24521 : { Feature_isGCN, 1106 /* ds_dec_src2_u64 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24522 : { Feature_isGCN, 1106 /* ds_dec_src2_u64 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24523 : { Feature_isGCN, 1122 /* ds_dec_u32 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24524 : { Feature_isGCN, 1122 /* ds_dec_u32 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24525 : { Feature_isGCN, 1122 /* ds_dec_u32 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24526 : { Feature_isGCN, 1122 /* ds_dec_u32 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24527 : { Feature_isGCN, 1133 /* ds_dec_u64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24528 : { Feature_isGCN, 1133 /* ds_dec_u64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24529 : { Feature_isGCN, 1133 /* ds_dec_u64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24530 : { Feature_isGCN, 1133 /* ds_dec_u64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24531 : { Feature_isGCN, 1214 /* ds_inc_rtn_u32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24532 : { Feature_isGCN, 1214 /* ds_inc_rtn_u32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24533 : { Feature_isGCN, 1214 /* ds_inc_rtn_u32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24534 : { Feature_isGCN, 1214 /* ds_inc_rtn_u32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24535 : { Feature_isGCN, 1229 /* ds_inc_rtn_u64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24536 : { Feature_isGCN, 1229 /* ds_inc_rtn_u64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24537 : { Feature_isGCN, 1229 /* ds_inc_rtn_u64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24538 : { Feature_isGCN, 1229 /* ds_inc_rtn_u64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24539 : { Feature_isGCN, 1244 /* ds_inc_src2_u32 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24540 : { Feature_isGCN, 1244 /* ds_inc_src2_u32 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24541 : { Feature_isGCN, 1244 /* ds_inc_src2_u32 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24542 : { Feature_isGCN, 1244 /* ds_inc_src2_u32 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24543 : { Feature_isGCN, 1260 /* ds_inc_src2_u64 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24544 : { Feature_isGCN, 1260 /* ds_inc_src2_u64 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24545 : { Feature_isGCN, 1260 /* ds_inc_src2_u64 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24546 : { Feature_isGCN, 1260 /* ds_inc_src2_u64 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24547 : { Feature_isGCN, 1276 /* ds_inc_u32 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24548 : { Feature_isGCN, 1276 /* ds_inc_u32 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24549 : { Feature_isGCN, 1276 /* ds_inc_u32 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24550 : { Feature_isGCN, 1276 /* ds_inc_u32 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24551 : { Feature_isGCN, 1287 /* ds_inc_u64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24552 : { Feature_isGCN, 1287 /* ds_inc_u64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24553 : { Feature_isGCN, 1287 /* ds_inc_u64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24554 : { Feature_isGCN, 1287 /* ds_inc_u64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24555 : { Feature_isGCN, 1298 /* ds_max_f32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24556 : { Feature_isGCN, 1298 /* ds_max_f32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24557 : { Feature_isGCN, 1298 /* ds_max_f32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24558 : { Feature_isGCN, 1298 /* ds_max_f32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24559 : { Feature_isGCN, 1309 /* ds_max_f64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24560 : { Feature_isGCN, 1309 /* ds_max_f64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24561 : { Feature_isGCN, 1309 /* ds_max_f64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24562 : { Feature_isGCN, 1309 /* ds_max_f64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24563 : { Feature_isGCN, 1320 /* ds_max_i32 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24564 : { Feature_isGCN, 1320 /* ds_max_i32 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24565 : { Feature_isGCN, 1320 /* ds_max_i32 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24566 : { Feature_isGCN, 1320 /* ds_max_i32 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24567 : { Feature_isGCN, 1331 /* ds_max_i64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24568 : { Feature_isGCN, 1331 /* ds_max_i64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24569 : { Feature_isGCN, 1331 /* ds_max_i64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24570 : { Feature_isGCN, 1331 /* ds_max_i64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24571 : { Feature_isGCN, 1342 /* ds_max_rtn_f32 */, MCK_DSOffsetparseDSOptionalOps, 16 /* 4 */ },
24572 : { Feature_isGCN, 1342 /* ds_max_rtn_f32 */, MCK_GDSparseDSOptionalOps, 32 /* 5 */ },
24573 : { Feature_isGCN, 1342 /* ds_max_rtn_f32 */, MCK_DSOffsetparseDSOptionalOps, 16 /* 4 */ },
24574 : { Feature_isGCN, 1342 /* ds_max_rtn_f32 */, MCK_GDSparseDSOptionalOps, 32 /* 5 */ },
24575 : { Feature_isGCN, 1357 /* ds_max_rtn_f64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24576 : { Feature_isGCN, 1357 /* ds_max_rtn_f64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24577 : { Feature_isGCN, 1357 /* ds_max_rtn_f64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24578 : { Feature_isGCN, 1357 /* ds_max_rtn_f64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24579 : { Feature_isGCN, 1372 /* ds_max_rtn_i32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24580 : { Feature_isGCN, 1372 /* ds_max_rtn_i32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24581 : { Feature_isGCN, 1372 /* ds_max_rtn_i32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24582 : { Feature_isGCN, 1372 /* ds_max_rtn_i32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24583 : { Feature_isGCN, 1387 /* ds_max_rtn_i64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24584 : { Feature_isGCN, 1387 /* ds_max_rtn_i64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24585 : { Feature_isGCN, 1387 /* ds_max_rtn_i64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24586 : { Feature_isGCN, 1387 /* ds_max_rtn_i64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24587 : { Feature_isGCN, 1402 /* ds_max_rtn_u32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24588 : { Feature_isGCN, 1402 /* ds_max_rtn_u32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24589 : { Feature_isGCN, 1402 /* ds_max_rtn_u32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24590 : { Feature_isGCN, 1402 /* ds_max_rtn_u32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24591 : { Feature_isGCN, 1417 /* ds_max_rtn_u64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24592 : { Feature_isGCN, 1417 /* ds_max_rtn_u64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24593 : { Feature_isGCN, 1417 /* ds_max_rtn_u64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24594 : { Feature_isGCN, 1417 /* ds_max_rtn_u64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24595 : { Feature_isGCN, 1432 /* ds_max_src2_f32 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24596 : { Feature_isGCN, 1432 /* ds_max_src2_f32 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24597 : { Feature_isGCN, 1432 /* ds_max_src2_f32 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24598 : { Feature_isGCN, 1432 /* ds_max_src2_f32 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24599 : { Feature_isGCN, 1448 /* ds_max_src2_f64 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24600 : { Feature_isGCN, 1448 /* ds_max_src2_f64 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24601 : { Feature_isGCN, 1448 /* ds_max_src2_f64 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24602 : { Feature_isGCN, 1448 /* ds_max_src2_f64 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24603 : { Feature_isGCN, 1464 /* ds_max_src2_i32 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24604 : { Feature_isGCN, 1464 /* ds_max_src2_i32 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24605 : { Feature_isGCN, 1464 /* ds_max_src2_i32 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24606 : { Feature_isGCN, 1464 /* ds_max_src2_i32 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24607 : { Feature_isGCN, 1480 /* ds_max_src2_i64 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24608 : { Feature_isGCN, 1480 /* ds_max_src2_i64 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24609 : { Feature_isGCN, 1480 /* ds_max_src2_i64 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24610 : { Feature_isGCN, 1480 /* ds_max_src2_i64 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24611 : { Feature_isGCN, 1496 /* ds_max_src2_u32 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24612 : { Feature_isGCN, 1496 /* ds_max_src2_u32 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24613 : { Feature_isGCN, 1496 /* ds_max_src2_u32 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24614 : { Feature_isGCN, 1496 /* ds_max_src2_u32 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24615 : { Feature_isGCN, 1512 /* ds_max_src2_u64 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24616 : { Feature_isGCN, 1512 /* ds_max_src2_u64 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24617 : { Feature_isGCN, 1512 /* ds_max_src2_u64 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24618 : { Feature_isGCN, 1512 /* ds_max_src2_u64 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24619 : { Feature_isGCN, 1528 /* ds_max_u32 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24620 : { Feature_isGCN, 1528 /* ds_max_u32 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24621 : { Feature_isGCN, 1528 /* ds_max_u32 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24622 : { Feature_isGCN, 1528 /* ds_max_u32 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24623 : { Feature_isGCN, 1539 /* ds_max_u64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24624 : { Feature_isGCN, 1539 /* ds_max_u64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24625 : { Feature_isGCN, 1539 /* ds_max_u64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24626 : { Feature_isGCN, 1539 /* ds_max_u64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24627 : { Feature_isGCN, 1550 /* ds_min_f32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24628 : { Feature_isGCN, 1550 /* ds_min_f32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24629 : { Feature_isGCN, 1550 /* ds_min_f32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24630 : { Feature_isGCN, 1550 /* ds_min_f32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24631 : { Feature_isGCN, 1561 /* ds_min_f64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24632 : { Feature_isGCN, 1561 /* ds_min_f64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24633 : { Feature_isGCN, 1561 /* ds_min_f64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24634 : { Feature_isGCN, 1561 /* ds_min_f64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24635 : { Feature_isGCN, 1572 /* ds_min_i32 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24636 : { Feature_isGCN, 1572 /* ds_min_i32 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24637 : { Feature_isGCN, 1572 /* ds_min_i32 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24638 : { Feature_isGCN, 1572 /* ds_min_i32 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24639 : { Feature_isGCN, 1583 /* ds_min_i64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24640 : { Feature_isGCN, 1583 /* ds_min_i64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24641 : { Feature_isGCN, 1583 /* ds_min_i64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24642 : { Feature_isGCN, 1583 /* ds_min_i64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24643 : { Feature_isGCN, 1594 /* ds_min_rtn_f32 */, MCK_DSOffsetparseDSOptionalOps, 16 /* 4 */ },
24644 : { Feature_isGCN, 1594 /* ds_min_rtn_f32 */, MCK_GDSparseDSOptionalOps, 32 /* 5 */ },
24645 : { Feature_isGCN, 1594 /* ds_min_rtn_f32 */, MCK_DSOffsetparseDSOptionalOps, 16 /* 4 */ },
24646 : { Feature_isGCN, 1594 /* ds_min_rtn_f32 */, MCK_GDSparseDSOptionalOps, 32 /* 5 */ },
24647 : { Feature_isGCN, 1609 /* ds_min_rtn_f64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24648 : { Feature_isGCN, 1609 /* ds_min_rtn_f64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24649 : { Feature_isGCN, 1609 /* ds_min_rtn_f64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24650 : { Feature_isGCN, 1609 /* ds_min_rtn_f64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24651 : { Feature_isGCN, 1624 /* ds_min_rtn_i32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24652 : { Feature_isGCN, 1624 /* ds_min_rtn_i32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24653 : { Feature_isGCN, 1624 /* ds_min_rtn_i32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24654 : { Feature_isGCN, 1624 /* ds_min_rtn_i32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24655 : { Feature_isGCN, 1639 /* ds_min_rtn_i64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24656 : { Feature_isGCN, 1639 /* ds_min_rtn_i64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24657 : { Feature_isGCN, 1639 /* ds_min_rtn_i64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24658 : { Feature_isGCN, 1639 /* ds_min_rtn_i64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24659 : { Feature_isGCN, 1654 /* ds_min_rtn_u32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24660 : { Feature_isGCN, 1654 /* ds_min_rtn_u32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24661 : { Feature_isGCN, 1654 /* ds_min_rtn_u32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24662 : { Feature_isGCN, 1654 /* ds_min_rtn_u32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24663 : { Feature_isGCN, 1669 /* ds_min_rtn_u64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24664 : { Feature_isGCN, 1669 /* ds_min_rtn_u64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24665 : { Feature_isGCN, 1669 /* ds_min_rtn_u64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24666 : { Feature_isGCN, 1669 /* ds_min_rtn_u64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24667 : { Feature_isGCN, 1684 /* ds_min_src2_f32 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24668 : { Feature_isGCN, 1684 /* ds_min_src2_f32 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24669 : { Feature_isGCN, 1684 /* ds_min_src2_f32 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24670 : { Feature_isGCN, 1684 /* ds_min_src2_f32 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24671 : { Feature_isGCN, 1700 /* ds_min_src2_f64 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24672 : { Feature_isGCN, 1700 /* ds_min_src2_f64 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24673 : { Feature_isGCN, 1700 /* ds_min_src2_f64 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24674 : { Feature_isGCN, 1700 /* ds_min_src2_f64 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24675 : { Feature_isGCN, 1716 /* ds_min_src2_i32 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24676 : { Feature_isGCN, 1716 /* ds_min_src2_i32 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24677 : { Feature_isGCN, 1716 /* ds_min_src2_i32 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24678 : { Feature_isGCN, 1716 /* ds_min_src2_i32 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24679 : { Feature_isGCN, 1732 /* ds_min_src2_i64 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24680 : { Feature_isGCN, 1732 /* ds_min_src2_i64 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24681 : { Feature_isGCN, 1732 /* ds_min_src2_i64 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24682 : { Feature_isGCN, 1732 /* ds_min_src2_i64 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24683 : { Feature_isGCN, 1748 /* ds_min_src2_u32 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24684 : { Feature_isGCN, 1748 /* ds_min_src2_u32 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24685 : { Feature_isGCN, 1748 /* ds_min_src2_u32 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24686 : { Feature_isGCN, 1748 /* ds_min_src2_u32 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24687 : { Feature_isGCN, 1764 /* ds_min_src2_u64 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24688 : { Feature_isGCN, 1764 /* ds_min_src2_u64 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24689 : { Feature_isGCN, 1764 /* ds_min_src2_u64 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24690 : { Feature_isGCN, 1764 /* ds_min_src2_u64 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24691 : { Feature_isGCN, 1780 /* ds_min_u32 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24692 : { Feature_isGCN, 1780 /* ds_min_u32 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24693 : { Feature_isGCN, 1780 /* ds_min_u32 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24694 : { Feature_isGCN, 1780 /* ds_min_u32 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24695 : { Feature_isGCN, 1791 /* ds_min_u64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24696 : { Feature_isGCN, 1791 /* ds_min_u64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24697 : { Feature_isGCN, 1791 /* ds_min_u64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24698 : { Feature_isGCN, 1791 /* ds_min_u64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24699 : { Feature_isGCN, 1802 /* ds_mskor_b32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24700 : { Feature_isGCN, 1802 /* ds_mskor_b32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24701 : { Feature_isGCN, 1802 /* ds_mskor_b32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24702 : { Feature_isGCN, 1802 /* ds_mskor_b32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24703 : { Feature_isGCN, 1815 /* ds_mskor_b64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24704 : { Feature_isGCN, 1815 /* ds_mskor_b64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24705 : { Feature_isGCN, 1815 /* ds_mskor_b64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24706 : { Feature_isGCN, 1815 /* ds_mskor_b64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24707 : { Feature_isGCN, 1828 /* ds_mskor_rtn_b32 */, MCK_DSOffsetparseDSOptionalOps, 16 /* 4 */ },
24708 : { Feature_isGCN, 1828 /* ds_mskor_rtn_b32 */, MCK_GDSparseDSOptionalOps, 32 /* 5 */ },
24709 : { Feature_isGCN, 1828 /* ds_mskor_rtn_b32 */, MCK_DSOffsetparseDSOptionalOps, 16 /* 4 */ },
24710 : { Feature_isGCN, 1828 /* ds_mskor_rtn_b32 */, MCK_GDSparseDSOptionalOps, 32 /* 5 */ },
24711 : { Feature_isGCN, 1845 /* ds_mskor_rtn_b64 */, MCK_DSOffsetparseDSOptionalOps, 16 /* 4 */ },
24712 : { Feature_isGCN, 1845 /* ds_mskor_rtn_b64 */, MCK_GDSparseDSOptionalOps, 32 /* 5 */ },
24713 : { Feature_isGCN, 1845 /* ds_mskor_rtn_b64 */, MCK_DSOffsetparseDSOptionalOps, 16 /* 4 */ },
24714 : { Feature_isGCN, 1845 /* ds_mskor_rtn_b64 */, MCK_GDSparseDSOptionalOps, 32 /* 5 */ },
24715 : { Feature_isGCN, 1862 /* ds_or_b32 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24716 : { Feature_isGCN, 1862 /* ds_or_b32 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24717 : { Feature_isGCN, 1862 /* ds_or_b32 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24718 : { Feature_isGCN, 1862 /* ds_or_b32 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24719 : { Feature_isGCN, 1872 /* ds_or_b64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24720 : { Feature_isGCN, 1872 /* ds_or_b64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24721 : { Feature_isGCN, 1872 /* ds_or_b64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24722 : { Feature_isGCN, 1872 /* ds_or_b64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24723 : { Feature_isGCN, 1882 /* ds_or_rtn_b32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24724 : { Feature_isGCN, 1882 /* ds_or_rtn_b32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24725 : { Feature_isGCN, 1882 /* ds_or_rtn_b32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24726 : { Feature_isGCN, 1882 /* ds_or_rtn_b32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24727 : { Feature_isGCN, 1896 /* ds_or_rtn_b64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24728 : { Feature_isGCN, 1896 /* ds_or_rtn_b64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24729 : { Feature_isGCN, 1896 /* ds_or_rtn_b64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24730 : { Feature_isGCN, 1896 /* ds_or_rtn_b64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24731 : { Feature_isGCN, 1910 /* ds_or_src2_b32 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24732 : { Feature_isGCN, 1910 /* ds_or_src2_b32 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24733 : { Feature_isGCN, 1910 /* ds_or_src2_b32 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24734 : { Feature_isGCN, 1910 /* ds_or_src2_b32 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24735 : { Feature_isGCN, 1925 /* ds_or_src2_b64 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24736 : { Feature_isGCN, 1925 /* ds_or_src2_b64 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24737 : { Feature_isGCN, 1925 /* ds_or_src2_b64 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24738 : { Feature_isGCN, 1925 /* ds_or_src2_b64 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24739 : { Feature_isGCN, 1940 /* ds_ordered_count */, MCK_DSOffsetparseDSOffsetOptional, 4 /* 2 */ },
24740 : { Feature_isGCN, 1940 /* ds_ordered_count */, MCK_DSOffsetparseDSOffsetOptional, 4 /* 2 */ },
24741 : { Feature_isGCN, 1957 /* ds_read2_b32 */, MCK_DSOffset1, 12 /* 2, 3 */ },
24742 : { Feature_isGCN, 1957 /* ds_read2_b32 */, MCK_GDSparseDSOff01OptionalOps, 16 /* 4 */ },
24743 : { Feature_isGCN, 1957 /* ds_read2_b32 */, MCK_DSOffset1, 12 /* 2, 3 */ },
24744 : { Feature_isGCN, 1957 /* ds_read2_b32 */, MCK_GDSparseDSOff01OptionalOps, 16 /* 4 */ },
24745 : { Feature_isGCN, 1970 /* ds_read2_b64 */, MCK_DSOffset1, 12 /* 2, 3 */ },
24746 : { Feature_isGCN, 1970 /* ds_read2_b64 */, MCK_GDSparseDSOff01OptionalOps, 16 /* 4 */ },
24747 : { Feature_isGCN, 1970 /* ds_read2_b64 */, MCK_DSOffset1, 12 /* 2, 3 */ },
24748 : { Feature_isGCN, 1970 /* ds_read2_b64 */, MCK_GDSparseDSOff01OptionalOps, 16 /* 4 */ },
24749 : { Feature_isGCN, 1983 /* ds_read2st64_b32 */, MCK_DSOffset1, 12 /* 2, 3 */ },
24750 : { Feature_isGCN, 1983 /* ds_read2st64_b32 */, MCK_GDSparseDSOff01OptionalOps, 16 /* 4 */ },
24751 : { Feature_isGCN, 1983 /* ds_read2st64_b32 */, MCK_DSOffset1, 12 /* 2, 3 */ },
24752 : { Feature_isGCN, 1983 /* ds_read2st64_b32 */, MCK_GDSparseDSOff01OptionalOps, 16 /* 4 */ },
24753 : { Feature_isGCN, 2000 /* ds_read2st64_b64 */, MCK_DSOffset1, 12 /* 2, 3 */ },
24754 : { Feature_isGCN, 2000 /* ds_read2st64_b64 */, MCK_GDSparseDSOff01OptionalOps, 16 /* 4 */ },
24755 : { Feature_isGCN, 2000 /* ds_read2st64_b64 */, MCK_DSOffset1, 12 /* 2, 3 */ },
24756 : { Feature_isGCN, 2000 /* ds_read2st64_b64 */, MCK_GDSparseDSOff01OptionalOps, 16 /* 4 */ },
24757 : { Feature_isGCN, 2017 /* ds_read_b32 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24758 : { Feature_isGCN, 2017 /* ds_read_b32 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24759 : { Feature_isGCN, 2017 /* ds_read_b32 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24760 : { Feature_isGCN, 2017 /* ds_read_b32 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24761 : { Feature_isGCN, 2029 /* ds_read_b64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24762 : { Feature_isGCN, 2029 /* ds_read_b64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24763 : { Feature_isGCN, 2029 /* ds_read_b64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24764 : { Feature_isGCN, 2029 /* ds_read_b64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24765 : { Feature_isGCN, 2041 /* ds_read_i16 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24766 : { Feature_isGCN, 2041 /* ds_read_i16 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24767 : { Feature_isGCN, 2041 /* ds_read_i16 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24768 : { Feature_isGCN, 2041 /* ds_read_i16 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24769 : { Feature_isGCN, 2053 /* ds_read_i8 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24770 : { Feature_isGCN, 2053 /* ds_read_i8 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24771 : { Feature_isGCN, 2053 /* ds_read_i8 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24772 : { Feature_isGCN, 2053 /* ds_read_i8 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24773 : { Feature_isGCN, 2064 /* ds_read_u16 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24774 : { Feature_isGCN, 2064 /* ds_read_u16 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24775 : { Feature_isGCN, 2064 /* ds_read_u16 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24776 : { Feature_isGCN, 2064 /* ds_read_u16 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24777 : { Feature_isGCN, 2076 /* ds_read_u8 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24778 : { Feature_isGCN, 2076 /* ds_read_u8 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24779 : { Feature_isGCN, 2076 /* ds_read_u8 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24780 : { Feature_isGCN, 2076 /* ds_read_u8 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24781 : { Feature_isGCN, 2087 /* ds_rsub_rtn_u32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24782 : { Feature_isGCN, 2087 /* ds_rsub_rtn_u32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24783 : { Feature_isGCN, 2087 /* ds_rsub_rtn_u32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24784 : { Feature_isGCN, 2087 /* ds_rsub_rtn_u32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24785 : { Feature_isGCN, 2103 /* ds_rsub_rtn_u64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24786 : { Feature_isGCN, 2103 /* ds_rsub_rtn_u64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24787 : { Feature_isGCN, 2103 /* ds_rsub_rtn_u64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24788 : { Feature_isGCN, 2103 /* ds_rsub_rtn_u64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24789 : { Feature_isGCN, 2119 /* ds_rsub_src2_u32 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24790 : { Feature_isGCN, 2119 /* ds_rsub_src2_u32 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24791 : { Feature_isGCN, 2119 /* ds_rsub_src2_u32 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24792 : { Feature_isGCN, 2119 /* ds_rsub_src2_u32 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24793 : { Feature_isGCN, 2136 /* ds_rsub_src2_u64 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24794 : { Feature_isGCN, 2136 /* ds_rsub_src2_u64 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24795 : { Feature_isGCN, 2136 /* ds_rsub_src2_u64 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24796 : { Feature_isGCN, 2136 /* ds_rsub_src2_u64 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24797 : { Feature_isGCN, 2153 /* ds_rsub_u32 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24798 : { Feature_isGCN, 2153 /* ds_rsub_u32 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24799 : { Feature_isGCN, 2153 /* ds_rsub_u32 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24800 : { Feature_isGCN, 2153 /* ds_rsub_u32 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24801 : { Feature_isGCN, 2165 /* ds_rsub_u64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24802 : { Feature_isGCN, 2165 /* ds_rsub_u64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24803 : { Feature_isGCN, 2165 /* ds_rsub_u64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24804 : { Feature_isGCN, 2165 /* ds_rsub_u64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24805 : { Feature_isGCN, 2177 /* ds_sub_rtn_u32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24806 : { Feature_isGCN, 2177 /* ds_sub_rtn_u32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24807 : { Feature_isGCN, 2177 /* ds_sub_rtn_u32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24808 : { Feature_isGCN, 2177 /* ds_sub_rtn_u32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24809 : { Feature_isGCN, 2192 /* ds_sub_rtn_u64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24810 : { Feature_isGCN, 2192 /* ds_sub_rtn_u64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24811 : { Feature_isGCN, 2192 /* ds_sub_rtn_u64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24812 : { Feature_isGCN, 2192 /* ds_sub_rtn_u64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24813 : { Feature_isGCN, 2207 /* ds_sub_src2_u32 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24814 : { Feature_isGCN, 2207 /* ds_sub_src2_u32 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24815 : { Feature_isGCN, 2207 /* ds_sub_src2_u32 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24816 : { Feature_isGCN, 2207 /* ds_sub_src2_u32 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24817 : { Feature_isGCN, 2223 /* ds_sub_src2_u64 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24818 : { Feature_isGCN, 2223 /* ds_sub_src2_u64 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24819 : { Feature_isGCN, 2223 /* ds_sub_src2_u64 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24820 : { Feature_isGCN, 2223 /* ds_sub_src2_u64 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24821 : { Feature_isGCN, 2239 /* ds_sub_u32 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24822 : { Feature_isGCN, 2239 /* ds_sub_u32 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24823 : { Feature_isGCN, 2239 /* ds_sub_u32 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24824 : { Feature_isGCN, 2239 /* ds_sub_u32 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24825 : { Feature_isGCN, 2250 /* ds_sub_u64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24826 : { Feature_isGCN, 2250 /* ds_sub_u64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24827 : { Feature_isGCN, 2250 /* ds_sub_u64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24828 : { Feature_isGCN, 2250 /* ds_sub_u64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24829 : { Feature_isGCN, 2261 /* ds_swizzle_b32 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24830 : { Feature_isGCN, 2261 /* ds_swizzle_b32 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24831 : { Feature_isGCN, 2261 /* ds_swizzle_b32 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24832 : { Feature_isGCN, 2261 /* ds_swizzle_b32 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24833 : { 0, 2276 /* ds_wrap_rtn_f32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24834 : { 0, 2276 /* ds_wrap_rtn_f32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24835 : { 0, 2276 /* ds_wrap_rtn_f32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24836 : { 0, 2276 /* ds_wrap_rtn_f32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24837 : { Feature_isGCN, 2292 /* ds_write2_b32 */, MCK_DSOffset1, 24 /* 3, 4 */ },
24838 : { Feature_isGCN, 2292 /* ds_write2_b32 */, MCK_GDSparseDSOff01OptionalOps, 32 /* 5 */ },
24839 : { Feature_isGCN, 2292 /* ds_write2_b32 */, MCK_DSOffset1, 24 /* 3, 4 */ },
24840 : { Feature_isGCN, 2292 /* ds_write2_b32 */, MCK_GDSparseDSOff01OptionalOps, 32 /* 5 */ },
24841 : { Feature_isGCN, 2306 /* ds_write2_b64 */, MCK_DSOffset1, 24 /* 3, 4 */ },
24842 : { Feature_isGCN, 2306 /* ds_write2_b64 */, MCK_GDSparseDSOff01OptionalOps, 32 /* 5 */ },
24843 : { Feature_isGCN, 2306 /* ds_write2_b64 */, MCK_DSOffset1, 24 /* 3, 4 */ },
24844 : { Feature_isGCN, 2306 /* ds_write2_b64 */, MCK_GDSparseDSOff01OptionalOps, 32 /* 5 */ },
24845 : { Feature_isGCN, 2320 /* ds_write2st64_b32 */, MCK_DSOffset1, 24 /* 3, 4 */ },
24846 : { Feature_isGCN, 2320 /* ds_write2st64_b32 */, MCK_GDSparseDSOff01OptionalOps, 32 /* 5 */ },
24847 : { Feature_isGCN, 2320 /* ds_write2st64_b32 */, MCK_DSOffset1, 24 /* 3, 4 */ },
24848 : { Feature_isGCN, 2320 /* ds_write2st64_b32 */, MCK_GDSparseDSOff01OptionalOps, 32 /* 5 */ },
24849 : { Feature_isGCN, 2338 /* ds_write2st64_b64 */, MCK_DSOffset1, 24 /* 3, 4 */ },
24850 : { Feature_isGCN, 2338 /* ds_write2st64_b64 */, MCK_GDSparseDSOff01OptionalOps, 32 /* 5 */ },
24851 : { Feature_isGCN, 2338 /* ds_write2st64_b64 */, MCK_DSOffset1, 24 /* 3, 4 */ },
24852 : { Feature_isGCN, 2338 /* ds_write2st64_b64 */, MCK_GDSparseDSOff01OptionalOps, 32 /* 5 */ },
24853 : { Feature_isGCN, 2356 /* ds_write_b16 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24854 : { Feature_isGCN, 2356 /* ds_write_b16 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24855 : { Feature_isGCN, 2356 /* ds_write_b16 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24856 : { Feature_isGCN, 2356 /* ds_write_b16 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24857 : { Feature_isGCN, 2369 /* ds_write_b32 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24858 : { Feature_isGCN, 2369 /* ds_write_b32 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24859 : { Feature_isGCN, 2369 /* ds_write_b32 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24860 : { Feature_isGCN, 2369 /* ds_write_b32 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24861 : { Feature_isGCN, 2382 /* ds_write_b64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24862 : { Feature_isGCN, 2382 /* ds_write_b64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24863 : { Feature_isGCN, 2382 /* ds_write_b64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24864 : { Feature_isGCN, 2382 /* ds_write_b64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24865 : { Feature_isGCN, 2395 /* ds_write_b8 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24866 : { Feature_isGCN, 2395 /* ds_write_b8 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24867 : { Feature_isGCN, 2395 /* ds_write_b8 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24868 : { Feature_isGCN, 2395 /* ds_write_b8 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24869 : { Feature_isGCN, 2407 /* ds_write_src2_b32 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24870 : { Feature_isGCN, 2407 /* ds_write_src2_b32 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24871 : { Feature_isGCN, 2407 /* ds_write_src2_b32 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24872 : { Feature_isGCN, 2407 /* ds_write_src2_b32 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24873 : { Feature_isGCN, 2425 /* ds_write_src2_b64 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24874 : { Feature_isGCN, 2425 /* ds_write_src2_b64 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24875 : { Feature_isGCN, 2425 /* ds_write_src2_b64 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24876 : { Feature_isGCN, 2425 /* ds_write_src2_b64 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24877 : { Feature_isGCN, 2443 /* ds_wrxchg2_rtn_b32 */, MCK_DSOffsetparseDSOptionalOps, 16 /* 4 */ },
24878 : { Feature_isGCN, 2443 /* ds_wrxchg2_rtn_b32 */, MCK_GDSparseDSOptionalOps, 32 /* 5 */ },
24879 : { Feature_isGCN, 2443 /* ds_wrxchg2_rtn_b32 */, MCK_DSOffsetparseDSOptionalOps, 16 /* 4 */ },
24880 : { Feature_isGCN, 2443 /* ds_wrxchg2_rtn_b32 */, MCK_GDSparseDSOptionalOps, 32 /* 5 */ },
24881 : { Feature_isGCN, 2462 /* ds_wrxchg2_rtn_b64 */, MCK_DSOffsetparseDSOptionalOps, 16 /* 4 */ },
24882 : { Feature_isGCN, 2462 /* ds_wrxchg2_rtn_b64 */, MCK_GDSparseDSOptionalOps, 32 /* 5 */ },
24883 : { Feature_isGCN, 2462 /* ds_wrxchg2_rtn_b64 */, MCK_DSOffsetparseDSOptionalOps, 16 /* 4 */ },
24884 : { Feature_isGCN, 2462 /* ds_wrxchg2_rtn_b64 */, MCK_GDSparseDSOptionalOps, 32 /* 5 */ },
24885 : { Feature_isGCN, 2481 /* ds_wrxchg2st64_rtn_b32 */, MCK_DSOffsetparseDSOptionalOps, 16 /* 4 */ },
24886 : { Feature_isGCN, 2481 /* ds_wrxchg2st64_rtn_b32 */, MCK_GDSparseDSOptionalOps, 32 /* 5 */ },
24887 : { Feature_isGCN, 2481 /* ds_wrxchg2st64_rtn_b32 */, MCK_DSOffsetparseDSOptionalOps, 16 /* 4 */ },
24888 : { Feature_isGCN, 2481 /* ds_wrxchg2st64_rtn_b32 */, MCK_GDSparseDSOptionalOps, 32 /* 5 */ },
24889 : { Feature_isGCN, 2504 /* ds_wrxchg2st64_rtn_b64 */, MCK_DSOffsetparseDSOptionalOps, 16 /* 4 */ },
24890 : { Feature_isGCN, 2504 /* ds_wrxchg2st64_rtn_b64 */, MCK_GDSparseDSOptionalOps, 32 /* 5 */ },
24891 : { Feature_isGCN, 2504 /* ds_wrxchg2st64_rtn_b64 */, MCK_DSOffsetparseDSOptionalOps, 16 /* 4 */ },
24892 : { Feature_isGCN, 2504 /* ds_wrxchg2st64_rtn_b64 */, MCK_GDSparseDSOptionalOps, 32 /* 5 */ },
24893 : { Feature_isGCN, 2527 /* ds_wrxchg_rtn_b32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24894 : { Feature_isGCN, 2527 /* ds_wrxchg_rtn_b32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24895 : { Feature_isGCN, 2527 /* ds_wrxchg_rtn_b32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24896 : { Feature_isGCN, 2527 /* ds_wrxchg_rtn_b32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24897 : { Feature_isGCN, 2545 /* ds_wrxchg_rtn_b64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24898 : { Feature_isGCN, 2545 /* ds_wrxchg_rtn_b64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24899 : { Feature_isGCN, 2545 /* ds_wrxchg_rtn_b64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24900 : { Feature_isGCN, 2545 /* ds_wrxchg_rtn_b64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24901 : { Feature_isGCN, 2563 /* ds_xor_b32 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24902 : { Feature_isGCN, 2563 /* ds_xor_b32 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24903 : { Feature_isGCN, 2563 /* ds_xor_b32 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24904 : { Feature_isGCN, 2563 /* ds_xor_b32 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24905 : { Feature_isGCN, 2574 /* ds_xor_b64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24906 : { Feature_isGCN, 2574 /* ds_xor_b64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24907 : { Feature_isGCN, 2574 /* ds_xor_b64 */, MCK_DSOffsetparseDSOptionalOps, 4 /* 2 */ },
24908 : { Feature_isGCN, 2574 /* ds_xor_b64 */, MCK_GDSparseDSOptionalOps, 8 /* 3 */ },
24909 : { Feature_isGCN, 2585 /* ds_xor_rtn_b32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24910 : { Feature_isGCN, 2585 /* ds_xor_rtn_b32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24911 : { Feature_isGCN, 2585 /* ds_xor_rtn_b32 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24912 : { Feature_isGCN, 2585 /* ds_xor_rtn_b32 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24913 : { Feature_isGCN, 2600 /* ds_xor_rtn_b64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24914 : { Feature_isGCN, 2600 /* ds_xor_rtn_b64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24915 : { Feature_isGCN, 2600 /* ds_xor_rtn_b64 */, MCK_DSOffsetparseDSOptionalOps, 8 /* 3 */ },
24916 : { Feature_isGCN, 2600 /* ds_xor_rtn_b64 */, MCK_GDSparseDSOptionalOps, 16 /* 4 */ },
24917 : { Feature_isGCN, 2615 /* ds_xor_src2_b32 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24918 : { Feature_isGCN, 2615 /* ds_xor_src2_b32 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24919 : { Feature_isGCN, 2615 /* ds_xor_src2_b32 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24920 : { Feature_isGCN, 2615 /* ds_xor_src2_b32 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24921 : { Feature_isGCN, 2631 /* ds_xor_src2_b64 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24922 : { Feature_isGCN, 2631 /* ds_xor_src2_b64 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24923 : { Feature_isGCN, 2631 /* ds_xor_src2_b64 */, MCK_DSOffsetparseDSOptionalOps, 2 /* 1 */ },
24924 : { Feature_isGCN, 2631 /* ds_xor_src2_b64 */, MCK_GDSparseDSOptionalOps, 4 /* 2 */ },
24925 : { Feature_isGCN, 4482 /* s_branch */, MCK_SoppBrTarget, 1 /* 0 */ },
24926 : { Feature_isGCN, 4622 /* s_cbranch_execnz */, MCK_SoppBrTarget, 1 /* 0 */ },
24927 : { Feature_isGCN, 4639 /* s_cbranch_execz */, MCK_SoppBrTarget, 1 /* 0 */ },
24928 : { Feature_isGCN, 4704 /* s_cbranch_scc0 */, MCK_SoppBrTarget, 1 /* 0 */ },
24929 : { Feature_isGCN, 4719 /* s_cbranch_scc1 */, MCK_SoppBrTarget, 1 /* 0 */ },
24930 : { Feature_isGCN, 4734 /* s_cbranch_vccnz */, MCK_SoppBrTarget, 1 /* 0 */ },
24931 : { Feature_isGCN, 4750 /* s_cbranch_vccz */, MCK_SoppBrTarget, 1 /* 0 */ },
24932 : { Feature_isGCN, 6054 /* s_waitcnt */, MCK_SWaitCnt, 1 /* 0 */ },
24933 : { Feature_isVI|Feature_isSICI, 6288 /* v_add_f16 */, MCK_Clamp, 8 /* 3 */ },
24934 : { Feature_isVI|Feature_isSICI, 6288 /* v_add_f16 */, MCK_OMod, 16 /* 4 */ },
24935 : { Feature_isVI|Feature_isVI, 6288 /* v_add_f16 */, MCK_Clamp, 8 /* 3 */ },
24936 : { Feature_isVI|Feature_isVI, 6288 /* v_add_f16 */, MCK_OMod, 16 /* 4 */ },
24937 : { Feature_isGCN|Feature_isSICI, 6298 /* v_add_f32 */, MCK_Clamp, 8 /* 3 */ },
24938 : { Feature_isGCN|Feature_isSICI, 6298 /* v_add_f32 */, MCK_OMod, 16 /* 4 */ },
24939 : { Feature_isGCN|Feature_isVI, 6298 /* v_add_f32 */, MCK_Clamp, 8 /* 3 */ },
24940 : { Feature_isGCN|Feature_isVI, 6298 /* v_add_f32 */, MCK_OMod, 16 /* 4 */ },
24941 : { Feature_isGCN|Feature_isSICI, 6308 /* v_add_f64 */, MCK_Clamp, 8 /* 3 */ },
24942 : { Feature_isGCN|Feature_isSICI, 6308 /* v_add_f64 */, MCK_OMod, 16 /* 4 */ },
24943 : { Feature_isGCN|Feature_isVI, 6308 /* v_add_f64 */, MCK_Clamp, 8 /* 3 */ },
24944 : { Feature_isGCN|Feature_isVI, 6308 /* v_add_f64 */, MCK_OMod, 16 /* 4 */ },
24945 : { Feature_isVI|Feature_isSICI, 6521 /* v_ceil_f16 */, MCK_Clamp, 4 /* 2 */ },
24946 : { Feature_isVI|Feature_isSICI, 6521 /* v_ceil_f16 */, MCK_OMod, 8 /* 3 */ },
24947 : { Feature_isVI|Feature_isVI, 6521 /* v_ceil_f16 */, MCK_Clamp, 4 /* 2 */ },
24948 : { Feature_isVI|Feature_isVI, 6521 /* v_ceil_f16 */, MCK_OMod, 8 /* 3 */ },
24949 : { Feature_isGCN|Feature_isSICI, 6532 /* v_ceil_f32 */, MCK_Clamp, 4 /* 2 */ },
24950 : { Feature_isGCN|Feature_isSICI, 6532 /* v_ceil_f32 */, MCK_OMod, 8 /* 3 */ },
24951 : { Feature_isGCN|Feature_isVI, 6532 /* v_ceil_f32 */, MCK_Clamp, 4 /* 2 */ },
24952 : { Feature_isGCN|Feature_isVI, 6532 /* v_ceil_f32 */, MCK_OMod, 8 /* 3 */ },
24953 : { Feature_isCIVI|Feature_isSICI, 6543 /* v_ceil_f64 */, MCK_Clamp, 4 /* 2 */ },
24954 : { Feature_isCIVI|Feature_isSICI, 6543 /* v_ceil_f64 */, MCK_OMod, 8 /* 3 */ },
24955 : { Feature_isCIVI|Feature_isVI, 6543 /* v_ceil_f64 */, MCK_Clamp, 4 /* 2 */ },
24956 : { Feature_isCIVI|Feature_isVI, 6543 /* v_ceil_f64 */, MCK_OMod, 8 /* 3 */ },
24957 : { Feature_isGCN|Feature_isSICI, 6596 /* v_cmp_eq_f32 */, MCK_Clamp, 8 /* 3 */ },
24958 : { Feature_isGCN|Feature_isSICI, 6596 /* v_cmp_eq_f32 */, MCK_OMod, 16 /* 4 */ },
24959 : { Feature_isGCN|Feature_isVI, 6596 /* v_cmp_eq_f32 */, MCK_Clamp, 8 /* 3 */ },
24960 : { Feature_isGCN|Feature_isVI, 6596 /* v_cmp_eq_f32 */, MCK_OMod, 16 /* 4 */ },
24961 : { Feature_isGCN|Feature_isSICI, 6609 /* v_cmp_eq_f64 */, MCK_Clamp, 8 /* 3 */ },
24962 : { Feature_isGCN|Feature_isSICI, 6609 /* v_cmp_eq_f64 */, MCK_OMod, 16 /* 4 */ },
24963 : { Feature_isGCN|Feature_isVI, 6609 /* v_cmp_eq_f64 */, MCK_Clamp, 8 /* 3 */ },
24964 : { Feature_isGCN|Feature_isVI, 6609 /* v_cmp_eq_f64 */, MCK_OMod, 16 /* 4 */ },
24965 : { Feature_isGCN|Feature_isSICI, 6674 /* v_cmp_f_f32 */, MCK_Clamp, 8 /* 3 */ },
24966 : { Feature_isGCN|Feature_isSICI, 6674 /* v_cmp_f_f32 */, MCK_OMod, 16 /* 4 */ },
24967 : { Feature_isGCN|Feature_isVI, 6674 /* v_cmp_f_f32 */, MCK_Clamp, 8 /* 3 */ },
24968 : { Feature_isGCN|Feature_isVI, 6674 /* v_cmp_f_f32 */, MCK_OMod, 16 /* 4 */ },
24969 : { Feature_isGCN|Feature_isSICI, 6686 /* v_cmp_f_f64 */, MCK_Clamp, 8 /* 3 */ },
24970 : { Feature_isGCN|Feature_isSICI, 6686 /* v_cmp_f_f64 */, MCK_OMod, 16 /* 4 */ },
24971 : { Feature_isGCN|Feature_isVI, 6686 /* v_cmp_f_f64 */, MCK_Clamp, 8 /* 3 */ },
24972 : { Feature_isGCN|Feature_isVI, 6686 /* v_cmp_f_f64 */, MCK_OMod, 16 /* 4 */ },
24973 : { Feature_isGCN|Feature_isSICI, 6746 /* v_cmp_ge_f32 */, MCK_Clamp, 8 /* 3 */ },
24974 : { Feature_isGCN|Feature_isSICI, 6746 /* v_cmp_ge_f32 */, MCK_OMod, 16 /* 4 */ },
24975 : { Feature_isGCN|Feature_isVI, 6746 /* v_cmp_ge_f32 */, MCK_Clamp, 8 /* 3 */ },
24976 : { Feature_isGCN|Feature_isVI, 6746 /* v_cmp_ge_f32 */, MCK_OMod, 16 /* 4 */ },
24977 : { Feature_isGCN|Feature_isSICI, 6759 /* v_cmp_ge_f64 */, MCK_Clamp, 8 /* 3 */ },
24978 : { Feature_isGCN|Feature_isSICI, 6759 /* v_cmp_ge_f64 */, MCK_OMod, 16 /* 4 */ },
24979 : { Feature_isGCN|Feature_isVI, 6759 /* v_cmp_ge_f64 */, MCK_Clamp, 8 /* 3 */ },
24980 : { Feature_isGCN|Feature_isVI, 6759 /* v_cmp_ge_f64 */, MCK_OMod, 16 /* 4 */ },
24981 : { Feature_isGCN|Feature_isSICI, 6824 /* v_cmp_gt_f32 */, MCK_Clamp, 8 /* 3 */ },
24982 : { Feature_isGCN|Feature_isSICI, 6824 /* v_cmp_gt_f32 */, MCK_OMod, 16 /* 4 */ },
24983 : { Feature_isGCN|Feature_isVI, 6824 /* v_cmp_gt_f32 */, MCK_Clamp, 8 /* 3 */ },
24984 : { Feature_isGCN|Feature_isVI, 6824 /* v_cmp_gt_f32 */, MCK_OMod, 16 /* 4 */ },
24985 : { Feature_isGCN|Feature_isSICI, 6837 /* v_cmp_gt_f64 */, MCK_Clamp, 8 /* 3 */ },
24986 : { Feature_isGCN|Feature_isSICI, 6837 /* v_cmp_gt_f64 */, MCK_OMod, 16 /* 4 */ },
24987 : { Feature_isGCN|Feature_isVI, 6837 /* v_cmp_gt_f64 */, MCK_Clamp, 8 /* 3 */ },
24988 : { Feature_isGCN|Feature_isVI, 6837 /* v_cmp_gt_f64 */, MCK_OMod, 16 /* 4 */ },
24989 : { Feature_isGCN|Feature_isSICI, 6902 /* v_cmp_le_f32 */, MCK_Clamp, 8 /* 3 */ },
24990 : { Feature_isGCN|Feature_isSICI, 6902 /* v_cmp_le_f32 */, MCK_OMod, 16 /* 4 */ },
24991 : { Feature_isGCN|Feature_isVI, 6902 /* v_cmp_le_f32 */, MCK_Clamp, 8 /* 3 */ },
24992 : { Feature_isGCN|Feature_isVI, 6902 /* v_cmp_le_f32 */, MCK_OMod, 16 /* 4 */ },
24993 : { Feature_isGCN|Feature_isSICI, 6915 /* v_cmp_le_f64 */, MCK_Clamp, 8 /* 3 */ },
24994 : { Feature_isGCN|Feature_isSICI, 6915 /* v_cmp_le_f64 */, MCK_OMod, 16 /* 4 */ },
24995 : { Feature_isGCN|Feature_isVI, 6915 /* v_cmp_le_f64 */, MCK_Clamp, 8 /* 3 */ },
24996 : { Feature_isGCN|Feature_isVI, 6915 /* v_cmp_le_f64 */, MCK_OMod, 16 /* 4 */ },
24997 : { Feature_isGCN|Feature_isSICI, 6980 /* v_cmp_lg_f32 */, MCK_Clamp, 8 /* 3 */ },
24998 : { Feature_isGCN|Feature_isSICI, 6980 /* v_cmp_lg_f32 */, MCK_OMod, 16 /* 4 */ },
24999 : { Feature_isGCN|Feature_isVI, 6980 /* v_cmp_lg_f32 */, MCK_Clamp, 8 /* 3 */ },
25000 : { Feature_isGCN|Feature_isVI, 6980 /* v_cmp_lg_f32 */, MCK_OMod, 16 /* 4 */ },
25001 : { Feature_isGCN|Feature_isSICI, 6993 /* v_cmp_lg_f64 */, MCK_Clamp, 8 /* 3 */ },
25002 : { Feature_isGCN|Feature_isSICI, 6993 /* v_cmp_lg_f64 */, MCK_OMod, 16 /* 4 */ },
25003 : { Feature_isGCN|Feature_isVI, 6993 /* v_cmp_lg_f64 */, MCK_Clamp, 8 /* 3 */ },
25004 : { Feature_isGCN|Feature_isVI, 6993 /* v_cmp_lg_f64 */, MCK_OMod, 16 /* 4 */ },
25005 : { Feature_isGCN|Feature_isSICI, 7006 /* v_cmp_lt_f32 */, MCK_Clamp, 8 /* 3 */ },
25006 : { Feature_isGCN|Feature_isSICI, 7006 /* v_cmp_lt_f32 */, MCK_OMod, 16 /* 4 */ },
25007 : { Feature_isGCN|Feature_isVI, 7006 /* v_cmp_lt_f32 */, MCK_Clamp, 8 /* 3 */ },
25008 : { Feature_isGCN|Feature_isVI, 7006 /* v_cmp_lt_f32 */, MCK_OMod, 16 /* 4 */ },
25009 : { Feature_isGCN|Feature_isSICI, 7019 /* v_cmp_lt_f64 */, MCK_Clamp, 8 /* 3 */ },
25010 : { Feature_isGCN|Feature_isSICI, 7019 /* v_cmp_lt_f64 */, MCK_OMod, 16 /* 4 */ },
25011 : { Feature_isGCN|Feature_isVI, 7019 /* v_cmp_lt_f64 */, MCK_Clamp, 8 /* 3 */ },
25012 : { Feature_isGCN|Feature_isVI, 7019 /* v_cmp_lt_f64 */, MCK_OMod, 16 /* 4 */ },
25013 : { Feature_isGCN|Feature_isSICI, 7136 /* v_cmp_neq_f32 */, MCK_Clamp, 8 /* 3 */ },
25014 : { Feature_isGCN|Feature_isSICI, 7136 /* v_cmp_neq_f32 */, MCK_OMod, 16 /* 4 */ },
25015 : { Feature_isGCN|Feature_isVI, 7136 /* v_cmp_neq_f32 */, MCK_Clamp, 8 /* 3 */ },
25016 : { Feature_isGCN|Feature_isVI, 7136 /* v_cmp_neq_f32 */, MCK_OMod, 16 /* 4 */ },
25017 : { Feature_isGCN|Feature_isSICI, 7150 /* v_cmp_neq_f64 */, MCK_Clamp, 8 /* 3 */ },
25018 : { Feature_isGCN|Feature_isSICI, 7150 /* v_cmp_neq_f64 */, MCK_OMod, 16 /* 4 */ },
25019 : { Feature_isGCN|Feature_isVI, 7150 /* v_cmp_neq_f64 */, MCK_Clamp, 8 /* 3 */ },
25020 : { Feature_isGCN|Feature_isVI, 7150 /* v_cmp_neq_f64 */, MCK_OMod, 16 /* 4 */ },
25021 : { Feature_isGCN|Feature_isSICI, 7164 /* v_cmp_nge_f32 */, MCK_Clamp, 8 /* 3 */ },
25022 : { Feature_isGCN|Feature_isSICI, 7164 /* v_cmp_nge_f32 */, MCK_OMod, 16 /* 4 */ },
25023 : { Feature_isGCN|Feature_isVI, 7164 /* v_cmp_nge_f32 */, MCK_Clamp, 8 /* 3 */ },
25024 : { Feature_isGCN|Feature_isVI, 7164 /* v_cmp_nge_f32 */, MCK_OMod, 16 /* 4 */ },
25025 : { Feature_isGCN|Feature_isSICI, 7178 /* v_cmp_nge_f64 */, MCK_Clamp, 8 /* 3 */ },
25026 : { Feature_isGCN|Feature_isSICI, 7178 /* v_cmp_nge_f64 */, MCK_OMod, 16 /* 4 */ },
25027 : { Feature_isGCN|Feature_isVI, 7178 /* v_cmp_nge_f64 */, MCK_Clamp, 8 /* 3 */ },
25028 : { Feature_isGCN|Feature_isVI, 7178 /* v_cmp_nge_f64 */, MCK_OMod, 16 /* 4 */ },
25029 : { Feature_isGCN|Feature_isSICI, 7192 /* v_cmp_ngt_f32 */, MCK_Clamp, 8 /* 3 */ },
25030 : { Feature_isGCN|Feature_isSICI, 7192 /* v_cmp_ngt_f32 */, MCK_OMod, 16 /* 4 */ },
25031 : { Feature_isGCN|Feature_isVI, 7192 /* v_cmp_ngt_f32 */, MCK_Clamp, 8 /* 3 */ },
25032 : { Feature_isGCN|Feature_isVI, 7192 /* v_cmp_ngt_f32 */, MCK_OMod, 16 /* 4 */ },
25033 : { Feature_isGCN|Feature_isSICI, 7206 /* v_cmp_ngt_f64 */, MCK_Clamp, 8 /* 3 */ },
25034 : { Feature_isGCN|Feature_isSICI, 7206 /* v_cmp_ngt_f64 */, MCK_OMod, 16 /* 4 */ },
25035 : { Feature_isGCN|Feature_isVI, 7206 /* v_cmp_ngt_f64 */, MCK_Clamp, 8 /* 3 */ },
25036 : { Feature_isGCN|Feature_isVI, 7206 /* v_cmp_ngt_f64 */, MCK_OMod, 16 /* 4 */ },
25037 : { Feature_isGCN|Feature_isSICI, 7220 /* v_cmp_nle_f32 */, MCK_Clamp, 8 /* 3 */ },
25038 : { Feature_isGCN|Feature_isSICI, 7220 /* v_cmp_nle_f32 */, MCK_OMod, 16 /* 4 */ },
25039 : { Feature_isGCN|Feature_isVI, 7220 /* v_cmp_nle_f32 */, MCK_Clamp, 8 /* 3 */ },
25040 : { Feature_isGCN|Feature_isVI, 7220 /* v_cmp_nle_f32 */, MCK_OMod, 16 /* 4 */ },
25041 : { Feature_isGCN|Feature_isSICI, 7234 /* v_cmp_nle_f64 */, MCK_Clamp, 8 /* 3 */ },
25042 : { Feature_isGCN|Feature_isSICI, 7234 /* v_cmp_nle_f64 */, MCK_OMod, 16 /* 4 */ },
25043 : { Feature_isGCN|Feature_isVI, 7234 /* v_cmp_nle_f64 */, MCK_Clamp, 8 /* 3 */ },
25044 : { Feature_isGCN|Feature_isVI, 7234 /* v_cmp_nle_f64 */, MCK_OMod, 16 /* 4 */ },
25045 : { Feature_isGCN|Feature_isSICI, 7248 /* v_cmp_nlg_f32 */, MCK_Clamp, 8 /* 3 */ },
25046 : { Feature_isGCN|Feature_isSICI, 7248 /* v_cmp_nlg_f32 */, MCK_OMod, 16 /* 4 */ },
25047 : { Feature_isGCN|Feature_isVI, 7248 /* v_cmp_nlg_f32 */, MCK_Clamp, 8 /* 3 */ },
25048 : { Feature_isGCN|Feature_isVI, 7248 /* v_cmp_nlg_f32 */, MCK_OMod, 16 /* 4 */ },
25049 : { Feature_isGCN|Feature_isSICI, 7262 /* v_cmp_nlg_f64 */, MCK_Clamp, 8 /* 3 */ },
25050 : { Feature_isGCN|Feature_isSICI, 7262 /* v_cmp_nlg_f64 */, MCK_OMod, 16 /* 4 */ },
25051 : { Feature_isGCN|Feature_isVI, 7262 /* v_cmp_nlg_f64 */, MCK_Clamp, 8 /* 3 */ },
25052 : { Feature_isGCN|Feature_isVI, 7262 /* v_cmp_nlg_f64 */, MCK_OMod, 16 /* 4 */ },
25053 : { Feature_isGCN|Feature_isSICI, 7276 /* v_cmp_nlt_f32 */, MCK_Clamp, 8 /* 3 */ },
25054 : { Feature_isGCN|Feature_isSICI, 7276 /* v_cmp_nlt_f32 */, MCK_OMod, 16 /* 4 */ },
25055 : { Feature_isGCN|Feature_isVI, 7276 /* v_cmp_nlt_f32 */, MCK_Clamp, 8 /* 3 */ },
25056 : { Feature_isGCN|Feature_isVI, 7276 /* v_cmp_nlt_f32 */, MCK_OMod, 16 /* 4 */ },
25057 : { Feature_isGCN|Feature_isSICI, 7290 /* v_cmp_nlt_f64 */, MCK_Clamp, 8 /* 3 */ },
25058 : { Feature_isGCN|Feature_isSICI, 7290 /* v_cmp_nlt_f64 */, MCK_OMod, 16 /* 4 */ },
25059 : { Feature_isGCN|Feature_isVI, 7290 /* v_cmp_nlt_f64 */, MCK_Clamp, 8 /* 3 */ },
25060 : { Feature_isGCN|Feature_isVI, 7290 /* v_cmp_nlt_f64 */, MCK_OMod, 16 /* 4 */ },
25061 : { Feature_isGCN|Feature_isSICI, 7304 /* v_cmp_o_f32 */, MCK_Clamp, 8 /* 3 */ },
25062 : { Feature_isGCN|Feature_isSICI, 7304 /* v_cmp_o_f32 */, MCK_OMod, 16 /* 4 */ },
25063 : { Feature_isGCN|Feature_isVI, 7304 /* v_cmp_o_f32 */, MCK_Clamp, 8 /* 3 */ },
25064 : { Feature_isGCN|Feature_isVI, 7304 /* v_cmp_o_f32 */, MCK_OMod, 16 /* 4 */ },
25065 : { Feature_isGCN|Feature_isSICI, 7316 /* v_cmp_o_f64 */, MCK_Clamp, 8 /* 3 */ },
25066 : { Feature_isGCN|Feature_isSICI, 7316 /* v_cmp_o_f64 */, MCK_OMod, 16 /* 4 */ },
25067 : { Feature_isGCN|Feature_isVI, 7316 /* v_cmp_o_f64 */, MCK_Clamp, 8 /* 3 */ },
25068 : { Feature_isGCN|Feature_isVI, 7316 /* v_cmp_o_f64 */, MCK_OMod, 16 /* 4 */ },
25069 : { Feature_isGCN|Feature_isSICI, 7376 /* v_cmp_tru_f32 */, MCK_Clamp, 8 /* 3 */ },
25070 : { Feature_isGCN|Feature_isSICI, 7376 /* v_cmp_tru_f32 */, MCK_OMod, 16 /* 4 */ },
25071 : { Feature_isGCN|Feature_isVI, 7376 /* v_cmp_tru_f32 */, MCK_Clamp, 8 /* 3 */ },
25072 : { Feature_isGCN|Feature_isVI, 7376 /* v_cmp_tru_f32 */, MCK_OMod, 16 /* 4 */ },
25073 : { Feature_isGCN|Feature_isSICI, 7390 /* v_cmp_tru_f64 */, MCK_Clamp, 8 /* 3 */ },
25074 : { Feature_isGCN|Feature_isSICI, 7390 /* v_cmp_tru_f64 */, MCK_OMod, 16 /* 4 */ },
25075 : { Feature_isGCN|Feature_isVI, 7390 /* v_cmp_tru_f64 */, MCK_Clamp, 8 /* 3 */ },
25076 : { Feature_isGCN|Feature_isVI, 7390 /* v_cmp_tru_f64 */, MCK_OMod, 16 /* 4 */ },
25077 : { Feature_isGCN|Feature_isSICI, 7404 /* v_cmp_u_f32 */, MCK_Clamp, 8 /* 3 */ },
25078 : { Feature_isGCN|Feature_isSICI, 7404 /* v_cmp_u_f32 */, MCK_OMod, 16 /* 4 */ },
25079 : { Feature_isGCN|Feature_isVI, 7404 /* v_cmp_u_f32 */, MCK_Clamp, 8 /* 3 */ },
25080 : { Feature_isGCN|Feature_isVI, 7404 /* v_cmp_u_f32 */, MCK_OMod, 16 /* 4 */ },
25081 : { Feature_isGCN|Feature_isSICI, 7416 /* v_cmp_u_f64 */, MCK_Clamp, 8 /* 3 */ },
25082 : { Feature_isGCN|Feature_isSICI, 7416 /* v_cmp_u_f64 */, MCK_OMod, 16 /* 4 */ },
25083 : { Feature_isGCN|Feature_isVI, 7416 /* v_cmp_u_f64 */, MCK_Clamp, 8 /* 3 */ },
25084 : { Feature_isGCN|Feature_isVI, 7416 /* v_cmp_u_f64 */, MCK_OMod, 16 /* 4 */ },
25085 : { Feature_isSICI|Feature_isSICI, 7428 /* v_cmps_eq_f32 */, MCK_Clamp, 8 /* 3 */ },
25086 : { Feature_isSICI|Feature_isSICI, 7428 /* v_cmps_eq_f32 */, MCK_OMod, 16 /* 4 */ },
25087 : { Feature_isSICI|Feature_isVI, 7428 /* v_cmps_eq_f32 */, MCK_Clamp, 8 /* 3 */ },
25088 : { Feature_isSICI|Feature_isVI, 7428 /* v_cmps_eq_f32 */, MCK_OMod, 16 /* 4 */ },
25089 : { Feature_isSICI|Feature_isSICI, 7442 /* v_cmps_eq_f64 */, MCK_Clamp, 8 /* 3 */ },
25090 : { Feature_isSICI|Feature_isSICI, 7442 /* v_cmps_eq_f64 */, MCK_OMod, 16 /* 4 */ },
25091 : { Feature_isSICI|Feature_isVI, 7442 /* v_cmps_eq_f64 */, MCK_Clamp, 8 /* 3 */ },
25092 : { Feature_isSICI|Feature_isVI, 7442 /* v_cmps_eq_f64 */, MCK_OMod, 16 /* 4 */ },
25093 : { Feature_isSICI|Feature_isSICI, 7456 /* v_cmps_f_f32 */, MCK_Clamp, 8 /* 3 */ },
25094 : { Feature_isSICI|Feature_isSICI, 7456 /* v_cmps_f_f32 */, MCK_OMod, 16 /* 4 */ },
25095 : { Feature_isSICI|Feature_isVI, 7456 /* v_cmps_f_f32 */, MCK_Clamp, 8 /* 3 */ },
25096 : { Feature_isSICI|Feature_isVI, 7456 /* v_cmps_f_f32 */, MCK_OMod, 16 /* 4 */ },
25097 : { Feature_isSICI|Feature_isSICI, 7469 /* v_cmps_f_f64 */, MCK_Clamp, 8 /* 3 */ },
25098 : { Feature_isSICI|Feature_isSICI, 7469 /* v_cmps_f_f64 */, MCK_OMod, 16 /* 4 */ },
25099 : { Feature_isSICI|Feature_isVI, 7469 /* v_cmps_f_f64 */, MCK_Clamp, 8 /* 3 */ },
25100 : { Feature_isSICI|Feature_isVI, 7469 /* v_cmps_f_f64 */, MCK_OMod, 16 /* 4 */ },
25101 : { Feature_isSICI|Feature_isSICI, 7482 /* v_cmps_ge_f32 */, MCK_Clamp, 8 /* 3 */ },
25102 : { Feature_isSICI|Feature_isSICI, 7482 /* v_cmps_ge_f32 */, MCK_OMod, 16 /* 4 */ },
25103 : { Feature_isSICI|Feature_isVI, 7482 /* v_cmps_ge_f32 */, MCK_Clamp, 8 /* 3 */ },
25104 : { Feature_isSICI|Feature_isVI, 7482 /* v_cmps_ge_f32 */, MCK_OMod, 16 /* 4 */ },
25105 : { Feature_isSICI|Feature_isSICI, 7496 /* v_cmps_ge_f64 */, MCK_Clamp, 8 /* 3 */ },
25106 : { Feature_isSICI|Feature_isSICI, 7496 /* v_cmps_ge_f64 */, MCK_OMod, 16 /* 4 */ },
25107 : { Feature_isSICI|Feature_isVI, 7496 /* v_cmps_ge_f64 */, MCK_Clamp, 8 /* 3 */ },
25108 : { Feature_isSICI|Feature_isVI, 7496 /* v_cmps_ge_f64 */, MCK_OMod, 16 /* 4 */ },
25109 : { Feature_isSICI|Feature_isSICI, 7510 /* v_cmps_gt_f32 */, MCK_Clamp, 8 /* 3 */ },
25110 : { Feature_isSICI|Feature_isSICI, 7510 /* v_cmps_gt_f32 */, MCK_OMod, 16 /* 4 */ },
25111 : { Feature_isSICI|Feature_isVI, 7510 /* v_cmps_gt_f32 */, MCK_Clamp, 8 /* 3 */ },
25112 : { Feature_isSICI|Feature_isVI, 7510 /* v_cmps_gt_f32 */, MCK_OMod, 16 /* 4 */ },
25113 : { Feature_isSICI|Feature_isSICI, 7524 /* v_cmps_gt_f64 */, MCK_Clamp, 8 /* 3 */ },
25114 : { Feature_isSICI|Feature_isSICI, 7524 /* v_cmps_gt_f64 */, MCK_OMod, 16 /* 4 */ },
25115 : { Feature_isSICI|Feature_isVI, 7524 /* v_cmps_gt_f64 */, MCK_Clamp, 8 /* 3 */ },
25116 : { Feature_isSICI|Feature_isVI, 7524 /* v_cmps_gt_f64 */, MCK_OMod, 16 /* 4 */ },
25117 : { Feature_isSICI|Feature_isSICI, 7538 /* v_cmps_le_f32 */, MCK_Clamp, 8 /* 3 */ },
25118 : { Feature_isSICI|Feature_isSICI, 7538 /* v_cmps_le_f32 */, MCK_OMod, 16 /* 4 */ },
25119 : { Feature_isSICI|Feature_isVI, 7538 /* v_cmps_le_f32 */, MCK_Clamp, 8 /* 3 */ },
25120 : { Feature_isSICI|Feature_isVI, 7538 /* v_cmps_le_f32 */, MCK_OMod, 16 /* 4 */ },
25121 : { Feature_isSICI|Feature_isSICI, 7552 /* v_cmps_le_f64 */, MCK_Clamp, 8 /* 3 */ },
25122 : { Feature_isSICI|Feature_isSICI, 7552 /* v_cmps_le_f64 */, MCK_OMod, 16 /* 4 */ },
25123 : { Feature_isSICI|Feature_isVI, 7552 /* v_cmps_le_f64 */, MCK_Clamp, 8 /* 3 */ },
25124 : { Feature_isSICI|Feature_isVI, 7552 /* v_cmps_le_f64 */, MCK_OMod, 16 /* 4 */ },
25125 : { Feature_isSICI|Feature_isSICI, 7566 /* v_cmps_lg_f32 */, MCK_Clamp, 8 /* 3 */ },
25126 : { Feature_isSICI|Feature_isSICI, 7566 /* v_cmps_lg_f32 */, MCK_OMod, 16 /* 4 */ },
25127 : { Feature_isSICI|Feature_isVI, 7566 /* v_cmps_lg_f32 */, MCK_Clamp, 8 /* 3 */ },
25128 : { Feature_isSICI|Feature_isVI, 7566 /* v_cmps_lg_f32 */, MCK_OMod, 16 /* 4 */ },
25129 : { Feature_isSICI|Feature_isSICI, 7580 /* v_cmps_lg_f64 */, MCK_Clamp, 8 /* 3 */ },
25130 : { Feature_isSICI|Feature_isSICI, 7580 /* v_cmps_lg_f64 */, MCK_OMod, 16 /* 4 */ },
25131 : { Feature_isSICI|Feature_isVI, 7580 /* v_cmps_lg_f64 */, MCK_Clamp, 8 /* 3 */ },
25132 : { Feature_isSICI|Feature_isVI, 7580 /* v_cmps_lg_f64 */, MCK_OMod, 16 /* 4 */ },
25133 : { Feature_isSICI|Feature_isSICI, 7594 /* v_cmps_lt_f32 */, MCK_Clamp, 8 /* 3 */ },
25134 : { Feature_isSICI|Feature_isSICI, 7594 /* v_cmps_lt_f32 */, MCK_OMod, 16 /* 4 */ },
25135 : { Feature_isSICI|Feature_isVI, 7594 /* v_cmps_lt_f32 */, MCK_Clamp, 8 /* 3 */ },
25136 : { Feature_isSICI|Feature_isVI, 7594 /* v_cmps_lt_f32 */, MCK_OMod, 16 /* 4 */ },
25137 : { Feature_isSICI|Feature_isSICI, 7608 /* v_cmps_lt_f64 */, MCK_Clamp, 8 /* 3 */ },
25138 : { Feature_isSICI|Feature_isSICI, 7608 /* v_cmps_lt_f64 */, MCK_OMod, 16 /* 4 */ },
25139 : { Feature_isSICI|Feature_isVI, 7608 /* v_cmps_lt_f64 */, MCK_Clamp, 8 /* 3 */ },
25140 : { Feature_isSICI|Feature_isVI, 7608 /* v_cmps_lt_f64 */, MCK_OMod, 16 /* 4 */ },
25141 : { Feature_isSICI|Feature_isSICI, 7622 /* v_cmps_neq_f32 */, MCK_Clamp, 8 /* 3 */ },
25142 : { Feature_isSICI|Feature_isSICI, 7622 /* v_cmps_neq_f32 */, MCK_OMod, 16 /* 4 */ },
25143 : { Feature_isSICI|Feature_isVI, 7622 /* v_cmps_neq_f32 */, MCK_Clamp, 8 /* 3 */ },
25144 : { Feature_isSICI|Feature_isVI, 7622 /* v_cmps_neq_f32 */, MCK_OMod, 16 /* 4 */ },
25145 : { Feature_isSICI|Feature_isSICI, 7637 /* v_cmps_neq_f64 */, MCK_Clamp, 8 /* 3 */ },
25146 : { Feature_isSICI|Feature_isSICI, 7637 /* v_cmps_neq_f64 */, MCK_OMod, 16 /* 4 */ },
25147 : { Feature_isSICI|Feature_isVI, 7637 /* v_cmps_neq_f64 */, MCK_Clamp, 8 /* 3 */ },
25148 : { Feature_isSICI|Feature_isVI, 7637 /* v_cmps_neq_f64 */, MCK_OMod, 16 /* 4 */ },
25149 : { Feature_isSICI|Feature_isSICI, 7652 /* v_cmps_nge_f32 */, MCK_Clamp, 8 /* 3 */ },
25150 : { Feature_isSICI|Feature_isSICI, 7652 /* v_cmps_nge_f32 */, MCK_OMod, 16 /* 4 */ },
25151 : { Feature_isSICI|Feature_isVI, 7652 /* v_cmps_nge_f32 */, MCK_Clamp, 8 /* 3 */ },
25152 : { Feature_isSICI|Feature_isVI, 7652 /* v_cmps_nge_f32 */, MCK_OMod, 16 /* 4 */ },
25153 : { Feature_isSICI|Feature_isSICI, 7667 /* v_cmps_nge_f64 */, MCK_Clamp, 8 /* 3 */ },
25154 : { Feature_isSICI|Feature_isSICI, 7667 /* v_cmps_nge_f64 */, MCK_OMod, 16 /* 4 */ },
25155 : { Feature_isSICI|Feature_isVI, 7667 /* v_cmps_nge_f64 */, MCK_Clamp, 8 /* 3 */ },
25156 : { Feature_isSICI|Feature_isVI, 7667 /* v_cmps_nge_f64 */, MCK_OMod, 16 /* 4 */ },
25157 : { Feature_isSICI|Feature_isSICI, 7682 /* v_cmps_ngt_f32 */, MCK_Clamp, 8 /* 3 */ },
25158 : { Feature_isSICI|Feature_isSICI, 7682 /* v_cmps_ngt_f32 */, MCK_OMod, 16 /* 4 */ },
25159 : { Feature_isSICI|Feature_isVI, 7682 /* v_cmps_ngt_f32 */, MCK_Clamp, 8 /* 3 */ },
25160 : { Feature_isSICI|Feature_isVI, 7682 /* v_cmps_ngt_f32 */, MCK_OMod, 16 /* 4 */ },
25161 : { Feature_isSICI|Feature_isSICI, 7697 /* v_cmps_ngt_f64 */, MCK_Clamp, 8 /* 3 */ },
25162 : { Feature_isSICI|Feature_isSICI, 7697 /* v_cmps_ngt_f64 */, MCK_OMod, 16 /* 4 */ },
25163 : { Feature_isSICI|Feature_isVI, 7697 /* v_cmps_ngt_f64 */, MCK_Clamp, 8 /* 3 */ },
25164 : { Feature_isSICI|Feature_isVI, 7697 /* v_cmps_ngt_f64 */, MCK_OMod, 16 /* 4 */ },
25165 : { Feature_isSICI|Feature_isSICI, 7712 /* v_cmps_nle_f32 */, MCK_Clamp, 8 /* 3 */ },
25166 : { Feature_isSICI|Feature_isSICI, 7712 /* v_cmps_nle_f32 */, MCK_OMod, 16 /* 4 */ },
25167 : { Feature_isSICI|Feature_isVI, 7712 /* v_cmps_nle_f32 */, MCK_Clamp, 8 /* 3 */ },
25168 : { Feature_isSICI|Feature_isVI, 7712 /* v_cmps_nle_f32 */, MCK_OMod, 16 /* 4 */ },
25169 : { Feature_isSICI|Feature_isSICI, 7727 /* v_cmps_nle_f64 */, MCK_Clamp, 8 /* 3 */ },
25170 : { Feature_isSICI|Feature_isSICI, 7727 /* v_cmps_nle_f64 */, MCK_OMod, 16 /* 4 */ },
25171 : { Feature_isSICI|Feature_isVI, 7727 /* v_cmps_nle_f64 */, MCK_Clamp, 8 /* 3 */ },
25172 : { Feature_isSICI|Feature_isVI, 7727 /* v_cmps_nle_f64 */, MCK_OMod, 16 /* 4 */ },
25173 : { Feature_isSICI|Feature_isSICI, 7742 /* v_cmps_nlg_f32 */, MCK_Clamp, 8 /* 3 */ },
25174 : { Feature_isSICI|Feature_isSICI, 7742 /* v_cmps_nlg_f32 */, MCK_OMod, 16 /* 4 */ },
25175 : { Feature_isSICI|Feature_isVI, 7742 /* v_cmps_nlg_f32 */, MCK_Clamp, 8 /* 3 */ },
25176 : { Feature_isSICI|Feature_isVI, 7742 /* v_cmps_nlg_f32 */, MCK_OMod, 16 /* 4 */ },
25177 : { Feature_isSICI|Feature_isSICI, 7757 /* v_cmps_nlg_f64 */, MCK_Clamp, 8 /* 3 */ },
25178 : { Feature_isSICI|Feature_isSICI, 7757 /* v_cmps_nlg_f64 */, MCK_OMod, 16 /* 4 */ },
25179 : { Feature_isSICI|Feature_isVI, 7757 /* v_cmps_nlg_f64 */, MCK_Clamp, 8 /* 3 */ },
25180 : { Feature_isSICI|Feature_isVI, 7757 /* v_cmps_nlg_f64 */, MCK_OMod, 16 /* 4 */ },
25181 : { Feature_isSICI|Feature_isSICI, 7772 /* v_cmps_nlt_f32 */, MCK_Clamp, 8 /* 3 */ },
25182 : { Feature_isSICI|Feature_isSICI, 7772 /* v_cmps_nlt_f32 */, MCK_OMod, 16 /* 4 */ },
25183 : { Feature_isSICI|Feature_isVI, 7772 /* v_cmps_nlt_f32 */, MCK_Clamp, 8 /* 3 */ },
25184 : { Feature_isSICI|Feature_isVI, 7772 /* v_cmps_nlt_f32 */, MCK_OMod, 16 /* 4 */ },
25185 : { Feature_isSICI|Feature_isSICI, 7787 /* v_cmps_nlt_f64 */, MCK_Clamp, 8 /* 3 */ },
25186 : { Feature_isSICI|Feature_isSICI, 7787 /* v_cmps_nlt_f64 */, MCK_OMod, 16 /* 4 */ },
25187 : { Feature_isSICI|Feature_isVI, 7787 /* v_cmps_nlt_f64 */, MCK_Clamp, 8 /* 3 */ },
25188 : { Feature_isSICI|Feature_isVI, 7787 /* v_cmps_nlt_f64 */, MCK_OMod, 16 /* 4 */ },
25189 : { Feature_isSICI|Feature_isSICI, 7802 /* v_cmps_o_f32 */, MCK_Clamp, 8 /* 3 */ },
25190 : { Feature_isSICI|Feature_isSICI, 7802 /* v_cmps_o_f32 */, MCK_OMod, 16 /* 4 */ },
25191 : { Feature_isSICI|Feature_isVI, 7802 /* v_cmps_o_f32 */, MCK_Clamp, 8 /* 3 */ },
25192 : { Feature_isSICI|Feature_isVI, 7802 /* v_cmps_o_f32 */, MCK_OMod, 16 /* 4 */ },
25193 : { Feature_isSICI|Feature_isSICI, 7815 /* v_cmps_o_f64 */, MCK_Clamp, 8 /* 3 */ },
25194 : { Feature_isSICI|Feature_isSICI, 7815 /* v_cmps_o_f64 */, MCK_OMod, 16 /* 4 */ },
25195 : { Feature_isSICI|Feature_isVI, 7815 /* v_cmps_o_f64 */, MCK_Clamp, 8 /* 3 */ },
25196 : { Feature_isSICI|Feature_isVI, 7815 /* v_cmps_o_f64 */, MCK_OMod, 16 /* 4 */ },
25197 : { Feature_isSICI|Feature_isSICI, 7828 /* v_cmps_tru_f32 */, MCK_Clamp, 8 /* 3 */ },
25198 : { Feature_isSICI|Feature_isSICI, 7828 /* v_cmps_tru_f32 */, MCK_OMod, 16 /* 4 */ },
25199 : { Feature_isSICI|Feature_isVI, 7828 /* v_cmps_tru_f32 */, MCK_Clamp, 8 /* 3 */ },
25200 : { Feature_isSICI|Feature_isVI, 7828 /* v_cmps_tru_f32 */, MCK_OMod, 16 /* 4 */ },
25201 : { Feature_isSICI|Feature_isSICI, 7843 /* v_cmps_tru_f64 */, MCK_Clamp, 8 /* 3 */ },
25202 : { Feature_isSICI|Feature_isSICI, 7843 /* v_cmps_tru_f64 */, MCK_OMod, 16 /* 4 */ },
25203 : { Feature_isSICI|Feature_isVI, 7843 /* v_cmps_tru_f64 */, MCK_Clamp, 8 /* 3 */ },
25204 : { Feature_isSICI|Feature_isVI, 7843 /* v_cmps_tru_f64 */, MCK_OMod, 16 /* 4 */ },
25205 : { Feature_isSICI|Feature_isSICI, 7858 /* v_cmps_u_f32 */, MCK_Clamp, 8 /* 3 */ },
25206 : { Feature_isSICI|Feature_isSICI, 7858 /* v_cmps_u_f32 */, MCK_OMod, 16 /* 4 */ },
25207 : { Feature_isSICI|Feature_isVI, 7858 /* v_cmps_u_f32 */, MCK_Clamp, 8 /* 3 */ },
25208 : { Feature_isSICI|Feature_isVI, 7858 /* v_cmps_u_f32 */, MCK_OMod, 16 /* 4 */ },
25209 : { Feature_isSICI|Feature_isSICI, 7871 /* v_cmps_u_f64 */, MCK_Clamp, 8 /* 3 */ },
25210 : { Feature_isSICI|Feature_isSICI, 7871 /* v_cmps_u_f64 */, MCK_OMod, 16 /* 4 */ },
25211 : { Feature_isSICI|Feature_isVI, 7871 /* v_cmps_u_f64 */, MCK_Clamp, 8 /* 3 */ },
25212 : { Feature_isSICI|Feature_isVI, 7871 /* v_cmps_u_f64 */, MCK_OMod, 16 /* 4 */ },
25213 : { Feature_isSICI|Feature_isSICI, 7884 /* v_cmpsx_eq_f32 */, MCK_Clamp, 8 /* 3 */ },
25214 : { Feature_isSICI|Feature_isSICI, 7884 /* v_cmpsx_eq_f32 */, MCK_OMod, 16 /* 4 */ },
25215 : { Feature_isSICI|Feature_isVI, 7884 /* v_cmpsx_eq_f32 */, MCK_Clamp, 8 /* 3 */ },
25216 : { Feature_isSICI|Feature_isVI, 7884 /* v_cmpsx_eq_f32 */, MCK_OMod, 16 /* 4 */ },
25217 : { Feature_isSICI|Feature_isSICI, 7899 /* v_cmpsx_eq_f64 */, MCK_Clamp, 8 /* 3 */ },
25218 : { Feature_isSICI|Feature_isSICI, 7899 /* v_cmpsx_eq_f64 */, MCK_OMod, 16 /* 4 */ },
25219 : { Feature_isSICI|Feature_isVI, 7899 /* v_cmpsx_eq_f64 */, MCK_Clamp, 8 /* 3 */ },
25220 : { Feature_isSICI|Feature_isVI, 7899 /* v_cmpsx_eq_f64 */, MCK_OMod, 16 /* 4 */ },
25221 : { Feature_isSICI|Feature_isSICI, 7914 /* v_cmpsx_f_f32 */, MCK_Clamp, 8 /* 3 */ },
25222 : { Feature_isSICI|Feature_isSICI, 7914 /* v_cmpsx_f_f32 */, MCK_OMod, 16 /* 4 */ },
25223 : { Feature_isSICI|Feature_isVI, 7914 /* v_cmpsx_f_f32 */, MCK_Clamp, 8 /* 3 */ },
25224 : { Feature_isSICI|Feature_isVI, 7914 /* v_cmpsx_f_f32 */, MCK_OMod, 16 /* 4 */ },
25225 : { Feature_isSICI|Feature_isSICI, 7928 /* v_cmpsx_f_f64 */, MCK_Clamp, 8 /* 3 */ },
25226 : { Feature_isSICI|Feature_isSICI, 7928 /* v_cmpsx_f_f64 */, MCK_OMod, 16 /* 4 */ },
25227 : { Feature_isSICI|Feature_isVI, 7928 /* v_cmpsx_f_f64 */, MCK_Clamp, 8 /* 3 */ },
25228 : { Feature_isSICI|Feature_isVI, 7928 /* v_cmpsx_f_f64 */, MCK_OMod, 16 /* 4 */ },
25229 : { Feature_isSICI|Feature_isSICI, 7942 /* v_cmpsx_ge_f32 */, MCK_Clamp, 8 /* 3 */ },
25230 : { Feature_isSICI|Feature_isSICI, 7942 /* v_cmpsx_ge_f32 */, MCK_OMod, 16 /* 4 */ },
25231 : { Feature_isSICI|Feature_isVI, 7942 /* v_cmpsx_ge_f32 */, MCK_Clamp, 8 /* 3 */ },
25232 : { Feature_isSICI|Feature_isVI, 7942 /* v_cmpsx_ge_f32 */, MCK_OMod, 16 /* 4 */ },
25233 : { Feature_isSICI|Feature_isSICI, 7957 /* v_cmpsx_ge_f64 */, MCK_Clamp, 8 /* 3 */ },
25234 : { Feature_isSICI|Feature_isSICI, 7957 /* v_cmpsx_ge_f64 */, MCK_OMod, 16 /* 4 */ },
25235 : { Feature_isSICI|Feature_isVI, 7957 /* v_cmpsx_ge_f64 */, MCK_Clamp, 8 /* 3 */ },
25236 : { Feature_isSICI|Feature_isVI, 7957 /* v_cmpsx_ge_f64 */, MCK_OMod, 16 /* 4 */ },
25237 : { Feature_isSICI|Feature_isSICI, 7972 /* v_cmpsx_gt_f32 */, MCK_Clamp, 8 /* 3 */ },
25238 : { Feature_isSICI|Feature_isSICI, 7972 /* v_cmpsx_gt_f32 */, MCK_OMod, 16 /* 4 */ },
25239 : { Feature_isSICI|Feature_isVI, 7972 /* v_cmpsx_gt_f32 */, MCK_Clamp, 8 /* 3 */ },
25240 : { Feature_isSICI|Feature_isVI, 7972 /* v_cmpsx_gt_f32 */, MCK_OMod, 16 /* 4 */ },
25241 : { Feature_isSICI|Feature_isSICI, 7987 /* v_cmpsx_gt_f64 */, MCK_Clamp, 8 /* 3 */ },
25242 : { Feature_isSICI|Feature_isSICI, 7987 /* v_cmpsx_gt_f64 */, MCK_OMod, 16 /* 4 */ },
25243 : { Feature_isSICI|Feature_isVI, 7987 /* v_cmpsx_gt_f64 */, MCK_Clamp, 8 /* 3 */ },
25244 : { Feature_isSICI|Feature_isVI, 7987 /* v_cmpsx_gt_f64 */, MCK_OMod, 16 /* 4 */ },
25245 : { Feature_isSICI|Feature_isSICI, 8002 /* v_cmpsx_le_f32 */, MCK_Clamp, 8 /* 3 */ },
25246 : { Feature_isSICI|Feature_isSICI, 8002 /* v_cmpsx_le_f32 */, MCK_OMod, 16 /* 4 */ },
25247 : { Feature_isSICI|Feature_isVI, 8002 /* v_cmpsx_le_f32 */, MCK_Clamp, 8 /* 3 */ },
25248 : { Feature_isSICI|Feature_isVI, 8002 /* v_cmpsx_le_f32 */, MCK_OMod, 16 /* 4 */ },
25249 : { Feature_isSICI|Feature_isSICI, 8017 /* v_cmpsx_le_f64 */, MCK_Clamp, 8 /* 3 */ },
25250 : { Feature_isSICI|Feature_isSICI, 8017 /* v_cmpsx_le_f64 */, MCK_OMod, 16 /* 4 */ },
25251 : { Feature_isSICI|Feature_isVI, 8017 /* v_cmpsx_le_f64 */, MCK_Clamp, 8 /* 3 */ },
25252 : { Feature_isSICI|Feature_isVI, 8017 /* v_cmpsx_le_f64 */, MCK_OMod, 16 /* 4 */ },
25253 : { Feature_isSICI|Feature_isSICI, 8032 /* v_cmpsx_lg_f32 */, MCK_Clamp, 8 /* 3 */ },
25254 : { Feature_isSICI|Feature_isSICI, 8032 /* v_cmpsx_lg_f32 */, MCK_OMod, 16 /* 4 */ },
25255 : { Feature_isSICI|Feature_isVI, 8032 /* v_cmpsx_lg_f32 */, MCK_Clamp, 8 /* 3 */ },
25256 : { Feature_isSICI|Feature_isVI, 8032 /* v_cmpsx_lg_f32 */, MCK_OMod, 16 /* 4 */ },
25257 : { Feature_isSICI|Feature_isSICI, 8047 /* v_cmpsx_lg_f64 */, MCK_Clamp, 8 /* 3 */ },
25258 : { Feature_isSICI|Feature_isSICI, 8047 /* v_cmpsx_lg_f64 */, MCK_OMod, 16 /* 4 */ },
25259 : { Feature_isSICI|Feature_isVI, 8047 /* v_cmpsx_lg_f64 */, MCK_Clamp, 8 /* 3 */ },
25260 : { Feature_isSICI|Feature_isVI, 8047 /* v_cmpsx_lg_f64 */, MCK_OMod, 16 /* 4 */ },
25261 : { Feature_isSICI|Feature_isSICI, 8062 /* v_cmpsx_lt_f32 */, MCK_Clamp, 8 /* 3 */ },
25262 : { Feature_isSICI|Feature_isSICI, 8062 /* v_cmpsx_lt_f32 */, MCK_OMod, 16 /* 4 */ },
25263 : { Feature_isSICI|Feature_isVI, 8062 /* v_cmpsx_lt_f32 */, MCK_Clamp, 8 /* 3 */ },
25264 : { Feature_isSICI|Feature_isVI, 8062 /* v_cmpsx_lt_f32 */, MCK_OMod, 16 /* 4 */ },
25265 : { Feature_isSICI|Feature_isSICI, 8077 /* v_cmpsx_lt_f64 */, MCK_Clamp, 8 /* 3 */ },
25266 : { Feature_isSICI|Feature_isSICI, 8077 /* v_cmpsx_lt_f64 */, MCK_OMod, 16 /* 4 */ },
25267 : { Feature_isSICI|Feature_isVI, 8077 /* v_cmpsx_lt_f64 */, MCK_Clamp, 8 /* 3 */ },
25268 : { Feature_isSICI|Feature_isVI, 8077 /* v_cmpsx_lt_f64 */, MCK_OMod, 16 /* 4 */ },
25269 : { Feature_isSICI|Feature_isSICI, 8092 /* v_cmpsx_neq_f32 */, MCK_Clamp, 8 /* 3 */ },
25270 : { Feature_isSICI|Feature_isSICI, 8092 /* v_cmpsx_neq_f32 */, MCK_OMod, 16 /* 4 */ },
25271 : { Feature_isSICI|Feature_isVI, 8092 /* v_cmpsx_neq_f32 */, MCK_Clamp, 8 /* 3 */ },
25272 : { Feature_isSICI|Feature_isVI, 8092 /* v_cmpsx_neq_f32 */, MCK_OMod, 16 /* 4 */ },
25273 : { Feature_isSICI|Feature_isSICI, 8108 /* v_cmpsx_neq_f64 */, MCK_Clamp, 8 /* 3 */ },
25274 : { Feature_isSICI|Feature_isSICI, 8108 /* v_cmpsx_neq_f64 */, MCK_OMod, 16 /* 4 */ },
25275 : { Feature_isSICI|Feature_isVI, 8108 /* v_cmpsx_neq_f64 */, MCK_Clamp, 8 /* 3 */ },
25276 : { Feature_isSICI|Feature_isVI, 8108 /* v_cmpsx_neq_f64 */, MCK_OMod, 16 /* 4 */ },
25277 : { Feature_isSICI|Feature_isSICI, 8124 /* v_cmpsx_nge_f32 */, MCK_Clamp, 8 /* 3 */ },
25278 : { Feature_isSICI|Feature_isSICI, 8124 /* v_cmpsx_nge_f32 */, MCK_OMod, 16 /* 4 */ },
25279 : { Feature_isSICI|Feature_isVI, 8124 /* v_cmpsx_nge_f32 */, MCK_Clamp, 8 /* 3 */ },
25280 : { Feature_isSICI|Feature_isVI, 8124 /* v_cmpsx_nge_f32 */, MCK_OMod, 16 /* 4 */ },
25281 : { Feature_isSICI|Feature_isSICI, 8140 /* v_cmpsx_nge_f64 */, MCK_Clamp, 8 /* 3 */ },
25282 : { Feature_isSICI|Feature_isSICI, 8140 /* v_cmpsx_nge_f64 */, MCK_OMod, 16 /* 4 */ },
25283 : { Feature_isSICI|Feature_isVI, 8140 /* v_cmpsx_nge_f64 */, MCK_Clamp, 8 /* 3 */ },
25284 : { Feature_isSICI|Feature_isVI, 8140 /* v_cmpsx_nge_f64 */, MCK_OMod, 16 /* 4 */ },
25285 : { Feature_isSICI|Feature_isSICI, 8156 /* v_cmpsx_ngt_f32 */, MCK_Clamp, 8 /* 3 */ },
25286 : { Feature_isSICI|Feature_isSICI, 8156 /* v_cmpsx_ngt_f32 */, MCK_OMod, 16 /* 4 */ },
25287 : { Feature_isSICI|Feature_isVI, 8156 /* v_cmpsx_ngt_f32 */, MCK_Clamp, 8 /* 3 */ },
25288 : { Feature_isSICI|Feature_isVI, 8156 /* v_cmpsx_ngt_f32 */, MCK_OMod, 16 /* 4 */ },
25289 : { Feature_isSICI|Feature_isSICI, 8172 /* v_cmpsx_ngt_f64 */, MCK_Clamp, 8 /* 3 */ },
25290 : { Feature_isSICI|Feature_isSICI, 8172 /* v_cmpsx_ngt_f64 */, MCK_OMod, 16 /* 4 */ },
25291 : { Feature_isSICI|Feature_isVI, 8172 /* v_cmpsx_ngt_f64 */, MCK_Clamp, 8 /* 3 */ },
25292 : { Feature_isSICI|Feature_isVI, 8172 /* v_cmpsx_ngt_f64 */, MCK_OMod, 16 /* 4 */ },
25293 : { Feature_isSICI|Feature_isSICI, 8188 /* v_cmpsx_nle_f32 */, MCK_Clamp, 8 /* 3 */ },
25294 : { Feature_isSICI|Feature_isSICI, 8188 /* v_cmpsx_nle_f32 */, MCK_OMod, 16 /* 4 */ },
25295 : { Feature_isSICI|Feature_isVI, 8188 /* v_cmpsx_nle_f32 */, MCK_Clamp, 8 /* 3 */ },
25296 : { Feature_isSICI|Feature_isVI, 8188 /* v_cmpsx_nle_f32 */, MCK_OMod, 16 /* 4 */ },
25297 : { Feature_isSICI|Feature_isSICI, 8204 /* v_cmpsx_nle_f64 */, MCK_Clamp, 8 /* 3 */ },
25298 : { Feature_isSICI|Feature_isSICI, 8204 /* v_cmpsx_nle_f64 */, MCK_OMod, 16 /* 4 */ },
25299 : { Feature_isSICI|Feature_isVI, 8204 /* v_cmpsx_nle_f64 */, MCK_Clamp, 8 /* 3 */ },
25300 : { Feature_isSICI|Feature_isVI, 8204 /* v_cmpsx_nle_f64 */, MCK_OMod, 16 /* 4 */ },
25301 : { Feature_isSICI|Feature_isSICI, 8220 /* v_cmpsx_nlg_f32 */, MCK_Clamp, 8 /* 3 */ },
25302 : { Feature_isSICI|Feature_isSICI, 8220 /* v_cmpsx_nlg_f32 */, MCK_OMod, 16 /* 4 */ },
25303 : { Feature_isSICI|Feature_isVI, 8220 /* v_cmpsx_nlg_f32 */, MCK_Clamp, 8 /* 3 */ },
25304 : { Feature_isSICI|Feature_isVI, 8220 /* v_cmpsx_nlg_f32 */, MCK_OMod, 16 /* 4 */ },
25305 : { Feature_isSICI|Feature_isSICI, 8236 /* v_cmpsx_nlg_f64 */, MCK_Clamp, 8 /* 3 */ },
25306 : { Feature_isSICI|Feature_isSICI, 8236 /* v_cmpsx_nlg_f64 */, MCK_OMod, 16 /* 4 */ },
25307 : { Feature_isSICI|Feature_isVI, 8236 /* v_cmpsx_nlg_f64 */, MCK_Clamp, 8 /* 3 */ },
25308 : { Feature_isSICI|Feature_isVI, 8236 /* v_cmpsx_nlg_f64 */, MCK_OMod, 16 /* 4 */ },
25309 : { Feature_isSICI|Feature_isSICI, 8252 /* v_cmpsx_nlt_f32 */, MCK_Clamp, 8 /* 3 */ },
25310 : { Feature_isSICI|Feature_isSICI, 8252 /* v_cmpsx_nlt_f32 */, MCK_OMod, 16 /* 4 */ },
25311 : { Feature_isSICI|Feature_isVI, 8252 /* v_cmpsx_nlt_f32 */, MCK_Clamp, 8 /* 3 */ },
25312 : { Feature_isSICI|Feature_isVI, 8252 /* v_cmpsx_nlt_f32 */, MCK_OMod, 16 /* 4 */ },
25313 : { Feature_isSICI|Feature_isSICI, 8268 /* v_cmpsx_nlt_f64 */, MCK_Clamp, 8 /* 3 */ },
25314 : { Feature_isSICI|Feature_isSICI, 8268 /* v_cmpsx_nlt_f64 */, MCK_OMod, 16 /* 4 */ },
25315 : { Feature_isSICI|Feature_isVI, 8268 /* v_cmpsx_nlt_f64 */, MCK_Clamp, 8 /* 3 */ },
25316 : { Feature_isSICI|Feature_isVI, 8268 /* v_cmpsx_nlt_f64 */, MCK_OMod, 16 /* 4 */ },
25317 : { Feature_isSICI|Feature_isSICI, 8284 /* v_cmpsx_o_f32 */, MCK_Clamp, 8 /* 3 */ },
25318 : { Feature_isSICI|Feature_isSICI, 8284 /* v_cmpsx_o_f32 */, MCK_OMod, 16 /* 4 */ },
25319 : { Feature_isSICI|Feature_isVI, 8284 /* v_cmpsx_o_f32 */, MCK_Clamp, 8 /* 3 */ },
25320 : { Feature_isSICI|Feature_isVI, 8284 /* v_cmpsx_o_f32 */, MCK_OMod, 16 /* 4 */ },
25321 : { Feature_isSICI|Feature_isSICI, 8298 /* v_cmpsx_o_f64 */, MCK_Clamp, 8 /* 3 */ },
25322 : { Feature_isSICI|Feature_isSICI, 8298 /* v_cmpsx_o_f64 */, MCK_OMod, 16 /* 4 */ },
25323 : { Feature_isSICI|Feature_isVI, 8298 /* v_cmpsx_o_f64 */, MCK_Clamp, 8 /* 3 */ },
25324 : { Feature_isSICI|Feature_isVI, 8298 /* v_cmpsx_o_f64 */, MCK_OMod, 16 /* 4 */ },
25325 : { Feature_isSICI|Feature_isSICI, 8312 /* v_cmpsx_tru_f32 */, MCK_Clamp, 8 /* 3 */ },
25326 : { Feature_isSICI|Feature_isSICI, 8312 /* v_cmpsx_tru_f32 */, MCK_OMod, 16 /* 4 */ },
25327 : { Feature_isSICI|Feature_isVI, 8312 /* v_cmpsx_tru_f32 */, MCK_Clamp, 8 /* 3 */ },
25328 : { Feature_isSICI|Feature_isVI, 8312 /* v_cmpsx_tru_f32 */, MCK_OMod, 16 /* 4 */ },
25329 : { Feature_isSICI|Feature_isSICI, 8328 /* v_cmpsx_tru_f64 */, MCK_Clamp, 8 /* 3 */ },
25330 : { Feature_isSICI|Feature_isSICI, 8328 /* v_cmpsx_tru_f64 */, MCK_OMod, 16 /* 4 */ },
25331 : { Feature_isSICI|Feature_isVI, 8328 /* v_cmpsx_tru_f64 */, MCK_Clamp, 8 /* 3 */ },
25332 : { Feature_isSICI|Feature_isVI, 8328 /* v_cmpsx_tru_f64 */, MCK_OMod, 16 /* 4 */ },
25333 : { Feature_isSICI|Feature_isSICI, 8344 /* v_cmpsx_u_f32 */, MCK_Clamp, 8 /* 3 */ },
25334 : { Feature_isSICI|Feature_isSICI, 8344 /* v_cmpsx_u_f32 */, MCK_OMod, 16 /* 4 */ },
25335 : { Feature_isSICI|Feature_isVI, 8344 /* v_cmpsx_u_f32 */, MCK_Clamp, 8 /* 3 */ },
25336 : { Feature_isSICI|Feature_isVI, 8344 /* v_cmpsx_u_f32 */, MCK_OMod, 16 /* 4 */ },
25337 : { Feature_isSICI|Feature_isSICI, 8358 /* v_cmpsx_u_f64 */, MCK_Clamp, 8 /* 3 */ },
25338 : { Feature_isSICI|Feature_isSICI, 8358 /* v_cmpsx_u_f64 */, MCK_OMod, 16 /* 4 */ },
25339 : { Feature_isSICI|Feature_isVI, 8358 /* v_cmpsx_u_f64 */, MCK_Clamp, 8 /* 3 */ },
25340 : { Feature_isSICI|Feature_isVI, 8358 /* v_cmpsx_u_f64 */, MCK_OMod, 16 /* 4 */ },
25341 : { Feature_isGCN|Feature_isSICI, 8406 /* v_cmpx_eq_f32 */, MCK_Clamp, 8 /* 3 */ },
25342 : { Feature_isGCN|Feature_isSICI, 8406 /* v_cmpx_eq_f32 */, MCK_OMod, 16 /* 4 */ },
25343 : { Feature_isGCN|Feature_isVI, 8406 /* v_cmpx_eq_f32 */, MCK_Clamp, 8 /* 3 */ },
25344 : { Feature_isGCN|Feature_isVI, 8406 /* v_cmpx_eq_f32 */, MCK_OMod, 16 /* 4 */ },
25345 : { Feature_isGCN|Feature_isSICI, 8420 /* v_cmpx_eq_f64 */, MCK_Clamp, 8 /* 3 */ },
25346 : { Feature_isGCN|Feature_isSICI, 8420 /* v_cmpx_eq_f64 */, MCK_OMod, 16 /* 4 */ },
25347 : { Feature_isGCN|Feature_isVI, 8420 /* v_cmpx_eq_f64 */, MCK_Clamp, 8 /* 3 */ },
25348 : { Feature_isGCN|Feature_isVI, 8420 /* v_cmpx_eq_f64 */, MCK_OMod, 16 /* 4 */ },
25349 : { Feature_isGCN|Feature_isSICI, 8490 /* v_cmpx_f_f32 */, MCK_Clamp, 8 /* 3 */ },
25350 : { Feature_isGCN|Feature_isSICI, 8490 /* v_cmpx_f_f32 */, MCK_OMod, 16 /* 4 */ },
25351 : { Feature_isGCN|Feature_isVI, 8490 /* v_cmpx_f_f32 */, MCK_Clamp, 8 /* 3 */ },
25352 : { Feature_isGCN|Feature_isVI, 8490 /* v_cmpx_f_f32 */, MCK_OMod, 16 /* 4 */ },
25353 : { Feature_isGCN|Feature_isSICI, 8503 /* v_cmpx_f_f64 */, MCK_Clamp, 8 /* 3 */ },
25354 : { Feature_isGCN|Feature_isSICI, 8503 /* v_cmpx_f_f64 */, MCK_OMod, 16 /* 4 */ },
25355 : { Feature_isGCN|Feature_isVI, 8503 /* v_cmpx_f_f64 */, MCK_Clamp, 8 /* 3 */ },
25356 : { Feature_isGCN|Feature_isVI, 8503 /* v_cmpx_f_f64 */, MCK_OMod, 16 /* 4 */ },
25357 : { Feature_isGCN|Feature_isSICI, 8568 /* v_cmpx_ge_f32 */, MCK_Clamp, 8 /* 3 */ },
25358 : { Feature_isGCN|Feature_isSICI, 8568 /* v_cmpx_ge_f32 */, MCK_OMod, 16 /* 4 */ },
25359 : { Feature_isGCN|Feature_isVI, 8568 /* v_cmpx_ge_f32 */, MCK_Clamp, 8 /* 3 */ },
25360 : { Feature_isGCN|Feature_isVI, 8568 /* v_cmpx_ge_f32 */, MCK_OMod, 16 /* 4 */ },
25361 : { Feature_isGCN|Feature_isSICI, 8582 /* v_cmpx_ge_f64 */, MCK_Clamp, 8 /* 3 */ },
25362 : { Feature_isGCN|Feature_isSICI, 8582 /* v_cmpx_ge_f64 */, MCK_OMod, 16 /* 4 */ },
25363 : { Feature_isGCN|Feature_isVI, 8582 /* v_cmpx_ge_f64 */, MCK_Clamp, 8 /* 3 */ },
25364 : { Feature_isGCN|Feature_isVI, 8582 /* v_cmpx_ge_f64 */, MCK_OMod, 16 /* 4 */ },
25365 : { Feature_isGCN|Feature_isSICI, 8652 /* v_cmpx_gt_f32 */, MCK_Clamp, 8 /* 3 */ },
25366 : { Feature_isGCN|Feature_isSICI, 8652 /* v_cmpx_gt_f32 */, MCK_OMod, 16 /* 4 */ },
25367 : { Feature_isGCN|Feature_isVI, 8652 /* v_cmpx_gt_f32 */, MCK_Clamp, 8 /* 3 */ },
25368 : { Feature_isGCN|Feature_isVI, 8652 /* v_cmpx_gt_f32 */, MCK_OMod, 16 /* 4 */ },
25369 : { Feature_isGCN|Feature_isSICI, 8666 /* v_cmpx_gt_f64 */, MCK_Clamp, 8 /* 3 */ },
25370 : { Feature_isGCN|Feature_isSICI, 8666 /* v_cmpx_gt_f64 */, MCK_OMod, 16 /* 4 */ },
25371 : { Feature_isGCN|Feature_isVI, 8666 /* v_cmpx_gt_f64 */, MCK_Clamp, 8 /* 3 */ },
25372 : { Feature_isGCN|Feature_isVI, 8666 /* v_cmpx_gt_f64 */, MCK_OMod, 16 /* 4 */ },
25373 : { Feature_isGCN|Feature_isSICI, 8736 /* v_cmpx_le_f32 */, MCK_Clamp, 8 /* 3 */ },
25374 : { Feature_isGCN|Feature_isSICI, 8736 /* v_cmpx_le_f32 */, MCK_OMod, 16 /* 4 */ },
25375 : { Feature_isGCN|Feature_isVI, 8736 /* v_cmpx_le_f32 */, MCK_Clamp, 8 /* 3 */ },
25376 : { Feature_isGCN|Feature_isVI, 8736 /* v_cmpx_le_f32 */, MCK_OMod, 16 /* 4 */ },
25377 : { Feature_isGCN|Feature_isSICI, 8750 /* v_cmpx_le_f64 */, MCK_Clamp, 8 /* 3 */ },
25378 : { Feature_isGCN|Feature_isSICI, 8750 /* v_cmpx_le_f64 */, MCK_OMod, 16 /* 4 */ },
25379 : { Feature_isGCN|Feature_isVI, 8750 /* v_cmpx_le_f64 */, MCK_Clamp, 8 /* 3 */ },
25380 : { Feature_isGCN|Feature_isVI, 8750 /* v_cmpx_le_f64 */, MCK_OMod, 16 /* 4 */ },
25381 : { Feature_isGCN|Feature_isSICI, 8820 /* v_cmpx_lg_f32 */, MCK_Clamp, 8 /* 3 */ },
25382 : { Feature_isGCN|Feature_isSICI, 8820 /* v_cmpx_lg_f32 */, MCK_OMod, 16 /* 4 */ },
25383 : { Feature_isGCN|Feature_isVI, 8820 /* v_cmpx_lg_f32 */, MCK_Clamp, 8 /* 3 */ },
25384 : { Feature_isGCN|Feature_isVI, 8820 /* v_cmpx_lg_f32 */, MCK_OMod, 16 /* 4 */ },
25385 : { Feature_isGCN|Feature_isSICI, 8834 /* v_cmpx_lg_f64 */, MCK_Clamp, 8 /* 3 */ },
25386 : { Feature_isGCN|Feature_isSICI, 8834 /* v_cmpx_lg_f64 */, MCK_OMod, 16 /* 4 */ },
25387 : { Feature_isGCN|Feature_isVI, 8834 /* v_cmpx_lg_f64 */, MCK_Clamp, 8 /* 3 */ },
25388 : { Feature_isGCN|Feature_isVI, 8834 /* v_cmpx_lg_f64 */, MCK_OMod, 16 /* 4 */ },
25389 : { Feature_isGCN|Feature_isSICI, 8848 /* v_cmpx_lt_f32 */, MCK_Clamp, 8 /* 3 */ },
25390 : { Feature_isGCN|Feature_isSICI, 8848 /* v_cmpx_lt_f32 */, MCK_OMod, 16 /* 4 */ },
25391 : { Feature_isGCN|Feature_isVI, 8848 /* v_cmpx_lt_f32 */, MCK_Clamp, 8 /* 3 */ },
25392 : { Feature_isGCN|Feature_isVI, 8848 /* v_cmpx_lt_f32 */, MCK_OMod, 16 /* 4 */ },
25393 : { Feature_isGCN|Feature_isSICI, 8862 /* v_cmpx_lt_f64 */, MCK_Clamp, 8 /* 3 */ },
25394 : { Feature_isGCN|Feature_isSICI, 8862 /* v_cmpx_lt_f64 */, MCK_OMod, 16 /* 4 */ },
25395 : { Feature_isGCN|Feature_isVI, 8862 /* v_cmpx_lt_f64 */, MCK_Clamp, 8 /* 3 */ },
25396 : { Feature_isGCN|Feature_isVI, 8862 /* v_cmpx_lt_f64 */, MCK_OMod, 16 /* 4 */ },
25397 : { Feature_isGCN|Feature_isSICI, 8988 /* v_cmpx_neq_f32 */, MCK_Clamp, 8 /* 3 */ },
25398 : { Feature_isGCN|Feature_isSICI, 8988 /* v_cmpx_neq_f32 */, MCK_OMod, 16 /* 4 */ },
25399 : { Feature_isGCN|Feature_isVI, 8988 /* v_cmpx_neq_f32 */, MCK_Clamp, 8 /* 3 */ },
25400 : { Feature_isGCN|Feature_isVI, 8988 /* v_cmpx_neq_f32 */, MCK_OMod, 16 /* 4 */ },
25401 : { Feature_isGCN|Feature_isSICI, 9003 /* v_cmpx_neq_f64 */, MCK_Clamp, 8 /* 3 */ },
25402 : { Feature_isGCN|Feature_isSICI, 9003 /* v_cmpx_neq_f64 */, MCK_OMod, 16 /* 4 */ },
25403 : { Feature_isGCN|Feature_isVI, 9003 /* v_cmpx_neq_f64 */, MCK_Clamp, 8 /* 3 */ },
25404 : { Feature_isGCN|Feature_isVI, 9003 /* v_cmpx_neq_f64 */, MCK_OMod, 16 /* 4 */ },
25405 : { Feature_isGCN|Feature_isSICI, 9018 /* v_cmpx_nge_f32 */, MCK_Clamp, 8 /* 3 */ },
25406 : { Feature_isGCN|Feature_isSICI, 9018 /* v_cmpx_nge_f32 */, MCK_OMod, 16 /* 4 */ },
25407 : { Feature_isGCN|Feature_isVI, 9018 /* v_cmpx_nge_f32 */, MCK_Clamp, 8 /* 3 */ },
25408 : { Feature_isGCN|Feature_isVI, 9018 /* v_cmpx_nge_f32 */, MCK_OMod, 16 /* 4 */ },
25409 : { Feature_isGCN|Feature_isSICI, 9033 /* v_cmpx_nge_f64 */, MCK_Clamp, 8 /* 3 */ },
25410 : { Feature_isGCN|Feature_isSICI, 9033 /* v_cmpx_nge_f64 */, MCK_OMod, 16 /* 4 */ },
25411 : { Feature_isGCN|Feature_isVI, 9033 /* v_cmpx_nge_f64 */, MCK_Clamp, 8 /* 3 */ },
25412 : { Feature_isGCN|Feature_isVI, 9033 /* v_cmpx_nge_f64 */, MCK_OMod, 16 /* 4 */ },
25413 : { Feature_isGCN|Feature_isSICI, 9048 /* v_cmpx_ngt_f32 */, MCK_Clamp, 8 /* 3 */ },
25414 : { Feature_isGCN|Feature_isSICI, 9048 /* v_cmpx_ngt_f32 */, MCK_OMod, 16 /* 4 */ },
25415 : { Feature_isGCN|Feature_isVI, 9048 /* v_cmpx_ngt_f32 */, MCK_Clamp, 8 /* 3 */ },
25416 : { Feature_isGCN|Feature_isVI, 9048 /* v_cmpx_ngt_f32 */, MCK_OMod, 16 /* 4 */ },
25417 : { Feature_isGCN|Feature_isSICI, 9063 /* v_cmpx_ngt_f64 */, MCK_Clamp, 8 /* 3 */ },
25418 : { Feature_isGCN|Feature_isSICI, 9063 /* v_cmpx_ngt_f64 */, MCK_OMod, 16 /* 4 */ },
25419 : { Feature_isGCN|Feature_isVI, 9063 /* v_cmpx_ngt_f64 */, MCK_Clamp, 8 /* 3 */ },
25420 : { Feature_isGCN|Feature_isVI, 9063 /* v_cmpx_ngt_f64 */, MCK_OMod, 16 /* 4 */ },
25421 : { Feature_isGCN|Feature_isSICI, 9078 /* v_cmpx_nle_f32 */, MCK_Clamp, 8 /* 3 */ },
25422 : { Feature_isGCN|Feature_isSICI, 9078 /* v_cmpx_nle_f32 */, MCK_OMod, 16 /* 4 */ },
25423 : { Feature_isGCN|Feature_isVI, 9078 /* v_cmpx_nle_f32 */, MCK_Clamp, 8 /* 3 */ },
25424 : { Feature_isGCN|Feature_isVI, 9078 /* v_cmpx_nle_f32 */, MCK_OMod, 16 /* 4 */ },
25425 : { Feature_isGCN|Feature_isSICI, 9093 /* v_cmpx_nle_f64 */, MCK_Clamp, 8 /* 3 */ },
25426 : { Feature_isGCN|Feature_isSICI, 9093 /* v_cmpx_nle_f64 */, MCK_OMod, 16 /* 4 */ },
25427 : { Feature_isGCN|Feature_isVI, 9093 /* v_cmpx_nle_f64 */, MCK_Clamp, 8 /* 3 */ },
25428 : { Feature_isGCN|Feature_isVI, 9093 /* v_cmpx_nle_f64 */, MCK_OMod, 16 /* 4 */ },
25429 : { Feature_isGCN|Feature_isSICI, 9108 /* v_cmpx_nlg_f32 */, MCK_Clamp, 8 /* 3 */ },
25430 : { Feature_isGCN|Feature_isSICI, 9108 /* v_cmpx_nlg_f32 */, MCK_OMod, 16 /* 4 */ },
25431 : { Feature_isGCN|Feature_isVI, 9108 /* v_cmpx_nlg_f32 */, MCK_Clamp, 8 /* 3 */ },
25432 : { Feature_isGCN|Feature_isVI, 9108 /* v_cmpx_nlg_f32 */, MCK_OMod, 16 /* 4 */ },
25433 : { Feature_isGCN|Feature_isSICI, 9123 /* v_cmpx_nlg_f64 */, MCK_Clamp, 8 /* 3 */ },
25434 : { Feature_isGCN|Feature_isSICI, 9123 /* v_cmpx_nlg_f64 */, MCK_OMod, 16 /* 4 */ },
25435 : { Feature_isGCN|Feature_isVI, 9123 /* v_cmpx_nlg_f64 */, MCK_Clamp, 8 /* 3 */ },
25436 : { Feature_isGCN|Feature_isVI, 9123 /* v_cmpx_nlg_f64 */, MCK_OMod, 16 /* 4 */ },
25437 : { Feature_isGCN|Feature_isSICI, 9138 /* v_cmpx_nlt_f32 */, MCK_Clamp, 8 /* 3 */ },
25438 : { Feature_isGCN|Feature_isSICI, 9138 /* v_cmpx_nlt_f32 */, MCK_OMod, 16 /* 4 */ },
25439 : { Feature_isGCN|Feature_isVI, 9138 /* v_cmpx_nlt_f32 */, MCK_Clamp, 8 /* 3 */ },
25440 : { Feature_isGCN|Feature_isVI, 9138 /* v_cmpx_nlt_f32 */, MCK_OMod, 16 /* 4 */ },
25441 : { Feature_isGCN|Feature_isSICI, 9153 /* v_cmpx_nlt_f64 */, MCK_Clamp, 8 /* 3 */ },
25442 : { Feature_isGCN|Feature_isSICI, 9153 /* v_cmpx_nlt_f64 */, MCK_OMod, 16 /* 4 */ },
25443 : { Feature_isGCN|Feature_isVI, 9153 /* v_cmpx_nlt_f64 */, MCK_Clamp, 8 /* 3 */ },
25444 : { Feature_isGCN|Feature_isVI, 9153 /* v_cmpx_nlt_f64 */, MCK_OMod, 16 /* 4 */ },
25445 : { Feature_isGCN|Feature_isSICI, 9168 /* v_cmpx_o_f32 */, MCK_Clamp, 8 /* 3 */ },
25446 : { Feature_isGCN|Feature_isSICI, 9168 /* v_cmpx_o_f32 */, MCK_OMod, 16 /* 4 */ },
25447 : { Feature_isGCN|Feature_isVI, 9168 /* v_cmpx_o_f32 */, MCK_Clamp, 8 /* 3 */ },
25448 : { Feature_isGCN|Feature_isVI, 9168 /* v_cmpx_o_f32 */, MCK_OMod, 16 /* 4 */ },
25449 : { Feature_isGCN|Feature_isSICI, 9181 /* v_cmpx_o_f64 */, MCK_Clamp, 8 /* 3 */ },
25450 : { Feature_isGCN|Feature_isSICI, 9181 /* v_cmpx_o_f64 */, MCK_OMod, 16 /* 4 */ },
25451 : { Feature_isGCN|Feature_isVI, 9181 /* v_cmpx_o_f64 */, MCK_Clamp, 8 /* 3 */ },
25452 : { Feature_isGCN|Feature_isVI, 9181 /* v_cmpx_o_f64 */, MCK_OMod, 16 /* 4 */ },
25453 : { Feature_isGCN|Feature_isSICI, 9246 /* v_cmpx_tru_f32 */, MCK_Clamp, 8 /* 3 */ },
25454 : { Feature_isGCN|Feature_isSICI, 9246 /* v_cmpx_tru_f32 */, MCK_OMod, 16 /* 4 */ },
25455 : { Feature_isGCN|Feature_isVI, 9246 /* v_cmpx_tru_f32 */, MCK_Clamp, 8 /* 3 */ },
25456 : { Feature_isGCN|Feature_isVI, 9246 /* v_cmpx_tru_f32 */, MCK_OMod, 16 /* 4 */ },
25457 : { Feature_isGCN|Feature_isSICI, 9261 /* v_cmpx_tru_f64 */, MCK_Clamp, 8 /* 3 */ },
25458 : { Feature_isGCN|Feature_isSICI, 9261 /* v_cmpx_tru_f64 */, MCK_OMod, 16 /* 4 */ },
25459 : { Feature_isGCN|Feature_isVI, 9261 /* v_cmpx_tru_f64 */, MCK_Clamp, 8 /* 3 */ },
25460 : { Feature_isGCN|Feature_isVI, 9261 /* v_cmpx_tru_f64 */, MCK_OMod, 16 /* 4 */ },
25461 : { Feature_isGCN|Feature_isSICI, 9276 /* v_cmpx_u_f32 */, MCK_Clamp, 8 /* 3 */ },
25462 : { Feature_isGCN|Feature_isSICI, 9276 /* v_cmpx_u_f32 */, MCK_OMod, 16 /* 4 */ },
25463 : { Feature_isGCN|Feature_isVI, 9276 /* v_cmpx_u_f32 */, MCK_Clamp, 8 /* 3 */ },
25464 : { Feature_isGCN|Feature_isVI, 9276 /* v_cmpx_u_f32 */, MCK_OMod, 16 /* 4 */ },
25465 : { Feature_isGCN|Feature_isSICI, 9289 /* v_cmpx_u_f64 */, MCK_Clamp, 8 /* 3 */ },
25466 : { Feature_isGCN|Feature_isSICI, 9289 /* v_cmpx_u_f64 */, MCK_OMod, 16 /* 4 */ },
25467 : { Feature_isGCN|Feature_isVI, 9289 /* v_cmpx_u_f64 */, MCK_Clamp, 8 /* 3 */ },
25468 : { Feature_isGCN|Feature_isVI, 9289 /* v_cmpx_u_f64 */, MCK_OMod, 16 /* 4 */ },
25469 : { Feature_isVI|Feature_isSICI, 9316 /* v_cos_f16 */, MCK_Clamp, 4 /* 2 */ },
25470 : { Feature_isVI|Feature_isSICI, 9316 /* v_cos_f16 */, MCK_OMod, 8 /* 3 */ },
25471 : { Feature_isVI|Feature_isVI, 9316 /* v_cos_f16 */, MCK_Clamp, 4 /* 2 */ },
25472 : { Feature_isVI|Feature_isVI, 9316 /* v_cos_f16 */, MCK_OMod, 8 /* 3 */ },
25473 : { Feature_isGCN|Feature_isSICI, 9326 /* v_cos_f32 */, MCK_Clamp, 4 /* 2 */ },
25474 : { Feature_isGCN|Feature_isSICI, 9326 /* v_cos_f32 */, MCK_OMod, 8 /* 3 */ },
25475 : { Feature_isGCN|Feature_isVI, 9326 /* v_cos_f32 */, MCK_Clamp, 4 /* 2 */ },
25476 : { Feature_isGCN|Feature_isVI, 9326 /* v_cos_f32 */, MCK_OMod, 8 /* 3 */ },
25477 : { Feature_isGCN|Feature_isSICI, 9336 /* v_cubeid_f32 */, MCK_Clamp, 16 /* 4 */ },
25478 : { Feature_isGCN|Feature_isSICI, 9336 /* v_cubeid_f32 */, MCK_OMod, 32 /* 5 */ },
25479 : { Feature_isGCN|Feature_isVI, 9336 /* v_cubeid_f32 */, MCK_Clamp, 16 /* 4 */ },
25480 : { Feature_isGCN|Feature_isVI, 9336 /* v_cubeid_f32 */, MCK_OMod, 32 /* 5 */ },
25481 : { Feature_isGCN|Feature_isSICI, 9349 /* v_cubema_f32 */, MCK_Clamp, 16 /* 4 */ },
25482 : { Feature_isGCN|Feature_isSICI, 9349 /* v_cubema_f32 */, MCK_OMod, 32 /* 5 */ },
25483 : { Feature_isGCN|Feature_isVI, 9349 /* v_cubema_f32 */, MCK_Clamp, 16 /* 4 */ },
25484 : { Feature_isGCN|Feature_isVI, 9349 /* v_cubema_f32 */, MCK_OMod, 32 /* 5 */ },
25485 : { Feature_isGCN|Feature_isSICI, 9362 /* v_cubesc_f32 */, MCK_Clamp, 16 /* 4 */ },
25486 : { Feature_isGCN|Feature_isSICI, 9362 /* v_cubesc_f32 */, MCK_OMod, 32 /* 5 */ },
25487 : { Feature_isGCN|Feature_isVI, 9362 /* v_cubesc_f32 */, MCK_Clamp, 16 /* 4 */ },
25488 : { Feature_isGCN|Feature_isVI, 9362 /* v_cubesc_f32 */, MCK_OMod, 32 /* 5 */ },
25489 : { Feature_isGCN|Feature_isSICI, 9375 /* v_cubetc_f32 */, MCK_Clamp, 16 /* 4 */ },
25490 : { Feature_isGCN|Feature_isSICI, 9375 /* v_cubetc_f32 */, MCK_OMod, 32 /* 5 */ },
25491 : { Feature_isGCN|Feature_isVI, 9375 /* v_cubetc_f32 */, MCK_Clamp, 16 /* 4 */ },
25492 : { Feature_isGCN|Feature_isVI, 9375 /* v_cubetc_f32 */, MCK_OMod, 32 /* 5 */ },
25493 : { Feature_isGCN|Feature_isSICI, 9388 /* v_cvt_f16_f32 */, MCK_Clamp, 4 /* 2 */ },
25494 : { Feature_isGCN|Feature_isSICI, 9388 /* v_cvt_f16_f32 */, MCK_OMod, 8 /* 3 */ },
25495 : { Feature_isGCN|Feature_isVI, 9388 /* v_cvt_f16_f32 */, MCK_Clamp, 4 /* 2 */ },
25496 : { Feature_isGCN|Feature_isVI, 9388 /* v_cvt_f16_f32 */, MCK_OMod, 8 /* 3 */ },
25497 : { Feature_isGCN|Feature_isSICI, 9444 /* v_cvt_f32_f64 */, MCK_Clamp, 4 /* 2 */ },
25498 : { Feature_isGCN|Feature_isSICI, 9444 /* v_cvt_f32_f64 */, MCK_OMod, 8 /* 3 */ },
25499 : { Feature_isGCN|Feature_isVI, 9444 /* v_cvt_f32_f64 */, MCK_Clamp, 4 /* 2 */ },
25500 : { Feature_isGCN|Feature_isVI, 9444 /* v_cvt_f32_f64 */, MCK_OMod, 8 /* 3 */ },
25501 : { Feature_isGCN|Feature_isSICI, 9554 /* v_cvt_f64_f32 */, MCK_Clamp, 4 /* 2 */ },
25502 : { Feature_isGCN|Feature_isSICI, 9554 /* v_cvt_f64_f32 */, MCK_OMod, 8 /* 3 */ },
25503 : { Feature_isGCN|Feature_isVI, 9554 /* v_cvt_f64_f32 */, MCK_Clamp, 4 /* 2 */ },
25504 : { Feature_isGCN|Feature_isVI, 9554 /* v_cvt_f64_f32 */, MCK_OMod, 8 /* 3 */ },
25505 : { Feature_isGCN|Feature_isSICI, 9596 /* v_cvt_flr_i32_f32 */, MCK_Clamp, 4 /* 2 */ },
25506 : { Feature_isGCN|Feature_isSICI, 9596 /* v_cvt_flr_i32_f32 */, MCK_OMod, 8 /* 3 */ },
25507 : { Feature_isGCN|Feature_isVI, 9596 /* v_cvt_flr_i32_f32 */, MCK_Clamp, 4 /* 2 */ },
25508 : { Feature_isGCN|Feature_isVI, 9596 /* v_cvt_flr_i32_f32 */, MCK_OMod, 8 /* 3 */ },
25509 : { Feature_isVI|Feature_isSICI, 9614 /* v_cvt_i16_f16 */, MCK_Clamp, 4 /* 2 */ },
25510 : { Feature_isVI|Feature_isSICI, 9614 /* v_cvt_i16_f16 */, MCK_OMod, 8 /* 3 */ },
25511 : { Feature_isVI|Feature_isVI, 9614 /* v_cvt_i16_f16 */, MCK_Clamp, 4 /* 2 */ },
25512 : { Feature_isVI|Feature_isVI, 9614 /* v_cvt_i16_f16 */, MCK_OMod, 8 /* 3 */ },
25513 : { Feature_isGCN|Feature_isSICI, 9628 /* v_cvt_i32_f32 */, MCK_Clamp, 4 /* 2 */ },
25514 : { Feature_isGCN|Feature_isSICI, 9628 /* v_cvt_i32_f32 */, MCK_OMod, 8 /* 3 */ },
25515 : { Feature_isGCN|Feature_isVI, 9628 /* v_cvt_i32_f32 */, MCK_Clamp, 4 /* 2 */ },
25516 : { Feature_isGCN|Feature_isVI, 9628 /* v_cvt_i32_f32 */, MCK_OMod, 8 /* 3 */ },
25517 : { Feature_isGCN|Feature_isSICI, 9642 /* v_cvt_i32_f64 */, MCK_Clamp, 4 /* 2 */ },
25518 : { Feature_isGCN|Feature_isSICI, 9642 /* v_cvt_i32_f64 */, MCK_OMod, 8 /* 3 */ },
25519 : { Feature_isGCN|Feature_isVI, 9642 /* v_cvt_i32_f64 */, MCK_Clamp, 4 /* 2 */ },
25520 : { Feature_isGCN|Feature_isVI, 9642 /* v_cvt_i32_f64 */, MCK_OMod, 8 /* 3 */ },
25521 : { Feature_isGCN|Feature_isSICI, 9707 /* v_cvt_pkaccum_u8_f32 */, MCK_Clamp, 8 /* 3 */ },
25522 : { Feature_isGCN|Feature_isSICI, 9707 /* v_cvt_pkaccum_u8_f32 */, MCK_OMod, 16 /* 4 */ },
25523 : { Feature_isGCN|Feature_isVI, 9707 /* v_cvt_pkaccum_u8_f32 */, MCK_Clamp, 8 /* 3 */ },
25524 : { Feature_isGCN|Feature_isVI, 9707 /* v_cvt_pkaccum_u8_f32 */, MCK_OMod, 16 /* 4 */ },
25525 : { Feature_isGCN|Feature_isSICI, 9728 /* v_cvt_pknorm_i16_f32 */, MCK_Clamp, 8 /* 3 */ },
25526 : { Feature_isGCN|Feature_isSICI, 9728 /* v_cvt_pknorm_i16_f32 */, MCK_OMod, 16 /* 4 */ },
25527 : { Feature_isGCN|Feature_isVI, 9728 /* v_cvt_pknorm_i16_f32 */, MCK_Clamp, 8 /* 3 */ },
25528 : { Feature_isGCN|Feature_isVI, 9728 /* v_cvt_pknorm_i16_f32 */, MCK_OMod, 16 /* 4 */ },
25529 : { Feature_isGCN|Feature_isSICI, 9749 /* v_cvt_pknorm_u16_f32 */, MCK_Clamp, 8 /* 3 */ },
25530 : { Feature_isGCN|Feature_isSICI, 9749 /* v_cvt_pknorm_u16_f32 */, MCK_OMod, 16 /* 4 */ },
25531 : { Feature_isGCN|Feature_isVI, 9749 /* v_cvt_pknorm_u16_f32 */, MCK_Clamp, 8 /* 3 */ },
25532 : { Feature_isGCN|Feature_isVI, 9749 /* v_cvt_pknorm_u16_f32 */, MCK_OMod, 16 /* 4 */ },
25533 : { Feature_isGCN|Feature_isSICI, 9770 /* v_cvt_pkrtz_f16_f32 */, MCK_Clamp, 8 /* 3 */ },
25534 : { Feature_isGCN|Feature_isSICI, 9770 /* v_cvt_pkrtz_f16_f32 */, MCK_OMod, 16 /* 4 */ },
25535 : { Feature_isGCN|Feature_isVI, 9770 /* v_cvt_pkrtz_f16_f32 */, MCK_Clamp, 8 /* 3 */ },
25536 : { Feature_isGCN|Feature_isVI, 9770 /* v_cvt_pkrtz_f16_f32 */, MCK_OMod, 16 /* 4 */ },
25537 : { Feature_isGCN|Feature_isSICI, 9790 /* v_cvt_rpi_i32_f32 */, MCK_Clamp, 4 /* 2 */ },
25538 : { Feature_isGCN|Feature_isSICI, 9790 /* v_cvt_rpi_i32_f32 */, MCK_OMod, 8 /* 3 */ },
25539 : { Feature_isGCN|Feature_isVI, 9790 /* v_cvt_rpi_i32_f32 */, MCK_Clamp, 4 /* 2 */ },
25540 : { Feature_isGCN|Feature_isVI, 9790 /* v_cvt_rpi_i32_f32 */, MCK_OMod, 8 /* 3 */ },
25541 : { Feature_isVI|Feature_isSICI, 9808 /* v_cvt_u16_f16 */, MCK_Clamp, 4 /* 2 */ },
25542 : { Feature_isVI|Feature_isSICI, 9808 /* v_cvt_u16_f16 */, MCK_OMod, 8 /* 3 */ },
25543 : { Feature_isVI|Feature_isVI, 9808 /* v_cvt_u16_f16 */, MCK_Clamp, 4 /* 2 */ },
25544 : { Feature_isVI|Feature_isVI, 9808 /* v_cvt_u16_f16 */, MCK_OMod, 8 /* 3 */ },
25545 : { Feature_isGCN|Feature_isSICI, 9822 /* v_cvt_u32_f32 */, MCK_Clamp, 4 /* 2 */ },
25546 : { Feature_isGCN|Feature_isSICI, 9822 /* v_cvt_u32_f32 */, MCK_OMod, 8 /* 3 */ },
25547 : { Feature_isGCN|Feature_isVI, 9822 /* v_cvt_u32_f32 */, MCK_Clamp, 4 /* 2 */ },
25548 : { Feature_isGCN|Feature_isVI, 9822 /* v_cvt_u32_f32 */, MCK_OMod, 8 /* 3 */ },
25549 : { Feature_isGCN|Feature_isSICI, 9836 /* v_cvt_u32_f64 */, MCK_Clamp, 4 /* 2 */ },
25550 : { Feature_isGCN|Feature_isSICI, 9836 /* v_cvt_u32_f64 */, MCK_OMod, 8 /* 3 */ },
25551 : { Feature_isGCN|Feature_isVI, 9836 /* v_cvt_u32_f64 */, MCK_Clamp, 4 /* 2 */ },
25552 : { Feature_isGCN|Feature_isVI, 9836 /* v_cvt_u32_f64 */, MCK_OMod, 8 /* 3 */ },
25553 : { Feature_isGCN|Feature_isSICI, 9850 /* v_div_fixup_f32 */, MCK_Clamp, 16 /* 4 */ },
25554 : { Feature_isGCN|Feature_isSICI, 9850 /* v_div_fixup_f32 */, MCK_OMod, 32 /* 5 */ },
25555 : { Feature_isGCN|Feature_isVI, 9850 /* v_div_fixup_f32 */, MCK_Clamp, 16 /* 4 */ },
25556 : { Feature_isGCN|Feature_isVI, 9850 /* v_div_fixup_f32 */, MCK_OMod, 32 /* 5 */ },
25557 : { Feature_isGCN|Feature_isSICI, 9866 /* v_div_fixup_f64 */, MCK_Clamp, 16 /* 4 */ },
25558 : { Feature_isGCN|Feature_isSICI, 9866 /* v_div_fixup_f64 */, MCK_OMod, 32 /* 5 */ },
25559 : { Feature_isGCN|Feature_isVI, 9866 /* v_div_fixup_f64 */, MCK_Clamp, 16 /* 4 */ },
25560 : { Feature_isGCN|Feature_isVI, 9866 /* v_div_fixup_f64 */, MCK_OMod, 32 /* 5 */ },
25561 : { Feature_isGCN|Feature_isSICI, 9882 /* v_div_fmas_f32 */, MCK_Clamp, 16 /* 4 */ },
25562 : { Feature_isGCN|Feature_isSICI, 9882 /* v_div_fmas_f32 */, MCK_OMod, 32 /* 5 */ },
25563 : { Feature_isGCN|Feature_isVI, 9882 /* v_div_fmas_f32 */, MCK_Clamp, 16 /* 4 */ },
25564 : { Feature_isGCN|Feature_isVI, 9882 /* v_div_fmas_f32 */, MCK_OMod, 32 /* 5 */ },
25565 : { Feature_isGCN|Feature_isSICI, 9897 /* v_div_fmas_f64 */, MCK_Clamp, 16 /* 4 */ },
25566 : { Feature_isGCN|Feature_isSICI, 9897 /* v_div_fmas_f64 */, MCK_OMod, 32 /* 5 */ },
25567 : { Feature_isGCN|Feature_isVI, 9897 /* v_div_fmas_f64 */, MCK_Clamp, 16 /* 4 */ },
25568 : { Feature_isGCN|Feature_isVI, 9897 /* v_div_fmas_f64 */, MCK_OMod, 32 /* 5 */ },
25569 : { Feature_isGCN|Feature_isSICI, 9912 /* v_div_scale_f32 */, MCK_Clamp, 32 /* 5 */ },
25570 : { Feature_isGCN|Feature_isSICI, 9912 /* v_div_scale_f32 */, MCK_OMod, 64 /* 6 */ },
25571 : { Feature_isGCN|Feature_isVI, 9912 /* v_div_scale_f32 */, MCK_Clamp, 32 /* 5 */ },
25572 : { Feature_isGCN|Feature_isVI, 9912 /* v_div_scale_f32 */, MCK_OMod, 64 /* 6 */ },
25573 : { Feature_isGCN|Feature_isSICI, 9928 /* v_div_scale_f64 */, MCK_Clamp, 32 /* 5 */ },
25574 : { Feature_isGCN|Feature_isSICI, 9928 /* v_div_scale_f64 */, MCK_OMod, 64 /* 6 */ },
25575 : { Feature_isGCN|Feature_isVI, 9928 /* v_div_scale_f64 */, MCK_Clamp, 32 /* 5 */ },
25576 : { Feature_isGCN|Feature_isVI, 9928 /* v_div_scale_f64 */, MCK_OMod, 64 /* 6 */ },
25577 : { Feature_isVI|Feature_isSICI, 9944 /* v_exp_f16 */, MCK_Clamp, 4 /* 2 */ },
25578 : { Feature_isVI|Feature_isSICI, 9944 /* v_exp_f16 */, MCK_OMod, 8 /* 3 */ },
25579 : { Feature_isVI|Feature_isVI, 9944 /* v_exp_f16 */, MCK_Clamp, 4 /* 2 */ },
25580 : { Feature_isVI|Feature_isVI, 9944 /* v_exp_f16 */, MCK_OMod, 8 /* 3 */ },
25581 : { Feature_isGCN|Feature_isSICI, 9954 /* v_exp_f32 */, MCK_Clamp, 4 /* 2 */ },
25582 : { Feature_isGCN|Feature_isSICI, 9954 /* v_exp_f32 */, MCK_OMod, 8 /* 3 */ },
25583 : { Feature_isGCN|Feature_isVI, 9954 /* v_exp_f32 */, MCK_Clamp, 4 /* 2 */ },
25584 : { Feature_isGCN|Feature_isVI, 9954 /* v_exp_f32 */, MCK_OMod, 8 /* 3 */ },
25585 : { Feature_isCIVI|Feature_isSICI, 9964 /* v_exp_legacy_f32 */, MCK_Clamp, 4 /* 2 */ },
25586 : { Feature_isCIVI|Feature_isSICI, 9964 /* v_exp_legacy_f32 */, MCK_OMod, 8 /* 3 */ },
25587 : { Feature_isCIVI|Feature_isVI, 9964 /* v_exp_legacy_f32 */, MCK_Clamp, 4 /* 2 */ },
25588 : { Feature_isCIVI|Feature_isVI, 9964 /* v_exp_legacy_f32 */, MCK_OMod, 8 /* 3 */ },
25589 : { Feature_isVI|Feature_isSICI, 10014 /* v_floor_f16 */, MCK_Clamp, 4 /* 2 */ },
25590 : { Feature_isVI|Feature_isSICI, 10014 /* v_floor_f16 */, MCK_OMod, 8 /* 3 */ },
25591 : { Feature_isVI|Feature_isVI, 10014 /* v_floor_f16 */, MCK_Clamp, 4 /* 2 */ },
25592 : { Feature_isVI|Feature_isVI, 10014 /* v_floor_f16 */, MCK_OMod, 8 /* 3 */ },
25593 : { Feature_isGCN|Feature_isSICI, 10026 /* v_floor_f32 */, MCK_Clamp, 4 /* 2 */ },
25594 : { Feature_isGCN|Feature_isSICI, 10026 /* v_floor_f32 */, MCK_OMod, 8 /* 3 */ },
25595 : { Feature_isGCN|Feature_isVI, 10026 /* v_floor_f32 */, MCK_Clamp, 4 /* 2 */ },
25596 : { Feature_isGCN|Feature_isVI, 10026 /* v_floor_f32 */, MCK_OMod, 8 /* 3 */ },
25597 : { Feature_isCIVI|Feature_isSICI, 10038 /* v_floor_f64 */, MCK_Clamp, 4 /* 2 */ },
25598 : { Feature_isCIVI|Feature_isSICI, 10038 /* v_floor_f64 */, MCK_OMod, 8 /* 3 */ },
25599 : { Feature_isCIVI|Feature_isVI, 10038 /* v_floor_f64 */, MCK_Clamp, 4 /* 2 */ },
25600 : { Feature_isCIVI|Feature_isVI, 10038 /* v_floor_f64 */, MCK_OMod, 8 /* 3 */ },
25601 : { Feature_isGCN|Feature_isSICI, 10050 /* v_fma_f32 */, MCK_Clamp, 16 /* 4 */ },
25602 : { Feature_isGCN|Feature_isSICI, 10050 /* v_fma_f32 */, MCK_OMod, 32 /* 5 */ },
25603 : { Feature_isGCN|Feature_isVI, 10050 /* v_fma_f32 */, MCK_Clamp, 16 /* 4 */ },
25604 : { Feature_isGCN|Feature_isVI, 10050 /* v_fma_f32 */, MCK_OMod, 32 /* 5 */ },
25605 : { Feature_isGCN|Feature_isSICI, 10060 /* v_fma_f64 */, MCK_Clamp, 16 /* 4 */ },
25606 : { Feature_isGCN|Feature_isSICI, 10060 /* v_fma_f64 */, MCK_OMod, 32 /* 5 */ },
25607 : { Feature_isGCN|Feature_isVI, 10060 /* v_fma_f64 */, MCK_Clamp, 16 /* 4 */ },
25608 : { Feature_isGCN|Feature_isVI, 10060 /* v_fma_f64 */, MCK_OMod, 32 /* 5 */ },
25609 : { Feature_isVI|Feature_isSICI, 10070 /* v_fract_f16 */, MCK_Clamp, 4 /* 2 */ },
25610 : { Feature_isVI|Feature_isSICI, 10070 /* v_fract_f16 */, MCK_OMod, 8 /* 3 */ },
25611 : { Feature_isVI|Feature_isVI, 10070 /* v_fract_f16 */, MCK_Clamp, 4 /* 2 */ },
25612 : { Feature_isVI|Feature_isVI, 10070 /* v_fract_f16 */, MCK_OMod, 8 /* 3 */ },
25613 : { Feature_isGCN|Feature_isSICI, 10082 /* v_fract_f32 */, MCK_Clamp, 4 /* 2 */ },
25614 : { Feature_isGCN|Feature_isSICI, 10082 /* v_fract_f32 */, MCK_OMod, 8 /* 3 */ },
25615 : { Feature_isGCN|Feature_isVI, 10082 /* v_fract_f32 */, MCK_Clamp, 4 /* 2 */ },
25616 : { Feature_isGCN|Feature_isVI, 10082 /* v_fract_f32 */, MCK_OMod, 8 /* 3 */ },
25617 : { Feature_isGCN|Feature_isSICI, 10094 /* v_fract_f64 */, MCK_Clamp, 4 /* 2 */ },
25618 : { Feature_isGCN|Feature_isSICI, 10094 /* v_fract_f64 */, MCK_OMod, 8 /* 3 */ },
25619 : { Feature_isGCN|Feature_isVI, 10094 /* v_fract_f64 */, MCK_Clamp, 4 /* 2 */ },
25620 : { Feature_isGCN|Feature_isVI, 10094 /* v_fract_f64 */, MCK_OMod, 8 /* 3 */ },
25621 : { Feature_isVI|Feature_isSICI, 10106 /* v_frexp_exp_i16_f16 */, MCK_Clamp, 4 /* 2 */ },
25622 : { Feature_isVI|Feature_isSICI, 10106 /* v_frexp_exp_i16_f16 */, MCK_OMod, 8 /* 3 */ },
25623 : { Feature_isVI|Feature_isVI, 10106 /* v_frexp_exp_i16_f16 */, MCK_Clamp, 4 /* 2 */ },
25624 : { Feature_isVI|Feature_isVI, 10106 /* v_frexp_exp_i16_f16 */, MCK_OMod, 8 /* 3 */ },
25625 : { Feature_isGCN|Feature_isSICI, 10126 /* v_frexp_exp_i32_f32 */, MCK_Clamp, 4 /* 2 */ },
25626 : { Feature_isGCN|Feature_isSICI, 10126 /* v_frexp_exp_i32_f32 */, MCK_OMod, 8 /* 3 */ },
25627 : { Feature_isGCN|Feature_isVI, 10126 /* v_frexp_exp_i32_f32 */, MCK_Clamp, 4 /* 2 */ },
25628 : { Feature_isGCN|Feature_isVI, 10126 /* v_frexp_exp_i32_f32 */, MCK_OMod, 8 /* 3 */ },
25629 : { Feature_isGCN|Feature_isSICI, 10146 /* v_frexp_exp_i32_f64 */, MCK_Clamp, 4 /* 2 */ },
25630 : { Feature_isGCN|Feature_isSICI, 10146 /* v_frexp_exp_i32_f64 */, MCK_OMod, 8 /* 3 */ },
25631 : { Feature_isGCN|Feature_isVI, 10146 /* v_frexp_exp_i32_f64 */, MCK_Clamp, 4 /* 2 */ },
25632 : { Feature_isGCN|Feature_isVI, 10146 /* v_frexp_exp_i32_f64 */, MCK_OMod, 8 /* 3 */ },
25633 : { Feature_isVI|Feature_isSICI, 10166 /* v_frexp_mant_f16 */, MCK_Clamp, 4 /* 2 */ },
25634 : { Feature_isVI|Feature_isSICI, 10166 /* v_frexp_mant_f16 */, MCK_OMod, 8 /* 3 */ },
25635 : { Feature_isVI|Feature_isVI, 10166 /* v_frexp_mant_f16 */, MCK_Clamp, 4 /* 2 */ },
25636 : { Feature_isVI|Feature_isVI, 10166 /* v_frexp_mant_f16 */, MCK_OMod, 8 /* 3 */ },
25637 : { Feature_isGCN|Feature_isSICI, 10183 /* v_frexp_mant_f32 */, MCK_Clamp, 4 /* 2 */ },
25638 : { Feature_isGCN|Feature_isSICI, 10183 /* v_frexp_mant_f32 */, MCK_OMod, 8 /* 3 */ },
25639 : { Feature_isGCN|Feature_isVI, 10183 /* v_frexp_mant_f32 */, MCK_Clamp, 4 /* 2 */ },
25640 : { Feature_isGCN|Feature_isVI, 10183 /* v_frexp_mant_f32 */, MCK_OMod, 8 /* 3 */ },
25641 : { Feature_isGCN|Feature_isSICI, 10200 /* v_frexp_mant_f64 */, MCK_Clamp, 4 /* 2 */ },
25642 : { Feature_isGCN|Feature_isSICI, 10200 /* v_frexp_mant_f64 */, MCK_OMod, 8 /* 3 */ },
25643 : { Feature_isGCN|Feature_isVI, 10200 /* v_frexp_mant_f64 */, MCK_Clamp, 4 /* 2 */ },
25644 : { Feature_isGCN|Feature_isVI, 10200 /* v_frexp_mant_f64 */, MCK_OMod, 8 /* 3 */ },
25645 : { Feature_isVI|Feature_isSICI, 10266 /* v_ldexp_f16 */, MCK_Clamp, 8 /* 3 */ },
25646 : { Feature_isVI|Feature_isSICI, 10266 /* v_ldexp_f16 */, MCK_OMod, 16 /* 4 */ },
25647 : { Feature_isVI|Feature_isVI, 10266 /* v_ldexp_f16 */, MCK_Clamp, 8 /* 3 */ },
25648 : { Feature_isVI|Feature_isVI, 10266 /* v_ldexp_f16 */, MCK_OMod, 16 /* 4 */ },
25649 : { Feature_isGCN|Feature_isSICI, 10278 /* v_ldexp_f32 */, MCK_Clamp, 8 /* 3 */ },
25650 : { Feature_isGCN|Feature_isSICI, 10278 /* v_ldexp_f32 */, MCK_OMod, 16 /* 4 */ },
25651 : { Feature_isGCN|Feature_isVI, 10278 /* v_ldexp_f32 */, MCK_Clamp, 8 /* 3 */ },
25652 : { Feature_isGCN|Feature_isVI, 10278 /* v_ldexp_f32 */, MCK_OMod, 16 /* 4 */ },
25653 : { Feature_isGCN|Feature_isSICI, 10290 /* v_ldexp_f64 */, MCK_Clamp, 8 /* 3 */ },
25654 : { Feature_isGCN|Feature_isSICI, 10290 /* v_ldexp_f64 */, MCK_OMod, 16 /* 4 */ },
25655 : { Feature_isGCN|Feature_isVI, 10290 /* v_ldexp_f64 */, MCK_Clamp, 8 /* 3 */ },
25656 : { Feature_isGCN|Feature_isVI, 10290 /* v_ldexp_f64 */, MCK_OMod, 16 /* 4 */ },
25657 : { Feature_isSICI|Feature_isSICI, 10302 /* v_log_clamp_f32 */, MCK_Clamp, 4 /* 2 */ },
25658 : { Feature_isSICI|Feature_isSICI, 10302 /* v_log_clamp_f32 */, MCK_OMod, 8 /* 3 */ },
25659 : { Feature_isVI|Feature_isSICI, 10318 /* v_log_f16 */, MCK_Clamp, 4 /* 2 */ },
25660 : { Feature_isVI|Feature_isSICI, 10318 /* v_log_f16 */, MCK_OMod, 8 /* 3 */ },
25661 : { Feature_isVI|Feature_isVI, 10318 /* v_log_f16 */, MCK_Clamp, 4 /* 2 */ },
25662 : { Feature_isVI|Feature_isVI, 10318 /* v_log_f16 */, MCK_OMod, 8 /* 3 */ },
25663 : { Feature_isGCN|Feature_isSICI, 10328 /* v_log_f32 */, MCK_Clamp, 4 /* 2 */ },
25664 : { Feature_isGCN|Feature_isSICI, 10328 /* v_log_f32 */, MCK_OMod, 8 /* 3 */ },
25665 : { Feature_isGCN|Feature_isVI, 10328 /* v_log_f32 */, MCK_Clamp, 4 /* 2 */ },
25666 : { Feature_isGCN|Feature_isVI, 10328 /* v_log_f32 */, MCK_OMod, 8 /* 3 */ },
25667 : { Feature_isCIVI|Feature_isSICI, 10338 /* v_log_legacy_f32 */, MCK_Clamp, 4 /* 2 */ },
25668 : { Feature_isCIVI|Feature_isSICI, 10338 /* v_log_legacy_f32 */, MCK_OMod, 8 /* 3 */ },
25669 : { Feature_isCIVI|Feature_isVI, 10338 /* v_log_legacy_f32 */, MCK_Clamp, 4 /* 2 */ },
25670 : { Feature_isCIVI|Feature_isVI, 10338 /* v_log_legacy_f32 */, MCK_OMod, 8 /* 3 */ },
25671 : { Feature_isVI|Feature_isSICI, 10483 /* v_mac_f16 */, MCK_Clamp, 8 /* 3 */ },
25672 : { Feature_isVI|Feature_isSICI, 10483 /* v_mac_f16 */, MCK_OMod, 16 /* 4 */ },
25673 : { Feature_isVI|Feature_isVI, 10483 /* v_mac_f16 */, MCK_Clamp, 8 /* 3 */ },
25674 : { Feature_isVI|Feature_isVI, 10483 /* v_mac_f16 */, MCK_OMod, 16 /* 4 */ },
25675 : { Feature_isGCN|Feature_isSICI, 10493 /* v_mac_f32 */, MCK_Clamp, 8 /* 3 */ },
25676 : { Feature_isGCN|Feature_isSICI, 10493 /* v_mac_f32 */, MCK_OMod, 16 /* 4 */ },
25677 : { Feature_isGCN|Feature_isVI, 10493 /* v_mac_f32 */, MCK_Clamp, 8 /* 3 */ },
25678 : { Feature_isGCN|Feature_isVI, 10493 /* v_mac_f32 */, MCK_OMod, 16 /* 4 */ },
25679 : { Feature_isGCN|Feature_isSICI, 10503 /* v_mac_legacy_f32 */, MCK_Clamp, 8 /* 3 */ },
25680 : { Feature_isGCN|Feature_isSICI, 10503 /* v_mac_legacy_f32 */, MCK_OMod, 16 /* 4 */ },
25681 : { Feature_isGCN|Feature_isVI, 10503 /* v_mac_legacy_f32 */, MCK_Clamp, 8 /* 3 */ },
25682 : { Feature_isGCN|Feature_isVI, 10503 /* v_mac_legacy_f32 */, MCK_OMod, 16 /* 4 */ },
25683 : { Feature_isGCN|Feature_isSICI, 10520 /* v_mad_f32 */, MCK_Clamp, 16 /* 4 */ },
25684 : { Feature_isGCN|Feature_isSICI, 10520 /* v_mad_f32 */, MCK_OMod, 32 /* 5 */ },
25685 : { Feature_isGCN|Feature_isVI, 10520 /* v_mad_f32 */, MCK_Clamp, 16 /* 4 */ },
25686 : { Feature_isGCN|Feature_isVI, 10520 /* v_mad_f32 */, MCK_OMod, 32 /* 5 */ },
25687 : { Feature_isGCN|Feature_isSICI, 10558 /* v_mad_legacy_f32 */, MCK_Clamp, 16 /* 4 */ },
25688 : { Feature_isGCN|Feature_isSICI, 10558 /* v_mad_legacy_f32 */, MCK_OMod, 32 /* 5 */ },
25689 : { Feature_isGCN|Feature_isVI, 10558 /* v_mad_legacy_f32 */, MCK_Clamp, 16 /* 4 */ },
25690 : { Feature_isGCN|Feature_isVI, 10558 /* v_mad_legacy_f32 */, MCK_OMod, 32 /* 5 */ },
25691 : { Feature_isGCN|Feature_isSICI, 10651 /* v_max3_f32 */, MCK_Clamp, 16 /* 4 */ },
25692 : { Feature_isGCN|Feature_isSICI, 10651 /* v_max3_f32 */, MCK_OMod, 32 /* 5 */ },
25693 : { Feature_isGCN|Feature_isVI, 10651 /* v_max3_f32 */, MCK_Clamp, 16 /* 4 */ },
25694 : { Feature_isGCN|Feature_isVI, 10651 /* v_max3_f32 */, MCK_OMod, 32 /* 5 */ },
25695 : { Feature_isVI|Feature_isSICI, 10684 /* v_max_f16 */, MCK_Clamp, 8 /* 3 */ },
25696 : { Feature_isVI|Feature_isSICI, 10684 /* v_max_f16 */, MCK_OMod, 16 /* 4 */ },
25697 : { Feature_isVI|Feature_isVI, 10684 /* v_max_f16 */, MCK_Clamp, 8 /* 3 */ },
25698 : { Feature_isVI|Feature_isVI, 10684 /* v_max_f16 */, MCK_OMod, 16 /* 4 */ },
25699 : { Feature_isGCN|Feature_isSICI, 10694 /* v_max_f32 */, MCK_Clamp, 8 /* 3 */ },
25700 : { Feature_isGCN|Feature_isSICI, 10694 /* v_max_f32 */, MCK_OMod, 16 /* 4 */ },
25701 : { Feature_isGCN|Feature_isVI, 10694 /* v_max_f32 */, MCK_Clamp, 8 /* 3 */ },
25702 : { Feature_isGCN|Feature_isVI, 10694 /* v_max_f32 */, MCK_OMod, 16 /* 4 */ },
25703 : { Feature_isGCN|Feature_isSICI, 10704 /* v_max_f64 */, MCK_Clamp, 8 /* 3 */ },
25704 : { Feature_isGCN|Feature_isSICI, 10704 /* v_max_f64 */, MCK_OMod, 16 /* 4 */ },
25705 : { Feature_isGCN|Feature_isVI, 10704 /* v_max_f64 */, MCK_Clamp, 8 /* 3 */ },
25706 : { Feature_isGCN|Feature_isVI, 10704 /* v_max_f64 */, MCK_OMod, 16 /* 4 */ },
25707 : { Feature_isSICI|Feature_isSICI, 10734 /* v_max_legacy_f32 */, MCK_Clamp, 8 /* 3 */ },
25708 : { Feature_isSICI|Feature_isSICI, 10734 /* v_max_legacy_f32 */, MCK_OMod, 16 /* 4 */ },
25709 : { Feature_isGCN|Feature_isSICI, 10809 /* v_med3_f32 */, MCK_Clamp, 16 /* 4 */ },
25710 : { Feature_isGCN|Feature_isSICI, 10809 /* v_med3_f32 */, MCK_OMod, 32 /* 5 */ },
25711 : { Feature_isGCN|Feature_isVI, 10809 /* v_med3_f32 */, MCK_Clamp, 16 /* 4 */ },
25712 : { Feature_isGCN|Feature_isVI, 10809 /* v_med3_f32 */, MCK_OMod, 32 /* 5 */ },
25713 : { Feature_isGCN|Feature_isSICI, 10842 /* v_min3_f32 */, MCK_Clamp, 16 /* 4 */ },
25714 : { Feature_isGCN|Feature_isSICI, 10842 /* v_min3_f32 */, MCK_OMod, 32 /* 5 */ },
25715 : { Feature_isGCN|Feature_isVI, 10842 /* v_min3_f32 */, MCK_Clamp, 16 /* 4 */ },
25716 : { Feature_isGCN|Feature_isVI, 10842 /* v_min3_f32 */, MCK_OMod, 32 /* 5 */ },
25717 : { Feature_isVI|Feature_isSICI, 10875 /* v_min_f16 */, MCK_Clamp, 8 /* 3 */ },
25718 : { Feature_isVI|Feature_isSICI, 10875 /* v_min_f16 */, MCK_OMod, 16 /* 4 */ },
25719 : { Feature_isVI|Feature_isVI, 10875 /* v_min_f16 */, MCK_Clamp, 8 /* 3 */ },
25720 : { Feature_isVI|Feature_isVI, 10875 /* v_min_f16 */, MCK_OMod, 16 /* 4 */ },
25721 : { Feature_isGCN|Feature_isSICI, 10885 /* v_min_f32 */, MCK_Clamp, 8 /* 3 */ },
25722 : { Feature_isGCN|Feature_isSICI, 10885 /* v_min_f32 */, MCK_OMod, 16 /* 4 */ },
25723 : { Feature_isGCN|Feature_isVI, 10885 /* v_min_f32 */, MCK_Clamp, 8 /* 3 */ },
25724 : { Feature_isGCN|Feature_isVI, 10885 /* v_min_f32 */, MCK_OMod, 16 /* 4 */ },
25725 : { Feature_isGCN|Feature_isSICI, 10895 /* v_min_f64 */, MCK_Clamp, 8 /* 3 */ },
25726 : { Feature_isGCN|Feature_isSICI, 10895 /* v_min_f64 */, MCK_OMod, 16 /* 4 */ },
25727 : { Feature_isGCN|Feature_isVI, 10895 /* v_min_f64 */, MCK_Clamp, 8 /* 3 */ },
25728 : { Feature_isGCN|Feature_isVI, 10895 /* v_min_f64 */, MCK_OMod, 16 /* 4 */ },
25729 : { Feature_isSICI|Feature_isSICI, 10925 /* v_min_legacy_f32 */, MCK_Clamp, 8 /* 3 */ },
25730 : { Feature_isSICI|Feature_isSICI, 10925 /* v_min_legacy_f32 */, MCK_OMod, 16 /* 4 */ },
25731 : { Feature_isVI|Feature_isSICI, 11059 /* v_mul_f16 */, MCK_Clamp, 8 /* 3 */ },
25732 : { Feature_isVI|Feature_isSICI, 11059 /* v_mul_f16 */, MCK_OMod, 16 /* 4 */ },
25733 : { Feature_isVI|Feature_isVI, 11059 /* v_mul_f16 */, MCK_Clamp, 8 /* 3 */ },
25734 : { Feature_isVI|Feature_isVI, 11059 /* v_mul_f16 */, MCK_OMod, 16 /* 4 */ },
25735 : { Feature_isGCN|Feature_isSICI, 11069 /* v_mul_f32 */, MCK_Clamp, 8 /* 3 */ },
25736 : { Feature_isGCN|Feature_isSICI, 11069 /* v_mul_f32 */, MCK_OMod, 16 /* 4 */ },
25737 : { Feature_isGCN|Feature_isVI, 11069 /* v_mul_f32 */, MCK_Clamp, 8 /* 3 */ },
25738 : { Feature_isGCN|Feature_isVI, 11069 /* v_mul_f32 */, MCK_OMod, 16 /* 4 */ },
25739 : { Feature_isGCN|Feature_isSICI, 11079 /* v_mul_f64 */, MCK_Clamp, 8 /* 3 */ },
25740 : { Feature_isGCN|Feature_isSICI, 11079 /* v_mul_f64 */, MCK_OMod, 16 /* 4 */ },
25741 : { Feature_isGCN|Feature_isVI, 11079 /* v_mul_f64 */, MCK_Clamp, 8 /* 3 */ },
25742 : { Feature_isGCN|Feature_isVI, 11079 /* v_mul_f64 */, MCK_OMod, 16 /* 4 */ },
25743 : { Feature_isGCN|Feature_isSICI, 11163 /* v_mul_legacy_f32 */, MCK_Clamp, 8 /* 3 */ },
25744 : { Feature_isGCN|Feature_isSICI, 11163 /* v_mul_legacy_f32 */, MCK_OMod, 16 /* 4 */ },
25745 : { Feature_isGCN|Feature_isVI, 11163 /* v_mul_legacy_f32 */, MCK_Clamp, 8 /* 3 */ },
25746 : { Feature_isGCN|Feature_isVI, 11163 /* v_mul_legacy_f32 */, MCK_OMod, 16 /* 4 */ },
25747 : { Feature_isSICI|Feature_isSICI, 11233 /* v_mullit_f32 */, MCK_Clamp, 16 /* 4 */ },
25748 : { Feature_isSICI|Feature_isSICI, 11233 /* v_mullit_f32 */, MCK_OMod, 32 /* 5 */ },
25749 : { Feature_isSICI|Feature_isVI, 11233 /* v_mullit_f32 */, MCK_Clamp, 16 /* 4 */ },
25750 : { Feature_isSICI|Feature_isVI, 11233 /* v_mullit_f32 */, MCK_OMod, 32 /* 5 */ },
25751 : { Feature_isSICI|Feature_isSICI, 11288 /* v_rcp_clamp_f32 */, MCK_Clamp, 4 /* 2 */ },
25752 : { Feature_isSICI|Feature_isSICI, 11288 /* v_rcp_clamp_f32 */, MCK_OMod, 8 /* 3 */ },
25753 : { Feature_isSICI|Feature_isSICI, 11304 /* v_rcp_clamp_f64 */, MCK_Clamp, 4 /* 2 */ },
25754 : { Feature_isSICI|Feature_isSICI, 11304 /* v_rcp_clamp_f64 */, MCK_OMod, 8 /* 3 */ },
25755 : { Feature_isVI|Feature_isSICI, 11320 /* v_rcp_f16 */, MCK_Clamp, 4 /* 2 */ },
25756 : { Feature_isVI|Feature_isSICI, 11320 /* v_rcp_f16 */, MCK_OMod, 8 /* 3 */ },
25757 : { Feature_isVI|Feature_isVI, 11320 /* v_rcp_f16 */, MCK_Clamp, 4 /* 2 */ },
25758 : { Feature_isVI|Feature_isVI, 11320 /* v_rcp_f16 */, MCK_OMod, 8 /* 3 */ },
25759 : { Feature_isGCN|Feature_isSICI, 11330 /* v_rcp_f32 */, MCK_Clamp, 4 /* 2 */ },
25760 : { Feature_isGCN|Feature_isSICI, 11330 /* v_rcp_f32 */, MCK_OMod, 8 /* 3 */ },
25761 : { Feature_isGCN|Feature_isVI, 11330 /* v_rcp_f32 */, MCK_Clamp, 4 /* 2 */ },
25762 : { Feature_isGCN|Feature_isVI, 11330 /* v_rcp_f32 */, MCK_OMod, 8 /* 3 */ },
25763 : { Feature_isGCN|Feature_isSICI, 11340 /* v_rcp_f64 */, MCK_Clamp, 4 /* 2 */ },
25764 : { Feature_isGCN|Feature_isSICI, 11340 /* v_rcp_f64 */, MCK_OMod, 8 /* 3 */ },
25765 : { Feature_isGCN|Feature_isVI, 11340 /* v_rcp_f64 */, MCK_Clamp, 4 /* 2 */ },
25766 : { Feature_isGCN|Feature_isVI, 11340 /* v_rcp_f64 */, MCK_OMod, 8 /* 3 */ },
25767 : { Feature_isGCN|Feature_isSICI, 11350 /* v_rcp_iflag_f32 */, MCK_Clamp, 4 /* 2 */ },
25768 : { Feature_isGCN|Feature_isSICI, 11350 /* v_rcp_iflag_f32 */, MCK_OMod, 8 /* 3 */ },
25769 : { Feature_isGCN|Feature_isVI, 11350 /* v_rcp_iflag_f32 */, MCK_Clamp, 4 /* 2 */ },
25770 : { Feature_isGCN|Feature_isVI, 11350 /* v_rcp_iflag_f32 */, MCK_OMod, 8 /* 3 */ },
25771 : { Feature_isSICI|Feature_isSICI, 11366 /* v_rcp_legacy_f32 */, MCK_Clamp, 4 /* 2 */ },
25772 : { Feature_isSICI|Feature_isSICI, 11366 /* v_rcp_legacy_f32 */, MCK_OMod, 8 /* 3 */ },
25773 : { Feature_isVI|Feature_isSICI, 11418 /* v_rndne_f16 */, MCK_Clamp, 4 /* 2 */ },
25774 : { Feature_isVI|Feature_isSICI, 11418 /* v_rndne_f16 */, MCK_OMod, 8 /* 3 */ },
25775 : { Feature_isVI|Feature_isVI, 11418 /* v_rndne_f16 */, MCK_Clamp, 4 /* 2 */ },
25776 : { Feature_isVI|Feature_isVI, 11418 /* v_rndne_f16 */, MCK_OMod, 8 /* 3 */ },
25777 : { Feature_isGCN|Feature_isSICI, 11430 /* v_rndne_f32 */, MCK_Clamp, 4 /* 2 */ },
25778 : { Feature_isGCN|Feature_isSICI, 11430 /* v_rndne_f32 */, MCK_OMod, 8 /* 3 */ },
25779 : { Feature_isGCN|Feature_isVI, 11430 /* v_rndne_f32 */, MCK_Clamp, 4 /* 2 */ },
25780 : { Feature_isGCN|Feature_isVI, 11430 /* v_rndne_f32 */, MCK_OMod, 8 /* 3 */ },
25781 : { Feature_isCIVI|Feature_isSICI, 11442 /* v_rndne_f64 */, MCK_Clamp, 4 /* 2 */ },
25782 : { Feature_isCIVI|Feature_isSICI, 11442 /* v_rndne_f64 */, MCK_OMod, 8 /* 3 */ },
25783 : { Feature_isCIVI|Feature_isVI, 11442 /* v_rndne_f64 */, MCK_Clamp, 4 /* 2 */ },
25784 : { Feature_isCIVI|Feature_isVI, 11442 /* v_rndne_f64 */, MCK_OMod, 8 /* 3 */ },
25785 : { Feature_isSICI|Feature_isSICI, 11454 /* v_rsq_clamp_f32 */, MCK_Clamp, 4 /* 2 */ },
25786 : { Feature_isSICI|Feature_isSICI, 11454 /* v_rsq_clamp_f32 */, MCK_OMod, 8 /* 3 */ },
25787 : { Feature_isSICI|Feature_isSICI, 11470 /* v_rsq_clamp_f64 */, MCK_Clamp, 4 /* 2 */ },
25788 : { Feature_isSICI|Feature_isSICI, 11470 /* v_rsq_clamp_f64 */, MCK_OMod, 8 /* 3 */ },
25789 : { Feature_isVI|Feature_isSICI, 11486 /* v_rsq_f16 */, MCK_Clamp, 4 /* 2 */ },
25790 : { Feature_isVI|Feature_isSICI, 11486 /* v_rsq_f16 */, MCK_OMod, 8 /* 3 */ },
25791 : { Feature_isVI|Feature_isVI, 11486 /* v_rsq_f16 */, MCK_Clamp, 4 /* 2 */ },
25792 : { Feature_isVI|Feature_isVI, 11486 /* v_rsq_f16 */, MCK_OMod, 8 /* 3 */ },
25793 : { Feature_isGCN|Feature_isSICI, 11496 /* v_rsq_f32 */, MCK_Clamp, 4 /* 2 */ },
25794 : { Feature_isGCN|Feature_isSICI, 11496 /* v_rsq_f32 */, MCK_OMod, 8 /* 3 */ },
25795 : { Feature_isGCN|Feature_isVI, 11496 /* v_rsq_f32 */, MCK_Clamp, 4 /* 2 */ },
25796 : { Feature_isGCN|Feature_isVI, 11496 /* v_rsq_f32 */, MCK_OMod, 8 /* 3 */ },
25797 : { Feature_isGCN|Feature_isSICI, 11506 /* v_rsq_f64 */, MCK_Clamp, 4 /* 2 */ },
25798 : { Feature_isGCN|Feature_isSICI, 11506 /* v_rsq_f64 */, MCK_OMod, 8 /* 3 */ },
25799 : { Feature_isGCN|Feature_isVI, 11506 /* v_rsq_f64 */, MCK_Clamp, 4 /* 2 */ },
25800 : { Feature_isGCN|Feature_isVI, 11506 /* v_rsq_f64 */, MCK_OMod, 8 /* 3 */ },
25801 : { Feature_isSICI|Feature_isSICI, 11516 /* v_rsq_legacy_f32 */, MCK_Clamp, 4 /* 2 */ },
25802 : { Feature_isSICI|Feature_isSICI, 11516 /* v_rsq_legacy_f32 */, MCK_OMod, 8 /* 3 */ },
25803 : { Feature_isVI|Feature_isSICI, 11543 /* v_sin_f16 */, MCK_Clamp, 4 /* 2 */ },
25804 : { Feature_isVI|Feature_isSICI, 11543 /* v_sin_f16 */, MCK_OMod, 8 /* 3 */ },
25805 : { Feature_isVI|Feature_isVI, 11543 /* v_sin_f16 */, MCK_Clamp, 4 /* 2 */ },
25806 : { Feature_isVI|Feature_isVI, 11543 /* v_sin_f16 */, MCK_OMod, 8 /* 3 */ },
25807 : { Feature_isGCN|Feature_isSICI, 11553 /* v_sin_f32 */, MCK_Clamp, 4 /* 2 */ },
25808 : { Feature_isGCN|Feature_isSICI, 11553 /* v_sin_f32 */, MCK_OMod, 8 /* 3 */ },
25809 : { Feature_isGCN|Feature_isVI, 11553 /* v_sin_f32 */, MCK_Clamp, 4 /* 2 */ },
25810 : { Feature_isGCN|Feature_isVI, 11553 /* v_sin_f32 */, MCK_OMod, 8 /* 3 */ },
25811 : { Feature_isVI|Feature_isSICI, 11563 /* v_sqrt_f16 */, MCK_Clamp, 4 /* 2 */ },
25812 : { Feature_isVI|Feature_isSICI, 11563 /* v_sqrt_f16 */, MCK_OMod, 8 /* 3 */ },
25813 : { Feature_isVI|Feature_isVI, 11563 /* v_sqrt_f16 */, MCK_Clamp, 4 /* 2 */ },
25814 : { Feature_isVI|Feature_isVI, 11563 /* v_sqrt_f16 */, MCK_OMod, 8 /* 3 */ },
25815 : { Feature_isGCN|Feature_isSICI, 11574 /* v_sqrt_f32 */, MCK_Clamp, 4 /* 2 */ },
25816 : { Feature_isGCN|Feature_isSICI, 11574 /* v_sqrt_f32 */, MCK_OMod, 8 /* 3 */ },
25817 : { Feature_isGCN|Feature_isVI, 11574 /* v_sqrt_f32 */, MCK_Clamp, 4 /* 2 */ },
25818 : { Feature_isGCN|Feature_isVI, 11574 /* v_sqrt_f32 */, MCK_OMod, 8 /* 3 */ },
25819 : { Feature_isGCN|Feature_isSICI, 11585 /* v_sqrt_f64 */, MCK_Clamp, 4 /* 2 */ },
25820 : { Feature_isGCN|Feature_isSICI, 11585 /* v_sqrt_f64 */, MCK_OMod, 8 /* 3 */ },
25821 : { Feature_isGCN|Feature_isVI, 11585 /* v_sqrt_f64 */, MCK_Clamp, 4 /* 2 */ },
25822 : { Feature_isGCN|Feature_isVI, 11585 /* v_sqrt_f64 */, MCK_OMod, 8 /* 3 */ },
25823 : { Feature_isVI|Feature_isSICI, 11596 /* v_sub_f16 */, MCK_Clamp, 8 /* 3 */ },
25824 : { Feature_isVI|Feature_isSICI, 11596 /* v_sub_f16 */, MCK_OMod, 16 /* 4 */ },
25825 : { Feature_isVI|Feature_isVI, 11596 /* v_sub_f16 */, MCK_Clamp, 8 /* 3 */ },
25826 : { Feature_isVI|Feature_isVI, 11596 /* v_sub_f16 */, MCK_OMod, 16 /* 4 */ },
25827 : { Feature_isGCN|Feature_isSICI, 11606 /* v_sub_f32 */, MCK_Clamp, 8 /* 3 */ },
25828 : { Feature_isGCN|Feature_isSICI, 11606 /* v_sub_f32 */, MCK_OMod, 16 /* 4 */ },
25829 : { Feature_isGCN|Feature_isVI, 11606 /* v_sub_f32 */, MCK_Clamp, 8 /* 3 */ },
25830 : { Feature_isGCN|Feature_isVI, 11606 /* v_sub_f32 */, MCK_OMod, 16 /* 4 */ },
25831 : { Feature_isVI|Feature_isSICI, 11661 /* v_subrev_f16 */, MCK_Clamp, 8 /* 3 */ },
25832 : { Feature_isVI|Feature_isSICI, 11661 /* v_subrev_f16 */, MCK_OMod, 16 /* 4 */ },
25833 : { Feature_isVI|Feature_isVI, 11661 /* v_subrev_f16 */, MCK_Clamp, 8 /* 3 */ },
25834 : { Feature_isVI|Feature_isVI, 11661 /* v_subrev_f16 */, MCK_OMod, 16 /* 4 */ },
25835 : { Feature_isGCN|Feature_isSICI, 11674 /* v_subrev_f32 */, MCK_Clamp, 8 /* 3 */ },
25836 : { Feature_isGCN|Feature_isSICI, 11674 /* v_subrev_f32 */, MCK_OMod, 16 /* 4 */ },
25837 : { Feature_isGCN|Feature_isVI, 11674 /* v_subrev_f32 */, MCK_Clamp, 8 /* 3 */ },
25838 : { Feature_isGCN|Feature_isVI, 11674 /* v_subrev_f32 */, MCK_OMod, 16 /* 4 */ },
25839 : { Feature_isGCN|Feature_isSICI, 11713 /* v_trig_preop_f64 */, MCK_Clamp, 8 /* 3 */ },
25840 : { Feature_isGCN|Feature_isSICI, 11713 /* v_trig_preop_f64 */, MCK_OMod, 16 /* 4 */ },
25841 : { Feature_isGCN|Feature_isVI, 11713 /* v_trig_preop_f64 */, MCK_Clamp, 8 /* 3 */ },
25842 : { Feature_isGCN|Feature_isVI, 11713 /* v_trig_preop_f64 */, MCK_OMod, 16 /* 4 */ },
25843 : { Feature_isVI|Feature_isSICI, 11730 /* v_trunc_f16 */, MCK_Clamp, 4 /* 2 */ },
25844 : { Feature_isVI|Feature_isSICI, 11730 /* v_trunc_f16 */, MCK_OMod, 8 /* 3 */ },
25845 : { Feature_isVI|Feature_isVI, 11730 /* v_trunc_f16 */, MCK_Clamp, 4 /* 2 */ },
25846 : { Feature_isVI|Feature_isVI, 11730 /* v_trunc_f16 */, MCK_OMod, 8 /* 3 */ },
25847 : { Feature_isGCN|Feature_isSICI, 11742 /* v_trunc_f32 */, MCK_Clamp, 4 /* 2 */ },
25848 : { Feature_isGCN|Feature_isSICI, 11742 /* v_trunc_f32 */, MCK_OMod, 8 /* 3 */ },
25849 : { Feature_isGCN|Feature_isVI, 11742 /* v_trunc_f32 */, MCK_Clamp, 4 /* 2 */ },
25850 : { Feature_isGCN|Feature_isVI, 11742 /* v_trunc_f32 */, MCK_OMod, 8 /* 3 */ },
25851 : { Feature_isCIVI|Feature_isSICI, 11754 /* v_trunc_f64 */, MCK_Clamp, 4 /* 2 */ },
25852 : { Feature_isCIVI|Feature_isSICI, 11754 /* v_trunc_f64 */, MCK_OMod, 8 /* 3 */ },
25853 : { Feature_isCIVI|Feature_isVI, 11754 /* v_trunc_f64 */, MCK_Clamp, 4 /* 2 */ },
25854 : { Feature_isCIVI|Feature_isVI, 11754 /* v_trunc_f64 */, MCK_OMod, 8 /* 3 */ },
25855 : };
25856 :
25857 3484 : AMDGPUAsmParser::OperandMatchResultTy AMDGPUAsmParser::
25858 : tryCustomParseOperand(OperandVector &Operands,
25859 : unsigned MCK) {
25860 :
25861 3484 : switch(MCK) {
25862 : case MCK_Clamp:
25863 526 : return parseVOP3OptionalOps(Operands);
25864 : case MCK_DSOffset1:
25865 76 : return parseDSOff01OptionalOps(Operands);
25866 : case MCK_DSOffsetparseDSOffsetOptional:
25867 2 : return parseDSOffsetOptional(Operands);
25868 : case MCK_DSOffsetparseDSOptionalOps:
25869 178 : return parseDSOptionalOps(Operands);
25870 : case MCK_GDSparseDSOff01OptionalOps:
25871 40 : return parseDSOff01OptionalOps(Operands);
25872 : case MCK_GDSparseDSOptionalOps:
25873 178 : return parseDSOptionalOps(Operands);
25874 : case MCK_GLC:
25875 540 : return parseMubufOptionalOps(Operands);
25876 : case MCK_MubufOffset:
25877 488 : return parseMubufOptionalOps(Operands);
25878 : case MCK_OMod:
25879 58 : return parseVOP3OptionalOps(Operands);
25880 : case MCK_SLC:
25881 720 : return parseMubufOptionalOps(Operands);
25882 : case MCK_SWaitCnt:
25883 16 : return parseSWaitCntOps(Operands);
25884 : case MCK_SoppBrTarget:
25885 14 : return parseSOppBrTarget(Operands);
25886 : case MCK_TFE:
25887 648 : return parseMubufOptionalOps(Operands);
25888 : default:
25889 : return MatchOperand_NoMatch;
25890 : }
25891 : return MatchOperand_NoMatch;
25892 : }
25893 :
25894 9654 : AMDGPUAsmParser::OperandMatchResultTy AMDGPUAsmParser::
25895 : MatchOperandParserImpl(OperandVector &Operands,
25896 : StringRef Mnemonic) {
25897 : // Get the current feature set.
25898 9654 : uint64_t AvailableFeatures = getAvailableFeatures();
25899 :
25900 : // Get the next operand index.
25901 19308 : unsigned NextOpNum = Operands.size()-1;
25902 : // Search the table.
25903 : std::pair<const OperandMatchEntry*, const OperandMatchEntry*> MnemonicRange =
25904 : std::equal_range(OperandMatchTable, OperandMatchTable+2348, Mnemonic,
25905 9654 : LessOpcodeOperand());
25906 :
25907 9654 : if (MnemonicRange.first == MnemonicRange.second)
25908 : return MatchOperand_NoMatch;
25909 :
25910 60562 : for (const OperandMatchEntry *it = MnemonicRange.first,
25911 : *ie = MnemonicRange.second; it != ie; ++it) {
25912 : // equal_range guarantees that instruction mnemonic matches.
25913 : assert(Mnemonic == it->getMnemonic());
25914 :
25915 : // check if the available features match
25916 61966 : if ((AvailableFeatures & it->RequiredFeatures) != it->RequiredFeatures) {
25917 : continue;
25918 : }
25919 :
25920 : // check if the operand in question has a custom parser.
25921 56574 : if (!(it->OperandMask & (1 << NextOpNum)))
25922 : continue;
25923 :
25924 : // call custom parse method to handle the operand
25925 3484 : OperandMatchResultTy Result = tryCustomParseOperand(Operands, it->Class);
25926 3484 : if (Result != MatchOperand_NoMatch)
25927 1404 : return Result;
25928 : }
25929 :
25930 : // Okay, we had no match.
25931 : return MatchOperand_NoMatch;
25932 : }
25933 :
25934 : #endif // GET_MATCHER_IMPLEMENTATION
25935 :
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