Line data Source code
1 : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2 : |* *|
3 : |* Calling Convention Implementation Fragment *|
4 : |* *|
5 : |* Automatically generated file, do not edit! *|
6 : |* *|
7 : \*===----------------------------------------------------------------------===*/
8 :
9 : static bool CC_AMDGPU(unsigned ValNo, MVT ValVT,
10 : MVT LocVT, CCValAssign::LocInfo LocInfo,
11 : ISD::ArgFlagsTy ArgFlags, CCState &State);
12 : static bool CC_AMDGPU_Kernel(unsigned ValNo, MVT ValVT,
13 : MVT LocVT, CCValAssign::LocInfo LocInfo,
14 : ISD::ArgFlagsTy ArgFlags, CCState &State);
15 : static bool CC_R600(unsigned ValNo, MVT ValVT,
16 : MVT LocVT, CCValAssign::LocInfo LocInfo,
17 : ISD::ArgFlagsTy ArgFlags, CCState &State);
18 : static bool CC_SI(unsigned ValNo, MVT ValVT,
19 : MVT LocVT, CCValAssign::LocInfo LocInfo,
20 : ISD::ArgFlagsTy ArgFlags, CCState &State);
21 :
22 :
23 13833 : static bool CC_AMDGPU(unsigned ValNo, MVT ValVT,
24 : MVT LocVT, CCValAssign::LocInfo LocInfo,
25 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
26 :
27 24984 : if (static_cast<const AMDGPUSubtarget&>(State.getMachineFunction().getSubtarget()).getGeneration() >=AMDGPUSubtarget::SOUTHERN_ISLANDS && State.getMachineFunction().getInfo<SIMachineFunctionInfo>()->getShaderType() == ShaderType::COMPUTE) {
28 10806 : if (!CC_AMDGPU_Kernel(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
29 : return false;
30 : }
31 :
32 5709 : if (static_cast<const AMDGPUSubtarget&>(State.getMachineFunction().getSubtarget()).getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && State.getMachineFunction().getInfo<R600MachineFunctionInfo>()->getShaderType() == ShaderType::COMPUTE) {
33 2617 : if (!CC_AMDGPU_Kernel(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
34 : return false;
35 : }
36 :
37 410 : if (static_cast<const AMDGPUSubtarget&>(State.getMachineFunction().getSubtarget()).getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
38 345 : if (!CC_SI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
39 : return false;
40 : }
41 :
42 65 : if (static_cast<const AMDGPUSubtarget&>(State.getMachineFunction().getSubtarget()).getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
43 65 : if (!CC_R600(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
44 : return false;
45 : }
46 :
47 : return true; // CC didn't match.
48 : }
49 :
50 :
51 : static bool CC_AMDGPU_Kernel(unsigned ValNo, MVT ValVT,
52 : MVT LocVT, CCValAssign::LocInfo LocInfo,
53 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
54 :
55 13423 : if (allocateStack(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
56 : return false;
57 :
58 : return true; // CC didn't match.
59 : }
60 :
61 :
62 65 : static bool CC_R600(unsigned ValNo, MVT ValVT,
63 : MVT LocVT, CCValAssign::LocInfo LocInfo,
64 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
65 :
66 65 : if (ArgFlags.isInReg()) {
67 65 : if (LocVT == MVT::v4f32 ||
68 : LocVT == MVT::v4i32) {
69 : static const MCPhysReg RegList1[] = {
70 : AMDGPU::T0_XYZW, AMDGPU::T1_XYZW, AMDGPU::T2_XYZW, AMDGPU::T3_XYZW, AMDGPU::T4_XYZW, AMDGPU::T5_XYZW, AMDGPU::T6_XYZW, AMDGPU::T7_XYZW, AMDGPU::T8_XYZW, AMDGPU::T9_XYZW, AMDGPU::T10_XYZW, AMDGPU::T11_XYZW, AMDGPU::T12_XYZW, AMDGPU::T13_XYZW, AMDGPU::T14_XYZW, AMDGPU::T15_XYZW, AMDGPU::T16_XYZW, AMDGPU::T17_XYZW, AMDGPU::T18_XYZW, AMDGPU::T19_XYZW, AMDGPU::T20_XYZW, AMDGPU::T21_XYZW, AMDGPU::T22_XYZW, AMDGPU::T23_XYZW, AMDGPU::T24_XYZW, AMDGPU::T25_XYZW, AMDGPU::T26_XYZW, AMDGPU::T27_XYZW, AMDGPU::T28_XYZW, AMDGPU::T29_XYZW, AMDGPU::T30_XYZW, AMDGPU::T31_XYZW, AMDGPU::T32_XYZW
71 : };
72 65 : if (unsigned Reg = State.AllocateReg(RegList1)) {
73 130 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
74 65 : return false;
75 : }
76 : }
77 : }
78 :
79 : return true; // CC didn't match.
80 : }
81 :
82 :
83 345 : static bool CC_SI(unsigned ValNo, MVT ValVT,
84 : MVT LocVT, CCValAssign::LocInfo LocInfo,
85 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
86 :
87 345 : if (ArgFlags.isInReg()) {
88 148 : if (LocVT == MVT::f32 ||
89 : LocVT == MVT::i32) {
90 : static const MCPhysReg RegList1[] = {
91 : AMDGPU::SGPR0, AMDGPU::SGPR1, AMDGPU::SGPR2, AMDGPU::SGPR3, AMDGPU::SGPR4, AMDGPU::SGPR5, AMDGPU::SGPR6, AMDGPU::SGPR7, AMDGPU::SGPR8, AMDGPU::SGPR9, AMDGPU::SGPR10, AMDGPU::SGPR11, AMDGPU::SGPR12, AMDGPU::SGPR13, AMDGPU::SGPR14, AMDGPU::SGPR15, AMDGPU::SGPR16, AMDGPU::SGPR17, AMDGPU::SGPR18, AMDGPU::SGPR19, AMDGPU::SGPR20, AMDGPU::SGPR21
92 : };
93 61 : if (unsigned Reg = State.AllocateReg(RegList1)) {
94 122 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
95 61 : return false;
96 : }
97 : }
98 : }
99 :
100 284 : if (ArgFlags.isInReg()) {
101 87 : if (LocVT == MVT::i64) {
102 : static const MCPhysReg RegList2[] = {
103 : AMDGPU::SGPR0, AMDGPU::SGPR2, AMDGPU::SGPR4, AMDGPU::SGPR6, AMDGPU::SGPR8, AMDGPU::SGPR10, AMDGPU::SGPR12, AMDGPU::SGPR14
104 : };
105 : static const MCPhysReg RegList3[] = {
106 : AMDGPU::SGPR1, AMDGPU::SGPR3, AMDGPU::SGPR5, AMDGPU::SGPR7, AMDGPU::SGPR9, AMDGPU::SGPR11, AMDGPU::SGPR13, AMDGPU::SGPR15
107 : };
108 87 : if (unsigned Reg = State.AllocateReg(RegList2, RegList3)) {
109 174 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
110 87 : return false;
111 : }
112 : }
113 : }
114 :
115 197 : if (!ArgFlags.isInReg()) {
116 197 : if (LocVT == MVT::f32 ||
117 : LocVT == MVT::i32) {
118 : static const MCPhysReg RegList4[] = {
119 : AMDGPU::VGPR0, AMDGPU::VGPR1, AMDGPU::VGPR2, AMDGPU::VGPR3, AMDGPU::VGPR4, AMDGPU::VGPR5, AMDGPU::VGPR6, AMDGPU::VGPR7, AMDGPU::VGPR8, AMDGPU::VGPR9, AMDGPU::VGPR10, AMDGPU::VGPR11, AMDGPU::VGPR12, AMDGPU::VGPR13, AMDGPU::VGPR14, AMDGPU::VGPR15, AMDGPU::VGPR16, AMDGPU::VGPR17, AMDGPU::VGPR18, AMDGPU::VGPR19, AMDGPU::VGPR20, AMDGPU::VGPR21, AMDGPU::VGPR22, AMDGPU::VGPR23, AMDGPU::VGPR24, AMDGPU::VGPR25, AMDGPU::VGPR26, AMDGPU::VGPR27, AMDGPU::VGPR28, AMDGPU::VGPR29, AMDGPU::VGPR30, AMDGPU::VGPR31
120 : };
121 129 : if (unsigned Reg = State.AllocateReg(RegList4)) {
122 258 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
123 129 : return false;
124 : }
125 : }
126 : }
127 :
128 68 : if (ArgFlags.isByVal()) {
129 68 : if (LocVT == MVT::i64) {
130 : static const MCPhysReg RegList5[] = {
131 : AMDGPU::SGPR0, AMDGPU::SGPR2, AMDGPU::SGPR4, AMDGPU::SGPR6, AMDGPU::SGPR8, AMDGPU::SGPR10, AMDGPU::SGPR12, AMDGPU::SGPR14
132 : };
133 : static const MCPhysReg RegList6[] = {
134 : AMDGPU::SGPR1, AMDGPU::SGPR3, AMDGPU::SGPR5, AMDGPU::SGPR7, AMDGPU::SGPR9, AMDGPU::SGPR11, AMDGPU::SGPR13, AMDGPU::SGPR15
135 : };
136 68 : if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) {
137 136 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
138 68 : return false;
139 : }
140 : }
141 : }
142 :
143 : return true; // CC didn't match.
144 : }
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